Project import
diff --git a/libc/Android.bp b/libc/Android.bp new file mode 100644 index 0000000..af3ba2b --- /dev/null +++ b/libc/Android.bp
@@ -0,0 +1,1994 @@ +// Define the common source files for all the libc instances +// ========================================================= +libc_common_src_files = [ + "bionic/ether_aton.c", + "bionic/ether_ntoa.c", + "bionic/fts.c", + "bionic/getpriority.c", + "bionic/initgroups.c", + "bionic/isatty.c", + "bionic/pututline.c", + "bionic/sched_cpualloc.c", + "bionic/sched_cpucount.c", + "bionic/sigblock.c", + "bionic/siginterrupt.c", + "bionic/sigsetmask.c", + "bionic/system_properties_compat.c", + "stdio/fread.c", + "stdio/refill.c", + "stdio/stdio.cpp", + "stdio/stdio_ext.cpp", + "stdlib/atexit.c", + "stdlib/exit.c", +] + +// Various kinds of cruft. +// ======================================================== +libc_common_src_files += [ + "bionic/ndk_cruft.cpp", +] + +libc_common_src_files_32 = [ + "bionic/legacy_32_bit_support.cpp", + "bionic/time64.c", +] + +libc_common_flags = [ + "-D_LIBC=1", + "-Wall", + "-Wextra", + "-Wunused", + "-Wno-deprecated-declarations", + "-Wframe-larger-than=2048", + + // Try to catch typical 32-bit assumptions that break with 64-bit pointers. + "-Werror=pointer-to-int-cast", + "-Werror=int-to-pointer-cast", + "-Werror=type-limits", + "-Werror", +] + +// Define some common cflags +// ======================================================== +cc_defaults { + name: "libc_defaults", + cflags: libc_common_flags, + asflags: libc_common_flags, + conlyflags: ["-std=gnu99"], + cppflags: [], + include_dirs: ["external/jemalloc/include"], + + stl: "none", + system_shared_libs: [], + sanitize: { + never: true, + }, + native_coverage: false, + clang: true, +} + +// ANDROIDMK TRANSLATION ERROR: unsupported directive +// ifeq ($(strip $(DEBUG_BIONIC_LIBC)),true) +//libc_common_cflags += ["-DDEBUG"] +// ANDROIDMK TRANSLATION ERROR: unsupported directive +// endif + +// ======================================================== +// libc_stack_protector.a - stack protector code +// ======================================================== +// +// Code that implements the stack protector (or that runs +// before TLS has been set up) needs to be compiled with +// -fno-stack-protector, since it accesses the stack canary +// TLS slot. + +cc_library_static { + + srcs: [ + "bionic/__libc_init_main_thread.cpp", + "bionic/__stack_chk_fail.cpp", + ], + arch: { + arm64: { + srcs: ["arch-arm64/bionic/__set_tls.c"], + }, + x86: { + srcs: ["arch-x86/bionic/__set_tls.cpp"], + }, + x86_64: { + srcs: ["arch-x86_64/bionic/__set_tls.c"], + }, + }, + + defaults: ["libc_defaults"], + cflags: ["-fno-stack-protector"], + name: "libc_stack_protector", +} + +// libc_init_static.cpp also needs to be built without stack protector, +// because it's responsible for setting up TLS for static executables. +// This isn't the case for dynamic executables because the dynamic linker +// has already set up the main thread's TLS. + +cc_library_static { + name: "libc_init_static", + defaults: ["libc_defaults"], + srcs: ["bionic/libc_init_static.cpp"], + cflags: ["-fno-stack-protector"], +} + + +// ======================================================== +// libc_tzcode.a - upstream 'tzcode' code +// ======================================================== + +cc_library_static { + + defaults: ["libc_defaults"], + srcs: [ + "tzcode/**/*.c", + "upstream-openbsd/lib/libc/time/wcsftime.c", // tzcode doesn't include wcsftime, so we use the OpenBSD one. + ], + + cflags: [ + "-Wno-unused-parameter", + // Don't use ridiculous amounts of stack. + "-DALL_STATE", + // Include tzsetwall, timelocal, timegm, time2posix, and posix2time. + "-DSTD_INSPIRED", + // Obviously, we want to be thread-safe. + "-DTHREAD_SAFE", + // The name of the tm_gmtoff field in our struct tm. + "-DTM_GMTOFF=tm_gmtoff", + // Where we store our tzdata. + "-DTZDIR=\\\"/system/usr/share/zoneinfo\\\"", + // Include `tzname`, `timezone`, and `daylight` globals. + "-DHAVE_POSIX_DECLS=0", + "-DUSG_COMPAT=1", + // Use the empty string (instead of " ") as the timezone abbreviation + // fallback. + "-DWILDABBR=\\\"\\\"", + "-DNO_RUN_TIME_WARNINGS_ABOUT_YEAR_2000_PROBLEMS_THANK_YOU", + "-Dlint", + ], + + local_include_dirs: ["tzcode/"], + name: "libc_tzcode", +} + +// ======================================================== +// libc_dns.a - modified NetBSD DNS code +// ======================================================== + +cc_library_static { + + defaults: ["libc_defaults"], + srcs: [ + "dns/**/*.c", + + "upstream-netbsd/lib/libc/isc/ev_streams.c", + "upstream-netbsd/lib/libc/isc/ev_timers.c", + "upstream-netbsd/lib/libc/resolv/mtctxres.c", + ], + + cflags: [ + "-DANDROID_CHANGES", + "-DINET6", + "-Wno-unused-parameter", + "-include netbsd-compat.h", + "-Wframe-larger-than=66000", + ], + + local_include_dirs: [ + "dns/include", + "private", + "upstream-netbsd/lib/libc/include", + "upstream-netbsd/android/include", + ], + + name: "libc_dns", +} + +// ======================================================== +// libc_freebsd.a - upstream FreeBSD C library code +// ======================================================== +// +// These files are built with the freebsd-compat.h header file +// automatically included. + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "upstream-freebsd/lib/libc/gen/ldexp.c", + "upstream-freebsd/lib/libc/gen/sleep.c", + "upstream-freebsd/lib/libc/gen/usleep.c", + "upstream-freebsd/lib/libc/stdlib/getopt_long.c", + "upstream-freebsd/lib/libc/stdlib/qsort.c", + "upstream-freebsd/lib/libc/stdlib/quick_exit.c", + "upstream-freebsd/lib/libc/string/wcpcpy.c", + "upstream-freebsd/lib/libc/string/wcpncpy.c", + "upstream-freebsd/lib/libc/string/wcscasecmp.c", + "upstream-freebsd/lib/libc/string/wcscat.c", + "upstream-freebsd/lib/libc/string/wcschr.c", + "upstream-freebsd/lib/libc/string/wcscmp.c", + "upstream-freebsd/lib/libc/string/wcscpy.c", + "upstream-freebsd/lib/libc/string/wcscspn.c", + "upstream-freebsd/lib/libc/string/wcsdup.c", + "upstream-freebsd/lib/libc/string/wcslcat.c", + "upstream-freebsd/lib/libc/string/wcslen.c", + "upstream-freebsd/lib/libc/string/wcsncasecmp.c", + "upstream-freebsd/lib/libc/string/wcsncat.c", + "upstream-freebsd/lib/libc/string/wcsncmp.c", + "upstream-freebsd/lib/libc/string/wcsncpy.c", + "upstream-freebsd/lib/libc/string/wcsnlen.c", + "upstream-freebsd/lib/libc/string/wcspbrk.c", + "upstream-freebsd/lib/libc/string/wcsrchr.c", + "upstream-freebsd/lib/libc/string/wcsspn.c", + "upstream-freebsd/lib/libc/string/wcstok.c", + "upstream-freebsd/lib/libc/string/wmemchr.c", + "upstream-freebsd/lib/libc/string/wmemcmp.c", + "upstream-freebsd/lib/libc/string/wmemmove.c", + "upstream-freebsd/lib/libc/string/wmemset.c", + ], + arch: { + arm64: { + exclude_srcs: [ + "upstream-freebsd/lib/libc/string/wmemmove.c", + ], + }, + x86: { + exclude_srcs: [ + "upstream-freebsd/lib/libc/string/wcschr.c", + "upstream-freebsd/lib/libc/string/wcscmp.c", + "upstream-freebsd/lib/libc/string/wcslen.c", + "upstream-freebsd/lib/libc/string/wcsrchr.c", + ], + atom: { + exclude_srcs: [ + "upstream-freebsd/lib/libc/string/wmemcmp.c", + ], + }, + ssse3: { + exclude_srcs: [ + "upstream-freebsd/lib/libc/string/wcscat.c", + "upstream-freebsd/lib/libc/string/wcscpy.c", + ], + }, + sse4: { + exclude_srcs: [ + "upstream-freebsd/lib/libc/string/wmemcmp.c", + ], + }, + }, + }, + + cflags: [ + "-Wno-sign-compare", + "-Wno-uninitialized", + "-include freebsd-compat.h", + ], + + local_include_dirs: [ + "upstream-freebsd/android/include", + ], + + name: "libc_freebsd", +} + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "upstream-freebsd/lib/libc/stdlib/realpath.c", + ], + + cflags: [ + "-Wno-sign-compare", + "-include freebsd-compat.h", + "-Wframe-larger-than=15000", + ], + + local_include_dirs: [ + "upstream-freebsd/android/include", + ], + + name: "libc_freebsd_large_stack", +} + +// ======================================================== +// libc_netbsd.a - upstream NetBSD C library code +// ======================================================== +// +// These files are built with the netbsd-compat.h header file +// automatically included. + +cc_library_static { + + defaults: ["libc_defaults"], + srcs: [ + "upstream-netbsd/common/lib/libc/stdlib/random.c", + "upstream-netbsd/lib/libc/gen/nice.c", + "upstream-netbsd/lib/libc/gen/popen.c", + "upstream-netbsd/lib/libc/gen/psignal.c", + "upstream-netbsd/lib/libc/gen/utime.c", + "upstream-netbsd/lib/libc/gen/utmp.c", + "upstream-netbsd/lib/libc/inet/nsap_addr.c", + "upstream-netbsd/lib/libc/regex/regcomp.c", + "upstream-netbsd/lib/libc/regex/regerror.c", + "upstream-netbsd/lib/libc/regex/regexec.c", + "upstream-netbsd/lib/libc/regex/regfree.c", + "upstream-netbsd/lib/libc/stdlib/bsearch.c", + "upstream-netbsd/lib/libc/stdlib/div.c", + "upstream-netbsd/lib/libc/stdlib/drand48.c", + "upstream-netbsd/lib/libc/stdlib/erand48.c", + "upstream-netbsd/lib/libc/stdlib/jrand48.c", + "upstream-netbsd/lib/libc/stdlib/lcong48.c", + "upstream-netbsd/lib/libc/stdlib/ldiv.c", + "upstream-netbsd/lib/libc/stdlib/lldiv.c", + "upstream-netbsd/lib/libc/stdlib/lrand48.c", + "upstream-netbsd/lib/libc/stdlib/mrand48.c", + "upstream-netbsd/lib/libc/stdlib/nrand48.c", + "upstream-netbsd/lib/libc/stdlib/_rand48.c", + "upstream-netbsd/lib/libc/stdlib/rand_r.c", + "upstream-netbsd/lib/libc/stdlib/reallocarr.c", + "upstream-netbsd/lib/libc/stdlib/seed48.c", + "upstream-netbsd/lib/libc/stdlib/srand48.c", + "upstream-netbsd/lib/libc/string/memccpy.c", + "upstream-netbsd/lib/libc/string/strcasestr.c", + "upstream-netbsd/lib/libc/string/strcoll.c", + "upstream-netbsd/lib/libc/string/strxfrm.c", + ], + multilib: { + lib32: { + // LP32 cruft + srcs: ["upstream-netbsd/common/lib/libc/hash/sha1/sha1.c"], + }, + }, + cflags: [ + "-Wno-sign-compare", + "-Wno-uninitialized", + "-Wno-unused-parameter", + "-DPOSIX_MISTAKE", + "-include netbsd-compat.h", + ], + + local_include_dirs: [ + "upstream-netbsd/android/include", + "upstream-netbsd/lib/libc/include", + ], + + name: "libc_netbsd", +} + +// ======================================================== +// libc_openbsd_ndk.a - upstream OpenBSD C library code +// that can be safely included in the libc_ndk.a (doesn't +// contain any troublesome global data or constructors). +// ======================================================== +// +// These files are built with the openbsd-compat.h header file +// automatically included. + +cc_library_static { + name: "libc_openbsd_ndk", + defaults: ["libc_defaults"], + srcs: [ + "upstream-openbsd/lib/libc/compat-43/killpg.c", + "upstream-openbsd/lib/libc/gen/alarm.c", + "upstream-openbsd/lib/libc/gen/ctype_.c", + "upstream-openbsd/lib/libc/gen/daemon.c", + "upstream-openbsd/lib/libc/gen/err.c", + "upstream-openbsd/lib/libc/gen/errx.c", + "upstream-openbsd/lib/libc/gen/fnmatch.c", + "upstream-openbsd/lib/libc/gen/ftok.c", + "upstream-openbsd/lib/libc/gen/getprogname.c", + "upstream-openbsd/lib/libc/gen/isctype.c", + "upstream-openbsd/lib/libc/gen/setprogname.c", + "upstream-openbsd/lib/libc/gen/time.c", + "upstream-openbsd/lib/libc/gen/tolower_.c", + "upstream-openbsd/lib/libc/gen/toupper_.c", + "upstream-openbsd/lib/libc/gen/verr.c", + "upstream-openbsd/lib/libc/gen/verrx.c", + "upstream-openbsd/lib/libc/gen/vwarn.c", + "upstream-openbsd/lib/libc/gen/vwarnx.c", + "upstream-openbsd/lib/libc/gen/warn.c", + "upstream-openbsd/lib/libc/gen/warnx.c", + "upstream-openbsd/lib/libc/locale/btowc.c", + "upstream-openbsd/lib/libc/locale/mbrlen.c", + "upstream-openbsd/lib/libc/locale/mbstowcs.c", + "upstream-openbsd/lib/libc/locale/mbtowc.c", + "upstream-openbsd/lib/libc/locale/wcscoll.c", + "upstream-openbsd/lib/libc/locale/wcstod.c", + "upstream-openbsd/lib/libc/locale/wcstof.c", + "upstream-openbsd/lib/libc/locale/wcstoimax.c", + "upstream-openbsd/lib/libc/locale/wcstol.c", + "upstream-openbsd/lib/libc/locale/wcstold.c", + "upstream-openbsd/lib/libc/locale/wcstoll.c", + "upstream-openbsd/lib/libc/locale/wcstombs.c", + "upstream-openbsd/lib/libc/locale/wcstoul.c", + "upstream-openbsd/lib/libc/locale/wcstoull.c", + "upstream-openbsd/lib/libc/locale/wcstoumax.c", + "upstream-openbsd/lib/libc/locale/wcsxfrm.c", + "upstream-openbsd/lib/libc/locale/wctob.c", + "upstream-openbsd/lib/libc/locale/wctomb.c", + "upstream-openbsd/lib/libc/net/base64.c", + "upstream-openbsd/lib/libc/net/htonl.c", + "upstream-openbsd/lib/libc/net/htons.c", + "upstream-openbsd/lib/libc/net/inet_lnaof.c", + "upstream-openbsd/lib/libc/net/inet_makeaddr.c", + "upstream-openbsd/lib/libc/net/inet_netof.c", + "upstream-openbsd/lib/libc/net/inet_ntoa.c", + "upstream-openbsd/lib/libc/net/inet_ntop.c", + "upstream-openbsd/lib/libc/net/inet_pton.c", + "upstream-openbsd/lib/libc/net/ntohl.c", + "upstream-openbsd/lib/libc/net/ntohs.c", + "upstream-openbsd/lib/libc/net/res_random.c", + "upstream-openbsd/lib/libc/stdio/fflush.c", + "upstream-openbsd/lib/libc/stdio/fgetln.c", + "upstream-openbsd/lib/libc/stdio/fgets.c", + "upstream-openbsd/lib/libc/stdio/fgetwc.c", + "upstream-openbsd/lib/libc/stdio/fgetws.c", + "upstream-openbsd/lib/libc/stdio/flags.c", + "upstream-openbsd/lib/libc/stdio/fmemopen.c", + "upstream-openbsd/lib/libc/stdio/fpurge.c", + "upstream-openbsd/lib/libc/stdio/fputs.c", + "upstream-openbsd/lib/libc/stdio/fputwc.c", + "upstream-openbsd/lib/libc/stdio/fputws.c", + "upstream-openbsd/lib/libc/stdio/fvwrite.c", + "upstream-openbsd/lib/libc/stdio/fwalk.c", + "upstream-openbsd/lib/libc/stdio/fwide.c", + "upstream-openbsd/lib/libc/stdio/fwrite.c", + "upstream-openbsd/lib/libc/stdio/getdelim.c", + "upstream-openbsd/lib/libc/stdio/gets.c", + "upstream-openbsd/lib/libc/stdio/makebuf.c", + "upstream-openbsd/lib/libc/stdio/mktemp.c", + "upstream-openbsd/lib/libc/stdio/open_memstream.c", + "upstream-openbsd/lib/libc/stdio/open_wmemstream.c", + "upstream-openbsd/lib/libc/stdio/perror.c", + "upstream-openbsd/lib/libc/stdio/puts.c", + "upstream-openbsd/lib/libc/stdio/rget.c", + "upstream-openbsd/lib/libc/stdio/setvbuf.c", + "upstream-openbsd/lib/libc/stdio/tempnam.c", + "upstream-openbsd/lib/libc/stdio/tmpnam.c", + "upstream-openbsd/lib/libc/stdio/ungetc.c", + "upstream-openbsd/lib/libc/stdio/ungetwc.c", + "upstream-openbsd/lib/libc/stdio/vasprintf.c", + "upstream-openbsd/lib/libc/stdio/vdprintf.c", + "upstream-openbsd/lib/libc/stdio/vfscanf.c", + "upstream-openbsd/lib/libc/stdio/vsscanf.c", + "upstream-openbsd/lib/libc/stdio/vswprintf.c", + "upstream-openbsd/lib/libc/stdio/vswscanf.c", + "upstream-openbsd/lib/libc/stdio/wbuf.c", + "upstream-openbsd/lib/libc/stdio/wsetup.c", + "upstream-openbsd/lib/libc/stdlib/abs.c", + "upstream-openbsd/lib/libc/stdlib/atoi.c", + "upstream-openbsd/lib/libc/stdlib/atol.c", + "upstream-openbsd/lib/libc/stdlib/atoll.c", + "upstream-openbsd/lib/libc/stdlib/getenv.c", + "upstream-openbsd/lib/libc/stdlib/getsubopt.c", + "upstream-openbsd/lib/libc/stdlib/insque.c", + "upstream-openbsd/lib/libc/stdlib/imaxabs.c", + "upstream-openbsd/lib/libc/stdlib/imaxdiv.c", + "upstream-openbsd/lib/libc/stdlib/labs.c", + "upstream-openbsd/lib/libc/stdlib/llabs.c", + "upstream-openbsd/lib/libc/stdlib/lsearch.c", + "upstream-openbsd/lib/libc/stdlib/reallocarray.c", + "upstream-openbsd/lib/libc/stdlib/remque.c", + "upstream-openbsd/lib/libc/stdlib/setenv.c", + "upstream-openbsd/lib/libc/stdlib/strtoimax.c", + "upstream-openbsd/lib/libc/stdlib/strtol.c", + "upstream-openbsd/lib/libc/stdlib/strtoll.c", + "upstream-openbsd/lib/libc/stdlib/strtoul.c", + "upstream-openbsd/lib/libc/stdlib/strtoull.c", + "upstream-openbsd/lib/libc/stdlib/strtoumax.c", + "upstream-openbsd/lib/libc/stdlib/system.c", + "upstream-openbsd/lib/libc/stdlib/tfind.c", + "upstream-openbsd/lib/libc/stdlib/tsearch.c", + "upstream-openbsd/lib/libc/string/strcasecmp.c", + "upstream-openbsd/lib/libc/string/strcspn.c", + "upstream-openbsd/lib/libc/string/strdup.c", + "upstream-openbsd/lib/libc/string/strndup.c", + "upstream-openbsd/lib/libc/string/strpbrk.c", + "upstream-openbsd/lib/libc/string/strsep.c", + "upstream-openbsd/lib/libc/string/strspn.c", + "upstream-openbsd/lib/libc/string/strstr.c", + "upstream-openbsd/lib/libc/string/strtok.c", + "upstream-openbsd/lib/libc/string/wmemcpy.c", + "upstream-openbsd/lib/libc/string/wcslcpy.c", + "upstream-openbsd/lib/libc/string/wcsstr.c", + "upstream-openbsd/lib/libc/string/wcswidth.c", + ], + + cflags: [ + "-Wno-sign-compare", + "-Wno-uninitialized", + "-Wno-unused-parameter", + "-include openbsd-compat.h", + ], + + local_include_dirs: [ + "private", + "stdio", + "upstream-openbsd/android/include", + "upstream-openbsd/lib/libc/include", + "upstream-openbsd/lib/libc/gdtoa/", + ], +} + +cc_library_static { + name: "libc_openbsd_large_stack", + defaults: ["libc_defaults"], + srcs: [ + "upstream-openbsd/lib/libc/gen/exec.c", + "upstream-openbsd/lib/libc/stdio/vfprintf.c", + "upstream-openbsd/lib/libc/stdio/vfwprintf.c", + "upstream-openbsd/lib/libc/stdio/vfwscanf.c", + ], + cflags: [ + "-include openbsd-compat.h", + "-Wno-sign-compare", + "-Wframe-larger-than=5000", + ], + + local_include_dirs: [ + "stdio", + "upstream-openbsd/android/include", + "upstream-openbsd/lib/libc/include", + "upstream-openbsd/lib/libc/gdtoa/", + ], +} + +// ======================================================== +// libc_openbsd.a - upstream OpenBSD C library code +// ======================================================== +// +// These files are built with the openbsd-compat.h header file +// automatically included. +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + // These two depend on getentropy_linux.c, which isn't in libc_ndk.a. + "upstream-openbsd/lib/libc/crypt/arc4random.c", + "upstream-openbsd/lib/libc/crypt/arc4random_uniform.c", + + // May be overriden by per-arch optimized versions + "upstream-openbsd/lib/libc/string/memchr.c", + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/memrchr.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/stpncpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + "upstream-openbsd/lib/libc/string/strcpy.c", + "upstream-openbsd/lib/libc/string/strlcat.c", + "upstream-openbsd/lib/libc/string/strlcpy.c", + "upstream-openbsd/lib/libc/string/strncat.c", + "upstream-openbsd/lib/libc/string/strncmp.c", + "upstream-openbsd/lib/libc/string/strncpy.c", + ], + + arch: { + arm: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/strcpy.c", + ], + cortex_a7: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + cortex_a53: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + cortex_a53_a57: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + cortex_a8: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + cortex_a9: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + cortex_a15: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + denver: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + krait: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + ], + }, + }, + arm64: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memchr.c", + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/strcpy.c", + "upstream-openbsd/lib/libc/string/strncmp.c", + ], + }, + + x86: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memchr.c", + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/memrchr.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/stpncpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + "upstream-openbsd/lib/libc/string/strcpy.c", + "upstream-openbsd/lib/libc/string/strncmp.c", + "upstream-openbsd/lib/libc/string/strncpy.c", + ], + ssse3: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/strlcat.c", + "upstream-openbsd/lib/libc/string/strlcpy.c", + "upstream-openbsd/lib/libc/string/strncat.c", + ], + }, + }, + + x86_64: { + exclude_srcs: [ + "upstream-openbsd/lib/libc/string/memmove.c", + "upstream-openbsd/lib/libc/string/stpcpy.c", + "upstream-openbsd/lib/libc/string/stpncpy.c", + "upstream-openbsd/lib/libc/string/strcat.c", + "upstream-openbsd/lib/libc/string/strcpy.c", + "upstream-openbsd/lib/libc/string/strlcat.c", + "upstream-openbsd/lib/libc/string/strlcpy.c", + "upstream-openbsd/lib/libc/string/strncat.c", + "upstream-openbsd/lib/libc/string/strncmp.c", + "upstream-openbsd/lib/libc/string/strncpy.c", + ], + }, + }, + + cflags: [ + "-Wno-sign-compare", + "-Wno-uninitialized", + "-Wno-unused-parameter", + "-include openbsd-compat.h", + ], + + local_include_dirs: [ + "private", + "upstream-openbsd/android/include", + ], + + name: "libc_openbsd", +} + +// ======================================================== +// libc_gdtoa.a - upstream OpenBSD C library gdtoa code +// ======================================================== +// +// These files are built with the openbsd-compat.h header file +// automatically included. + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "upstream-openbsd/android/gdtoa_support.cpp", + "upstream-openbsd/lib/libc/gdtoa/dmisc.c", + "upstream-openbsd/lib/libc/gdtoa/dtoa.c", + "upstream-openbsd/lib/libc/gdtoa/gdtoa.c", + "upstream-openbsd/lib/libc/gdtoa/gethex.c", + "upstream-openbsd/lib/libc/gdtoa/gmisc.c", + "upstream-openbsd/lib/libc/gdtoa/hd_init.c", + "upstream-openbsd/lib/libc/gdtoa/hdtoa.c", + "upstream-openbsd/lib/libc/gdtoa/hexnan.c", + "upstream-openbsd/lib/libc/gdtoa/ldtoa.c", + "upstream-openbsd/lib/libc/gdtoa/misc.c", + "upstream-openbsd/lib/libc/gdtoa/smisc.c", + "upstream-openbsd/lib/libc/gdtoa/strtod.c", + "upstream-openbsd/lib/libc/gdtoa/strtodg.c", + "upstream-openbsd/lib/libc/gdtoa/strtof.c", + "upstream-openbsd/lib/libc/gdtoa/strtord.c", + "upstream-openbsd/lib/libc/gdtoa/sum.c", + "upstream-openbsd/lib/libc/gdtoa/ulp.c", + ], + multilib: { + lib64: { + srcs: ["upstream-openbsd/lib/libc/gdtoa/strtorQ.c"], + }, + }, + + cflags: [ + "-Wno-sign-compare", + "-Wno-uninitialized", + "-include openbsd-compat.h", + ], + + local_include_dirs: [ + "private", + "upstream-openbsd/android/include", + "upstream-openbsd/lib/libc/include", + ], + + name: "libc_gdtoa", +} + +// ======================================================== +// libc_bionic.a - home-grown C library code +// ======================================================== + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + // The following implementations depend on pthread data, so we can't + // include them in libc_ndk.a. + "bionic/__cxa_thread_atexit_impl.cpp", + "bionic/fork.cpp", + + // The data that backs getauxval is initialized in the libc init + // functions which are invoked by the linker. If this file is included + // in libc_ndk.a, only one of the copies of the global data will be + // initialized, resulting in nullptr dereferences. + "bionic/getauxval.cpp", + + // These four require getauxval, which isn't available on older + // platforms. + "bionic/getentropy_linux.c", + "bionic/sysconf.cpp", + "bionic/vdso.cpp", + "bionic/setjmp_cookie.cpp", + + "bionic/__memcpy_chk.cpp", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + "bionic/strchr.cpp", + "bionic/strnlen.c", + "bionic/strrchr.cpp", + ], + + arch: { + arm: { + srcs: [ + "arch-arm/generic/bionic/memcmp.S", + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + + "arch-arm/bionic/abort_arm.S", + "arch-arm/bionic/atomics_arm.c", + "arch-arm/bionic/__bionic_clone.S", + "arch-arm/bionic/_exit_with_stack_teardown.S", + "arch-arm/bionic/libgcc_compat.c", + "arch-arm/bionic/popcount_tab.c", + "arch-arm/bionic/__restore.S", + "arch-arm/bionic/setjmp.S", + "arch-arm/bionic/syscall.S", + "arch-arm/bionic/vfork.S", + ], + exclude_srcs: [ + "bionic/__memcpy_chk.cpp", + ], + cortex_a7: { + srcs: [ + "arch-arm/cortex-a7/bionic/memset.S", + + "arch-arm/cortex-a15/bionic/memcpy.S", + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/__strcat_chk.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/__strcpy_chk.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + cortex_a53: { + srcs: [ + "arch-arm/cortex-a53/bionic/memcpy.S", + "arch-arm/cortex-a53/bionic/__strcat_chk.S", + "arch-arm/cortex-a53/bionic/__strcpy_chk.S", + + "arch-arm/cortex-a7/bionic/memset.S", + + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + cortex_a53_a57: { + srcs: [ + "arch-arm/cortex-a15/bionic/memcpy.S", + "arch-arm/cortex-a15/bionic/memset.S", + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/__strcat_chk.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/__strcpy_chk.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + cortex_a8: { + srcs: [ + "arch-arm/cortex-a15/bionic/memcpy.S", + "arch-arm/cortex-a15/bionic/memset.S", + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/__strcat_chk.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/__strcpy_chk.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + cortex_a9: { + srcs: [ + "arch-arm/cortex-a9/bionic/memcpy.S", + "arch-arm/cortex-a9/bionic/memset.S", + "arch-arm/cortex-a9/bionic/stpcpy.S", + "arch-arm/cortex-a9/bionic/strcat.S", + "arch-arm/cortex-a9/bionic/__strcat_chk.S", + "arch-arm/cortex-a9/bionic/strcmp.S", + "arch-arm/cortex-a9/bionic/strcpy.S", + "arch-arm/cortex-a9/bionic/__strcpy_chk.S", + "arch-arm/cortex-a9/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + cortex_a15: { + srcs: [ + "arch-arm/cortex-a15/bionic/memcpy.S", + "arch-arm/cortex-a15/bionic/memset.S", + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/__strcat_chk.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/__strcpy_chk.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + denver: { + srcs: [ + "arch-arm/denver/bionic/memcpy.S", + "arch-arm/denver/bionic/memmove.S", + "arch-arm/denver/bionic/memset.S", + "arch-arm/denver/bionic/__strcat_chk.S", + "arch-arm/denver/bionic/__strcpy_chk.S", + + // Use cortex-a15 versions of strcat/strcpy/strlen. + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/strcmp.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/strlen.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + krait: { + srcs: [ + "arch-arm/krait/bionic/memcpy.S", + "arch-arm/krait/bionic/memset.S", + "arch-arm/krait/bionic/strcmp.S", + "arch-arm/krait/bionic/__strcat_chk.S", + "arch-arm/krait/bionic/__strcpy_chk.S", + + // Use cortex-a15 versions of strcat/strcpy/strlen. + "arch-arm/cortex-a15/bionic/stpcpy.S", + "arch-arm/cortex-a15/bionic/strcat.S", + "arch-arm/cortex-a15/bionic/strcpy.S", + "arch-arm/cortex-a15/bionic/strlen.S", + + "arch-arm/denver/bionic/memmove.S", + ], + exclude_srcs: [ + "arch-arm/generic/bionic/memcpy.S", + "arch-arm/generic/bionic/memset.S", + "arch-arm/generic/bionic/strcmp.S", + "arch-arm/generic/bionic/strcpy.S", + "arch-arm/generic/bionic/strlen.c", + "bionic/__strcat_chk.cpp", + "bionic/__strcpy_chk.cpp", + ], + }, + + }, + arm64: { + srcs: [ + "arch-arm64/generic/bionic/memchr.S", + "arch-arm64/generic/bionic/memcmp.S", + "arch-arm64/generic/bionic/memcpy.S", + "arch-arm64/generic/bionic/memmove.S", + "arch-arm64/generic/bionic/memset.S", + "arch-arm64/generic/bionic/stpcpy.S", + "arch-arm64/generic/bionic/strchr.S", + "arch-arm64/generic/bionic/strcmp.S", + "arch-arm64/generic/bionic/strcpy.S", + "arch-arm64/generic/bionic/strlen.S", + "arch-arm64/generic/bionic/strncmp.S", + "arch-arm64/generic/bionic/strnlen.S", + "arch-arm64/generic/bionic/wmemmove.S", + + "arch-arm64/bionic/__bionic_clone.S", + "arch-arm64/bionic/_exit_with_stack_teardown.S", + "arch-arm64/bionic/setjmp.S", + "arch-arm64/bionic/syscall.S", + "arch-arm64/bionic/vfork.S", + ], + exclude_srcs: [ + "bionic/__memcpy_chk.cpp", + "bionic/strchr.cpp", + "bionic/strnlen.c", + ], + denver64: { + srcs: [ + "arch-arm64/denver64/bionic/memcpy.S", + "arch-arm64/denver64/bionic/memset.S", + ], + exclude_srcs: [ + "arch-arm64/generic/bionic/memcpy.S", + "arch-arm64/generic/bionic/memset.S", + ], + }, + }, + + mips: { + srcs: [ + "arch-mips/string/memcmp.c", + "arch-mips/string/memcpy.S", + "arch-mips/string/memset.S", + "arch-mips/string/strcmp.S", + + "arch-mips/bionic/__bionic_clone.S", + "arch-mips/bionic/cacheflush.cpp", + "arch-mips/bionic/_exit_with_stack_teardown.S", + "arch-mips/bionic/libgcc_compat.c", + "arch-mips/bionic/setjmp.S", + "arch-mips/bionic/syscall.S", + "arch-mips/bionic/vfork.S", + + "arch-mips/string/mips_strlen.c", + ], + rev6: { + srcs: [ + "arch-mips/string/strlen.c", + ], + exclude_srcs: [ + "arch-mips/string/mips_strlen.c", + ], + }, + }, + mips64: { + srcs: [ + "arch-mips/string/memcmp.c", + "arch-mips/string/memcpy.S", + "arch-mips/string/memset.S", + "arch-mips/string/strcmp.S", + "arch-mips/string/strlen.c", + + "arch-mips64/bionic/__bionic_clone.S", + "arch-mips64/bionic/_exit_with_stack_teardown.S", + "arch-mips64/bionic/setjmp.S", + "arch-mips64/bionic/syscall.S", + "arch-mips64/bionic/vfork.S", + "arch-mips64/bionic/stat.cpp", + ], + }, + + x86: { + srcs: [ + "arch-x86/generic/string/memcmp.S", + "arch-x86/generic/string/strcmp.S", + "arch-x86/generic/string/strncmp.S", + "arch-x86/generic/string/strcat.S", + "arch-x86/atom/string/sse2-memchr-atom.S", + "arch-x86/atom/string/sse2-memrchr-atom.S", + "arch-x86/atom/string/sse2-strchr-atom.S", + "arch-x86/atom/string/sse2-strnlen-atom.S", + "arch-x86/atom/string/sse2-strrchr-atom.S", + "arch-x86/atom/string/sse2-wcschr-atom.S", + "arch-x86/atom/string/sse2-wcsrchr-atom.S", + "arch-x86/atom/string/sse2-wcslen-atom.S", + "arch-x86/atom/string/sse2-wcscmp-atom.S", + "arch-x86/silvermont/string/sse2-memcpy-slm.S", + "arch-x86/silvermont/string/sse2-memmove-slm.S", + "arch-x86/silvermont/string/sse2-memset-slm.S", + "arch-x86/silvermont/string/sse2-stpcpy-slm.S", + "arch-x86/silvermont/string/sse2-stpncpy-slm.S", + "arch-x86/silvermont/string/sse2-strcpy-slm.S", + "arch-x86/silvermont/string/sse2-strlen-slm.S", + "arch-x86/silvermont/string/sse2-strncpy-slm.S", + + "arch-x86/bionic/__bionic_clone.S", + "arch-x86/bionic/_exit_with_stack_teardown.S", + "arch-x86/bionic/libgcc_compat.c", + "arch-x86/bionic/__restore.S", + "arch-x86/bionic/setjmp.S", + "arch-x86/bionic/syscall.S", + "arch-x86/bionic/vfork.S", + ], + + exclude_srcs: [ + "bionic/strchr.cpp", + "bionic/strnlen.c", + "bionic/strrchr.cpp", + ], + atom: { + srcs: [ + "arch-x86/atom/string/sse2-memset-atom.S", + "arch-x86/atom/string/sse2-strlen-atom.S", + "arch-x86/atom/string/ssse3-memcmp-atom.S", + "arch-x86/atom/string/ssse3-memcpy-atom.S", + "arch-x86/atom/string/ssse3-memmove-atom.S", + "arch-x86/atom/string/ssse3-strcpy-atom.S", + "arch-x86/atom/string/ssse3-strncpy-atom.S", + "arch-x86/atom/string/ssse3-wmemcmp-atom.S", + ], + exclude_srcs: [ + "arch-x86/generic/string/memcmp.S", + "arch-x86/silvermont/string/sse2-memcpy-slm.S", + "arch-x86/silvermont/string/sse2-memmove-slm.S", + "arch-x86/silvermont/string/sse2-memset-slm.S", + "arch-x86/silvermont/string/sse2-strcpy-slm.S", + "arch-x86/silvermont/string/sse2-strlen-slm.S", + "arch-x86/silvermont/string/sse2-strncpy-slm.S", + ], + }, + ssse3: { + srcs: [ + "arch-x86/atom/string/ssse3-strncat-atom.S", + "arch-x86/atom/string/ssse3-strlcat-atom.S", + "arch-x86/atom/string/ssse3-strlcpy-atom.S", + "arch-x86/atom/string/ssse3-strcat-atom.S", + "arch-x86/atom/string/ssse3-strcmp-atom.S", + "arch-x86/atom/string/ssse3-strncmp-atom.S", + "arch-x86/atom/string/ssse3-wcscat-atom.S", + "arch-x86/atom/string/ssse3-wcscpy-atom.S", + ], + exclude_srcs: [ + "arch-x86/generic/string/strcmp.S", + "arch-x86/generic/string/strncmp.S", + "arch-x86/generic/string/strcat.S", + ], + }, + sse4: { + srcs: [ + "arch-x86/silvermont/string/sse4-memcmp-slm.S", + "arch-x86/silvermont/string/sse4-wmemcmp-slm.S", + ], + exclude_srcs: [ + "arch-x86/generic/string/memcmp.S", + ], + }, + }, + x86_64: { + srcs: [ + "arch-x86_64/string/sse2-memcpy-slm.S", + "arch-x86_64/string/sse2-memmove-slm.S", + "arch-x86_64/string/sse2-memset-slm.S", + "arch-x86_64/string/sse2-stpcpy-slm.S", + "arch-x86_64/string/sse2-stpncpy-slm.S", + "arch-x86_64/string/sse2-strcat-slm.S", + "arch-x86_64/string/sse2-strcpy-slm.S", + "arch-x86_64/string/sse2-strlcat-slm.S", + "arch-x86_64/string/sse2-strlcpy-slm.S", + "arch-x86_64/string/sse2-strlen-slm.S", + "arch-x86_64/string/sse2-strncat-slm.S", + "arch-x86_64/string/sse2-strncpy-slm.S", + "arch-x86_64/string/sse4-memcmp-slm.S", + "arch-x86_64/string/ssse3-strcmp-slm.S", + "arch-x86_64/string/ssse3-strncmp-slm.S", + + "arch-x86_64/bionic/__bionic_clone.S", + "arch-x86_64/bionic/_exit_with_stack_teardown.S", + "arch-x86_64/bionic/__restore_rt.S", + "arch-x86_64/bionic/setjmp.S", + "arch-x86_64/bionic/syscall.S", + "arch-x86_64/bionic/vfork.S", + ], + }, + }, + + cppflags: ["-Wold-style-cast"], + include_dirs: ["bionic/libstdc++/include"], + name: "libc_bionic", +} + +// ======================================================== +// libc_bionic_ndk.a- The portions of libc_bionic that can +// be safely used in libc_ndk.a (no troublesome global data +// or constructors). +// ======================================================== +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "bionic/abort.cpp", + "bionic/accept.cpp", + "bionic/accept4.cpp", + "bionic/access.cpp", + "bionic/arpa_inet.cpp", + "bionic/assert.cpp", + "bionic/atof.cpp", + "bionic/bionic_arc4random.cpp", + "bionic/bionic_netlink.cpp", + "bionic/bionic_systrace.cpp", + "bionic/bionic_time_conversions.cpp", + "bionic/brk.cpp", + "bionic/c16rtomb.cpp", + "bionic/c32rtomb.cpp", + "bionic/chmod.cpp", + "bionic/chown.cpp", + "bionic/clearenv.cpp", + "bionic/clock.cpp", + "bionic/clock_getcpuclockid.cpp", + "bionic/clock_nanosleep.cpp", + "bionic/clone.cpp", + "bionic/close.cpp", + "bionic/__cmsg_nxthdr.cpp", + "bionic/connect.cpp", + "bionic/ctype.cpp", + "bionic/dirent.cpp", + "bionic/dup2.cpp", + "bionic/epoll_create.cpp", + "bionic/epoll_pwait.cpp", + "bionic/epoll_wait.cpp", + "bionic/__errno.cpp", + "bionic/error.cpp", + "bionic/eventfd_read.cpp", + "bionic/eventfd_write.cpp", + "bionic/faccessat.cpp", + "bionic/fchmod.cpp", + "bionic/fchmodat.cpp", + "bionic/ffs.cpp", + "bionic/fgetxattr.cpp", + "bionic/flistxattr.cpp", + "bionic/flockfile.cpp", + "bionic/fortify.cpp", + "bionic/fpclassify.cpp", + "bionic/fsetxattr.cpp", + "bionic/ftruncate.cpp", + "bionic/ftw.cpp", + "bionic/futimens.cpp", + "bionic/getcwd.cpp", + "bionic/getdomainname.cpp", + "bionic/gethostname.cpp", + "bionic/getpagesize.cpp", + "bionic/getpgrp.cpp", + "bionic/getpid.cpp", + "bionic/gettid.cpp", + "bionic/__gnu_basename.cpp", + "bionic/grp_pwd.cpp", + "bionic/ifaddrs.cpp", + "bionic/inotify_init.cpp", + "bionic/ioctl.cpp", + "bionic/lchown.cpp", + "bionic/lfs64_support.cpp", + "bionic/__libc_current_sigrtmax.cpp", + "bionic/__libc_current_sigrtmin.cpp", + "bionic/libc_init_common.cpp", + "bionic/libc_logging.cpp", + "bionic/libgen.cpp", + "bionic/link.cpp", + "bionic/locale.cpp", + "bionic/lockf.cpp", + "bionic/lstat.cpp", + "bionic/malloc_info.cpp", + "bionic/mblen.cpp", + "bionic/mbrtoc16.cpp", + "bionic/mbrtoc32.cpp", + "bionic/mbstate.cpp", + "bionic/memmem.cpp", + "bionic/mempcpy.cpp", + "bionic/mkdir.cpp", + "bionic/mkfifo.cpp", + "bionic/mknod.cpp", + "bionic/mntent.cpp", + "bionic/mremap.cpp", + "bionic/netdb.cpp", + "bionic/NetdClientDispatch.cpp", + "bionic/net_if.cpp", + "bionic/netinet_in.cpp", + "bionic/nl_types.cpp", + "bionic/open.cpp", + "bionic/pathconf.cpp", + "bionic/pause.cpp", + "bionic/pipe.cpp", + "bionic/poll.cpp", + "bionic/posix_fadvise.cpp", + "bionic/posix_fallocate.cpp", + "bionic/posix_madvise.cpp", + "bionic/posix_timers.cpp", + "bionic/ptrace.cpp", + "bionic/pty.cpp", + "bionic/raise.cpp", + "bionic/rand.cpp", + "bionic/readlink.cpp", + "bionic/reboot.cpp", + "bionic/recv.cpp", + "bionic/rename.cpp", + "bionic/rmdir.cpp", + "bionic/scandir.cpp", + "bionic/sched_getaffinity.cpp", + "bionic/sched_getcpu.cpp", + "bionic/semaphore.cpp", + "bionic/send.cpp", + "bionic/setegid.cpp", + "bionic/__set_errno.cpp", + "bionic/seteuid.cpp", + "bionic/setpgrp.cpp", + "bionic/sigaction.cpp", + "bionic/sigaddset.cpp", + "bionic/sigdelset.cpp", + "bionic/sigemptyset.cpp", + "bionic/sigfillset.cpp", + "bionic/sighold.cpp", + "bionic/sigignore.cpp", + "bionic/sigismember.cpp", + "bionic/signal.cpp", + "bionic/signalfd.cpp", + "bionic/sigpause.cpp", + "bionic/sigpending.cpp", + "bionic/sigprocmask.cpp", + "bionic/sigqueue.cpp", + "bionic/sigrelse.cpp", + "bionic/sigset.cpp", + "bionic/sigsuspend.cpp", + "bionic/sigtimedwait.cpp", + "bionic/sigwait.cpp", + "bionic/sigwaitinfo.cpp", + "bionic/socket.cpp", + "bionic/stat.cpp", + "bionic/statvfs.cpp", + "bionic/strchrnul.cpp", + "bionic/strerror.cpp", + "bionic/strerror_r.cpp", + "bionic/strsignal.cpp", + "bionic/strtold.cpp", + "bionic/symlink.cpp", + "bionic/sync_file_range.cpp", + "bionic/sysinfo.cpp", + "bionic/syslog.cpp", + "bionic/sys_msg.cpp", + "bionic/sys_sem.cpp", + "bionic/sys_shm.cpp", + "bionic/sys_siglist.c", + "bionic/sys_signame.c", + "bionic/sys_time.cpp", + "bionic/system_properties.cpp", + "bionic/tdestroy.cpp", + "bionic/termios.cpp", + "bionic/thread_private.cpp", + "bionic/tmpfile.cpp", + "bionic/umount.cpp", + "bionic/unlink.cpp", + "bionic/wait.cpp", + "bionic/wchar.cpp", + "bionic/wctype.cpp", + "bionic/wmempcpy.cpp", + ], + + multilib: { + lib32: { + // LP32 cruft + srcs: ["bionic/mmap.cpp"], + }, + }, + + cppflags: ["-Wold-style-cast"], + local_include_dirs: ["stdio"], + include_dirs: ["bionic/libstdc++/include"], + name: "libc_bionic_ndk", +} + +// ======================================================== +// libc_pthread.a - pthreads parts that previously lived in +// libc_bionic.a. Relocated to their own library because +// they can't be included in libc_ndk.a (as they layout of +// pthread_t has changed over the years and has ABI +// compatibility issues). +// ======================================================== + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "bionic/pthread_atfork.cpp", + "bionic/pthread_attr.cpp", + "bionic/pthread_barrier.cpp", + "bionic/pthread_cond.cpp", + "bionic/pthread_create.cpp", + "bionic/pthread_detach.cpp", + "bionic/pthread_equal.cpp", + "bionic/pthread_exit.cpp", + "bionic/pthread_getcpuclockid.cpp", + "bionic/pthread_getschedparam.cpp", + "bionic/pthread_gettid_np.cpp", + "bionic/pthread_internal.cpp", + "bionic/pthread_join.cpp", + "bionic/pthread_key.cpp", + "bionic/pthread_kill.cpp", + "bionic/pthread_mutex.cpp", + "bionic/pthread_once.cpp", + "bionic/pthread_rwlock.cpp", + "bionic/pthread_self.cpp", + "bionic/pthread_setname_np.cpp", + "bionic/pthread_setschedparam.cpp", + "bionic/pthread_sigmask.cpp", + "bionic/pthread_spinlock.cpp", + ], + + cppflags: ["-Wold-style-cast"], + include_dirs: ["bionic/libstdc++/include"], + name: "libc_pthread", +} + +// ======================================================== +// libc_syscalls.a +// ======================================================== + +cc_library_static { + defaults: ["libc_defaults"], + arch: { + arm: { + srcs: ["arch-arm/syscalls/**/*.S"], + }, + arm64: { + srcs: ["arch-arm64/syscalls/**/*.S"], + }, + mips: { + srcs: ["arch-mips/syscalls/**/*.S"], + }, + mips64: { + srcs: ["arch-mips64/syscalls/**/*.S"], + }, + x86: { + srcs: ["arch-x86/syscalls/**/*.S"], + }, + x86_64: { + srcs: ["arch-x86_64/syscalls/**/*.S"], + }, + }, + name: "libc_syscalls", +} + +// ======================================================== +// libc_aeabi.a +// This is an LP32 ARM-only library that needs to be built with -fno-builtin +// to avoid infinite recursion. For the other architectures we just build an +// empty library to keep this makefile simple. +// ======================================================== + +cc_library_static { + defaults: ["libc_defaults"], + arch: { + arm: { + srcs: ["arch-arm/bionic/__aeabi.c"], + }, + }, + name: "libc_aeabi", + cflags: ["-fno-builtin"], +} + +// ======================================================== +// libc_ndk.a +// Compatibility library for the NDK. This library contains +// all the parts of libc that are safe to statically link. +// We can't safely statically link things that can only run +// on a certain version of the OS. Examples include +// anything that talks to netd (a large portion of the DNS +// code) and anything that is dependent on the layout of a +// data structure that has changed across releases (such as +// pthread_t). +// ======================================================== + +cc_library_static { + name: "libc_ndk", + defaults: ["libc_defaults"], + srcs: libc_common_src_files + ["bionic/malloc_common.cpp"], + multilib: { + lib32: { + srcs: libc_common_src_files_32, + }, + }, + arch: { + arm: { + srcs: [ + "arch-arm/bionic/exidx_dynamic.c", + "arch-common/bionic/crtbegin_so.c", + "arch-arm/bionic/atexit_legacy.c", + "arch-common/bionic/crtend_so.S", + ], + whole_static_libs: ["libc_aeabi"], + }, + }, + + cflags: [ + "-fvisibility=hidden", + "-DLIBC_STATIC", + ], + + whole_static_libs: [ + "libc_bionic_ndk", + "libc_freebsd", + "libc_freebsd_large_stack", + "libc_gdtoa", + "libc_malloc", + "libc_netbsd", + "libc_openbsd_large_stack", + "libc_openbsd_ndk", + "libc_stack_protector", + "libc_syscalls", + "libc_tzcode", + "libm", + "libjemalloc", + "libstdc++", + ], +} + +// ======================================================== +// libc_common.a +// ======================================================== + +cc_library_static { + defaults: ["libc_defaults"], + srcs: libc_common_src_files, + multilib: { + lib32: { + srcs: libc_common_src_files_32, + }, + }, + name: "libc_common", + + whole_static_libs: [ + "libc_bionic", + "libc_bionic_ndk", + "libc_dns", + "libc_freebsd", + "libc_freebsd_large_stack", + "libc_gdtoa", + "libc_malloc", + "libc_netbsd", + "libc_openbsd", + "libc_openbsd_large_stack", + "libc_openbsd_ndk", + "libc_pthread", + "libc_stack_protector", + "libc_syscalls", + "libc_tzcode", + "libstdc++", + ], + + arch: { + arm: { + whole_static_libs: ["libc_aeabi"], + }, + }, +} + +// ======================================================== +// libc_nomalloc.a +// ======================================================== +// +// This is a version of the static C library that does not +// include malloc. It's useful in situations when the user wants +// to provide their own malloc implementation, or wants to +// explicitly disallow the use of malloc, such as in the +// dynamic linker. + +cc_library_static { + defaults: ["libc_defaults"], + srcs: [ + "bionic/dl_iterate_phdr_static.cpp", + ], + + arch: { + arm: { + srcs: ["arch-arm/bionic/exidx_static.c"], + }, + }, + + cflags: ["-DLIBC_STATIC"], + + name: "libc_nomalloc", + + whole_static_libs: [ + "libc_common", + "libc_init_static", + ], +} + +// ======================================================== +// libc_malloc.a: the _prefixed_ malloc functions (like dlcalloc). +// ======================================================== +cc_library_static { + defaults: ["libc_defaults"], + srcs: ["bionic/jemalloc_wrapper.cpp"], + cflags: ["-fvisibility=hidden"], + + name: "libc_malloc", +} + +// ======================================================== +// libc.a + libc.so +// ======================================================== +cc_library { + defaults: ["libc_defaults"], + name: "libc", + product_variables: { + platform_sdk_version: { + asflags: ["-DPLATFORM_SDK_VERSION=%d"], + }, + }, + static: { + srcs: [ + "bionic/dl_iterate_phdr_static.cpp", + "bionic/malloc_common.cpp", + "bionic/libc_init_static.cpp", + ], + cflags: ["-DLIBC_STATIC"], + whole_static_libs: ["libc_init_static", "libjemalloc"], + }, + shared: { + srcs: [ + "arch-common/bionic/crtbegin_so.c", + "arch-common/bionic/crtbrand.S", + "bionic/malloc_common.cpp", + "bionic/libc_init_dynamic.cpp", + "bionic/NetdClient.cpp", + "arch-common/bionic/crtend_so.S", + ], + whole_static_libs: ["libjemalloc"], + }, + + required: ["tzdata"], + + // Leave the symbols in the shared library so that stack unwinders can produce + // meaningful name resolution. + strip: { + keep_symbols: true, + }, + + // WARNING: The only library libc.so should depend on is libdl.so! If you add other libraries, + // make sure to add -Wl,--exclude-libs=libgcc.a to the LOCAL_LDFLAGS for those libraries. This + // ensures that symbols that are pulled into those new libraries from libgcc.a are not declared + // external; if that were the case, then libc would not pull those symbols from libgcc.a as it + // should, instead relying on the external symbols from the dependent libraries. That would + // create a "cloaked" dependency on libgcc.a in libc though the libraries, which is not what + // you wanted! + + shared_libs: ["libdl"], + whole_static_libs: ["libc_common"], + + nocrt: true, + + arch: { + arm: { + //TODO: This is to work around b/24465209. Remove after root cause is fixed + ldflags: ["-Wl,--hash-style=both"], + + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.arm.map", + + shared: { + srcs: [ + "arch-arm/bionic/exidx_dynamic.c", + + // special for arm + "arch-arm/bionic/atexit_legacy.c", + ], + // special for arm + cflags: ["-DCRT_LEGACY_WORKAROUND"], + }, + static: { + srcs: ["arch-arm/bionic/exidx_static.c"], + }, + }, + arm64: { + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.arm64.map", + }, + mips: { + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.mips.map", + }, + mips64: { + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.mips64.map", + }, + x86: { + //TODO: This is to work around b/24465209. Remove after root cause is fixed + ldflags: ["-Wl,--hash-style=both"], + + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.x86.map", + }, + x86_64: { + // Don't re-export new/delete and friends, even if the compiler really wants to. + version_script: "libc.x86_64.map", + }, + }, +} + +// ======================================================== +// libc_logging.a +// ======================================================== +cc_library_static { + defaults: ["libc_defaults"], + + srcs: [ + "bionic/libc_logging.cpp", + ], + + name: "libc_logging", +} + +// ======================================================== +// libstdc++.so + libstdc++.a +// ======================================================== +cc_library { + defaults: ["libc_defaults"], + include_dirs: ["bionic/libstdc++/include"], + srcs: [ + "bionic/__cxa_guard.cpp", + "bionic/__cxa_pure_virtual.cpp", + "bionic/new.cpp", + ], + name: "libstdc++", + system_shared_libs: ["libc"], + shared: { + static_libs: ["libc_logging"], + }, + + //TODO (dimitry): This is to work around b/24465209. Remove after root cause is fixed + arch: { + arm: { + ldflags: ["-Wl,--hash-style=both"], + version_script: "libstdc++.arm.map", + }, + arm64: { + version_script: "libstdc++.arm64.map", + }, + mips: { + version_script: "libstdc++.mips.map", + }, + mips64: { + version_script: "libstdc++.mips64.map", + }, + x86: { + ldflags: ["-Wl,--hash-style=both"], + version_script: "libstdc++.x86.map", + }, + x86_64: { + version_script: "libstdc++.x86_64.map", + }, + }, +} + +cc_defaults { + name: "crt_defaults", + + no_default_compiler_flags: true, + + arch: { + arm: { + local_include_dirs: ["arch-arm/include"], + }, + arm64: { + local_include_dirs: ["arch-arm64/include"], + }, + mips: { + local_include_dirs: ["arch-mips/include"], + }, + mips64: { + local_include_dirs: ["arch-mips64/include"], + }, + x86: { + local_include_dirs: ["arch-x86/include"], + }, + x86_64: { + local_include_dirs: ["arch-x86_64/include"], + }, + }, + clang: false, +} + +cc_defaults { + name: "crt_so_defaults", + + arch: { + mips: { + cflags: ["-fPIC"], + }, + mips64: { + cflags: ["-fPIC"], + }, + x86: { + cflags: ["-fPIC"], + }, + x86_64: { + cflags: ["-fPIC"], + }, + }, +} + +// Android.mk:start +// # crt obj files +// # ======================================================== +// # crtbrand.c needs <stdint.h> and a #define for the platform SDK version. +// libc_crt_target_cflags := \ +// -I$(LOCAL_PATH)/include \ +// -DPLATFORM_SDK_VERSION=$(PLATFORM_SDK_VERSION) \ +// +// my_2nd_arch_prefix := +// include $(LOCAL_PATH)/arch-$(TARGET_ARCH)/$(TARGET_ARCH).mk +// include $(LOCAL_PATH)/crt.mk +// ifdef TARGET_2ND_ARCH +// my_2nd_arch_prefix := $(TARGET_2ND_ARCH_VAR_PREFIX) +// include $(LOCAL_PATH)/arch-$(TARGET_2ND_ARCH)/$(TARGET_2ND_ARCH).mk +// include $(LOCAL_PATH)/crt.mk +// my_2nd_arch_prefix := +// endif +// +// include $(call all-makefiles-under,$(LOCAL_PATH)) +// Android.mk:end +cc_object { + name: "crtbrand", + local_include_dirs: ["include"], + product_variables: { + platform_sdk_version: { + asflags: ["-DPLATFORM_SDK_VERSION=%d"], + }, + }, + srcs: ["arch-common/bionic/crtbrand.S"], + + defaults: [ + "crt_defaults", + "crt_so_defaults", + ], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_so1", + local_include_dirs: ["include"], + srcs: ["arch-common/bionic/crtbegin_so.c"], + + defaults: [ + "crt_defaults", + "crt_so_defaults", + ], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_so", + + defaults: [ + "crt_defaults", + "crt_so_defaults", + ], + objs: [ + "crtbegin_so1", + "crtbrand", + ], +} + +// Android.mk:ignore +cc_object { + name: "crtend_so", + local_include_dirs: ["include"], + srcs: ["arch-common/bionic/crtend_so.S"], + + defaults: [ + "crt_defaults", + "crt_so_defaults", + ], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_static1", + local_include_dirs: ["include"], + srcs: ["arch-common/bionic/crtbegin.c"], + + arch: { + arm64: { + srcs: [ + "arch-arm64/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + mips: { + srcs: [ + "arch-mips/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + mips64: { + srcs: [ + "arch-mips64/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + }, + + defaults: ["crt_defaults"], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_static", + + objs: [ + "crtbegin_static1", + "crtbrand", + ], + defaults: ["crt_defaults"], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_dynamic1", + local_include_dirs: ["include"], + srcs: ["arch-common/bionic/crtbegin.c"], + + arch: { + arm64: { + srcs: [ + "arch-arm64/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + mips: { + srcs: [ + "arch-mips/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + mips64: { + srcs: [ + "arch-mips64/bionic/crtbegin.c", + ], + exclude_srcs: [ + "arch-common/bionic/crtbegin.c", + ], + }, + }, + defaults: ["crt_defaults"], +} + +// Android.mk:ignore +cc_object { + name: "crtbegin_dynamic", + + objs: [ + "crtbegin_dynamic1", + "crtbrand", + ], + defaults: ["crt_defaults"], +} + +// Android.mk:ignore +cc_object { + // We rename crtend.o to crtend_android.o to avoid a + // name clash between gcc and bionic. + name: "crtend_android", + local_include_dirs: ["include"], + srcs: ["arch-common/bionic/crtend.S"], + + defaults: ["crt_defaults"], +} + +subdirs = ["malloc_debug"]
diff --git a/libc/Android.mk b/libc/Android.mk new file mode 100644 index 0000000..888404c --- /dev/null +++ b/libc/Android.mk
@@ -0,0 +1,4 @@ +LOCAL_PATH := $(call my-dir) + +include $(call all-makefiles-under,$(LOCAL_PATH)) +
diff --git a/libc/MODULE_LICENSE_BSD b/libc/MODULE_LICENSE_BSD new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/libc/MODULE_LICENSE_BSD
diff --git a/libc/NOTICE b/libc/NOTICE new file mode 100644 index 0000000..26591a9 --- /dev/null +++ b/libc/NOTICE
@@ -0,0 +1,5172 @@ + Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + + strchr - find a character in a string + + Copyright (c) 2014, ARM Limited + All rights Reserved. + Copyright (c) 2014, Linaro Ltd. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the company nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + + Copyright (c) 1993 John Brezak + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. 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Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1982, 1986, 1993 + The Regents of the University of California. All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1983, 1987, 1989 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1983, 1989 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1983, 1989, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1983, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1983, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1985 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1985 Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1985, 1988, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +Portions Copyright (c) 1993 by Digital Equipment Corporation. + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies, and that +the name of Digital Equipment Corporation not be used in advertising or +publicity pertaining to distribution of the document or software without +specific, written prior permission. + +THE SOFTWARE IS PROVIDED "AS IS" AND DIGITAL EQUIPMENT CORP. DISCLAIMS ALL +WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL DIGITAL EQUIPMENT +CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL +DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS +ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1985, 1989, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1985, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1985, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1987 Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1987, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1987, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1988 Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1988 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1988, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1988, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1988, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software written by Ken Arnold and +published in UNIX Review, Vol. 6, No. 8. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989 The Regents of the University of California. +All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Roger L. Snyder. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1989, 1993 + The Regents of the University of California. All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990 Regents of the University of California. +All rights reserved. + +This code is derived from software contributed to Berkeley by +Chris Torek. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990 The Regents of the University of California. +All rights reserved. + +This code is derived from software contributed to Berkeley by +Chris Torek. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990 The Regents of the University of California. +All rights reserved. + +This code is derived from software contributed to Berkeley by +William Jolitz. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Chris Torek. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Donn Seeley at UUNET Technologies, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Donn Seeley at UUNET Technologies, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993 + The Regents of the University of California. All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993, 1994 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1990, 1993, 1994 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Chris Torek. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1991 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1991, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1991, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Berkeley Software Design, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1991, 1993 + The Regents of the University of California. All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +This code is derived from software contributed to Berkeley by +Hugh Smith at The University of Guelph. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1991, 1993, 1995, + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Havard Eidnes. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992 Henry Spencer. +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Henry Spencer of the University of Toronto. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Ralph Campbell. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Ralph Campbell. This file is derived from the MIPS RISC +Architecture book by Gerry Kane. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. + +This software was developed by the Computer Systems Engineering group +at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and +contributed to Berkeley. + +All advertising materials mentioning features or use of this software +must display the following acknowledgement: + This product includes software developed by the University of + California, Lawrence Berkeley Laboratory. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993 + The Regents of the University of California. All rights reserved. +(c) UNIX System Laboratories, Inc. +All or some portions of this file are derived from material licensed +to the University of California by American Telephone and Telegraph +Co. or Unix System Laboratories, Inc. and are reproduced herein with +the permission of UNIX System Laboratories, Inc. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993, 1994 + The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Henry Spencer. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1992, 1993, 1994 Henry Spencer. + +This code is derived from software contributed to Berkeley by +Henry Spencer. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the University of + California, Berkeley and its contributors. +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1993 Martin Birgmeier +All rights reserved. + +You may redistribute unmodified or modified versions of this source +code provided that the above copyright notice and this and the +following conditions are retained. + +This software is provided ``as is'', and comes with no warranties +of any kind. I shall in no event be liable for anything that happens +to anyone/anything when using this software. + +------------------------------------------------------------------- + +Copyright (c) 1994 SigmaSoft, Th. Lockert <tholo@sigmasoft.com> +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1996 by Internet Software Consortium. + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND INTERNET SOFTWARE CONSORTIUM DISCLAIMS +ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL INTERNET SOFTWARE +CONSORTIUM BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL +DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR +PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS +ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1996, David Mazieres <dm@uun.org> +Copyright (c) 2008, Damien Miller <djm@openbsd.org> +Copyright (c) 2013, Markus Friedl <markus@openbsd.org> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1996-1998, 2008 Theo de Raadt +Copyright (c) 1997, 2008-2009 Todd C. Miller + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1997 Mark Brinicombe +Copyright (c) 2010 Android Open Source Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by Mark Brinicombe +4. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997 Niklas Hallqvist. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997 Todd C. Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1997 Todd C. Miller <Todd.Miller@courtesan.com> +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. +All rights reserved. + +This code was contributed to The NetBSD Foundation by Klaus Klein. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the NetBSD + Foundation, Inc. and its contributors. +4. Neither the name of The NetBSD Foundation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997, 1998, 1999, 2004 The NetBSD Foundation, Inc. +All rights reserved. + +This code is derived from software contributed to The NetBSD Foundation +by Luke Mewburn. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997, 1998, 1999, 2004 The NetBSD Foundation, Inc. +All rights reserved. + +This code is derived from software contributed to The NetBSD Foundation +by Luke Mewburn; and by Jason R. Thorpe. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the NetBSD + Foundation, Inc. and its contributors. +4. Neither the name of The NetBSD Foundation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1997, 2005 Todd C. Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +------------------------------------------------------------------- + +Copyright (c) 1998 Softweyr LLC. All rights reserved. + +strtok_r, from Berkeley strtok +Oct 13, 1998 by Wes Peters <wes@softweyr.com> + +Copyright (c) 1988, 1993 + The Regents of the University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notices, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notices, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY SOFTWEYR LLC, THE REGENTS AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SOFTWEYR LLC, THE +REGENTS, OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1998 The NetBSD Foundation, Inc. +All rights reserved. + +This code is derived from software contributed to The NetBSD Foundation +by Klaus Klein. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by the NetBSD + Foundation, Inc. and its contributors. +4. Neither the name of The NetBSD Foundation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 1998 Todd C. Miller <Todd.Miller@courtesan.com> +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 2002 Todd C. Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. 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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 2002-2004 Tim J. Robbins +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. 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Vidrine, Safeport Network Services, and Network +Associates Laboratories, the Security Research Division of Network +Associates, Inc. under DARPA/SPAWAR contract N66001-01-C-8035 +("CBOSS"), as part of the DARPA CHATS research program. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 2003 Todd C. Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. 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Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. 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AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- + +Copyright (c) 2004 by Internet Systems Consortium, Inc. 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Miller <Todd.Miller@courtesan.com> + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. 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But Niels designed the +actual system based on the constraints. + +Later modified by Damien Miller to wrap the LCG output in a 15-bit +permutation generator based on a Luby-Rackoff block cipher. This +ensures the output is non-repeating and preserves the MSB twiddle +trick, but makes it more resistant to LCG prediction. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. 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(hereinafter called IBM) grants +permission under its copyrights to use, copy, modify, and distribute this +Software with or without fee, provided that the above copyright notice and +all paragraphs of this notice appear in all copies, and that the name of IBM +not be used in connection with the marketing of any product incorporating +the Software or modifications thereof, without specific, written prior +permission. + +To the extent it has a right to do so, IBM grants an immunity from suit +under its patents, if any, for the use, sale or manufacture of products to +the extent that such products are used for performing Domain Name System +dynamic updates in TCP/IP networks by means of the Software. No immunity is +granted for any product per se or for any other function of any product. + +THE SOFTWARE IS PROVIDED "AS IS", AND IBM DISCLAIMS ALL WARRANTIES, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE. IN NO EVENT SHALL IBM BE LIABLE FOR ANY SPECIAL, +DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER ARISING +OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE, EVEN +IF IBM IS APPRISED OF THE POSSIBILITY OF SUCH DAMAGES. + +------------------------------------------------------------------- + +Portions Copyright(C) 1995, Jason Downs. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998, 1999 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998, 2000 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2000 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 2000 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + +------------------------------------------------------------------- + +memchr - find a character in a memory zone + +Copyright (c) 2014, ARM Limited +All rights Reserved. +Copyright (c) 2014, Linaro Ltd. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the company nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +------------------------------------------------------------------- +
diff --git a/libc/SYSCALLS.TXT b/libc/SYSCALLS.TXT new file mode 100644 index 0000000..42c8f01 --- /dev/null +++ b/libc/SYSCALLS.TXT
@@ -0,0 +1,356 @@ +# This file is used to automatically generate bionic's system call stubs. +# +# Each non-blank, non-comment line has the following format: +# +# return_type func_name[|alias_list][:syscall_name[:socketcall_id]]([parameter_list]) arch_list +# +# where: +# arch_list ::= "all" | arch+ +# arch ::= "arm" | "arm64" | "mips" | "mips64" | "x86" | "x86_64" +# +# Note: +# - syscall_name corresponds to the name of the syscall, which may differ from +# the exported function name (example: the exit syscall is implemented by the _exit() +# function, which is not the same as the standard C exit() function which calls it) +# +# - alias_list is optional comma separated list of function aliases. +# +# - The call_id parameter, given that func_name and syscall_name have +# been provided, allows the user to specify dispatch style syscalls. +# For example, socket() syscall on i386 actually becomes: +# socketcall(__NR_socket, 1, *(rest of args on stack)). +# +# - Each parameter type is assumed to be stored in 32 bits. +# +# This file is processed by a python script named gensyscalls.py. + +int execve(const char*, char* const*, char* const*) all + +uid_t getuid:getuid32() arm,x86 +uid_t getuid:getuid() arm64,mips,mips64,x86_64 +gid_t getgid:getgid32() arm,x86 +gid_t getgid:getgid() arm64,mips,mips64,x86_64 +uid_t geteuid:geteuid32() arm,x86 +uid_t geteuid:geteuid() arm64,mips,mips64,x86_64 +gid_t getegid:getegid32() arm,x86 +gid_t getegid:getegid() arm64,mips,mips64,x86_64 +uid_t getresuid:getresuid32(uid_t* ruid, uid_t* euid, uid_t* suid) arm,x86 +uid_t getresuid:getresuid(uid_t* ruid, uid_t* euid, uid_t* suid) arm64,mips,mips64,x86_64 +gid_t getresgid:getresgid32(gid_t* rgid, gid_t* egid, gid_t* sgid) arm,x86 +gid_t getresgid:getresgid(gid_t* rgid, gid_t* egid, gid_t* sgid) arm64,mips,mips64,x86_64 +ssize_t readahead(int, off64_t, size_t) all +int getgroups:getgroups32(int, gid_t*) arm,x86 +int getgroups:getgroups(int, gid_t*) arm64,mips,mips64,x86_64 +pid_t getpgid(pid_t) all +pid_t getppid() all +pid_t getsid(pid_t) all +pid_t setsid() all +int setgid:setgid32(gid_t) arm,x86 +int setgid:setgid(gid_t) arm64,mips,mips64,x86_64 +int setuid:setuid32(uid_t) arm,x86 +int setuid:setuid(uid_t) arm64,mips,mips64,x86_64 +int setreuid:setreuid32(uid_t, uid_t) arm,x86 +int setreuid:setreuid(uid_t, uid_t) arm64,mips,mips64,x86_64 +int setresuid:setresuid32(uid_t, uid_t, uid_t) arm,x86 +int setresuid:setresuid(uid_t, uid_t, uid_t) arm64,mips,mips64,x86_64 +int setresgid:setresgid32(gid_t, gid_t, gid_t) arm,x86 +int setresgid:setresgid(gid_t, gid_t, gid_t) arm64,mips,mips64,x86_64 +void* __brk:brk(void*) all +int kill(pid_t, int) all +int tgkill(pid_t tgid, pid_t tid, int sig) all +int __ptrace:ptrace(int request, int pid, void* addr, void* data) all + +# <sys/resource.h> +int getrusage(int, struct rusage*) all +int __getpriority:getpriority(int, int) all +int setpriority(int, int, int) all +# On LP64, rlimit and rlimit64 are the same. +# On 32-bit systems we use prlimit64 to implement the rlimit64 functions. +int getrlimit:ugetrlimit(int, struct rlimit*) arm,x86 +int getrlimit(int, struct rlimit*) mips +int getrlimit|getrlimit64(int, struct rlimit*) arm64,mips64,x86_64 +int setrlimit(int, const struct rlimit*) arm,mips,x86 +int setrlimit|setrlimit64(int, const struct rlimit*) arm64,mips64,x86_64 +int prlimit64|prlimit(pid_t, int, struct rlimit64*, const struct rlimit64*) arm64,mips64,x86_64 +int prlimit64(pid_t, int, struct rlimit64*, const struct rlimit64*) arm,mips,x86 + +int setgroups:setgroups32(int, const gid_t*) arm,x86 +int setgroups:setgroups(int, const gid_t*) arm64,mips,mips64,x86_64 +int setpgid(pid_t, pid_t) all +int setregid:setregid32(gid_t, gid_t) arm,x86 +int setregid:setregid(gid_t, gid_t) arm64,mips,mips64,x86_64 +int chroot(const char*) all +int prctl(int, unsigned long, unsigned long, unsigned long, unsigned long) all +long __arch_prctl:arch_prctl(int, unsigned long) x86_64 +int capget(cap_user_header_t header, cap_user_data_t data) all +int capset(cap_user_header_t header, const cap_user_data_t data) all +int sigaltstack(const stack_t*, stack_t*) all +int acct(const char* filepath) all + +# file descriptors +ssize_t read(int, void*, size_t) all +ssize_t write(int, const void*, size_t) all +ssize_t pread64(int, void*, size_t, off64_t) arm,mips,x86 +ssize_t pread64|pread(int, void*, size_t, off_t) arm64,mips64,x86_64 +ssize_t pwrite64(int, void*, size_t, off64_t) arm,mips,x86 +ssize_t pwrite64|pwrite(int, void*, size_t, off_t) arm64,mips64,x86_64 + +# On LP32, preadv/pwritev don't use off64_t --- they use pairs of 32-bit +# arguments to avoid problems on architectures like ARM where 64-bit arguments +# must be in a register pair starting with an even-numbered register. +# See linux/fs/read_write.c and https://lwn.net/Articles/311630/. +ssize_t __preadv64:preadv(int, const struct iovec*, int, long, long) arm,mips,x86 +ssize_t preadv|preadv64(int, const struct iovec*, int, off_t) arm64,mips64,x86_64 +ssize_t __pwritev64:pwritev(int, const struct iovec*, int, long, long) arm,mips,x86 +ssize_t pwritev|pwritev64(int, const struct iovec*, int, off_t) arm64,mips64,x86_64 + +int ___close:close(int) all +pid_t __getpid:getpid() all +int munmap(void*, size_t) all +void* ___mremap:mremap(void*, size_t, size_t, int, void*) all +int msync(const void*, size_t, int) all +int mprotect(const void*, size_t, int) all +int madvise(void*, size_t, int) all +int mlock(const void* addr, size_t len) all +int munlock(const void* addr, size_t len) all +int mlockall(int flags) all +int munlockall() all +int mincore(void* start, size_t length, unsigned char* vec) all +int __ioctl:ioctl(int, int, void*) all +int readv(int, const struct iovec*, int) all +int writev(int, const struct iovec*, int) all +int __fcntl64:fcntl64(int, int, void*) arm,mips,x86 +int fcntl(int, int, void*) arm64,mips64,x86_64 +int flock(int, int) all +int ___fchmod:fchmod(int, mode_t) all +int dup(int) all +int pipe2(int*, int) all +int dup3(int, int, int) all +int fsync(int) all +int fdatasync(int) all +int fchown:fchown32(int, uid_t, gid_t) arm,x86 +int fchown:fchown(int, uid_t, gid_t) arm64,mips,mips64,x86_64 +void sync(void) all +int ___fsetxattr:fsetxattr(int, const char*, const void*, size_t, int) all +ssize_t ___fgetxattr:fgetxattr(int, const char*, void*, size_t) all +ssize_t ___flistxattr:flistxattr(int, char*, size_t) all +int fremovexattr(int, const char*) all + +int __getdents64:getdents64(unsigned int, struct dirent*, unsigned int) arm,arm64,mips,mips64,x86,x86_64 + +int __openat:openat(int, const char*, int, mode_t) all +int ___faccessat:faccessat(int, const char*, int) all +int ___fchmodat:fchmodat(int, const char*, mode_t) all +int fchownat(int, const char*, uid_t, gid_t, int) all +int fstatat64|fstatat:fstatat64(int, const char*, struct stat*, int) arm,mips,x86 +int fstatat64|fstatat:newfstatat(int, const char*, struct stat*, int) arm64,x86_64 +int linkat(int, const char*, int, const char*, int) all +int mkdirat(int, const char*, mode_t) all +int mknodat(int, const char*, mode_t, dev_t) all +int readlinkat(int, const char*, char*, size_t) all +int renameat(int, const char*, int, const char*) all +int symlinkat(const char*, int, const char*) all +int unlinkat(int, const char*, int) all +int utimensat(int, const char*, const struct timespec times[2], int) all + +# Paired off_t/off64_t system calls. On 64-bit systems, +# sizeof(off_t) == sizeof(off64_t), so there we emit two symbols that are +# aliases. On 32-bit systems, we have two different system calls. +# That means that every system call in this section should take three lines. +off_t lseek(int, off_t, int) arm,mips,x86 +int __llseek:_llseek(int, unsigned long, unsigned long, off64_t*, int) arm,mips,x86 +off_t lseek|lseek64(int, off_t, int) arm64,mips64,x86_64 +int ftruncate64(int, off64_t) arm,mips,x86 +int ftruncate|ftruncate64(int, off_t) arm64,mips64,x86_64 +ssize_t sendfile(int out_fd, int in_fd, off_t* offset, size_t count) arm,mips,x86 +ssize_t sendfile64(int out_fd, int in_fd, off64_t* offset, size_t count) arm,mips,x86 +ssize_t sendfile|sendfile64(int out_fd, int in_fd, off_t* offset, size_t count) arm64,mips64,x86_64 +int truncate(const char*, off_t) arm,mips,x86 +int truncate64(const char*, off64_t) arm,mips,x86 +int truncate|truncate64(const char*, off_t) arm64,mips64,x86_64 +# (mmap only gets two lines because we only used the 64-bit variant on 32-bit systems.) +void* __mmap2:mmap2(void*, size_t, int, int, int, long) arm,mips,x86 +void* mmap|mmap64(void*, size_t, int, int, int, off_t) arm64,mips64,x86_64 +# (fallocate only gets two lines because there is no 32-bit variant.) +int fallocate64:fallocate(int, int, off64_t, off64_t) arm,mips,x86 +int fallocate|fallocate64(int, int, off_t, off_t) arm64,mips64,x86_64 + +# posix_fadvise64 is awkward: arm has shuffled arguments, +# the POSIX functions don't set errno, and no architecture has posix_fadvise. +int __arm_fadvise64_64:arm_fadvise64_64(int, int, off64_t, off64_t) arm +int __fadvise64:fadvise64_64(int, off64_t, off64_t, int) x86 +int __fadvise64:fadvise64(int, off64_t, off64_t, int) arm64,mips,mips64,x86_64 + +int __fstatfs64:fstatfs64(int, size_t, struct statfs*) arm,mips,x86 +int __fstatfs:fstatfs(int, struct statfs*) arm64,mips64,x86_64 +int __statfs64:statfs64(const char*, size_t, struct statfs*) arm,mips,x86 +int __statfs:statfs(const char*, struct statfs*) arm64,mips64,x86_64 + +int fstat64|fstat:fstat64(int, struct stat*) arm,mips,x86 +int fstat64|fstat:fstat(int, struct stat*) arm64,x86_64 + +# file system +int chdir(const char*) all +int mount(const char*, const char*, const char*, unsigned long, const void*) all +int umount2(const char*, int) all +int __getcwd:getcwd(char* buf, size_t size) all +int fchdir(int) all +int setxattr(const char*, const char*, const void*, size_t, int) all +int lsetxattr(const char*, const char*, const void*, size_t, int) all +ssize_t getxattr(const char*, const char*, void*, size_t) all +ssize_t lgetxattr(const char*, const char*, void*, size_t) all +ssize_t listxattr(const char*, char*, size_t) all +ssize_t llistxattr(const char*, char*, size_t) all +int removexattr(const char*, const char*) all +int lremovexattr(const char*, const char*) all +int swapon(const char*, int) all +int swapoff(const char*) all + +# time +int settimeofday(const struct timeval*, const struct timezone*) all +clock_t times(struct tms*) all +int nanosleep(const struct timespec*, struct timespec*) all +int clock_settime(clockid_t, const struct timespec*) all +int clock_getres(clockid_t, struct timespec*) all +int ___clock_nanosleep:clock_nanosleep(clockid_t, int, const struct timespec*, struct timespec*) all +int getitimer(int, const struct itimerval*) all +int setitimer(int, const struct itimerval*, struct itimerval*) all +int __timer_create:timer_create(clockid_t clockid, struct sigevent* evp, __kernel_timer_t* timerid) all +int __timer_settime:timer_settime(__kernel_timer_t, int, const struct itimerspec*, struct itimerspec*) all +int __timer_gettime:timer_gettime(__kernel_timer_t, struct itimerspec*) all +int __timer_getoverrun:timer_getoverrun(__kernel_timer_t) all +int __timer_delete:timer_delete(__kernel_timer_t) all +int timerfd_create(clockid_t, int) all +int timerfd_settime(int, int, const struct itimerspec*, struct itimerspec*) all +int timerfd_gettime(int, struct itimerspec*) all +int adjtimex(struct timex*) all +int clock_adjtime(clockid_t, struct timex*) all + +# signals +int __sigaction:sigaction(int, const struct sigaction*, struct sigaction*) arm,mips,x86 +int __rt_sigaction:rt_sigaction(int, const struct sigaction*, struct sigaction*, size_t) all +int __rt_sigpending:rt_sigpending(sigset_t*, size_t) all +int __rt_sigprocmask:rt_sigprocmask(int, const sigset_t*, sigset_t*, size_t) all +int __rt_sigsuspend:rt_sigsuspend(const sigset_t*, size_t) all +int __rt_sigtimedwait:rt_sigtimedwait(const sigset_t*, siginfo_t*, const timespec*, size_t) all +int ___rt_sigqueueinfo:rt_sigqueueinfo(pid_t, int, siginfo_t*) all +int __signalfd4:signalfd4(int, const sigset_t*, size_t, int) all + +# sockets +int __socket:socket(int, int, int) arm,arm64,mips,mips64,x86_64 +int socketpair(int, int, int, int*) arm,arm64,mips,mips64,x86_64 +int bind(int, struct sockaddr*, socklen_t) arm,arm64,mips,mips64,x86_64 +int __connect:connect(int, struct sockaddr*, socklen_t) arm,arm64,mips,mips64,x86_64 +int listen(int, int) arm,arm64,mips,mips64,x86_64 +int __accept4:accept4(int, struct sockaddr*, socklen_t*, int) arm,arm64,mips,mips64,x86_64 +int getsockname(int, struct sockaddr*, socklen_t*) arm,arm64,mips,mips64,x86_64 +int getpeername(int, struct sockaddr*, socklen_t*) arm,arm64,mips,mips64,x86_64 +int sendto(int, const void*, size_t, int, const struct sockaddr*, socklen_t) arm,arm64,mips,mips64,x86_64 +int recvfrom(int, void*, size_t, unsigned int, struct sockaddr*, socklen_t*) arm,arm64,mips,mips64,x86_64 +int shutdown(int, int) arm,arm64,mips,mips64,x86_64 +int setsockopt(int, int, int, const void*, socklen_t) arm,arm64,mips,mips64,x86_64 +int getsockopt(int, int, int, void*, socklen_t*) arm,arm64,mips,mips64,x86_64 +ssize_t recvmsg(int, struct msghdr*, unsigned int) arm,arm64,mips,mips64,x86_64 +ssize_t sendmsg(int, const struct msghdr*, unsigned int) arm,arm64,mips,mips64,x86_64 +int recvmmsg(int, struct mmsghdr*, unsigned int, int, const struct timespec*) arm,arm64,mips,mips64,x86_64 +int sendmmsg(int, struct mmsghdr*, unsigned int, int) arm,arm64,mips,mips64,x86_64 + +# sockets for x86. These are done as an "indexed" call to socketcall syscall. +int __socket:socketcall:1(int, int, int) x86 +int bind:socketcall:2(int, struct sockaddr*, int) x86 +int __connect:socketcall:3(int, struct sockaddr*, socklen_t) x86 +int listen:socketcall:4(int, int) x86 +int getsockname:socketcall:6(int, struct sockaddr*, socklen_t*) x86 +int getpeername:socketcall:7(int, struct sockaddr*, socklen_t*) x86 +int socketpair:socketcall:8(int, int, int, int*) x86 +int sendto:socketcall:11(int, const void*, size_t, int, const struct sockaddr*, socklen_t) x86 +int recvfrom:socketcall:12(int, void*, size_t, unsigned int, struct sockaddr*, socklen_t*) x86 +int shutdown:socketcall:13(int, int) x86 +int setsockopt:socketcall:14(int, int, int, const void*, socklen_t) x86 +int getsockopt:socketcall:15(int, int, int, void*, socklen_t*) x86 +int sendmsg:socketcall:16(int, const struct msghdr*, unsigned int) x86 +int recvmsg:socketcall:17(int, struct msghdr*, unsigned int) x86 +int __accept4:socketcall:18(int, struct sockaddr*, socklen_t*, int) x86 +int recvmmsg:socketcall:19(int, struct mmsghdr*, unsigned int, int, const struct timespec*) x86 +int sendmmsg:socketcall:20(int, struct mmsghdr*, unsigned int, int) x86 + +# scheduler & real-time +int sched_setscheduler(pid_t pid, int policy, const struct sched_param* param) all +int sched_getscheduler(pid_t pid) all +int sched_yield(void) all +int sched_setparam(pid_t pid, const struct sched_param* param) all +int sched_getparam(pid_t pid, struct sched_param* param) all +int sched_get_priority_max(int policy) all +int sched_get_priority_min(int policy) all +int sched_rr_get_interval(pid_t pid, struct timespec* interval) all +int sched_setaffinity(pid_t pid, size_t setsize, const cpu_set_t* set) all +int setns(int, int) all +int unshare(int) all +int __sched_getaffinity:sched_getaffinity(pid_t pid, size_t setsize, cpu_set_t* set) all +int __getcpu:getcpu(unsigned*, unsigned*, void*) all + +# other +int uname(struct utsname*) all +mode_t umask(mode_t) all +int __reboot:reboot(int, int, int, void*) all +int init_module(void*, unsigned long, const char*) all +int delete_module(const char*, unsigned int) all +int klogctl:syslog(int, char*, int) all +int sysinfo(struct sysinfo*) all +int personality(unsigned long) all + +ssize_t tee(int, int, size_t, unsigned int) all +ssize_t splice(int, off64_t*, int, off64_t*, size_t, unsigned int) all +ssize_t vmsplice(int, const struct iovec*, size_t, unsigned int) all + +int epoll_create1(int) all +int epoll_ctl(int, int op, int, struct epoll_event*) all +int __epoll_pwait:epoll_pwait(int, struct epoll_event*, int, int, const sigset_t*, size_t) all + +int eventfd:eventfd2(unsigned int, int) all + +void _exit|_Exit:exit_group(int) all +void __exit:exit(int) all + +int inotify_init1(int) all +int inotify_add_watch(int, const char*, unsigned int) all +int inotify_rm_watch(int, unsigned int) all + +int __pselect6:pselect6(int, fd_set*, fd_set*, fd_set*, timespec*, void*) all +int __ppoll:ppoll(pollfd*, unsigned int, timespec*, const sigset_t*, size_t) all + +ssize_t process_vm_readv(pid_t, const struct iovec*, unsigned long, const struct iovec*, unsigned long, unsigned long) all +ssize_t process_vm_writev(pid_t, const struct iovec*, unsigned long, const struct iovec*, unsigned long, unsigned long) all + +int quotactl(int, const char*, int, char*) all + +int __set_tid_address:set_tid_address(int*) all + +int setfsgid(gid_t) all +int setfsuid(uid_t) all + +int setdomainname(const char*, size_t) all +int sethostname(const char*, size_t) all + +int __sync_file_range:sync_file_range(int, off64_t, off64_t, unsigned int) arm64,mips,mips64,x86,x86_64 +int __sync_file_range2:sync_file_range2(int, unsigned int, off64_t, off64_t) arm + +pid_t wait4(pid_t, int*, int, struct rusage*) all +int __waitid:waitid(int, pid_t, struct siginfo_t*, int, void*) all + +# ARM-specific +int __set_tls:__ARM_NR_set_tls(void*) arm +int cacheflush:__ARM_NR_cacheflush(long start, long end, long flags) arm + +# MIPS-specific +int _flush_cache:cacheflush(char* addr, const int nbytes, const int op) mips +int __set_tls:set_thread_area(void*) mips,mips64 + +# x86-specific +int __set_thread_area:set_thread_area(void*) x86 + +# vdso stuff. +int clock_gettime(clockid_t, timespec*) mips,mips64 +int __clock_gettime:clock_gettime(clockid_t, timespec*) arm,arm64,x86,x86_64 +int gettimeofday(timeval*, timezone*) mips,mips64 +int __gettimeofday:gettimeofday(timeval*, timezone*) arm,arm64,x86,x86_64
diff --git a/libc/arch-arm/bionic/__aeabi.c b/libc/arch-arm/bionic/__aeabi.c new file mode 100644 index 0000000..1620d45 --- /dev/null +++ b/libc/arch-arm/bionic/__aeabi.c
@@ -0,0 +1,185 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if defined(__clang__) +// clang interprets -fno-builtin more loosely than you might expect, +// and thinks it's okay to still substitute builtins as long as they're +// named __aeabi_* rather than __builtin_*, which causes infinite +// recursion if we have the fortified memcpy visible in this file. +#undef _FORTIFY_SOURCE +#endif + +#include <stddef.h> +#include <string.h> + +extern int __cxa_atexit(void (*)(void*), void*, void*); + +// All of these are weak symbols to avoid multiple definition errors when +// linking with libstdc++-v3 or compiler-rt. + +/* The "C++ ABI for ARM" document states that static C++ constructors, + * which are called from the .init_array, should manually call + * __aeabi_atexit() to register static destructors explicitly. + * + * Note that 'dso_handle' is the address of a magic linker-generate + * variable from the shared object that contains the constructor/destructor + */ + +int __attribute__((weak)) +__aeabi_atexit_impl(void *object, void (*destructor) (void *), void *dso_handle) { + return __cxa_atexit(destructor, object, dso_handle); +} + +int __attribute__((weak)) +__aeabi_atexit_impl2(void *object, void (*destructor) (void *), void *dso_handle) { + return __cxa_atexit(destructor, object, dso_handle); +} + + +void __attribute__((weak)) __aeabi_memcpy8_impl(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memcpy4_impl(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memcpy_impl(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memcpy8_impl2(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memcpy4_impl2(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memcpy_impl2(void *dest, const void *src, size_t n) { + memcpy(dest, src, n); +} + + +void __attribute__((weak)) __aeabi_memmove8_impl(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memmove4_impl(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memmove_impl(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memmove8_impl2(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memmove4_impl2(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +void __attribute__((weak)) __aeabi_memmove_impl2(void *dest, const void *src, size_t n) { + memmove(dest, src, n); +} + +/* + * __aeabi_memset has the order of its second and third arguments reversed. + * This allows __aeabi_memclr to tail-call __aeabi_memset + */ + +void __attribute__((weak)) __aeabi_memset8_impl(void *dest, size_t n, int c) { + memset(dest, c, n); +} + +void __attribute__((weak)) __aeabi_memset4_impl(void *dest, size_t n, int c) { + memset(dest, c, n); +} + +void __attribute__((weak)) __aeabi_memset_impl(void *dest, size_t n, int c) { + memset(dest, c, n); +} + +void __attribute__((weak)) __aeabi_memset8_impl2(void *dest, size_t n, int c) { + memset(dest, c, n); +} + +void __attribute__((weak)) __aeabi_memset4_impl2(void *dest, size_t n, int c) { + memset(dest, c, n); +} + +void __attribute__((weak)) __aeabi_memset_impl2(void *dest, size_t n, int c) { + memset(dest, c, n); +} + + +void __attribute__((weak)) __aeabi_memclr8_impl(void *dest, size_t n) { + __aeabi_memset8_impl(dest, n, 0); +} + +void __attribute__((weak)) __aeabi_memclr4_impl(void *dest, size_t n) { + __aeabi_memset4_impl(dest, n, 0); +} + +void __attribute__((weak)) __aeabi_memclr_impl(void *dest, size_t n) { + __aeabi_memset_impl(dest, n, 0); +} + +void __attribute__((weak)) __aeabi_memclr8_impl2(void *dest, size_t n) { + __aeabi_memset8_impl(dest, n, 0); +} + +void __attribute__((weak)) __aeabi_memclr4_impl2(void *dest, size_t n) { + __aeabi_memset4_impl(dest, n, 0); +} + +void __attribute__((weak)) __aeabi_memclr_impl2(void *dest, size_t n) { + __aeabi_memset_impl(dest, n, 0); +} + +#define __AEABI_SYMVERS(fn_name) \ +__asm__(".symver " #fn_name "_impl, " #fn_name "@@LIBC_N"); \ +__asm__(".symver " #fn_name "_impl2, " #fn_name "@LIBC_PRIVATE") + +__AEABI_SYMVERS(__aeabi_atexit); +__AEABI_SYMVERS(__aeabi_memcpy8); +__AEABI_SYMVERS(__aeabi_memcpy4); +__AEABI_SYMVERS(__aeabi_memcpy); +__AEABI_SYMVERS(__aeabi_memmove8); +__AEABI_SYMVERS(__aeabi_memmove4); +__AEABI_SYMVERS(__aeabi_memmove); +__AEABI_SYMVERS(__aeabi_memset8); +__AEABI_SYMVERS(__aeabi_memset4); +__AEABI_SYMVERS(__aeabi_memset); +__AEABI_SYMVERS(__aeabi_memclr8); +__AEABI_SYMVERS(__aeabi_memclr4); +__AEABI_SYMVERS(__aeabi_memclr); + +#undef __AEABI_SYMVERS
diff --git a/libc/arch-arm/bionic/__bionic_clone.S b/libc/arch-arm/bionic/__bionic_clone.S new file mode 100644 index 0000000..b771357 --- /dev/null +++ b/libc/arch-arm/bionic/__bionic_clone.S
@@ -0,0 +1,70 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); +ENTRY(__bionic_clone) + mov ip, sp + # save registers to parent stack + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + + # load extra parameters + ldmfd ip, {r4, r5, r6} + + # Push 'fn' and 'arg' onto the child stack. + stmdb r1!, {r5, r6} + + # Make the system call. + ldr r7, =__NR_clone + swi #0 + + # Are we the child? + movs r0, r0 + beq 1f + + # In the parent, reload saved registers then either return or set errno. + ldmfd sp!, {r4, r5, r6, r7} + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal + +1: # The child. + # Setting lr to 0 will make the unwinder stop at __start_thread + mov lr, #0 + # Call __start_thread with the 'fn' and 'arg' we stored on the child stack. + pop {r0, r1} + b __start_thread +END(__bionic_clone) +.hidden __bionic_clone
diff --git a/libc/arch-arm/bionic/__restore.S b/libc/arch-arm/bionic/__restore.S new file mode 100644 index 0000000..8c1e41d --- /dev/null +++ b/libc/arch-arm/bionic/__restore.S
@@ -0,0 +1,63 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// gdb is smart enough to unwind through signal frames with just the regular +// CFI information but libgcc and libunwind both need extra help. We do this +// by using .fnstart/.fnend and inserting a nop before both __restore and +// __restore_rt (but covered by the .fnstart/.fnend) so that although they're +// not inside the functions from objdump's point of view, an unwinder that +// blindly looks at the previous instruction (but is then smart enough to check +// the unwind information to find out where it landed) gets the right answer. +// Make sure not to have both DWARF and ARM unwind information, so only +// use the ARM unwind information. + +// We need to place .fnstart ourselves (but we may as well keep the free .fnend). +#undef __bionic_asm_custom_entry +#define __bionic_asm_custom_entry(f) + + .fnstart + .save {r0-r15} + .pad #32 + nop +ENTRY_PRIVATE_NO_DWARF(__restore) + // This function must have exactly this instruction sequence. + mov r7, #__NR_sigreturn + swi #0 +END_NO_DWARF(__restore) + + .fnstart + .save {r0-r15} + .pad #160 + nop +ENTRY_PRIVATE_NO_DWARF(__restore_rt) + // This function must have exactly this instruction sequence. + mov r7, #__NR_rt_sigreturn + swi #0 +END_NO_DWARF(__restore_rt)
diff --git a/libc/arch-arm/bionic/_exit_with_stack_teardown.S b/libc/arch-arm/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..1a67fed --- /dev/null +++ b/libc/arch-arm/bionic/_exit_with_stack_teardown.S
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + ldr r7, =__NR_munmap + swi #0 + // If munmap failed, we ignore the failure and exit anyway. + + mov r0, #0 + ldr r7, =__NR_exit + swi #0 + // The exit syscall does not return. +END(_exit_with_stack_teardown)
diff --git a/libc/arch-arm/bionic/abort_arm.S b/libc/arch-arm/bionic/abort_arm.S new file mode 100644 index 0000000..1039502 --- /dev/null +++ b/libc/arch-arm/bionic/abort_arm.S
@@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +/* + * Coding the abort function in assembly so that registers are guaranteed to + * be preserved properly regardless of GCC's assumption on the "noreturn" + * attribute. When the registers are not properly preserved we won't be able + * to unwind the stack all the way to the bottom to fully reveal the call + * sequence when the crash happens. + */ +ENTRY(abort) + stmfd sp!, {r3, r14} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r3, 0 + .cfi_rel_offset r14, 4 + bl __libc_android_abort +END(abort)
diff --git a/libc/arch-arm/bionic/atexit_legacy.c b/libc/arch-arm/bionic/atexit_legacy.c new file mode 100644 index 0000000..c0d704d --- /dev/null +++ b/libc/arch-arm/bionic/atexit_legacy.c
@@ -0,0 +1,60 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/types.h> +#include <stdio.h> + +#include "private/libc_logging.h" + +/* + * This source file should only be included by libc.so, its purpose is + * to support legacy ARM binaries by exporting a publicly visible + * implementation of atexit(). + */ + +extern int __cxa_atexit(void (*func)(void *), void *arg, void *dso); + +/* + * Register a function to be performed at exit. + */ +int +atexit(void (*func)(void)) +{ + /* + * Exit functions queued by this version of atexit will not be called + * on dlclose(), and when they are called (at program exit), the + * calling library may have been dlclose()'d, causing the program to + * crash. + */ + static char const warning[] = "WARNING: generic atexit() called from legacy shared library\n"; + + __libc_format_log(ANDROID_LOG_WARN, "libc", warning); + fprintf(stderr, warning); + + return (__cxa_atexit((void (*)(void *))func, NULL, NULL)); +}
diff --git a/libc/arch-arm/bionic/atomics_arm.c b/libc/arch-arm/bionic/atomics_arm.c new file mode 100644 index 0000000..d69eaff --- /dev/null +++ b/libc/arch-arm/bionic/atomics_arm.c
@@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +/* The purpose of this file is to export a small set of atomic-related + * functions from the C library, to ensure binary ABI compatibility for + * the NDK. + * + * These functions were initially exposed by the NDK through <sys/atomics.h>, + * which was unfortunate because their implementation didn't provide any + * memory barriers at all. + * + * This wasn't a problem for the platform code that used them, because it + * used explicit barrier instructions around them. On the other hand, it means + * that any NDK-generated machine code that linked against them would not + * perform correctly when running on multi-core devices. + * + * To fix this, the platform code was first modified to not use any of these + * functions (everything is now inlined through assembly statements, see + * libc/private/bionic_arm_inline.h and the headers it includes. + * + * The functions here are thus only for the benefit of NDK applications, + * and now includes full memory barriers to prevent any random memory ordering + * issue from cropping. + * + * Note that we also provide an updated <sys/atomics.h> header that defines + * always_inlined versions of the functions that use the GCC builtin + * intrinsics to perform the same thing. + * + * NOTE: There is no need for a similar file for non-ARM platforms. + */ + +/* DO NOT INCLUDE <sys/atomics.h> HERE ! */ + +int +__atomic_cmpxchg(int old, int _new, volatile int *ptr) +{ + /* We must return 0 on success */ + return __sync_val_compare_and_swap(ptr, old, _new) != old; +} + +int +__atomic_swap(int _new, volatile int *ptr) +{ + int prev; + do { + prev = *ptr; + } while (__sync_val_compare_and_swap(ptr, prev, _new) != prev); + return prev; +} + +int +__atomic_dec(volatile int *ptr) +{ + return __sync_fetch_and_sub (ptr, 1); +} + +int +__atomic_inc(volatile int *ptr) +{ + return __sync_fetch_and_add (ptr, 1); +}
diff --git a/libc/arch-arm/bionic/exidx_dynamic.c b/libc/arch-arm/bionic/exidx_dynamic.c new file mode 100644 index 0000000..60ac8af --- /dev/null +++ b/libc/arch-arm/bionic/exidx_dynamic.c
@@ -0,0 +1,49 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <link.h> + +/* For a given PC, find the .so that it belongs to. + * Returns the base address of the .ARM.exidx section + * for that .so, and the number of 8-byte entries + * in that section (via *pcount). + * + * libgcc declares __gnu_Unwind_Find_exidx() as a weak symbol, with + * the expectation that libc will define it and call through to + * a differently-named function in the dynamic linker. + */ +_Unwind_Ptr __gnu_Unwind_Find_exidx_impl(_Unwind_Ptr pc, int *pcount) { + return dl_unwind_find_exidx(pc, pcount); +} + +_Unwind_Ptr __gnu_Unwind_Find_exidx_impl2(_Unwind_Ptr pc, int *pcount) { + return dl_unwind_find_exidx(pc, pcount); +} + +__asm__(".symver __gnu_Unwind_Find_exidx_impl,__gnu_Unwind_Find_exidx@LIBC_PRIVATE"); +__asm__(".symver __gnu_Unwind_Find_exidx_impl2,__gnu_Unwind_Find_exidx@@LIBC_N");
diff --git a/libc/arch-arm/bionic/exidx_static.c b/libc/arch-arm/bionic/exidx_static.c new file mode 100644 index 0000000..72c0a5b --- /dev/null +++ b/libc/arch-arm/bionic/exidx_static.c
@@ -0,0 +1,46 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <link.h> + +/* Find the .ARM.exidx section (which in the case of a static executable + * can be identified through its start and end symbols), and return its + * beginning and numbe of entries to the caller. Note that for static + * executables we do not need to use the value of the PC to find the + * EXIDX section. + */ + +extern unsigned __exidx_end; +extern unsigned __exidx_start; + +_Unwind_Ptr __gnu_Unwind_Find_exidx(_Unwind_Ptr pc __attribute__((unused)), + int *pcount) +{ + *pcount = (__exidx_end-__exidx_start)/8; + return (_Unwind_Ptr)__exidx_start; +}
diff --git a/libc/arch-arm/bionic/libgcc_compat.c b/libc/arch-arm/bionic/libgcc_compat.c new file mode 100644 index 0000000..abd1422 --- /dev/null +++ b/libc/arch-arm/bionic/libgcc_compat.c
@@ -0,0 +1,185 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern char __adddf3; +extern char __addsf3; +extern char __aeabi_cdcmpeq; +extern char __aeabi_cdcmple; +extern char __aeabi_cdrcmple; +extern char __aeabi_d2f; +extern char __aeabi_d2iz; +extern char __aeabi_dadd; +extern char __aeabi_dcmpeq; +extern char __aeabi_dcmpge; +extern char __aeabi_dcmpgt; +extern char __aeabi_dcmple; +extern char __aeabi_dcmplt; +extern char __aeabi_dcmpun; +extern char __aeabi_ddiv; +extern char __aeabi_dmul; +extern char __aeabi_drsub; +extern char __aeabi_dsub; +extern char __aeabi_f2d; +extern char __aeabi_f2iz; +extern char __aeabi_f2uiz; +extern char __aeabi_fadd; +extern char __aeabi_fcmpun; +extern char __aeabi_fdiv; +extern char __aeabi_fmul; +extern char __aeabi_frsub; +extern char __aeabi_fsub; +extern char __aeabi_i2d; +extern char __aeabi_i2f; +extern char __aeabi_idiv; +extern char __aeabi_idivmod; +extern char __aeabi_l2d; +extern char __aeabi_l2f; +extern char __aeabi_lasr; +extern char __aeabi_ldivmod; +extern char __aeabi_llsl; +extern char __aeabi_llsr; +extern char __aeabi_lmul; +extern char __aeabi_ui2d; +extern char __aeabi_ui2f; +extern char __aeabi_uidiv; +extern char __aeabi_uidivmod; +extern char __aeabi_ul2d; +extern char __aeabi_ul2f; +extern char __aeabi_uldivmod; +extern char __aeabi_unwind_cpp_pr0; +extern char __aeabi_unwind_cpp_pr1; +extern char __cmpdf2; +extern char __divdf3; +extern char __divsf3; +extern char __eqdf2; +extern char __extendsfdf2; +extern char __fixdfsi; +extern char __fixsfsi; +extern char __floatdidf; +extern char __floatdisf; +extern char __floatsidf; +extern char __floatsisf; +extern char __floatundidf; +extern char __floatundisf; +extern char __floatunsidf; +extern char __floatunsisf; +extern char __gedf2; +extern char __gtdf2; +extern char __ledf2; +extern char __ltdf2; +extern char __muldf3; +extern char __muldi3; +extern char __mulsf3; +extern char __nedf2; +extern char __popcount_tab; +extern char __popcountsi2; +extern char __subdf3; +extern char __subsf3; +extern char __truncdfsf2; +extern char __unorddf2; +extern char __unordsf2; + +void* __bionic_libgcc_compat_symbols[] = { + &__adddf3, + &__addsf3, + &__aeabi_cdcmpeq, + &__aeabi_cdcmple, + &__aeabi_cdrcmple, + &__aeabi_d2f, + &__aeabi_d2iz, + &__aeabi_dadd, + &__aeabi_dcmpeq, + &__aeabi_dcmpge, + &__aeabi_dcmpgt, + &__aeabi_dcmple, + &__aeabi_dcmplt, + &__aeabi_dcmpun, + &__aeabi_ddiv, + &__aeabi_dmul, + &__aeabi_drsub, + &__aeabi_dsub, + &__aeabi_f2d, + &__aeabi_f2iz, + &__aeabi_f2uiz, + &__aeabi_fadd, + &__aeabi_fcmpun, + &__aeabi_fdiv, + &__aeabi_fmul, + &__aeabi_frsub, + &__aeabi_fsub, + &__aeabi_i2d, + &__aeabi_i2f, + &__aeabi_idiv, + &__aeabi_idivmod, + &__aeabi_l2d, + &__aeabi_l2f, + &__aeabi_lasr, + &__aeabi_ldivmod, + &__aeabi_llsl, + &__aeabi_llsr, + &__aeabi_lmul, + &__aeabi_ui2d, + &__aeabi_ui2f, + &__aeabi_uidiv, + &__aeabi_uidivmod, + &__aeabi_ul2d, + &__aeabi_ul2f, + &__aeabi_uldivmod, + &__aeabi_unwind_cpp_pr0, + &__aeabi_unwind_cpp_pr1, + &__cmpdf2, + &__divdf3, + &__divsf3, + &__eqdf2, + &__extendsfdf2, + &__fixdfsi, + &__fixsfsi, + &__floatdidf, + &__floatdisf, + &__floatsidf, + &__floatsisf, + &__floatundidf, + &__floatundisf, + &__floatunsidf, + &__floatunsisf, + &__gedf2, + &__gtdf2, + &__ledf2, + &__ltdf2, + &__muldf3, + &__muldi3, + &__mulsf3, + &__nedf2, + &__popcount_tab, + &__popcountsi2, + &__subdf3, + &__subsf3, + &__truncdfsf2, + &__unorddf2, + &__unordsf2, +};
diff --git a/libc/arch-arm/bionic/popcount_tab.c b/libc/arch-arm/bionic/popcount_tab.c new file mode 100644 index 0000000..eb2faa9 --- /dev/null +++ b/libc/arch-arm/bionic/popcount_tab.c
@@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Export this to maintain ABI compatibilty with libgcc, since compiler-rt +// doesn't use a table-driven implementation of __popcount. +const unsigned char __popcount_tab[256] = { + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, + 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, + 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, + 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, + 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, + 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, + 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, + 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, + 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 +};
diff --git a/libc/arch-arm/bionic/setjmp.S b/libc/arch-arm/bionic/setjmp.S new file mode 100644 index 0000000..91d158a --- /dev/null +++ b/libc/arch-arm/bionic/setjmp.S
@@ -0,0 +1,265 @@ +/* + * Copyright (c) 1997 Mark Brinicombe + * Copyright (c) 2010 Android Open Source Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// According to the ARM AAPCS document, we only need to save +// the following registers: +// +// Core r4-r11, sp, lr +// AAPCS 5.1.1: +// A subroutine must preserve the contents of the registers r4-r8, r10, r11 +// and SP (and r9 in PCS variants that designate r9 as v6). +// +// VFP d8-d15 +// AAPCS 5.1.2.1: +// Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine +// calls; registers s0-s15 (d0-d7, q0-q3) do not need to be preserved +// (and can be used for passing arguments or returning results in standard +// procedure-call variants). Registers d16-d31 (q8-q15), if present, do +// not need to be preserved. +// +// FPSCR saved because glibc does. + +// The internal structure of a jmp_buf is totally private. +// Current layout (changes from release to release): +// +// word name description +// 0 sigflag/cookie setjmp cookie in top 31 bits, signal mask flag in low bit +// 1 sigmask signal mask (not used with _setjmp / _longjmp) +// 2 float_base base of float registers (d8 to d15) +// 18 float_state floating-point status and control register +// 19 core_base base of core registers (r4-r11, r13-r14) +// 29 checksum checksum of all of the core registers, to give better error messages. +// 30 reserved reserved entries (room to grow) +// 64 +// +// NOTE: float_base must be at an even word index, since the +// FP registers will be loaded/stored with instructions +// that expect 8-byte alignment. + +#define _JB_SIGFLAG 0 +#define _JB_SIGMASK (_JB_SIGFLAG+1) +#define _JB_FLOAT_BASE (_JB_SIGMASK+1) +#define _JB_FLOAT_STATE (_JB_FLOAT_BASE + (15-8+1)*2) +#define _JB_CORE_BASE (_JB_FLOAT_STATE+1) +#define _JB_CHECKSUM (_JB_CORE_BASE+10) + +ENTRY(setjmp) + mov r1, #1 + b sigsetjmp +END(setjmp) + +ENTRY(_setjmp) + mov r1, #0 + b sigsetjmp +END(_setjmp) + +#define MANGLE_REGISTERS 1 +#define USE_CHECKSUM 1 + +.macro m_mangle_registers reg +#if MANGLE_REGISTERS + eor r4, r4, \reg + eor r5, r5, \reg + eor r6, r6, \reg + eor r7, r7, \reg + eor r8, r8, \reg + eor r9, r9, \reg + eor r10, r10, \reg + eor r11, r11, \reg + eor r13, r13, \reg + eor r14, r14, \reg +#endif +.endm + +.macro m_unmangle_registers reg + m_mangle_registers \reg +.endm + +.macro m_calculate_checksum dst, src, scratch + mov \dst, #0 + .irp i,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28 + ldr \scratch, [\src, #(\i * 4)] + eor \dst, \dst, \scratch + .endr +.endm + +// int sigsetjmp(sigjmp_buf env, int save_signal_mask); +ENTRY(sigsetjmp) + stmfd sp!, {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + mov r0, r1 + bl __bionic_setjmp_cookie_get + mov r1, r0 + + ldmfd sp, {r0} + + // Save the setjmp cookie for later. + bic r2, r1, #1 + stmfd sp!, {r2} + .cfi_adjust_cfa_offset 4 + + // Record the setjmp cookie and whether or not we're saving the signal mask. + str r1, [r0, #(_JB_SIGFLAG * 4)] + + // Do we need to save the signal mask? + tst r1, #1 + beq 1f + + // Align the stack. + sub sp, #4 + .cfi_adjust_cfa_offset 4 + + // Save the current signal mask. + add r2, r0, #(_JB_SIGMASK * 4) + mov r0, #2 // SIG_SETMASK + mov r1, #0 + bl sigprocmask + + // Unalign the stack. + add sp, #4 + .cfi_adjust_cfa_offset -4 + +1: + ldmfd sp!, {r2} + .cfi_adjust_cfa_offset -4 + ldmfd sp!, {r0, lr} + .cfi_adjust_cfa_offset -8 + .cfi_restore r0 + .cfi_restore lr + + // Save core registers. + add r1, r0, #(_JB_CORE_BASE * 4) + m_mangle_registers r2 + + // ARM deprecates using sp in the register list for stmia. + stmia r1, {r4-r11, lr} + str sp, [r1, #(9 * 4)] + m_unmangle_registers r2 + + // Save floating-point registers. + add r1, r0, #(_JB_FLOAT_BASE * 4) + vstmia r1, {d8-d15} + + // Save floating-point state. + fmrx r1, fpscr + str r1, [r0, #(_JB_FLOAT_STATE * 4)] + +#if USE_CHECKSUM + // Calculate the checksum. + m_calculate_checksum r12, r0, r2 + str r12, [r0, #(_JB_CHECKSUM * 4)] +#endif + + mov r0, #0 + bx lr +END(sigsetjmp) + +// void siglongjmp(sigjmp_buf env, int value); +ENTRY(siglongjmp) + stmfd sp!, {r0, r1, lr} + .cfi_def_cfa_offset 12 + .cfi_rel_offset r0, 0 + .cfi_rel_offset r1, 4 + .cfi_rel_offset lr, 8 + +#if USE_CHECKSUM + // Check the checksum before doing anything. + m_calculate_checksum r12, r0, r3 + ldr r2, [r0, #(_JB_CHECKSUM * 4)] + + teq r2, r12 + bne __bionic_setjmp_checksum_mismatch +#endif + + // Fetch the signal flag. + ldr r1, [r0, #(_JB_SIGFLAG * 4)] + + // Do we need to restore the signal mask? + ands r1, r1, #1 + beq 1f + + // Restore the signal mask. + ldr r0, [r0, #(_JB_SIGMASK * 4)] + bl sigsetmask + +1: + ldmfd sp!, {r0, r1, lr} + .cfi_adjust_cfa_offset -12 + .cfi_restore r0 + .cfi_restore r1 + .cfi_restore lr + + // Restore floating-point registers. + add r2, r0, #(_JB_FLOAT_BASE * 4) + vldmia r2, {d8-d15} + + // Restore floating-point state. + ldr r2, [r0, #(_JB_FLOAT_STATE * 4)] + fmxr fpscr, r2 + + // Load the cookie. + ldr r3, [r0, #(_JB_SIGFLAG * 4)] + bic r3, r3, #1 + + // Restore core registers. + add r2, r0, #(_JB_CORE_BASE * 4) + + // ARM deprecates using sp in the register list for ldmia. + ldmia r2, {r4-r11, lr} + ldr sp, [r2, #(9 * 4)] + m_unmangle_registers r3 + + // Save the return value/address and check the setjmp cookie. + stmfd sp!, {r1, lr} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset lr, 4 + mov r0, r3 + bl __bionic_setjmp_cookie_check + + // Restore return value/address. + ldmfd sp!, {r0, lr} + .cfi_adjust_cfa_offset -8 + .cfi_restore lr + + teq r0, #0 + moveq r0, #1 + bx lr +END(siglongjmp) + +ALIAS_SYMBOL(longjmp, siglongjmp) +ALIAS_SYMBOL(_longjmp, siglongjmp)
diff --git a/libc/arch-arm/bionic/syscall.S b/libc/arch-arm/bionic/syscall.S new file mode 100644 index 0000000..d0df379 --- /dev/null +++ b/libc/arch-arm/bionic/syscall.S
@@ -0,0 +1,51 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +ENTRY(syscall) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + mov r7, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + ldmfd ip, {r3, r4, r5, r6} + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(syscall)
diff --git a/libc/arch-arm/bionic/vfork.S b/libc/arch-arm/bionic/vfork.S new file mode 100644 index 0000000..1b7cbad --- /dev/null +++ b/libc/arch-arm/bionic/vfork.S
@@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +ENTRY(vfork) + // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0 + mrc p15, 0, r3, c13, c0, 3 + ldr r3, [r3, #4] + mov r0, #0 + str r0, [r3, #12] + + mov ip, r7 + ldr r7, =__NR_vfork + swi #0 + mov r7, ip + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(vfork)
diff --git a/libc/arch-arm/cortex-a15/bionic/__strcat_chk.S b/libc/arch-arm/cortex-a15/bionic/__strcat_chk.S new file mode 100644 index 0000000..3692f04 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/__strcat_chk.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "memcpy_base.S" + +#include "__strcat_chk_common.S"
diff --git a/libc/arch-arm/cortex-a15/bionic/__strcat_chk_common.S b/libc/arch-arm/cortex-a15/bionic/__strcat_chk_common.S new file mode 100644 index 0000000..a610dd5 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/__strcat_chk_common.S
@@ -0,0 +1,199 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of src string, then get the source of the dst string. +// Check that the two lengths together don't exceed the threshold, then +// do a memcpy of the data. +ENTRY(__strcat_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + push {r4, r5} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + + mov lr, r2 + + // Save the dst register to r5 + mov r5, r0 + + // Zero out r4 + eor r4, r4, r4 + + // r1 contains the address of the string to count. +.L_strlen_start: + mov r0, r1 + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r1], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r1, r0 + sub r3, r3, #1 + b .L_finish + +.L_zero_in_first_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_finish + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_finish + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_finish + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_finish + +.L_zero_in_second_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_finish + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_finish + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_finish + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_finish: + cmp r4, #0 + bne .L_strlen_done + + // Time to get the dst string length. + mov r1, r5 + + // Save the original source address to r5. + mov r5, r0 + + // Save the current length (adding 1 for the terminator). + add r4, r3, #1 + b .L_strlen_start + + // r0 holds the pointer to the dst string. + // r3 holds the dst string length. + // r4 holds the src string length + 1. +.L_strlen_done: + add r2, r3, r4 + cmp r2, lr + itt hi + movhi r0, lr + bhi __strcat_chk_fail + + // Set up the registers for the memcpy code. + mov r1, r5 + pld [r1, #64] + mov r2, r4 + add r0, r0, r3 + pop {r4, r5} + .cfi_adjust_cfa_offset -8 + .cfi_restore r4 + .cfi_restore r5 + +#include MEMCPY_BASE + + // Undo the above cfi directives + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 +END(__strcat_chk)
diff --git a/libc/arch-arm/cortex-a15/bionic/__strcpy_chk.S b/libc/arch-arm/cortex-a15/bionic/__strcpy_chk.S new file mode 100644 index 0000000..d8cb3d9 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/__strcpy_chk.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "memcpy_base.S" + +#include "__strcpy_chk_common.S"
diff --git a/libc/arch-arm/cortex-a15/bionic/__strcpy_chk_common.S b/libc/arch-arm/cortex-a15/bionic/__strcpy_chk_common.S new file mode 100644 index 0000000..377e720 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/__strcpy_chk_common.S
@@ -0,0 +1,161 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of the source string first, then do a memcpy of the data +// instead of a strcpy. +ENTRY(__strcpy_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + mov lr, r2 + mov r0, r1 + + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r0], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r0], #8 + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r0, r1 + sub r3, r3, #1 + b .L_check_size + +.L_zero_in_first_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_check_size + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_check_size + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_check_size + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_check_size + +.L_zero_in_second_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_check_size + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_check_size + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_check_size + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_check_size: + pld [r1, #0] + pld [r1, #64] + ldr r0, [sp] + + // Add 1 for copy length to get the string terminator. + add r2, r3, #1 + + cmp r2, lr + itt hi + movhi r0, r2 + bhi __strcpy_chk_fail + +#include MEMCPY_BASE + +END(__strcpy_chk)
diff --git a/libc/arch-arm/cortex-a15/bionic/memcpy.S b/libc/arch-arm/cortex-a15/bionic/memcpy.S new file mode 100644 index 0000000..537f3de --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/memcpy.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "memcpy_base.S" + +#include "memcpy_common.S"
diff --git a/libc/arch-arm/cortex-a15/bionic/memcpy_base.S b/libc/arch-arm/cortex-a15/bionic/memcpy_base.S new file mode 100644 index 0000000..aac737d --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/memcpy_base.S
@@ -0,0 +1,334 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +.L_memcpy_base: + // Assumes that n >= 0, and dst, src are valid pointers. + // For any sizes less than 832 use the neon code that doesn't + // care about the src alignment. This avoids any checks + // for src alignment, and offers the best improvement since + // smaller sized copies are dominated by the overhead of + // the pre and post main loop. + // For larger copies, if src and dst cannot both be aligned to + // word boundaries, use the neon code. + // For all other copies, align dst to a double word boundary + // and copy using LDRD/STRD instructions. + + cmp r2, #16 + blo .L_copy_less_than_16_unknown_align + + // TODO: The aligned copy code is extremely slow copying some large + // buffers so always go through the unaligned path for now. + //cmp r2, #832 + //bge .L_check_alignment + +.L_copy_unknown_alignment: + // Unknown alignment of src and dst. + // Assumes that the first few bytes have already been prefetched. + + // Align destination to 128 bits. The mainloop store instructions + // require this alignment or they will throw an exception. + rsb r3, r0, #0 + ands r3, r3, #0xF + beq 2f + + // Copy up to 15 bytes (count in r3). + sub r2, r2, r3 + movs ip, r3, lsl #31 + + itt mi + ldrbmi lr, [r1], #1 + strbmi lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1], #1 + strbcs ip, [r0], #1 + strbcs lr, [r0], #1 + + movs ip, r3, lsl #29 + bge 1f + // Copies 4 bytes, dst 32 bits aligned before, at least 64 bits after. + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]! +1: bcc 2f + // Copies 8 bytes, dst 64 bits aligned before, at least 128 bits after. + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0, :64]! + +2: // Make sure we have at least 64 bytes to copy. + subs r2, r2, #64 + blo 2f + +1: // The main loop copies 64 bytes at a time. + vld1.8 {d0 - d3}, [r1]! + vld1.8 {d4 - d7}, [r1]! + pld [r1, #(64*4)] + subs r2, r2, #64 + vst1.8 {d0 - d3}, [r0, :128]! + vst1.8 {d4 - d7}, [r0, :128]! + bhs 1b + +2: // Fix-up the remaining count and make sure we have >= 32 bytes left. + adds r2, r2, #32 + blo 3f + + // 32 bytes. These cache lines were already preloaded. + vld1.8 {d0 - d3}, [r1]! + sub r2, r2, #32 + vst1.8 {d0 - d3}, [r0, :128]! +3: // Less than 32 left. + add r2, r2, #32 + tst r2, #0x10 + beq .L_copy_less_than_16_unknown_align + // Copies 16 bytes, destination 128 bits aligned. + vld1.8 {d0, d1}, [r1]! + vst1.8 {d0, d1}, [r0, :128]! + +.L_copy_less_than_16_unknown_align: + // Copy up to 15 bytes (count in r2). + movs ip, r2, lsl #29 + bcc 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0]! +1: bge 2f + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! + +2: // Copy 0 to 4 bytes. + lsls r2, r2, #31 + itt ne + ldrbne lr, [r1], #1 + strbne lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1] + strbcs ip, [r0], #1 + strbcs lr, [r0] + + pop {r0, pc} + +.L_check_alignment: + // If src and dst cannot both be aligned to a word boundary, + // use the unaligned copy version. + eor r3, r0, r1 + ands r3, r3, #0x3 + bne .L_copy_unknown_alignment + + // To try and improve performance, stack layout changed, + // i.e., not keeping the stack looking like users expect + // (highest numbered register at highest address). + strd r4, r5, [sp, #-8]! + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + strd r6, r7, [sp, #-8]! + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r6, 0 + .cfi_rel_offset r7, 4 + strd r8, r9, [sp, #-8]! + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r8, 0 + .cfi_rel_offset r9, 4 + + // Optimized for already aligned dst code. + ands ip, r0, #3 + bne .L_dst_not_word_aligned + +.L_word_aligned: + // Align the destination buffer to 8 bytes, to make sure double + // loads and stores don't cross a cache line boundary, + // as they are then more expensive even if the data is in the cache + // (require two load/store issue cycles instead of one). + // If only one of the buffers is not 8 bytes aligned, + // then it's more important to align dst than src, + // because there is more penalty for stores + // than loads that cross a cacheline boundary. + // This check and realignment are only done if there is >= 832 + // bytes to copy. + + // Dst is word aligned, but check if it is already double word aligned. + ands r3, r0, #4 + beq 1f + ldr r3, [r1], #4 + str r3, [r0], #4 + sub r2, #4 + +1: // Can only get here if > 64 bytes to copy, so don't do check r2. + sub r2, #64 + +2: // Every loop iteration copies 64 bytes. + .irp offset, #0, #8, #16, #24, #32 + ldrd r4, r5, [r1, \offset] + strd r4, r5, [r0, \offset] + .endr + + ldrd r4, r5, [r1, #40] + ldrd r6, r7, [r1, #48] + ldrd r8, r9, [r1, #56] + + // Keep the pld as far from the next load as possible. + // The amount to prefetch was determined experimentally using + // large sizes, and verifying the prefetch size does not affect + // the smaller copies too much. + // WARNING: If the ldrd and strd instructions get too far away + // from each other, performance suffers. Three loads + // in a row is the best tradeoff. + pld [r1, #(64*16)] + strd r4, r5, [r0, #40] + strd r6, r7, [r0, #48] + strd r8, r9, [r0, #56] + + add r0, r0, #64 + add r1, r1, #64 + subs r2, r2, #64 + bge 2b + + // Fix-up the remaining count and make sure we have >= 32 bytes left. + adds r2, r2, #32 + blo 4f + + // Copy 32 bytes. These cache lines were already preloaded. + .irp offset, #0, #8, #16, #24 + ldrd r4, r5, [r1, \offset] + strd r4, r5, [r0, \offset] + .endr + add r1, r1, #32 + add r0, r0, #32 + sub r2, r2, #32 +4: // Less than 32 left. + add r2, r2, #32 + tst r2, #0x10 + beq 5f + // Copy 16 bytes. + .irp offset, #0, #8 + ldrd r4, r5, [r1, \offset] + strd r4, r5, [r0, \offset] + .endr + add r1, r1, #16 + add r0, r0, #16 + +5: // Copy up to 15 bytes (count in r2). + movs ip, r2, lsl #29 + bcc 1f + // Copy 8 bytes. + ldrd r4, r5, [r1], #8 + strd r4, r5, [r0], #8 +1: bge 2f + // Copy 4 bytes. + ldr r4, [r1], #4 + str r4, [r0], #4 +2: // Copy 0 to 4 bytes. + lsls r2, r2, #31 + itt ne + ldrbne lr, [r1], #1 + strbne lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1] + strbcs ip, [r0], #1 + strbcs lr, [r0] + + // Restore registers: optimized pop {r0, pc} + ldrd r8, r9, [sp], #8 + .cfi_adjust_cfa_offset -8 + .cfi_restore r8 + .cfi_restore r9 + ldrd r6, r7, [sp], #8 + .cfi_adjust_cfa_offset -8 + .cfi_restore r6 + .cfi_restore r7 + ldrd r4, r5, [sp], #8 + .cfi_adjust_cfa_offset -8 + .cfi_restore r4 + .cfi_restore r5 + pop {r0, pc} + + // Put the cfi directives back for the below instructions. + .cfi_adjust_cfa_offset 24 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + .cfi_rel_offset r8, 16 + .cfi_rel_offset r9, 20 + +.L_dst_not_word_aligned: + // Align dst to word. + rsb ip, ip, #4 + cmp ip, #2 + + itt gt + ldrbgt lr, [r1], #1 + strbgt lr, [r0], #1 + + itt ge + ldrbge lr, [r1], #1 + strbge lr, [r0], #1 + + ldrb lr, [r1], #1 + strb lr, [r0], #1 + + sub r2, r2, ip + + // Src is guaranteed to be at least word aligned by this point. + b .L_word_aligned + + // Undo any cfi directives from above. + .cfi_adjust_cfa_offset -24 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + .cfi_restore r8 + .cfi_restore r9
diff --git a/libc/arch-arm/cortex-a15/bionic/memcpy_common.S b/libc/arch-arm/cortex-a15/bionic/memcpy_common.S new file mode 100644 index 0000000..4d1167f --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/memcpy_common.S
@@ -0,0 +1,82 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .text + .syntax unified + .fpu neon + +ENTRY(__memcpy_chk) + cmp r2, r3 + bls memcpy + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + bl __memcpy_chk_fail +END(__memcpy_chk) + +// Prototype: void *memcpy (void *dst, const void *src, size_t count). +ENTRY(memcpy) + pld [r1, #64] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + +#include MEMCPY_BASE +END(memcpy)
diff --git a/libc/arch-arm/cortex-a15/bionic/memset.S b/libc/arch-arm/cortex-a15/bionic/memset.S new file mode 100644 index 0000000..2542f3f --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/memset.S
@@ -0,0 +1,170 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + /* + * Optimized memset() for ARM. + * + * memset() returns its first argument. + */ + + .fpu neon + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + stmfd sp!, {r0} + .cfi_def_cfa_offset 4 + .cfi_rel_offset r0, 0 + + // The new algorithm is slower for copies < 16 so use the old + // neon code in that case. + cmp r2, #16 + blo .L_set_less_than_16_unknown_align + + // Use strd which requires an even and odd register so move the + // values so that: + // r0 and r1 contain the memset value + // r2 is the number of bytes to set + // r3 is the destination pointer + mov r3, r0 + + // Copy the byte value in every byte of r1. + mov r1, r1, lsl #24 + orr r1, r1, r1, lsr #8 + orr r1, r1, r1, lsr #16 + +.L_check_alignment: + // Align destination to a double word to avoid the strd crossing + // a cache line boundary. + ands ip, r3, #7 + bne .L_do_double_word_align + +.L_double_word_aligned: + mov r0, r1 + + subs r2, #64 + blo .L_set_less_than_64 + +1: // Main loop sets 64 bytes at a time. + .irp offset, #0, #8, #16, #24, #32, #40, #48, #56 + strd r0, r1, [r3, \offset] + .endr + + add r3, #64 + subs r2, #64 + bge 1b + +.L_set_less_than_64: + // Restore r2 to the count of bytes left to set. + add r2, #64 + lsls ip, r2, #27 + bcc .L_set_less_than_32 + // Set 32 bytes. + .irp offset, #0, #8, #16, #24 + strd r0, r1, [r3, \offset] + .endr + add r3, #32 + +.L_set_less_than_32: + bpl .L_set_less_than_16 + // Set 16 bytes. + .irp offset, #0, #8 + strd r0, r1, [r3, \offset] + .endr + add r3, #16 + +.L_set_less_than_16: + // Less than 16 bytes to set. + lsls ip, r2, #29 + bcc .L_set_less_than_8 + + // Set 8 bytes. + strd r0, r1, [r3], #8 + +.L_set_less_than_8: + bpl .L_set_less_than_4 + // Set 4 bytes + str r1, [r3], #4 + +.L_set_less_than_4: + lsls ip, r2, #31 + it ne + strbne r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3] + + ldmfd sp!, {r0} + bx lr + +.L_do_double_word_align: + rsb ip, ip, #8 + sub r2, r2, ip + movs r0, ip, lsl #31 + it mi + strbmi r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + + // Dst is at least word aligned by this point. + cmp ip, #4 + blo .L_double_word_aligned + str r1, [r3], #4 + b .L_double_word_aligned + +.L_set_less_than_16_unknown_align: + // Set up to 15 bytes. + vdup.8 d0, r1 + movs ip, r2, lsl #29 + bcc 1f + vst1.8 {d0}, [r0]! +1: bge 2f + vst1.32 {d0[0]}, [r0]! +2: movs ip, r2, lsl #31 + it mi + strbmi r1, [r0], #1 + itt cs + strbcs r1, [r0], #1 + strbcs r1, [r0], #1 + ldmfd sp!, {r0} + bx lr +END(memset)
diff --git a/libc/arch-arm/cortex-a15/bionic/stpcpy.S b/libc/arch-arm/cortex-a15/bionic/stpcpy.S new file mode 100644 index 0000000..740523b --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/stpcpy.S
@@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define STPCPY +#include "string_copy.S"
diff --git a/libc/arch-arm/cortex-a15/bionic/strcat.S b/libc/arch-arm/cortex-a15/bionic/strcat.S new file mode 100644 index 0000000..157cc9f --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/strcat.S
@@ -0,0 +1,575 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + + .macro m_push + push {r0, r4, r5, lr} + .endm // m_push + + .macro m_pop + pop {r0, r4, r5, pc} + .endm // m_pop + + .macro m_scan_byte + ldrb r3, [r0] + cbz r3, .L_strcat_r0_scan_done + add r0, #1 + .endm // m_scan_byte + + .macro m_copy_byte reg, cmd, label + ldrb \reg, [r1], #1 + strb \reg, [r0], #1 + \cmd \reg, \label + .endm // m_copy_byte + +ENTRY(strcat) + // Quick check to see if src is empty. + ldrb r2, [r1] + pld [r1, #0] + cbnz r2, .L_strcat_continue + bx lr + +.L_strcat_continue: + // To speed up really small dst strings, unroll checking the first 4 bytes. + m_push + m_scan_byte + m_scan_byte + m_scan_byte + m_scan_byte + + ands r3, r0, #7 + beq .L_strcat_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_strcat_align_to_32 + + ldrb r5, [r0] + cbz r5, .L_strcat_r0_scan_done + add r0, r0, #1 + +.L_strcat_align_to_32: + bcc .L_strcat_align_to_64 + + ldrb r2, [r0] + cbz r2, .L_strcat_r0_scan_done + add r0, r0, #1 + ldrb r4, [r0] + cbz r4, .L_strcat_r0_scan_done + add r0, r0, #1 + +.L_strcat_align_to_64: + tst r3, #4 + beq .L_strcat_mainloop + ldr r3, [r0], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcat_zero_in_second_register + b .L_strcat_mainloop + +.L_strcat_r0_scan_done: + // For short copies, hard-code checking the first 8 bytes since this + // new code doesn't win until after about 8 bytes. + m_copy_byte reg=r2, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r3, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r4, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r5, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r2, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r3, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r4, cmd=cbz, label=.L_strcpy_finish + m_copy_byte reg=r5, cmd=cbnz, label=.L_strcpy_continue + +.L_strcpy_finish: + m_pop + +.L_strcpy_continue: + ands r3, r0, #7 + beq .L_strcpy_check_src_align + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_strcpy_align_to_32 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + +.L_strcpy_align_to_32: + bcc .L_strcpy_align_to_64 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + +.L_strcpy_align_to_64: + tst r3, #4 + beq .L_strcpy_check_src_align + // Read one byte at a time since we don't know the src alignment + // and we don't want to read into a different page. + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .L_strcpy_complete + +.L_strcpy_check_src_align: + // At this point dst is aligned to a double word, check if src + // is also aligned to a double word. + ands r3, r1, #7 + bne .L_strcpy_unaligned_copy + + .p2align 2 +.L_strcpy_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_mainloop + +.L_strcpy_complete: + m_pop + +.L_strcpy_zero_in_first_register: + lsls lr, ip, #17 + bne .L_strcpy_copy1byte + bcs .L_strcpy_copy2bytes + lsls ip, ip, #1 + bne .L_strcpy_copy3bytes + +.L_strcpy_copy4bytes: + // Copy 4 bytes to the destiniation. + str r2, [r0] + m_pop + +.L_strcpy_copy1byte: + strb r2, [r0] + m_pop + +.L_strcpy_copy2bytes: + strh r2, [r0] + m_pop + +.L_strcpy_copy3bytes: + strh r2, [r0], #2 + lsr r2, #16 + strb r2, [r0] + m_pop + +.L_strcpy_zero_in_second_register: + lsls lr, ip, #17 + bne .L_strcpy_copy5bytes + bcs .L_strcpy_copy6bytes + lsls ip, ip, #1 + bne .L_strcpy_copy7bytes + + // Copy 8 bytes to the destination. + strd r2, r3, [r0] + m_pop + +.L_strcpy_copy5bytes: + str r2, [r0], #4 + strb r3, [r0] + m_pop + +.L_strcpy_copy6bytes: + str r2, [r0], #4 + strh r3, [r0] + m_pop + +.L_strcpy_copy7bytes: + str r2, [r0], #4 + strh r3, [r0], #2 + lsr r3, #16 + strb r3, [r0] + m_pop + +.L_strcpy_unaligned_copy: + // Dst is aligned to a double word, while src is at an unknown alignment. + // There are 7 different versions of the unaligned copy code + // to prevent overreading the src. The mainloop of every single version + // will store 64 bits per loop. The difference is how much of src can + // be read without potentially crossing a page boundary. + tbb [pc, r3] +.L_strcpy_unaligned_branchtable: + .byte 0 + .byte ((.L_strcpy_unalign7 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign6 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign5 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign4 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign3 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign2 - .L_strcpy_unaligned_branchtable)/2) + .byte ((.L_strcpy_unalign1 - .L_strcpy_unaligned_branchtable)/2) + + .p2align 2 + // Can read 7 bytes before possibly crossing a page. +.L_strcpy_unalign7: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + ldrb r3, [r1] + cbz r3, .L_strcpy_unalign7_copy5bytes + ldrb r4, [r1, #1] + cbz r4, .L_strcpy_unalign7_copy6bytes + ldrb r5, [r1, #2] + cbz r5, .L_strcpy_unalign7_copy7bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + lsrs ip, r3, #24 + strd r2, r3, [r0], #8 + beq .L_strcpy_unalign_return + b .L_strcpy_unalign7 + +.L_strcpy_unalign7_copy5bytes: + str r2, [r0], #4 + strb r3, [r0] +.L_strcpy_unalign_return: + m_pop + +.L_strcpy_unalign7_copy6bytes: + str r2, [r0], #4 + strb r3, [r0], #1 + strb r4, [r0], #1 + m_pop + +.L_strcpy_unalign7_copy7bytes: + str r2, [r0], #4 + strb r3, [r0], #1 + strb r4, [r0], #1 + strb r5, [r0], #1 + m_pop + + .p2align 2 + // Can read 6 bytes before possibly crossing a page. +.L_strcpy_unalign6: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .L_strcpy_unalign_copy5bytes + ldrb r5, [r1, #1] + cbz r5, .L_strcpy_unalign_copy6bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + tst r3, #0xff0000 + beq .L_strcpy_copy7bytes + lsrs ip, r3, #24 + strd r2, r3, [r0], #8 + beq .L_strcpy_unalign_return + b .L_strcpy_unalign6 + + .p2align 2 + // Can read 5 bytes before possibly crossing a page. +.L_strcpy_unalign5: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .L_strcpy_unalign_copy5bytes + + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_unalign5 + +.L_strcpy_unalign_copy5bytes: + str r2, [r0], #4 + strb r4, [r0] + m_pop + +.L_strcpy_unalign_copy6bytes: + str r2, [r0], #4 + strb r4, [r0], #1 + strb r5, [r0] + m_pop + + .p2align 2 + // Can read 4 bytes before possibly crossing a page. +.L_strcpy_unalign4: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + ldr r3, [r1], #4 + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_unalign4 + + .p2align 2 + // Can read 3 bytes before possibly crossing a page. +.L_strcpy_unalign3: + ldrb r2, [r1] + cbz r2, .L_strcpy_unalign3_copy1byte + ldrb r3, [r1, #1] + cbz r3, .L_strcpy_unalign3_copy2bytes + ldrb r4, [r1, #2] + cbz r4, .L_strcpy_unalign3_copy3bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + lsrs lr, r2, #24 + beq .L_strcpy_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_unalign3 + +.L_strcpy_unalign3_copy1byte: + strb r2, [r0] + m_pop + +.L_strcpy_unalign3_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_pop + +.L_strcpy_unalign3_copy3bytes: + strb r2, [r0], #1 + strb r3, [r0], #1 + strb r4, [r0] + m_pop + + .p2align 2 + // Can read 2 bytes before possibly crossing a page. +.L_strcpy_unalign2: + ldrb r2, [r1] + cbz r2, .L_strcpy_unalign_copy1byte + ldrb r4, [r1, #1] + cbz r4, .L_strcpy_unalign_copy2bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + pld [r1, #64] + + tst r2, #0xff0000 + beq .L_strcpy_copy3bytes + lsrs ip, r2, #24 + beq .L_strcpy_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_unalign2 + + .p2align 2 + // Can read 1 byte before possibly crossing a page. +.L_strcpy_unalign1: + ldrb r2, [r1] + cbz r2, .L_strcpy_unalign_copy1byte + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcpy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .L_strcpy_unalign1 + +.L_strcpy_unalign_copy1byte: + strb r2, [r0] + m_pop + +.L_strcpy_unalign_copy2bytes: + strb r2, [r0], #1 + strb r4, [r0] + m_pop + + .p2align 2 +.L_strcat_mainloop: + ldrd r2, r3, [r0], #8 + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_strcat_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_strcat_zero_in_second_register + b .L_strcat_mainloop + +.L_strcat_zero_in_first_register: + // Prefetch the src now, it's going to be used soon. + pld [r1, #0] + lsls lr, ip, #17 + bne .L_strcat_sub8 + bcs .L_strcat_sub7 + lsls ip, ip, #1 + bne .L_strcat_sub6 + + sub r0, r0, #5 + b .L_strcat_r0_scan_done + +.L_strcat_sub8: + sub r0, r0, #8 + b .L_strcat_r0_scan_done + +.L_strcat_sub7: + sub r0, r0, #7 + b .L_strcat_r0_scan_done + +.L_strcat_sub6: + sub r0, r0, #6 + b .L_strcat_r0_scan_done + +.L_strcat_zero_in_second_register: + // Prefetch the src now, it's going to be used soon. + pld [r1, #0] + lsls lr, ip, #17 + bne .L_strcat_sub4 + bcs .L_strcat_sub3 + lsls ip, ip, #1 + bne .L_strcat_sub2 + + sub r0, r0, #1 + b .L_strcat_r0_scan_done + +.L_strcat_sub4: + sub r0, r0, #4 + b .L_strcat_r0_scan_done + +.L_strcat_sub3: + sub r0, r0, #3 + b .L_strcat_r0_scan_done + +.L_strcat_sub2: + sub r0, r0, #2 + b .L_strcat_r0_scan_done +END(strcat)
diff --git a/libc/arch-arm/cortex-a15/bionic/strcmp.S b/libc/arch-arm/cortex-a15/bionic/strcmp.S new file mode 100644 index 0000000..5c8914b --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/strcmp.S
@@ -0,0 +1,375 @@ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +#ifdef __ARMEB__ +#define S2LOMEM lsl +#define S2LOMEMEQ lsleq +#define S2HIMEM lsr +#define MSB 0x000000ff +#define LSB 0xff000000 +#define BYTE0_OFFSET 24 +#define BYTE1_OFFSET 16 +#define BYTE2_OFFSET 8 +#define BYTE3_OFFSET 0 +#else /* not __ARMEB__ */ +#define S2LOMEM lsr +#define S2LOMEMEQ lsreq +#define S2HIMEM lsl +#define BYTE0_OFFSET 0 +#define BYTE1_OFFSET 8 +#define BYTE2_OFFSET 16 +#define BYTE3_OFFSET 24 +#define MSB 0xff000000 +#define LSB 0x000000ff +#endif /* not __ARMEB__ */ + +.syntax unified + +#if defined (__thumb__) + .thumb + .thumb_func +#endif + +ENTRY(strcmp) + /* Use LDRD whenever possible. */ + +/* The main thing to look out for when comparing large blocks is that + the loads do not cross a page boundary when loading past the index + of the byte with the first difference or the first string-terminator. + + For example, if the strings are identical and the string-terminator + is at index k, byte by byte comparison will not load beyond address + s1+k and s2+k; word by word comparison may load up to 3 bytes beyond + k; double word - up to 7 bytes. If the load of these bytes crosses + a page boundary, it might cause a memory fault (if the page is not mapped) + that would not have happened in byte by byte comparison. + + If an address is (double) word aligned, then a load of a (double) word + from that address will not cross a page boundary. + Therefore, the algorithm below considers word and double-word alignment + of strings separately. */ + +/* High-level description of the algorithm. + + * The fast path: if both strings are double-word aligned, + use LDRD to load two words from each string in every loop iteration. + * If the strings have the same offset from a word boundary, + use LDRB to load and compare byte by byte until + the first string is aligned to a word boundary (at most 3 bytes). + This is optimized for quick return on short unaligned strings. + * If the strings have the same offset from a double-word boundary, + use LDRD to load two words from each string in every loop iteration, as in the fast path. + * If the strings do not have the same offset from a double-word boundary, + load a word from the second string before the loop to initialize the queue. + Use LDRD to load two words from every string in every loop iteration. + Inside the loop, load the second word from the second string only after comparing + the first word, using the queued value, to guarantee safety across page boundaries. + * If the strings do not have the same offset from a word boundary, + use LDR and a shift queue. Order of loads and comparisons matters, + similarly to the previous case. + + * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value. + * The only difference between ARM and Thumb modes is the use of CBZ instruction. + * The only difference between big and little endian is the use of REV in little endian + to compute the return value, instead of MOV. +*/ + + .macro m_cbz reg label +#ifdef __thumb2__ + cbz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + beq \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbz */ + + .macro m_cbnz reg label +#ifdef __thumb2__ + cbnz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + bne \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbnz */ + + .macro init + /* Macro to save temporary registers and prepare magic values. */ + subs sp, sp, #16 + .cfi_def_cfa_offset 16 + strd r4, r5, [sp, #8] + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + strd r6, r7, [sp] + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + mvn r6, #0 /* all F */ + mov r7, #0 /* all 0 */ + .endm /* init */ + + .macro magic_compare_and_branch w1 w2 label + /* Macro to compare registers w1 and w2 and conditionally branch to label. */ + cmp \w1, \w2 /* Are w1 and w2 the same? */ + magic_find_zero_bytes \w1 + it eq + cmpeq ip, #0 /* Is there a zero byte in w1? */ + bne \label + .endm /* magic_compare_and_branch */ + + .macro magic_find_zero_bytes w1 + /* Macro to find all-zero bytes in w1, result is in ip. */ + uadd8 ip, \w1, r6 + sel ip, r7, r6 + .endm /* magic_find_zero_bytes */ + + .macro setup_return w1 w2 +#ifdef __ARMEB__ + mov r1, \w1 + mov r2, \w2 +#else /* not __ARMEB__ */ + rev r1, \w1 + rev r2, \w2 +#endif /* not __ARMEB__ */ + .endm /* setup_return */ + + pld [r0, #0] + pld [r1, #0] + + /* Are both strings double-word aligned? */ + orr ip, r0, r1 + tst ip, #7 + bne .L_do_align + + /* Fast path. */ + init + +.L_doubleword_aligned: + + /* Get here when the strings to compare are double-word aligned. */ + /* Compare two words in every iteration. */ + .p2align 2 +2: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string. */ + ldrd r2, r3, [r0], #8 + ldrd r4, r5, [r1], #8 + + magic_compare_and_branch w1=r2, w2=r4, label=.L_return_24 + magic_compare_and_branch w1=r3, w2=r5, label=.L_return_35 + b 2b + +.L_do_align: + /* Is the first string word-aligned? */ + ands ip, r0, #3 + beq .L_word_aligned_r0 + + /* Fast compare byte by byte until the first string is word-aligned. */ + /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes + to read until the next word boundary is 4-ip. */ + bic r0, r0, #3 + ldr r2, [r0], #4 + lsls ip, ip, #31 + beq .L_byte2 + bcs .L_byte3 + +.L_byte1: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE1_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte2: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE2_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte3: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE3_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbnz reg=r3, label=.L_word_aligned_r0 + +.L_fast_return: + mov r0, ip + bx lr + +.L_word_aligned_r0: + init + /* The first string is word-aligned. */ + /* Is the second string word-aligned? */ + ands ip, r1, #3 + bne .L_strcmp_unaligned + +.L_word_aligned: + /* The strings are word-aligned. */ + /* Is the first string double-word aligned? */ + tst r0, #4 + beq .L_doubleword_aligned_r0 + + /* If r0 is not double-word aligned yet, align it by loading + and comparing the next word from each string. */ + ldr r2, [r0], #4 + ldr r4, [r1], #4 + magic_compare_and_branch w1=r2 w2=r4 label=.L_return_24 + +.L_doubleword_aligned_r0: + /* Get here when r0 is double-word aligned. */ + /* Is r1 doubleword_aligned? */ + tst r1, #4 + beq .L_doubleword_aligned + + /* Get here when the strings to compare are word-aligned, + r0 is double-word aligned, but r1 is not double-word aligned. */ + + /* Initialize the queue. */ + ldr r5, [r1], #4 + + /* Compare two words in every iteration. */ + .p2align 2 +3: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string and compare. */ + ldrd r2, r3, [r0], #8 + magic_compare_and_branch w1=r2 w2=r5 label=.L_return_25 + ldrd r4, r5, [r1], #8 + magic_compare_and_branch w1=r3 w2=r4 label=.L_return_34 + b 3b + + .macro miscmp_word offsetlo offsethi + /* Macro to compare misaligned strings. */ + /* r0, r1 are word-aligned, and at least one of the strings + is not double-word aligned. */ + /* Compare one word in every loop iteration. */ + /* OFFSETLO is the original bit-offset of r1 from a word-boundary, + OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word). */ + + /* Initialize the shift queue. */ + ldr r5, [r1], #4 + + /* Compare one word from each string in every loop iteration. */ + .p2align 2 +7: + ldr r3, [r0], #4 + S2LOMEM r5, r5, #\offsetlo + magic_find_zero_bytes w1=r3 + cmp r7, ip, S2HIMEM #\offsetlo + and r2, r3, r6, S2LOMEM #\offsetlo + it eq + cmpeq r2, r5 + bne .L_return_25 + ldr r5, [r1], #4 + cmp ip, #0 + eor r3, r2, r3 + S2HIMEM r2, r5, #\offsethi + it eq + cmpeq r3, r2 + bne .L_return_32 + b 7b + .endm /* miscmp_word */ + +.L_strcmp_unaligned: + /* r0 is word-aligned, r1 is at offset ip from a word. */ + /* Align r1 to the (previous) word-boundary. */ + bic r1, r1, #3 + + /* Unaligned comparison word by word using LDRs. */ + cmp ip, #2 + beq .L_miscmp_word_16 /* If ip == 2. */ + bge .L_miscmp_word_24 /* If ip == 3. */ + miscmp_word offsetlo=8 offsethi=24 /* If ip == 1. */ +.L_miscmp_word_16: miscmp_word offsetlo=16 offsethi=16 +.L_miscmp_word_24: miscmp_word offsetlo=24 offsethi=8 + + +.L_return_32: + setup_return w1=r3, w2=r2 + b .L_do_return +.L_return_34: + setup_return w1=r3, w2=r4 + b .L_do_return +.L_return_25: + setup_return w1=r2, w2=r5 + b .L_do_return +.L_return_35: + setup_return w1=r3, w2=r5 + b .L_do_return +.L_return_24: + setup_return w1=r2, w2=r4 + +.L_do_return: + +#ifdef __ARMEB__ + mov r0, ip +#else /* not __ARMEB__ */ + rev r0, ip +#endif /* not __ARMEB__ */ + + /* Restore temporaries early, before computing the return value. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + /* There is a zero or a different byte between r1 and r2. */ + /* r0 contains a mask of all-zero bytes in r1. */ + /* Using r0 and not ip here because cbz requires low register. */ + m_cbz reg=r0, label=.L_compute_return_value + clz r0, r0 + /* r0 contains the number of bits on the left of the first all-zero byte in r1. */ + rsb r0, r0, #24 + /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1. */ + lsr r1, r1, r0 + lsr r2, r2, r0 + +.L_compute_return_value: + movs r0, #1 + cmp r1, r2 + /* The return value is computed as follows. + If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return. + If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0, + which means r0:=r0-r0-1 and r0 is #-1 at return. + If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1, + which means r0:=r0-r0 and r0 is #0 at return. + (C==0 and Z==1) cannot happen because the carry bit is "not borrow". */ + it ls + sbcls r0, r0, r0 + bx lr +END(strcmp)
diff --git a/libc/arch-arm/cortex-a15/bionic/strcpy.S b/libc/arch-arm/cortex-a15/bionic/strcpy.S new file mode 100644 index 0000000..951face --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/strcpy.S
@@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define STRCPY +#include "string_copy.S"
diff --git a/libc/arch-arm/cortex-a15/bionic/string_copy.S b/libc/arch-arm/cortex-a15/bionic/string_copy.S new file mode 100644 index 0000000..92d1c98 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/string_copy.S
@@ -0,0 +1,520 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(STPCPY) && !defined(STRCPY) +#error "Either STPCPY or STRCPY must be defined." +#endif + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +#if defined(STPCPY) + .macro m_push + push {r4, r5, lr} + .cfi_def_cfa_offset 12 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset lr, 8 + .endm // m_push +#else + .macro m_push + push {r0, r4, r5, lr} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r0, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset r5, 8 + .cfi_rel_offset lr, 12 + .endm // m_push +#endif + +#if defined(STPCPY) + .macro m_pop + pop {r4, r5, pc} + .endm // m_pop +#else + .macro m_pop + pop {r0, r4, r5, pc} + .endm // m_pop +#endif + + .macro m_copy_byte reg, cmd, label + ldrb \reg, [r1], #1 + strb \reg, [r0], #1 + \cmd \reg, \label + .endm // m_copy_byte + +#if defined(STPCPY) +ENTRY(stpcpy) +#else +ENTRY(strcpy) +#endif + // For short copies, hard-code checking the first 8 bytes since this + // new code doesn't win until after about 8 bytes. + m_push + m_copy_byte reg=r2, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r5, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r2, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r5, cmd=cbnz, label=.Lstringcopy_continue + +.Lstringcopy_finish: +#if defined(STPCPY) + sub r0, r0, #1 +#endif + m_pop + +.Lstringcopy_continue: + pld [r1, #0] + ands r3, r0, #7 + beq .Lstringcopy_check_src_align + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .Lstringcopy_align_to_32 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + +.Lstringcopy_align_to_32: + bcc .Lstringcopy_align_to_64 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + +.Lstringcopy_align_to_64: + tst r3, #4 + beq .Lstringcopy_check_src_align + // Read one byte at a time since we don't have any idea about the alignment + // of the source and we don't want to read into a different page. + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + +.Lstringcopy_check_src_align: + // At this point dst is aligned to a double word, check if src + // is also aligned to a double word. + ands r3, r1, #7 + bne .Lstringcopy_unaligned_copy + + .p2align 2 +.Lstringcopy_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_mainloop + +.Lstringcopy_complete: +#if defined(STPCPY) + sub r0, r0, #1 +#endif + m_pop + +.Lstringcopy_zero_in_first_register: + lsls lr, ip, #17 + bne .Lstringcopy_copy1byte + bcs .Lstringcopy_copy2bytes + lsls ip, ip, #1 + bne .Lstringcopy_copy3bytes + +.Lstringcopy_copy4bytes: + // Copy 4 bytes to the destiniation. +#if defined(STPCPY) + str r2, [r0], #3 +#else + str r2, [r0] +#endif + m_pop + +.Lstringcopy_copy1byte: + strb r2, [r0] + m_pop + +.Lstringcopy_copy2bytes: +#if defined(STPCPY) + strh r2, [r0], #1 +#else + strh r2, [r0] +#endif + m_pop + +.Lstringcopy_copy3bytes: + strh r2, [r0], #2 + lsr r2, #16 + strb r2, [r0] + m_pop + +.Lstringcopy_zero_in_second_register: + lsls lr, ip, #17 + bne .Lstringcopy_copy5bytes + bcs .Lstringcopy_copy6bytes + lsls ip, ip, #1 + bne .Lstringcopy_copy7bytes + + // Copy 8 bytes to the destination. + strd r2, r3, [r0] +#if defined(STPCPY) + add r0, r0, #7 +#endif + m_pop + +.Lstringcopy_copy5bytes: + str r2, [r0], #4 + strb r3, [r0] + m_pop + +.Lstringcopy_copy6bytes: + str r2, [r0], #4 +#if defined(STPCPY) + strh r3, [r0], #1 +#else + strh r3, [r0] +#endif + m_pop + +.Lstringcopy_copy7bytes: + str r2, [r0], #4 + strh r3, [r0], #2 + lsr r3, #16 + strb r3, [r0] + m_pop + +.Lstringcopy_unaligned_copy: + // Dst is aligned to a double word, while src is at an unknown alignment. + // There are 7 different versions of the unaligned copy code + // to prevent overreading the src. The mainloop of every single version + // will store 64 bits per loop. The difference is how much of src can + // be read without potentially crossing a page boundary. + tbb [pc, r3] +.Lstringcopy_unaligned_branchtable: + .byte 0 + .byte ((.Lstringcopy_unalign7 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign6 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign5 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign4 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign3 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign2 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign1 - .Lstringcopy_unaligned_branchtable)/2) + + .p2align 2 + // Can read 7 bytes before possibly crossing a page. +.Lstringcopy_unalign7: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r3, [r1] + cbz r3, .Lstringcopy_unalign7_copy5bytes + ldrb r4, [r1, #1] + cbz r4, .Lstringcopy_unalign7_copy6bytes + ldrb r5, [r1, #2] + cbz r5, .Lstringcopy_unalign7_copy7bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + lsrs ip, r3, #24 + strd r2, r3, [r0], #8 +#if defined(STPCPY) + beq .Lstringcopy_finish +#else + beq .Lstringcopy_unalign_return +#endif + b .Lstringcopy_unalign7 + +.Lstringcopy_unalign7_copy5bytes: + str r2, [r0], #4 + strb r3, [r0] +.Lstringcopy_unalign_return: + m_pop + +.Lstringcopy_unalign7_copy6bytes: + str r2, [r0], #4 + strb r3, [r0], #1 + strb r4, [r0] + m_pop + +.Lstringcopy_unalign7_copy7bytes: + str r2, [r0], #4 + strb r3, [r0], #1 + strb r4, [r0], #1 + strb r5, [r0] + m_pop + + .p2align 2 + // Can read 6 bytes before possibly crossing a page. +.Lstringcopy_unalign6: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstringcopy_unalign_copy5bytes + ldrb r5, [r1, #1] + cbz r5, .Lstringcopy_unalign_copy6bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + tst r3, #0xff0000 + beq .Lstringcopy_copy7bytes + lsrs ip, r3, #24 + strd r2, r3, [r0], #8 +#if defined(STPCPY) + beq .Lstringcopy_finish +#else + beq .Lstringcopy_unalign_return +#endif + b .Lstringcopy_unalign6 + + .p2align 2 + // Can read 5 bytes before possibly crossing a page. +.Lstringcopy_unalign5: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstringcopy_unalign_copy5bytes + + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_unalign5 + +.Lstringcopy_unalign_copy5bytes: + str r2, [r0], #4 + strb r4, [r0] + m_pop + +.Lstringcopy_unalign_copy6bytes: + str r2, [r0], #4 + strb r4, [r0], #1 + strb r5, [r0] + m_pop + + .p2align 2 + // Can read 4 bytes before possibly crossing a page. +.Lstringcopy_unalign4: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldr r3, [r1], #4 + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_unalign4 + + .p2align 2 + // Can read 3 bytes before possibly crossing a page. +.Lstringcopy_unalign3: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign3_copy1byte + ldrb r3, [r1, #1] + cbz r3, .Lstringcopy_unalign3_copy2bytes + ldrb r4, [r1, #2] + cbz r4, .Lstringcopy_unalign3_copy3bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + lsrs lr, r2, #24 + beq .Lstringcopy_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_unalign3 + +.Lstringcopy_unalign3_copy1byte: + strb r2, [r0] + m_pop + +.Lstringcopy_unalign3_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_pop + +.Lstringcopy_unalign3_copy3bytes: + strb r2, [r0], #1 + strb r3, [r0], #1 + strb r4, [r0] + m_pop + + .p2align 2 + // Can read 2 bytes before possibly crossing a page. +.Lstringcopy_unalign2: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign_copy1byte + ldrb r4, [r1, #1] + cbz r4, .Lstringcopy_unalign_copy2bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + pld [r1, #64] + + tst r2, #0xff0000 + beq .Lstringcopy_copy3bytes + lsrs ip, r2, #24 + beq .Lstringcopy_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_unalign2 + + .p2align 2 + // Can read 1 byte before possibly crossing a page. +.Lstringcopy_unalign1: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign_copy1byte + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + strd r2, r3, [r0], #8 + b .Lstringcopy_unalign1 + +.Lstringcopy_unalign_copy1byte: + strb r2, [r0] + m_pop + +.Lstringcopy_unalign_copy2bytes: + strb r2, [r0], #1 + strb r4, [r0] + m_pop +#if defined(STPCPY) +END(stpcpy) +#else +END(strcpy) +#endif
diff --git a/libc/arch-arm/cortex-a15/bionic/strlen.S b/libc/arch-arm/cortex-a15/bionic/strlen.S new file mode 100644 index 0000000..4fd6284 --- /dev/null +++ b/libc/arch-arm/cortex-a15/bionic/strlen.S
@@ -0,0 +1,165 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +ENTRY(strlen) + pld [r0, #0] + mov r1, r0 + + ands r3, r0, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_return + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_return + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_return + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r1], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_return: + sub r0, r1, r0 + sub r0, r0, #1 + bx lr + +.L_zero_in_first_register: + sub r0, r1, r0 + lsls r3, ip, #17 + bne .L_sub8_and_return + bcs .L_sub7_and_return + lsls ip, ip, #1 + bne .L_sub6_and_return + + sub r0, r0, #5 + bx lr + +.L_sub8_and_return: + sub r0, r0, #8 + bx lr + +.L_sub7_and_return: + sub r0, r0, #7 + bx lr + +.L_sub6_and_return: + sub r0, r0, #6 + bx lr + +.L_zero_in_second_register: + sub r0, r1, r0 + lsls r3, ip, #17 + bne .L_sub4_and_return + bcs .L_sub3_and_return + lsls ip, ip, #1 + bne .L_sub2_and_return + + sub r0, r0, #1 + bx lr + +.L_sub4_and_return: + sub r0, r0, #4 + bx lr + +.L_sub3_and_return: + sub r0, r0, #3 + bx lr + +.L_sub2_and_return: + sub r0, r0, #2 + bx lr +END(strlen)
diff --git a/libc/arch-arm/cortex-a53/bionic/__strcat_chk.S b/libc/arch-arm/cortex-a53/bionic/__strcat_chk.S new file mode 100644 index 0000000..c5bc98a --- /dev/null +++ b/libc/arch-arm/cortex-a53/bionic/__strcat_chk.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "arch-arm/cortex-a53/bionic/memcpy_base.S" + +#include "arch-arm/cortex-a15/bionic/__strcat_chk_common.S"
diff --git a/libc/arch-arm/cortex-a53/bionic/__strcpy_chk.S b/libc/arch-arm/cortex-a53/bionic/__strcpy_chk.S new file mode 100644 index 0000000..1f8945d --- /dev/null +++ b/libc/arch-arm/cortex-a53/bionic/__strcpy_chk.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "arch-arm/cortex-a53/bionic/memcpy_base.S" + +#include "arch-arm/cortex-a15/bionic/__strcpy_chk_common.S"
diff --git a/libc/arch-arm/cortex-a53/bionic/memcpy.S b/libc/arch-arm/cortex-a53/bionic/memcpy.S new file mode 100644 index 0000000..664f574 --- /dev/null +++ b/libc/arch-arm/cortex-a53/bionic/memcpy.S
@@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Indicate which memcpy base file to include. +#define MEMCPY_BASE "arch-arm/cortex-a53/bionic/memcpy_base.S" + +#include "arch-arm/cortex-a15/bionic/memcpy_common.S"
diff --git a/libc/arch-arm/cortex-a53/bionic/memcpy_base.S b/libc/arch-arm/cortex-a53/bionic/memcpy_base.S new file mode 100644 index 0000000..2749fc8 --- /dev/null +++ b/libc/arch-arm/cortex-a53/bionic/memcpy_base.S
@@ -0,0 +1,143 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +.L_memcpy_base: + // Assumes that n >= 0, and dst, src are valid pointers. + cmp r2, #16 + blo .L_copy_less_than_16_unknown_align + +.L_copy_unknown_alignment: + // Unknown alignment of src and dst. + // Assumes that the first few bytes have already been prefetched. + + // Align destination to 128 bits. The mainloop store instructions + // require this alignment or they will throw an exception. + rsb r3, r0, #0 + ands r3, r3, #0xF + beq 2f + + // Copy up to 15 bytes (count in r3). + sub r2, r2, r3 + movs ip, r3, lsl #31 + + itt mi + ldrbmi lr, [r1], #1 + strbmi lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1], #1 + strbcs ip, [r0], #1 + strbcs lr, [r0], #1 + + movs ip, r3, lsl #29 + bge 1f + // Copies 4 bytes, dst 32 bits aligned before, at least 64 bits after. + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]! +1: bcc 2f + // Copies 8 bytes, dst 64 bits aligned before, at least 128 bits after. + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0, :64]! + +2: // Make sure we have at least 64 bytes to copy. + subs r2, r2, #64 + blo 2f + +1: // The main loop copies 64 bytes at a time. + vld1.8 {d0 - d3}, [r1]! + vld1.8 {d4 - d7}, [r1]! + subs r2, r2, #64 + vstmia r0!, {d0 - d7} + pld [r1, #(64*10)] + bhs 1b + +2: // Fix-up the remaining count and make sure we have >= 32 bytes left. + adds r2, r2, #32 + blo 3f + + // 32 bytes. These cache lines were already preloaded. + vld1.8 {d0 - d3}, [r1]! + sub r2, r2, #32 + vst1.8 {d0 - d3}, [r0, :128]! +3: // Less than 32 left. + add r2, r2, #32 + tst r2, #0x10 + beq .L_copy_less_than_16_unknown_align + // Copies 16 bytes, destination 128 bits aligned. + vld1.8 {d0, d1}, [r1]! + vst1.8 {d0, d1}, [r0, :128]! + +.L_copy_less_than_16_unknown_align: + // Copy up to 15 bytes (count in r2). + movs ip, r2, lsl #29 + bcc 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0]! +1: bge 2f + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! + +2: // Copy 0 to 4 bytes. + lsls r2, r2, #31 + itt ne + ldrbne lr, [r1], #1 + strbne lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1] + strbcs ip, [r0], #1 + strbcs lr, [r0] + + pop {r0, pc}
diff --git a/libc/arch-arm/cortex-a7/bionic/memset.S b/libc/arch-arm/cortex-a7/bionic/memset.S new file mode 100644 index 0000000..e4fb1b4 --- /dev/null +++ b/libc/arch-arm/cortex-a7/bionic/memset.S
@@ -0,0 +1,159 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + /* + * Optimized memset() for ARM. + * + * memset() returns its first argument. + */ + + .fpu neon + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + mov r3, r0 + // At this point only d0, d1 are going to be used below. + vdup.8 q0, r1 + cmp r2, #16 + blo .L_set_less_than_16_unknown_align + +.L_check_alignment: + // Align destination to a double word to avoid the store crossing + // a cache line boundary. + ands ip, r3, #7 + bne .L_do_double_word_align + +.L_double_word_aligned: + // Duplicate since the less than 64 can use d2, d3. + vmov q1, q0 + subs r2, #64 + blo .L_set_less_than_64 + + // Duplicate the copy value so that we can store 64 bytes at a time. + vmov q2, q0 + vmov q3, q0 + +1: // Main loop stores 64 bytes at a time. + subs r2, #64 + vstmia r3!, {d0 - d7} + bge 1b + +.L_set_less_than_64: + // Restore r2 to the count of bytes left to set. + add r2, #64 + lsls ip, r2, #27 + bcc .L_set_less_than_32 + // Set 32 bytes. + vstmia r3!, {d0 - d3} + +.L_set_less_than_32: + bpl .L_set_less_than_16 + // Set 16 bytes. + vstmia r3!, {d0, d1} + +.L_set_less_than_16: + // Less than 16 bytes to set. + lsls ip, r2, #29 + bcc .L_set_less_than_8 + + // Set 8 bytes. + vstmia r3!, {d0} + +.L_set_less_than_8: + bpl .L_set_less_than_4 + // Set 4 bytes + vst1.32 {d0[0]}, [r3]! + +.L_set_less_than_4: + lsls ip, r2, #31 + it ne + strbne r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3] + bx lr + +.L_do_double_word_align: + rsb ip, ip, #8 + sub r2, r2, ip + + // Do this comparison now, otherwise we'll need to save a + // register to the stack since we've used all available + // registers. + cmp ip, #4 + blo 1f + + // Need to do a four byte copy. + movs ip, ip, lsl #31 + it mi + strbmi r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + vst1.32 {d0[0]}, [r3]! + b .L_double_word_aligned + +1: + // No four byte copy. + movs ip, ip, lsl #31 + it mi + strbmi r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + b .L_double_word_aligned + +.L_set_less_than_16_unknown_align: + // Set up to 15 bytes. + movs ip, r2, lsl #29 + bcc 1f + vst1.8 {d0}, [r3]! +1: bge 2f + vst1.32 {d0[0]}, [r3]! +2: movs ip, r2, lsl #31 + it mi + strbmi r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + bx lr +END(memset)
diff --git a/libc/arch-arm/cortex-a9/bionic/__strcat_chk.S b/libc/arch-arm/cortex-a9/bionic/__strcat_chk.S new file mode 100644 index 0000000..776c782 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/__strcat_chk.S
@@ -0,0 +1,198 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + .fpu neon + .thumb + .thumb_func + +// Get the length of src string, then get the source of the dst string. +// Check that the two lengths together don't exceed the threshold, then +// do a memcpy of the data. +ENTRY(__strcat_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + push {r4, r5} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + + mov lr, r2 + + // Save the dst register to r5 + mov r5, r0 + + // Zero out r4 + eor r4, r4, r4 + + // r1 contains the address of the string to count. +.L_strlen_start: + mov r0, r1 + + ands r3, r0, #7 + bne .L_align_src + + .p2align 2 +.L_mainloop: + ldmia r1!, {r2, r3} + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_zero_in_first_register: + sub r3, r1, r0 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq .L_check_byte1_reg1 + + sub r3, r3, #8 + b .L_finish + +.L_check_byte1_reg1: + bcc .L_check_byte2_reg1 + + sub r3, r3, #7 + b .L_finish + +.L_check_byte2_reg1: + // Check for zero in byte 2. + tst ip, #0x800000 + it ne + subne r3, r3, #6 + bne .L_finish + sub r3, r3, #5 + b .L_finish + +.L_zero_in_second_register: + sub r3, r1, r0 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq .L_check_byte1_reg2 + + sub r3, r3, #4 + b .L_finish + +.L_check_byte1_reg2: + bcc .L_check_byte2_reg2 + + sub r3, r3, #3 + b .L_finish + +.L_check_byte2_reg2: + // Check for zero in byte 2. + tst ip, #0x800000 + it ne + subne r3, r3, #2 + bne .L_finish + sub r3, r3, #1 + b .L_finish + +.L_align_src: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r1], #1 + cbz r2, .L_done + +.L_align_to_32: + bcc .L_align_to_64 + + ldrb r2, [r1], #1 + cbz r2, .L_done + ldrb r2, [r1], #1 + cbz r2, .L_done + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_done: + sub r3, r1, r0 + sub r3, r3, #1 + +.L_finish: + cmp r4, #0 + bne .L_strlen_done + + // Time to get the dst string length. + mov r1, r5 + + // Save the original source address to r5. + mov r5, r0 + + // Save the current length (adding 1 for the terminator). + add r4, r3, #1 + b .L_strlen_start + + // r0 holds the pointer to the dst string. + // r3 holds the dst string length. + // r4 holds the src string length + 1. +.L_strlen_done: + add r2, r3, r4 + cmp r2, lr + itt hi + movhi r0, lr + bhi __strcat_chk_fail + + // Set up the registers for the memcpy code. + mov r1, r5 + pld [r1, #64] + mov r2, r4 + add r0, r0, r3 + pop {r4, r5} + + // Fall through into the memcpy_base function. +END(__strcat_chk) + +#define MEMCPY_BASE __strcat_chk_memcpy_base +#define MEMCPY_BASE_ALIGNED __strcat_chk_memcpy_base_aligned +#include "memcpy_base.S"
diff --git a/libc/arch-arm/cortex-a9/bionic/__strcpy_chk.S b/libc/arch-arm/cortex-a9/bionic/__strcpy_chk.S new file mode 100644 index 0000000..1d5e70b --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/__strcpy_chk.S
@@ -0,0 +1,166 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + .fpu neon + .thumb + .thumb_func + +// Get the length of the source string first, then do a memcpy of the data +// instead of a strcpy. +ENTRY(__strcpy_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + mov lr, r2 + mov r0, r1 + + ands r3, r0, #7 + bne .L_align_src + + .p2align 2 +.L_mainloop: + ldmia r0!, {r2, r3} + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_zero_in_first_register: + sub r3, r0, r1 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq .L_check_byte1_reg1 + + sub r3, r3, #8 + b .L_check_size + +.L_check_byte1_reg1: + bcc .L_check_byte2_reg1 + + sub r3, r3, #7 + b .L_check_size + +.L_check_byte2_reg1: + // Check for zero in byte 2. + tst ip, #0x800000 + it ne + subne r3, r3, #6 + bne .L_check_size + sub r3, r3, #5 + b .L_check_size + +.L_zero_in_second_register: + sub r3, r0, r1 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq .L_check_byte1_reg2 + + sub r3, r3, #4 + b .L_check_size + +.L_check_byte1_reg2: + bcc .L_check_byte2_reg2 + + sub r3, r3, #3 + b .L_check_size + +.L_check_byte2_reg2: + // Check for zero in byte 2. + tst ip, #0x800000 + it ne + subne r3, r3, #2 + bne .L_check_size + sub r3, r3, #1 + b .L_check_size + +.L_align_src: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r0], #1 + cbz r2, .L_done + +.L_align_to_32: + bcc .L_align_to_64 + + ldrb r2, [r0], #1 + cbz r2, .L_done + ldrb r2, [r0], #1 + cbz r2, .L_done + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r2, [r0], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_done: + sub r3, r0, r1 + sub r3, r3, #1 + +.L_check_size: + pld [r1, #0] + pld [r1, #64] + ldr r0, [sp] + + // Add 1 for copy length to get the string terminator. + add r2, r3, #1 + + cmp r2, lr + itt hi + movhi r0, r2 + bhi __strcpy_chk_fail + + // Fall through into the memcpy_base function. +END(__strcpy_chk) + +#define MEMCPY_BASE __strcpy_chk_memcpy_base +#define MEMCPY_BASE_ALIGNED __strcpy_chk_memcpy_base_aligned +#include "memcpy_base.S"
diff --git a/libc/arch-arm/cortex-a9/bionic/memcpy.S b/libc/arch-arm/cortex-a9/bionic/memcpy.S new file mode 100644 index 0000000..93a8629 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/memcpy.S
@@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +/* + * This code assumes it is running on a processor that supports all arm v7 + * instructions, that supports neon instructions, and that has a 32 byte + * cache line. + */ + + .syntax unified + .fpu neon + .thumb + .thumb_func + +ENTRY(__memcpy_chk) + cmp r2, r3 + bls memcpy + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + pld [r1, #0] + stmfd sp!, {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + pld [r1, #64] +END(memcpy) + +#define MEMCPY_BASE __memcpy_base +#define MEMCPY_BASE_ALIGNED __memcpy_base_aligned +#include "memcpy_base.S"
diff --git a/libc/arch-arm/cortex-a9/bionic/memcpy_base.S b/libc/arch-arm/cortex-a9/bionic/memcpy_base.S new file mode 100644 index 0000000..966b9b3 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/memcpy_base.S
@@ -0,0 +1,222 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * This code assumes it is running on a processor that supports all arm v7 + * instructions, that supports neon instructions, and that has a 32 byte + * cache line. + */ + +ENTRY_PRIVATE(MEMCPY_BASE) + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + // Check so divider is at least 16 bytes, needed for alignment code. + cmp r2, #16 + blo 5f + + /* check if buffers are aligned. If so, run arm-only version */ + eor r3, r0, r1 + ands r3, r3, #0x3 + beq MEMCPY_BASE_ALIGNED + + /* Check the upper size limit for Neon unaligned memory access in memcpy */ + cmp r2, #224 + blo 3f + + /* align destination to 16 bytes for the write-buffer */ + rsb r3, r0, #0 + ands r3, r3, #0xF + beq 3f + + /* copy up to 15-bytes (count in r3) */ + sub r2, r2, r3 + movs ip, r3, lsl #31 + itt mi + ldrbmi lr, [r1], #1 + strbmi lr, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1], #1 + strbcs ip, [r0], #1 + strbcs lr, [r0], #1 + movs ip, r3, lsl #29 + bge 1f + // copies 4 bytes, destination 32-bits aligned + vld1.32 {d0[0]}, [r1]! + vst1.32 {d0[0]}, [r0, :32]! +1: bcc 2f + // copies 8 bytes, destination 64-bits aligned + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0, :64]! +2: + /* preload immediately the next cache line, which we may need */ + pld [r1, #0] + pld [r1, #(32 * 2)] +3: + /* make sure we have at least 64 bytes to copy */ + subs r2, r2, #64 + blo 2f + + /* preload all the cache lines we need */ + pld [r1, #(32 * 4)] + pld [r1, #(32 * 6)] + +1: /* The main loop copies 64 bytes at a time */ + vld1.8 {d0 - d3}, [r1]! + vld1.8 {d4 - d7}, [r1]! + pld [r1, #(32 * 6)] + subs r2, r2, #64 + vst1.8 {d0 - d3}, [r0]! + vst1.8 {d4 - d7}, [r0]! + bhs 1b + +2: /* fix-up the remaining count and make sure we have >= 32 bytes left */ + add r2, r2, #64 + subs r2, r2, #32 + blo 4f + +3: /* 32 bytes at a time. These cache lines were already preloaded */ + vld1.8 {d0 - d3}, [r1]! + subs r2, r2, #32 + vst1.8 {d0 - d3}, [r0]! + bhs 3b + +4: /* less than 32 left */ + add r2, r2, #32 + tst r2, #0x10 + beq 5f + // copies 16 bytes, 128-bits aligned + vld1.8 {d0, d1}, [r1]! + vst1.8 {d0, d1}, [r0]! +5: /* copy up to 15-bytes (count in r2) */ + movs ip, r2, lsl #29 + bcc 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0]! +1: bge 2f + vld1.32 {d0[0]}, [r1]! + vst1.32 {d0[0]}, [r0]! +2: movs ip, r2, lsl #31 + itt mi + ldrbmi r3, [r1], #1 + strbmi r3, [r0], #1 + itttt cs + ldrbcs ip, [r1], #1 + ldrbcs lr, [r1], #1 + strbcs ip, [r0], #1 + strbcs lr, [r0], #1 + + ldmfd sp!, {r0, pc} +END(MEMCPY_BASE) + +ENTRY_PRIVATE(MEMCPY_BASE_ALIGNED) + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + /* Simple arm-only copy loop to handle aligned copy operations */ + stmfd sp!, {r4-r8} + .cfi_adjust_cfa_offset 20 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + .cfi_rel_offset r8, 16 + pld [r1, #(32 * 4)] + + /* Check alignment */ + rsb r3, r1, #0 + ands r3, #3 + beq 2f + + /* align source to 32 bits. We need to insert 2 instructions between + * a ldr[b|h] and str[b|h] because byte and half-word instructions + * stall 2 cycles. + */ + movs r12, r3, lsl #31 + sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */ + itt mi + ldrbmi r3, [r1], #1 + strbmi r3, [r0], #1 + itttt cs + ldrbcs r4, [r1], #1 + ldrbcs r5, [r1], #1 + strbcs r4, [r0], #1 + strbcs r5, [r0], #1 + +2: + subs r2, r2, #64 + blt 4f + +3: /* Main copy loop, copying 64 bytes at a time */ + pld [r1, #(32 * 8)] + ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr} + stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr} + ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr} + stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr} + subs r2, r2, #64 + bge 3b + +4: /* Check if there are > 32 bytes left */ + adds r2, r2, #64 + subs r2, r2, #32 + blt 5f + + /* Copy 32 bytes */ + ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr} + stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr} + subs r2, #32 + +5: /* Handle any remaining bytes */ + adds r2, #32 + beq 6f + + movs r12, r2, lsl #28 + itt cs + ldmiacs r1!, {r3, r4, r5, r6} /* 16 bytes */ + stmiacs r0!, {r3, r4, r5, r6} + itt mi + ldmiami r1!, {r7, r8} /* 8 bytes */ + stmiami r0!, {r7, r8} + movs r12, r2, lsl #30 + itt cs + ldrcs r3, [r1], #4 /* 4 bytes */ + strcs r3, [r0], #4 + itt mi + ldrhmi r4, [r1], #2 /* 2 bytes */ + strhmi r4, [r0], #2 + tst r2, #0x1 + itt ne + ldrbne r3, [r1] /* last byte */ + strbne r3, [r0] +6: + ldmfd sp!, {r4-r8} + ldmfd sp!, {r0, pc} +END(MEMCPY_BASE_ALIGNED)
diff --git a/libc/arch-arm/cortex-a9/bionic/memset.S b/libc/arch-arm/cortex-a9/bionic/memset.S new file mode 100644 index 0000000..d00231b --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/memset.S
@@ -0,0 +1,161 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +/* + * This code assumes it is running on a processor that supports all arm v7 + * instructions and that supports neon instructions. + */ + + .fpu neon + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memset_chk_fail +END(__memset_chk) + +/* memset() returns its first argument. */ +ENTRY(memset) + // The neon memset only wins for less than 132. + cmp r2, #132 + bhi .L_memset_large_copy + + mov r3, r0 + vdup.8 q0, r1 + + /* make sure we have at least 32 bytes to write */ + subs r2, r2, #32 + blo 2f + vmov q1, q0 + +1: /* The main loop writes 32 bytes at a time */ + subs r2, r2, #32 + vst1.8 {d0 - d3}, [r3]! + bhs 1b + +2: /* less than 32 left */ + add r2, r2, #32 + tst r2, #0x10 + beq 3f + + // writes 16 bytes, 128-bits aligned + vst1.8 {d0, d1}, [r3]! +3: /* write up to 15-bytes (count in r2) */ + movs ip, r2, lsl #29 + bcc 1f + vst1.8 {d0}, [r3]! +1: bge 2f + vst1.32 {d0[0]}, [r3]! +2: movs ip, r2, lsl #31 + strbmi r1, [r3], #1 + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + bx lr + +.L_memset_large_copy: + /* compute the offset to align the destination + * offset = (4-(src&3))&3 = -src & 3 + */ + stmfd sp!, {r0, r4-r7, lr} + .cfi_def_cfa_offset 24 + .cfi_rel_offset r0, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset r5, 8 + .cfi_rel_offset r6, 12 + .cfi_rel_offset r7, 16 + .cfi_rel_offset lr, 20 + + rsb r3, r0, #0 + ands r3, r3, #3 + cmp r3, r2 + movhi r3, r2 + + /* splat r1 */ + mov r1, r1, lsl #24 + orr r1, r1, r1, lsr #8 + orr r1, r1, r1, lsr #16 + + movs r12, r3, lsl #31 + strbcs r1, [r0], #1 /* can't use strh (alignment unknown) */ + strbcs r1, [r0], #1 + strbmi r1, [r0], #1 + subs r2, r2, r3 + popls {r0, r4-r7, pc} /* return */ + + /* align the destination to a cache-line */ + mov r12, r1 + mov lr, r1 + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + + rsb r3, r0, #0 + ands r3, r3, #0x1C + beq 3f + cmp r3, r2 + andhi r3, r2, #0x1C + sub r2, r2, r3 + + /* conditionally writes 0 to 7 words (length in r3) */ + movs r3, r3, lsl #28 + stmcs r0!, {r1, lr} + stmcs r0!, {r1, lr} + stmmi r0!, {r1, lr} + movs r3, r3, lsl #2 + strcs r1, [r0], #4 + +3: + subs r2, r2, #32 + mov r3, r1 + bmi 2f +1: subs r2, r2, #32 + stmia r0!, {r1,r3,r4,r5,r6,r7,r12,lr} + bhs 1b +2: add r2, r2, #32 + + /* conditionally stores 0 to 31 bytes */ + movs r2, r2, lsl #28 + stmcs r0!, {r1,r3,r12,lr} + stmmi r0!, {r1, lr} + movs r2, r2, lsl #2 + strcs r1, [r0], #4 + strhmi r1, [r0], #2 + movs r2, r2, lsl #2 + strbcs r1, [r0] + ldmfd sp!, {r0, r4-r7, pc} +END(memset)
diff --git a/libc/arch-arm/cortex-a9/bionic/stpcpy.S b/libc/arch-arm/cortex-a9/bionic/stpcpy.S new file mode 100644 index 0000000..740523b --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/stpcpy.S
@@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define STPCPY +#include "string_copy.S"
diff --git a/libc/arch-arm/cortex-a9/bionic/strcat.S b/libc/arch-arm/cortex-a9/bionic/strcat.S new file mode 100644 index 0000000..9077a74 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/strcat.S
@@ -0,0 +1,555 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + + .macro m_push + push {r0, r4, r5, lr} + .endm // m_push + + .macro m_ret inst + \inst {r0, r4, r5, pc} + .endm // m_ret + + .macro m_scan_byte + ldrb r3, [r0] + cbz r3, .Lstrcat_r0_scan_done + add r0, #1 + .endm // m_scan_byte + + .macro m_copy_byte reg, cmd, label + ldrb \reg, [r1], #1 + strb \reg, [r0], #1 + \cmd \reg, \label + .endm // m_copy_byte + +ENTRY(strcat) + // Quick check to see if src is empty. + ldrb r2, [r1] + pld [r1, #0] + cbnz r2, .Lstrcat_continue + bx lr + +.Lstrcat_continue: + // To speed up really small dst strings, unroll checking the first 4 bytes. + m_push + m_scan_byte + m_scan_byte + m_scan_byte + m_scan_byte + + ands r3, r0, #7 + bne .Lstrcat_align_src + + .p2align 2 +.Lstrcat_mainloop: + ldmia r0!, {r2, r3} + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcat_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcat_zero_in_second_register + b .Lstrcat_mainloop + +.Lstrcat_zero_in_first_register: + sub r0, r0, #4 + +.Lstrcat_zero_in_second_register: + // Check for zero in byte 0. + tst ip, #0x80 + it ne + subne r0, r0, #4 + bne .Lstrcat_r0_scan_done + // Check for zero in byte 1. + tst ip, #0x8000 + it ne + subne r0, r0, #3 + bne .Lstrcat_r0_scan_done + // Check for zero in byte 2. + tst ip, #0x800000 + it ne + subne r0, r0, #2 + it eq + // Zero is in byte 3. + subeq r0, r0, #1 + +.Lstrcat_r0_scan_done: + // Unroll the first 8 bytes that will be copied. + m_copy_byte reg=r2, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r5, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r2, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstrcpy_finish + m_copy_byte reg=r5, cmd=cbnz, label=.Lstrcpy_continue + +.Lstrcpy_finish: + m_ret inst=pop + +.Lstrcpy_continue: + pld [r1, #0] + ands r3, r0, #7 + bne .Lstrcpy_align_dst + +.Lstrcpy_check_src_align: + // At this point dst is aligned to a double word, check if src + // is also aligned to a double word. + ands r3, r1, #7 + bne .Lstrcpy_unaligned_copy + + .p2align 2 +.Lstrcpy_mainloop: + ldmia r1!, {r2, r3} + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_mainloop + +.Lstrcpy_zero_in_first_register: + lsls lr, ip, #17 + itt ne + strbne r2, [r0] + m_ret inst=popne + itt cs + strhcs r2, [r0] + m_ret inst=popcs + lsls ip, ip, #1 + itt eq + streq r2, [r0] + m_ret inst=popeq + strh r2, [r0], #2 + lsr r3, r2, #16 + strb r3, [r0] + m_ret inst=pop + +.Lstrcpy_zero_in_second_register: + lsls lr, ip, #17 + ittt ne + stmiane r0!, {r2} + strbne r3, [r0] + m_ret inst=popne + ittt cs + strcs r2, [r0], #4 + strhcs r3, [r0] + m_ret inst=popcs + lsls ip, ip, #1 + itt eq + stmiaeq r0, {r2, r3} + m_ret inst=popeq + stmia r0!, {r2} + strh r3, [r0], #2 + lsr r4, r3, #16 + strb r4, [r0] + m_ret inst=pop + +.Lstrcpy_align_dst: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .Lstrcpy_align_to_32 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstrcpy_complete + +.Lstrcpy_align_to_32: + bcc .Lstrcpy_align_to_64 + + ldrb r4, [r1], #1 + strb r4, [r0], #1 + cmp r4, #0 + it eq + m_ret inst=popeq + ldrb r5, [r1], #1 + strb r5, [r0], #1 + cmp r5, #0 + it eq + m_ret inst=popeq + +.Lstrcpy_align_to_64: + tst r3, #4 + beq .Lstrcpy_check_src_align + // Read one byte at a time since we don't know the src alignment + // and we don't want to read into a different page. + ldrb r4, [r1], #1 + strb r4, [r0], #1 + cbz r4, .Lstrcpy_complete + ldrb r5, [r1], #1 + strb r5, [r0], #1 + cbz r5, .Lstrcpy_complete + ldrb r4, [r1], #1 + strb r4, [r0], #1 + cbz r4, .Lstrcpy_complete + ldrb r5, [r1], #1 + strb r5, [r0], #1 + cbz r5, .Lstrcpy_complete + b .Lstrcpy_check_src_align + +.Lstrcpy_complete: + m_ret inst=pop + +.Lstrcpy_unaligned_copy: + // Dst is aligned to a double word, while src is at an unknown alignment. + // There are 7 different versions of the unaligned copy code + // to prevent overreading the src. The mainloop of every single version + // will store 64 bits per loop. The difference is how much of src can + // be read without potentially crossing a page boundary. + tbb [pc, r3] +.Lstrcpy_unaligned_branchtable: + .byte 0 + .byte ((.Lstrcpy_unalign7 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign6 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign5 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign4 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign3 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign2 - .Lstrcpy_unaligned_branchtable)/2) + .byte ((.Lstrcpy_unalign1 - .Lstrcpy_unaligned_branchtable)/2) + + .p2align 2 + // Can read 7 bytes before possibly crossing a page. +.Lstrcpy_unalign7: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + ldrb r3, [r1] + cbz r3, .Lstrcpy_unalign7_copy5bytes + ldrb r4, [r1, #1] + cbz r4, .Lstrcpy_unalign7_copy6bytes + ldrb r5, [r1, #2] + cbz r5, .Lstrcpy_unalign7_copy7bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + lsrs ip, r3, #24 + stmia r0!, {r2, r3} + beq .Lstrcpy_unalign_return + b .Lstrcpy_unalign7 + +.Lstrcpy_unalign7_copy5bytes: + stmia r0!, {r2} + strb r3, [r0] +.Lstrcpy_unalign_return: + m_ret inst=pop + +.Lstrcpy_unalign7_copy6bytes: + stmia r0!, {r2} + strb r3, [r0], #1 + strb r4, [r0], #1 + m_ret inst=pop + +.Lstrcpy_unalign7_copy7bytes: + stmia r0!, {r2} + strb r3, [r0], #1 + strb r4, [r0], #1 + strb r5, [r0], #1 + m_ret inst=pop + + .p2align 2 + // Can read 6 bytes before possibly crossing a page. +.Lstrcpy_unalign6: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstrcpy_unalign_copy5bytes + ldrb r5, [r1, #1] + cbz r5, .Lstrcpy_unalign_copy6bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + tst r3, #0xff0000 + beq .Lstrcpy_unalign6_copy7bytes + lsrs ip, r3, #24 + stmia r0!, {r2, r3} + beq .Lstrcpy_unalign_return + b .Lstrcpy_unalign6 + +.Lstrcpy_unalign6_copy7bytes: + stmia r0!, {r2} + strh r3, [r0], #2 + lsr r3, #16 + strb r3, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 5 bytes before possibly crossing a page. +.Lstrcpy_unalign5: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstrcpy_unalign_copy5bytes + + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_unalign5 + +.Lstrcpy_unalign_copy5bytes: + stmia r0!, {r2} + strb r4, [r0] + m_ret inst=pop + +.Lstrcpy_unalign_copy6bytes: + stmia r0!, {r2} + strb r4, [r0], #1 + strb r5, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 4 bytes before possibly crossing a page. +.Lstrcpy_unalign4: + ldmia r1!, {r2} + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + ldmia r1!, {r3} + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_unalign4 + + .p2align 2 + // Can read 3 bytes before possibly crossing a page. +.Lstrcpy_unalign3: + ldrb r2, [r1] + cbz r2, .Lstrcpy_unalign3_copy1byte + ldrb r3, [r1, #1] + cbz r3, .Lstrcpy_unalign3_copy2bytes + ldrb r4, [r1, #2] + cbz r4, .Lstrcpy_unalign3_copy3bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + lsrs lr, r2, #24 + beq .Lstrcpy_unalign_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_unalign3 + +.Lstrcpy_unalign3_copy1byte: + strb r2, [r0] + m_ret inst=pop + +.Lstrcpy_unalign3_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_ret inst=pop + +.Lstrcpy_unalign3_copy3bytes: + strb r2, [r0], #1 + strb r3, [r0], #1 + strb r4, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 2 bytes before possibly crossing a page. +.Lstrcpy_unalign2: + ldrb r2, [r1] + cbz r2, .Lstrcpy_unalign_copy1byte + ldrb r3, [r1, #1] + cbz r3, .Lstrcpy_unalign_copy2bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + pld [r1, #64] + + tst r2, #0xff0000 + beq .Lstrcpy_unalign_copy3bytes + lsrs ip, r2, #24 + beq .Lstrcpy_unalign_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_unalign2 + + .p2align 2 + // Can read 1 byte before possibly crossing a page. +.Lstrcpy_unalign1: + ldrb r2, [r1] + cbz r2, .Lstrcpy_unalign_copy1byte + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcpy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstrcpy_unalign1 + +.Lstrcpy_unalign_copy1byte: + strb r2, [r0] + m_ret inst=pop + +.Lstrcpy_unalign_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_ret inst=pop + +.Lstrcpy_unalign_copy3bytes: + strh r2, [r0], #2 + lsr r2, #16 + strb r2, [r0] + m_ret inst=pop + +.Lstrcpy_unalign_copy4bytes: + stmia r0, {r2} + m_ret inst=pop + +.Lstrcat_align_src: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .Lstrcat_align_to_32 + ldrb r2, [r0], #1 + cbz r2, .Lstrcat_r0_update + +.Lstrcat_align_to_32: + bcc .Lstrcat_align_to_64 + ldrb r2, [r0], #1 + cbz r2, .Lstrcat_r0_update + ldrb r2, [r0], #1 + cbz r2, .Lstrcat_r0_update + +.Lstrcat_align_to_64: + tst r3, #4 + beq .Lstrcat_mainloop + ldr r3, [r0], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstrcat_zero_in_second_register + b .Lstrcat_mainloop + +.Lstrcat_r0_update: + sub r0, r0, #1 + b .Lstrcat_r0_scan_done +END(strcat)
diff --git a/libc/arch-arm/cortex-a9/bionic/strcmp.S b/libc/arch-arm/cortex-a9/bionic/strcmp.S new file mode 100644 index 0000000..ba191d6 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/strcmp.S
@@ -0,0 +1,547 @@ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +#ifdef __ARMEB__ +#define S2LOMEM lsl +#define S2LOMEMEQ lsleq +#define S2HIMEM lsr +#define MSB 0x000000ff +#define LSB 0xff000000 +#define BYTE0_OFFSET 24 +#define BYTE1_OFFSET 16 +#define BYTE2_OFFSET 8 +#define BYTE3_OFFSET 0 +#else /* not __ARMEB__ */ +#define S2LOMEM lsr +#define S2LOMEMEQ lsreq +#define S2HIMEM lsl +#define BYTE0_OFFSET 0 +#define BYTE1_OFFSET 8 +#define BYTE2_OFFSET 16 +#define BYTE3_OFFSET 24 +#define MSB 0xff000000 +#define LSB 0x000000ff +#endif /* not __ARMEB__ */ + +.syntax unified + +#if defined (__thumb__) + .thumb + .thumb_func +#endif + +ENTRY(strcmp) + /* Use LDRD whenever possible. */ + +/* The main thing to look out for when comparing large blocks is that + the loads do not cross a page boundary when loading past the index + of the byte with the first difference or the first string-terminator. + + For example, if the strings are identical and the string-terminator + is at index k, byte by byte comparison will not load beyond address + s1+k and s2+k; word by word comparison may load up to 3 bytes beyond + k; double word - up to 7 bytes. If the load of these bytes crosses + a page boundary, it might cause a memory fault (if the page is not mapped) + that would not have happened in byte by byte comparison. + + If an address is (double) word aligned, then a load of a (double) word + from that address will not cross a page boundary. + Therefore, the algorithm below considers word and double-word alignment + of strings separately. */ + +/* High-level description of the algorithm. + + * The fast path: if both strings are double-word aligned, + use LDRD to load two words from each string in every loop iteration. + * If the strings have the same offset from a word boundary, + use LDRB to load and compare byte by byte until + the first string is aligned to a word boundary (at most 3 bytes). + This is optimized for quick return on short unaligned strings. + * If the strings have the same offset from a double-word boundary, + use LDRD to load two words from each string in every loop iteration, as in the fast path. + * If the strings do not have the same offset from a double-word boundary, + load a word from the second string before the loop to initialize the queue. + Use LDRD to load two words from every string in every loop iteration. + Inside the loop, load the second word from the second string only after comparing + the first word, using the queued value, to guarantee safety across page boundaries. + * If the strings do not have the same offset from a word boundary, + use LDR and a shift queue. Order of loads and comparisons matters, + similarly to the previous case. + + * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value. + * The only difference between ARM and Thumb modes is the use of CBZ instruction. + * The only difference between big and little endian is the use of REV in little endian + to compute the return value, instead of MOV. +*/ + + .macro m_cbz reg label +#ifdef __thumb2__ + cbz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + beq \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbz */ + + .macro m_cbnz reg label +#ifdef __thumb2__ + cbnz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + bne \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbnz */ + + .macro init + /* Macro to save temporary registers and prepare magic values. */ + subs sp, sp, #16 + .cfi_def_cfa_offset 16 + strd r4, r5, [sp, #8] + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + strd r6, r7, [sp] + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + mvn r6, #0 /* all F */ + mov r7, #0 /* all 0 */ + .endm /* init */ + + .macro magic_compare_and_branch w1 w2 label + /* Macro to compare registers w1 and w2 and conditionally branch to label. */ + cmp \w1, \w2 /* Are w1 and w2 the same? */ + magic_find_zero_bytes \w1 + it eq + cmpeq ip, #0 /* Is there a zero byte in w1? */ + bne \label + .endm /* magic_compare_and_branch */ + + .macro magic_find_zero_bytes w1 + /* Macro to find all-zero bytes in w1, result is in ip. */ + uadd8 ip, \w1, r6 + sel ip, r7, r6 + .endm /* magic_find_zero_bytes */ + + .macro setup_return w1 w2 +#ifdef __ARMEB__ + mov r1, \w1 + mov r2, \w2 +#else /* not __ARMEB__ */ + rev r1, \w1 + rev r2, \w2 +#endif /* not __ARMEB__ */ + .endm /* setup_return */ + + pld [r0, #0] + pld [r1, #0] + + /* Are both strings double-word aligned? */ + orr ip, r0, r1 + tst ip, #7 + bne .L_do_align + + /* Fast path. */ + init + +.L_doubleword_aligned: + + /* Get here when the strings to compare are double-word aligned. */ + /* Compare two words in every iteration. */ + .p2align 2 +2: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string. */ + ldrd r2, r3, [r0], #8 + ldrd r4, r5, [r1], #8 + + magic_compare_and_branch w1=r2, w2=r4, label=.L_return_24 + magic_compare_and_branch w1=r3, w2=r5, label=.L_return_35 + b 2b + +.L_do_align: + /* Is the first string word-aligned? */ + ands ip, r0, #3 + beq .L_word_aligned_r0 + + /* Fast compare byte by byte until the first string is word-aligned. */ + /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes + to read until the next word boundary is 4-ip. */ + bic r0, r0, #3 + ldr r2, [r0], #4 + lsls ip, ip, #31 + beq .L_byte2 + bcs .L_byte3 + +.L_byte1: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE1_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte2: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE2_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte3: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE3_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbnz reg=r3, label=.L_word_aligned_r0 + +.L_fast_return: + mov r0, ip + bx lr + +.L_word_aligned_r0: + init + /* The first string is word-aligned. */ + /* Is the second string word-aligned? */ + ands ip, r1, #3 + bne .L_strcmp_unaligned + +.L_word_aligned: + /* The strings are word-aligned. */ + /* Is the first string double-word aligned? */ + tst r0, #4 + beq .L_doubleword_aligned_r0 + + /* If r0 is not double-word aligned yet, align it by loading + and comparing the next word from each string. */ + ldr r2, [r0], #4 + ldr r4, [r1], #4 + magic_compare_and_branch w1=r2 w2=r4 label=.L_return_24 + +.L_doubleword_aligned_r0: + /* Get here when r0 is double-word aligned. */ + /* Is r1 doubleword_aligned? */ + tst r1, #4 + beq .L_doubleword_aligned + + /* Get here when the strings to compare are word-aligned, + r0 is double-word aligned, but r1 is not double-word aligned. */ + + /* Initialize the queue. */ + ldr r5, [r1], #4 + + /* Compare two words in every iteration. */ + .p2align 2 +3: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string and compare. */ + ldrd r2, r3, [r0], #8 + magic_compare_and_branch w1=r2 w2=r5 label=.L_return_25 + ldrd r4, r5, [r1], #8 + magic_compare_and_branch w1=r3 w2=r4 label=.L_return_34 + b 3b + + .macro miscmp_word offsetlo offsethi + /* Macro to compare misaligned strings. */ + /* r0, r1 are word-aligned, and at least one of the strings + is not double-word aligned. */ + /* Compare one word in every loop iteration. */ + /* OFFSETLO is the original bit-offset of r1 from a word-boundary, + OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word). */ + + /* Initialize the shift queue. */ + ldr r5, [r1], #4 + + /* Compare one word from each string in every loop iteration. */ + .p2align 2 +7: + ldr r3, [r0], #4 + S2LOMEM r5, r5, #\offsetlo + magic_find_zero_bytes w1=r3 + cmp r7, ip, S2HIMEM #\offsetlo + and r2, r3, r6, S2LOMEM #\offsetlo + it eq + cmpeq r2, r5 + bne .L_return_25 + ldr r5, [r1], #4 + cmp ip, #0 + eor r3, r2, r3 + S2HIMEM r2, r5, #\offsethi + it eq + cmpeq r3, r2 + bne .L_return_32 + b 7b + .endm /* miscmp_word */ + +.L_return_32: + setup_return w1=r3, w2=r2 + b .L_do_return +.L_return_34: + setup_return w1=r3, w2=r4 + b .L_do_return +.L_return_25: + setup_return w1=r2, w2=r5 + b .L_do_return +.L_return_35: + setup_return w1=r3, w2=r5 + b .L_do_return +.L_return_24: + setup_return w1=r2, w2=r4 + +.L_do_return: + +#ifdef __ARMEB__ + mov r0, ip +#else /* not __ARMEB__ */ + rev r0, ip +#endif /* not __ARMEB__ */ + + /* Restore temporaries early, before computing the return value. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + /* There is a zero or a different byte between r1 and r2. */ + /* r0 contains a mask of all-zero bytes in r1. */ + /* Using r0 and not ip here because cbz requires low register. */ + m_cbz reg=r0, label=.L_compute_return_value + clz r0, r0 + /* r0 contains the number of bits on the left of the first all-zero byte in r1. */ + rsb r0, r0, #24 + /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1. */ + lsr r1, r1, r0 + lsr r2, r2, r0 + +.L_compute_return_value: + movs r0, #1 + cmp r1, r2 + /* The return value is computed as follows. + If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return. + If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0, + which means r0:=r0-r0-1 and r0 is #-1 at return. + If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1, + which means r0:=r0-r0 and r0 is #0 at return. + (C==0 and Z==1) cannot happen because the carry bit is "not borrow". */ + it ls + sbcls r0, r0, r0 + bx lr + + /* The code from the previous version of strcmp.S handles all of the + * cases where the first string and seconds string cannot both be + * aligned to a word boundary faster than the new algorithm. See + * bionic/libc/arch-arm/cortex-a15/bionic/strcmp.S for the unedited + * version of the code. + */ +.L_strcmp_unaligned: + wp1 .req r0 + wp2 .req r1 + b1 .req r2 + w1 .req r4 + w2 .req r5 + t1 .req ip + @ r3 is scratch + +2: + mov b1, #1 + orr b1, b1, b1, lsl #8 + orr b1, b1, b1, lsl #16 + + and t1, wp2, #3 + bic wp2, wp2, #3 + ldr w1, [wp1], #4 + ldr w2, [wp2], #4 + cmp t1, #2 + beq 2f + bhi 3f + + /* Critical inner Loop: Block with 3 bytes initial overlap */ + .p2align 2 +1: + bic t1, w1, #MSB + cmp t1, w2, S2LOMEM #8 + sub r3, w1, b1 + bic r3, r3, w1 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, S2HIMEM #24 + bne 6f + ldr w1, [wp1], #4 + b 1b +4: + S2LOMEM w2, w2, #8 + b 8f + +5: +#ifdef __ARMEB__ + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #0xff000000 + itt ne + tstne w1, #0x00ff0000 + tstne w1, #0x0000ff00 + beq 7f +#else + bics r3, r3, #0xff000000 + bne 7f +#endif + ldrb w2, [wp2] + S2LOMEM t1, w1, #24 +#ifdef __ARMEB__ + lsl w2, w2, #24 +#endif + b 8f + +6: + S2LOMEM t1, w1, #24 + and w2, w2, #LSB + b 8f + + /* Critical inner Loop: Block with 2 bytes initial overlap */ + .p2align 2 +2: + S2HIMEM t1, w1, #16 + sub r3, w1, b1 + S2LOMEM t1, t1, #16 + bic r3, r3, w1 + cmp t1, w2, S2LOMEM #16 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, S2HIMEM #16 + bne 6f + ldr w1, [wp1], #4 + b 2b + +5: +#ifdef __ARMEB__ + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #0xff000000 + it ne + tstne w1, #0x00ff0000 + beq 7f +#else + lsls r3, r3, #16 + bne 7f +#endif + ldrh w2, [wp2] + S2LOMEM t1, w1, #16 +#ifdef __ARMEB__ + lsl w2, w2, #16 +#endif + b 8f + +6: + S2HIMEM w2, w2, #16 + S2LOMEM t1, w1, #16 +4: + S2LOMEM w2, w2, #16 + b 8f + + /* Critical inner Loop: Block with 1 byte initial overlap */ + .p2align 2 +3: + and t1, w1, #LSB + cmp t1, w2, S2LOMEM #24 + sub r3, w1, b1 + bic r3, r3, w1 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, S2HIMEM #8 + bne 6f + ldr w1, [wp1], #4 + b 3b +4: + S2LOMEM w2, w2, #24 + b 8f +5: + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #LSB + beq 7f + ldr w2, [wp2], #4 +6: + S2LOMEM t1, w1, #8 + bic w2, w2, #MSB + b 8f +7: + mov r0, #0 + + /* Restore registers and stack. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + bx lr + +8: + and r2, t1, #LSB + and r0, w2, #LSB + cmp r0, #1 + it cs + cmpcs r0, r2 + itt eq + S2LOMEMEQ t1, t1, #8 + S2LOMEMEQ w2, w2, #8 + beq 8b + sub r0, r2, r0 + + /* Restore registers and stack. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + + bx lr +END(strcmp)
diff --git a/libc/arch-arm/cortex-a9/bionic/strcpy.S b/libc/arch-arm/cortex-a9/bionic/strcpy.S new file mode 100644 index 0000000..951face --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/strcpy.S
@@ -0,0 +1,30 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define STRCPY +#include "string_copy.S"
diff --git a/libc/arch-arm/cortex-a9/bionic/string_copy.S b/libc/arch-arm/cortex-a9/bionic/string_copy.S new file mode 100644 index 0000000..642db0f --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/string_copy.S
@@ -0,0 +1,542 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(STPCPY) && !defined(STRCPY) +#error "Either STPCPY or STRCPY must be defined." +#endif + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +#if defined(STPCPY) + .macro m_push + push {r4, r5, lr} + .cfi_def_cfa_offset 12 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset lr, 8 + .endm // m_push +#else + .macro m_push + push {r0, r4, r5, lr} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r0, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset r5, 8 + .cfi_rel_offset lr, 12 + .endm // m_push +#endif + +#if defined(STPCPY) + .macro m_ret inst + \inst {r4, r5, pc} + .endm // m_ret +#else + .macro m_ret inst + \inst {r0, r4, r5, pc} + .endm // m_ret +#endif + + .macro m_copy_byte reg, cmd, label + ldrb \reg, [r1], #1 + strb \reg, [r0], #1 + \cmd \reg, \label + .endm // m_copy_byte + +#if defined(STPCPY) +ENTRY(stpcpy) +#else +ENTRY(strcpy) +#endif + // Unroll the first 8 bytes that will be copied. + m_push + m_copy_byte reg=r2, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r5, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r2, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r3, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r4, cmd=cbz, label=.Lstringcopy_finish + m_copy_byte reg=r5, cmd=cbnz, label=.Lstringcopy_continue + +.Lstringcopy_finish: +#if defined(STPCPY) + sub r0, r0, #1 +#endif + m_ret inst=pop + +.Lstringcopy_continue: + pld [r1, #0] + ands r3, r0, #7 + bne .Lstringcopy_align_dst + +.Lstringcopy_check_src_align: + // At this point dst is aligned to a double word, check if src + // is also aligned to a double word. + ands r3, r1, #7 + bne .Lstringcopy_unaligned_copy + + .p2align 2 +.Lstringcopy_mainloop: + ldmia r1!, {r2, r3} + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_mainloop + +.Lstringcopy_zero_in_first_register: + lsls lr, ip, #17 + itt ne + strbne r2, [r0] + m_ret inst=popne + itt cs +#if defined(STPCPY) + strhcs r2, [r0], #1 +#else + strhcs r2, [r0] +#endif + m_ret inst=popcs + lsls ip, ip, #1 + itt eq +#if defined(STPCPY) + streq r2, [r0], #3 +#else + streq r2, [r0] +#endif + m_ret inst=popeq + strh r2, [r0], #2 + lsr r3, r2, #16 + strb r3, [r0] + m_ret inst=pop + +.Lstringcopy_zero_in_second_register: + lsls lr, ip, #17 + ittt ne + stmiane r0!, {r2} + strbne r3, [r0] + m_ret inst=popne + ittt cs + strcs r2, [r0], #4 +#if defined(STPCPY) + strhcs r3, [r0], #1 +#else + strhcs r3, [r0] +#endif + m_ret inst=popcs + lsls ip, ip, #1 +#if defined(STPCPY) + ittt eq +#else + itt eq +#endif + stmiaeq r0, {r2, r3} +#if defined(STPCPY) + addeq r0, r0, #7 +#endif + m_ret inst=popeq + stmia r0!, {r2} + strh r3, [r0], #2 + lsr r4, r3, #16 + strb r4, [r0] + m_ret inst=pop + +.Lstringcopy_align_dst: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .Lstringcopy_align_to_32 + + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + +.Lstringcopy_align_to_32: + bcc .Lstringcopy_align_to_64 + + ldrb r4, [r1], #1 + strb r4, [r0], #1 + cmp r4, #0 +#if defined(STPCPY) + itt eq + subeq r0, r0, #1 +#else + it eq +#endif + m_ret inst=popeq + ldrb r5, [r1], #1 + strb r5, [r0], #1 + cmp r5, #0 +#if defined(STPCPY) + itt eq + subeq r0, r0, #1 +#else + it eq +#endif + m_ret inst=popeq + +.Lstringcopy_align_to_64: + tst r3, #4 + beq .Lstringcopy_check_src_align + // Read one byte at a time since we don't have any idea about the alignment + // of the source and we don't want to read into a different page. + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + ldrb r2, [r1], #1 + strb r2, [r0], #1 + cbz r2, .Lstringcopy_complete + b .Lstringcopy_check_src_align + +.Lstringcopy_complete: +#if defined(STPCPY) + sub r0, r0, #1 +#endif + m_ret inst=pop + +.Lstringcopy_unaligned_copy: + // Dst is aligned to a double word, while src is at an unknown alignment. + // There are 7 different versions of the unaligned copy code + // to prevent overreading the src. The mainloop of every single version + // will store 64 bits per loop. The difference is how much of src can + // be read without potentially crossing a page boundary. + tbb [pc, r3] +.Lstringcopy_unaligned_branchtable: + .byte 0 + .byte ((.Lstringcopy_unalign7 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign6 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign5 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign4 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign3 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign2 - .Lstringcopy_unaligned_branchtable)/2) + .byte ((.Lstringcopy_unalign1 - .Lstringcopy_unaligned_branchtable)/2) + + .p2align 2 + // Can read 7 bytes before possibly crossing a page. +.Lstringcopy_unalign7: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r3, [r1] + cbz r3, .Lstringcopy_unalign7_copy5bytes + ldrb r4, [r1, #1] + cbz r4, .Lstringcopy_unalign7_copy6bytes + ldrb r5, [r1, #2] + cbz r5, .Lstringcopy_unalign7_copy7bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + lsrs ip, r3, #24 + stmia r0!, {r2, r3} +#if defined(STPCPY) + beq .Lstringcopy_finish +#else + beq .Lstringcopy_unalign_return +#endif + b .Lstringcopy_unalign7 + +.Lstringcopy_unalign7_copy5bytes: + stmia r0!, {r2} + strb r3, [r0] +.Lstringcopy_unalign_return: + m_ret inst=pop + +.Lstringcopy_unalign7_copy6bytes: + stmia r0!, {r2} + strb r3, [r0], #1 + strb r4, [r0] + m_ret inst=pop + +.Lstringcopy_unalign7_copy7bytes: + stmia r0!, {r2} + strb r3, [r0], #1 + strb r4, [r0], #1 + strb r5, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 6 bytes before possibly crossing a page. +.Lstringcopy_unalign6: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstringcopy_unalign_copy5bytes + ldrb r5, [r1, #1] + cbz r5, .Lstringcopy_unalign_copy6bytes + + ldr r3, [r1], #4 + pld [r1, #64] + + tst r3, #0xff0000 + beq .Lstringcopy_unalign6_copy7bytes + lsrs ip, r3, #24 + stmia r0!, {r2, r3} +#if defined(STPCPY) + beq .Lstringcopy_finish +#else + beq .Lstringcopy_unalign_return +#endif + b .Lstringcopy_unalign6 + +.Lstringcopy_unalign6_copy7bytes: + stmia r0!, {r2} + strh r3, [r0], #2 + lsr r3, #16 + strb r3, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 5 bytes before possibly crossing a page. +.Lstringcopy_unalign5: + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldrb r4, [r1] + cbz r4, .Lstringcopy_unalign_copy5bytes + + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_unalign5 + +.Lstringcopy_unalign_copy5bytes: + stmia r0!, {r2} + strb r4, [r0] + m_ret inst=pop + +.Lstringcopy_unalign_copy6bytes: + stmia r0!, {r2} + strb r4, [r0], #1 + strb r5, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 4 bytes before possibly crossing a page. +.Lstringcopy_unalign4: + ldmia r1!, {r2} + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + ldmia r1!, {r3} + pld [r1, #64] + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_unalign4 + + .p2align 2 + // Can read 3 bytes before possibly crossing a page. +.Lstringcopy_unalign3: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign3_copy1byte + ldrb r3, [r1, #1] + cbz r3, .Lstringcopy_unalign3_copy2bytes + ldrb r4, [r1, #2] + cbz r4, .Lstringcopy_unalign3_copy3bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + lsrs lr, r2, #24 + beq .Lstringcopy_unalign_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_unalign3 + +.Lstringcopy_unalign3_copy1byte: + strb r2, [r0] + m_ret inst=pop + +.Lstringcopy_unalign3_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_ret inst=pop + +.Lstringcopy_unalign3_copy3bytes: + strb r2, [r0], #1 + strb r3, [r0], #1 + strb r4, [r0] + m_ret inst=pop + + .p2align 2 + // Can read 2 bytes before possibly crossing a page. +.Lstringcopy_unalign2: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign_copy1byte + ldrb r3, [r1, #1] + cbz r3, .Lstringcopy_unalign_copy2bytes + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + pld [r1, #64] + + tst r2, #0xff0000 + beq .Lstringcopy_unalign_copy3bytes + lsrs ip, r2, #24 + beq .Lstringcopy_unalign_copy4bytes + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_unalign2 + + .p2align 2 + // Can read 1 byte before possibly crossing a page. +.Lstringcopy_unalign1: + ldrb r2, [r1] + cbz r2, .Lstringcopy_unalign_copy1byte + + ldr r2, [r1], #4 + ldr r3, [r1], #4 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .Lstringcopy_zero_in_second_register + + stmia r0!, {r2, r3} + b .Lstringcopy_unalign1 + +.Lstringcopy_unalign_copy1byte: + strb r2, [r0] + m_ret inst=pop + +.Lstringcopy_unalign_copy2bytes: + strb r2, [r0], #1 + strb r3, [r0] + m_ret inst=pop + +.Lstringcopy_unalign_copy3bytes: + strh r2, [r0], #2 + lsr r2, #16 + strb r2, [r0] + m_ret inst=pop + +.Lstringcopy_unalign_copy4bytes: + stmia r0, {r2} +#if defined(STPCPY) + add r0, r0, #3 +#endif + m_ret inst=pop +#if defined(STPCPY) +END(stpcpy) +#else +END(strcpy) +#endif
diff --git a/libc/arch-arm/cortex-a9/bionic/strlen.S b/libc/arch-arm/cortex-a9/bionic/strlen.S new file mode 100644 index 0000000..b92b043 --- /dev/null +++ b/libc/arch-arm/cortex-a9/bionic/strlen.S
@@ -0,0 +1,167 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +ENTRY(strlen) + pld [r0, #0] + mov r1, r0 + + ands r3, r0, #7 + bne align_src + + .p2align 2 +mainloop: + ldmia r1!, {r2, r3} + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne zero_in_second_register + b mainloop + +zero_in_first_register: + sub r0, r1, r0 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq check_byte1_reg1 + + sub r0, r0, #8 + bx lr + +check_byte1_reg1: + bcc check_byte2_reg1 + + sub r0, r0, #7 + bx lr + +check_byte2_reg1: + // Check for zero in byte 2. + tst ip, #0x800000 + itt ne + subne r0, r0, #6 + bxne lr + sub r0, r0, #5 + bx lr + +zero_in_second_register: + sub r0, r1, r0 + // Check for zero in byte 0. + lsls r2, ip, #17 + beq check_byte1_reg2 + + sub r0, r0, #4 + bx lr + +check_byte1_reg2: + bcc check_byte2_reg2 + + sub r0, r0, #3 + bx lr + +check_byte2_reg2: + // Check for zero in byte 2. + tst ip, #0x800000 + itt ne + subne r0, r0, #2 + bxne lr + sub r0, r0, #1 + bx lr + +align_src: + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq align_to_32 + + ldrb r2, [r1], #1 + cbz r2, done + +align_to_32: + bcc align_to_64 + + ldrb r2, [r1], #1 + cbz r2, done + ldrb r2, [r1], #1 + cbz r2, done + +align_to_64: + tst r3, #4 + beq mainloop + ldr r2, [r1], #4 + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne zero_in_second_register + b mainloop + +done: + sub r0, r1, r0 + sub r0, r0, #1 + bx lr +END(strlen)
diff --git a/libc/arch-arm/denver/bionic/__strcat_chk.S b/libc/arch-arm/denver/bionic/__strcat_chk.S new file mode 100644 index 0000000..9f7db59 --- /dev/null +++ b/libc/arch-arm/denver/bionic/__strcat_chk.S
@@ -0,0 +1,194 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of src string, then get the source of the dst string. +// Check that the two lengths together don't exceed the threshold, then +// do a memcpy of the data. +ENTRY(__strcat_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + push {r4, r5} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + + mov lr, r2 + + // Save the dst register to r5 + mov r5, r0 + + // Zero out r4 + eor r4, r4, r4 + + // r1 contains the address of the string to count. +.L_strlen_start: + mov r0, r1 + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r1], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r1, r0 + sub r3, r3, #1 + b .L_finish + +.L_zero_in_first_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_finish + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_finish + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_finish + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_finish + +.L_zero_in_second_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_finish + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_finish + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_finish + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_finish: + cmp r4, #0 + bne .L_strlen_done + + // Time to get the dst string length. + mov r1, r5 + + // Save the original source address to r5. + mov r5, r0 + + // Save the current length (adding 1 for the terminator). + add r4, r3, #1 + b .L_strlen_start + + // r0 holds the pointer to the dst string. + // r3 holds the dst string length. + // r4 holds the src string length + 1. +.L_strlen_done: + add r2, r3, r4 + cmp r2, lr + itt hi + movhi r0, lr + bhi __strcat_chk_fail + + // Set up the registers for the memcpy code. + mov r1, r5 + pld [r1, #64] + mov r2, r4 + add r0, r0, r3 + pop {r4, r5} +END(__strcat_chk) + +#define MEMCPY_BASE __strcat_chk_memcpy_base +#define MEMCPY_BASE_ALIGNED __strcat_chk_memcpy_base_aligned + +#include "memcpy_base.S"
diff --git a/libc/arch-arm/denver/bionic/__strcpy_chk.S b/libc/arch-arm/denver/bionic/__strcpy_chk.S new file mode 100644 index 0000000..9b7ea91 --- /dev/null +++ b/libc/arch-arm/denver/bionic/__strcpy_chk.S
@@ -0,0 +1,164 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of the source string first, then do a memcpy of the data +// instead of a strcpy. +ENTRY(__strcpy_chk) + pld [r0, #0] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + mov lr, r2 + mov r0, r1 + + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r0], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r0], #8 + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r0, r1 + sub r3, r3, #1 + b .L_check_size + +.L_zero_in_first_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_check_size + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_check_size + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_check_size + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_check_size + +.L_zero_in_second_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_check_size + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_check_size + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_check_size + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_check_size: + pld [r1, #0] + pld [r1, #64] + ldr r0, [sp] + + // Add 1 for copy length to get the string terminator. + add r2, r3, #1 + + cmp r2, lr + itt hi + movhi r0, r2 + bhi __strcpy_chk_fail + + // Fall through into the memcpy_base function. +END(__strcpy_chk) + +#define MEMCPY_BASE __strcpy_chk_memcpy_base +#define MEMCPY_BASE_ALIGNED __strcpy_chk_memcpy_base_aligned +#include "memcpy_base.S"
diff --git a/libc/arch-arm/denver/bionic/memcpy.S b/libc/arch-arm/denver/bionic/memcpy.S new file mode 100644 index 0000000..d4e0fb4 --- /dev/null +++ b/libc/arch-arm/denver/bionic/memcpy.S
@@ -0,0 +1,86 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +// Prototype: void *memcpy (void *dst, const void *src, size_t count). + +#include <private/bionic_asm.h> + + .text + .syntax unified + .fpu neon + +ENTRY(__memcpy_chk) + cmp r2, r3 + bls memcpy + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + pld [r1, #64] + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 +END(memcpy) + +#define MEMCPY_BASE __memcpy_base +#define MEMCPY_BASE_ALIGNED __memcpy_base_aligned +#include "memcpy_base.S"
diff --git a/libc/arch-arm/denver/bionic/memcpy_base.S b/libc/arch-arm/denver/bionic/memcpy_base.S new file mode 100644 index 0000000..2abb486 --- /dev/null +++ b/libc/arch-arm/denver/bionic/memcpy_base.S
@@ -0,0 +1,234 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * Copyright (c) 2013-2014, NVIDIA Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define CACHE_LINE_SIZE (64) +#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*6) + +ENTRY_PRIVATE(MEMCPY_BASE) + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + cmp r2, #0 + beq .L_memcpy_done + cmp r0, r1 + beq .L_memcpy_done + + /* preload next cache line */ + pld [r1, #CACHE_LINE_SIZE*1] + + /* Deal with very small blocks (< 32bytes) asap */ + cmp r2, #32 + blo .L_memcpy_lt_32bytes + /* no need to align if len < 128 bytes */ + cmp r2, #128 + blo .L_memcpy_lt_128bytes + + /* large copy, align dest to 64 byte boundry */ + pld [r1, #CACHE_LINE_SIZE*2] + rsb r3, r0, #0 + ands r3, r3, #0x3F + pld [r1, #CACHE_LINE_SIZE*3] + beq .L_memcpy_dispatch + sub r2, r2, r3 + /* copy 1 byte */ + movs ip, r3, lsl #31 + itt mi + ldrbmi ip, [r1], #1 + strbmi ip, [r0], #1 + /* copy 2 bytes */ + itt cs + ldrhcs ip, [r1], #2 + strhcs ip, [r0], #2 + /* copy 4 bytes */ + movs ip, r3, lsl #29 + itt mi + ldrmi ip, [r1], #4 + strmi ip, [r0], #4 + /* copy 8 bytes */ + bcc 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0, :64]! +1: /* copy 16 bytes */ + movs ip, r3, lsl #27 + bpl 1f + vld1.8 {q0}, [r1]! + vst1.8 {q0}, [r0, :128]! +1: /* copy 32 bytes */ + bcc .L_memcpy_dispatch + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + +.L_memcpy_dispatch: + // pre-decrement by 128 to detect nearly-done condition easily, but + // also need to check if we have less than 128 bytes left at this + // point due to alignment code above + subs r2, r2, #128 + blo .L_memcpy_lt_128presub + + // Denver does better if both source and dest are aligned so + // we'll special-case that even though the code is virually identical + tst r1, #0xF + bne .L_memcpy_neon_unalign_src_pld + + // DRAM memcpy should be throttled slightly to get full bandwidth + // + cmp r2, #32768 + bhi .L_memcpy_neon_unalign_src_pld + .align 4 +1: + /* copy 128 bytes in each loop */ + subs r2, r2, #128 + + /* preload a cache line */ + pld [r1, #PREFETCH_DISTANCE] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1, :128]! + vst1.8 {q0, q1}, [r0, :256]! + vld1.8 {q0, q1}, [r1, :128]! + vst1.8 {q0, q1}, [r0, :256]! + /* preload a cache line */ + pld [r1, #PREFETCH_DISTANCE] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1, :128]! + vst1.8 {q0, q1}, [r0, :256]! + vld1.8 {q0, q1}, [r1, :128]! + vst1.8 {q0, q1}, [r0, :256]! + + bhs 1b + adds r2, r2, #128 + bne .L_memcpy_lt_128bytes_align + pop {r0, pc} + + .align 4 +.L_memcpy_neon_unalign_src_pld: +1: + /* copy 128 bytes in each loop */ + subs r2, r2, #128 + + /* preload a cache line */ + pld [r1, #PREFETCH_DISTANCE] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + /* preload a cache line */ + pld [r1, #PREFETCH_DISTANCE] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + + bhs 1b + adds r2, r2, #128 + bne .L_memcpy_lt_128bytes_align + pop {r0, pc} + +.L_memcpy_lt_128presub: + add r2, r2, #128 +.L_memcpy_lt_128bytes_align: + /* copy 64 bytes */ + movs ip, r2, lsl #26 + bcc 1f + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! +1: /* copy 32 bytes */ + bpl 1f + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0, :256]! +1: /* copy 16 bytes */ + movs ip, r2, lsl #28 + bcc 1f + vld1.8 {q0}, [r1]! + vst1.8 {q0}, [r0, :128]! +1: /* copy 8 bytes */ + bpl 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0, :64]! +1: /* copy 4 bytes */ + tst r2, #4 + itt ne + ldrne ip, [r1], #4 + strne ip, [r0], #4 + /* copy 2 bytes */ + movs ip, r2, lsl #31 + itt cs + ldrhcs ip, [r1], #2 + strhcs ip, [r0], #2 + /* copy 1 byte */ + itt mi + ldrbmi ip, [r1] + strbmi ip, [r0] + + pop {r0, pc} + +.L_memcpy_lt_128bytes: + /* copy 64 bytes */ + movs ip, r2, lsl #26 + bcc 1f + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0]! + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0]! +1: /* copy 32 bytes */ + bpl .L_memcpy_lt_32bytes + vld1.8 {q0, q1}, [r1]! + vst1.8 {q0, q1}, [r0]! +.L_memcpy_lt_32bytes: + /* copy 16 bytes */ + movs ip, r2, lsl #28 + bcc 1f + vld1.8 {q0}, [r1]! + vst1.8 {q0}, [r0]! +1: /* copy 8 bytes */ + bpl 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0]! +1: /* copy 4 bytes */ + tst r2, #4 + itt ne + ldrne ip, [r1], #4 + strne ip, [r0], #4 + /* copy 2 bytes */ + movs ip, r2, lsl #31 + itt cs + ldrhcs ip, [r1], #2 + strhcs ip, [r0], #2 + /* copy 1 byte */ + itt mi + ldrbmi ip, [r1] + strbmi ip, [r0] + +.L_memcpy_done: + pop {r0, pc} +END(MEMCPY_BASE)
diff --git a/libc/arch-arm/denver/bionic/memmove.S b/libc/arch-arm/denver/bionic/memmove.S new file mode 100644 index 0000000..94302f3 --- /dev/null +++ b/libc/arch-arm/denver/bionic/memmove.S
@@ -0,0 +1,280 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .text + .syntax unified + .fpu neon + +#define CACHE_LINE_SIZE (64) +#define MEMCPY_BLOCK_SIZE_SMALL (32768) +#define MEMCPY_BLOCK_SIZE_MID (1048576) +#define PREFETCH_DISTANCE_NEAR (CACHE_LINE_SIZE*4) +#define PREFETCH_DISTANCE_MID (CACHE_LINE_SIZE*4) +#define PREFETCH_DISTANCE_FAR (CACHE_LINE_SIZE*16) + +ENTRY(memmove) + cmp r2, #0 + cmpne r0, r1 + bxeq lr + subs r3, r0, r1 + bls .L_jump_to_memcpy + cmp r2, r3 + bhi .L_reversed_memcpy + +.L_jump_to_memcpy: + b memcpy + +.L_reversed_memcpy: + push {r0, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + add r0, r0, r2 + add r1, r1, r2 + + /* preload next cache line */ + pld [r1, #-CACHE_LINE_SIZE] + pld [r1, #-CACHE_LINE_SIZE*2] + +.L_reversed_memcpy_align_dest: + /* Deal with very small blocks (< 32bytes) asap */ + cmp r2, #32 + blo .L_reversed_memcpy_lt_32bytes + /* no need to align if len < 128 bytes */ + cmp r2, #128 + blo .L_reversed_memcpy_lt_128bytes + /* align destination to 64 bytes (1 cache line) */ + ands r3, r0, #0x3f + beq .L_reversed_memcpy_dispatch + sub r2, r2, r3 +0: /* copy 1 byte */ + movs ip, r3, lsl #31 + ldrbmi ip, [r1, #-1]! + strbmi ip, [r0, #-1]! +1: /* copy 2 bytes */ + ldrbcs ip, [r1, #-1]! + strbcs ip, [r0, #-1]! + ldrbcs ip, [r1, #-1]! + strbcs ip, [r0, #-1]! +2: /* copy 4 bytes */ + movs ip, r3, lsl #29 + bpl 3f + sub r1, r1, #4 + sub r0, r0, #4 + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1] + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32] +3: /* copy 8 bytes */ + bcc 4f + sub r1, r1, #8 + sub r0, r0, #8 + vld1.8 {d0}, [r1] + vst1.8 {d0}, [r0, :64] +4: /* copy 16 bytes */ + movs ip, r3, lsl #27 + bpl 5f + sub r1, r1, #16 + sub r0, r0, #16 + vld1.8 {q0}, [r1] + vst1.8 {q0}, [r0, :128] +5: /* copy 32 bytes */ + bcc .L_reversed_memcpy_dispatch + sub r1, r1, #32 + sub r0, r0, #32 + vld1.8 {q0, q1}, [r1] + vst1.8 {q0, q1}, [r0, :256] + +.L_reversed_memcpy_dispatch: + /* preload more cache lines */ + pld [r1, #-CACHE_LINE_SIZE*3] + pld [r1, #-CACHE_LINE_SIZE*4] + + cmp r2, #MEMCPY_BLOCK_SIZE_SMALL + blo .L_reversed_memcpy_neon_pld_near + cmp r2, #MEMCPY_BLOCK_SIZE_MID + blo .L_reversed_memcpy_neon_pld_mid + b .L_reversed_memcpy_neon_pld_far + +.L_reversed_memcpy_neon_pld_near: + /* less than 128 bytes? */ + subs r2, r2, #128 + blo 1f + sub r1, r1, #32 + sub r0, r0, #32 + mov r3, #-32 + .align 4 +0: + /* copy 128 bytes in each loop */ + subs r2, r2, #128 + + /* preload to cache */ + pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + + /* preload to cache */ + pld [r1, #-(PREFETCH_DISTANCE_NEAR+CACHE_LINE_SIZE*2)+32] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + + bhs 0b + add r1, r1, #32 + add r0, r0, #32 +1: + adds r2, r2, #128 + bne .L_reversed_memcpy_lt_128bytes + pop {r0, pc} + +.L_reversed_memcpy_neon_pld_mid: + subs r2, r2, #128 + sub r1, r1, #32 + sub r0, r0, #32 + mov r3, #-32 + .align 4 +0: + /* copy 128 bytes in each loop */ + subs r2, r2, #128 + + /* preload to cache */ + pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + + /* preload to cache */ + pld [r1, #-(PREFETCH_DISTANCE_MID+CACHE_LINE_SIZE)+32] + /* copy a cache line */ + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + vld1.8 {q0, q1}, [r1], r3 + vst1.8 {q0, q1}, [r0, :256], r3 + + bhs 0b + add r1, r1, #32 + add r0, r0, #32 +1: + adds r2, r2, #128 + bne .L_reversed_memcpy_lt_128bytes + pop {r0, pc} + +.L_reversed_memcpy_neon_pld_far: + sub r2, r2, #128 + sub r0, r0, #128 + sub r1, r1, #128 + .align 4 +0: + /* copy 128 bytes in each loop */ + subs r2, r2, #128 + + /* preload to cache */ + pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE*2)+128] + pld [r1, #-(PREFETCH_DISTANCE_FAR+CACHE_LINE_SIZE)+128] + /* read */ + vld1.8 {q0, q1}, [r1]! + vld1.8 {q2, q3}, [r1]! + vld1.8 {q8, q9}, [r1]! + vld1.8 {q10, q11}, [r1]! + /* write */ + vst1.8 {q0, q1}, [r0, :256]! + vst1.8 {q2, q3}, [r0, :256]! + vst1.8 {q8, q9}, [r0, :256]! + vst1.8 {q10, q11}, [r0, :256]! + + sub r0, r0, #256 + sub r1, r1, #256 + bhs 0b + add r0, r0, #128 + add r1, r1, #128 +1: + adds r2, r2, #128 + bne .L_reversed_memcpy_lt_128bytes + pop {r0, pc} + +.L_reversed_memcpy_lt_128bytes: +6: /* copy 64 bytes */ + movs ip, r2, lsl #26 + bcc 5f + sub r1, r1, #32 + sub r0, r0, #32 + vld1.8 {q0, q1}, [r1] + vst1.8 {q0, q1}, [r0] + sub r1, r1, #32 + sub r0, r0, #32 + vld1.8 {q0, q1}, [r1] + vst1.8 {q0, q1}, [r0] +5: /* copy 32 bytes */ + bpl 4f + sub r1, r1, #32 + sub r0, r0, #32 + vld1.8 {q0, q1}, [r1] + vst1.8 {q0, q1}, [r0] +.L_reversed_memcpy_lt_32bytes: +4: /* copy 16 bytes */ + movs ip, r2, lsl #28 + bcc 3f + sub r1, r1, #16 + sub r0, r0, #16 + vld1.8 {q0}, [r1] + vst1.8 {q0}, [r0] +3: /* copy 8 bytes */ + bpl 2f + sub r1, r1, #8 + sub r0, r0, #8 + vld1.8 {d0}, [r1] + vst1.8 {d0}, [r0] +2: /* copy 4 bytes */ + ands ip, r2, #0x4 + beq 1f + sub r1, r1, #4 + sub r0, r0, #4 + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1] + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0] +1: /* copy 2 bytes */ + movs ip, r2, lsl #31 + ldrbcs ip, [r1, #-1]! + strbcs ip, [r0, #-1]! + ldrbcs ip, [r1, #-1]! + strbcs ip, [r0, #-1]! +0: /* copy 1 byte */ + ldrbmi ip, [r1, #-1]! + strbmi ip, [r0, #-1]! + + pop {r0, pc} + +END(memmove)
diff --git a/libc/arch-arm/denver/bionic/memset.S b/libc/arch-arm/denver/bionic/memset.S new file mode 100644 index 0000000..88ffe5c --- /dev/null +++ b/libc/arch-arm/denver/bionic/memset.S
@@ -0,0 +1,186 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + /* + * Optimized memset() for ARM. + * + * memset() returns its first argument. + */ + + .cpu cortex-a15 + .fpu neon + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + pldw [r0] + mov r3, r0 + + // Duplicate the low byte of r1 + mov r1, r1, lsl #24 + orr r1, r1, r1, lsr #8 + orr r1, r1, r1, lsr #16 + + cmp r2, #16 + blo .L_less_than_16 + + // This section handles regions 16 bytes or larger + // + // Use aligned vst1.8 and vstm when possible. Register values will be: + // ip is scratch + // q0, q1, and r1 contain the memset value + // r2 is the number of bytes to set + // r3 is the advancing destination pointer + vdup.32 q0, r1 + + ands ip, r3, 0xF + beq .L_memset_aligned + + // Align dest pointer to 16-byte boundary. + pldw [r0, #64] + rsb ip, ip, #16 + + // Pre-adjust the byte count to reflect post-aligment value. Expecting + // 8-byte alignment to be rather common so we special case that one. + sub r2, r2, ip + + /* set 1 byte */ + tst ip, #1 + it ne + strbne r1, [r3], #1 + /* set 2 bytes */ + tst ip, #2 + it ne + strhne r1, [r3], #2 + /* set 4 bytes */ + movs ip, ip, lsl #29 + it mi + strmi r1, [r3], #4 + /* set 8 bytes */ + itt cs + strcs r1, [r3], #4 + strcs r1, [r3], #4 + +.L_memset_aligned: + // Destination is now 16-byte aligned. Determine how to handle + // remaining bytes. + vmov q1, q0 + cmp r2, #128 + blo .L_less_than_128 + + // We need to set a larger block of memory. Use four Q regs to + // set a full cache line in one instruction. Pre-decrement + // r2 to simplify end-of-loop detection + vmov q2, q0 + vmov q3, q0 + pldw [r0, #128] + sub r2, r2, #128 + .align 4 +.L_memset_loop_128: + pldw [r3, #192] + vstm r3!, {q0, q1, q2, q3} + vstm r3!, {q0, q1, q2, q3} + subs r2, r2, #128 + bhs .L_memset_loop_128 + + // Un-bias r2 so it contains the number of bytes left. Early + // exit if we are done. + adds r2, r2, #128 + beq 2f + + .align 4 +.L_less_than_128: + // set 64 bytes + movs ip, r2, lsl #26 + bcc 1f + vst1.8 {q0, q1}, [r3, :128]! + vst1.8 {q0, q1}, [r3, :128]! + beq 2f +1: + // set 32 bytes + bpl 1f + vst1.8 {q0, q1}, [r3, :128]! +1: + // set 16 bytes + movs ip, r2, lsl #28 + bcc 1f + vst1.8 {q0}, [r3, :128]! + beq 2f +1: + // set 8 bytes + bpl 1f + vst1.8 {d0}, [r3, :64]! +1: + // set 4 bytes + tst r2, #4 + it ne + strne r1, [r3], #4 +1: + // set 2 bytes + movs ip, r2, lsl #31 + it cs + strhcs r1, [r3], #2 + // set 1 byte + it mi + strbmi r1, [r3] +2: + bx lr + +.L_less_than_16: + // Store up to 15 bytes without worrying about byte alignment + movs ip, r2, lsl #29 + bcc 1f + str r1, [r3], #4 + str r1, [r3], #4 + beq 2f +1: + it mi + strmi r1, [r3], #4 + movs ip, r2, lsl #31 + it mi + strbmi r1, [r3], #1 + itt cs + strbcs r1, [r3], #1 + strbcs r1, [r3] +2: + bx lr +END(memset)
diff --git a/libc/arch-arm/generic/bionic/memcmp.S b/libc/arch-arm/generic/bionic/memcmp.S new file mode 100644 index 0000000..e648720 --- /dev/null +++ b/libc/arch-arm/generic/bionic/memcmp.S
@@ -0,0 +1,343 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + +#ifdef HAVE_32_BYTE_CACHE_LINE +#define CACHE_LINE_SIZE 32 +#else +#define CACHE_LINE_SIZE 64 +#endif + +/* + * Optimized memcmp() for Cortex-A9. + */ + +.syntax unified + +ENTRY(memcmp) + pld [r0, #(CACHE_LINE_SIZE * 0)] + pld [r0, #(CACHE_LINE_SIZE * 1)] + + /* take of the case where length is 0 or the buffers are the same */ + cmp r0, r1 + moveq r0, #0 + bxeq lr + + pld [r1, #(CACHE_LINE_SIZE * 0)] + pld [r1, #(CACHE_LINE_SIZE * 1)] + + /* make sure we have at least 8+4 bytes, this simplify things below + * and avoid some overhead for small blocks + */ + cmp r2, #(8+4) + bmi 10f +/* + * Neon optimization + * Comparing 32 bytes at a time + */ +#if defined(__ARM_NEON__) && defined(NEON_UNALIGNED_ACCESS) + subs r2, r2, #32 + blo 3f + + /* preload all the cache lines we need. */ + pld [r0, #(CACHE_LINE_SIZE * 2)] + pld [r1, #(CACHE_LINE_SIZE * 2)] + +1: /* The main loop compares 32 bytes at a time */ + vld1.8 {d0 - d3}, [r0]! + pld [r0, #(CACHE_LINE_SIZE * 2)] + vld1.8 {d4 - d7}, [r1]! + pld [r1, #(CACHE_LINE_SIZE * 2)] + + /* Start subtracting the values and merge results */ + vsub.i8 q0, q2 + vsub.i8 q1, q3 + vorr q2, q0, q1 + vorr d4, d5 + vmov r3, ip, d4 + /* Check if there are any differences among the 32 bytes */ + orrs r3, ip + bne 2f + subs r2, r2, #32 + bhs 1b + b 3f +2: + /* Check if the difference was in the first or last 16 bytes */ + sub r0, #32 + vorr d0, d1 + sub r1, #32 + vmov r3, ip, d0 + orrs r3, ip + /* if the first 16 bytes are equal, we only have to rewind 16 bytes */ + ittt eq + subeq r2, #16 + addeq r0, #16 + addeq r1, #16 + +3: /* fix-up the remaining count */ + add r2, r2, #32 + + cmp r2, #(8+4) + bmi 10f +#endif + + /* save registers */ + stmfd sp!, {r4, lr} + .cfi_def_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset lr, 4 + + /* since r0 hold the result, move the first source + * pointer somewhere else + */ + mov r4, r0 + + /* align first pointer to word boundary + * offset = -src & 3 + */ + rsb r3, r4, #0 + ands r3, r3, #3 + beq 0f + + /* align first pointer */ + sub r2, r2, r3 +1: ldrb r0, [r4], #1 + ldrb ip, [r1], #1 + subs r0, r0, ip + bne 9f + subs r3, r3, #1 + bne 1b + + +0: /* here the first pointer is aligned, and we have at least 4 bytes + * to process. + */ + + /* see if the pointers are congruent */ + eor r0, r4, r1 + ands r0, r0, #3 + bne 5f + + /* congruent case, 32 bytes per iteration + * We need to make sure there are at least 32+4 bytes left + * because we effectively read ahead one word, and we could + * read past the buffer (and segfault) if we're not careful. + */ + + ldr ip, [r1] + subs r2, r2, #(32 + 4) + bmi 1f + +0: pld [r4, #(CACHE_LINE_SIZE * 2)] + pld [r1, #(CACHE_LINE_SIZE * 2)] + ldr r0, [r4], #4 + ldr lr, [r1, #4]! + eors r0, r0, ip + ldreq r0, [r4], #4 + ldreq ip, [r1, #4]! + eorseq r0, r0, lr + ldreq r0, [r4], #4 + ldreq lr, [r1, #4]! + eorseq r0, r0, ip + ldreq r0, [r4], #4 + ldreq ip, [r1, #4]! + eorseq r0, r0, lr + ldreq r0, [r4], #4 + ldreq lr, [r1, #4]! + eorseq r0, r0, ip + ldreq r0, [r4], #4 + ldreq ip, [r1, #4]! + eorseq r0, r0, lr + ldreq r0, [r4], #4 + ldreq lr, [r1, #4]! + eorseq r0, r0, ip + ldreq r0, [r4], #4 + ldreq ip, [r1, #4]! + eorseq r0, r0, lr + bne 2f + subs r2, r2, #32 + bhs 0b + + /* do we have at least 4 bytes left? */ +1: adds r2, r2, #(32 - 4 + 4) + bmi 4f + + /* finish off 4 bytes at a time */ +3: ldr r0, [r4], #4 + ldr ip, [r1], #4 + eors r0, r0, ip + bne 2f + subs r2, r2, #4 + bhs 3b + + /* are we done? */ +4: adds r2, r2, #4 + moveq r0, #0 + beq 9f + + /* finish off the remaining bytes */ + b 8f + +2: /* the last 4 bytes are different, restart them */ + sub r4, r4, #4 + sub r1, r1, #4 + mov r2, #4 + + /* process the last few bytes */ +8: ldrb r0, [r4], #1 + ldrb ip, [r1], #1 + // stall + subs r0, r0, ip + bne 9f + subs r2, r2, #1 + bne 8b + +9: /* restore registers and return */ + ldmfd sp!, {r4, pc} + +10: /* process less than 12 bytes */ + cmp r2, #0 + moveq r0, #0 + bxeq lr + mov r3, r0 +11: + ldrb r0, [r3], #1 + ldrb ip, [r1], #1 + subs r0, ip + bxne lr + subs r2, r2, #1 + bne 11b + bx lr + +5: /*************** non-congruent case ***************/ + and r0, r1, #3 + cmp r0, #2 + bne 4f + + /* here, offset is 2 (16-bits aligned, special cased) */ + + /* make sure we have at least 16 bytes to process */ + subs r2, r2, #16 + addmi r2, r2, #16 + bmi 8b + + /* align the unaligned pointer */ + bic r1, r1, #3 + ldr lr, [r1], #4 + +6: pld [r1, #(CACHE_LINE_SIZE * 2)] + pld [r4, #(CACHE_LINE_SIZE * 2)] + mov ip, lr, lsr #16 + ldr lr, [r1], #4 + ldr r0, [r4], #4 + orr ip, ip, lr, lsl #16 + eors r0, r0, ip + moveq ip, lr, lsr #16 + ldreq lr, [r1], #4 + ldreq r0, [r4], #4 + orreq ip, ip, lr, lsl #16 + eorseq r0, r0, ip + moveq ip, lr, lsr #16 + ldreq lr, [r1], #4 + ldreq r0, [r4], #4 + orreq ip, ip, lr, lsl #16 + eorseq r0, r0, ip + moveq ip, lr, lsr #16 + ldreq lr, [r1], #4 + ldreq r0, [r4], #4 + orreq ip, ip, lr, lsl #16 + eorseq r0, r0, ip + bne 7f + subs r2, r2, #16 + bhs 6b + sub r1, r1, #2 + /* are we done? */ + adds r2, r2, #16 + moveq r0, #0 + beq 9b + /* finish off the remaining bytes */ + b 8b + +7: /* fix up the 2 pointers and fallthrough... */ + sub r1, r1, #(4+2) + sub r4, r4, #4 + mov r2, #4 + b 8b + + +4: /*************** offset is 1 or 3 (less optimized) ***************/ + + stmfd sp!, {r5, r6, r7} + + // r5 = rhs + // r6 = lhs + // r7 = scratch + + mov r5, r0, lsl #3 /* r5 = right shift */ + rsb r6, r5, #32 /* r6 = left shift */ + + /* align the unaligned pointer */ + bic r1, r1, #3 + ldr r7, [r1], #4 + sub r2, r2, #8 + +6: mov ip, r7, lsr r5 + ldr r7, [r1], #4 + ldr r0, [r4], #4 + orr ip, ip, r7, lsl r6 + eors r0, r0, ip + moveq ip, r7, lsr r5 + ldreq r7, [r1], #4 + ldreq r0, [r4], #4 + orreq ip, ip, r7, lsl r6 + eorseq r0, r0, ip + bne 7f + subs r2, r2, #8 + bhs 6b + + sub r1, r1, r6, lsr #3 + ldmfd sp!, {r5, r6, r7} + + /* are we done? */ + adds r2, r2, #8 + moveq r0, #0 + beq 9b + + /* finish off the remaining bytes */ + b 8b + +7: /* fix up the 2 pointers and fallthrough... */ + sub r1, r1, #4 + sub r1, r1, r6, lsr #3 + sub r4, r4, #4 + mov r2, #4 + ldmfd sp!, {r5, r6, r7} + b 8b +END(memcmp)
diff --git a/libc/arch-arm/generic/bionic/memcpy.S b/libc/arch-arm/generic/bionic/memcpy.S new file mode 100644 index 0000000..a3ebb95 --- /dev/null +++ b/libc/arch-arm/generic/bionic/memcpy.S
@@ -0,0 +1,391 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + /* + * Optimized memcpy() for ARM. + * + * note that memcpy() always returns the destination pointer, + * so we have to preserve R0. + */ + + .syntax unified + +ENTRY(__memcpy_chk) + cmp r2, r3 + bls memcpy + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + /* The stack must always be 64-bits aligned to be compliant with the + * ARM ABI. Since we have to save R0, we might as well save R4 + * which we can use for better pipelining of the reads below + */ + stmfd sp!, {r0, r4, lr} + .cfi_def_cfa_offset 12 + .cfi_rel_offset r0, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset lr, 8 + /* Making room for r5-r11 which will be spilled later */ + sub sp, sp, #28 + .cfi_adjust_cfa_offset 28 + + // preload the destination because we'll align it to a cache line + // with small writes. Also start the source "pump". + pld [r0, #0] + pld [r1, #0] + pld [r1, #32] + + /* it simplifies things to take care of len<4 early */ + cmp r2, #4 + blo .Lcopy_last_3_and_return + + /* compute the offset to align the source + * offset = (4-(src&3))&3 = -src & 3 + */ + rsb r3, r1, #0 + ands r3, r3, #3 + beq .Lsrc_aligned + + /* align source to 32 bits. We need to insert 2 instructions between + * a ldr[b|h] and str[b|h] because byte and half-word instructions + * stall 2 cycles. + */ + movs r12, r3, lsl #31 + sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */ + ldrbmi r3, [r1], #1 + ldrbcs r4, [r1], #1 + ldrbcs r12,[r1], #1 + strbmi r3, [r0], #1 + strbcs r4, [r0], #1 + strbcs r12,[r0], #1 + +.Lsrc_aligned: + + /* see if src and dst are aligned together (congruent) */ + eor r12, r0, r1 + tst r12, #3 + bne .Lnon_congruent + + /* Use post-incriment mode for stm to spill r5-r11 to reserved stack + * frame. Don't update sp. + */ + stmea sp, {r5-r11} + + /* align the destination to a cache-line */ + rsb r3, r0, #0 + ands r3, r3, #0x1C + beq .Lcongruent_aligned32 + cmp r3, r2 + andhi r3, r2, #0x1C + + /* conditionally copies 0 to 7 words (length in r3) */ + movs r12, r3, lsl #28 + ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */ + ldmmi r1!, {r8, r9} /* 8 bytes */ + stmcs r0!, {r4, r5, r6, r7} + stmmi r0!, {r8, r9} + tst r3, #0x4 + ldrne r10,[r1], #4 /* 4 bytes */ + strne r10,[r0], #4 + sub r2, r2, r3 + +.Lcongruent_aligned32: + /* + * here source is aligned to 32 bytes. + */ + +.Lcached_aligned32: + subs r2, r2, #32 + blo .Lless_than_32_left + + /* + * We preload a cache-line up to 64 bytes ahead. On the 926, this will + * stall only until the requested world is fetched, but the linefill + * continues in the the background. + * While the linefill is going, we write our previous cache-line + * into the write-buffer (which should have some free space). + * When the linefill is done, the writebuffer will + * start dumping its content into memory + * + * While all this is going, we then load a full cache line into + * 8 registers, this cache line should be in the cache by now + * (or partly in the cache). + * + * This code should work well regardless of the source/dest alignment. + * + */ + + // Align the preload register to a cache-line because the cpu does + // "critical word first" (the first word requested is loaded first). + bic r12, r1, #0x1F + add r12, r12, #64 + +1: ldmia r1!, { r4-r11 } + pld [r12, #64] + subs r2, r2, #32 + + // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi + // for ARM9 preload will not be safely guarded by the preceding subs. + // When it is safely guarded the only possibility to have SIGSEGV here + // is because the caller overstates the length. + ldrhi r3, [r12], #32 /* cheap ARM9 preload */ + stmia r0!, { r4-r11 } + bhs 1b + + add r2, r2, #32 + +.Lless_than_32_left: + /* + * less than 32 bytes left at this point (length in r2) + */ + + /* skip all this if there is nothing to do, which should + * be a common case (if not executed the code below takes + * about 16 cycles) + */ + tst r2, #0x1F + beq 1f + + /* conditionnaly copies 0 to 31 bytes */ + movs r12, r2, lsl #28 + ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */ + ldmmi r1!, {r8, r9} /* 8 bytes */ + stmcs r0!, {r4, r5, r6, r7} + stmmi r0!, {r8, r9} + movs r12, r2, lsl #30 + ldrcs r3, [r1], #4 /* 4 bytes */ + ldrhmi r4, [r1], #2 /* 2 bytes */ + strcs r3, [r0], #4 + strhmi r4, [r0], #2 + tst r2, #0x1 + ldrbne r3, [r1] /* last byte */ + strbne r3, [r0] + + /* we're done! restore everything and return */ +1: ldmfd sp!, {r5-r11} + ldmfd sp!, {r0, r4, pc} + + /********************************************************************/ + +.Lnon_congruent: + /* + * here source is aligned to 4 bytes + * but destination is not. + * + * in the code below r2 is the number of bytes read + * (the number of bytes written is always smaller, because we have + * partial words in the shift queue) + */ + cmp r2, #4 + blo .Lcopy_last_3_and_return + + /* Use post-increment mode for stm to spill r5-r11 to reserved stack + * frame. Don't update sp. + */ + stmea sp, {r5-r11} + + /* compute shifts needed to align src to dest */ + rsb r5, r0, #0 + and r5, r5, #3 /* r5 = # bytes in partial words */ + mov r12, r5, lsl #3 /* r12 = right */ + rsb lr, r12, #32 /* lr = left */ + + /* read the first word */ + ldr r3, [r1], #4 + sub r2, r2, #4 + + /* write a partial word (0 to 3 bytes), such that destination + * becomes aligned to 32 bits (r5 = nb of words to copy for alignment) + */ + movs r5, r5, lsl #31 + strbmi r3, [r0], #1 + movmi r3, r3, lsr #8 + strbcs r3, [r0], #1 + movcs r3, r3, lsr #8 + strbcs r3, [r0], #1 + movcs r3, r3, lsr #8 + + cmp r2, #4 + blo .Lpartial_word_tail + + /* Align destination to 32 bytes (cache line boundary) */ +1: tst r0, #0x1c + beq 2f + ldr r5, [r1], #4 + sub r2, r2, #4 + orr r4, r3, r5, lsl lr + mov r3, r5, lsr r12 + str r4, [r0], #4 + cmp r2, #4 + bhs 1b + blo .Lpartial_word_tail + + /* copy 32 bytes at a time */ +2: subs r2, r2, #32 + blo .Lless_than_thirtytwo + + /* Use immediate mode for the shifts, because there is an extra cycle + * for register shifts, which could account for up to 50% of + * performance hit. + */ + + cmp r12, #24 + beq .Lloop24 + cmp r12, #8 + beq .Lloop8 + +.Lloop16: + ldr r12, [r1], #4 +1: mov r4, r12 + ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} + pld [r1, #64] + subs r2, r2, #32 + ldrhs r12, [r1], #4 + orr r3, r3, r4, lsl #16 + mov r4, r4, lsr #16 + orr r4, r4, r5, lsl #16 + mov r5, r5, lsr #16 + orr r5, r5, r6, lsl #16 + mov r6, r6, lsr #16 + orr r6, r6, r7, lsl #16 + mov r7, r7, lsr #16 + orr r7, r7, r8, lsl #16 + mov r8, r8, lsr #16 + orr r8, r8, r9, lsl #16 + mov r9, r9, lsr #16 + orr r9, r9, r10, lsl #16 + mov r10, r10, lsr #16 + orr r10, r10, r11, lsl #16 + stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} + mov r3, r11, lsr #16 + bhs 1b + b .Lless_than_thirtytwo + +.Lloop8: + ldr r12, [r1], #4 +1: mov r4, r12 + ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} + pld [r1, #64] + subs r2, r2, #32 + ldrhs r12, [r1], #4 + orr r3, r3, r4, lsl #24 + mov r4, r4, lsr #8 + orr r4, r4, r5, lsl #24 + mov r5, r5, lsr #8 + orr r5, r5, r6, lsl #24 + mov r6, r6, lsr #8 + orr r6, r6, r7, lsl #24 + mov r7, r7, lsr #8 + orr r7, r7, r8, lsl #24 + mov r8, r8, lsr #8 + orr r8, r8, r9, lsl #24 + mov r9, r9, lsr #8 + orr r9, r9, r10, lsl #24 + mov r10, r10, lsr #8 + orr r10, r10, r11, lsl #24 + stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} + mov r3, r11, lsr #8 + bhs 1b + b .Lless_than_thirtytwo + +.Lloop24: + ldr r12, [r1], #4 +1: mov r4, r12 + ldmia r1!, { r5,r6,r7, r8,r9,r10,r11} + pld [r1, #64] + subs r2, r2, #32 + ldrhs r12, [r1], #4 + orr r3, r3, r4, lsl #8 + mov r4, r4, lsr #24 + orr r4, r4, r5, lsl #8 + mov r5, r5, lsr #24 + orr r5, r5, r6, lsl #8 + mov r6, r6, lsr #24 + orr r6, r6, r7, lsl #8 + mov r7, r7, lsr #24 + orr r7, r7, r8, lsl #8 + mov r8, r8, lsr #24 + orr r8, r8, r9, lsl #8 + mov r9, r9, lsr #24 + orr r9, r9, r10, lsl #8 + mov r10, r10, lsr #24 + orr r10, r10, r11, lsl #8 + stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10} + mov r3, r11, lsr #24 + bhs 1b + + +.Lless_than_thirtytwo: + /* copy the last 0 to 31 bytes of the source */ + rsb r12, lr, #32 /* we corrupted r12, recompute it */ + add r2, r2, #32 + cmp r2, #4 + blo .Lpartial_word_tail + +1: ldr r5, [r1], #4 + sub r2, r2, #4 + orr r4, r3, r5, lsl lr + mov r3, r5, lsr r12 + str r4, [r0], #4 + cmp r2, #4 + bhs 1b + +.Lpartial_word_tail: + /* we have a partial word in the input buffer */ + movs r5, lr, lsl #(31-3) + strbmi r3, [r0], #1 + movmi r3, r3, lsr #8 + strbcs r3, [r0], #1 + movcs r3, r3, lsr #8 + strbcs r3, [r0], #1 + + /* Refill spilled registers from the stack. Don't update sp. */ + ldmfd sp, {r5-r11} + +.Lcopy_last_3_and_return: + movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */ + ldrbmi r2, [r1], #1 + ldrbcs r3, [r1], #1 + ldrbcs r12,[r1] + strbmi r2, [r0], #1 + strbcs r3, [r0], #1 + strbcs r12,[r0] + + /* we're done! restore sp and spilled registers and return */ + add sp, sp, #28 + ldmfd sp!, {r0, r4, pc} +END(memcpy)
diff --git a/libc/arch-arm/generic/bionic/memset.S b/libc/arch-arm/generic/bionic/memset.S new file mode 100644 index 0000000..1fd0de1 --- /dev/null +++ b/libc/arch-arm/generic/bionic/memset.S
@@ -0,0 +1,111 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + /* + * Optimized memset() for ARM. + * + * memset() returns its first argument. + */ + + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + /* compute the offset to align the destination + * offset = (4-(src&3))&3 = -src & 3 + */ + .save {r0, r4-r7, lr} + stmfd sp!, {r0, r4-r7, lr} + rsb r3, r0, #0 + ands r3, r3, #3 + cmp r3, r2 + movhi r3, r2 + + /* splat r1 */ + mov r1, r1, lsl #24 + orr r1, r1, r1, lsr #8 + orr r1, r1, r1, lsr #16 + + movs r12, r3, lsl #31 + strbcs r1, [r0], #1 /* can't use strh (alignment unknown) */ + strbcs r1, [r0], #1 + strbmi r1, [r0], #1 + subs r2, r2, r3 + popls {r0, r4-r7, pc} /* return */ + + /* align the destination to a cache-line */ + mov r12, r1 + mov lr, r1 + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + + rsb r3, r0, #0 + ands r3, r3, #0x1C + beq 3f + cmp r3, r2 + andhi r3, r2, #0x1C + sub r2, r2, r3 + + /* conditionally writes 0 to 7 words (length in r3) */ + movs r3, r3, lsl #28 + stmcs r0!, {r1, lr} + stmcs r0!, {r1, lr} + stmmi r0!, {r1, lr} + movs r3, r3, lsl #2 + strcs r1, [r0], #4 + +3: + subs r2, r2, #32 + mov r3, r1 + bmi 2f +1: subs r2, r2, #32 + stmia r0!, {r1,r3,r4,r5,r6,r7,r12,lr} + bhs 1b +2: add r2, r2, #32 + + /* conditionally stores 0 to 31 bytes */ + movs r2, r2, lsl #28 + stmcs r0!, {r1,r3,r12,lr} + stmmi r0!, {r1, lr} + movs r2, r2, lsl #2 + strcs r1, [r0], #4 + strhmi r1, [r0], #2 + movs r2, r2, lsl #2 + strbcs r1, [r0] + ldmfd sp!, {r0, r4-r7, pc} +END(memset)
diff --git a/libc/arch-arm/generic/bionic/strcmp.S b/libc/arch-arm/generic/bionic/strcmp.S new file mode 100644 index 0000000..10b6704 --- /dev/null +++ b/libc/arch-arm/generic/bionic/strcmp.S
@@ -0,0 +1,316 @@ +/* + * Copyright (c) 2011 The Android Open Source Project + * Copyright (c) 2008 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .text + +#ifdef __ARMEB__ +#define SHFT2LSB lsl +#define SHFT2LSBEQ lsleq +#define SHFT2MSB lsr +#define SHFT2MSBEQ lsreq +#define MSB 0x000000ff +#define LSB 0xff000000 +#else +#define SHFT2LSB lsr +#define SHFT2LSBEQ lsreq +#define SHFT2MSB lsl +#define SHFT2MSBEQ lsleq +#define MSB 0xff000000 +#define LSB 0x000000ff +#endif + +#define magic1(REG) REG +#define magic2(REG) REG, lsl #7 + +ENTRY(strcmp) + pld [r0, #0] + pld [r1, #0] + eor r2, r0, r1 + tst r2, #3 + + /* Strings not at same byte offset from a word boundary. */ + bne .Lstrcmp_unaligned + ands r2, r0, #3 + bic r0, r0, #3 + bic r1, r1, #3 + ldr ip, [r0], #4 + it eq + ldreq r3, [r1], #4 + beq 1f + + /* Although s1 and s2 have identical initial alignment, they are + * not currently word aligned. Rather than comparing bytes, + * make sure that any bytes fetched from before the addressed + * bytes are forced to 0xff. Then they will always compare + * equal. + */ + eor r2, r2, #3 + lsl r2, r2, #3 + mvn r3, #MSB + SHFT2LSB r2, r3, r2 + ldr r3, [r1], #4 + orr ip, ip, r2 + orr r3, r3, r2 +1: + /* Load the 'magic' constant 0x01010101. */ + str r4, [sp, #-4]! + mov r4, #1 + orr r4, r4, r4, lsl #8 + orr r4, r4, r4, lsl #16 + .p2align 2 +4: + pld [r0, #8] + pld [r1, #8] + sub r2, ip, magic1(r4) + cmp ip, r3 + itttt eq + + /* check for any zero bytes in first word */ + biceq r2, r2, ip + tsteq r2, magic2(r4) + ldreq ip, [r0], #4 + ldreq r3, [r1], #4 + beq 4b +2: + /* There's a zero or a different byte in the word */ + SHFT2MSB r0, ip, #24 + SHFT2LSB ip, ip, #8 + cmp r0, #1 + it cs + cmpcs r0, r3, SHFT2MSB #24 + it eq + SHFT2LSBEQ r3, r3, #8 + beq 2b + /* On a big-endian machine, r0 contains the desired byte in bits + * 0-7; on a little-endian machine they are in bits 24-31. In + * both cases the other bits in r0 are all zero. For r3 the + * interesting byte is at the other end of the word, but the + * other bits are not necessarily zero. We need a signed result + * representing the differnece in the unsigned bytes, so for the + * little-endian case we can't just shift the interesting bits up. + */ +#ifdef __ARMEB__ + sub r0, r0, r3, lsr #24 +#else + and r3, r3, #255 + /* No RSB instruction in Thumb2 */ +#ifdef __thumb2__ + lsr r0, r0, #24 + sub r0, r0, r3 +#else + rsb r0, r3, r0, lsr #24 +#endif +#endif + ldr r4, [sp], #4 + bx lr + +.Lstrcmp_unaligned: + wp1 .req r0 + wp2 .req r1 + b1 .req r2 + w1 .req r4 + w2 .req r5 + t1 .req ip + @ r3 is scratch + + /* First of all, compare bytes until wp1(sp1) is word-aligned. */ +1: + tst wp1, #3 + beq 2f + ldrb r2, [wp1], #1 + ldrb r3, [wp2], #1 + cmp r2, #1 + it cs + cmpcs r2, r3 + beq 1b + sub r0, r2, r3 + bx lr + +2: + str r5, [sp, #-4]! + str r4, [sp, #-4]! + mov b1, #1 + orr b1, b1, b1, lsl #8 + orr b1, b1, b1, lsl #16 + + and t1, wp2, #3 + bic wp2, wp2, #3 + ldr w1, [wp1], #4 + ldr w2, [wp2], #4 + cmp t1, #2 + beq 2f + bhi 3f + + /* Critical inner Loop: Block with 3 bytes initial overlap */ + .p2align 2 +1: + bic t1, w1, #MSB + cmp t1, w2, SHFT2LSB #8 + sub r3, w1, b1 + bic r3, r3, w1 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, SHFT2MSB #24 + bne 6f + ldr w1, [wp1], #4 + b 1b +4: + SHFT2LSB w2, w2, #8 + b 8f + +5: +#ifdef __ARMEB__ + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #0xff000000 + itt ne + tstne w1, #0x00ff0000 + tstne w1, #0x0000ff00 + beq 7f +#else + bics r3, r3, #0xff000000 + bne 7f +#endif + ldrb w2, [wp2] + SHFT2LSB t1, w1, #24 +#ifdef __ARMEB__ + lsl w2, w2, #24 +#endif + b 8f + +6: + SHFT2LSB t1, w1, #24 + and w2, w2, #LSB + b 8f + + /* Critical inner Loop: Block with 2 bytes initial overlap */ + .p2align 2 +2: + SHFT2MSB t1, w1, #16 + sub r3, w1, b1 + SHFT2LSB t1, t1, #16 + bic r3, r3, w1 + cmp t1, w2, SHFT2LSB #16 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, SHFT2MSB #16 + bne 6f + ldr w1, [wp1], #4 + b 2b + +5: +#ifdef __ARMEB__ + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #0xff000000 + it ne + tstne w1, #0x00ff0000 + beq 7f +#else + lsls r3, r3, #16 + bne 7f +#endif + ldrh w2, [wp2] + SHFT2LSB t1, w1, #16 +#ifdef __ARMEB__ + lsl w2, w2, #16 +#endif + b 8f + +6: + SHFT2MSB w2, w2, #16 + SHFT2LSB t1, w1, #16 +4: + SHFT2LSB w2, w2, #16 + b 8f + + /* Critical inner Loop: Block with 1 byte initial overlap */ + .p2align 2 +3: + and t1, w1, #LSB + cmp t1, w2, SHFT2LSB #24 + sub r3, w1, b1 + bic r3, r3, w1 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, SHFT2MSB #8 + bne 6f + ldr w1, [wp1], #4 + b 3b +4: + SHFT2LSB w2, w2, #24 + b 8f +5: + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #LSB + beq 7f + ldr w2, [wp2], #4 +6: + SHFT2LSB t1, w1, #8 + bic w2, w2, #MSB + b 8f +7: + mov r0, #0 + ldr r4, [sp], #4 + ldr r5, [sp], #4 + bx lr + +8: + and r2, t1, #LSB + and r0, w2, #LSB + cmp r0, #1 + it cs + cmpcs r0, r2 + itt eq + SHFT2LSBEQ t1, t1, #8 + SHFT2LSBEQ w2, w2, #8 + beq 8b + sub r0, r2, r0 + ldr r4, [sp], #4 + ldr r5, [sp], #4 + bx lr +END(strcmp)
diff --git a/libc/arch-arm/generic/bionic/strcpy.S b/libc/arch-arm/generic/bionic/strcpy.S new file mode 100644 index 0000000..c0ab9e5 --- /dev/null +++ b/libc/arch-arm/generic/bionic/strcpy.S
@@ -0,0 +1,134 @@ +/* + * Copyright (C) 2010 The Android Open Source Project + * Copyright (c) 2008 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>. + */ + +#include <private/bionic_asm.h> + +.syntax unified + +ENTRY(strcpy) + pld [r1, #0] + eor r2, r0, r1 + mov ip, r0 + tst r2, #3 + bne 4f + tst r1, #3 + bne 3f +5: + str r5, [sp, #-4]! + mov r5, #0x01 + orr r5, r5, r5, lsl #8 + orr r5, r5, r5, lsl #16 + + str r4, [sp, #-4]! + tst r1, #4 + ldr r3, [r1], #4 + beq 2f + sub r2, r3, r5 + bics r2, r2, r3 + tst r2, r5, lsl #7 + itt eq + streq r3, [ip], #4 + ldreq r3, [r1], #4 + bne 1f + /* Inner loop. We now know that r1 is 64-bit aligned, so we + can safely fetch up to two words. This allows us to avoid + load stalls. */ + .p2align 2 +2: + pld [r1, #8] + ldr r4, [r1], #4 + sub r2, r3, r5 + bics r2, r2, r3 + tst r2, r5, lsl #7 + sub r2, r4, r5 + bne 1f + str r3, [ip], #4 + bics r2, r2, r4 + tst r2, r5, lsl #7 + itt eq + ldreq r3, [r1], #4 + streq r4, [ip], #4 + beq 2b + mov r3, r4 +1: +#ifdef __ARMEB__ + rors r3, r3, #24 +#endif + strb r3, [ip], #1 + tst r3, #0xff +#ifdef __ARMEL__ + ror r3, r3, #8 +#endif + bne 1b + ldr r4, [sp], #4 + ldr r5, [sp], #4 + bx lr + + /* Strings have the same offset from word alignment, but it's + not zero. */ +3: + tst r1, #1 + beq 1f + ldrb r2, [r1], #1 + strb r2, [ip], #1 + cmp r2, #0 + it eq + bxeq lr +1: + tst r1, #2 + beq 5b + ldrh r2, [r1], #2 +#ifdef __ARMEB__ + tst r2, #0xff00 + iteet ne + strhne r2, [ip], #2 + lsreq r2, r2, #8 + strbeq r2, [ip] + tstne r2, #0xff +#else + tst r2, #0xff + itet ne + strhne r2, [ip], #2 + strbeq r2, [ip] + tstne r2, #0xff00 +#endif + bne 5b + bx lr + + /* src and dst do not have a common word-alignement. Fall back to + byte copying. */ +4: + ldrb r2, [r1], #1 + strb r2, [ip], #1 + cmp r2, #0 + bne 4b + bx lr +END(strcpy)
diff --git a/libc/arch-arm/generic/bionic/strlen.c b/libc/arch-arm/generic/bionic/strlen.c new file mode 100644 index 0000000..b9f3a2a --- /dev/null +++ b/libc/arch-arm/generic/bionic/strlen.c
@@ -0,0 +1,136 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <string.h> +#include <stdint.h> + +size_t strlen(const char *s) +{ + __builtin_prefetch(s); + __builtin_prefetch(s+32); + + union { + const char *b; + const uint32_t *w; + uintptr_t i; + } u; + + // these are some scratch variables for the asm code below + uint32_t v, t; + + // initialize the string length to zero + size_t l = 0; + + // align the pointer to a 32-bit word boundary + u.b = s; + while (u.i & 0x3) { + if (__builtin_expect(*u.b++ == 0, 0)) { + goto done; + } + l++; + } + + // loop for each word, testing if it contains a zero byte + // if so, exit the loop and update the length. + // We need to process 32 bytes per loop to schedule PLD properly + // and achieve the maximum bus speed. + asm( + "ldr %[v], [%[s]], #4 \n" + "sub %[l], %[l], %[s] \n" + "0: \n" + "pld [%[s], #64] \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" +#if !defined(__OPTIMIZE_SIZE__) + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" + "bne 1f \n" + "sub %[t], %[v], %[mask], lsr #7\n" + "and %[t], %[t], %[mask] \n" + "bics %[t], %[t], %[v] \n" + "it eq \n" + "ldreq %[v], [%[s]], #4 \n" +#endif + "beq 0b \n" + "1: \n" + "add %[l], %[l], %[s] \n" + "tst %[v], #0xFF \n" + "beq 2f \n" + "add %[l], %[l], #1 \n" + "tst %[v], #0xFF00 \n" + "beq 2f \n" + "add %[l], %[l], #1 \n" + "tst %[v], #0xFF0000 \n" + "it ne \n" + "addne %[l], %[l], #1 \n" + "2: \n" + : [l]"=&r"(l), [v]"=&r"(v), [t]"=&r"(t), [s]"=&r"(u.b) + : "%[l]"(l), "%[s]"(u.b), [mask]"r"(0x80808080UL) + : "cc" + ); + +done: + return l; +}
diff --git a/libc/arch-arm/include/machine/asm.h b/libc/arch-arm/include/machine/asm.h new file mode 100644 index 0000000..70dbe67 --- /dev/null +++ b/libc/arch-arm/include/machine/asm.h
@@ -0,0 +1,51 @@ +/* $OpenBSD: asm.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: asm.h,v 1.4 2001/07/16 05:43:32 matt Exp $ */ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)asm.h 5.5 (Berkeley) 5/7/91 + */ + +#ifndef _ARM32_ASM_H_ +#define _ARM32_ASM_H_ + +#define __bionic_asm_align 0 + +#undef __bionic_asm_custom_entry +#undef __bionic_asm_custom_end +#define __bionic_asm_custom_entry(f) .fnstart +#define __bionic_asm_custom_end(f) .fnend + +#undef __bionic_asm_function_type +#define __bionic_asm_function_type #function + +#endif /* !_ARM_ASM_H_ */
diff --git a/libc/arch-arm/include/machine/cpu-features.h b/libc/arch-arm/include/machine/cpu-features.h new file mode 100644 index 0000000..fc8c80d --- /dev/null +++ b/libc/arch-arm/include/machine/cpu-features.h
@@ -0,0 +1,48 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _ARM_MACHINE_CPU_FEATURES_H +#define _ARM_MACHINE_CPU_FEATURES_H + +/* __ARM_ARCH__ is a number corresponding to the ARM revision + * we're going to support. Our toolchain doesn't define __ARM_ARCH__ + * so try to guess it. + */ +#ifndef __ARM_ARCH__ +# if defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ || \ + defined __ARM_ARCH_7R__ || defined __ARM_ARCH_7M__ +# define __ARM_ARCH__ 7 +# elif defined __ARM_ARCH_6__ || defined __ARM_ARCH_6J__ || \ + defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6Z__ || \ + defined __ARM_ARCH_6KZ__ || defined __ARM_ARCH_6T2__ +# define __ARM_ARCH__ 6 +# else +# error Unknown or unsupported ARM architecture +# endif +#endif + +#endif /* _ARM_MACHINE_CPU_FEATURES_H */
diff --git a/libc/arch-arm/include/machine/elf_machdep.h b/libc/arch-arm/include/machine/elf_machdep.h new file mode 100644 index 0000000..542f638 --- /dev/null +++ b/libc/arch-arm/include/machine/elf_machdep.h
@@ -0,0 +1,140 @@ +/* $NetBSD: elf_machdep.h,v 1.10 2012/08/05 04:12:46 matt Exp $ */ + +#ifndef _ARM_ELF_MACHDEP_H_ +#define _ARM_ELF_MACHDEP_H_ + +#if defined(__ARMEB__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#else +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#endif + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x00000001 +#define EF_ARM_HASENTRY 0x00000002 +#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */ +#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */ +#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */ +#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */ +#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */ +#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */ +#define EF_ARM_PIC 0x00000020 +#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */ +#define EF_ARM_NEW_ABI 0x00000080 +#define EF_ARM_OLD_ABI 0x00000100 +#define EF_ARM_SOFT_FLOAT 0x00000200 +#define EF_ARM_EABIMASK 0xff000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 +#define EF_ARM_EABI_VER3 0x03000000 +#define EF_ARM_EABI_VER4 0x04000000 +#define EF_ARM_EABI_VER5 0x05000000 + +#define ELF32_MACHDEP_ID_CASES \ + case EM_ARM: \ + break; + +#define ELF32_MACHDEP_ID EM_ARM + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* Processor specific relocation types */ + +#define R_ARM_NONE 0 +#define R_ARM_PC24 1 +#define R_ARM_ABS32 2 +#define R_ARM_REL32 3 +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 +#define R_ARM_ABS12 6 +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 + +/* TLS relocations */ +#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ +#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ +#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ + +/* 20-31 are reserved for ARM Linux. */ +#define R_ARM_COPY 20 +#define R_ARM_GLOB_DAT 21 +#define R_ARM_JUMP_SLOT 22 +#define R_ARM_RELATIVE 23 +#define R_ARM_GOTOFF 24 +#define R_ARM_GOTPC 25 +#define R_ARM_GOT32 26 +#define R_ARM_PLT32 27 + +#define R_ARM_ALU_PCREL_7_0 32 +#define R_ARM_ALU_PCREL_15_8 33 +#define R_ARM_ALU_PCREL_23_15 34 +#define R_ARM_ALU_SBREL_11_0 35 +#define R_ARM_ALU_SBREL_19_12 36 +#define R_ARM_ALU_SBREL_27_20 37 + +/* 96-111 are reserved to G++. */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 +#define R_ARM_THM_PC9 103 + +/* More TLS relocations */ +#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic */ +#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic */ +#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS */ +#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of */ +#define R_ARM_TLS_LE32 108 +#define R_ARM_TLS_LDO12 109 +#define R_ARM_TLS_LE12 110 +#define R_ARM_TLS_IE12GP 111 + +/* 112-127 are reserved for private experiments. */ + +#define R_ARM_IRELATIVE 160 + +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS32 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + +#define R_TYPE(name) __CONCAT(R_ARM_,name) + +/* Processor specific program header flags */ +#define PF_ARM_SB 0x10000000 +#define PF_ARM_PI 0x20000000 +#define PF_ARM_ENTRY 0x80000000 + +/* Processor specific section header flags */ +#define SHF_ENTRYSECT 0x10000000 +#define SHF_COMDEF 0x80000000 + +/* Processor specific symbol types */ +#define STT_ARM_TFUNC STT_LOPROC + +#ifdef _KERNEL +#ifdef ELFSIZE +#define ELF_MD_PROBE_FUNC ELFNAME2(arm_netbsd,probe) +#endif + +struct exec_package; + +int arm_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +#endif + +#endif /* _ARM_ELF_MACHDEP_H_ */
diff --git a/libc/arch-arm/include/machine/fenv.h b/libc/arch-arm/include/machine/fenv.h new file mode 100644 index 0000000..0e483e3 --- /dev/null +++ b/libc/arch-arm/include/machine/fenv.h
@@ -0,0 +1,63 @@ +/*- + * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ + */ + +/* + * Rewritten for Android. + * + * The ARM FPSCR is described here: + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html + */ + +#ifndef _ARM_FENV_H_ +#define _ARM_FENV_H_ + +#include <sys/types.h> + +__BEGIN_DECLS + +typedef __uint32_t fenv_t; +typedef __uint32_t fexcept_t; + +/* Exception flags. */ +#define FE_INVALID 0x01 +#define FE_DIVBYZERO 0x02 +#define FE_OVERFLOW 0x04 +#define FE_UNDERFLOW 0x08 +#define FE_INEXACT 0x10 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ + FE_OVERFLOW | FE_UNDERFLOW) + +/* Rounding modes. */ +#define FE_TONEAREST 0x0 +#define FE_UPWARD 0x1 +#define FE_DOWNWARD 0x2 +#define FE_TOWARDZERO 0x3 + +__END_DECLS + +#endif /* !_ARM_FENV_H_ */
diff --git a/libc/arch-arm/include/machine/setjmp.h b/libc/arch-arm/include/machine/setjmp.h new file mode 100644 index 0000000..cc9c347 --- /dev/null +++ b/libc/arch-arm/include/machine/setjmp.h
@@ -0,0 +1,35 @@ +/* + * Copyright (C) 2010 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* _JBLEN is the size of a jmp_buf in longs. + * Do not modify this value or you will break the ABI ! + * + * This value comes from the original OpenBSD ARM-specific header + * that was replaced by this one. + */ +#define _JBLEN 64
diff --git a/libc/arch-arm/krait/bionic/__strcat_chk.S b/libc/arch-arm/krait/bionic/__strcat_chk.S new file mode 100644 index 0000000..a46ff98 --- /dev/null +++ b/libc/arch-arm/krait/bionic/__strcat_chk.S
@@ -0,0 +1,199 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of src string, then get the source of the dst string. +// Check that the two lengths together don't exceed the threshold, then +// do a memcpy of the data. +ENTRY(__strcat_chk) + pld [r0, #0] + push {r0, lr} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + push {r4, r5} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + + mov lr, r2 + + // Save the dst register to r5 + mov r5, r0 + + // Zero out r4 + eor r4, r4, r4 + + // r1 contains the address of the string to count. +.L_strlen_start: + mov r0, r1 + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r1], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r1], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r1], #8 + + pld [r1, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r1, r0 + sub r3, r3, #1 + b .L_finish + +.L_zero_in_first_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_finish + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_finish + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_finish + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_finish + +.L_zero_in_second_register: + sub r3, r1, r0 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_finish + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_finish + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_finish + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_finish: + cmp r4, #0 + bne .L_strlen_done + + // Time to get the dst string length. + mov r1, r5 + + // Save the original source address to r5. + mov r5, r0 + + // Save the current length (adding 1 for the terminator). + add r4, r3, #1 + b .L_strlen_start + + // r0 holds the pointer to the dst string. + // r3 holds the dst string length. + // r4 holds the src string length + 1. +.L_strlen_done: + add r2, r3, r4 + cmp r2, lr + itt hi + movhi r0, lr + bhi __strcat_chk_fail + + // Set up the registers for the memcpy code. + mov r1, r5 + pld [r1, #64] + mov r2, r4 + add r0, r0, r3 + pop {r4, r5} + .cfi_adjust_cfa_offset -8 + .cfi_restore r4 + .cfi_restore r5 + +#include "memcpy_base.S" + + // Undo the above cfi directives. + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 +END(__strcat_chk)
diff --git a/libc/arch-arm/krait/bionic/__strcpy_chk.S b/libc/arch-arm/krait/bionic/__strcpy_chk.S new file mode 100644 index 0000000..9c2f66a --- /dev/null +++ b/libc/arch-arm/krait/bionic/__strcpy_chk.S
@@ -0,0 +1,161 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + + .syntax unified + + .thumb + .thumb_func + +// Get the length of the source string first, then do a memcpy of the data +// instead of a strcpy. +ENTRY(__strcpy_chk) + pld [r0, #0] + push {r0, lr} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + + mov lr, r2 + mov r0, r1 + + ands r3, r1, #7 + beq .L_mainloop + + // Align to a double word (64 bits). + rsb r3, r3, #8 + lsls ip, r3, #31 + beq .L_align_to_32 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_32: + bcc .L_align_to_64 + ands ip, r3, #2 + beq .L_align_to_64 + + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + ldrb r2, [r0], #1 + cbz r2, .L_update_count_and_finish + +.L_align_to_64: + tst r3, #4 + beq .L_mainloop + ldr r3, [r0], #4 + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + + .p2align 2 +.L_mainloop: + ldrd r2, r3, [r0], #8 + + pld [r0, #64] + + sub ip, r2, #0x01010101 + bic ip, ip, r2 + ands ip, ip, #0x80808080 + bne .L_zero_in_first_register + + sub ip, r3, #0x01010101 + bic ip, ip, r3 + ands ip, ip, #0x80808080 + bne .L_zero_in_second_register + b .L_mainloop + +.L_update_count_and_finish: + sub r3, r0, r1 + sub r3, r3, #1 + b .L_check_size + +.L_zero_in_first_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub8_and_finish + bcs .L_sub7_and_finish + lsls ip, ip, #1 + bne .L_sub6_and_finish + + sub r3, r3, #5 + b .L_check_size + +.L_sub8_and_finish: + sub r3, r3, #8 + b .L_check_size + +.L_sub7_and_finish: + sub r3, r3, #7 + b .L_check_size + +.L_sub6_and_finish: + sub r3, r3, #6 + b .L_check_size + +.L_zero_in_second_register: + sub r3, r0, r1 + lsls r2, ip, #17 + bne .L_sub4_and_finish + bcs .L_sub3_and_finish + lsls ip, ip, #1 + bne .L_sub2_and_finish + + sub r3, r3, #1 + b .L_check_size + +.L_sub4_and_finish: + sub r3, r3, #4 + b .L_check_size + +.L_sub3_and_finish: + sub r3, r3, #3 + b .L_check_size + +.L_sub2_and_finish: + sub r3, r3, #2 + +.L_check_size: + pld [r1, #0] + pld [r1, #64] + ldr r0, [sp] + + // Add 1 for copy length to get the string terminator. + add r2, r3, #1 + + cmp r2, lr + itt hi + movhi r0, r2 + bhi __strcpy_chk_fail + +#include "memcpy_base.S" + +END(__strcpy_chk)
diff --git a/libc/arch-arm/krait/bionic/memcpy.S b/libc/arch-arm/krait/bionic/memcpy.S new file mode 100644 index 0000000..de6f432 --- /dev/null +++ b/libc/arch-arm/krait/bionic/memcpy.S
@@ -0,0 +1,65 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Assumes neon instructions and a cache line size of 32 bytes. */ + +#include <private/bionic_asm.h> + +/* + * This code assumes it is running on a processor that supports all arm v7 + * instructions, that supports neon instructions, and that has a 32 byte + * cache line. + */ + + .text + .syntax unified + .fpu neon + .thumb + .thumb_func + +ENTRY(__memcpy_chk) + cmp r2, r3 + bls memcpy + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + pld [r1, #64] + stmfd sp!, {r0, lr} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r0, 0 + .cfi_rel_offset lr, 4 + +#include "memcpy_base.S" +END(memcpy)
diff --git a/libc/arch-arm/krait/bionic/memcpy_base.S b/libc/arch-arm/krait/bionic/memcpy_base.S new file mode 100644 index 0000000..7368e63 --- /dev/null +++ b/libc/arch-arm/krait/bionic/memcpy_base.S
@@ -0,0 +1,190 @@ +/*************************************************************************** + Copyright (c) 2009-2013 The Linux Foundation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of The Linux Foundation nor the names of its contributors may + be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ***************************************************************************/ + +/* Assumes neon instructions and a cache line size of 64 bytes. */ + +#include <machine/asm.h> + +#define PLDOFFS (10) +#define PLDTHRESH (PLDOFFS) +#define BBTHRESH (4096/64) +#define PLDSIZE (64) + +#if (PLDOFFS < 1) +#error Routine does not support offsets less than 1 +#endif + +#if (PLDTHRESH < PLDOFFS) +#error PLD threshold must be greater than or equal to the PLD offset +#endif + + .text + .fpu neon + +.L_memcpy_base: + cmp r2, #4 + blt .L_neon_lt4 + cmp r2, #16 + blt .L_neon_lt16 + cmp r2, #32 + blt .L_neon_16 + cmp r2, #64 + blt .L_neon_copy_32_a + + mov r12, r2, lsr #6 + cmp r12, #PLDTHRESH + ble .L_neon_copy_64_loop_nopld + + push {r9, r10} + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset r9, 0 + .cfi_rel_offset r10, 4 + + cmp r12, #BBTHRESH + ble .L_neon_prime_pump + + add lr, r0, #0x400 + add r9, r1, #(PLDOFFS*PLDSIZE) + sub lr, lr, r9 + lsl lr, lr, #21 + lsr lr, lr, #21 + add lr, lr, #(PLDOFFS*PLDSIZE) + cmp r12, lr, lsr #6 + ble .L_neon_prime_pump + + itt gt + movgt r9, #(PLDOFFS) + rsbsgt r9, r9, lr, lsr #6 + ble .L_neon_prime_pump + + add r10, r1, lr + bic r10, #0x3F + + sub r12, r12, lr, lsr #6 + + cmp r9, r12 + itee le + suble r12, r12, r9 + movgt r9, r12 + movgt r12, #0 + + pld [r1, #((PLDOFFS-1)*PLDSIZE)] +.L_neon_copy_64_loop_outer_doublepld: + pld [r1, #((PLDOFFS)*PLDSIZE)] + vld1.32 {q0, q1}, [r1]! + vld1.32 {q2, q3}, [r1]! + ldr r3, [r10] + subs r9, r9, #1 + vst1.32 {q0, q1}, [r0]! + vst1.32 {q2, q3}, [r0]! + add r10, #64 + bne .L_neon_copy_64_loop_outer_doublepld + cmp r12, #0 + beq .L_neon_pop_before_nopld + + cmp r12, #(512*1024/64) + blt .L_neon_copy_64_loop_outer + +.L_neon_copy_64_loop_ddr: + vld1.32 {q0, q1}, [r1]! + vld1.32 {q2, q3}, [r1]! + pld [r10] + subs r12, r12, #1 + vst1.32 {q0, q1}, [r0]! + vst1.32 {q2, q3}, [r0]! + add r10, #64 + bne .L_neon_copy_64_loop_ddr + b .L_neon_pop_before_nopld + +.L_neon_prime_pump: + mov lr, #(PLDOFFS*PLDSIZE) + add r10, r1, #(PLDOFFS*PLDSIZE) + bic r10, #0x3F + sub r12, r12, #PLDOFFS + ldr r3, [r10, #(-1*PLDSIZE)] + +.L_neon_copy_64_loop_outer: + vld1.32 {q0, q1}, [r1]! + vld1.32 {q2, q3}, [r1]! + ldr r3, [r10] + subs r12, r12, #1 + vst1.32 {q0, q1}, [r0]! + vst1.32 {q2, q3}, [r0]! + add r10, #64 + bne .L_neon_copy_64_loop_outer + +.L_neon_pop_before_nopld: + mov r12, lr, lsr #6 + pop {r9, r10} + .cfi_adjust_cfa_offset -8 + .cfi_restore r9 + .cfi_restore r10 + +.L_neon_copy_64_loop_nopld: + vld1.32 {q8, q9}, [r1]! + vld1.32 {q10, q11}, [r1]! + subs r12, r12, #1 + vst1.32 {q8, q9}, [r0]! + vst1.32 {q10, q11}, [r0]! + bne .L_neon_copy_64_loop_nopld + ands r2, r2, #0x3f + beq .L_neon_exit + +.L_neon_copy_32_a: + movs r3, r2, lsl #27 + bcc .L_neon_16 + vld1.32 {q0,q1}, [r1]! + vst1.32 {q0,q1}, [r0]! + +.L_neon_16: + bpl .L_neon_lt16 + vld1.32 {q8}, [r1]! + vst1.32 {q8}, [r0]! + ands r2, r2, #0x0f + beq .L_neon_exit + +.L_neon_lt16: + movs r3, r2, lsl #29 + bcc 1f + vld1.8 {d0}, [r1]! + vst1.8 {d0}, [r0]! +1: + bge .L_neon_lt4 + vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]! + vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! + +.L_neon_lt4: + movs r2, r2, lsl #31 + itt cs + ldrhcs r3, [r1], #2 + strhcs r3, [r0], #2 + itt mi + ldrbmi r3, [r1] + strbmi r3, [r0] + +.L_neon_exit: + pop {r0, pc}
diff --git a/libc/arch-arm/krait/bionic/memset.S b/libc/arch-arm/krait/bionic/memset.S new file mode 100644 index 0000000..228942c --- /dev/null +++ b/libc/arch-arm/krait/bionic/memset.S
@@ -0,0 +1,85 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +/* + * This code assumes it is running on a processor that supports all arm v7 + * instructions, that supports neon instructions, and that supports + * unaligned neon instruction accesses to memory. + */ + + .fpu neon + .syntax unified + +ENTRY(__memset_chk) + cmp r2, r3 + bls memset + + // Preserve lr for backtrace. + push {lr} + .cfi_def_cfa_offset 4 + .cfi_rel_offset lr, 0 + + bl __memset_chk_fail +END(__memset_chk) + +/* memset() returns its first argument. */ +ENTRY(memset) + mov r3, r0 + vdup.8 q0, r1 + + /* make sure we have at least 32 bytes to write */ + subs r2, r2, #32 + blo 2f + vmov q1, q0 + +1: /* The main loop writes 32 bytes at a time */ + subs r2, r2, #32 + vst1.8 {d0 - d3}, [r3]! + bhs 1b + +2: /* less than 32 left */ + add r2, r2, #32 + tst r2, #0x10 + beq 3f + + // writes 16 bytes, 128-bits aligned + vst1.8 {d0, d1}, [r3]! +3: /* write up to 15-bytes (count in r2) */ + movs ip, r2, lsl #29 + bcc 1f + vst1.8 {d0}, [r3]! +1: bge 2f + vst1.32 {d0[0]}, [r3]! +2: movs ip, r2, lsl #31 + strbmi r1, [r3], #1 + strbcs r1, [r3], #1 + strbcs r1, [r3], #1 + bx lr +END(memset)
diff --git a/libc/arch-arm/krait/bionic/strcmp.S b/libc/arch-arm/krait/bionic/strcmp.S new file mode 100644 index 0000000..b871c76 --- /dev/null +++ b/libc/arch-arm/krait/bionic/strcmp.S
@@ -0,0 +1,485 @@ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +#ifdef __ARMEB__ +#define S2LOMEM lsl +#define S2LOMEMEQ lsleq +#define S2HIMEM lsr +#define MSB 0x000000ff +#define LSB 0xff000000 +#define BYTE0_OFFSET 24 +#define BYTE1_OFFSET 16 +#define BYTE2_OFFSET 8 +#define BYTE3_OFFSET 0 +#else /* not __ARMEB__ */ +#define S2LOMEM lsr +#define S2LOMEMEQ lsreq +#define S2HIMEM lsl +#define BYTE0_OFFSET 0 +#define BYTE1_OFFSET 8 +#define BYTE2_OFFSET 16 +#define BYTE3_OFFSET 24 +#define MSB 0xff000000 +#define LSB 0x000000ff +#endif /* not __ARMEB__ */ + +.syntax unified + +#if defined (__thumb__) + .thumb + .thumb_func +#endif + +ENTRY(strcmp) + /* Use LDRD whenever possible. */ + +/* The main thing to look out for when comparing large blocks is that + the loads do not cross a page boundary when loading past the index + of the byte with the first difference or the first string-terminator. + + For example, if the strings are identical and the string-terminator + is at index k, byte by byte comparison will not load beyond address + s1+k and s2+k; word by word comparison may load up to 3 bytes beyond + k; double word - up to 7 bytes. If the load of these bytes crosses + a page boundary, it might cause a memory fault (if the page is not mapped) + that would not have happened in byte by byte comparison. + + If an address is (double) word aligned, then a load of a (double) word + from that address will not cross a page boundary. + Therefore, the algorithm below considers word and double-word alignment + of strings separately. */ + +/* High-level description of the algorithm. + + * The fast path: if both strings are double-word aligned, + use LDRD to load two words from each string in every loop iteration. + * If the strings have the same offset from a word boundary, + use LDRB to load and compare byte by byte until + the first string is aligned to a word boundary (at most 3 bytes). + This is optimized for quick return on short unaligned strings. + * If the strings have the same offset from a double-word boundary, + use LDRD to load two words from each string in every loop iteration, as in the fast path. + * If the strings do not have the same offset from a double-word boundary, + load a word from the second string before the loop to initialize the queue. + Use LDRD to load two words from every string in every loop iteration. + Inside the loop, load the second word from the second string only after comparing + the first word, using the queued value, to guarantee safety across page boundaries. + * If the strings do not have the same offset from a word boundary, + use LDR and a shift queue. Order of loads and comparisons matters, + similarly to the previous case. + + * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value. + * The only difference between ARM and Thumb modes is the use of CBZ instruction. + * The only difference between big and little endian is the use of REV in little endian + to compute the return value, instead of MOV. +*/ + + .macro m_cbz reg label +#ifdef __thumb2__ + cbz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + beq \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbz */ + + .macro m_cbnz reg label +#ifdef __thumb2__ + cbnz \reg, \label +#else /* not defined __thumb2__ */ + cmp \reg, #0 + bne \label +#endif /* not defined __thumb2__ */ + .endm /* m_cbnz */ + + .macro init + /* Macro to save temporary registers and prepare magic values. */ + subs sp, sp, #16 + .cfi_def_cfa_offset 16 + strd r4, r5, [sp, #8] + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + strd r6, r7, [sp] + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + mvn r6, #0 /* all F */ + mov r7, #0 /* all 0 */ + .endm /* init */ + + .macro magic_compare_and_branch w1 w2 label + /* Macro to compare registers w1 and w2 and conditionally branch to label. */ + cmp \w1, \w2 /* Are w1 and w2 the same? */ + magic_find_zero_bytes \w1 + it eq + cmpeq ip, #0 /* Is there a zero byte in w1? */ + bne \label + .endm /* magic_compare_and_branch */ + + .macro magic_find_zero_bytes w1 + /* Macro to find all-zero bytes in w1, result is in ip. */ + uadd8 ip, \w1, r6 + sel ip, r7, r6 + .endm /* magic_find_zero_bytes */ + + .macro setup_return w1 w2 +#ifdef __ARMEB__ + mov r1, \w1 + mov r2, \w2 +#else /* not __ARMEB__ */ + rev r1, \w1 + rev r2, \w2 +#endif /* not __ARMEB__ */ + .endm /* setup_return */ + + pld [r0, #0] + pld [r1, #0] + + /* Are both strings double-word aligned? */ + orr ip, r0, r1 + tst ip, #7 + bne .L_do_align + + /* Fast path. */ + init + +.L_doubleword_aligned: + + /* Get here when the strings to compare are double-word aligned. */ + /* Compare two words in every iteration. */ + .p2align 2 +2: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string. */ + ldrd r2, r3, [r0], #8 + ldrd r4, r5, [r1], #8 + + magic_compare_and_branch w1=r2, w2=r4, label=.L_return_24 + magic_compare_and_branch w1=r3, w2=r5, label=.L_return_35 + b 2b + +.L_do_align: + /* Is the first string word-aligned? */ + ands ip, r0, #3 + beq .L_word_aligned_r0 + + /* Fast compare byte by byte until the first string is word-aligned. */ + /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes + to read until the next word boundary is 4-ip. */ + bic r0, r0, #3 + ldr r2, [r0], #4 + lsls ip, ip, #31 + beq .L_byte2 + bcs .L_byte3 + +.L_byte1: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE1_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte2: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE2_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbz reg=r3, label=.L_fast_return + +.L_byte3: + ldrb ip, [r1], #1 + uxtb r3, r2, ror #BYTE3_OFFSET + subs ip, r3, ip + bne .L_fast_return + m_cbnz reg=r3, label=.L_word_aligned_r0 + +.L_fast_return: + mov r0, ip + bx lr + +.L_word_aligned_r0: + init + /* The first string is word-aligned. */ + /* Is the second string word-aligned? */ + ands ip, r1, #3 + bne .L_strcmp_unaligned + +.L_word_aligned: + /* The strings are word-aligned. */ + /* Is the first string double-word aligned? */ + tst r0, #4 + beq .L_doubleword_aligned_r0 + + /* If r0 is not double-word aligned yet, align it by loading + and comparing the next word from each string. */ + ldr r2, [r0], #4 + ldr r4, [r1], #4 + magic_compare_and_branch w1=r2 w2=r4 label=.L_return_24 + +.L_doubleword_aligned_r0: + /* Get here when r0 is double-word aligned. */ + /* Is r1 doubleword_aligned? */ + tst r1, #4 + beq .L_doubleword_aligned + + /* Get here when the strings to compare are word-aligned, + r0 is double-word aligned, but r1 is not double-word aligned. */ + + /* Initialize the queue. */ + ldr r5, [r1], #4 + + /* Compare two words in every iteration. */ + .p2align 2 +3: + pld [r0, #16] + pld [r1, #16] + + /* Load the next double-word from each string and compare. */ + ldrd r2, r3, [r0], #8 + magic_compare_and_branch w1=r2 w2=r5 label=.L_return_25 + ldrd r4, r5, [r1], #8 + magic_compare_and_branch w1=r3 w2=r4 label=.L_return_34 + b 3b + + .macro miscmp_word offsetlo offsethi + /* Macro to compare misaligned strings. */ + /* r0, r1 are word-aligned, and at least one of the strings + is not double-word aligned. */ + /* Compare one word in every loop iteration. */ + /* OFFSETLO is the original bit-offset of r1 from a word-boundary, + OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word). */ + + /* Initialize the shift queue. */ + ldr r5, [r1], #4 + + /* Compare one word from each string in every loop iteration. */ + .p2align 2 +7: + ldr r3, [r0], #4 + S2LOMEM r5, r5, #\offsetlo + magic_find_zero_bytes w1=r3 + cmp r7, ip, S2HIMEM #\offsetlo + and r2, r3, r6, S2LOMEM #\offsetlo + it eq + cmpeq r2, r5 + bne .L_return_25 + ldr r5, [r1], #4 + cmp ip, #0 + eor r3, r2, r3 + S2HIMEM r2, r5, #\offsethi + it eq + cmpeq r3, r2 + bne .L_return_32 + b 7b + .endm /* miscmp_word */ + +.L_strcmp_unaligned: + /* r0 is word-aligned, r1 is at offset ip from a word. */ + /* Align r1 to the (previous) word-boundary. */ + bic r1, r1, #3 + + /* Unaligned comparison word by word using LDRs. */ + cmp ip, #2 + beq .L_miscmp_word_16 /* If ip == 2. */ + bge .L_miscmp_word_24 /* If ip == 3. */ + miscmp_word offsetlo=8 offsethi=24 /* If ip == 1. */ +.L_miscmp_word_24: miscmp_word offsetlo=24 offsethi=8 + + +.L_return_32: + setup_return w1=r3, w2=r2 + b .L_do_return +.L_return_34: + setup_return w1=r3, w2=r4 + b .L_do_return +.L_return_25: + setup_return w1=r2, w2=r5 + b .L_do_return +.L_return_35: + setup_return w1=r3, w2=r5 + b .L_do_return +.L_return_24: + setup_return w1=r2, w2=r4 + +.L_do_return: + +#ifdef __ARMEB__ + mov r0, ip +#else /* not __ARMEB__ */ + rev r0, ip +#endif /* not __ARMEB__ */ + + /* Restore temporaries early, before computing the return value. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + /* There is a zero or a different byte between r1 and r2. */ + /* r0 contains a mask of all-zero bytes in r1. */ + /* Using r0 and not ip here because cbz requires low register. */ + m_cbz reg=r0, label=.L_compute_return_value + clz r0, r0 + /* r0 contains the number of bits on the left of the first all-zero byte in r1. */ + rsb r0, r0, #24 + /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1. */ + lsr r1, r1, r0 + lsr r2, r2, r0 + +.L_compute_return_value: + movs r0, #1 + cmp r1, r2 + /* The return value is computed as follows. + If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return. + If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0, + which means r0:=r0-r0-1 and r0 is #-1 at return. + If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1, + which means r0:=r0-r0 and r0 is #0 at return. + (C==0 and Z==1) cannot happen because the carry bit is "not borrow". */ + it ls + sbcls r0, r0, r0 + bx lr + + /* The code from the previous version of strcmp.S handles this + * particular case (the second string is 2 bytes off a word alignment) + * faster than any current version. In this very specific case, use the + * previous version. See bionic/libc/arch-arm/cortex-a15/bionic/strcmp.S + * for the unedited version of this code. + */ +.L_miscmp_word_16: + wp1 .req r0 + wp2 .req r1 + b1 .req r2 + w1 .req r4 + w2 .req r5 + t1 .req ip + @ r3 is scratch + + /* At this point, wp1 (r0) has already been word-aligned. */ +2: + mov b1, #1 + orr b1, b1, b1, lsl #8 + orr b1, b1, b1, lsl #16 + + and t1, wp2, #3 + bic wp2, wp2, #3 + ldr w1, [wp1], #4 + ldr w2, [wp2], #4 + + /* Critical inner Loop: Block with 2 bytes initial overlap */ + .p2align 2 +2: + S2HIMEM t1, w1, #16 + sub r3, w1, b1 + S2LOMEM t1, t1, #16 + bic r3, r3, w1 + cmp t1, w2, S2LOMEM #16 + bne 4f + ands r3, r3, b1, lsl #7 + it eq + ldreq w2, [wp2], #4 + bne 5f + eor t1, t1, w1 + cmp t1, w2, S2HIMEM #16 + bne 6f + ldr w1, [wp1], #4 + b 2b + +5: +#ifdef __ARMEB__ + /* The syndrome value may contain false ones if the string ends + * with the bytes 0x01 0x00 + */ + tst w1, #0xff000000 + it ne + tstne w1, #0x00ff0000 + beq 7f +#else + lsls r3, r3, #16 + bne 7f +#endif + ldrh w2, [wp2] + S2LOMEM t1, w1, #16 +#ifdef __ARMEB__ + lsl w2, w2, #16 +#endif + b 8f + +6: + S2HIMEM w2, w2, #16 + S2LOMEM t1, w1, #16 +4: + S2LOMEM w2, w2, #16 + b 8f + +7: + mov r0, #0 + + /* Restore registers and stack. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + bx lr + +8: + and r2, t1, #LSB + and r0, w2, #LSB + cmp r0, #1 + it cs + cmpcs r0, r2 + itt eq + S2LOMEMEQ t1, t1, #8 + S2LOMEMEQ w2, w2, #8 + beq 8b + sub r0, r2, r0 + + /* Restore registers and stack. */ + ldrd r6, r7, [sp] + ldrd r4, r5, [sp, #8] + adds sp, sp, #16 + .cfi_def_cfa_offset 0 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + + bx lr +END(strcmp)
diff --git a/libc/arch-arm/syscalls/___clock_nanosleep.S b/libc/arch-arm/syscalls/___clock_nanosleep.S new file mode 100644 index 0000000..ef8f065 --- /dev/null +++ b/libc/arch-arm/syscalls/___clock_nanosleep.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___clock_nanosleep) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_clock_nanosleep + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___clock_nanosleep) +.hidden ___clock_nanosleep
diff --git a/libc/arch-arm/syscalls/___close.S b/libc/arch-arm/syscalls/___close.S new file mode 100644 index 0000000..05d3352 --- /dev/null +++ b/libc/arch-arm/syscalls/___close.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___close) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_close + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___close) +.hidden ___close
diff --git a/libc/arch-arm/syscalls/___faccessat.S b/libc/arch-arm/syscalls/___faccessat.S new file mode 100644 index 0000000..8bb4cf8 --- /dev/null +++ b/libc/arch-arm/syscalls/___faccessat.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___faccessat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_faccessat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___faccessat) +.hidden ___faccessat
diff --git a/libc/arch-arm/syscalls/___fchmod.S b/libc/arch-arm/syscalls/___fchmod.S new file mode 100644 index 0000000..b2312cb --- /dev/null +++ b/libc/arch-arm/syscalls/___fchmod.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmod) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fchmod + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___fchmod) +.hidden ___fchmod
diff --git a/libc/arch-arm/syscalls/___fchmodat.S b/libc/arch-arm/syscalls/___fchmodat.S new file mode 100644 index 0000000..4773610 --- /dev/null +++ b/libc/arch-arm/syscalls/___fchmodat.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmodat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fchmodat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___fchmodat) +.hidden ___fchmodat
diff --git a/libc/arch-arm/syscalls/___fgetxattr.S b/libc/arch-arm/syscalls/___fgetxattr.S new file mode 100644 index 0000000..25be039 --- /dev/null +++ b/libc/arch-arm/syscalls/___fgetxattr.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fgetxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fgetxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___fgetxattr) +.hidden ___fgetxattr
diff --git a/libc/arch-arm/syscalls/___flistxattr.S b/libc/arch-arm/syscalls/___flistxattr.S new file mode 100644 index 0000000..904e4ca --- /dev/null +++ b/libc/arch-arm/syscalls/___flistxattr.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___flistxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_flistxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___flistxattr) +.hidden ___flistxattr
diff --git a/libc/arch-arm/syscalls/___fsetxattr.S b/libc/arch-arm/syscalls/___fsetxattr.S new file mode 100644 index 0000000..5445191 --- /dev/null +++ b/libc/arch-arm/syscalls/___fsetxattr.S
@@ -0,0 +1,23 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fsetxattr) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_fsetxattr + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___fsetxattr) +.hidden ___fsetxattr
diff --git a/libc/arch-arm/syscalls/___mremap.S b/libc/arch-arm/syscalls/___mremap.S new file mode 100644 index 0000000..ade8d78 --- /dev/null +++ b/libc/arch-arm/syscalls/___mremap.S
@@ -0,0 +1,23 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___mremap) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_mremap + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___mremap) +.hidden ___mremap
diff --git a/libc/arch-arm/syscalls/___rt_sigqueueinfo.S b/libc/arch-arm/syscalls/___rt_sigqueueinfo.S new file mode 100644 index 0000000..1367e56 --- /dev/null +++ b/libc/arch-arm/syscalls/___rt_sigqueueinfo.S
@@ -0,0 +1,17 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___rt_sigqueueinfo) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigqueueinfo + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(___rt_sigqueueinfo) +.hidden ___rt_sigqueueinfo
diff --git a/libc/arch-arm/syscalls/__accept4.S b/libc/arch-arm/syscalls/__accept4.S new file mode 100644 index 0000000..42aa47c --- /dev/null +++ b/libc/arch-arm/syscalls/__accept4.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_accept4 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__accept4)
diff --git a/libc/arch-arm/syscalls/__arm_fadvise64_64.S b/libc/arch-arm/syscalls/__arm_fadvise64_64.S new file mode 100644 index 0000000..761c4d6 --- /dev/null +++ b/libc/arch-arm/syscalls/__arm_fadvise64_64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__arm_fadvise64_64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_arm_fadvise64_64 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__arm_fadvise64_64)
diff --git a/libc/arch-arm/syscalls/__brk.S b/libc/arch-arm/syscalls/__brk.S new file mode 100644 index 0000000..246924c --- /dev/null +++ b/libc/arch-arm/syscalls/__brk.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_brk + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__brk)
diff --git a/libc/arch-arm/syscalls/__clock_gettime.S b/libc/arch-arm/syscalls/__clock_gettime.S new file mode 100644 index 0000000..30eff03 --- /dev/null +++ b/libc/arch-arm/syscalls/__clock_gettime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__clock_gettime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_clock_gettime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__clock_gettime)
diff --git a/libc/arch-arm/syscalls/__connect.S b/libc/arch-arm/syscalls/__connect.S new file mode 100644 index 0000000..873b14d --- /dev/null +++ b/libc/arch-arm/syscalls/__connect.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_connect + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__connect)
diff --git a/libc/arch-arm/syscalls/__epoll_pwait.S b/libc/arch-arm/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..3642ee3 --- /dev/null +++ b/libc/arch-arm/syscalls/__epoll_pwait.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_epoll_pwait + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__epoll_pwait)
diff --git a/libc/arch-arm/syscalls/__exit.S b/libc/arch-arm/syscalls/__exit.S new file mode 100644 index 0000000..4ed31b0 --- /dev/null +++ b/libc/arch-arm/syscalls/__exit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_exit + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__exit)
diff --git a/libc/arch-arm/syscalls/__fcntl64.S b/libc/arch-arm/syscalls/__fcntl64.S new file mode 100644 index 0000000..0afdbee --- /dev/null +++ b/libc/arch-arm/syscalls/__fcntl64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fcntl64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fcntl64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__fcntl64)
diff --git a/libc/arch-arm/syscalls/__fstatfs64.S b/libc/arch-arm/syscalls/__fstatfs64.S new file mode 100644 index 0000000..9117313 --- /dev/null +++ b/libc/arch-arm/syscalls/__fstatfs64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fstatfs64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fstatfs64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__fstatfs64)
diff --git a/libc/arch-arm/syscalls/__getcpu.S b/libc/arch-arm/syscalls/__getcpu.S new file mode 100644 index 0000000..430acb3 --- /dev/null +++ b/libc/arch-arm/syscalls/__getcpu.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getcpu + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__getcpu)
diff --git a/libc/arch-arm/syscalls/__getcwd.S b/libc/arch-arm/syscalls/__getcwd.S new file mode 100644 index 0000000..53000b8 --- /dev/null +++ b/libc/arch-arm/syscalls/__getcwd.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getcwd + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__getcwd)
diff --git a/libc/arch-arm/syscalls/__getdents64.S b/libc/arch-arm/syscalls/__getdents64.S new file mode 100644 index 0000000..0ea61b8 --- /dev/null +++ b/libc/arch-arm/syscalls/__getdents64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getdents64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__getdents64)
diff --git a/libc/arch-arm/syscalls/__getpid.S b/libc/arch-arm/syscalls/__getpid.S new file mode 100644 index 0000000..b555385 --- /dev/null +++ b/libc/arch-arm/syscalls/__getpid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getpid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__getpid)
diff --git a/libc/arch-arm/syscalls/__getpriority.S b/libc/arch-arm/syscalls/__getpriority.S new file mode 100644 index 0000000..34f4bea --- /dev/null +++ b/libc/arch-arm/syscalls/__getpriority.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getpriority + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__getpriority)
diff --git a/libc/arch-arm/syscalls/__gettimeofday.S b/libc/arch-arm/syscalls/__gettimeofday.S new file mode 100644 index 0000000..de0eca5 --- /dev/null +++ b/libc/arch-arm/syscalls/__gettimeofday.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__gettimeofday) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_gettimeofday + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__gettimeofday)
diff --git a/libc/arch-arm/syscalls/__ioctl.S b/libc/arch-arm/syscalls/__ioctl.S new file mode 100644 index 0000000..5871e58 --- /dev/null +++ b/libc/arch-arm/syscalls/__ioctl.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_ioctl + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__ioctl)
diff --git a/libc/arch-arm/syscalls/__llseek.S b/libc/arch-arm/syscalls/__llseek.S new file mode 100644 index 0000000..3cff318 --- /dev/null +++ b/libc/arch-arm/syscalls/__llseek.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__llseek) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR__llseek + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__llseek)
diff --git a/libc/arch-arm/syscalls/__mmap2.S b/libc/arch-arm/syscalls/__mmap2.S new file mode 100644 index 0000000..f11e467 --- /dev/null +++ b/libc/arch-arm/syscalls/__mmap2.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__mmap2) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_mmap2 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__mmap2)
diff --git a/libc/arch-arm/syscalls/__openat.S b/libc/arch-arm/syscalls/__openat.S new file mode 100644 index 0000000..403d9b5 --- /dev/null +++ b/libc/arch-arm/syscalls/__openat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_openat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__openat)
diff --git a/libc/arch-arm/syscalls/__ppoll.S b/libc/arch-arm/syscalls/__ppoll.S new file mode 100644 index 0000000..02de8a8 --- /dev/null +++ b/libc/arch-arm/syscalls/__ppoll.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_ppoll + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__ppoll)
diff --git a/libc/arch-arm/syscalls/__preadv64.S b/libc/arch-arm/syscalls/__preadv64.S new file mode 100644 index 0000000..19eaaa5 --- /dev/null +++ b/libc/arch-arm/syscalls/__preadv64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__preadv64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_preadv + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__preadv64)
diff --git a/libc/arch-arm/syscalls/__pselect6.S b/libc/arch-arm/syscalls/__pselect6.S new file mode 100644 index 0000000..8f31e1b --- /dev/null +++ b/libc/arch-arm/syscalls/__pselect6.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_pselect6 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__pselect6)
diff --git a/libc/arch-arm/syscalls/__ptrace.S b/libc/arch-arm/syscalls/__ptrace.S new file mode 100644 index 0000000..8ad554d --- /dev/null +++ b/libc/arch-arm/syscalls/__ptrace.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_ptrace + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__ptrace)
diff --git a/libc/arch-arm/syscalls/__pwritev64.S b/libc/arch-arm/syscalls/__pwritev64.S new file mode 100644 index 0000000..afcbe40 --- /dev/null +++ b/libc/arch-arm/syscalls/__pwritev64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pwritev64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_pwritev + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__pwritev64)
diff --git a/libc/arch-arm/syscalls/__reboot.S b/libc/arch-arm/syscalls/__reboot.S new file mode 100644 index 0000000..15ca814 --- /dev/null +++ b/libc/arch-arm/syscalls/__reboot.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_reboot + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__reboot)
diff --git a/libc/arch-arm/syscalls/__rt_sigaction.S b/libc/arch-arm/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..21d9977 --- /dev/null +++ b/libc/arch-arm/syscalls/__rt_sigaction.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigaction + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__rt_sigaction)
diff --git a/libc/arch-arm/syscalls/__rt_sigpending.S b/libc/arch-arm/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..b726b85 --- /dev/null +++ b/libc/arch-arm/syscalls/__rt_sigpending.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigpending + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__rt_sigpending)
diff --git a/libc/arch-arm/syscalls/__rt_sigprocmask.S b/libc/arch-arm/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..11b326f --- /dev/null +++ b/libc/arch-arm/syscalls/__rt_sigprocmask.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigprocmask + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__rt_sigprocmask)
diff --git a/libc/arch-arm/syscalls/__rt_sigsuspend.S b/libc/arch-arm/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..5d06418 --- /dev/null +++ b/libc/arch-arm/syscalls/__rt_sigsuspend.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigsuspend + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__rt_sigsuspend)
diff --git a/libc/arch-arm/syscalls/__rt_sigtimedwait.S b/libc/arch-arm/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..dc7c3e7 --- /dev/null +++ b/libc/arch-arm/syscalls/__rt_sigtimedwait.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_rt_sigtimedwait + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__rt_sigtimedwait)
diff --git a/libc/arch-arm/syscalls/__sched_getaffinity.S b/libc/arch-arm/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..21f8330 --- /dev/null +++ b/libc/arch-arm/syscalls/__sched_getaffinity.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_getaffinity + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__sched_getaffinity)
diff --git a/libc/arch-arm/syscalls/__set_tid_address.S b/libc/arch-arm/syscalls/__set_tid_address.S new file mode 100644 index 0000000..79dfd7f --- /dev/null +++ b/libc/arch-arm/syscalls/__set_tid_address.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_set_tid_address + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__set_tid_address)
diff --git a/libc/arch-arm/syscalls/__set_tls.S b/libc/arch-arm/syscalls/__set_tls.S new file mode 100644 index 0000000..a9a4b9a --- /dev/null +++ b/libc/arch-arm/syscalls/__set_tls.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tls) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__ARM_NR_set_tls + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__set_tls)
diff --git a/libc/arch-arm/syscalls/__sigaction.S b/libc/arch-arm/syscalls/__sigaction.S new file mode 100644 index 0000000..8f3f143 --- /dev/null +++ b/libc/arch-arm/syscalls/__sigaction.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sigaction) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sigaction + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__sigaction)
diff --git a/libc/arch-arm/syscalls/__signalfd4.S b/libc/arch-arm/syscalls/__signalfd4.S new file mode 100644 index 0000000..51a27c8 --- /dev/null +++ b/libc/arch-arm/syscalls/__signalfd4.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_signalfd4 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__signalfd4)
diff --git a/libc/arch-arm/syscalls/__socket.S b/libc/arch-arm/syscalls/__socket.S new file mode 100644 index 0000000..c50cd6f --- /dev/null +++ b/libc/arch-arm/syscalls/__socket.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_socket + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__socket)
diff --git a/libc/arch-arm/syscalls/__statfs64.S b/libc/arch-arm/syscalls/__statfs64.S new file mode 100644 index 0000000..320b0ee --- /dev/null +++ b/libc/arch-arm/syscalls/__statfs64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__statfs64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_statfs64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__statfs64)
diff --git a/libc/arch-arm/syscalls/__sync_file_range2.S b/libc/arch-arm/syscalls/__sync_file_range2.S new file mode 100644 index 0000000..4346e1b --- /dev/null +++ b/libc/arch-arm/syscalls/__sync_file_range2.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sync_file_range2) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_sync_file_range2 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__sync_file_range2)
diff --git a/libc/arch-arm/syscalls/__timer_create.S b/libc/arch-arm/syscalls/__timer_create.S new file mode 100644 index 0000000..fd7567b --- /dev/null +++ b/libc/arch-arm/syscalls/__timer_create.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timer_create + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__timer_create)
diff --git a/libc/arch-arm/syscalls/__timer_delete.S b/libc/arch-arm/syscalls/__timer_delete.S new file mode 100644 index 0000000..6761abb --- /dev/null +++ b/libc/arch-arm/syscalls/__timer_delete.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timer_delete + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__timer_delete)
diff --git a/libc/arch-arm/syscalls/__timer_getoverrun.S b/libc/arch-arm/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..a925d83 --- /dev/null +++ b/libc/arch-arm/syscalls/__timer_getoverrun.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timer_getoverrun + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__timer_getoverrun)
diff --git a/libc/arch-arm/syscalls/__timer_gettime.S b/libc/arch-arm/syscalls/__timer_gettime.S new file mode 100644 index 0000000..c0da770 --- /dev/null +++ b/libc/arch-arm/syscalls/__timer_gettime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timer_gettime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__timer_gettime)
diff --git a/libc/arch-arm/syscalls/__timer_settime.S b/libc/arch-arm/syscalls/__timer_settime.S new file mode 100644 index 0000000..de4e7e6 --- /dev/null +++ b/libc/arch-arm/syscalls/__timer_settime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timer_settime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__timer_settime)
diff --git a/libc/arch-arm/syscalls/__waitid.S b/libc/arch-arm/syscalls/__waitid.S new file mode 100644 index 0000000..f4dfa59 --- /dev/null +++ b/libc/arch-arm/syscalls/__waitid.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_waitid + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(__waitid)
diff --git a/libc/arch-arm/syscalls/_exit.S b/libc/arch-arm/syscalls/_exit.S new file mode 100644 index 0000000..1c3d174 --- /dev/null +++ b/libc/arch-arm/syscalls/_exit.S
@@ -0,0 +1,18 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_exit_group + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(_exit) + +ALIAS_SYMBOL(_Exit, _exit)
diff --git a/libc/arch-arm/syscalls/acct.S b/libc/arch-arm/syscalls/acct.S new file mode 100644 index 0000000..cdf1099 --- /dev/null +++ b/libc/arch-arm/syscalls/acct.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_acct + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(acct)
diff --git a/libc/arch-arm/syscalls/adjtimex.S b/libc/arch-arm/syscalls/adjtimex.S new file mode 100644 index 0000000..6ebae7e --- /dev/null +++ b/libc/arch-arm/syscalls/adjtimex.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(adjtimex) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_adjtimex + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(adjtimex)
diff --git a/libc/arch-arm/syscalls/bind.S b/libc/arch-arm/syscalls/bind.S new file mode 100644 index 0000000..af518d8 --- /dev/null +++ b/libc/arch-arm/syscalls/bind.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_bind + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(bind)
diff --git a/libc/arch-arm/syscalls/cacheflush.S b/libc/arch-arm/syscalls/cacheflush.S new file mode 100644 index 0000000..752749a --- /dev/null +++ b/libc/arch-arm/syscalls/cacheflush.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(cacheflush) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__ARM_NR_cacheflush + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(cacheflush)
diff --git a/libc/arch-arm/syscalls/capget.S b/libc/arch-arm/syscalls/capget.S new file mode 100644 index 0000000..9be110b --- /dev/null +++ b/libc/arch-arm/syscalls/capget.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_capget + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(capget)
diff --git a/libc/arch-arm/syscalls/capset.S b/libc/arch-arm/syscalls/capset.S new file mode 100644 index 0000000..0bd5009 --- /dev/null +++ b/libc/arch-arm/syscalls/capset.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_capset + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(capset)
diff --git a/libc/arch-arm/syscalls/chdir.S b/libc/arch-arm/syscalls/chdir.S new file mode 100644 index 0000000..c75f5e2 --- /dev/null +++ b/libc/arch-arm/syscalls/chdir.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_chdir + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(chdir)
diff --git a/libc/arch-arm/syscalls/chroot.S b/libc/arch-arm/syscalls/chroot.S new file mode 100644 index 0000000..d197d42 --- /dev/null +++ b/libc/arch-arm/syscalls/chroot.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_chroot + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(chroot)
diff --git a/libc/arch-arm/syscalls/clock_adjtime.S b/libc/arch-arm/syscalls/clock_adjtime.S new file mode 100644 index 0000000..e59a240 --- /dev/null +++ b/libc/arch-arm/syscalls/clock_adjtime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_adjtime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_clock_adjtime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(clock_adjtime)
diff --git a/libc/arch-arm/syscalls/clock_getres.S b/libc/arch-arm/syscalls/clock_getres.S new file mode 100644 index 0000000..e101127 --- /dev/null +++ b/libc/arch-arm/syscalls/clock_getres.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_clock_getres + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(clock_getres)
diff --git a/libc/arch-arm/syscalls/clock_settime.S b/libc/arch-arm/syscalls/clock_settime.S new file mode 100644 index 0000000..f00a072 --- /dev/null +++ b/libc/arch-arm/syscalls/clock_settime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_clock_settime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(clock_settime)
diff --git a/libc/arch-arm/syscalls/delete_module.S b/libc/arch-arm/syscalls/delete_module.S new file mode 100644 index 0000000..80dd0f5 --- /dev/null +++ b/libc/arch-arm/syscalls/delete_module.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_delete_module + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(delete_module)
diff --git a/libc/arch-arm/syscalls/dup.S b/libc/arch-arm/syscalls/dup.S new file mode 100644 index 0000000..0d06bdc --- /dev/null +++ b/libc/arch-arm/syscalls/dup.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_dup + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(dup)
diff --git a/libc/arch-arm/syscalls/dup3.S b/libc/arch-arm/syscalls/dup3.S new file mode 100644 index 0000000..7dea858 --- /dev/null +++ b/libc/arch-arm/syscalls/dup3.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_dup3 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(dup3)
diff --git a/libc/arch-arm/syscalls/epoll_create1.S b/libc/arch-arm/syscalls/epoll_create1.S new file mode 100644 index 0000000..8b413d9 --- /dev/null +++ b/libc/arch-arm/syscalls/epoll_create1.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_epoll_create1 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(epoll_create1)
diff --git a/libc/arch-arm/syscalls/epoll_ctl.S b/libc/arch-arm/syscalls/epoll_ctl.S new file mode 100644 index 0000000..807dd69 --- /dev/null +++ b/libc/arch-arm/syscalls/epoll_ctl.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_epoll_ctl + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(epoll_ctl)
diff --git a/libc/arch-arm/syscalls/eventfd.S b/libc/arch-arm/syscalls/eventfd.S new file mode 100644 index 0000000..51f4a49 --- /dev/null +++ b/libc/arch-arm/syscalls/eventfd.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_eventfd2 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(eventfd)
diff --git a/libc/arch-arm/syscalls/execve.S b/libc/arch-arm/syscalls/execve.S new file mode 100644 index 0000000..1b72f0e --- /dev/null +++ b/libc/arch-arm/syscalls/execve.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_execve + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(execve)
diff --git a/libc/arch-arm/syscalls/fallocate64.S b/libc/arch-arm/syscalls/fallocate64.S new file mode 100644 index 0000000..4bfd5e3 --- /dev/null +++ b/libc/arch-arm/syscalls/fallocate64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_fallocate + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fallocate64)
diff --git a/libc/arch-arm/syscalls/fchdir.S b/libc/arch-arm/syscalls/fchdir.S new file mode 100644 index 0000000..dca18c4 --- /dev/null +++ b/libc/arch-arm/syscalls/fchdir.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fchdir + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fchdir)
diff --git a/libc/arch-arm/syscalls/fchown.S b/libc/arch-arm/syscalls/fchown.S new file mode 100644 index 0000000..51ee60c --- /dev/null +++ b/libc/arch-arm/syscalls/fchown.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fchown32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fchown)
diff --git a/libc/arch-arm/syscalls/fchownat.S b/libc/arch-arm/syscalls/fchownat.S new file mode 100644 index 0000000..2aac0fe --- /dev/null +++ b/libc/arch-arm/syscalls/fchownat.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_fchownat + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fchownat)
diff --git a/libc/arch-arm/syscalls/fdatasync.S b/libc/arch-arm/syscalls/fdatasync.S new file mode 100644 index 0000000..f97adc6 --- /dev/null +++ b/libc/arch-arm/syscalls/fdatasync.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fdatasync + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fdatasync)
diff --git a/libc/arch-arm/syscalls/flock.S b/libc/arch-arm/syscalls/flock.S new file mode 100644 index 0000000..e2874f6 --- /dev/null +++ b/libc/arch-arm/syscalls/flock.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_flock + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(flock)
diff --git a/libc/arch-arm/syscalls/fremovexattr.S b/libc/arch-arm/syscalls/fremovexattr.S new file mode 100644 index 0000000..89be704 --- /dev/null +++ b/libc/arch-arm/syscalls/fremovexattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fremovexattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fremovexattr)
diff --git a/libc/arch-arm/syscalls/fstat64.S b/libc/arch-arm/syscalls/fstat64.S new file mode 100644 index 0000000..c2c7101 --- /dev/null +++ b/libc/arch-arm/syscalls/fstat64.S
@@ -0,0 +1,18 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstat64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fstat64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fstat64) + +ALIAS_SYMBOL(fstat, fstat64)
diff --git a/libc/arch-arm/syscalls/fstatat64.S b/libc/arch-arm/syscalls/fstatat64.S new file mode 100644 index 0000000..545dc16 --- /dev/null +++ b/libc/arch-arm/syscalls/fstatat64.S
@@ -0,0 +1,18 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatat64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fstatat64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fstatat64) + +ALIAS_SYMBOL(fstatat, fstatat64)
diff --git a/libc/arch-arm/syscalls/fsync.S b/libc/arch-arm/syscalls/fsync.S new file mode 100644 index 0000000..24b9a87 --- /dev/null +++ b/libc/arch-arm/syscalls/fsync.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_fsync + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(fsync)
diff --git a/libc/arch-arm/syscalls/ftruncate64.S b/libc/arch-arm/syscalls/ftruncate64.S new file mode 100644 index 0000000..ee1a2a6 --- /dev/null +++ b/libc/arch-arm/syscalls/ftruncate64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_ftruncate64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(ftruncate64)
diff --git a/libc/arch-arm/syscalls/getegid.S b/libc/arch-arm/syscalls/getegid.S new file mode 100644 index 0000000..f4e17b5 --- /dev/null +++ b/libc/arch-arm/syscalls/getegid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getegid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getegid)
diff --git a/libc/arch-arm/syscalls/geteuid.S b/libc/arch-arm/syscalls/geteuid.S new file mode 100644 index 0000000..01898f8 --- /dev/null +++ b/libc/arch-arm/syscalls/geteuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_geteuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(geteuid)
diff --git a/libc/arch-arm/syscalls/getgid.S b/libc/arch-arm/syscalls/getgid.S new file mode 100644 index 0000000..ee124a6 --- /dev/null +++ b/libc/arch-arm/syscalls/getgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getgid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getgid)
diff --git a/libc/arch-arm/syscalls/getgroups.S b/libc/arch-arm/syscalls/getgroups.S new file mode 100644 index 0000000..4c1bfdb --- /dev/null +++ b/libc/arch-arm/syscalls/getgroups.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getgroups32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getgroups)
diff --git a/libc/arch-arm/syscalls/getitimer.S b/libc/arch-arm/syscalls/getitimer.S new file mode 100644 index 0000000..b9773ad --- /dev/null +++ b/libc/arch-arm/syscalls/getitimer.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getitimer + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getitimer)
diff --git a/libc/arch-arm/syscalls/getpeername.S b/libc/arch-arm/syscalls/getpeername.S new file mode 100644 index 0000000..6bf6002 --- /dev/null +++ b/libc/arch-arm/syscalls/getpeername.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getpeername + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getpeername)
diff --git a/libc/arch-arm/syscalls/getpgid.S b/libc/arch-arm/syscalls/getpgid.S new file mode 100644 index 0000000..d5c9c8a --- /dev/null +++ b/libc/arch-arm/syscalls/getpgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getpgid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getpgid)
diff --git a/libc/arch-arm/syscalls/getppid.S b/libc/arch-arm/syscalls/getppid.S new file mode 100644 index 0000000..91db24e --- /dev/null +++ b/libc/arch-arm/syscalls/getppid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getppid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getppid)
diff --git a/libc/arch-arm/syscalls/getresgid.S b/libc/arch-arm/syscalls/getresgid.S new file mode 100644 index 0000000..8fb7f28 --- /dev/null +++ b/libc/arch-arm/syscalls/getresgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getresgid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getresgid)
diff --git a/libc/arch-arm/syscalls/getresuid.S b/libc/arch-arm/syscalls/getresuid.S new file mode 100644 index 0000000..ebec6e1 --- /dev/null +++ b/libc/arch-arm/syscalls/getresuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getresuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getresuid)
diff --git a/libc/arch-arm/syscalls/getrlimit.S b/libc/arch-arm/syscalls/getrlimit.S new file mode 100644 index 0000000..0c9e662 --- /dev/null +++ b/libc/arch-arm/syscalls/getrlimit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_ugetrlimit + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getrlimit)
diff --git a/libc/arch-arm/syscalls/getrusage.S b/libc/arch-arm/syscalls/getrusage.S new file mode 100644 index 0000000..e74a4ad --- /dev/null +++ b/libc/arch-arm/syscalls/getrusage.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getrusage + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getrusage)
diff --git a/libc/arch-arm/syscalls/getsid.S b/libc/arch-arm/syscalls/getsid.S new file mode 100644 index 0000000..c918820 --- /dev/null +++ b/libc/arch-arm/syscalls/getsid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getsid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getsid)
diff --git a/libc/arch-arm/syscalls/getsockname.S b/libc/arch-arm/syscalls/getsockname.S new file mode 100644 index 0000000..a30a291 --- /dev/null +++ b/libc/arch-arm/syscalls/getsockname.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getsockname + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getsockname)
diff --git a/libc/arch-arm/syscalls/getsockopt.S b/libc/arch-arm/syscalls/getsockopt.S new file mode 100644 index 0000000..4143bbd --- /dev/null +++ b/libc/arch-arm/syscalls/getsockopt.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_getsockopt + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getsockopt)
diff --git a/libc/arch-arm/syscalls/getuid.S b/libc/arch-arm/syscalls/getuid.S new file mode 100644 index 0000000..cdc86bc --- /dev/null +++ b/libc/arch-arm/syscalls/getuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getuid)
diff --git a/libc/arch-arm/syscalls/getxattr.S b/libc/arch-arm/syscalls/getxattr.S new file mode 100644 index 0000000..116d917 --- /dev/null +++ b/libc/arch-arm/syscalls/getxattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_getxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(getxattr)
diff --git a/libc/arch-arm/syscalls/init_module.S b/libc/arch-arm/syscalls/init_module.S new file mode 100644 index 0000000..8fecf68 --- /dev/null +++ b/libc/arch-arm/syscalls/init_module.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_init_module + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(init_module)
diff --git a/libc/arch-arm/syscalls/inotify_add_watch.S b/libc/arch-arm/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..61e666c --- /dev/null +++ b/libc/arch-arm/syscalls/inotify_add_watch.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_inotify_add_watch + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(inotify_add_watch)
diff --git a/libc/arch-arm/syscalls/inotify_init1.S b/libc/arch-arm/syscalls/inotify_init1.S new file mode 100644 index 0000000..6cf066e --- /dev/null +++ b/libc/arch-arm/syscalls/inotify_init1.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_inotify_init1 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(inotify_init1)
diff --git a/libc/arch-arm/syscalls/inotify_rm_watch.S b/libc/arch-arm/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..1455da1 --- /dev/null +++ b/libc/arch-arm/syscalls/inotify_rm_watch.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_inotify_rm_watch + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(inotify_rm_watch)
diff --git a/libc/arch-arm/syscalls/kill.S b/libc/arch-arm/syscalls/kill.S new file mode 100644 index 0000000..82df861 --- /dev/null +++ b/libc/arch-arm/syscalls/kill.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_kill + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(kill)
diff --git a/libc/arch-arm/syscalls/klogctl.S b/libc/arch-arm/syscalls/klogctl.S new file mode 100644 index 0000000..47a03c6 --- /dev/null +++ b/libc/arch-arm/syscalls/klogctl.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_syslog + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(klogctl)
diff --git a/libc/arch-arm/syscalls/lgetxattr.S b/libc/arch-arm/syscalls/lgetxattr.S new file mode 100644 index 0000000..157271c --- /dev/null +++ b/libc/arch-arm/syscalls/lgetxattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_lgetxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(lgetxattr)
diff --git a/libc/arch-arm/syscalls/linkat.S b/libc/arch-arm/syscalls/linkat.S new file mode 100644 index 0000000..6e74d06 --- /dev/null +++ b/libc/arch-arm/syscalls/linkat.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_linkat + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(linkat)
diff --git a/libc/arch-arm/syscalls/listen.S b/libc/arch-arm/syscalls/listen.S new file mode 100644 index 0000000..5ad75c0 --- /dev/null +++ b/libc/arch-arm/syscalls/listen.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_listen + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(listen)
diff --git a/libc/arch-arm/syscalls/listxattr.S b/libc/arch-arm/syscalls/listxattr.S new file mode 100644 index 0000000..093927d --- /dev/null +++ b/libc/arch-arm/syscalls/listxattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_listxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(listxattr)
diff --git a/libc/arch-arm/syscalls/llistxattr.S b/libc/arch-arm/syscalls/llistxattr.S new file mode 100644 index 0000000..5d0e7c8 --- /dev/null +++ b/libc/arch-arm/syscalls/llistxattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_llistxattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(llistxattr)
diff --git a/libc/arch-arm/syscalls/lremovexattr.S b/libc/arch-arm/syscalls/lremovexattr.S new file mode 100644 index 0000000..4e0bcec --- /dev/null +++ b/libc/arch-arm/syscalls/lremovexattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_lremovexattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(lremovexattr)
diff --git a/libc/arch-arm/syscalls/lseek.S b/libc/arch-arm/syscalls/lseek.S new file mode 100644 index 0000000..cbdc441 --- /dev/null +++ b/libc/arch-arm/syscalls/lseek.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_lseek + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(lseek)
diff --git a/libc/arch-arm/syscalls/lsetxattr.S b/libc/arch-arm/syscalls/lsetxattr.S new file mode 100644 index 0000000..c41fb88 --- /dev/null +++ b/libc/arch-arm/syscalls/lsetxattr.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_lsetxattr + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(lsetxattr)
diff --git a/libc/arch-arm/syscalls/madvise.S b/libc/arch-arm/syscalls/madvise.S new file mode 100644 index 0000000..c2d7d20 --- /dev/null +++ b/libc/arch-arm/syscalls/madvise.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_madvise + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(madvise)
diff --git a/libc/arch-arm/syscalls/mincore.S b/libc/arch-arm/syscalls/mincore.S new file mode 100644 index 0000000..c93fe94 --- /dev/null +++ b/libc/arch-arm/syscalls/mincore.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mincore + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mincore)
diff --git a/libc/arch-arm/syscalls/mkdirat.S b/libc/arch-arm/syscalls/mkdirat.S new file mode 100644 index 0000000..4f93c61 --- /dev/null +++ b/libc/arch-arm/syscalls/mkdirat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mkdirat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mkdirat)
diff --git a/libc/arch-arm/syscalls/mknodat.S b/libc/arch-arm/syscalls/mknodat.S new file mode 100644 index 0000000..91baae8 --- /dev/null +++ b/libc/arch-arm/syscalls/mknodat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mknodat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mknodat)
diff --git a/libc/arch-arm/syscalls/mlock.S b/libc/arch-arm/syscalls/mlock.S new file mode 100644 index 0000000..eb72f6f --- /dev/null +++ b/libc/arch-arm/syscalls/mlock.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mlock + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mlock)
diff --git a/libc/arch-arm/syscalls/mlockall.S b/libc/arch-arm/syscalls/mlockall.S new file mode 100644 index 0000000..2984087 --- /dev/null +++ b/libc/arch-arm/syscalls/mlockall.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mlockall + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mlockall)
diff --git a/libc/arch-arm/syscalls/mount.S b/libc/arch-arm/syscalls/mount.S new file mode 100644 index 0000000..ed28ab2 --- /dev/null +++ b/libc/arch-arm/syscalls/mount.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_mount + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mount)
diff --git a/libc/arch-arm/syscalls/mprotect.S b/libc/arch-arm/syscalls/mprotect.S new file mode 100644 index 0000000..9bb1282 --- /dev/null +++ b/libc/arch-arm/syscalls/mprotect.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_mprotect + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(mprotect)
diff --git a/libc/arch-arm/syscalls/msync.S b/libc/arch-arm/syscalls/msync.S new file mode 100644 index 0000000..bcbab04 --- /dev/null +++ b/libc/arch-arm/syscalls/msync.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_msync + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(msync)
diff --git a/libc/arch-arm/syscalls/munlock.S b/libc/arch-arm/syscalls/munlock.S new file mode 100644 index 0000000..bf1b814 --- /dev/null +++ b/libc/arch-arm/syscalls/munlock.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_munlock + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(munlock)
diff --git a/libc/arch-arm/syscalls/munlockall.S b/libc/arch-arm/syscalls/munlockall.S new file mode 100644 index 0000000..b45a5a2 --- /dev/null +++ b/libc/arch-arm/syscalls/munlockall.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_munlockall + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(munlockall)
diff --git a/libc/arch-arm/syscalls/munmap.S b/libc/arch-arm/syscalls/munmap.S new file mode 100644 index 0000000..2b7a121 --- /dev/null +++ b/libc/arch-arm/syscalls/munmap.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_munmap + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(munmap)
diff --git a/libc/arch-arm/syscalls/nanosleep.S b/libc/arch-arm/syscalls/nanosleep.S new file mode 100644 index 0000000..83fd323 --- /dev/null +++ b/libc/arch-arm/syscalls/nanosleep.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_nanosleep + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(nanosleep)
diff --git a/libc/arch-arm/syscalls/personality.S b/libc/arch-arm/syscalls/personality.S new file mode 100644 index 0000000..5ad6132 --- /dev/null +++ b/libc/arch-arm/syscalls/personality.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_personality + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(personality)
diff --git a/libc/arch-arm/syscalls/pipe2.S b/libc/arch-arm/syscalls/pipe2.S new file mode 100644 index 0000000..f543f9d --- /dev/null +++ b/libc/arch-arm/syscalls/pipe2.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_pipe2 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(pipe2)
diff --git a/libc/arch-arm/syscalls/prctl.S b/libc/arch-arm/syscalls/prctl.S new file mode 100644 index 0000000..a2d869c --- /dev/null +++ b/libc/arch-arm/syscalls/prctl.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_prctl + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(prctl)
diff --git a/libc/arch-arm/syscalls/pread64.S b/libc/arch-arm/syscalls/pread64.S new file mode 100644 index 0000000..dc07bb3 --- /dev/null +++ b/libc/arch-arm/syscalls/pread64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_pread64 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(pread64)
diff --git a/libc/arch-arm/syscalls/prlimit64.S b/libc/arch-arm/syscalls/prlimit64.S new file mode 100644 index 0000000..0f04aaa --- /dev/null +++ b/libc/arch-arm/syscalls/prlimit64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_prlimit64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(prlimit64)
diff --git a/libc/arch-arm/syscalls/process_vm_readv.S b/libc/arch-arm/syscalls/process_vm_readv.S new file mode 100644 index 0000000..48c49dc --- /dev/null +++ b/libc/arch-arm/syscalls/process_vm_readv.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_readv) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_process_vm_readv + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(process_vm_readv)
diff --git a/libc/arch-arm/syscalls/process_vm_writev.S b/libc/arch-arm/syscalls/process_vm_writev.S new file mode 100644 index 0000000..4c21c43 --- /dev/null +++ b/libc/arch-arm/syscalls/process_vm_writev.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_writev) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_process_vm_writev + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(process_vm_writev)
diff --git a/libc/arch-arm/syscalls/pwrite64.S b/libc/arch-arm/syscalls/pwrite64.S new file mode 100644 index 0000000..5749f6b --- /dev/null +++ b/libc/arch-arm/syscalls/pwrite64.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_pwrite64 + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(pwrite64)
diff --git a/libc/arch-arm/syscalls/quotactl.S b/libc/arch-arm/syscalls/quotactl.S new file mode 100644 index 0000000..fde17f4 --- /dev/null +++ b/libc/arch-arm/syscalls/quotactl.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(quotactl) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_quotactl + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(quotactl)
diff --git a/libc/arch-arm/syscalls/read.S b/libc/arch-arm/syscalls/read.S new file mode 100644 index 0000000..5051358 --- /dev/null +++ b/libc/arch-arm/syscalls/read.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_read + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(read)
diff --git a/libc/arch-arm/syscalls/readahead.S b/libc/arch-arm/syscalls/readahead.S new file mode 100644 index 0000000..6952b4e --- /dev/null +++ b/libc/arch-arm/syscalls/readahead.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_readahead + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(readahead)
diff --git a/libc/arch-arm/syscalls/readlinkat.S b/libc/arch-arm/syscalls/readlinkat.S new file mode 100644 index 0000000..36d46fa --- /dev/null +++ b/libc/arch-arm/syscalls/readlinkat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_readlinkat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(readlinkat)
diff --git a/libc/arch-arm/syscalls/readv.S b/libc/arch-arm/syscalls/readv.S new file mode 100644 index 0000000..565af6a --- /dev/null +++ b/libc/arch-arm/syscalls/readv.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_readv + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(readv)
diff --git a/libc/arch-arm/syscalls/recvfrom.S b/libc/arch-arm/syscalls/recvfrom.S new file mode 100644 index 0000000..115a09c --- /dev/null +++ b/libc/arch-arm/syscalls/recvfrom.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_recvfrom + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(recvfrom)
diff --git a/libc/arch-arm/syscalls/recvmmsg.S b/libc/arch-arm/syscalls/recvmmsg.S new file mode 100644 index 0000000..6cf2b92 --- /dev/null +++ b/libc/arch-arm/syscalls/recvmmsg.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_recvmmsg + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(recvmmsg)
diff --git a/libc/arch-arm/syscalls/recvmsg.S b/libc/arch-arm/syscalls/recvmsg.S new file mode 100644 index 0000000..19a9fca --- /dev/null +++ b/libc/arch-arm/syscalls/recvmsg.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_recvmsg + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(recvmsg)
diff --git a/libc/arch-arm/syscalls/removexattr.S b/libc/arch-arm/syscalls/removexattr.S new file mode 100644 index 0000000..46f847d --- /dev/null +++ b/libc/arch-arm/syscalls/removexattr.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_removexattr + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(removexattr)
diff --git a/libc/arch-arm/syscalls/renameat.S b/libc/arch-arm/syscalls/renameat.S new file mode 100644 index 0000000..89fc513 --- /dev/null +++ b/libc/arch-arm/syscalls/renameat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_renameat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(renameat)
diff --git a/libc/arch-arm/syscalls/sched_get_priority_max.S b/libc/arch-arm/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..23b1d62 --- /dev/null +++ b/libc/arch-arm/syscalls/sched_get_priority_max.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_get_priority_max + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_get_priority_max)
diff --git a/libc/arch-arm/syscalls/sched_get_priority_min.S b/libc/arch-arm/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..65a967c --- /dev/null +++ b/libc/arch-arm/syscalls/sched_get_priority_min.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_get_priority_min + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_get_priority_min)
diff --git a/libc/arch-arm/syscalls/sched_getparam.S b/libc/arch-arm/syscalls/sched_getparam.S new file mode 100644 index 0000000..700041e --- /dev/null +++ b/libc/arch-arm/syscalls/sched_getparam.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_getparam + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_getparam)
diff --git a/libc/arch-arm/syscalls/sched_getscheduler.S b/libc/arch-arm/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..b4f5d13 --- /dev/null +++ b/libc/arch-arm/syscalls/sched_getscheduler.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_getscheduler + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_getscheduler)
diff --git a/libc/arch-arm/syscalls/sched_rr_get_interval.S b/libc/arch-arm/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..ea30b62 --- /dev/null +++ b/libc/arch-arm/syscalls/sched_rr_get_interval.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_rr_get_interval + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_rr_get_interval)
diff --git a/libc/arch-arm/syscalls/sched_setaffinity.S b/libc/arch-arm/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..636845b --- /dev/null +++ b/libc/arch-arm/syscalls/sched_setaffinity.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_setaffinity + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_setaffinity)
diff --git a/libc/arch-arm/syscalls/sched_setparam.S b/libc/arch-arm/syscalls/sched_setparam.S new file mode 100644 index 0000000..f24b96e --- /dev/null +++ b/libc/arch-arm/syscalls/sched_setparam.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_setparam + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_setparam)
diff --git a/libc/arch-arm/syscalls/sched_setscheduler.S b/libc/arch-arm/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..5bfa202 --- /dev/null +++ b/libc/arch-arm/syscalls/sched_setscheduler.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_setscheduler + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_setscheduler)
diff --git a/libc/arch-arm/syscalls/sched_yield.S b/libc/arch-arm/syscalls/sched_yield.S new file mode 100644 index 0000000..7b93a6e --- /dev/null +++ b/libc/arch-arm/syscalls/sched_yield.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sched_yield + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sched_yield)
diff --git a/libc/arch-arm/syscalls/sendfile.S b/libc/arch-arm/syscalls/sendfile.S new file mode 100644 index 0000000..52e78d0 --- /dev/null +++ b/libc/arch-arm/syscalls/sendfile.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sendfile + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sendfile)
diff --git a/libc/arch-arm/syscalls/sendfile64.S b/libc/arch-arm/syscalls/sendfile64.S new file mode 100644 index 0000000..416e9d2 --- /dev/null +++ b/libc/arch-arm/syscalls/sendfile64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sendfile64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sendfile64)
diff --git a/libc/arch-arm/syscalls/sendmmsg.S b/libc/arch-arm/syscalls/sendmmsg.S new file mode 100644 index 0000000..f97d264 --- /dev/null +++ b/libc/arch-arm/syscalls/sendmmsg.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sendmmsg + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sendmmsg)
diff --git a/libc/arch-arm/syscalls/sendmsg.S b/libc/arch-arm/syscalls/sendmsg.S new file mode 100644 index 0000000..215219a --- /dev/null +++ b/libc/arch-arm/syscalls/sendmsg.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sendmsg + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sendmsg)
diff --git a/libc/arch-arm/syscalls/sendto.S b/libc/arch-arm/syscalls/sendto.S new file mode 100644 index 0000000..29b7b0b --- /dev/null +++ b/libc/arch-arm/syscalls/sendto.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_sendto + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sendto)
diff --git a/libc/arch-arm/syscalls/setdomainname.S b/libc/arch-arm/syscalls/setdomainname.S new file mode 100644 index 0000000..4014a48 --- /dev/null +++ b/libc/arch-arm/syscalls/setdomainname.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setdomainname) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setdomainname + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setdomainname)
diff --git a/libc/arch-arm/syscalls/setfsgid.S b/libc/arch-arm/syscalls/setfsgid.S new file mode 100644 index 0000000..2f0f08c --- /dev/null +++ b/libc/arch-arm/syscalls/setfsgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setfsgid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setfsgid)
diff --git a/libc/arch-arm/syscalls/setfsuid.S b/libc/arch-arm/syscalls/setfsuid.S new file mode 100644 index 0000000..ce663e0 --- /dev/null +++ b/libc/arch-arm/syscalls/setfsuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setfsuid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setfsuid)
diff --git a/libc/arch-arm/syscalls/setgid.S b/libc/arch-arm/syscalls/setgid.S new file mode 100644 index 0000000..6f1cbed --- /dev/null +++ b/libc/arch-arm/syscalls/setgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setgid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setgid)
diff --git a/libc/arch-arm/syscalls/setgroups.S b/libc/arch-arm/syscalls/setgroups.S new file mode 100644 index 0000000..1fb494c --- /dev/null +++ b/libc/arch-arm/syscalls/setgroups.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setgroups32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setgroups)
diff --git a/libc/arch-arm/syscalls/sethostname.S b/libc/arch-arm/syscalls/sethostname.S new file mode 100644 index 0000000..c4c2db5 --- /dev/null +++ b/libc/arch-arm/syscalls/sethostname.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sethostname) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sethostname + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sethostname)
diff --git a/libc/arch-arm/syscalls/setitimer.S b/libc/arch-arm/syscalls/setitimer.S new file mode 100644 index 0000000..511a5d1 --- /dev/null +++ b/libc/arch-arm/syscalls/setitimer.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setitimer + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setitimer)
diff --git a/libc/arch-arm/syscalls/setns.S b/libc/arch-arm/syscalls/setns.S new file mode 100644 index 0000000..b1902dc --- /dev/null +++ b/libc/arch-arm/syscalls/setns.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setns + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setns)
diff --git a/libc/arch-arm/syscalls/setpgid.S b/libc/arch-arm/syscalls/setpgid.S new file mode 100644 index 0000000..fe05fc9 --- /dev/null +++ b/libc/arch-arm/syscalls/setpgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setpgid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setpgid)
diff --git a/libc/arch-arm/syscalls/setpriority.S b/libc/arch-arm/syscalls/setpriority.S new file mode 100644 index 0000000..960eee0 --- /dev/null +++ b/libc/arch-arm/syscalls/setpriority.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setpriority + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setpriority)
diff --git a/libc/arch-arm/syscalls/setregid.S b/libc/arch-arm/syscalls/setregid.S new file mode 100644 index 0000000..0b5f444 --- /dev/null +++ b/libc/arch-arm/syscalls/setregid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setregid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setregid)
diff --git a/libc/arch-arm/syscalls/setresgid.S b/libc/arch-arm/syscalls/setresgid.S new file mode 100644 index 0000000..64677d3 --- /dev/null +++ b/libc/arch-arm/syscalls/setresgid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setresgid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setresgid)
diff --git a/libc/arch-arm/syscalls/setresuid.S b/libc/arch-arm/syscalls/setresuid.S new file mode 100644 index 0000000..e3888f6 --- /dev/null +++ b/libc/arch-arm/syscalls/setresuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setresuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setresuid)
diff --git a/libc/arch-arm/syscalls/setreuid.S b/libc/arch-arm/syscalls/setreuid.S new file mode 100644 index 0000000..15c2665 --- /dev/null +++ b/libc/arch-arm/syscalls/setreuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setreuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setreuid)
diff --git a/libc/arch-arm/syscalls/setrlimit.S b/libc/arch-arm/syscalls/setrlimit.S new file mode 100644 index 0000000..b9014eb --- /dev/null +++ b/libc/arch-arm/syscalls/setrlimit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setrlimit + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setrlimit)
diff --git a/libc/arch-arm/syscalls/setsid.S b/libc/arch-arm/syscalls/setsid.S new file mode 100644 index 0000000..fb71474 --- /dev/null +++ b/libc/arch-arm/syscalls/setsid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setsid + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setsid)
diff --git a/libc/arch-arm/syscalls/setsockopt.S b/libc/arch-arm/syscalls/setsockopt.S new file mode 100644 index 0000000..8ea3893 --- /dev/null +++ b/libc/arch-arm/syscalls/setsockopt.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_setsockopt + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setsockopt)
diff --git a/libc/arch-arm/syscalls/settimeofday.S b/libc/arch-arm/syscalls/settimeofday.S new file mode 100644 index 0000000..00dfdeb --- /dev/null +++ b/libc/arch-arm/syscalls/settimeofday.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_settimeofday + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(settimeofday)
diff --git a/libc/arch-arm/syscalls/setuid.S b/libc/arch-arm/syscalls/setuid.S new file mode 100644 index 0000000..447ed1b --- /dev/null +++ b/libc/arch-arm/syscalls/setuid.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_setuid32 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setuid)
diff --git a/libc/arch-arm/syscalls/setxattr.S b/libc/arch-arm/syscalls/setxattr.S new file mode 100644 index 0000000..8ba4b77 --- /dev/null +++ b/libc/arch-arm/syscalls/setxattr.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_setxattr + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(setxattr)
diff --git a/libc/arch-arm/syscalls/shutdown.S b/libc/arch-arm/syscalls/shutdown.S new file mode 100644 index 0000000..51ed0cf --- /dev/null +++ b/libc/arch-arm/syscalls/shutdown.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_shutdown + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(shutdown)
diff --git a/libc/arch-arm/syscalls/sigaltstack.S b/libc/arch-arm/syscalls/sigaltstack.S new file mode 100644 index 0000000..2f97800 --- /dev/null +++ b/libc/arch-arm/syscalls/sigaltstack.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sigaltstack + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sigaltstack)
diff --git a/libc/arch-arm/syscalls/socketpair.S b/libc/arch-arm/syscalls/socketpair.S new file mode 100644 index 0000000..e537235 --- /dev/null +++ b/libc/arch-arm/syscalls/socketpair.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_socketpair + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(socketpair)
diff --git a/libc/arch-arm/syscalls/splice.S b/libc/arch-arm/syscalls/splice.S new file mode 100644 index 0000000..6bc3f0d --- /dev/null +++ b/libc/arch-arm/syscalls/splice.S
@@ -0,0 +1,22 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + mov ip, sp + stmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 16 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + ldmfd ip, {r4, r5, r6} + ldr r7, =__NR_splice + swi #0 + ldmfd sp!, {r4, r5, r6, r7} + .cfi_def_cfa_offset 0 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(splice)
diff --git a/libc/arch-arm/syscalls/swapoff.S b/libc/arch-arm/syscalls/swapoff.S new file mode 100644 index 0000000..25832ef --- /dev/null +++ b/libc/arch-arm/syscalls/swapoff.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_swapoff + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(swapoff)
diff --git a/libc/arch-arm/syscalls/swapon.S b/libc/arch-arm/syscalls/swapon.S new file mode 100644 index 0000000..df4c71e --- /dev/null +++ b/libc/arch-arm/syscalls/swapon.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_swapon + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(swapon)
diff --git a/libc/arch-arm/syscalls/symlinkat.S b/libc/arch-arm/syscalls/symlinkat.S new file mode 100644 index 0000000..ec2ee4f --- /dev/null +++ b/libc/arch-arm/syscalls/symlinkat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_symlinkat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(symlinkat)
diff --git a/libc/arch-arm/syscalls/sync.S b/libc/arch-arm/syscalls/sync.S new file mode 100644 index 0000000..b73dcaa --- /dev/null +++ b/libc/arch-arm/syscalls/sync.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sync) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sync + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sync)
diff --git a/libc/arch-arm/syscalls/sysinfo.S b/libc/arch-arm/syscalls/sysinfo.S new file mode 100644 index 0000000..1584ea4 --- /dev/null +++ b/libc/arch-arm/syscalls/sysinfo.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sysinfo) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_sysinfo + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(sysinfo)
diff --git a/libc/arch-arm/syscalls/tee.S b/libc/arch-arm/syscalls/tee.S new file mode 100644 index 0000000..efd12ca --- /dev/null +++ b/libc/arch-arm/syscalls/tee.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tee) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_tee + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(tee)
diff --git a/libc/arch-arm/syscalls/tgkill.S b/libc/arch-arm/syscalls/tgkill.S new file mode 100644 index 0000000..43fe62c --- /dev/null +++ b/libc/arch-arm/syscalls/tgkill.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tgkill) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_tgkill + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(tgkill)
diff --git a/libc/arch-arm/syscalls/timerfd_create.S b/libc/arch-arm/syscalls/timerfd_create.S new file mode 100644 index 0000000..4aa3107 --- /dev/null +++ b/libc/arch-arm/syscalls/timerfd_create.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_create) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timerfd_create + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(timerfd_create)
diff --git a/libc/arch-arm/syscalls/timerfd_gettime.S b/libc/arch-arm/syscalls/timerfd_gettime.S new file mode 100644 index 0000000..6ae93e4 --- /dev/null +++ b/libc/arch-arm/syscalls/timerfd_gettime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_gettime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timerfd_gettime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(timerfd_gettime)
diff --git a/libc/arch-arm/syscalls/timerfd_settime.S b/libc/arch-arm/syscalls/timerfd_settime.S new file mode 100644 index 0000000..2dd4aac --- /dev/null +++ b/libc/arch-arm/syscalls/timerfd_settime.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_settime) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_timerfd_settime + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(timerfd_settime)
diff --git a/libc/arch-arm/syscalls/times.S b/libc/arch-arm/syscalls/times.S new file mode 100644 index 0000000..1ff636d --- /dev/null +++ b/libc/arch-arm/syscalls/times.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(times) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_times + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(times)
diff --git a/libc/arch-arm/syscalls/truncate.S b/libc/arch-arm/syscalls/truncate.S new file mode 100644 index 0000000..0bee4d2 --- /dev/null +++ b/libc/arch-arm/syscalls/truncate.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_truncate + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(truncate)
diff --git a/libc/arch-arm/syscalls/truncate64.S b/libc/arch-arm/syscalls/truncate64.S new file mode 100644 index 0000000..74e9eb2 --- /dev/null +++ b/libc/arch-arm/syscalls/truncate64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate64) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_truncate64 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(truncate64)
diff --git a/libc/arch-arm/syscalls/umask.S b/libc/arch-arm/syscalls/umask.S new file mode 100644 index 0000000..ca3e058 --- /dev/null +++ b/libc/arch-arm/syscalls/umask.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umask) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_umask + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(umask)
diff --git a/libc/arch-arm/syscalls/umount2.S b/libc/arch-arm/syscalls/umount2.S new file mode 100644 index 0000000..6e1ba32 --- /dev/null +++ b/libc/arch-arm/syscalls/umount2.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umount2) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_umount2 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(umount2)
diff --git a/libc/arch-arm/syscalls/uname.S b/libc/arch-arm/syscalls/uname.S new file mode 100644 index 0000000..4f2b8a2 --- /dev/null +++ b/libc/arch-arm/syscalls/uname.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(uname) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_uname + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(uname)
diff --git a/libc/arch-arm/syscalls/unlinkat.S b/libc/arch-arm/syscalls/unlinkat.S new file mode 100644 index 0000000..ac7bfae --- /dev/null +++ b/libc/arch-arm/syscalls/unlinkat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unlinkat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_unlinkat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(unlinkat)
diff --git a/libc/arch-arm/syscalls/unshare.S b/libc/arch-arm/syscalls/unshare.S new file mode 100644 index 0000000..4558a60 --- /dev/null +++ b/libc/arch-arm/syscalls/unshare.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unshare) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_unshare + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(unshare)
diff --git a/libc/arch-arm/syscalls/utimensat.S b/libc/arch-arm/syscalls/utimensat.S new file mode 100644 index 0000000..9524507 --- /dev/null +++ b/libc/arch-arm/syscalls/utimensat.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(utimensat) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_utimensat + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(utimensat)
diff --git a/libc/arch-arm/syscalls/vmsplice.S b/libc/arch-arm/syscalls/vmsplice.S new file mode 100644 index 0000000..90ab8b4 --- /dev/null +++ b/libc/arch-arm/syscalls/vmsplice.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(vmsplice) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_vmsplice + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(vmsplice)
diff --git a/libc/arch-arm/syscalls/wait4.S b/libc/arch-arm/syscalls/wait4.S new file mode 100644 index 0000000..40bb5a5 --- /dev/null +++ b/libc/arch-arm/syscalls/wait4.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(wait4) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_wait4 + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(wait4)
diff --git a/libc/arch-arm/syscalls/write.S b/libc/arch-arm/syscalls/write.S new file mode 100644 index 0000000..4abbe6b --- /dev/null +++ b/libc/arch-arm/syscalls/write.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(write) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_write + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(write)
diff --git a/libc/arch-arm/syscalls/writev.S b/libc/arch-arm/syscalls/writev.S new file mode 100644 index 0000000..3103237 --- /dev/null +++ b/libc/arch-arm/syscalls/writev.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(writev) + mov ip, r7 + .cfi_register r7, ip + ldr r7, =__NR_writev + swi #0 + mov r7, ip + .cfi_restore r7 + cmn r0, #(MAX_ERRNO + 1) + bxls lr + neg r0, r0 + b __set_errno_internal +END(writev)
diff --git a/libc/arch-arm64/bionic/__bionic_clone.S b/libc/arch-arm64/bionic/__bionic_clone.S new file mode 100644 index 0000000..27e44e7 --- /dev/null +++ b/libc/arch-arm64/bionic/__bionic_clone.S
@@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); + +ENTRY(__bionic_clone) + # Push 'fn' and 'arg' onto the child stack. + stp x5, x6, [x1, #-16]! + + # Make the system call. + mov x8, __NR_clone + svc #0 + + # Are we the child? + cbz x0, .L_bc_child + + # Set errno if something went wrong. + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret + +.L_bc_child: + # We're in the child now. Set the end of the frame record chain. + mov x29, #0 + # Setting x30 to 0 will make the unwinder stop at __start_thread. + mov x30, #0 + # Call __start_thread with the 'fn' and 'arg' we stored on the child stack. + ldp x0, x1, [sp], #16 + b __start_thread +END(__bionic_clone) +.hidden __bionic_clone
diff --git a/libc/arch-arm64/bionic/__set_tls.c b/libc/arch-arm64/bionic/__set_tls.c new file mode 100644 index 0000000..0d88d11 --- /dev/null +++ b/libc/arch-arm64/bionic/__set_tls.c
@@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> + +__LIBC_HIDDEN__ void __set_tls(void* tls) { + asm("msr tpidr_el0, %0" : : "r" (tls)); +}
diff --git a/libc/arch-arm64/bionic/_exit_with_stack_teardown.S b/libc/arch-arm64/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..6a7b1e5 --- /dev/null +++ b/libc/arch-arm64/bionic/_exit_with_stack_teardown.S
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + mov w8, __NR_munmap + svc #0 + // If munmap failed, we ignore the failure and exit anyway. + + mov x0, #0 + mov w8, __NR_exit + svc #0 + // The exit syscall does not return. +END(_exit_with_stack_teardown)
diff --git a/libc/arch-arm64/bionic/crtbegin.c b/libc/arch-arm64/bionic/crtbegin.c new file mode 100644 index 0000000..7e2c5d7 --- /dev/null +++ b/libc/arch-arm64/bionic/crtbegin.c
@@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "../../bionic/libc_init_common.h" +#include <stddef.h> +#include <stdint.h> + +__attribute__ ((section (".preinit_array"))) +void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".init_array"))) +void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".fini_array"))) +void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1; + + +__LIBC_HIDDEN__ void do_arm64_start(void* raw_args) { + structors_array_t array; + array.preinit_array = &__PREINIT_ARRAY__; + array.init_array = &__INIT_ARRAY__; + array.fini_array = &__FINI_ARRAY__; + __libc_init(raw_args, NULL, &main, &array); +} + +/* + * Put the value of sp in x0 and call do_arm64_init(). The latter will then + * then be able to access the stack as prepared by the kernel's execve system + * call (via the first argument). + */ +__asm__ ( +" .text \n" +" .align 2 \n" +" .global _start \n" +" .hidden _start \n" +" .type _start, %function \n" +"_start: \n" +" add x0, sp, xzr \n" +" b do_arm64_start \n" +" .size _start, .-_start \n" +); + +#include "../../arch-common/bionic/__dso_handle.h" +#include "../../arch-common/bionic/atexit.h" +#include "../../arch-common/bionic/pthread_atfork.h"
diff --git a/libc/arch-arm64/bionic/setjmp.S b/libc/arch-arm64/bionic/setjmp.S new file mode 100644 index 0000000..2550134 --- /dev/null +++ b/libc/arch-arm64/bionic/setjmp.S
@@ -0,0 +1,259 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// According to AARCH64 PCS document we need to save the following +// registers: +// +// Core x19 - x30, sp (see section 5.1.1) +// VFP d8 - d15 (see section 5.1.2) +// +// NOTE: All the registers saved here will have 64 bit vales. +// AAPCS mandates that the higher part of q registers do not need to +// be saved by the callee. +// +// The internal structure of a jmp_buf is totally private. +// Current layout (changes from release to release): +// +// word name description +// 0 sigflag/cookie setjmp cookie in top 31 bits, signal mask flag in low bit +// 1 sigmask signal mask (not used with _setjmp / _longjmp) +// 2 core_base base of core registers (x19-x30, sp) +// 15 float_base base of float registers (d8-d15) +// 23 checksum checksum of core registers +// 24 reserved reserved entries (room to grow) +// 32 + +#define _JB_SIGFLAG 0 +#define _JB_SIGMASK (_JB_SIGFLAG + 1) +#define _JB_X30_SP (_JB_SIGMASK + 1) +#define _JB_X28_X29 (_JB_X30_SP + 2) +#define _JB_X26_X27 (_JB_X28_X29 + 2) +#define _JB_X24_X25 (_JB_X26_X27 + 2) +#define _JB_X22_X23 (_JB_X24_X25 + 2) +#define _JB_X20_X21 (_JB_X22_X23 + 2) +#define _JB_X19 (_JB_X20_X21 + 2) +#define _JB_D14_D15 (_JB_X19 + 1) +#define _JB_D12_D13 (_JB_D14_D15 + 2) +#define _JB_D10_D11 (_JB_D12_D13 + 2) +#define _JB_D8_D9 (_JB_D10_D11 + 2) +#define _JB_CHECKSUM (_JB_D8_D9 + 2) + +#define MANGLE_REGISTERS 1 +#define USE_CHECKSUM 1 + +.macro m_mangle_registers reg, sp_reg +#if MANGLE_REGISTERS + eor x19, x19, \reg + eor x20, x20, \reg + eor x21, x21, \reg + eor x22, x22, \reg + eor x23, x23, \reg + eor x24, x24, \reg + eor x25, x25, \reg + eor x26, x26, \reg + eor x27, x27, \reg + eor x28, x28, \reg + eor x29, x29, \reg + eor x30, x30, \reg + eor \sp_reg, \sp_reg, \reg +#endif +.endm + +.macro m_calculate_checksum dst, src, scratch + mov \dst, #0 + .irp i,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22 + ldr \scratch, [\src, #(\i * 8)] + eor \dst, \dst, \scratch + .endr +.endm + +.macro m_unmangle_registers reg, sp_reg + m_mangle_registers \reg, sp_reg=\sp_reg +.endm + +ENTRY(setjmp) + mov w1, #1 + b sigsetjmp +END(setjmp) + +ENTRY(_setjmp) + mov w1, #0 + b sigsetjmp +END(_setjmp) + +// int sigsetjmp(sigjmp_buf env, int save_signal_mask); +ENTRY(sigsetjmp) + stp x0, x30, [sp, #-16]! + .cfi_def_cfa_offset 16 + .cfi_rel_offset x0, 0 + .cfi_rel_offset x30, 8 + + // Get the cookie and store it along with the signal flag. + mov x0, x1 + bl __bionic_setjmp_cookie_get + mov x1, x0 + ldr x0, [sp, #0] + str x1, [x0, #(_JB_SIGFLAG * 8)] + + // Do we need to save the signal mask? + tbz w1, #0, 1f + + // Save the cookie for later. + stp x1, xzr, [sp, #-16]! + .cfi_adjust_cfa_offset 16 + + // Save current signal mask. + // The 'how' argument is ignored if new_mask is NULL. + mov x1, #0 // NULL. + add x2, x0, #(_JB_SIGMASK * 8) // old_mask. + bl sigprocmask + + ldp x1, xzr, [sp], #16 + .cfi_adjust_cfa_offset -16 + +1: + // Restore original x0 and lr. + ldp x0, x30, [sp], #16 + .cfi_adjust_cfa_offset -16 + .cfi_restore x0 + .cfi_restore x30 + + // Mask off the signal flag bit. + bic x1, x1, #1 + + // Save core registers. + mov x10, sp + m_mangle_registers x1, sp_reg=x10 + stp x30, x10, [x0, #(_JB_X30_SP * 8)] + stp x28, x29, [x0, #(_JB_X28_X29 * 8)] + stp x26, x27, [x0, #(_JB_X26_X27 * 8)] + stp x24, x25, [x0, #(_JB_X24_X25 * 8)] + stp x22, x23, [x0, #(_JB_X22_X23 * 8)] + stp x20, x21, [x0, #(_JB_X20_X21 * 8)] + str x19, [x0, #(_JB_X19 * 8)] + m_unmangle_registers x1, sp_reg=x10 + + // Save floating point registers. + stp d14, d15, [x0, #(_JB_D14_D15 * 8)] + stp d12, d13, [x0, #(_JB_D12_D13 * 8)] + stp d10, d11, [x0, #(_JB_D10_D11 * 8)] + stp d8, d9, [x0, #(_JB_D8_D9 * 8)] + +#if USE_CHECKSUM + // Calculate the checksum. + m_calculate_checksum x12, x0, x2 + str x12, [x0, #(_JB_CHECKSUM * 8)] +#endif + + mov w0, #0 + ret +END(sigsetjmp) + +// void siglongjmp(sigjmp_buf env, int value); +ENTRY(siglongjmp) +#if USE_CHECKSUM + // Check the checksum before doing anything. + m_calculate_checksum x12, x0, x2 + ldr x2, [x0, #(_JB_CHECKSUM * 8)] + + cmp x2, x12 + bne __bionic_setjmp_checksum_mismatch +#endif + + // Do we need to restore the signal mask? + ldr x2, [x0, #(_JB_SIGFLAG * 8)] + tbz w2, #0, 1f + + stp x0, x30, [sp, #-16]! + .cfi_adjust_cfa_offset 16 + .cfi_rel_offset x0, 0 + .cfi_rel_offset x30, 8 + + // Restore signal mask. + mov x19, x1 // Save 'value'. + + mov x2, x0 + mov x0, #2 // SIG_SETMASK + add x1, x2, #(_JB_SIGMASK * 8) // new_mask. + mov x2, #0 // NULL. + bl sigprocmask + mov x1, x19 // Restore 'value'. + + // Restore original x0 and lr. + ldp x0, x30, [sp], #16 + .cfi_adjust_cfa_offset -16 + .cfi_restore x0 + .cfi_restore x30 + + ldr x2, [x0, #(_JB_SIGFLAG * 8)] +1: + // Restore core registers. + bic x2, x2, #1 + ldp x30, x10, [x0, #(_JB_X30_SP * 8)] + ldp x28, x29, [x0, #(_JB_X28_X29 * 8)] + ldp x26, x27, [x0, #(_JB_X26_X27 * 8)] + ldp x24, x25, [x0, #(_JB_X24_X25 * 8)] + ldp x22, x23, [x0, #(_JB_X22_X23 * 8)] + ldp x20, x21, [x0, #(_JB_X20_X21 * 8)] + ldr x19, [x0, #(_JB_X19 * 8)] + m_unmangle_registers x2, sp_reg=x10 + mov sp, x10 + + stp x0, x1, [sp, #-16]! + .cfi_adjust_cfa_offset 16 + .cfi_rel_offset x0, 0 + .cfi_rel_offset x1, 8 + stp x30, xzr, [sp, #-16]! + .cfi_adjust_cfa_offset 16 + .cfi_rel_offset x30, 0 + ldr x0, [x0, #(_JB_SIGFLAG * 8)] + bl __bionic_setjmp_cookie_check + ldp x30, xzr, [sp], #16 + .cfi_adjust_cfa_offset -16 + .cfi_restore x30 + ldp x0, x1, [sp], #16 + .cfi_adjust_cfa_offset -16 + .cfi_restore x0 + .cfi_restore x1 + + // Restore floating point registers. + ldp d14, d15, [x0, #(_JB_D14_D15 * 8)] + ldp d12, d13, [x0, #(_JB_D12_D13 * 8)] + ldp d10, d11, [x0, #(_JB_D10_D11 * 8)] + ldp d8, d9, [x0, #(_JB_D8_D9 * 8)] + + // Set return value. + cmp w1, wzr + csinc w0, w1, wzr, ne + ret +END(siglongjmp) + +ALIAS_SYMBOL(longjmp, siglongjmp) +ALIAS_SYMBOL(_longjmp, siglongjmp)
diff --git a/libc/arch-arm64/bionic/syscall.S b/libc/arch-arm64/bionic/syscall.S new file mode 100644 index 0000000..8389f98 --- /dev/null +++ b/libc/arch-arm64/bionic/syscall.S
@@ -0,0 +1,49 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +ENTRY(syscall) + /* Move syscall No. from x0 to x8 */ + mov x8, x0 + /* Move syscall parameters from x1 thru x6 to x0 thru x5 */ + mov x0, x1 + mov x1, x2 + mov x2, x3 + mov x3, x4 + mov x4, x5 + mov x5, x6 + svc #0 + + /* check if syscall returned successfully */ + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(syscall)
diff --git a/libc/arch-arm64/bionic/vfork.S b/libc/arch-arm64/bionic/vfork.S new file mode 100644 index 0000000..92fa333 --- /dev/null +++ b/libc/arch-arm64/bionic/vfork.S
@@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <asm/signal.h> +#include <linux/sched.h> + +ENTRY(vfork) + // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0 + mrs x0, tpidr_el0 + ldr x0, [x0, #8] + str wzr, [x0, #20] + + mov x0, #(CLONE_VM | CLONE_VFORK | SIGCHLD) + mov x1, xzr + mov x2, xzr + mov x3, xzr + mov x4, xzr + + mov x8, __NR_clone + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(vfork)
diff --git a/libc/arch-arm64/denver64/bionic/memcpy.S b/libc/arch-arm64/denver64/bionic/memcpy.S new file mode 100644 index 0000000..0be2aac --- /dev/null +++ b/libc/arch-arm64/denver64/bionic/memcpy.S
@@ -0,0 +1,48 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Prototype: void *memcpy (void *dst, const void *src, size_t count). + +#include <private/bionic_asm.h> + +ENTRY(__memcpy_chk) + cmp x2, x3 + bls memcpy + + // Preserve for accurate backtrace. + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_rel_offset x29, 0 + .cfi_rel_offset x30, 8 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + #include "memcpy_base.S" +END(memcpy)
diff --git a/libc/arch-arm64/denver64/bionic/memcpy_base.S b/libc/arch-arm64/denver64/bionic/memcpy_base.S new file mode 100644 index 0000000..3d7e9dd --- /dev/null +++ b/libc/arch-arm64/denver64/bionic/memcpy_base.S
@@ -0,0 +1,199 @@ +/* Copyright (c) 2012, Linaro Limited + All rights reserved. + Copyright (c) 2014, NVIDIA Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * denver, ARMv8-a, AArch64 + * Unaligned accesses + * + */ + +#define dstin x0 +#define src x1 +#define count x2 +#define tmp1 x3 +#define tmp1w w3 +#define tmp2 x4 +#define tmp2w w4 +#define tmp3 x5 +#define tmp3w w5 +#define dst x6 + +#define A_l x7 +#define A_h x8 +#define B_l x9 +#define B_h x10 +#define C_l x11 +#define C_h x12 +#define D_l x13 +#define D_h x14 + +#define QA_l q0 +#define QA_h q1 +#define QB_l q2 +#define QB_h q3 + + mov dst, dstin + cmp count, #64 + b.ge .Lcpy_not_short + cmp count, #15 + b.le .Ltail15tiny + + /* Deal with small copies quickly by dropping straight into the + * exit block. */ +.Ltail63: + /* Copy up to 48 bytes of data. At this point we only need the + * bottom 6 bits of count to be accurate. */ + ands tmp1, count, #0x30 + b.eq .Ltail15 + add dst, dst, tmp1 + add src, src, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + ldp A_l, A_h, [src, #-48] + stp A_l, A_h, [dst, #-48] +1: + ldp A_l, A_h, [src, #-32] + stp A_l, A_h, [dst, #-32] +2: + ldp A_l, A_h, [src, #-16] + stp A_l, A_h, [dst, #-16] + +.Ltail15: + ands count, count, #15 + beq 1f + add src, src, count + ldp A_l, A_h, [src, #-16] + add dst, dst, count + stp A_l, A_h, [dst, #-16] +1: + ret + +.Ltail15tiny: + /* Copy up to 15 bytes of data. Does not assume additional data + being copied. */ + tbz count, #3, 1f + ldr tmp1, [src], #8 + str tmp1, [dst], #8 +1: + tbz count, #2, 1f + ldr tmp1w, [src], #4 + str tmp1w, [dst], #4 +1: + tbz count, #1, 1f + ldrh tmp1w, [src], #2 + strh tmp1w, [dst], #2 +1: + tbz count, #0, 1f + ldrb tmp1w, [src] + strb tmp1w, [dst] +1: + ret + +.Lcpy_not_short: + /* We don't much care about the alignment of DST, but we want SRC + * to be 128-bit (16 byte) aligned so that we don't cross cache line + * boundaries on both loads and stores. */ + neg tmp2, src + ands tmp2, tmp2, #15 /* Bytes to reach alignment. */ + b.eq 2f + sub count, count, tmp2 + /* Copy more data than needed; it's faster than jumping + * around copying sub-Quadword quantities. We know that + * it can't overrun. */ + ldp A_l, A_h, [src] + add src, src, tmp2 + stp A_l, A_h, [dst] + add dst, dst, tmp2 + /* There may be less than 63 bytes to go now. */ + cmp count, #63 + b.le .Ltail63 +2: + subs count, count, #128 + b.ge .Lcpy_body_large + /* Less than 128 bytes to copy, so handle 64 here and then jump + * to the tail. */ + ldp QA_l, QA_h, [src] + ldp QB_l, QB_h, [src, #32] + stp QA_l, QA_h, [dst] + stp QB_l, QB_h, [dst, #32] + tst count, #0x3f + add src, src, #64 + add dst, dst, #64 + b.ne .Ltail63 + ret + + /* Critical loop. Start at a new cache line boundary. Assuming + * 64 bytes per line this ensures the entire loop is in one line. */ + .p2align 6 +.Lcpy_body_large: + cmp count, 65536 + bhi .Lcpy_body_huge + /* There are at least 128 bytes to copy. */ + ldp QA_l, QA_h, [src, #0] + sub dst, dst, #32 /* Pre-bias. */ + ldp QB_l, QB_h, [src, #32]! /* src += 64 - Pre-bias. */ +1: + stp QA_l, QA_h, [dst, #32] + ldp QA_l, QA_h, [src, #32] + stp QB_l, QB_h, [dst, #64]! + ldp QB_l, QB_h, [src, #64]! + + subs count, count, #64 + b.ge 1b + + stp QA_l, QA_h, [dst, #32] + stp QB_l, QB_h, [dst, #64] + add src, src, #32 + add dst, dst, #64 + 32 + tst count, #0x3f + b.ne .Ltail63 + ret +.Lcpy_body_huge: + /* There are at least 128 bytes to copy. */ + ldp QA_l, QA_h, [src, #0] + sub dst, dst, #32 /* Pre-bias. */ + ldp QB_l, QB_h, [src, #32]! +1: + stnp QA_l, QA_h, [dst, #32] + stnp QB_l, QB_h, [dst, #64] + ldp QA_l, QA_h, [src, #32] + ldp QB_l, QB_h, [src, #64]! + add dst, dst, #64 + + subs count, count, #64 + b.ge 1b + + stnp QA_l, QA_h, [dst, #32] + stnp QB_l, QB_h, [dst, #64] + add src, src, #32 + add dst, dst, #64 + 32 + tst count, #0x3f + b.ne .Ltail63 + ret
diff --git a/libc/arch-arm64/denver64/bionic/memset.S b/libc/arch-arm64/denver64/bionic/memset.S new file mode 100644 index 0000000..bea5b26 --- /dev/null +++ b/libc/arch-arm64/denver64/bionic/memset.S
@@ -0,0 +1,285 @@ +/* Copyright (c) 2012, Linaro Limited + All rights reserved. + Copyright (c) 2014, NVIDIA Corporation. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * denver, ARMv8-a, AArch64 + * Unaligned accesses + * + */ + +#include <private/bionic_asm.h> + +/* By default we assume that the DC instruction can be used to zero + data blocks more efficiently. In some circumstances this might be + unsafe, for example in an asymmetric multiprocessor environment with + different DC clear lengths (neither the upper nor lower lengths are + safe to use). The feature can be disabled by defining DONT_USE_DC. + + If code may be run in a virtualized environment, then define + MAYBE_VIRT. This will cause the code to cache the system register + values rather than re-reading them each call. */ + +#define dstin x0 +#define val w1 +#define count x2 +#define dst_count x3 /* for __memset_chk */ +#define tmp1 x3 +#define tmp1w w3 +#define tmp2 x4 +#define tmp2w w4 +#define zva_len_x x5 +#define zva_len w5 +#define zva_bits_x x6 + +#define A_l x7 +#define A_lw w7 +#define dst x8 +#define tmp3w w9 + +#define QA_l q0 + +ENTRY(__memset_chk) + cmp count, dst_count + bls memset + + // Preserve for accurate backtrace. + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_rel_offset x29, 0 + .cfi_rel_offset x30, 8 + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + + mov dst, dstin /* Preserve return value. */ + ands A_lw, val, #255 +#ifndef DONT_USE_DC +# b.eq .Lzero_mem +#endif + orr A_lw, A_lw, A_lw, lsl #8 + orr A_lw, A_lw, A_lw, lsl #16 + orr A_l, A_l, A_l, lsl #32 +.Ltail_maybe_long: + cmp count, #256 + b.ge .Lnot_short +.Ltail_maybe_tiny: + cmp count, #15 + b.le .Ltail15tiny +.Ltail255: + ands tmp1, count, #0xC0 + b.eq .Ltail63 + dup v0.4s, A_lw + cmp tmp1w, #0x80 + b.eq 1f + b.lt 2f + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 +1: + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 +2: + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 +.Ltail63: + ands tmp1, count, #0x30 + b.eq .Ltail15 + add dst, dst, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + stp A_l, A_l, [dst, #-48] +1: + stp A_l, A_l, [dst, #-32] +2: + stp A_l, A_l, [dst, #-16] + +.Ltail15: + and count, count, #15 + add dst, dst, count + stp A_l, A_l, [dst, #-16] /* Repeat some/all of last store. */ + ret + +.Ltail15tiny: + /* Set up to 15 bytes. Does not assume earlier memory + being set. */ + tbz count, #3, 1f + str A_l, [dst], #8 +1: + tbz count, #2, 1f + str A_lw, [dst], #4 +1: + tbz count, #1, 1f + strh A_lw, [dst], #2 +1: + tbz count, #0, 1f + strb A_lw, [dst] +1: + ret + + /* Critical loop. Start at a new cache line boundary. Assuming + * 64 bytes per line, this ensures the entire loop is in one line. */ + .p2align 6 +.Lnot_short: + dup v0.4s, A_lw + neg tmp2, dst + ands tmp2, tmp2, #15 + b.eq 2f + /* Bring DST to 128-bit (16-byte) alignment. We know that there's + * more than that to set, so we simply store 16 bytes and advance by + * the amount required to reach alignment. */ + sub count, count, tmp2 + stp A_l, A_l, [dst] + add dst, dst, tmp2 + /* There may be less than 63 bytes to go now. */ + cmp count, #255 + b.le .Ltail255 +2: + cmp count, #2097152 + b.gt 3f +1: + sub count, count, #256 +2: + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + stp QA_l, QA_l, [dst], #32 + subs count, count, #256 + b.ge 2b + tst count, #0xff + b.ne .Ltail255 + ret +3: + sub count, count, #64 +4: + subs count, count, #64 + stnp QA_l, QA_l, [dst] + stnp QA_l, QA_l, [dst, #32] + add dst, dst, #64 + b.ge 4b + tst count, #0x3f + b.ne .Ltail63 + ret + +#ifndef DONT_USE_DC + /* For zeroing memory, check to see if we can use the ZVA feature to + * zero entire 'cache' lines. */ +.Lzero_mem: + mov A_l, #0 + cmp count, #63 + b.le .Ltail_maybe_tiny + neg tmp2, dst + ands tmp2, tmp2, #15 + b.eq 1f + sub count, count, tmp2 + stp A_l, A_l, [dst] + add dst, dst, tmp2 + cmp count, #63 + b.le .Ltail63 +1: + /* For zeroing small amounts of memory, it's not worth setting up + * the line-clear code. */ + cmp count, #128 + b.lt .Lnot_short +#ifdef MAYBE_VIRT + /* For efficiency when virtualized, we cache the ZVA capability. */ + adrp tmp2, .Lcache_clear + ldr zva_len, [tmp2, #:lo12:.Lcache_clear] + tbnz zva_len, #31, .Lnot_short + cbnz zva_len, .Lzero_by_line + mrs tmp1, dczid_el0 + tbz tmp1, #4, 1f + /* ZVA not available. Remember this for next time. */ + mov zva_len, #~0 + str zva_len, [tmp2, #:lo12:.Lcache_clear] + b .Lnot_short +1: + mov tmp3w, #4 + and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ + lsl zva_len, tmp3w, zva_len + str zva_len, [tmp2, #:lo12:.Lcache_clear] +#else + mrs tmp1, dczid_el0 + tbnz tmp1, #4, .Lnot_short + mov tmp3w, #4 + and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ + lsl zva_len, tmp3w, zva_len +#endif + +.Lzero_by_line: + /* Compute how far we need to go to become suitably aligned. We're + * already at quad-word alignment. */ + cmp count, zva_len_x + b.lt .Lnot_short /* Not enough to reach alignment. */ + sub zva_bits_x, zva_len_x, #1 + neg tmp2, dst + ands tmp2, tmp2, zva_bits_x + b.eq 1f /* Already aligned. */ + /* Not aligned, check that there's enough to copy after alignment. */ + sub tmp1, count, tmp2 + cmp tmp1, #64 + ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */ + b.lt .Lnot_short + /* We know that there's at least 64 bytes to zero and that it's safe + * to overrun by 64 bytes. */ + mov count, tmp1 +2: + stp A_l, A_l, [dst] + stp A_l, A_l, [dst, #16] + stp A_l, A_l, [dst, #32] + subs tmp2, tmp2, #64 + stp A_l, A_l, [dst, #48] + add dst, dst, #64 + b.ge 2b + /* We've overrun a bit, so adjust dst downwards. */ + add dst, dst, tmp2 +1: + sub count, count, zva_len_x +3: + dc zva, dst + add dst, dst, zva_len_x + subs count, count, zva_len_x + b.ge 3b + ands count, count, zva_bits_x + b.ne .Ltail_maybe_long + ret +END(memset) + +#ifdef MAYBE_VIRT + .bss + .p2align 2 +.Lcache_clear: + .space 4 +#endif +#endif /* DONT_USE_DC */
diff --git a/libc/arch-arm64/generic/bionic/memchr.S b/libc/arch-arm64/generic/bionic/memchr.S new file mode 100644 index 0000000..a00dd8d --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memchr.S
@@ -0,0 +1,165 @@ +/* + * memchr - find a character in a memory zone + * + * Copyright (c) 2014, ARM Limited + * All rights Reserved. + * Copyright (c) 2014, Linaro Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the company nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Assumptions: + * + * ARMv8-a, AArch64 + * Neon Available. + */ + +#include <private/bionic_asm.h> + +/* Arguments and results. */ +#define srcin x0 +#define chrin w1 +#define cntin x2 + +#define result x0 + +#define src x3 +#define tmp x4 +#define wtmp2 w5 +#define synd x6 +#define soff x9 +#define cntrem x10 + +#define vrepchr v0 +#define vdata1 v1 +#define vdata2 v2 +#define vhas_chr1 v3 +#define vhas_chr2 v4 +#define vrepmask v5 +#define vend v6 + +/* + * Core algorithm: + * + * For each 32-byte chunk we calculate a 64-bit syndrome value, with two bits + * per byte. For each tuple, bit 0 is set if the relevant byte matched the + * requested character and bit 1 is not used (faster than using a 32bit + * syndrome). Since the bits in the syndrome reflect exactly the order in which + * things occur in the original string, counting trailing zeros allows to + * identify exactly which byte has matched. + */ + +ENTRY(memchr) + /* + * Magic constant 0x40100401 allows us to identify which lane matches + * the requested byte. + */ + cbz cntin, .Lzero_length + mov wtmp2, #0x0401 + movk wtmp2, #0x4010, lsl #16 + dup vrepchr.16b, chrin + /* Work with aligned 32-byte chunks */ + bic src, srcin, #31 + dup vrepmask.4s, wtmp2 + ands soff, srcin, #31 + and cntrem, cntin, #31 + b.eq .Lloop + + /* + * Input string is not 32-byte aligned. We calculate the syndrome + * value for the aligned 32 bytes block containing the first bytes + * and mask the irrelevant part. + */ + + ld1 {vdata1.16b, vdata2.16b}, [src], #32 + sub tmp, soff, #32 + adds cntin, cntin, tmp + cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b + cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b + and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b + and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b + addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */ + addp vend.16b, vend.16b, vend.16b /* 128->64 */ + mov synd, vend.d[0] + /* Clear the soff*2 lower bits */ + lsl tmp, soff, #1 + lsr synd, synd, tmp + lsl synd, synd, tmp + /* The first block can also be the last */ + b.ls .Lmasklast + /* Have we found something already? */ + cbnz synd, .Ltail + +.Lloop: + ld1 {vdata1.16b, vdata2.16b}, [src], #32 + subs cntin, cntin, #32 + cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b + cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b + /* If we're out of data we finish regardless of the result */ + b.ls .Lend + /* Use a fast check for the termination condition */ + orr vend.16b, vhas_chr1.16b, vhas_chr2.16b + addp vend.2d, vend.2d, vend.2d + mov synd, vend.d[0] + /* We're not out of data, loop if we haven't found the character */ + cbz synd, .Lloop + +.Lend: + /* Termination condition found, let's calculate the syndrome value */ + and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b + and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b + addp vend.16b, vhas_chr1.16b, vhas_chr2.16b /* 256->128 */ + addp vend.16b, vend.16b, vend.16b /* 128->64 */ + mov synd, vend.d[0] + /* Only do the clear for the last possible block */ + b.hi .Ltail + +.Lmasklast: + /* Clear the (32 - ((cntrem + soff) % 32)) * 2 upper bits */ + add tmp, cntrem, soff + and tmp, tmp, #31 + sub tmp, tmp, #32 + neg tmp, tmp, lsl #1 + lsl synd, synd, tmp + lsr synd, synd, tmp + +.Ltail: + /* Count the trailing zeros using bit reversing */ + rbit synd, synd + /* Compensate the last post-increment */ + sub src, src, #32 + /* Check that we have found a character */ + cmp synd, #0 + /* And count the leading zeros */ + clz synd, synd + /* Compute the potential result */ + add result, src, synd, lsr #1 + /* Select result or NULL */ + csel result, xzr, result, eq + ret + +.Lzero_length: + mov result, xzr + ret +END(memchr)
diff --git a/libc/arch-arm64/generic/bionic/memcmp.S b/libc/arch-arm64/generic/bionic/memcmp.S new file mode 100644 index 0000000..3d08ecd --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memcmp.S
@@ -0,0 +1,155 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#include <private/bionic_asm.h> + +/* Parameters and result. */ +#define src1 x0 +#define src2 x1 +#define limit x2 +#define result x0 + +/* Internal variables. */ +#define data1 x3 +#define data1w w3 +#define data2 x4 +#define data2w w4 +#define has_nul x5 +#define diff x6 +#define endloop x7 +#define tmp1 x8 +#define tmp2 x9 +#define tmp3 x10 +#define pos x11 +#define limit_wd x12 +#define mask x13 + +ENTRY(memcmp) + cbz limit, .Lret0 + eor tmp1, src1, src2 + tst tmp1, #7 + b.ne .Lmisaligned8 + ands tmp1, src1, #7 + b.ne .Lmutual_align + add limit_wd, limit, #7 + lsr limit_wd, limit_wd, #3 + /* Start of performance-critical section -- one 64B cache line. */ +.Lloop_aligned: + ldr data1, [src1], #8 + ldr data2, [src2], #8 +.Lstart_realigned: + subs limit_wd, limit_wd, #1 + eor diff, data1, data2 /* Non-zero if differences found. */ + csinv endloop, diff, xzr, ne /* Last Dword or differences. */ + cbz endloop, .Lloop_aligned + /* End of performance-critical section -- one 64B cache line. */ + + /* Not reached the limit, must have found a diff. */ + cbnz limit_wd, .Lnot_limit + + /* Limit % 8 == 0 => all bytes significant. */ + ands limit, limit, #7 + b.eq .Lnot_limit + + lsl limit, limit, #3 /* Bits -> bytes. */ + mov mask, #~0 +#ifdef __AARCH64EB__ + lsr mask, mask, limit +#else + lsl mask, mask, limit +#endif + bic data1, data1, mask + bic data2, data2, mask + + orr diff, diff, mask +.Lnot_limit: + +#ifndef __AARCH64EB__ + rev diff, diff + rev data1, data1 + rev data2, data2 +#endif + /* The MS-non-zero bit of DIFF marks either the first bit + that is different, or the end of the significant data. + Shifting left now will bring the critical information into the + top bits. */ + clz pos, diff + lsl data1, data1, pos + lsl data2, data2, pos + /* But we need to zero-extend (char is unsigned) the value and then + perform a signed 32-bit subtraction. */ + lsr data1, data1, #56 + sub result, data1, data2, lsr #56 + ret + +.Lmutual_align: + /* Sources are mutually aligned, but are not currently at an + alignment boundary. Round down the addresses and then mask off + the bytes that precede the start point. */ + bic src1, src1, #7 + bic src2, src2, #7 + add limit, limit, tmp1 /* Adjust the limit for the extra. */ + lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */ + ldr data1, [src1], #8 + neg tmp1, tmp1 /* Bits to alignment -64. */ + ldr data2, [src2], #8 + mov tmp2, #~0 +#ifdef __AARCH64EB__ + /* Big-endian. Early bytes are at MSB. */ + lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#else + /* Little-endian. Early bytes are at LSB. */ + lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#endif + add limit_wd, limit, #7 + orr data1, data1, tmp2 + orr data2, data2, tmp2 + lsr limit_wd, limit_wd, #3 + b .Lstart_realigned + +.Lret0: + mov result, #0 + ret + + .p2align 6 +.Lmisaligned8: + sub limit, limit, #1 +1: + /* Perhaps we can do better than this. */ + ldrb data1w, [src1], #1 + ldrb data2w, [src2], #1 + subs limit, limit, #1 + ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */ + b.eq 1b + sub result, data1, data2 + ret +END(memcmp)
diff --git a/libc/arch-arm64/generic/bionic/memcpy.S b/libc/arch-arm64/generic/bionic/memcpy.S new file mode 100644 index 0000000..0be2aac --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memcpy.S
@@ -0,0 +1,48 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +// Prototype: void *memcpy (void *dst, const void *src, size_t count). + +#include <private/bionic_asm.h> + +ENTRY(__memcpy_chk) + cmp x2, x3 + bls memcpy + + // Preserve for accurate backtrace. + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_rel_offset x29, 0 + .cfi_rel_offset x30, 8 + + bl __memcpy_chk_fail +END(__memcpy_chk) + +ENTRY(memcpy) + #include "memcpy_base.S" +END(memcpy)
diff --git a/libc/arch-arm64/generic/bionic/memcpy_base.S b/libc/arch-arm64/generic/bionic/memcpy_base.S new file mode 100644 index 0000000..c5d42ce --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memcpy_base.S
@@ -0,0 +1,179 @@ +/* Copyright (c) 2012, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + * Unaligned accesses + * + */ + +#define dstin x0 +#define src x1 +#define count x2 +#define tmp1 x3 +#define tmp1w w3 +#define tmp2 x4 +#define tmp2w w4 +#define tmp3 x5 +#define tmp3w w5 +#define dst x6 + +#define A_l x7 +#define A_h x8 +#define B_l x9 +#define B_h x10 +#define C_l x11 +#define C_h x12 +#define D_l x13 +#define D_h x14 + + mov dst, dstin + cmp count, #64 + b.ge .Lcpy_not_short + cmp count, #15 + b.le .Ltail15tiny + + /* Deal with small copies quickly by dropping straight into the + * exit block. */ +.Ltail63: + /* Copy up to 48 bytes of data. At this point we only need the + * bottom 6 bits of count to be accurate. */ + ands tmp1, count, #0x30 + b.eq .Ltail15 + add dst, dst, tmp1 + add src, src, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + ldp A_l, A_h, [src, #-48] + stp A_l, A_h, [dst, #-48] +1: + ldp A_l, A_h, [src, #-32] + stp A_l, A_h, [dst, #-32] +2: + ldp A_l, A_h, [src, #-16] + stp A_l, A_h, [dst, #-16] + +.Ltail15: + ands count, count, #15 + beq 1f + add src, src, count + ldp A_l, A_h, [src, #-16] + add dst, dst, count + stp A_l, A_h, [dst, #-16] +1: + ret + +.Ltail15tiny: + /* Copy up to 15 bytes of data. Does not assume additional data + being copied. */ + tbz count, #3, 1f + ldr tmp1, [src], #8 + str tmp1, [dst], #8 +1: + tbz count, #2, 1f + ldr tmp1w, [src], #4 + str tmp1w, [dst], #4 +1: + tbz count, #1, 1f + ldrh tmp1w, [src], #2 + strh tmp1w, [dst], #2 +1: + tbz count, #0, 1f + ldrb tmp1w, [src] + strb tmp1w, [dst] +1: + ret + +.Lcpy_not_short: + /* We don't much care about the alignment of DST, but we want SRC + * to be 128-bit (16 byte) aligned so that we don't cross cache line + * boundaries on both loads and stores. */ + neg tmp2, src + ands tmp2, tmp2, #15 /* Bytes to reach alignment. */ + b.eq 2f + sub count, count, tmp2 + /* Copy more data than needed; it's faster than jumping + * around copying sub-Quadword quantities. We know that + * it can't overrun. */ + ldp A_l, A_h, [src] + add src, src, tmp2 + stp A_l, A_h, [dst] + add dst, dst, tmp2 + /* There may be less than 63 bytes to go now. */ + cmp count, #63 + b.le .Ltail63 +2: + subs count, count, #128 + b.ge .Lcpy_body_large + /* Less than 128 bytes to copy, so handle 64 here and then jump + * to the tail. */ + ldp A_l, A_h, [src] + ldp B_l, B_h, [src, #16] + ldp C_l, C_h, [src, #32] + ldp D_l, D_h, [src, #48] + stp A_l, A_h, [dst] + stp B_l, B_h, [dst, #16] + stp C_l, C_h, [dst, #32] + stp D_l, D_h, [dst, #48] + tst count, #0x3f + add src, src, #64 + add dst, dst, #64 + b.ne .Ltail63 + ret + + /* Critical loop. Start at a new cache line boundary. Assuming + * 64 bytes per line this ensures the entire loop is in one line. */ + .p2align 6 +.Lcpy_body_large: + /* There are at least 128 bytes to copy. */ + ldp A_l, A_h, [src, #0] + sub dst, dst, #16 /* Pre-bias. */ + ldp B_l, B_h, [src, #16] + ldp C_l, C_h, [src, #32] + ldp D_l, D_h, [src, #48]! /* src += 64 - Pre-bias. */ +1: + stp A_l, A_h, [dst, #16] + ldp A_l, A_h, [src, #16] + stp B_l, B_h, [dst, #32] + ldp B_l, B_h, [src, #32] + stp C_l, C_h, [dst, #48] + ldp C_l, C_h, [src, #48] + stp D_l, D_h, [dst, #64]! + ldp D_l, D_h, [src, #64]! + subs count, count, #64 + b.ge 1b + stp A_l, A_h, [dst, #16] + stp B_l, B_h, [dst, #32] + stp C_l, C_h, [dst, #48] + stp D_l, D_h, [dst, #64] + add src, src, #16 + add dst, dst, #64 + 16 + tst count, #0x3f + b.ne .Ltail63 + ret
diff --git a/libc/arch-arm64/generic/bionic/memmove.S b/libc/arch-arm64/generic/bionic/memmove.S new file mode 100644 index 0000000..739ce49 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memmove.S
@@ -0,0 +1,329 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + * Unaligned accesses + * wchar_t is 4 bytes + */ + +#include <private/bionic_asm.h> + +/* Parameters and result. */ +#define dstin x0 +#define src x1 +#define count x2 +#define tmp1 x3 +#define tmp1w w3 +#define tmp2 x4 +#define tmp2w w4 +#define tmp3 x5 +#define tmp3w w5 +#define dst x6 + +#define A_l x7 +#define A_h x8 +#define B_l x9 +#define B_h x10 +#define C_l x11 +#define C_h x12 +#define D_l x13 +#define D_h x14 + +#if defined(WMEMMOVE) +ENTRY(wmemmove) + lsl count, count, #2 +#else +ENTRY(memmove) +#endif + cmp dstin, src + b.lo .Ldownwards + add tmp1, src, count + cmp dstin, tmp1 + b.hs memcpy /* No overlap. */ + + /* Upwards move with potential overlap. + * Need to move from the tail backwards. SRC and DST point one + * byte beyond the remaining data to move. */ + add dst, dstin, count + add src, src, count + cmp count, #64 + b.ge .Lmov_not_short_up + + /* Deal with small moves quickly by dropping straight into the + * exit block. */ +.Ltail63up: + /* Move up to 48 bytes of data. At this point we only need the + * bottom 6 bits of count to be accurate. */ + ands tmp1, count, #0x30 + b.eq .Ltail15up + sub dst, dst, tmp1 + sub src, src, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + ldp A_l, A_h, [src, #32] + stp A_l, A_h, [dst, #32] +1: + ldp A_l, A_h, [src, #16] + stp A_l, A_h, [dst, #16] +2: + ldp A_l, A_h, [src] + stp A_l, A_h, [dst] +.Ltail15up: + /* Move up to 15 bytes of data. Does not assume additional data + * being moved. */ + tbz count, #3, 1f + ldr tmp1, [src, #-8]! + str tmp1, [dst, #-8]! +1: + tbz count, #2, 1f + ldr tmp1w, [src, #-4]! + str tmp1w, [dst, #-4]! +1: + tbz count, #1, 1f + ldrh tmp1w, [src, #-2]! + strh tmp1w, [dst, #-2]! +1: + tbz count, #0, 1f + ldrb tmp1w, [src, #-1] + strb tmp1w, [dst, #-1] +1: + ret + +.Lmov_not_short_up: + /* We don't much care about the alignment of DST, but we want SRC + * to be 128-bit (16 byte) aligned so that we don't cross cache line + * boundaries on both loads and stores. */ + ands tmp2, src, #15 /* Bytes to reach alignment. */ + b.eq 2f + sub count, count, tmp2 + /* Move enough data to reach alignment; unlike memcpy, we have to + * be aware of the overlap, which means we can't move data twice. */ + tbz tmp2, #3, 1f + ldr tmp1, [src, #-8]! + str tmp1, [dst, #-8]! +1: + tbz tmp2, #2, 1f + ldr tmp1w, [src, #-4]! + str tmp1w, [dst, #-4]! +1: + tbz tmp2, #1, 1f + ldrh tmp1w, [src, #-2]! + strh tmp1w, [dst, #-2]! +1: + tbz tmp2, #0, 1f + ldrb tmp1w, [src, #-1]! + strb tmp1w, [dst, #-1]! +1: + + /* There may be less than 63 bytes to go now. */ + cmp count, #63 + b.le .Ltail63up +2: + subs count, count, #128 + b.ge .Lmov_body_large_up + /* Less than 128 bytes to move, so handle 64 here and then jump + * to the tail. */ + ldp A_l, A_h, [src, #-64]! + ldp B_l, B_h, [src, #16] + ldp C_l, C_h, [src, #32] + ldp D_l, D_h, [src, #48] + stp A_l, A_h, [dst, #-64]! + stp B_l, B_h, [dst, #16] + stp C_l, C_h, [dst, #32] + stp D_l, D_h, [dst, #48] + tst count, #0x3f + b.ne .Ltail63up + ret + + /* Critical loop. Start at a new Icache line boundary. Assuming + * 64 bytes per line this ensures the entire loop is in one line. */ + .p2align 6 +.Lmov_body_large_up: + /* There are at least 128 bytes to move. */ + ldp A_l, A_h, [src, #-16] + ldp B_l, B_h, [src, #-32] + ldp C_l, C_h, [src, #-48] + ldp D_l, D_h, [src, #-64]! +1: + stp A_l, A_h, [dst, #-16] + ldp A_l, A_h, [src, #-16] + stp B_l, B_h, [dst, #-32] + ldp B_l, B_h, [src, #-32] + stp C_l, C_h, [dst, #-48] + ldp C_l, C_h, [src, #-48] + stp D_l, D_h, [dst, #-64]! + ldp D_l, D_h, [src, #-64]! + subs count, count, #64 + b.ge 1b + stp A_l, A_h, [dst, #-16] + stp B_l, B_h, [dst, #-32] + stp C_l, C_h, [dst, #-48] + stp D_l, D_h, [dst, #-64]! + tst count, #0x3f + b.ne .Ltail63up + ret + + +.Ldownwards: + /* For a downwards move we can safely use memcpy provided that + * DST is more than 16 bytes away from SRC. */ + sub tmp1, src, #16 + cmp dstin, tmp1 + b.ls memcpy /* May overlap, but not critically. */ + + mov dst, dstin /* Preserve DSTIN for return value. */ + cmp count, #64 + b.ge .Lmov_not_short_down + + /* Deal with small moves quickly by dropping straight into the + * exit block. */ +.Ltail63down: + /* Move up to 48 bytes of data. At this point we only need the + * bottom 6 bits of count to be accurate. */ + ands tmp1, count, #0x30 + b.eq .Ltail15down + add dst, dst, tmp1 + add src, src, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + ldp A_l, A_h, [src, #-48] + stp A_l, A_h, [dst, #-48] +1: + ldp A_l, A_h, [src, #-32] + stp A_l, A_h, [dst, #-32] +2: + ldp A_l, A_h, [src, #-16] + stp A_l, A_h, [dst, #-16] +.Ltail15down: + /* Move up to 15 bytes of data. Does not assume additional data + being moved. */ + tbz count, #3, 1f + ldr tmp1, [src], #8 + str tmp1, [dst], #8 +1: + tbz count, #2, 1f + ldr tmp1w, [src], #4 + str tmp1w, [dst], #4 +1: + tbz count, #1, 1f + ldrh tmp1w, [src], #2 + strh tmp1w, [dst], #2 +1: + tbz count, #0, 1f + ldrb tmp1w, [src] + strb tmp1w, [dst] +1: + ret + +.Lmov_not_short_down: + /* We don't much care about the alignment of DST, but we want SRC + * to be 128-bit (16 byte) aligned so that we don't cross cache line + * boundaries on both loads and stores. */ + neg tmp2, src + ands tmp2, tmp2, #15 /* Bytes to reach alignment. */ + b.eq 2f + sub count, count, tmp2 + /* Move enough data to reach alignment; unlike memcpy, we have to + * be aware of the overlap, which means we can't move data twice. */ + tbz tmp2, #3, 1f + ldr tmp1, [src], #8 + str tmp1, [dst], #8 +1: + tbz tmp2, #2, 1f + ldr tmp1w, [src], #4 + str tmp1w, [dst], #4 +1: + tbz tmp2, #1, 1f + ldrh tmp1w, [src], #2 + strh tmp1w, [dst], #2 +1: + tbz tmp2, #0, 1f + ldrb tmp1w, [src], #1 + strb tmp1w, [dst], #1 +1: + + /* There may be less than 63 bytes to go now. */ + cmp count, #63 + b.le .Ltail63down +2: + subs count, count, #128 + b.ge .Lmov_body_large_down + /* Less than 128 bytes to move, so handle 64 here and then jump + * to the tail. */ + ldp A_l, A_h, [src] + ldp B_l, B_h, [src, #16] + ldp C_l, C_h, [src, #32] + ldp D_l, D_h, [src, #48] + stp A_l, A_h, [dst] + stp B_l, B_h, [dst, #16] + stp C_l, C_h, [dst, #32] + stp D_l, D_h, [dst, #48] + tst count, #0x3f + add src, src, #64 + add dst, dst, #64 + b.ne .Ltail63down + ret + + /* Critical loop. Start at a new cache line boundary. Assuming + * 64 bytes per line this ensures the entire loop is in one line. */ + .p2align 6 +.Lmov_body_large_down: + /* There are at least 128 bytes to move. */ + ldp A_l, A_h, [src, #0] + sub dst, dst, #16 /* Pre-bias. */ + ldp B_l, B_h, [src, #16] + ldp C_l, C_h, [src, #32] + ldp D_l, D_h, [src, #48]! /* src += 64 - Pre-bias. */ +1: + stp A_l, A_h, [dst, #16] + ldp A_l, A_h, [src, #16] + stp B_l, B_h, [dst, #32] + ldp B_l, B_h, [src, #32] + stp C_l, C_h, [dst, #48] + ldp C_l, C_h, [src, #48] + stp D_l, D_h, [dst, #64]! + ldp D_l, D_h, [src, #64]! + subs count, count, #64 + b.ge 1b + stp A_l, A_h, [dst, #16] + stp B_l, B_h, [dst, #32] + stp C_l, C_h, [dst, #48] + stp D_l, D_h, [dst, #64] + add src, src, #16 + add dst, dst, #64 + 16 + tst count, #0x3f + b.ne .Ltail63down + ret +#if defined(WMEMMOVE) +END(wmemmove) +#else +END(memmove) +#endif
diff --git a/libc/arch-arm64/generic/bionic/memset.S b/libc/arch-arm64/generic/bionic/memset.S new file mode 100644 index 0000000..9626c0b --- /dev/null +++ b/libc/arch-arm64/generic/bionic/memset.S
@@ -0,0 +1,246 @@ +/* Copyright (c) 2012, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + * Unaligned accesses + * + */ + +#include <private/bionic_asm.h> + +/* By default we assume that the DC instruction can be used to zero + data blocks more efficiently. In some circumstances this might be + unsafe, for example in an asymmetric multiprocessor environment with + different DC clear lengths (neither the upper nor lower lengths are + safe to use). + + If code may be run in a virtualized environment, then define + MAYBE_VIRT. This will cause the code to cache the system register + values rather than re-reading them each call. */ + +#define dstin x0 +#define val w1 +#define count x2 +#define dst_count x3 /* for __memset_chk */ +#define tmp1 x3 +#define tmp1w w3 +#define tmp2 x4 +#define tmp2w w4 +#define zva_len_x x5 +#define zva_len w5 +#define zva_bits_x x6 + +#define A_l x7 +#define A_lw w7 +#define dst x8 +#define tmp3w w9 + +ENTRY(__memset_chk) + cmp count, dst_count + bls memset + + // Preserve for accurate backtrace. + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_rel_offset x29, 0 + .cfi_rel_offset x30, 8 + + bl __memset_chk_fail +END(__memset_chk) + +ENTRY(memset) + + mov dst, dstin /* Preserve return value. */ + ands A_lw, val, #255 + b.eq .Lzero_mem + orr A_lw, A_lw, A_lw, lsl #8 + orr A_lw, A_lw, A_lw, lsl #16 + orr A_l, A_l, A_l, lsl #32 +.Ltail_maybe_long: + cmp count, #64 + b.ge .Lnot_short +.Ltail_maybe_tiny: + cmp count, #15 + b.le .Ltail15tiny +.Ltail63: + ands tmp1, count, #0x30 + b.eq .Ltail15 + add dst, dst, tmp1 + cmp tmp1w, #0x20 + b.eq 1f + b.lt 2f + stp A_l, A_l, [dst, #-48] +1: + stp A_l, A_l, [dst, #-32] +2: + stp A_l, A_l, [dst, #-16] + +.Ltail15: + and count, count, #15 + add dst, dst, count + stp A_l, A_l, [dst, #-16] /* Repeat some/all of last store. */ + ret + +.Ltail15tiny: + /* Set up to 15 bytes. Does not assume earlier memory + being set. */ + tbz count, #3, 1f + str A_l, [dst], #8 +1: + tbz count, #2, 1f + str A_lw, [dst], #4 +1: + tbz count, #1, 1f + strh A_lw, [dst], #2 +1: + tbz count, #0, 1f + strb A_lw, [dst] +1: + ret + + /* Critical loop. Start at a new cache line boundary. Assuming + * 64 bytes per line, this ensures the entire loop is in one line. */ + .p2align 6 +.Lnot_short: + neg tmp2, dst + ands tmp2, tmp2, #15 + b.eq 2f + /* Bring DST to 128-bit (16-byte) alignment. We know that there's + * more than that to set, so we simply store 16 bytes and advance by + * the amount required to reach alignment. */ + sub count, count, tmp2 + stp A_l, A_l, [dst] + add dst, dst, tmp2 + /* There may be less than 63 bytes to go now. */ + cmp count, #63 + b.le .Ltail63 +2: + sub dst, dst, #16 /* Pre-bias. */ + sub count, count, #64 +1: + stp A_l, A_l, [dst, #16] + stp A_l, A_l, [dst, #32] + stp A_l, A_l, [dst, #48] + stp A_l, A_l, [dst, #64]! + subs count, count, #64 + b.ge 1b + tst count, #0x3f + add dst, dst, #16 + b.ne .Ltail63 + ret + + /* For zeroing memory, check to see if we can use the ZVA feature to + * zero entire 'cache' lines. */ +.Lzero_mem: + mov A_l, #0 + cmp count, #63 + b.le .Ltail_maybe_tiny + neg tmp2, dst + ands tmp2, tmp2, #15 + b.eq 1f + sub count, count, tmp2 + stp A_l, A_l, [dst] + add dst, dst, tmp2 + cmp count, #63 + b.le .Ltail63 +1: + /* For zeroing small amounts of memory, it's not worth setting up + * the line-clear code. */ + cmp count, #128 + b.lt .Lnot_short +#ifdef MAYBE_VIRT + /* For efficiency when virtualized, we cache the ZVA capability. */ + adrp tmp2, .Lcache_clear + ldr zva_len, [tmp2, #:lo12:.Lcache_clear] + tbnz zva_len, #31, .Lnot_short + cbnz zva_len, .Lzero_by_line + mrs tmp1, dczid_el0 + tbz tmp1, #4, 1f + /* ZVA not available. Remember this for next time. */ + mov zva_len, #~0 + str zva_len, [tmp2, #:lo12:.Lcache_clear] + b .Lnot_short +1: + mov tmp3w, #4 + and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ + lsl zva_len, tmp3w, zva_len + str zva_len, [tmp2, #:lo12:.Lcache_clear] +#else + mrs tmp1, dczid_el0 + tbnz tmp1, #4, .Lnot_short + mov tmp3w, #4 + and zva_len, tmp1w, #15 /* Safety: other bits reserved. */ + lsl zva_len, tmp3w, zva_len +#endif + +.Lzero_by_line: + /* Compute how far we need to go to become suitably aligned. We're + * already at quad-word alignment. */ + cmp count, zva_len_x + b.lt .Lnot_short /* Not enough to reach alignment. */ + sub zva_bits_x, zva_len_x, #1 + neg tmp2, dst + ands tmp2, tmp2, zva_bits_x + b.eq 1f /* Already aligned. */ + /* Not aligned, check that there's enough to copy after alignment. */ + sub tmp1, count, tmp2 + cmp tmp1, #64 + ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */ + b.lt .Lnot_short + /* We know that there's at least 64 bytes to zero and that it's safe + * to overrun by 64 bytes. */ + mov count, tmp1 +2: + stp A_l, A_l, [dst] + stp A_l, A_l, [dst, #16] + stp A_l, A_l, [dst, #32] + subs tmp2, tmp2, #64 + stp A_l, A_l, [dst, #48] + add dst, dst, #64 + b.ge 2b + /* We've overrun a bit, so adjust dst downwards. */ + add dst, dst, tmp2 +1: + sub count, count, zva_len_x +3: + dc zva, dst + add dst, dst, zva_len_x + subs count, count, zva_len_x + b.ge 3b + ands count, count, zva_bits_x + b.ne .Ltail_maybe_long + ret +END(memset) + +#ifdef MAYBE_VIRT + .bss + .p2align 2 +.Lcache_clear: + .space 4 +#endif
diff --git a/libc/arch-arm64/generic/bionic/stpcpy.S b/libc/arch-arm64/generic/bionic/stpcpy.S new file mode 100644 index 0000000..e4a7993 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/stpcpy.S
@@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define STPCPY +#include "string_copy.S"
diff --git a/libc/arch-arm64/generic/bionic/strchr.S b/libc/arch-arm64/generic/bionic/strchr.S new file mode 100644 index 0000000..b54106d --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strchr.S
@@ -0,0 +1,154 @@ +/* + strchr - find a character in a string + + Copyright (c) 2014, ARM Limited + All rights Reserved. + Copyright (c) 2014, Linaro Ltd. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the company nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + * Neon Available. + */ + +#include <private/bionic_asm.h> + +/* Arguments and results. */ +#define srcin x0 +#define chrin w1 + +#define result x0 + +#define src x2 +#define tmp1 x3 +#define wtmp2 w4 +#define tmp3 x5 + +#define vrepchr v0 +#define vdata1 v1 +#define vdata2 v2 +#define vhas_nul1 v3 +#define vhas_nul2 v4 +#define vhas_chr1 v5 +#define vhas_chr2 v6 +#define vrepmask_0 v7 +#define vrepmask_c v16 +#define vend1 v17 +#define vend2 v18 + +/* Core algorithm. + + For each 32-byte hunk we calculate a 64-bit syndrome value, with + two bits per byte (LSB is always in bits 0 and 1, for both big + and little-endian systems). For each tuple, bit 0 is set iff + the relevant byte matched the requested character; bit 1 is set + iff the relevant byte matched the NUL end of string (we trigger + off bit0 for the special case of looking for NUL). Since the bits + in the syndrome reflect exactly the order in which things occur + in the original string a count_trailing_zeros() operation will + identify exactly which byte is causing the termination, and why. */ + +/* Locals and temporaries. */ + +ENTRY(strchr) + /* Magic constant 0x40100401 to allow us to identify which lane + matches the requested byte. Magic constant 0x80200802 used + similarly for NUL termination. */ + mov wtmp2, #0x0401 + movk wtmp2, #0x4010, lsl #16 + dup vrepchr.16b, chrin + bic src, srcin, #31 /* Work with aligned 32-byte hunks. */ + dup vrepmask_c.4s, wtmp2 + ands tmp1, srcin, #31 + add vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */ + b.eq .Lloop + + /* Input string is not 32-byte aligned. Rather than forcing + the padding bytes to a safe value, we calculate the syndrome + for all the bytes, but then mask off those bits of the + syndrome that are related to the padding. */ + ld1 {vdata1.16b, vdata2.16b}, [src], #32 + neg tmp1, tmp1 + cmeq vhas_nul1.16b, vdata1.16b, #0 + cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b + cmeq vhas_nul2.16b, vdata2.16b, #0 + cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b + and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b + and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b + and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b + and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b + orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b + orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b + lsl tmp1, tmp1, #1 + addp vend1.16b, vend1.16b, vend2.16b // 256->128 + mov tmp3, #~0 + addp vend1.16b, vend1.16b, vend2.16b // 128->64 + lsr tmp1, tmp3, tmp1 + + mov tmp3, vend1.d[0] + bic tmp1, tmp3, tmp1 // Mask padding bits. + cbnz tmp1, .Ltail + +.Lloop: + ld1 {vdata1.16b, vdata2.16b}, [src], #32 + cmeq vhas_nul1.16b, vdata1.16b, #0 + cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b + cmeq vhas_nul2.16b, vdata2.16b, #0 + cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b + /* Use a fast check for the termination condition. */ + orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b + orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b + orr vend1.16b, vend1.16b, vend2.16b + addp vend1.2d, vend1.2d, vend1.2d + mov tmp1, vend1.d[0] + cbz tmp1, .Lloop + + /* Termination condition found. Now need to establish exactly why + we terminated. */ + and vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b + and vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b + and vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b + and vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b + orr vend1.16b, vhas_nul1.16b, vhas_chr1.16b + orr vend2.16b, vhas_nul2.16b, vhas_chr2.16b + addp vend1.16b, vend1.16b, vend2.16b // 256->128 + addp vend1.16b, vend1.16b, vend2.16b // 128->64 + + mov tmp1, vend1.d[0] +.Ltail: + /* Count the trailing zeros, by bit reversing... */ + rbit tmp1, tmp1 + /* Re-bias source. */ + sub src, src, #32 + clz tmp1, tmp1 /* And counting the leading zeros. */ + /* Tmp1 is even if the target charager was found first. Otherwise + we've found the end of string and we weren't looking for NUL. */ + tst tmp1, #1 + add result, src, tmp1, lsr #1 + csel result, result, xzr, eq + ret +END(strchr)
diff --git a/libc/arch-arm64/generic/bionic/strcmp.S b/libc/arch-arm64/generic/bionic/strcmp.S new file mode 100644 index 0000000..3cce478 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strcmp.S
@@ -0,0 +1,162 @@ +/* Copyright (c) 2012, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#include <private/bionic_asm.h> + +#define REP8_01 0x0101010101010101 +#define REP8_7f 0x7f7f7f7f7f7f7f7f +#define REP8_80 0x8080808080808080 + +/* Parameters and result. */ +#define src1 x0 +#define src2 x1 +#define result x0 + +/* Internal variables. */ +#define data1 x2 +#define data1w w2 +#define data2 x3 +#define data2w w3 +#define has_nul x4 +#define diff x5 +#define syndrome x6 +#define tmp1 x7 +#define tmp2 x8 +#define tmp3 x9 +#define zeroones x10 +#define pos x11 + + /* Start of performance-critical section -- one 64B cache line. */ +ENTRY(strcmp) + eor tmp1, src1, src2 + mov zeroones, #REP8_01 + tst tmp1, #7 + b.ne .Lmisaligned8 + ands tmp1, src1, #7 + b.ne .Lmutual_align + /* NUL detection works on the principle that (X - 1) & (~X) & 0x80 + (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and + can be done in parallel across the entire word. */ +.Lloop_aligned: + ldr data1, [src1], #8 + ldr data2, [src2], #8 +.Lstart_realigned: + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + eor diff, data1, data2 /* Non-zero if differences found. */ + bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */ + orr syndrome, diff, has_nul + cbz syndrome, .Lloop_aligned + /* End of performance-critical section -- one 64B cache line. */ + +#ifndef __AARCH64EB__ + rev syndrome, syndrome + rev data1, data1 + /* The MS-non-zero bit of the syndrome marks either the first bit + that is different, or the top bit of the first zero byte. + Shifting left now will bring the critical information into the + top bits. */ + clz pos, syndrome + rev data2, data2 + lsl data1, data1, pos + lsl data2, data2, pos + /* But we need to zero-extend (char is unsigned) the value and then + perform a signed 32-bit subtraction. */ + lsr data1, data1, #56 + sub result, data1, data2, lsr #56 + ret +#else + /* For big-endian we cannot use the trick with the syndrome value + as carry-propagation can corrupt the upper bits if the trailing + bytes in the string contain 0x01. */ + /* However, if there is no NUL byte in the dword, we can generate + the result directly. We can't just subtract the bytes as the + MSB might be significant. */ + cbnz has_nul, 1f + cmp data1, data2 + cset result, ne + cneg result, result, lo + ret +1: + /* Re-compute the NUL-byte detection, using a byte-reversed value. */ + rev tmp3, data1 + sub tmp1, tmp3, zeroones + orr tmp2, tmp3, #REP8_7f + bic has_nul, tmp1, tmp2 + rev has_nul, has_nul + orr syndrome, diff, has_nul + clz pos, syndrome + /* The MS-non-zero bit of the syndrome marks either the first bit + that is different, or the top bit of the first zero byte. + Shifting left now will bring the critical information into the + top bits. */ + lsl data1, data1, pos + lsl data2, data2, pos + /* But we need to zero-extend (char is unsigned) the value and then + perform a signed 32-bit subtraction. */ + lsr data1, data1, #56 + sub result, data1, data2, lsr #56 + ret +#endif + +.Lmutual_align: + /* Sources are mutually aligned, but are not currently at an + alignment boundary. Round down the addresses and then mask off + the bytes that preceed the start point. */ + bic src1, src1, #7 + bic src2, src2, #7 + lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */ + ldr data1, [src1], #8 + neg tmp1, tmp1 /* Bits to alignment -64. */ + ldr data2, [src2], #8 + mov tmp2, #~0 +#ifdef __AARCH64EB__ + /* Big-endian. Early bytes are at MSB. */ + lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#else + /* Little-endian. Early bytes are at LSB. */ + lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#endif + orr data1, data1, tmp2 + orr data2, data2, tmp2 + b .Lstart_realigned + +.Lmisaligned8: + /* We can do better than this. */ + ldrb data1w, [src1], #1 + ldrb data2w, [src2], #1 + cmp data1w, #1 + ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */ + b.eq .Lmisaligned8 + sub result, data1, data2 + ret +END(strcmp)
diff --git a/libc/arch-arm64/generic/bionic/strcpy.S b/libc/arch-arm64/generic/bionic/strcpy.S new file mode 100644 index 0000000..260c321 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strcpy.S
@@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define STRCPY +#include "string_copy.S"
diff --git a/libc/arch-arm64/generic/bionic/string_copy.S b/libc/arch-arm64/generic/bionic/string_copy.S new file mode 100644 index 0000000..2bf969d --- /dev/null +++ b/libc/arch-arm64/generic/bionic/string_copy.S
@@ -0,0 +1,245 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#if !defined(STPCPY) && !defined(STRCPY) +#error "Either STPCPY or STRCPY must be defined." +#endif + +#include <private/bionic_asm.h> + +/* Arguments and results. */ +#if defined(STPCPY) +#define dst x0 +#elif defined(STRCPY) +#define dstin x0 +#endif +#define src x1 + +/* Locals and temporaries. */ +#if defined(STRCPY) +#define dst x2 +#endif +#define data1 x3 +#define data1_w w3 +#define data2 x4 +#define data2_w w4 +#define has_nul1 x5 +#define has_nul1_w w5 +#define has_nul2 x6 +#define tmp1 x7 +#define tmp2 x8 +#define tmp3 x9 +#define tmp4 x10 +#define zeroones x11 +#define zeroones_w w11 +#define pos x12 + +#define REP8_01 0x0101010101010101 +#define REP8_7f 0x7f7f7f7f7f7f7f7f +#define REP8_80 0x8080808080808080 + +#if defined(STPCPY) +ENTRY(stpcpy) +#elif defined(STRCPY) +ENTRY(strcpy) +#endif + mov zeroones, #REP8_01 +#if defined(STRCPY) + mov dst, dstin +#endif + ands tmp1, src, #15 + b.ne .Lmisaligned + // NUL detection works on the principle that (X - 1) & (~X) & 0x80 + // (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and + // can be done in parallel across the entire word. + // The inner loop deals with two Dwords at a time. This has a + // slightly higher start-up cost, but we should win quite quickly, + // especially on cores with a high number of issue slots per + // cycle, as we get much better parallelism out of the operations. +.Lloop: + ldp data1, data2, [src], #16 + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + bic has_nul1, tmp1, tmp2 + cbnz has_nul1, .Lnul_in_data1 + sub tmp3, data2, zeroones + orr tmp4, data2, #REP8_7f + bic has_nul2, tmp3, tmp4 + cbnz has_nul2, .Lnul_in_data2 + // No NUL in either register, copy it in a single instruction. + stp data1, data2, [dst], #16 + b .Lloop + +.Lnul_in_data1: + rev has_nul1, has_nul1 + clz pos, has_nul1 + add tmp1, pos, #0x8 + + tbz tmp1, #6, 1f +#if defined(STPCPY) + str data1, [dst], #7 +#elif defined(STRCPY) + str data1, [dst] +#endif + ret +1: + tbz tmp1, #5, 1f + str data1_w, [dst], #4 + lsr data1, data1, #32 +1: + tbz tmp1, #4, 1f + strh data1_w, [dst], #2 + lsr data1, data1, #16 +1: + tbz tmp1, #3, 1f + strb data1_w, [dst] +#if defined(STPCPY) + ret +#endif +1: +#if defined(STPCPY) + // Back up one so that dst points to the '\0' string terminator. + sub dst, dst, #1 +#endif + ret + +.Lnul_in_data2: + str data1, [dst], #8 + rev has_nul2, has_nul2 + clz pos, has_nul2 + add tmp1, pos, #0x8 + + tbz tmp1, #6, 1f +#if defined(STPCPY) + str data2, [dst], #7 +#elif defined(STRCPY) + str data2, [dst] +#endif + ret +1: + tbz tmp1, #5, 1f + str data2_w, [dst], #4 + lsr data2, data2, #32 +1: + tbz tmp1, #4, 1f + strh data2_w, [dst], #2 + lsr data2, data2, #16 +1: + tbz tmp1, #3, 1f + strb data2_w, [dst] +#if defined(STPCPY) + ret +#endif +1: +#if defined(STPCPY) + // Back up one so that dst points to the '\0' string terminator. + sub dst, dst, #1 +#endif + ret + +.Lmisaligned: + tbz src, #0, 1f + ldrb data1_w, [src], #1 + strb data1_w, [dst], #1 + cbnz data1_w, 1f +#if defined(STPCPY) + // Back up one so that dst points to the '\0' string terminator. + sub dst, dst, #1 +#endif + ret +1: + tbz src, #1, 1f + ldrb data1_w, [src], #1 + strb data1_w, [dst], #1 + cbz data1_w, .Ldone + ldrb data2_w, [src], #1 + strb data2_w, [dst], #1 + cbnz data2_w, 1f +.Ldone: +#if defined(STPCPY) + // Back up one so that dst points to the '\0' string terminator. + sub dst, dst, #1 +#endif + ret +1: + tbz src, #2, 1f + ldr data1_w, [src], #4 + // Check for a zero. + sub has_nul1_w, data1_w, zeroones_w + bic has_nul1_w, has_nul1_w, data1_w + ands has_nul1_w, has_nul1_w, #0x80808080 + b.ne .Lnul_in_data1 + str data1_w, [dst], #4 +1: + tbz src, #3, .Lloop + ldr data1, [src], #8 + // Check for a zero. + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + bics has_nul1, tmp1, tmp2 + b.ne .Lnul_in_data1 + str data1, [dst], #8 + b .Lloop +#if defined(STPCPY) +END(stpcpy) +#elif defined(STRCPY) +END(strcpy) +#endif
diff --git a/libc/arch-arm64/generic/bionic/strlen.S b/libc/arch-arm64/generic/bionic/strlen.S new file mode 100644 index 0000000..3bd9809 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strlen.S
@@ -0,0 +1,126 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#include <private/bionic_asm.h> + +/* Arguments and results. */ +#define srcin x0 +#define len x0 + +/* Locals and temporaries. */ +#define src x1 +#define data1 x2 +#define data2 x3 +#define data2a x4 +#define has_nul1 x5 +#define has_nul2 x6 +#define tmp1 x7 +#define tmp2 x8 +#define tmp3 x9 +#define tmp4 x10 +#define zeroones x11 +#define pos x12 + +#define REP8_01 0x0101010101010101 +#define REP8_7f 0x7f7f7f7f7f7f7f7f +#define REP8_80 0x8080808080808080 + + /* Start of critial section -- keep to one 64Byte cache line. */ +ENTRY(strlen) + mov zeroones, #REP8_01 + bic src, srcin, #15 + ands tmp1, srcin, #15 + b.ne .Lmisaligned + /* NUL detection works on the principle that (X - 1) & (~X) & 0x80 + (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and + can be done in parallel across the entire word. */ + /* The inner loop deals with two Dwords at a time. This has a + slightly higher start-up cost, but we should win quite quickly, + especially on cores with a high number of issue slots per + cycle, as we get much better parallelism out of the operations. */ +.Lloop: + ldp data1, data2, [src], #16 +.Lrealigned: + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + sub tmp3, data2, zeroones + orr tmp4, data2, #REP8_7f + bic has_nul1, tmp1, tmp2 + bics has_nul2, tmp3, tmp4 + ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */ + b.eq .Lloop + /* End of critical section -- keep to one 64Byte cache line. */ + + sub len, src, srcin + cbz has_nul1, .Lnul_in_data2 +#ifdef __AARCH64EB__ + mov data2, data1 +#endif + sub len, len, #8 + mov has_nul2, has_nul1 +.Lnul_in_data2: +#ifdef __AARCH64EB__ + /* For big-endian, carry propagation (if the final byte in the + string is 0x01) means we cannot use has_nul directly. The + easiest way to get the correct byte is to byte-swap the data + and calculate the syndrome a second time. */ + rev data2, data2 + sub tmp1, data2, zeroones + orr tmp2, data2, #REP8_7f + bic has_nul2, tmp1, tmp2 +#endif + sub len, len, #8 + rev has_nul2, has_nul2 + clz pos, has_nul2 + add len, len, pos, lsr #3 /* Bits to bytes. */ + ret + +.Lmisaligned: + cmp tmp1, #8 + neg tmp1, tmp1 + ldp data1, data2, [src], #16 + lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */ + mov tmp2, #~0 +#ifdef __AARCH64EB__ + /* Big-endian. Early bytes are at MSB. */ + lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#else + /* Little-endian. Early bytes are at LSB. */ + lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */ +#endif + orr data1, data1, tmp2 + orr data2a, data2, tmp2 + csinv data1, data1, xzr, le + csel data2, data2, data2a, le + b .Lrealigned + +END(strlen)
diff --git a/libc/arch-arm64/generic/bionic/strncmp.S b/libc/arch-arm64/generic/bionic/strncmp.S new file mode 100644 index 0000000..267f663 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strncmp.S
@@ -0,0 +1,217 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#include <private/bionic_asm.h> + +#define REP8_01 0x0101010101010101 +#define REP8_7f 0x7f7f7f7f7f7f7f7f +#define REP8_80 0x8080808080808080 + +/* Parameters and result. */ +#define src1 x0 +#define src2 x1 +#define limit x2 +#define result x0 + +/* Internal variables. */ +#define data1 x3 +#define data1w w3 +#define data2 x4 +#define data2w w4 +#define has_nul x5 +#define diff x6 +#define syndrome x7 +#define tmp1 x8 +#define tmp2 x9 +#define tmp3 x10 +#define zeroones x11 +#define pos x12 +#define limit_wd x13 +#define mask x14 +#define endloop x15 + + .text + .p2align 6 + .rep 7 + nop /* Pad so that the loop below fits a cache line. */ + .endr +ENTRY(strncmp) + cbz limit, .Lret0 + eor tmp1, src1, src2 + mov zeroones, #REP8_01 + tst tmp1, #7 + b.ne .Lmisaligned8 + ands tmp1, src1, #7 + b.ne .Lmutual_align + /* Calculate the number of full and partial words -1. */ + sub limit_wd, limit, #1 /* limit != 0, so no underflow. */ + lsr limit_wd, limit_wd, #3 /* Convert to Dwords. */ + + /* NUL detection works on the principle that (X - 1) & (~X) & 0x80 + (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and + can be done in parallel across the entire word. */ + /* Start of performance-critical section -- one 64B cache line. */ +.Lloop_aligned: + ldr data1, [src1], #8 + ldr data2, [src2], #8 +.Lstart_realigned: + subs limit_wd, limit_wd, #1 + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + eor diff, data1, data2 /* Non-zero if differences found. */ + csinv endloop, diff, xzr, pl /* Last Dword or differences. */ + bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */ + ccmp endloop, #0, #0, eq + b.eq .Lloop_aligned + /* End of performance-critical section -- one 64B cache line. */ + + /* Not reached the limit, must have found the end or a diff. */ + tbz limit_wd, #63, .Lnot_limit + + /* Limit % 8 == 0 => all bytes significant. */ + ands limit, limit, #7 + b.eq .Lnot_limit + + lsl limit, limit, #3 /* Bits -> bytes. */ + mov mask, #~0 +#ifdef __AARCH64EB__ + lsr mask, mask, limit +#else + lsl mask, mask, limit +#endif + bic data1, data1, mask + bic data2, data2, mask + + /* Make sure that the NUL byte is marked in the syndrome. */ + orr has_nul, has_nul, mask + +.Lnot_limit: + orr syndrome, diff, has_nul + +#ifndef __AARCH64EB__ + rev syndrome, syndrome + rev data1, data1 + /* The MS-non-zero bit of the syndrome marks either the first bit + that is different, or the top bit of the first zero byte. + Shifting left now will bring the critical information into the + top bits. */ + clz pos, syndrome + rev data2, data2 + lsl data1, data1, pos + lsl data2, data2, pos + /* But we need to zero-extend (char is unsigned) the value and then + perform a signed 32-bit subtraction. */ + lsr data1, data1, #56 + sub result, data1, data2, lsr #56 + ret +#else + /* For big-endian we cannot use the trick with the syndrome value + as carry-propagation can corrupt the upper bits if the trailing + bytes in the string contain 0x01. */ + /* However, if there is no NUL byte in the dword, we can generate + the result directly. We can't just subtract the bytes as the + MSB might be significant. */ + cbnz has_nul, 1f + cmp data1, data2 + cset result, ne + cneg result, result, lo + ret +1: + /* Re-compute the NUL-byte detection, using a byte-reversed value. */ + rev tmp3, data1 + sub tmp1, tmp3, zeroones + orr tmp2, tmp3, #REP8_7f + bic has_nul, tmp1, tmp2 + rev has_nul, has_nul + orr syndrome, diff, has_nul + clz pos, syndrome + /* The MS-non-zero bit of the syndrome marks either the first bit + that is different, or the top bit of the first zero byte. + Shifting left now will bring the critical information into the + top bits. */ + lsl data1, data1, pos + lsl data2, data2, pos + /* But we need to zero-extend (char is unsigned) the value and then + perform a signed 32-bit subtraction. */ + lsr data1, data1, #56 + sub result, data1, data2, lsr #56 + ret +#endif + +.Lmutual_align: + /* Sources are mutually aligned, but are not currently at an + alignment boundary. Round down the addresses and then mask off + the bytes that precede the start point. + We also need to adjust the limit calculations, but without + overflowing if the limit is near ULONG_MAX. */ + bic src1, src1, #7 + bic src2, src2, #7 + ldr data1, [src1], #8 + neg tmp3, tmp1, lsl #3 /* 64 - bits(bytes beyond align). */ + ldr data2, [src2], #8 + mov tmp2, #~0 + sub limit_wd, limit, #1 /* limit != 0, so no underflow. */ +#ifdef __AARCH64EB__ + /* Big-endian. Early bytes are at MSB. */ + lsl tmp2, tmp2, tmp3 /* Shift (tmp1 & 63). */ +#else + /* Little-endian. Early bytes are at LSB. */ + lsr tmp2, tmp2, tmp3 /* Shift (tmp1 & 63). */ +#endif + and tmp3, limit_wd, #7 + lsr limit_wd, limit_wd, #3 + /* Adjust the limit. Only low 3 bits used, so overflow irrelevant. */ + add limit, limit, tmp1 + add tmp3, tmp3, tmp1 + orr data1, data1, tmp2 + orr data2, data2, tmp2 + add limit_wd, limit_wd, tmp3, lsr #3 + b .Lstart_realigned + +.Lret0: + mov result, #0 + ret + + .p2align 6 +.Lmisaligned8: + sub limit, limit, #1 +1: + /* Perhaps we can do better than this. */ + ldrb data1w, [src1], #1 + ldrb data2w, [src2], #1 + subs limit, limit, #1 + ccmp data1w, #1, #0, cs /* NZCV = 0b0000. */ + ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */ + b.eq 1b + sub result, data1, data2 + ret +END(strncmp)
diff --git a/libc/arch-arm64/generic/bionic/strnlen.S b/libc/arch-arm64/generic/bionic/strnlen.S new file mode 100644 index 0000000..0ad446e --- /dev/null +++ b/libc/arch-arm64/generic/bionic/strnlen.S
@@ -0,0 +1,174 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Assumptions: + * + * ARMv8-a, AArch64 + */ + +#include <private/bionic_asm.h> + +/* Arguments and results. */ +#define srcin x0 +#define len x0 +#define limit x1 + +/* Locals and temporaries. */ +#define src x2 +#define data1 x3 +#define data2 x4 +#define data2a x5 +#define has_nul1 x6 +#define has_nul2 x7 +#define tmp1 x8 +#define tmp2 x9 +#define tmp3 x10 +#define tmp4 x11 +#define zeroones x12 +#define pos x13 +#define limit_wd x14 + +#define REP8_01 0x0101010101010101 +#define REP8_7f 0x7f7f7f7f7f7f7f7f +#define REP8_80 0x8080808080808080 + + .text + .p2align 6 +.Lstart: + /* Pre-pad to ensure critical loop begins an icache line. */ + .rep 7 + nop + .endr + /* Put this code here to avoid wasting more space with pre-padding. */ +.Lhit_limit: + mov len, limit + ret + +ENTRY(strnlen) + cbz limit, .Lhit_limit + mov zeroones, #REP8_01 + bic src, srcin, #15 + ands tmp1, srcin, #15 + b.ne .Lmisaligned + /* Calculate the number of full and partial words -1. */ + sub limit_wd, limit, #1 /* Limit != 0, so no underflow. */ + lsr limit_wd, limit_wd, #4 /* Convert to Qwords. */ + + /* NUL detection works on the principle that (X - 1) & (~X) & 0x80 + (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and + can be done in parallel across the entire word. */ + /* The inner loop deals with two Dwords at a time. This has a + slightly higher start-up cost, but we should win quite quickly, + especially on cores with a high number of issue slots per + cycle, as we get much better parallelism out of the operations. */ + + /* Start of critial section -- keep to one 64Byte cache line. */ +.Lloop: + ldp data1, data2, [src], #16 +.Lrealigned: + sub tmp1, data1, zeroones + orr tmp2, data1, #REP8_7f + sub tmp3, data2, zeroones + orr tmp4, data2, #REP8_7f + bic has_nul1, tmp1, tmp2 + bic has_nul2, tmp3, tmp4 + subs limit_wd, limit_wd, #1 + orr tmp1, has_nul1, has_nul2 + ccmp tmp1, #0, #0, pl /* NZCV = 0000 */ + b.eq .Lloop + /* End of critical section -- keep to one 64Byte cache line. */ + + orr tmp1, has_nul1, has_nul2 + cbz tmp1, .Lhit_limit /* No null in final Qword. */ + + /* We know there's a null in the final Qword. The easiest thing + to do now is work out the length of the string and return + MIN (len, limit). */ + + sub len, src, srcin + cbz has_nul1, .Lnul_in_data2 +#ifdef __AARCH64EB__ + mov data2, data1 +#endif + sub len, len, #8 + mov has_nul2, has_nul1 +.Lnul_in_data2: +#ifdef __AARCH64EB__ + /* For big-endian, carry propagation (if the final byte in the + string is 0x01) means we cannot use has_nul directly. The + easiest way to get the correct byte is to byte-swap the data + and calculate the syndrome a second time. */ + rev data2, data2 + sub tmp1, data2, zeroones + orr tmp2, data2, #REP8_7f + bic has_nul2, tmp1, tmp2 +#endif + sub len, len, #8 + rev has_nul2, has_nul2 + clz pos, has_nul2 + add len, len, pos, lsr #3 /* Bits to bytes. */ + cmp len, limit + csel len, len, limit, ls /* Return the lower value. */ + ret + +.Lmisaligned: + /* Deal with a partial first word. + We're doing two things in parallel here; + 1) Calculate the number of words (but avoiding overflow if + limit is near ULONG_MAX) - to do this we need to work out + limit + tmp1 - 1 as a 65-bit value before shifting it; + 2) Load and mask the initial data words - we force the bytes + before the ones we are interested in to 0xff - this ensures + early bytes will not hit any zero detection. */ + sub limit_wd, limit, #1 + neg tmp4, tmp1 + cmp tmp1, #8 + + and tmp3, limit_wd, #15 + lsr limit_wd, limit_wd, #4 + mov tmp2, #~0 + + ldp data1, data2, [src], #16 + lsl tmp4, tmp4, #3 /* Bytes beyond alignment -> bits. */ + add tmp3, tmp3, tmp1 + +#ifdef __AARCH64EB__ + /* Big-endian. Early bytes are at MSB. */ + lsl tmp2, tmp2, tmp4 /* Shift (tmp1 & 63). */ +#else + /* Little-endian. Early bytes are at LSB. */ + lsr tmp2, tmp2, tmp4 /* Shift (tmp1 & 63). */ +#endif + add limit_wd, limit_wd, tmp3, lsr #4 + + orr data1, data1, tmp2 + orr data2a, data2, tmp2 + + csinv data1, data1, xzr, le + csel data2, data2, data2a, le + b .Lrealigned +END(strnlen)
diff --git a/libc/arch-arm64/generic/bionic/wmemmove.S b/libc/arch-arm64/generic/bionic/wmemmove.S new file mode 100644 index 0000000..e4f67f7 --- /dev/null +++ b/libc/arch-arm64/generic/bionic/wmemmove.S
@@ -0,0 +1,30 @@ +/* Copyright (c) 2014, Linaro Limited + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Linaro nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define WMEMMOVE +#include "memmove.S" +#undef WMEMMOVE
diff --git a/libc/arch-arm64/include/machine/asm.h b/libc/arch-arm64/include/machine/asm.h new file mode 100644 index 0000000..2bea043 --- /dev/null +++ b/libc/arch-arm64/include/machine/asm.h
@@ -0,0 +1,46 @@ +/* $OpenBSD: asm.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */ +/* $NetBSD: asm.h,v 1.4 2001/07/16 05:43:32 matt Exp $ */ + +/* + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)asm.h 5.5 (Berkeley) 5/7/91 + */ + +#ifndef _AARCH64_ASM_H_ +#define _AARCH64_ASM_H_ + +#define __bionic_asm_align 0 + +#undef __bionic_asm_function_type +#define __bionic_asm_function_type %function + +#endif /* _AARCH64_ASM_H_ */
diff --git a/libc/arch-arm64/include/machine/elf_machdep.h b/libc/arch-arm64/include/machine/elf_machdep.h new file mode 100644 index 0000000..6eab313 --- /dev/null +++ b/libc/arch-arm64/include/machine/elf_machdep.h
@@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _AARCH64_ELF_MACHDEP_H_ +#define _AARCH64_ELF_MACHDEP_H_ + +#if defined(__AARCH64EB__) +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#else +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB +#endif + +#define ELF64_MACHDEP_ID_CASES \ + case EM_AARCH64: \ + break; + +#define ELF64_MACHDEP_ID EM_AARCH64 + +#define ARCH_ELFSIZE 64 /* MD native binary size */ + +/* Null relocations */ +#define R_ARM_NONE 0 +#define R_AARCH64_NONE 256 + +/* Static Data relocations */ +#define R_AARCH64_ABS64 257 +#define R_AARCH64_ABS32 258 +#define R_AARCH64_ABS16 259 +#define R_AARCH64_PREL64 260 +#define R_AARCH64_PREL32 261 +#define R_AARCH64_PREL16 262 + +#define R_AARCH64_MOVW_UABS_G0 263 +#define R_AARCH64_MOVW_UABS_G0_NC 264 +#define R_AARCH64_MOVW_UABS_G1 265 +#define R_AARCH64_MOVW_UABS_G1_NC 266 +#define R_AARCH64_MOVW_UABS_G2 267 +#define R_AARCH64_MOVW_UABS_G2_NC 268 +#define R_AARCH64_MOVW_UABS_G3 269 +#define R_AARCH64_MOVW_SABS_G0 270 +#define R_AARCH64_MOVW_SABS_G1 271 +#define R_AARCH64_MOVW_SABS_G2 272 + +/* PC-relative addresses */ +#define R_AARCH64_LD_PREL_LO19 273 +#define R_AARCH64_ADR_PREL_LO21 274 +#define R_AARCH64_ADR_PREL_PG_HI21 275 +#define R_AARCH64_ADR_PREL_PG_HI21_NC 276 +#define R_AARCH64_ADD_ABS_LO12_NC 277 +#define R_AARCH64_LDST8_ABS_LO12_NC 278 + +/* Control-flow relocations */ +#define R_AARCH64_TSTBR14 279 +#define R_AARCH64_CONDBR19 280 +#define R_AARCH64_JUMP26 282 +#define R_AARCH64_CALL26 283 +#define R_AARCH64_LDST16_ABS_LO12_NC 284 +#define R_AARCH64_LDST32_ABS_LO12_NC 285 +#define R_AARCH64_LDST64_ABS_LO12_NC 286 +#define R_AARCH64_LDST128_ABS_LO12_NC 299 + +#define R_AARCH64_MOVW_PREL_G0 287 +#define R_AARCH64_MOVW_PREL_G0_NC 288 +#define R_AARCH64_MOVW_PREL_G1 289 +#define R_AARCH64_MOVW_PREL_G1_NC 290 +#define R_AARCH64_MOVW_PREL_G2 291 +#define R_AARCH64_MOVW_PREL_G2_NC 292 +#define R_AARCH64_MOVW_PREL_G3 293 + +/* Dynamic relocations */ +#define R_AARCH64_COPY 1024 +#define R_AARCH64_GLOB_DAT 1025 /* Create GOT entry. */ +#define R_AARCH64_JUMP_SLOT 1026 /* Create PLT entry. */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */ +#define R_AARCH64_TLS_TPREL64 1030 +#define R_AARCH64_TLS_DTPREL32 1031 +#define R_AARCH64_IRELATIVE 1032 + +#define R_TYPE(name) __CONCAT(R_AARCH64_,name) + +#endif /* _AARCH64_ELF_MACHDEP_H_ */
diff --git a/libc/arch-arm64/include/machine/fenv.h b/libc/arch-arm64/include/machine/fenv.h new file mode 100644 index 0000000..a8568b8 --- /dev/null +++ b/libc/arch-arm64/include/machine/fenv.h
@@ -0,0 +1,102 @@ +/*- + * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ + */ + +/* + * In ARMv8, AArch64 state, floating-point operation is controlled by: + * + * * FPCR - 32Bit Floating-Point Control Register: + * * [31:27] - Reserved, Res0; + * * [26] - AHP, Alternative half-precision control bit; + * * [25] - DN, Default NaN mode control bit; + * * [24] - FZ, Flush-to-zero mode control bit; + * * [23:22] - RMode, Rounding Mode control field: + * * 00 - Round to Nearest (RN) mode; + * * 01 - Round towards Plus Infinity (RP) mode; + * * 10 - Round towards Minus Infinity (RM) mode; + * * 11 - Round towards Zero (RZ) mode. + * * [21:20] - Stride, ignored during AArch64 execution; + * * [19] - Reserved, Res0; + * * [18:16] - Len, ignored during AArch64 execution; + * * [15] - IDE, Input Denormal exception trap; + * * [14:13] - Reserved, Res0; + * * [12] - IXE, Inexact exception trap; + * * [11] - UFE, Underflow exception trap; + * * [10] - OFE, Overflow exception trap; + * * [9] - DZE, Division by Zero exception; + * * [8] - IOE, Invalid Operation exception; + * * [7:0] - Reserved, Res0. + * + * * FPSR - 32Bit Floating-Point Status Register: + * * [31] - N, Negative condition flag for AArch32 (AArch64 sets PSTATE.N); + * * [30] - Z, Zero condition flag for AArch32 (AArch64 sets PSTATE.Z); + * * [29] - C, Carry conditon flag for AArch32 (AArch64 sets PSTATE.C); + * * [28] - V, Overflow conditon flag for AArch32 (AArch64 sets PSTATE.V); + * * [27] - QC, Cumulative saturation bit, Advanced SIMD only; + * * [26:8] - Reserved, Res0; + * * [7] - IDC, Input Denormal cumulative exception; + * * [6:5] - Reserved, Res0; + * * [4] - IXC, Inexact cumulative exception; + * * [3] - UFC, Underflow cumulative exception; + * * [2] - OFC, Overflow cumulative exception; + * * [1] - DZC, Division by Zero cumulative exception; + * * [0] - IOC, Invalid Operation cumulative exception. + */ + +#ifndef _ARM64_FENV_H_ +#define _ARM64_FENV_H_ + +#include <sys/types.h> + +__BEGIN_DECLS + +typedef struct { + __uint32_t __control; /* FPCR, Floating-point Control Register */ + __uint32_t __status; /* FPSR, Floating-point Status Register */ +} fenv_t; + +typedef __uint32_t fexcept_t; + +/* Exception flags. */ +#define FE_INVALID 0x01 +#define FE_DIVBYZERO 0x02 +#define FE_OVERFLOW 0x04 +#define FE_UNDERFLOW 0x08 +#define FE_INEXACT 0x10 +#define FE_DENORMAL 0x80 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ + FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL) + +/* Rounding modes. */ +#define FE_TONEAREST 0x0 +#define FE_UPWARD 0x1 +#define FE_DOWNWARD 0x2 +#define FE_TOWARDZERO 0x3 + +__END_DECLS + +#endif /* !_ARM64_FENV_H_ */
diff --git a/libc/arch-arm64/include/machine/setjmp.h b/libc/arch-arm64/include/machine/setjmp.h new file mode 100644 index 0000000..27c2fe5 --- /dev/null +++ b/libc/arch-arm64/include/machine/setjmp.h
@@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* _JBLEN is the size of a jmp_buf in longs (64bit on AArch64) */ +#define _JBLEN 32
diff --git a/libc/arch-arm64/syscalls/___clock_nanosleep.S b/libc/arch-arm64/syscalls/___clock_nanosleep.S new file mode 100644 index 0000000..0dcfd4f --- /dev/null +++ b/libc/arch-arm64/syscalls/___clock_nanosleep.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___clock_nanosleep) + mov x8, __NR_clock_nanosleep + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___clock_nanosleep) +.hidden ___clock_nanosleep
diff --git a/libc/arch-arm64/syscalls/___close.S b/libc/arch-arm64/syscalls/___close.S new file mode 100644 index 0000000..8fb8361 --- /dev/null +++ b/libc/arch-arm64/syscalls/___close.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___close) + mov x8, __NR_close + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___close) +.hidden ___close
diff --git a/libc/arch-arm64/syscalls/___faccessat.S b/libc/arch-arm64/syscalls/___faccessat.S new file mode 100644 index 0000000..6a41b69 --- /dev/null +++ b/libc/arch-arm64/syscalls/___faccessat.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___faccessat) + mov x8, __NR_faccessat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___faccessat) +.hidden ___faccessat
diff --git a/libc/arch-arm64/syscalls/___fchmod.S b/libc/arch-arm64/syscalls/___fchmod.S new file mode 100644 index 0000000..a143c65 --- /dev/null +++ b/libc/arch-arm64/syscalls/___fchmod.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmod) + mov x8, __NR_fchmod + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___fchmod) +.hidden ___fchmod
diff --git a/libc/arch-arm64/syscalls/___fchmodat.S b/libc/arch-arm64/syscalls/___fchmodat.S new file mode 100644 index 0000000..1ab3736 --- /dev/null +++ b/libc/arch-arm64/syscalls/___fchmodat.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmodat) + mov x8, __NR_fchmodat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___fchmodat) +.hidden ___fchmodat
diff --git a/libc/arch-arm64/syscalls/___fgetxattr.S b/libc/arch-arm64/syscalls/___fgetxattr.S new file mode 100644 index 0000000..c0334cc --- /dev/null +++ b/libc/arch-arm64/syscalls/___fgetxattr.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fgetxattr) + mov x8, __NR_fgetxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___fgetxattr) +.hidden ___fgetxattr
diff --git a/libc/arch-arm64/syscalls/___flistxattr.S b/libc/arch-arm64/syscalls/___flistxattr.S new file mode 100644 index 0000000..02c8478 --- /dev/null +++ b/libc/arch-arm64/syscalls/___flistxattr.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___flistxattr) + mov x8, __NR_flistxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___flistxattr) +.hidden ___flistxattr
diff --git a/libc/arch-arm64/syscalls/___fsetxattr.S b/libc/arch-arm64/syscalls/___fsetxattr.S new file mode 100644 index 0000000..92be8de --- /dev/null +++ b/libc/arch-arm64/syscalls/___fsetxattr.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fsetxattr) + mov x8, __NR_fsetxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___fsetxattr) +.hidden ___fsetxattr
diff --git a/libc/arch-arm64/syscalls/___mremap.S b/libc/arch-arm64/syscalls/___mremap.S new file mode 100644 index 0000000..aeb93bc --- /dev/null +++ b/libc/arch-arm64/syscalls/___mremap.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___mremap) + mov x8, __NR_mremap + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___mremap) +.hidden ___mremap
diff --git a/libc/arch-arm64/syscalls/___rt_sigqueueinfo.S b/libc/arch-arm64/syscalls/___rt_sigqueueinfo.S new file mode 100644 index 0000000..85ea132 --- /dev/null +++ b/libc/arch-arm64/syscalls/___rt_sigqueueinfo.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___rt_sigqueueinfo) + mov x8, __NR_rt_sigqueueinfo + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(___rt_sigqueueinfo) +.hidden ___rt_sigqueueinfo
diff --git a/libc/arch-arm64/syscalls/__accept4.S b/libc/arch-arm64/syscalls/__accept4.S new file mode 100644 index 0000000..559e6a7 --- /dev/null +++ b/libc/arch-arm64/syscalls/__accept4.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + mov x8, __NR_accept4 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__accept4) +.hidden __accept4
diff --git a/libc/arch-arm64/syscalls/__brk.S b/libc/arch-arm64/syscalls/__brk.S new file mode 100644 index 0000000..fb794bf --- /dev/null +++ b/libc/arch-arm64/syscalls/__brk.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + mov x8, __NR_brk + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__brk) +.hidden __brk
diff --git a/libc/arch-arm64/syscalls/__clock_gettime.S b/libc/arch-arm64/syscalls/__clock_gettime.S new file mode 100644 index 0000000..658ab29 --- /dev/null +++ b/libc/arch-arm64/syscalls/__clock_gettime.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__clock_gettime) + mov x8, __NR_clock_gettime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__clock_gettime) +.hidden __clock_gettime
diff --git a/libc/arch-arm64/syscalls/__connect.S b/libc/arch-arm64/syscalls/__connect.S new file mode 100644 index 0000000..c18e6eb --- /dev/null +++ b/libc/arch-arm64/syscalls/__connect.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + mov x8, __NR_connect + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__connect) +.hidden __connect
diff --git a/libc/arch-arm64/syscalls/__epoll_pwait.S b/libc/arch-arm64/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..acf2bbf --- /dev/null +++ b/libc/arch-arm64/syscalls/__epoll_pwait.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + mov x8, __NR_epoll_pwait + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__epoll_pwait) +.hidden __epoll_pwait
diff --git a/libc/arch-arm64/syscalls/__exit.S b/libc/arch-arm64/syscalls/__exit.S new file mode 100644 index 0000000..b6b1866 --- /dev/null +++ b/libc/arch-arm64/syscalls/__exit.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + mov x8, __NR_exit + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__exit) +.hidden __exit
diff --git a/libc/arch-arm64/syscalls/__fadvise64.S b/libc/arch-arm64/syscalls/__fadvise64.S new file mode 100644 index 0000000..695d094 --- /dev/null +++ b/libc/arch-arm64/syscalls/__fadvise64.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fadvise64) + mov x8, __NR_fadvise64 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__fadvise64) +.hidden __fadvise64
diff --git a/libc/arch-arm64/syscalls/__fstatfs.S b/libc/arch-arm64/syscalls/__fstatfs.S new file mode 100644 index 0000000..7e350d6 --- /dev/null +++ b/libc/arch-arm64/syscalls/__fstatfs.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fstatfs) + mov x8, __NR_fstatfs + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__fstatfs) +.hidden __fstatfs
diff --git a/libc/arch-arm64/syscalls/__getcpu.S b/libc/arch-arm64/syscalls/__getcpu.S new file mode 100644 index 0000000..11ed68e --- /dev/null +++ b/libc/arch-arm64/syscalls/__getcpu.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + mov x8, __NR_getcpu + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__getcpu) +.hidden __getcpu
diff --git a/libc/arch-arm64/syscalls/__getcwd.S b/libc/arch-arm64/syscalls/__getcwd.S new file mode 100644 index 0000000..c64f4d2 --- /dev/null +++ b/libc/arch-arm64/syscalls/__getcwd.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + mov x8, __NR_getcwd + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__getcwd) +.hidden __getcwd
diff --git a/libc/arch-arm64/syscalls/__getdents64.S b/libc/arch-arm64/syscalls/__getdents64.S new file mode 100644 index 0000000..9943390 --- /dev/null +++ b/libc/arch-arm64/syscalls/__getdents64.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + mov x8, __NR_getdents64 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__getdents64) +.hidden __getdents64
diff --git a/libc/arch-arm64/syscalls/__getpid.S b/libc/arch-arm64/syscalls/__getpid.S new file mode 100644 index 0000000..fbc96df --- /dev/null +++ b/libc/arch-arm64/syscalls/__getpid.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + mov x8, __NR_getpid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__getpid) +.hidden __getpid
diff --git a/libc/arch-arm64/syscalls/__getpriority.S b/libc/arch-arm64/syscalls/__getpriority.S new file mode 100644 index 0000000..9d98e22 --- /dev/null +++ b/libc/arch-arm64/syscalls/__getpriority.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + mov x8, __NR_getpriority + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__getpriority) +.hidden __getpriority
diff --git a/libc/arch-arm64/syscalls/__gettimeofday.S b/libc/arch-arm64/syscalls/__gettimeofday.S new file mode 100644 index 0000000..0c8206a --- /dev/null +++ b/libc/arch-arm64/syscalls/__gettimeofday.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__gettimeofday) + mov x8, __NR_gettimeofday + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__gettimeofday) +.hidden __gettimeofday
diff --git a/libc/arch-arm64/syscalls/__ioctl.S b/libc/arch-arm64/syscalls/__ioctl.S new file mode 100644 index 0000000..62bc28c --- /dev/null +++ b/libc/arch-arm64/syscalls/__ioctl.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + mov x8, __NR_ioctl + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__ioctl) +.hidden __ioctl
diff --git a/libc/arch-arm64/syscalls/__openat.S b/libc/arch-arm64/syscalls/__openat.S new file mode 100644 index 0000000..8b6853f --- /dev/null +++ b/libc/arch-arm64/syscalls/__openat.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + mov x8, __NR_openat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__openat) +.hidden __openat
diff --git a/libc/arch-arm64/syscalls/__ppoll.S b/libc/arch-arm64/syscalls/__ppoll.S new file mode 100644 index 0000000..1f54d67 --- /dev/null +++ b/libc/arch-arm64/syscalls/__ppoll.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + mov x8, __NR_ppoll + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__ppoll) +.hidden __ppoll
diff --git a/libc/arch-arm64/syscalls/__pselect6.S b/libc/arch-arm64/syscalls/__pselect6.S new file mode 100644 index 0000000..388d84e --- /dev/null +++ b/libc/arch-arm64/syscalls/__pselect6.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + mov x8, __NR_pselect6 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__pselect6) +.hidden __pselect6
diff --git a/libc/arch-arm64/syscalls/__ptrace.S b/libc/arch-arm64/syscalls/__ptrace.S new file mode 100644 index 0000000..d68b674 --- /dev/null +++ b/libc/arch-arm64/syscalls/__ptrace.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + mov x8, __NR_ptrace + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__ptrace) +.hidden __ptrace
diff --git a/libc/arch-arm64/syscalls/__reboot.S b/libc/arch-arm64/syscalls/__reboot.S new file mode 100644 index 0000000..79cd5be --- /dev/null +++ b/libc/arch-arm64/syscalls/__reboot.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + mov x8, __NR_reboot + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__reboot) +.hidden __reboot
diff --git a/libc/arch-arm64/syscalls/__rt_sigaction.S b/libc/arch-arm64/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..65fea2e --- /dev/null +++ b/libc/arch-arm64/syscalls/__rt_sigaction.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + mov x8, __NR_rt_sigaction + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__rt_sigaction) +.hidden __rt_sigaction
diff --git a/libc/arch-arm64/syscalls/__rt_sigpending.S b/libc/arch-arm64/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..6553781 --- /dev/null +++ b/libc/arch-arm64/syscalls/__rt_sigpending.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + mov x8, __NR_rt_sigpending + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__rt_sigpending) +.hidden __rt_sigpending
diff --git a/libc/arch-arm64/syscalls/__rt_sigprocmask.S b/libc/arch-arm64/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..95127d6 --- /dev/null +++ b/libc/arch-arm64/syscalls/__rt_sigprocmask.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + mov x8, __NR_rt_sigprocmask + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__rt_sigprocmask) +.hidden __rt_sigprocmask
diff --git a/libc/arch-arm64/syscalls/__rt_sigsuspend.S b/libc/arch-arm64/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..7cbd8d6 --- /dev/null +++ b/libc/arch-arm64/syscalls/__rt_sigsuspend.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + mov x8, __NR_rt_sigsuspend + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__rt_sigsuspend) +.hidden __rt_sigsuspend
diff --git a/libc/arch-arm64/syscalls/__rt_sigtimedwait.S b/libc/arch-arm64/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..8001635 --- /dev/null +++ b/libc/arch-arm64/syscalls/__rt_sigtimedwait.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + mov x8, __NR_rt_sigtimedwait + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__rt_sigtimedwait) +.hidden __rt_sigtimedwait
diff --git a/libc/arch-arm64/syscalls/__sched_getaffinity.S b/libc/arch-arm64/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..7dad15e --- /dev/null +++ b/libc/arch-arm64/syscalls/__sched_getaffinity.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + mov x8, __NR_sched_getaffinity + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__sched_getaffinity) +.hidden __sched_getaffinity
diff --git a/libc/arch-arm64/syscalls/__set_tid_address.S b/libc/arch-arm64/syscalls/__set_tid_address.S new file mode 100644 index 0000000..f7ae16d --- /dev/null +++ b/libc/arch-arm64/syscalls/__set_tid_address.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + mov x8, __NR_set_tid_address + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__set_tid_address) +.hidden __set_tid_address
diff --git a/libc/arch-arm64/syscalls/__signalfd4.S b/libc/arch-arm64/syscalls/__signalfd4.S new file mode 100644 index 0000000..f6e3497 --- /dev/null +++ b/libc/arch-arm64/syscalls/__signalfd4.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + mov x8, __NR_signalfd4 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__signalfd4) +.hidden __signalfd4
diff --git a/libc/arch-arm64/syscalls/__socket.S b/libc/arch-arm64/syscalls/__socket.S new file mode 100644 index 0000000..344bb2d --- /dev/null +++ b/libc/arch-arm64/syscalls/__socket.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + mov x8, __NR_socket + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__socket) +.hidden __socket
diff --git a/libc/arch-arm64/syscalls/__statfs.S b/libc/arch-arm64/syscalls/__statfs.S new file mode 100644 index 0000000..962c590 --- /dev/null +++ b/libc/arch-arm64/syscalls/__statfs.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__statfs) + mov x8, __NR_statfs + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__statfs) +.hidden __statfs
diff --git a/libc/arch-arm64/syscalls/__sync_file_range.S b/libc/arch-arm64/syscalls/__sync_file_range.S new file mode 100644 index 0000000..776e900 --- /dev/null +++ b/libc/arch-arm64/syscalls/__sync_file_range.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sync_file_range) + mov x8, __NR_sync_file_range + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__sync_file_range) +.hidden __sync_file_range
diff --git a/libc/arch-arm64/syscalls/__timer_create.S b/libc/arch-arm64/syscalls/__timer_create.S new file mode 100644 index 0000000..4790845 --- /dev/null +++ b/libc/arch-arm64/syscalls/__timer_create.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + mov x8, __NR_timer_create + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__timer_create) +.hidden __timer_create
diff --git a/libc/arch-arm64/syscalls/__timer_delete.S b/libc/arch-arm64/syscalls/__timer_delete.S new file mode 100644 index 0000000..ce12613 --- /dev/null +++ b/libc/arch-arm64/syscalls/__timer_delete.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + mov x8, __NR_timer_delete + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__timer_delete) +.hidden __timer_delete
diff --git a/libc/arch-arm64/syscalls/__timer_getoverrun.S b/libc/arch-arm64/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..2cfdf6a --- /dev/null +++ b/libc/arch-arm64/syscalls/__timer_getoverrun.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + mov x8, __NR_timer_getoverrun + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__timer_getoverrun) +.hidden __timer_getoverrun
diff --git a/libc/arch-arm64/syscalls/__timer_gettime.S b/libc/arch-arm64/syscalls/__timer_gettime.S new file mode 100644 index 0000000..a1ea323 --- /dev/null +++ b/libc/arch-arm64/syscalls/__timer_gettime.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + mov x8, __NR_timer_gettime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__timer_gettime) +.hidden __timer_gettime
diff --git a/libc/arch-arm64/syscalls/__timer_settime.S b/libc/arch-arm64/syscalls/__timer_settime.S new file mode 100644 index 0000000..059d705 --- /dev/null +++ b/libc/arch-arm64/syscalls/__timer_settime.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + mov x8, __NR_timer_settime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__timer_settime) +.hidden __timer_settime
diff --git a/libc/arch-arm64/syscalls/__waitid.S b/libc/arch-arm64/syscalls/__waitid.S new file mode 100644 index 0000000..8bd649d --- /dev/null +++ b/libc/arch-arm64/syscalls/__waitid.S
@@ -0,0 +1,15 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + mov x8, __NR_waitid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(__waitid) +.hidden __waitid
diff --git a/libc/arch-arm64/syscalls/_exit.S b/libc/arch-arm64/syscalls/_exit.S new file mode 100644 index 0000000..d50f38d --- /dev/null +++ b/libc/arch-arm64/syscalls/_exit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + mov x8, __NR_exit_group + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(_exit) + +ALIAS_SYMBOL(_Exit, _exit)
diff --git a/libc/arch-arm64/syscalls/acct.S b/libc/arch-arm64/syscalls/acct.S new file mode 100644 index 0000000..48cb4e9 --- /dev/null +++ b/libc/arch-arm64/syscalls/acct.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + mov x8, __NR_acct + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(acct)
diff --git a/libc/arch-arm64/syscalls/adjtimex.S b/libc/arch-arm64/syscalls/adjtimex.S new file mode 100644 index 0000000..712e468 --- /dev/null +++ b/libc/arch-arm64/syscalls/adjtimex.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(adjtimex) + mov x8, __NR_adjtimex + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(adjtimex)
diff --git a/libc/arch-arm64/syscalls/bind.S b/libc/arch-arm64/syscalls/bind.S new file mode 100644 index 0000000..47170ff --- /dev/null +++ b/libc/arch-arm64/syscalls/bind.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + mov x8, __NR_bind + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(bind)
diff --git a/libc/arch-arm64/syscalls/capget.S b/libc/arch-arm64/syscalls/capget.S new file mode 100644 index 0000000..7e0dfe9 --- /dev/null +++ b/libc/arch-arm64/syscalls/capget.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + mov x8, __NR_capget + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(capget)
diff --git a/libc/arch-arm64/syscalls/capset.S b/libc/arch-arm64/syscalls/capset.S new file mode 100644 index 0000000..e7b7a8d --- /dev/null +++ b/libc/arch-arm64/syscalls/capset.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + mov x8, __NR_capset + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(capset)
diff --git a/libc/arch-arm64/syscalls/chdir.S b/libc/arch-arm64/syscalls/chdir.S new file mode 100644 index 0000000..723cd08 --- /dev/null +++ b/libc/arch-arm64/syscalls/chdir.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + mov x8, __NR_chdir + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(chdir)
diff --git a/libc/arch-arm64/syscalls/chroot.S b/libc/arch-arm64/syscalls/chroot.S new file mode 100644 index 0000000..e4f6bd9 --- /dev/null +++ b/libc/arch-arm64/syscalls/chroot.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + mov x8, __NR_chroot + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(chroot)
diff --git a/libc/arch-arm64/syscalls/clock_adjtime.S b/libc/arch-arm64/syscalls/clock_adjtime.S new file mode 100644 index 0000000..c2c191e --- /dev/null +++ b/libc/arch-arm64/syscalls/clock_adjtime.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_adjtime) + mov x8, __NR_clock_adjtime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(clock_adjtime)
diff --git a/libc/arch-arm64/syscalls/clock_getres.S b/libc/arch-arm64/syscalls/clock_getres.S new file mode 100644 index 0000000..33fda8f --- /dev/null +++ b/libc/arch-arm64/syscalls/clock_getres.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + mov x8, __NR_clock_getres + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(clock_getres)
diff --git a/libc/arch-arm64/syscalls/clock_settime.S b/libc/arch-arm64/syscalls/clock_settime.S new file mode 100644 index 0000000..62354d1 --- /dev/null +++ b/libc/arch-arm64/syscalls/clock_settime.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + mov x8, __NR_clock_settime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(clock_settime)
diff --git a/libc/arch-arm64/syscalls/delete_module.S b/libc/arch-arm64/syscalls/delete_module.S new file mode 100644 index 0000000..db8d947 --- /dev/null +++ b/libc/arch-arm64/syscalls/delete_module.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + mov x8, __NR_delete_module + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(delete_module)
diff --git a/libc/arch-arm64/syscalls/dup.S b/libc/arch-arm64/syscalls/dup.S new file mode 100644 index 0000000..4e95045 --- /dev/null +++ b/libc/arch-arm64/syscalls/dup.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + mov x8, __NR_dup + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(dup)
diff --git a/libc/arch-arm64/syscalls/dup3.S b/libc/arch-arm64/syscalls/dup3.S new file mode 100644 index 0000000..2e6be32 --- /dev/null +++ b/libc/arch-arm64/syscalls/dup3.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + mov x8, __NR_dup3 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(dup3)
diff --git a/libc/arch-arm64/syscalls/epoll_create1.S b/libc/arch-arm64/syscalls/epoll_create1.S new file mode 100644 index 0000000..6ef518e --- /dev/null +++ b/libc/arch-arm64/syscalls/epoll_create1.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + mov x8, __NR_epoll_create1 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(epoll_create1)
diff --git a/libc/arch-arm64/syscalls/epoll_ctl.S b/libc/arch-arm64/syscalls/epoll_ctl.S new file mode 100644 index 0000000..1188f38 --- /dev/null +++ b/libc/arch-arm64/syscalls/epoll_ctl.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + mov x8, __NR_epoll_ctl + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(epoll_ctl)
diff --git a/libc/arch-arm64/syscalls/eventfd.S b/libc/arch-arm64/syscalls/eventfd.S new file mode 100644 index 0000000..ca5df12 --- /dev/null +++ b/libc/arch-arm64/syscalls/eventfd.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + mov x8, __NR_eventfd2 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(eventfd)
diff --git a/libc/arch-arm64/syscalls/execve.S b/libc/arch-arm64/syscalls/execve.S new file mode 100644 index 0000000..fc8fb68 --- /dev/null +++ b/libc/arch-arm64/syscalls/execve.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + mov x8, __NR_execve + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(execve)
diff --git a/libc/arch-arm64/syscalls/fallocate.S b/libc/arch-arm64/syscalls/fallocate.S new file mode 100644 index 0000000..d42a0ba --- /dev/null +++ b/libc/arch-arm64/syscalls/fallocate.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate) + mov x8, __NR_fallocate + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fallocate) + +ALIAS_SYMBOL(fallocate64, fallocate)
diff --git a/libc/arch-arm64/syscalls/fchdir.S b/libc/arch-arm64/syscalls/fchdir.S new file mode 100644 index 0000000..2e164cb --- /dev/null +++ b/libc/arch-arm64/syscalls/fchdir.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + mov x8, __NR_fchdir + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fchdir)
diff --git a/libc/arch-arm64/syscalls/fchown.S b/libc/arch-arm64/syscalls/fchown.S new file mode 100644 index 0000000..4456f1b --- /dev/null +++ b/libc/arch-arm64/syscalls/fchown.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + mov x8, __NR_fchown + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fchown)
diff --git a/libc/arch-arm64/syscalls/fchownat.S b/libc/arch-arm64/syscalls/fchownat.S new file mode 100644 index 0000000..7ba6611 --- /dev/null +++ b/libc/arch-arm64/syscalls/fchownat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + mov x8, __NR_fchownat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fchownat)
diff --git a/libc/arch-arm64/syscalls/fcntl.S b/libc/arch-arm64/syscalls/fcntl.S new file mode 100644 index 0000000..e2787ae --- /dev/null +++ b/libc/arch-arm64/syscalls/fcntl.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fcntl) + mov x8, __NR_fcntl + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fcntl)
diff --git a/libc/arch-arm64/syscalls/fdatasync.S b/libc/arch-arm64/syscalls/fdatasync.S new file mode 100644 index 0000000..225ab29 --- /dev/null +++ b/libc/arch-arm64/syscalls/fdatasync.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + mov x8, __NR_fdatasync + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fdatasync)
diff --git a/libc/arch-arm64/syscalls/flock.S b/libc/arch-arm64/syscalls/flock.S new file mode 100644 index 0000000..0c036c8 --- /dev/null +++ b/libc/arch-arm64/syscalls/flock.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + mov x8, __NR_flock + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(flock)
diff --git a/libc/arch-arm64/syscalls/fremovexattr.S b/libc/arch-arm64/syscalls/fremovexattr.S new file mode 100644 index 0000000..cf3a371 --- /dev/null +++ b/libc/arch-arm64/syscalls/fremovexattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + mov x8, __NR_fremovexattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fremovexattr)
diff --git a/libc/arch-arm64/syscalls/fstat64.S b/libc/arch-arm64/syscalls/fstat64.S new file mode 100644 index 0000000..f7c9f54 --- /dev/null +++ b/libc/arch-arm64/syscalls/fstat64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstat64) + mov x8, __NR_fstat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fstat64) + +ALIAS_SYMBOL(fstat, fstat64)
diff --git a/libc/arch-arm64/syscalls/fstatat64.S b/libc/arch-arm64/syscalls/fstatat64.S new file mode 100644 index 0000000..9f8f2c5 --- /dev/null +++ b/libc/arch-arm64/syscalls/fstatat64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatat64) + mov x8, __NR_newfstatat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fstatat64) + +ALIAS_SYMBOL(fstatat, fstatat64)
diff --git a/libc/arch-arm64/syscalls/fsync.S b/libc/arch-arm64/syscalls/fsync.S new file mode 100644 index 0000000..2bc0d0b --- /dev/null +++ b/libc/arch-arm64/syscalls/fsync.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + mov x8, __NR_fsync + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(fsync)
diff --git a/libc/arch-arm64/syscalls/ftruncate.S b/libc/arch-arm64/syscalls/ftruncate.S new file mode 100644 index 0000000..c21e098 --- /dev/null +++ b/libc/arch-arm64/syscalls/ftruncate.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate) + mov x8, __NR_ftruncate + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(ftruncate) + +ALIAS_SYMBOL(ftruncate64, ftruncate)
diff --git a/libc/arch-arm64/syscalls/getegid.S b/libc/arch-arm64/syscalls/getegid.S new file mode 100644 index 0000000..f7d60d9 --- /dev/null +++ b/libc/arch-arm64/syscalls/getegid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + mov x8, __NR_getegid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getegid)
diff --git a/libc/arch-arm64/syscalls/geteuid.S b/libc/arch-arm64/syscalls/geteuid.S new file mode 100644 index 0000000..3096a92 --- /dev/null +++ b/libc/arch-arm64/syscalls/geteuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + mov x8, __NR_geteuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(geteuid)
diff --git a/libc/arch-arm64/syscalls/getgid.S b/libc/arch-arm64/syscalls/getgid.S new file mode 100644 index 0000000..2f921ff --- /dev/null +++ b/libc/arch-arm64/syscalls/getgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + mov x8, __NR_getgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getgid)
diff --git a/libc/arch-arm64/syscalls/getgroups.S b/libc/arch-arm64/syscalls/getgroups.S new file mode 100644 index 0000000..a9a897e --- /dev/null +++ b/libc/arch-arm64/syscalls/getgroups.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + mov x8, __NR_getgroups + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getgroups)
diff --git a/libc/arch-arm64/syscalls/getitimer.S b/libc/arch-arm64/syscalls/getitimer.S new file mode 100644 index 0000000..f37063c --- /dev/null +++ b/libc/arch-arm64/syscalls/getitimer.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + mov x8, __NR_getitimer + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getitimer)
diff --git a/libc/arch-arm64/syscalls/getpeername.S b/libc/arch-arm64/syscalls/getpeername.S new file mode 100644 index 0000000..8374d60 --- /dev/null +++ b/libc/arch-arm64/syscalls/getpeername.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + mov x8, __NR_getpeername + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getpeername)
diff --git a/libc/arch-arm64/syscalls/getpgid.S b/libc/arch-arm64/syscalls/getpgid.S new file mode 100644 index 0000000..ffc0d91 --- /dev/null +++ b/libc/arch-arm64/syscalls/getpgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + mov x8, __NR_getpgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getpgid)
diff --git a/libc/arch-arm64/syscalls/getppid.S b/libc/arch-arm64/syscalls/getppid.S new file mode 100644 index 0000000..1e21bdf --- /dev/null +++ b/libc/arch-arm64/syscalls/getppid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + mov x8, __NR_getppid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getppid)
diff --git a/libc/arch-arm64/syscalls/getresgid.S b/libc/arch-arm64/syscalls/getresgid.S new file mode 100644 index 0000000..b15357a --- /dev/null +++ b/libc/arch-arm64/syscalls/getresgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + mov x8, __NR_getresgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getresgid)
diff --git a/libc/arch-arm64/syscalls/getresuid.S b/libc/arch-arm64/syscalls/getresuid.S new file mode 100644 index 0000000..53de6b7 --- /dev/null +++ b/libc/arch-arm64/syscalls/getresuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + mov x8, __NR_getresuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getresuid)
diff --git a/libc/arch-arm64/syscalls/getrlimit.S b/libc/arch-arm64/syscalls/getrlimit.S new file mode 100644 index 0000000..03ee9a8 --- /dev/null +++ b/libc/arch-arm64/syscalls/getrlimit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + mov x8, __NR_getrlimit + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getrlimit) + +ALIAS_SYMBOL(getrlimit64, getrlimit)
diff --git a/libc/arch-arm64/syscalls/getrusage.S b/libc/arch-arm64/syscalls/getrusage.S new file mode 100644 index 0000000..676221a --- /dev/null +++ b/libc/arch-arm64/syscalls/getrusage.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + mov x8, __NR_getrusage + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getrusage)
diff --git a/libc/arch-arm64/syscalls/getsid.S b/libc/arch-arm64/syscalls/getsid.S new file mode 100644 index 0000000..cfbdfdb --- /dev/null +++ b/libc/arch-arm64/syscalls/getsid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + mov x8, __NR_getsid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getsid)
diff --git a/libc/arch-arm64/syscalls/getsockname.S b/libc/arch-arm64/syscalls/getsockname.S new file mode 100644 index 0000000..4cca55d --- /dev/null +++ b/libc/arch-arm64/syscalls/getsockname.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + mov x8, __NR_getsockname + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getsockname)
diff --git a/libc/arch-arm64/syscalls/getsockopt.S b/libc/arch-arm64/syscalls/getsockopt.S new file mode 100644 index 0000000..96b8c0f --- /dev/null +++ b/libc/arch-arm64/syscalls/getsockopt.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + mov x8, __NR_getsockopt + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getsockopt)
diff --git a/libc/arch-arm64/syscalls/getuid.S b/libc/arch-arm64/syscalls/getuid.S new file mode 100644 index 0000000..ef95ba7 --- /dev/null +++ b/libc/arch-arm64/syscalls/getuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + mov x8, __NR_getuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getuid)
diff --git a/libc/arch-arm64/syscalls/getxattr.S b/libc/arch-arm64/syscalls/getxattr.S new file mode 100644 index 0000000..2b38f3d --- /dev/null +++ b/libc/arch-arm64/syscalls/getxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + mov x8, __NR_getxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(getxattr)
diff --git a/libc/arch-arm64/syscalls/init_module.S b/libc/arch-arm64/syscalls/init_module.S new file mode 100644 index 0000000..913c7cc --- /dev/null +++ b/libc/arch-arm64/syscalls/init_module.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + mov x8, __NR_init_module + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(init_module)
diff --git a/libc/arch-arm64/syscalls/inotify_add_watch.S b/libc/arch-arm64/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..83a5b57 --- /dev/null +++ b/libc/arch-arm64/syscalls/inotify_add_watch.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + mov x8, __NR_inotify_add_watch + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(inotify_add_watch)
diff --git a/libc/arch-arm64/syscalls/inotify_init1.S b/libc/arch-arm64/syscalls/inotify_init1.S new file mode 100644 index 0000000..d3bc81b --- /dev/null +++ b/libc/arch-arm64/syscalls/inotify_init1.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + mov x8, __NR_inotify_init1 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(inotify_init1)
diff --git a/libc/arch-arm64/syscalls/inotify_rm_watch.S b/libc/arch-arm64/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..c44445f --- /dev/null +++ b/libc/arch-arm64/syscalls/inotify_rm_watch.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + mov x8, __NR_inotify_rm_watch + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(inotify_rm_watch)
diff --git a/libc/arch-arm64/syscalls/kill.S b/libc/arch-arm64/syscalls/kill.S new file mode 100644 index 0000000..0334ff0 --- /dev/null +++ b/libc/arch-arm64/syscalls/kill.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + mov x8, __NR_kill + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(kill)
diff --git a/libc/arch-arm64/syscalls/klogctl.S b/libc/arch-arm64/syscalls/klogctl.S new file mode 100644 index 0000000..625f359 --- /dev/null +++ b/libc/arch-arm64/syscalls/klogctl.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + mov x8, __NR_syslog + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(klogctl)
diff --git a/libc/arch-arm64/syscalls/lgetxattr.S b/libc/arch-arm64/syscalls/lgetxattr.S new file mode 100644 index 0000000..89db206 --- /dev/null +++ b/libc/arch-arm64/syscalls/lgetxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + mov x8, __NR_lgetxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(lgetxattr)
diff --git a/libc/arch-arm64/syscalls/linkat.S b/libc/arch-arm64/syscalls/linkat.S new file mode 100644 index 0000000..62aea3a --- /dev/null +++ b/libc/arch-arm64/syscalls/linkat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + mov x8, __NR_linkat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(linkat)
diff --git a/libc/arch-arm64/syscalls/listen.S b/libc/arch-arm64/syscalls/listen.S new file mode 100644 index 0000000..ba97be9 --- /dev/null +++ b/libc/arch-arm64/syscalls/listen.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + mov x8, __NR_listen + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(listen)
diff --git a/libc/arch-arm64/syscalls/listxattr.S b/libc/arch-arm64/syscalls/listxattr.S new file mode 100644 index 0000000..48208e6 --- /dev/null +++ b/libc/arch-arm64/syscalls/listxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + mov x8, __NR_listxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(listxattr)
diff --git a/libc/arch-arm64/syscalls/llistxattr.S b/libc/arch-arm64/syscalls/llistxattr.S new file mode 100644 index 0000000..ed66005 --- /dev/null +++ b/libc/arch-arm64/syscalls/llistxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + mov x8, __NR_llistxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(llistxattr)
diff --git a/libc/arch-arm64/syscalls/lremovexattr.S b/libc/arch-arm64/syscalls/lremovexattr.S new file mode 100644 index 0000000..b5e51c7 --- /dev/null +++ b/libc/arch-arm64/syscalls/lremovexattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + mov x8, __NR_lremovexattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(lremovexattr)
diff --git a/libc/arch-arm64/syscalls/lseek.S b/libc/arch-arm64/syscalls/lseek.S new file mode 100644 index 0000000..93afeb7 --- /dev/null +++ b/libc/arch-arm64/syscalls/lseek.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + mov x8, __NR_lseek + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(lseek) + +ALIAS_SYMBOL(lseek64, lseek)
diff --git a/libc/arch-arm64/syscalls/lsetxattr.S b/libc/arch-arm64/syscalls/lsetxattr.S new file mode 100644 index 0000000..b873513 --- /dev/null +++ b/libc/arch-arm64/syscalls/lsetxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + mov x8, __NR_lsetxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(lsetxattr)
diff --git a/libc/arch-arm64/syscalls/madvise.S b/libc/arch-arm64/syscalls/madvise.S new file mode 100644 index 0000000..6fced41 --- /dev/null +++ b/libc/arch-arm64/syscalls/madvise.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + mov x8, __NR_madvise + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(madvise)
diff --git a/libc/arch-arm64/syscalls/mincore.S b/libc/arch-arm64/syscalls/mincore.S new file mode 100644 index 0000000..5781b4c --- /dev/null +++ b/libc/arch-arm64/syscalls/mincore.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + mov x8, __NR_mincore + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mincore)
diff --git a/libc/arch-arm64/syscalls/mkdirat.S b/libc/arch-arm64/syscalls/mkdirat.S new file mode 100644 index 0000000..fa868a2 --- /dev/null +++ b/libc/arch-arm64/syscalls/mkdirat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + mov x8, __NR_mkdirat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mkdirat)
diff --git a/libc/arch-arm64/syscalls/mknodat.S b/libc/arch-arm64/syscalls/mknodat.S new file mode 100644 index 0000000..13632ec --- /dev/null +++ b/libc/arch-arm64/syscalls/mknodat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + mov x8, __NR_mknodat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mknodat)
diff --git a/libc/arch-arm64/syscalls/mlock.S b/libc/arch-arm64/syscalls/mlock.S new file mode 100644 index 0000000..1eee85c --- /dev/null +++ b/libc/arch-arm64/syscalls/mlock.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + mov x8, __NR_mlock + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mlock)
diff --git a/libc/arch-arm64/syscalls/mlockall.S b/libc/arch-arm64/syscalls/mlockall.S new file mode 100644 index 0000000..d4ca185 --- /dev/null +++ b/libc/arch-arm64/syscalls/mlockall.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + mov x8, __NR_mlockall + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mlockall)
diff --git a/libc/arch-arm64/syscalls/mmap.S b/libc/arch-arm64/syscalls/mmap.S new file mode 100644 index 0000000..65371bc --- /dev/null +++ b/libc/arch-arm64/syscalls/mmap.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mmap) + mov x8, __NR_mmap + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mmap) + +ALIAS_SYMBOL(mmap64, mmap)
diff --git a/libc/arch-arm64/syscalls/mount.S b/libc/arch-arm64/syscalls/mount.S new file mode 100644 index 0000000..cd35017 --- /dev/null +++ b/libc/arch-arm64/syscalls/mount.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + mov x8, __NR_mount + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mount)
diff --git a/libc/arch-arm64/syscalls/mprotect.S b/libc/arch-arm64/syscalls/mprotect.S new file mode 100644 index 0000000..9dd8812 --- /dev/null +++ b/libc/arch-arm64/syscalls/mprotect.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + mov x8, __NR_mprotect + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(mprotect)
diff --git a/libc/arch-arm64/syscalls/msync.S b/libc/arch-arm64/syscalls/msync.S new file mode 100644 index 0000000..72387ea --- /dev/null +++ b/libc/arch-arm64/syscalls/msync.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + mov x8, __NR_msync + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(msync)
diff --git a/libc/arch-arm64/syscalls/munlock.S b/libc/arch-arm64/syscalls/munlock.S new file mode 100644 index 0000000..d2a248c --- /dev/null +++ b/libc/arch-arm64/syscalls/munlock.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + mov x8, __NR_munlock + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(munlock)
diff --git a/libc/arch-arm64/syscalls/munlockall.S b/libc/arch-arm64/syscalls/munlockall.S new file mode 100644 index 0000000..ac42cb4 --- /dev/null +++ b/libc/arch-arm64/syscalls/munlockall.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + mov x8, __NR_munlockall + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(munlockall)
diff --git a/libc/arch-arm64/syscalls/munmap.S b/libc/arch-arm64/syscalls/munmap.S new file mode 100644 index 0000000..9d3f6a6 --- /dev/null +++ b/libc/arch-arm64/syscalls/munmap.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + mov x8, __NR_munmap + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(munmap)
diff --git a/libc/arch-arm64/syscalls/nanosleep.S b/libc/arch-arm64/syscalls/nanosleep.S new file mode 100644 index 0000000..d3e6fae --- /dev/null +++ b/libc/arch-arm64/syscalls/nanosleep.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + mov x8, __NR_nanosleep + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(nanosleep)
diff --git a/libc/arch-arm64/syscalls/personality.S b/libc/arch-arm64/syscalls/personality.S new file mode 100644 index 0000000..f9f3bf6 --- /dev/null +++ b/libc/arch-arm64/syscalls/personality.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + mov x8, __NR_personality + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(personality)
diff --git a/libc/arch-arm64/syscalls/pipe2.S b/libc/arch-arm64/syscalls/pipe2.S new file mode 100644 index 0000000..89181cd --- /dev/null +++ b/libc/arch-arm64/syscalls/pipe2.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + mov x8, __NR_pipe2 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(pipe2)
diff --git a/libc/arch-arm64/syscalls/prctl.S b/libc/arch-arm64/syscalls/prctl.S new file mode 100644 index 0000000..86f4df5 --- /dev/null +++ b/libc/arch-arm64/syscalls/prctl.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + mov x8, __NR_prctl + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(prctl)
diff --git a/libc/arch-arm64/syscalls/pread64.S b/libc/arch-arm64/syscalls/pread64.S new file mode 100644 index 0000000..6c9f0e9 --- /dev/null +++ b/libc/arch-arm64/syscalls/pread64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + mov x8, __NR_pread64 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(pread64) + +ALIAS_SYMBOL(pread, pread64)
diff --git a/libc/arch-arm64/syscalls/preadv.S b/libc/arch-arm64/syscalls/preadv.S new file mode 100644 index 0000000..cb8300d --- /dev/null +++ b/libc/arch-arm64/syscalls/preadv.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(preadv) + mov x8, __NR_preadv + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(preadv) + +ALIAS_SYMBOL(preadv64, preadv)
diff --git a/libc/arch-arm64/syscalls/prlimit64.S b/libc/arch-arm64/syscalls/prlimit64.S new file mode 100644 index 0000000..9c018ba --- /dev/null +++ b/libc/arch-arm64/syscalls/prlimit64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + mov x8, __NR_prlimit64 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(prlimit64) + +ALIAS_SYMBOL(prlimit, prlimit64)
diff --git a/libc/arch-arm64/syscalls/process_vm_readv.S b/libc/arch-arm64/syscalls/process_vm_readv.S new file mode 100644 index 0000000..1dd113b --- /dev/null +++ b/libc/arch-arm64/syscalls/process_vm_readv.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_readv) + mov x8, __NR_process_vm_readv + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(process_vm_readv)
diff --git a/libc/arch-arm64/syscalls/process_vm_writev.S b/libc/arch-arm64/syscalls/process_vm_writev.S new file mode 100644 index 0000000..fb29cf8 --- /dev/null +++ b/libc/arch-arm64/syscalls/process_vm_writev.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_writev) + mov x8, __NR_process_vm_writev + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(process_vm_writev)
diff --git a/libc/arch-arm64/syscalls/pwrite64.S b/libc/arch-arm64/syscalls/pwrite64.S new file mode 100644 index 0000000..1599c14 --- /dev/null +++ b/libc/arch-arm64/syscalls/pwrite64.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + mov x8, __NR_pwrite64 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(pwrite64) + +ALIAS_SYMBOL(pwrite, pwrite64)
diff --git a/libc/arch-arm64/syscalls/pwritev.S b/libc/arch-arm64/syscalls/pwritev.S new file mode 100644 index 0000000..621466a --- /dev/null +++ b/libc/arch-arm64/syscalls/pwritev.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwritev) + mov x8, __NR_pwritev + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(pwritev) + +ALIAS_SYMBOL(pwritev64, pwritev)
diff --git a/libc/arch-arm64/syscalls/quotactl.S b/libc/arch-arm64/syscalls/quotactl.S new file mode 100644 index 0000000..b67d47e --- /dev/null +++ b/libc/arch-arm64/syscalls/quotactl.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(quotactl) + mov x8, __NR_quotactl + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(quotactl)
diff --git a/libc/arch-arm64/syscalls/read.S b/libc/arch-arm64/syscalls/read.S new file mode 100644 index 0000000..ddb88c8 --- /dev/null +++ b/libc/arch-arm64/syscalls/read.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + mov x8, __NR_read + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(read)
diff --git a/libc/arch-arm64/syscalls/readahead.S b/libc/arch-arm64/syscalls/readahead.S new file mode 100644 index 0000000..445abd4 --- /dev/null +++ b/libc/arch-arm64/syscalls/readahead.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + mov x8, __NR_readahead + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(readahead)
diff --git a/libc/arch-arm64/syscalls/readlinkat.S b/libc/arch-arm64/syscalls/readlinkat.S new file mode 100644 index 0000000..62cc9e2 --- /dev/null +++ b/libc/arch-arm64/syscalls/readlinkat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + mov x8, __NR_readlinkat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(readlinkat)
diff --git a/libc/arch-arm64/syscalls/readv.S b/libc/arch-arm64/syscalls/readv.S new file mode 100644 index 0000000..6e7f151 --- /dev/null +++ b/libc/arch-arm64/syscalls/readv.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + mov x8, __NR_readv + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(readv)
diff --git a/libc/arch-arm64/syscalls/recvfrom.S b/libc/arch-arm64/syscalls/recvfrom.S new file mode 100644 index 0000000..aecf165 --- /dev/null +++ b/libc/arch-arm64/syscalls/recvfrom.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + mov x8, __NR_recvfrom + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(recvfrom)
diff --git a/libc/arch-arm64/syscalls/recvmmsg.S b/libc/arch-arm64/syscalls/recvmmsg.S new file mode 100644 index 0000000..b9cae69 --- /dev/null +++ b/libc/arch-arm64/syscalls/recvmmsg.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + mov x8, __NR_recvmmsg + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(recvmmsg)
diff --git a/libc/arch-arm64/syscalls/recvmsg.S b/libc/arch-arm64/syscalls/recvmsg.S new file mode 100644 index 0000000..2dafdc9 --- /dev/null +++ b/libc/arch-arm64/syscalls/recvmsg.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + mov x8, __NR_recvmsg + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(recvmsg)
diff --git a/libc/arch-arm64/syscalls/removexattr.S b/libc/arch-arm64/syscalls/removexattr.S new file mode 100644 index 0000000..ede36a6 --- /dev/null +++ b/libc/arch-arm64/syscalls/removexattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + mov x8, __NR_removexattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(removexattr)
diff --git a/libc/arch-arm64/syscalls/renameat.S b/libc/arch-arm64/syscalls/renameat.S new file mode 100644 index 0000000..96025df --- /dev/null +++ b/libc/arch-arm64/syscalls/renameat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + mov x8, __NR_renameat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(renameat)
diff --git a/libc/arch-arm64/syscalls/sched_get_priority_max.S b/libc/arch-arm64/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..c848889 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_get_priority_max.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + mov x8, __NR_sched_get_priority_max + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_get_priority_max)
diff --git a/libc/arch-arm64/syscalls/sched_get_priority_min.S b/libc/arch-arm64/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..74b72a2 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_get_priority_min.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + mov x8, __NR_sched_get_priority_min + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_get_priority_min)
diff --git a/libc/arch-arm64/syscalls/sched_getparam.S b/libc/arch-arm64/syscalls/sched_getparam.S new file mode 100644 index 0000000..75a32d4 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_getparam.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + mov x8, __NR_sched_getparam + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_getparam)
diff --git a/libc/arch-arm64/syscalls/sched_getscheduler.S b/libc/arch-arm64/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..e24baf2 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_getscheduler.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + mov x8, __NR_sched_getscheduler + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_getscheduler)
diff --git a/libc/arch-arm64/syscalls/sched_rr_get_interval.S b/libc/arch-arm64/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..2a6936b --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_rr_get_interval.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + mov x8, __NR_sched_rr_get_interval + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_rr_get_interval)
diff --git a/libc/arch-arm64/syscalls/sched_setaffinity.S b/libc/arch-arm64/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..30b58f6 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_setaffinity.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + mov x8, __NR_sched_setaffinity + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_setaffinity)
diff --git a/libc/arch-arm64/syscalls/sched_setparam.S b/libc/arch-arm64/syscalls/sched_setparam.S new file mode 100644 index 0000000..eaf25ba --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_setparam.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + mov x8, __NR_sched_setparam + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_setparam)
diff --git a/libc/arch-arm64/syscalls/sched_setscheduler.S b/libc/arch-arm64/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..31d53c4 --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_setscheduler.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + mov x8, __NR_sched_setscheduler + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_setscheduler)
diff --git a/libc/arch-arm64/syscalls/sched_yield.S b/libc/arch-arm64/syscalls/sched_yield.S new file mode 100644 index 0000000..4cfeeda --- /dev/null +++ b/libc/arch-arm64/syscalls/sched_yield.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + mov x8, __NR_sched_yield + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sched_yield)
diff --git a/libc/arch-arm64/syscalls/sendfile.S b/libc/arch-arm64/syscalls/sendfile.S new file mode 100644 index 0000000..50ac12d --- /dev/null +++ b/libc/arch-arm64/syscalls/sendfile.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + mov x8, __NR_sendfile + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sendfile) + +ALIAS_SYMBOL(sendfile64, sendfile)
diff --git a/libc/arch-arm64/syscalls/sendmmsg.S b/libc/arch-arm64/syscalls/sendmmsg.S new file mode 100644 index 0000000..e91c246 --- /dev/null +++ b/libc/arch-arm64/syscalls/sendmmsg.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + mov x8, __NR_sendmmsg + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sendmmsg)
diff --git a/libc/arch-arm64/syscalls/sendmsg.S b/libc/arch-arm64/syscalls/sendmsg.S new file mode 100644 index 0000000..a343543 --- /dev/null +++ b/libc/arch-arm64/syscalls/sendmsg.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + mov x8, __NR_sendmsg + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sendmsg)
diff --git a/libc/arch-arm64/syscalls/sendto.S b/libc/arch-arm64/syscalls/sendto.S new file mode 100644 index 0000000..6a6813e --- /dev/null +++ b/libc/arch-arm64/syscalls/sendto.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + mov x8, __NR_sendto + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sendto)
diff --git a/libc/arch-arm64/syscalls/setdomainname.S b/libc/arch-arm64/syscalls/setdomainname.S new file mode 100644 index 0000000..18f8d4b --- /dev/null +++ b/libc/arch-arm64/syscalls/setdomainname.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setdomainname) + mov x8, __NR_setdomainname + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setdomainname)
diff --git a/libc/arch-arm64/syscalls/setfsgid.S b/libc/arch-arm64/syscalls/setfsgid.S new file mode 100644 index 0000000..1a45df3 --- /dev/null +++ b/libc/arch-arm64/syscalls/setfsgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + mov x8, __NR_setfsgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setfsgid)
diff --git a/libc/arch-arm64/syscalls/setfsuid.S b/libc/arch-arm64/syscalls/setfsuid.S new file mode 100644 index 0000000..cd4efd7 --- /dev/null +++ b/libc/arch-arm64/syscalls/setfsuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + mov x8, __NR_setfsuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setfsuid)
diff --git a/libc/arch-arm64/syscalls/setgid.S b/libc/arch-arm64/syscalls/setgid.S new file mode 100644 index 0000000..c128fb9 --- /dev/null +++ b/libc/arch-arm64/syscalls/setgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + mov x8, __NR_setgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setgid)
diff --git a/libc/arch-arm64/syscalls/setgroups.S b/libc/arch-arm64/syscalls/setgroups.S new file mode 100644 index 0000000..aedabd6 --- /dev/null +++ b/libc/arch-arm64/syscalls/setgroups.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + mov x8, __NR_setgroups + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setgroups)
diff --git a/libc/arch-arm64/syscalls/sethostname.S b/libc/arch-arm64/syscalls/sethostname.S new file mode 100644 index 0000000..2dea457 --- /dev/null +++ b/libc/arch-arm64/syscalls/sethostname.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sethostname) + mov x8, __NR_sethostname + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sethostname)
diff --git a/libc/arch-arm64/syscalls/setitimer.S b/libc/arch-arm64/syscalls/setitimer.S new file mode 100644 index 0000000..7ce8617 --- /dev/null +++ b/libc/arch-arm64/syscalls/setitimer.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + mov x8, __NR_setitimer + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setitimer)
diff --git a/libc/arch-arm64/syscalls/setns.S b/libc/arch-arm64/syscalls/setns.S new file mode 100644 index 0000000..386e8f4 --- /dev/null +++ b/libc/arch-arm64/syscalls/setns.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + mov x8, __NR_setns + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setns)
diff --git a/libc/arch-arm64/syscalls/setpgid.S b/libc/arch-arm64/syscalls/setpgid.S new file mode 100644 index 0000000..458c88b --- /dev/null +++ b/libc/arch-arm64/syscalls/setpgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + mov x8, __NR_setpgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setpgid)
diff --git a/libc/arch-arm64/syscalls/setpriority.S b/libc/arch-arm64/syscalls/setpriority.S new file mode 100644 index 0000000..ed58f26 --- /dev/null +++ b/libc/arch-arm64/syscalls/setpriority.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + mov x8, __NR_setpriority + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setpriority)
diff --git a/libc/arch-arm64/syscalls/setregid.S b/libc/arch-arm64/syscalls/setregid.S new file mode 100644 index 0000000..30d902d --- /dev/null +++ b/libc/arch-arm64/syscalls/setregid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + mov x8, __NR_setregid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setregid)
diff --git a/libc/arch-arm64/syscalls/setresgid.S b/libc/arch-arm64/syscalls/setresgid.S new file mode 100644 index 0000000..f56e6ce --- /dev/null +++ b/libc/arch-arm64/syscalls/setresgid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + mov x8, __NR_setresgid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setresgid)
diff --git a/libc/arch-arm64/syscalls/setresuid.S b/libc/arch-arm64/syscalls/setresuid.S new file mode 100644 index 0000000..d5c5cc6 --- /dev/null +++ b/libc/arch-arm64/syscalls/setresuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + mov x8, __NR_setresuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setresuid)
diff --git a/libc/arch-arm64/syscalls/setreuid.S b/libc/arch-arm64/syscalls/setreuid.S new file mode 100644 index 0000000..e76c72e --- /dev/null +++ b/libc/arch-arm64/syscalls/setreuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + mov x8, __NR_setreuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setreuid)
diff --git a/libc/arch-arm64/syscalls/setrlimit.S b/libc/arch-arm64/syscalls/setrlimit.S new file mode 100644 index 0000000..52c75a1 --- /dev/null +++ b/libc/arch-arm64/syscalls/setrlimit.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + mov x8, __NR_setrlimit + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setrlimit) + +ALIAS_SYMBOL(setrlimit64, setrlimit)
diff --git a/libc/arch-arm64/syscalls/setsid.S b/libc/arch-arm64/syscalls/setsid.S new file mode 100644 index 0000000..1bb4cc7 --- /dev/null +++ b/libc/arch-arm64/syscalls/setsid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + mov x8, __NR_setsid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setsid)
diff --git a/libc/arch-arm64/syscalls/setsockopt.S b/libc/arch-arm64/syscalls/setsockopt.S new file mode 100644 index 0000000..14b0136 --- /dev/null +++ b/libc/arch-arm64/syscalls/setsockopt.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + mov x8, __NR_setsockopt + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setsockopt)
diff --git a/libc/arch-arm64/syscalls/settimeofday.S b/libc/arch-arm64/syscalls/settimeofday.S new file mode 100644 index 0000000..4f0a078 --- /dev/null +++ b/libc/arch-arm64/syscalls/settimeofday.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + mov x8, __NR_settimeofday + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(settimeofday)
diff --git a/libc/arch-arm64/syscalls/setuid.S b/libc/arch-arm64/syscalls/setuid.S new file mode 100644 index 0000000..5500dd6 --- /dev/null +++ b/libc/arch-arm64/syscalls/setuid.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + mov x8, __NR_setuid + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setuid)
diff --git a/libc/arch-arm64/syscalls/setxattr.S b/libc/arch-arm64/syscalls/setxattr.S new file mode 100644 index 0000000..5ba9e3c --- /dev/null +++ b/libc/arch-arm64/syscalls/setxattr.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + mov x8, __NR_setxattr + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(setxattr)
diff --git a/libc/arch-arm64/syscalls/shutdown.S b/libc/arch-arm64/syscalls/shutdown.S new file mode 100644 index 0000000..ab067fa --- /dev/null +++ b/libc/arch-arm64/syscalls/shutdown.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + mov x8, __NR_shutdown + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(shutdown)
diff --git a/libc/arch-arm64/syscalls/sigaltstack.S b/libc/arch-arm64/syscalls/sigaltstack.S new file mode 100644 index 0000000..a9cbcaf --- /dev/null +++ b/libc/arch-arm64/syscalls/sigaltstack.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + mov x8, __NR_sigaltstack + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sigaltstack)
diff --git a/libc/arch-arm64/syscalls/socketpair.S b/libc/arch-arm64/syscalls/socketpair.S new file mode 100644 index 0000000..bd70dac --- /dev/null +++ b/libc/arch-arm64/syscalls/socketpair.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + mov x8, __NR_socketpair + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(socketpair)
diff --git a/libc/arch-arm64/syscalls/splice.S b/libc/arch-arm64/syscalls/splice.S new file mode 100644 index 0000000..a5450d9 --- /dev/null +++ b/libc/arch-arm64/syscalls/splice.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + mov x8, __NR_splice + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(splice)
diff --git a/libc/arch-arm64/syscalls/swapoff.S b/libc/arch-arm64/syscalls/swapoff.S new file mode 100644 index 0000000..0103bd7 --- /dev/null +++ b/libc/arch-arm64/syscalls/swapoff.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + mov x8, __NR_swapoff + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(swapoff)
diff --git a/libc/arch-arm64/syscalls/swapon.S b/libc/arch-arm64/syscalls/swapon.S new file mode 100644 index 0000000..560c960 --- /dev/null +++ b/libc/arch-arm64/syscalls/swapon.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + mov x8, __NR_swapon + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(swapon)
diff --git a/libc/arch-arm64/syscalls/symlinkat.S b/libc/arch-arm64/syscalls/symlinkat.S new file mode 100644 index 0000000..4a4ea27 --- /dev/null +++ b/libc/arch-arm64/syscalls/symlinkat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + mov x8, __NR_symlinkat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(symlinkat)
diff --git a/libc/arch-arm64/syscalls/sync.S b/libc/arch-arm64/syscalls/sync.S new file mode 100644 index 0000000..d285d43 --- /dev/null +++ b/libc/arch-arm64/syscalls/sync.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sync) + mov x8, __NR_sync + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sync)
diff --git a/libc/arch-arm64/syscalls/sysinfo.S b/libc/arch-arm64/syscalls/sysinfo.S new file mode 100644 index 0000000..80a8641 --- /dev/null +++ b/libc/arch-arm64/syscalls/sysinfo.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sysinfo) + mov x8, __NR_sysinfo + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(sysinfo)
diff --git a/libc/arch-arm64/syscalls/tee.S b/libc/arch-arm64/syscalls/tee.S new file mode 100644 index 0000000..d7baa26 --- /dev/null +++ b/libc/arch-arm64/syscalls/tee.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tee) + mov x8, __NR_tee + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(tee)
diff --git a/libc/arch-arm64/syscalls/tgkill.S b/libc/arch-arm64/syscalls/tgkill.S new file mode 100644 index 0000000..fd9ec3b --- /dev/null +++ b/libc/arch-arm64/syscalls/tgkill.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tgkill) + mov x8, __NR_tgkill + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(tgkill)
diff --git a/libc/arch-arm64/syscalls/timerfd_create.S b/libc/arch-arm64/syscalls/timerfd_create.S new file mode 100644 index 0000000..ee805fd --- /dev/null +++ b/libc/arch-arm64/syscalls/timerfd_create.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_create) + mov x8, __NR_timerfd_create + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(timerfd_create)
diff --git a/libc/arch-arm64/syscalls/timerfd_gettime.S b/libc/arch-arm64/syscalls/timerfd_gettime.S new file mode 100644 index 0000000..4d5e2f9 --- /dev/null +++ b/libc/arch-arm64/syscalls/timerfd_gettime.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_gettime) + mov x8, __NR_timerfd_gettime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(timerfd_gettime)
diff --git a/libc/arch-arm64/syscalls/timerfd_settime.S b/libc/arch-arm64/syscalls/timerfd_settime.S new file mode 100644 index 0000000..e925a0c --- /dev/null +++ b/libc/arch-arm64/syscalls/timerfd_settime.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_settime) + mov x8, __NR_timerfd_settime + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(timerfd_settime)
diff --git a/libc/arch-arm64/syscalls/times.S b/libc/arch-arm64/syscalls/times.S new file mode 100644 index 0000000..d7b9c74 --- /dev/null +++ b/libc/arch-arm64/syscalls/times.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(times) + mov x8, __NR_times + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(times)
diff --git a/libc/arch-arm64/syscalls/truncate.S b/libc/arch-arm64/syscalls/truncate.S new file mode 100644 index 0000000..e01cc7d --- /dev/null +++ b/libc/arch-arm64/syscalls/truncate.S
@@ -0,0 +1,16 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate) + mov x8, __NR_truncate + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(truncate) + +ALIAS_SYMBOL(truncate64, truncate)
diff --git a/libc/arch-arm64/syscalls/umask.S b/libc/arch-arm64/syscalls/umask.S new file mode 100644 index 0000000..0d71fa6 --- /dev/null +++ b/libc/arch-arm64/syscalls/umask.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umask) + mov x8, __NR_umask + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(umask)
diff --git a/libc/arch-arm64/syscalls/umount2.S b/libc/arch-arm64/syscalls/umount2.S new file mode 100644 index 0000000..c25344e --- /dev/null +++ b/libc/arch-arm64/syscalls/umount2.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umount2) + mov x8, __NR_umount2 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(umount2)
diff --git a/libc/arch-arm64/syscalls/uname.S b/libc/arch-arm64/syscalls/uname.S new file mode 100644 index 0000000..dfdcc03 --- /dev/null +++ b/libc/arch-arm64/syscalls/uname.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(uname) + mov x8, __NR_uname + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(uname)
diff --git a/libc/arch-arm64/syscalls/unlinkat.S b/libc/arch-arm64/syscalls/unlinkat.S new file mode 100644 index 0000000..b1eba63 --- /dev/null +++ b/libc/arch-arm64/syscalls/unlinkat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unlinkat) + mov x8, __NR_unlinkat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(unlinkat)
diff --git a/libc/arch-arm64/syscalls/unshare.S b/libc/arch-arm64/syscalls/unshare.S new file mode 100644 index 0000000..74f5663 --- /dev/null +++ b/libc/arch-arm64/syscalls/unshare.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unshare) + mov x8, __NR_unshare + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(unshare)
diff --git a/libc/arch-arm64/syscalls/utimensat.S b/libc/arch-arm64/syscalls/utimensat.S new file mode 100644 index 0000000..b8c6b04 --- /dev/null +++ b/libc/arch-arm64/syscalls/utimensat.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(utimensat) + mov x8, __NR_utimensat + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(utimensat)
diff --git a/libc/arch-arm64/syscalls/vmsplice.S b/libc/arch-arm64/syscalls/vmsplice.S new file mode 100644 index 0000000..9490efb --- /dev/null +++ b/libc/arch-arm64/syscalls/vmsplice.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(vmsplice) + mov x8, __NR_vmsplice + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(vmsplice)
diff --git a/libc/arch-arm64/syscalls/wait4.S b/libc/arch-arm64/syscalls/wait4.S new file mode 100644 index 0000000..12973b8 --- /dev/null +++ b/libc/arch-arm64/syscalls/wait4.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(wait4) + mov x8, __NR_wait4 + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(wait4)
diff --git a/libc/arch-arm64/syscalls/write.S b/libc/arch-arm64/syscalls/write.S new file mode 100644 index 0000000..e8c3270 --- /dev/null +++ b/libc/arch-arm64/syscalls/write.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(write) + mov x8, __NR_write + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(write)
diff --git a/libc/arch-arm64/syscalls/writev.S b/libc/arch-arm64/syscalls/writev.S new file mode 100644 index 0000000..baaffda --- /dev/null +++ b/libc/arch-arm64/syscalls/writev.S
@@ -0,0 +1,14 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(writev) + mov x8, __NR_writev + svc #0 + + cmn x0, #(MAX_ERRNO + 1) + cneg x0, x0, hi + b.hi __set_errno_internal + + ret +END(writev)
diff --git a/libc/arch-common/bionic/__dso_handle.h b/libc/arch-common/bionic/__dso_handle.h new file mode 100644 index 0000000..d4bff77 --- /dev/null +++ b/libc/arch-common/bionic/__dso_handle.h
@@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#ifndef CRT_LEGACY_WORKAROUND +__attribute__ ((visibility ("hidden"))) +#endif +#ifdef __aarch64__ +__attribute__ ((section (".data"))) +#else +__attribute__ ((section (".bss"))) +#endif +void *__dso_handle = (void *) 0;
diff --git a/libc/arch-common/bionic/__dso_handle_so.h b/libc/arch-common/bionic/__dso_handle_so.h new file mode 100644 index 0000000..fab328a --- /dev/null +++ b/libc/arch-common/bionic/__dso_handle_so.h
@@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +__attribute__ ((visibility ("hidden"))) +__attribute__ ((section (".data"))) +#ifdef __aarch64__ +void *__dso_handle = (void *) 0; +#else +void *__dso_handle = &__dso_handle; +#endif
diff --git a/libc/arch-common/bionic/asm_multiarch.h b/libc/arch-common/bionic/asm_multiarch.h new file mode 100644 index 0000000..91cb8af --- /dev/null +++ b/libc/arch-common/bionic/asm_multiarch.h
@@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef __LP64__ +# define ASM_PTR_SIZE(x) .quad x +# define ASM_ALIGN_TO_PTR_SIZE .balign 8 +#else +# define ASM_PTR_SIZE(x) .long x +# define ASM_ALIGN_TO_PTR_SIZE .balign 4 +#endif +
diff --git a/libc/arch-common/bionic/atexit.h b/libc/arch-common/bionic/atexit.h new file mode 100644 index 0000000..90aa030 --- /dev/null +++ b/libc/arch-common/bionic/atexit.h
@@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stddef.h> + +extern void* __dso_handle; + +extern int __cxa_atexit(void (*)(void*), void*, void*); + +__attribute__ ((visibility ("hidden"))) +void __atexit_handler_wrapper(void* func) { + if (func != NULL) { + (*(void (*)(void))func)(); + } +} + +__attribute__ ((visibility ("hidden"))) +int atexit(void (*func)(void)) { + return (__cxa_atexit(&__atexit_handler_wrapper, func, &__dso_handle)); +}
diff --git a/libc/arch-common/bionic/crtbegin.c b/libc/arch-common/bionic/crtbegin.c new file mode 100644 index 0000000..c46405c --- /dev/null +++ b/libc/arch-common/bionic/crtbegin.c
@@ -0,0 +1,65 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "../../bionic/libc_init_common.h" +#include <stddef.h> +#include <stdint.h> + +__attribute__ ((section (".preinit_array"))) +void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".init_array"))) +void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".fini_array"))) +void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1; + +__LIBC_HIDDEN__ +#ifdef __i386__ +__attribute__((force_align_arg_pointer)) +#endif +void _start() { + structors_array_t array; + array.preinit_array = &__PREINIT_ARRAY__; + array.init_array = &__INIT_ARRAY__; + array.fini_array = &__FINI_ARRAY__; + + void* raw_args = (void*) ((uintptr_t) __builtin_frame_address(0) + sizeof(void*)); +#ifdef __x86_64__ + // 16-byte stack alignment is required by x86_64 ABI + asm("andq $~15, %rsp"); +#endif + __libc_init(raw_args, NULL, &main, &array); +} + +#include "__dso_handle.h" +#include "atexit.h" +#include "pthread_atfork.h" +#ifdef __i386__ +# include "../../arch-x86/bionic/__stack_chk_fail_local.h" +#endif
diff --git a/libc/arch-common/bionic/crtbegin_so.c b/libc/arch-common/bionic/crtbegin_so.c new file mode 100644 index 0000000..3754363 --- /dev/null +++ b/libc/arch-common/bionic/crtbegin_so.c
@@ -0,0 +1,62 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern void __cxa_finalize(void *); +extern void *__dso_handle; + +__attribute__((visibility("hidden"),destructor)) +void __on_dlclose() { + __cxa_finalize(&__dso_handle); +} + +/* CRT_LEGACY_WORKAROUND should only be defined when building + * this file as part of the platform's C library. + * + * The C library already defines a function named 'atexit()' + * for backwards compatibility with older NDK-generated binaries. + * + * For newer ones, 'atexit' is actually embedded in the C + * runtime objects that are linked into the final ELF + * binary (shared library or executable), and will call + * __cxa_atexit() in order to un-register any atexit() + * handler when a library is unloaded. + * + * This function must be global *and* hidden. Only the + * code inside the same ELF binary should be able to access it. + */ + +#ifdef CRT_LEGACY_WORKAROUND +# include "__dso_handle.h" +#else +# include "__dso_handle_so.h" +# include "atexit.h" +#endif +#include "pthread_atfork.h" +#ifdef __i386__ +# include "../../arch-x86/bionic/__stack_chk_fail_local.h" +#endif
diff --git a/libc/arch-common/bionic/crtbrand.S b/libc/arch-common/bionic/crtbrand.S new file mode 100644 index 0000000..11bbfbe --- /dev/null +++ b/libc/arch-common/bionic/crtbrand.S
@@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .section .note.android.ident,"a",%note + .align 2 + .type abitag, %object +abitag: + .long 2f-1f /* int32_t namesz */ + .long 3f-2f /* int32_t descsz */ + .long 1 /* int32_t type */ +1: .ascii "Android\0" /* char name[] */ +2: .long PLATFORM_SDK_VERSION /* int32_t android_api */ +3: + .size abitag, .-abitag
diff --git a/libc/arch-common/bionic/crtend.S b/libc/arch-common/bionic/crtend.S new file mode 100644 index 0000000..87d1120 --- /dev/null +++ b/libc/arch-common/bionic/crtend.S
@@ -0,0 +1,55 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "asm_multiarch.h" + + .section .preinit_array, "aw" + ASM_ALIGN_TO_PTR_SIZE + ASM_PTR_SIZE(0) + + .section .init_array, "aw" + ASM_ALIGN_TO_PTR_SIZE + ASM_PTR_SIZE(0) + + .section .fini_array, "aw" + ASM_ALIGN_TO_PTR_SIZE + ASM_PTR_SIZE(0) + +#if defined(__linux__) && defined(__ELF__) + .section .note.GNU-stack,"",%progbits +#endif +#if defined(__i386__) || defined(__x86_64__) + .section .eh_frame,"a",@progbits +#if defined(__i386__) + .balign 4 +#endif + .type __FRAME_END__, @object + .size __FRAME_END__, 4 +__FRAME_END__: + .zero 4 +#endif
diff --git a/libc/arch-common/bionic/crtend_so.S b/libc/arch-common/bionic/crtend_so.S new file mode 100644 index 0000000..e7b8cac --- /dev/null +++ b/libc/arch-common/bionic/crtend_so.S
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if defined(__linux__) && defined(__ELF__) + .section .note.GNU-stack,"",%progbits +#endif +#if defined(__i386__) || defined(__x86_64__) + .section .eh_frame,"a",@progbits +#if defined(__i386__) + .balign 4 +#endif + .type __FRAME_END__, @object + .size __FRAME_END__, 4 +__FRAME_END__: + .zero 4 +#endif
diff --git a/libc/arch-common/bionic/pthread_atfork.h b/libc/arch-common/bionic/pthread_atfork.h new file mode 100644 index 0000000..0c48a12 --- /dev/null +++ b/libc/arch-common/bionic/pthread_atfork.h
@@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +extern void* __dso_handle; + +extern int __register_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void), void* dso); + +#ifndef _LIBC +// Libc used to export this in previous versions, therefore it needs +// to remain global for binary compatibility. +__attribute__ ((visibility ("hidden"))) +#endif +int pthread_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void)) { + return __register_atfork(prepare, parent, child, &__dso_handle); +} +
diff --git a/libc/arch-mips/bionic/__bionic_clone.S b/libc/arch-mips/bionic/__bionic_clone.S new file mode 100644 index 0000000..b216efe --- /dev/null +++ b/libc/arch-mips/bionic/__bionic_clone.S
@@ -0,0 +1,72 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/errno.h> +#include <linux/sched.h> + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); +ENTRY(__bionic_clone) + .set noreorder + .cpload t9 + .set reorder + + # set up child stack + subu a1,16 + lw t0,20(sp) # fn + lw t1,24(sp) # arg + sw t0,0(a1) # fn + sw t1,4(a1) # arg + + # remainder of arguments are correct for clone system call + li v0,__NR_clone + syscall + + bnez a3,.L__error_bc + + beqz v0,.L__thread_start_bc + + j ra + +.L__thread_start_bc: + # Clear return address in child so we don't unwind further. + li ra,0 + + lw a0,0(sp) # fn + lw a1,4(sp) # arg + + # void __start_thread(int (*func)(void*), void *arg) + la t9,__start_thread + j t9 + +.L__error_bc: + move a0,v0 + la t9,__set_errno_internal + j t9 +END(__bionic_clone) +.hidden __bionic_clone
diff --git a/libc/arch-mips/bionic/_exit_with_stack_teardown.S b/libc/arch-mips/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..7d47160 --- /dev/null +++ b/libc/arch-mips/bionic/_exit_with_stack_teardown.S
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + li v0, __NR_munmap + syscall + // If munmap failed, we ignore the failure and exit anyway. + + li a0, 0 + li v0, __NR_exit + syscall + // The exit syscall does not return. +END(_exit_with_stack_teardown)
diff --git a/libc/arch-mips/bionic/cacheflush.cpp b/libc/arch-mips/bionic/cacheflush.cpp new file mode 100644 index 0000000..98c0bd4 --- /dev/null +++ b/libc/arch-mips/bionic/cacheflush.cpp
@@ -0,0 +1,63 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <unistd.h> +#include <sys/cachectl.h> + +#include "private/libc_logging.h" + +// Linux historically defines a cacheflush(3) routine for MIPS +// with this signature: + +// int cacheflush(char *addr, int nbytes, int cache); + +// Android defines an alternate cacheflush routine which exposes the +// ARM system call interface: + +// int cacheflush (long start, long end, long flags) + +// This is an attempt to maintain compatibility between the historical MIPS +// usage for software previously ported to MIPS and Android specific +// uses of cacheflush(). + +int cacheflush(long start, long end, long /*flags*/) { + if (end < start) { + // It looks like this is really a MIPS-style cacheflush call. + static bool warned = false; + if (!warned) { + __libc_format_log(ANDROID_LOG_WARN, "libc", "cacheflush called with (start,len) instead of (start,end)"); + warned = true; + } + end += start; + } + + // Use the GCC builtin. This will generate inline synci instructions if available, + // or call _flush_cache(start, len, BCACHE) directly. + __builtin___clear_cache(reinterpret_cast<char*>(start), reinterpret_cast<char*>(end)); + return 0; +}
diff --git a/libc/arch-mips/bionic/crtbegin.c b/libc/arch-mips/bionic/crtbegin.c new file mode 100644 index 0000000..d72ec7b --- /dev/null +++ b/libc/arch-mips/bionic/crtbegin.c
@@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "../../bionic/libc_init_common.h" +#include <stddef.h> +#include <stdint.h> + +__attribute__ ((section (".preinit_array"))) +void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".init_array"))) +void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".fini_array"))) +void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1; + + +__LIBC_HIDDEN__ void do_mips_start(void *raw_args) { + structors_array_t array; + array.preinit_array = &__PREINIT_ARRAY__; + array.init_array = &__INIT_ARRAY__; + array.fini_array = &__FINI_ARRAY__; + + __libc_init(raw_args, NULL, &main, &array); +} + +/* + * This function prepares the return address with a branch-and-link + * instruction (bal) and then uses a .cpload to compute the Global + * Offset Table (GOT) pointer ($gp). The $gp is then used to load + * the address of _do_start() into $t9 just before calling it. + * Terminating the stack with a NULL return address. + */ +__asm__ ( +" .set push \n" +" \n" +" .text \n" +" .align 4 \n" +" .type __start,@function \n" +" .globl __start \n" +" .globl _start \n" +" \n" +" .ent __start \n" +"__start: \n" +" _start: \n" +" .frame $sp,32,$ra \n" +" .mask 0x80000000,-4 \n" +" \n" +" .set noreorder \n" +" bal 1f \n" +" nop \n" +"1: \n" +" .cpload $ra \n" +" .set reorder \n" +" \n" +" move $a0, $sp \n" +" addiu $sp, $sp, (-32) \n" +" sw $0, 28($sp) \n" +" la $t9, do_mips_start \n" +" jalr $t9 \n" +" \n" +"2: b 2b \n" +" .end __start \n" +" \n" +" .set pop \n" +); + +#include "../../arch-common/bionic/__dso_handle.h" +#include "../../arch-common/bionic/atexit.h" +#include "../../arch-common/bionic/pthread_atfork.h"
diff --git a/libc/arch-mips/bionic/libgcc_compat.c b/libc/arch-mips/bionic/libgcc_compat.c new file mode 100644 index 0000000..1a0f566 --- /dev/null +++ b/libc/arch-mips/bionic/libgcc_compat.c
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern char __divdi3; +extern char __moddi3; +extern char __popcountsi2; +extern char __udivdi3; +extern char __umoddi3; + +void* __bionic_libgcc_compat_symbols[] = { + &__divdi3, + &__moddi3, + &__popcountsi2, + &__udivdi3, + &__umoddi3, +};
diff --git a/libc/arch-mips/bionic/setjmp.S b/libc/arch-mips/bionic/setjmp.S new file mode 100644 index 0000000..3b4ff55 --- /dev/null +++ b/libc/arch-mips/bionic/setjmp.S
@@ -0,0 +1,417 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Opsycon AB nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +/*- + * Copyright (c) 1991, 1993, 1995, + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Havard Eidnes. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)signal.h 8.1 (Berkeley) 6/10/93 + */ + +#include <private/bionic_asm.h> +#include <machine/setjmp.h> + +/* jmpbuf is declared to users as an array of longs, which is only + * 4-byte aligned in 32-bit builds. The Mips jmpbuf begins with a + * dynamically-sized 0- or 4-byte unused filler so that double-prec FP regs + * are saved to 8-byte-aligned mem cells. + * All the following jmpbuf offsets are from the rounded-DOWN base addr. + */ + +/* Fields of same size on all MIPS abis: */ +/* field: byte offset: size: */ +/* dynam filler (0*4) 0-4 bytes of rounddown filler, DON'T TOUCH!! + often overlays user storage!! */ +#define SC_FPSR_OFFSET (1*4) /* 4 bytes, floating point control/status reg */ +/* following fields are 8-byte aligned */ +#define SC_FLAG_OFFSET (2*4) /* 8 bytes, cookie and savesigs flag, first actual field */ +#define SC_MASK_OFFSET (4*4) /* 16 bytes, mips32/mips64 version of sigset_t */ +#define SC_CKSUM_OFFSET (8*4) /* 8 bytes, used for checksum */ + +/* Registers that are 4-byte on mips32 o32, and 8-byte on mips64 n64 abi */ +#define SC_REGS_OFFSET (10*4) /* SC_REGS_BYTES */ +#define SC_REGS_SAVED 12 /*regs*/ /* ra,s0-s8,gp,sp */ +#define SC_REGS_BYTES (SC_REGS_SAVED*REGSZ) +#define SC_REGS SC_REGS_OFFSET + +/* Double floating pt registers are 8-bytes on all abis, + * but the number of saved fp regs varies for o32/n32 versus n64 abis: + */ + +#ifdef __LP64__ +#define SC_FPREGS_SAVED 8 /* all fp regs f24,f25,f26,f27,f28,f29,f30,f31 */ +#else +#define SC_FPREGS_SAVED 6 /* even fp regs f20,f22,f24,f26,f28,f30 */ +#endif + +#define SC_FPREGS_OFFSET (SC_REGS_OFFSET + SC_REGS_BYTES) /* SC_FPREGS_BYTES */ +#define SC_FPREGS_BYTES (SC_FPREGS_SAVED*REGSZ_FP) +#define SC_FPREGS SC_FPREGS_OFFSET + +#define SC_TOTAL_BYTES (SC_FPREGS_OFFSET + SC_FPREGS_BYTES) +#define SC_TOTAL_LONGS (SC_TOTAL_BYTES/REGSZ) + +#if SC_TOTAL_LONGS > _JBLEN +#error _JBLEN is too small +#endif + +#define USE_CHECKSUM 1 + +.macro m_mangle_reg_and_store reg, cookie, temp, offset + xor \temp, \reg, \cookie + REG_S \temp, \offset +.endm + +.macro m_unmangle_reg_and_load reg, cookie, temp, offset + REG_L \temp, \offset + xor \reg, \temp, \cookie +.endm + +.macro m_calculate_checksum dst, src, scratch + REG_L \dst, REGSZ(\src) +#ifdef __LP64__ + /* 64 bit: checksum offset is 4 (actual _JBLEN is 25) */ + .irp i,2,3,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24 +#else + /* 32 bit: checksum offset is 8 (actual _JBLEN is 34) */ + .irp i,2,3,4,5,6,7,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33 +#endif + REG_L \scratch, \i*REGSZ(\src) + xor \dst, \dst, \scratch + .endr +.endm + +/* + * + * GPOFF and FRAMESIZE must be the same for all setjmp/longjmp routines + * + */ + +FRAMESZ= MKFSIZ(2,6) +A1OFF= FRAMESZ-4*REGSZ +A0OFF= FRAMESZ-3*REGSZ +GPOFF= FRAMESZ-2*REGSZ +RAOFF= FRAMESZ-1*REGSZ + +NON_LEAF(sigsetjmp, FRAMESZ, ra) + .mask 0x80000000, RAOFF + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(GPOFF, sigsetjmp) + SAVE_GP(GPOFF) + .set reorder + +setjmp_common: +#ifndef __LP64__ + li t0, ~7 + and a0, t0 # round jmpbuf addr DOWN to 8-byte boundary +#endif + REG_S ra, RAOFF(sp) # spill state + REG_S a0, A0OFF(sp) + + # get the cookie and store it along with the signal flag. + move a0, a1 + jal __bionic_setjmp_cookie_get + REG_L a0, A0OFF(sp) + + REG_S v0, SC_FLAG_OFFSET(a0) # save cookie and savesigs flag + andi t0, v0, 1 # extract savesigs flag + + beqz t0, 1f # do saving of signal mask? + + # call sigprocmask(int how ignored, sigset_t* null, sigset_t* SC_MASK(a0)): + LA a2, SC_MASK_OFFSET(a0) # gets current signal mask + li a0, 0 # how; ignored when new mask is null + li a1, 0 # null new mask + jal sigprocmask # get current signal mask + REG_L a0, A0OFF(sp) +1: + REG_L gp, GPOFF(sp) # restore spills + REG_L ra, RAOFF(sp) + REG_L t0, SC_FLAG_OFFSET(a0) # move cookie to temp reg + + # callee-saved long-sized regs: + PTR_ADDU v1, sp, FRAMESZ # save orig sp + + # m_mangle_reg_and_store reg, cookie, temp, offset + m_mangle_reg_and_store ra, t0, t1, SC_REGS+0*REGSZ(a0) + m_mangle_reg_and_store s0, t0, t2, SC_REGS+1*REGSZ(a0) + m_mangle_reg_and_store s1, t0, t3, SC_REGS+2*REGSZ(a0) + m_mangle_reg_and_store s2, t0, t1, SC_REGS+3*REGSZ(a0) + m_mangle_reg_and_store s3, t0, t2, SC_REGS+4*REGSZ(a0) + m_mangle_reg_and_store s4, t0, t3, SC_REGS+5*REGSZ(a0) + m_mangle_reg_and_store s5, t0, t1, SC_REGS+6*REGSZ(a0) + m_mangle_reg_and_store s6, t0, t2, SC_REGS+7*REGSZ(a0) + m_mangle_reg_and_store s7, t0, t3, SC_REGS+8*REGSZ(a0) + m_mangle_reg_and_store s8, t0, t1, SC_REGS+9*REGSZ(a0) + m_mangle_reg_and_store gp, t0, t2, SC_REGS+10*REGSZ(a0) + m_mangle_reg_and_store v1, t0, t3, SC_REGS+11*REGSZ(a0) + + cfc1 v0, $31 + +#ifdef __LP64__ + # callee-saved fp regs on mips n64 ABI are $f24..$f31 + s.d $f24, SC_FPREGS+0*REGSZ_FP(a0) + s.d $f25, SC_FPREGS+1*REGSZ_FP(a0) + s.d $f26, SC_FPREGS+2*REGSZ_FP(a0) + s.d $f27, SC_FPREGS+3*REGSZ_FP(a0) + s.d $f28, SC_FPREGS+4*REGSZ_FP(a0) + s.d $f29, SC_FPREGS+5*REGSZ_FP(a0) + s.d $f30, SC_FPREGS+6*REGSZ_FP(a0) + s.d $f31, SC_FPREGS+7*REGSZ_FP(a0) +#else + # callee-saved fp regs on mips o32 ABI are + # the even-numbered double fp regs $f20,$f22,...$f30 + s.d $f20, SC_FPREGS+0*REGSZ_FP(a0) + s.d $f22, SC_FPREGS+1*REGSZ_FP(a0) + s.d $f24, SC_FPREGS+2*REGSZ_FP(a0) + s.d $f26, SC_FPREGS+3*REGSZ_FP(a0) + s.d $f28, SC_FPREGS+4*REGSZ_FP(a0) + s.d $f30, SC_FPREGS+5*REGSZ_FP(a0) +#endif + sw v0, SC_FPSR_OFFSET(a0) +#if USE_CHECKSUM + m_calculate_checksum t0, a0, t1 + REG_S t0, SC_CKSUM_OFFSET(a0) +#endif + move v0, zero + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j ra +END(sigsetjmp) + + +# Alternate entry points: + +NON_LEAF(setjmp, FRAMESZ, ra) + .mask 0x80000000, RAOFF + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, setjmp) # can't share sigsetjmp's gp code + SAVE_GP(GPOFF) + .set reorder + + li a1, 1 # save/restore signals state + b setjmp_common # tail call +END(setjmp) + + +NON_LEAF(_setjmp, FRAMESZ, ra) + .mask 0x80000000, RAOFF + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, _setjmp) # can't share sigsetjmp's gp code + SAVE_GP(GPOFF) + .set reorder + + li a1, 0 # don't save/restore signals + b setjmp_common # tail call +END(_setjmp) + + +NON_LEAF(siglongjmp, FRAMESZ, ra) + .mask 0x80000000, RAOFF + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, siglongjmp) + SAVE_GP(GPOFF) + .set reorder + +#ifndef __LP64__ + li t0, ~7 + and a0, t0 # round jmpbuf addr DOWN to 8-byte boundary +#endif + + move s1, a1 # temp spill + move s0, a0 + +#if USE_CHECKSUM + m_calculate_checksum t0, s0, s2 + REG_L s2, SC_CKSUM_OFFSET(s0) + beq t0, s2, 0f + nop + jal __bionic_setjmp_checksum_mismatch + nop +0: +#endif + + # extract savesigs flag + REG_L s2, SC_FLAG_OFFSET(s0) + andi t0, s2, 1 + beqz t0, 1f # restore signal mask? + + # call sigprocmask(int how SIG_SETMASK, sigset_t* SC_MASK(a0), sigset_t* null): + LA a1, SC_MASK_OFFSET(s0) # signals being restored + li a0, 3 # mips SIG_SETMASK + li a2, 0 # null + jal sigprocmask # restore signal mask +1: + move t0, s2 # get cookie to temp reg + move a1, s1 + move a0, s0 + + # callee-saved long-sized regs: + + # m_unmangle_reg_and_load reg, cookie, temp, offset + # don't restore gp yet, old value is needed for cookie_check call + m_unmangle_reg_and_load ra, t0, t1, SC_REGS+0*REGSZ(a0) + m_unmangle_reg_and_load s0, t0, t2, SC_REGS+1*REGSZ(a0) + m_unmangle_reg_and_load s1, t0, t3, SC_REGS+2*REGSZ(a0) + m_unmangle_reg_and_load s2, t0, t1, SC_REGS+3*REGSZ(a0) + m_unmangle_reg_and_load s3, t0, t2, SC_REGS+4*REGSZ(a0) + m_unmangle_reg_and_load s4, t0, t3, SC_REGS+5*REGSZ(a0) + m_unmangle_reg_and_load s5, t0, t1, SC_REGS+6*REGSZ(a0) + m_unmangle_reg_and_load s6, t0, t2, SC_REGS+7*REGSZ(a0) + m_unmangle_reg_and_load s7, t0, t3, SC_REGS+8*REGSZ(a0) + m_unmangle_reg_and_load s8, t0, t1, SC_REGS+9*REGSZ(a0) + m_unmangle_reg_and_load v1, t0, t2, SC_REGS+10*REGSZ(a0) + m_unmangle_reg_and_load sp, t0, t3, SC_REGS+11*REGSZ(a0) + + lw v0, SC_FPSR_OFFSET(a0) + ctc1 v0, $31 # restore old fr mode before fp values +#ifdef __LP64__ + # callee-saved fp regs on mips n64 ABI are $f24..$f31 + l.d $f24, SC_FPREGS+0*REGSZ_FP(a0) + l.d $f25, SC_FPREGS+1*REGSZ_FP(a0) + l.d $f26, SC_FPREGS+2*REGSZ_FP(a0) + l.d $f27, SC_FPREGS+3*REGSZ_FP(a0) + l.d $f28, SC_FPREGS+4*REGSZ_FP(a0) + l.d $f29, SC_FPREGS+5*REGSZ_FP(a0) + l.d $f30, SC_FPREGS+6*REGSZ_FP(a0) + l.d $f31, SC_FPREGS+7*REGSZ_FP(a0) +#else + # callee-saved fp regs on mips o32 ABI are + # the even-numbered double fp regs $f20,$f22,...$f30 + l.d $f20, SC_FPREGS+0*REGSZ_FP(a0) + l.d $f22, SC_FPREGS+1*REGSZ_FP(a0) + l.d $f24, SC_FPREGS+2*REGSZ_FP(a0) + l.d $f26, SC_FPREGS+3*REGSZ_FP(a0) + l.d $f28, SC_FPREGS+4*REGSZ_FP(a0) + l.d $f30, SC_FPREGS+5*REGSZ_FP(a0) +#endif + + # check cookie + PTR_SUBU sp, FRAMESZ + REG_S v1, GPOFF(sp) + REG_S ra, RAOFF(sp) + REG_S a1, A1OFF(sp) + move a0, t0 + jal __bionic_setjmp_cookie_check + REG_L gp, GPOFF(sp) + REG_L ra, RAOFF(sp) + REG_L a1, A1OFF(sp) + PTR_ADDU sp, FRAMESZ + + sltiu t0, a1, 1 # never return 0! + xor v0, a1, t0 + j ra # return to setjmp call site +END(siglongjmp) + +ALIAS_SYMBOL(longjmp, siglongjmp) +ALIAS_SYMBOL(_longjmp, siglongjmp)
diff --git a/libc/arch-mips/bionic/syscall.S b/libc/arch-mips/bionic/syscall.S new file mode 100644 index 0000000..5fed0ac --- /dev/null +++ b/libc/arch-mips/bionic/syscall.S
@@ -0,0 +1,61 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +/* + * The caller is only required to allocate 16 bytes of stack for a0-a3. + * syscall has up to 6 arguments, so we need space for the extra two arguments. + */ +#define STACKSIZE 2*4 + +ENTRY(syscall) + .set noreorder + .cpload t9 + move v0, a0 + move a0, a1 + move a1, a2 + move a2, a3 + lw a3, 16(sp) + lw t0, 20(sp) + lw t1, 24(sp) + subu sp, STACKSIZE + sw t0, 16(sp) + sw t1, 20(sp) + syscall + addu sp, STACKSIZE + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(syscall)
diff --git a/libc/arch-mips/bionic/vfork.S b/libc/arch-mips/bionic/vfork.S new file mode 100644 index 0000000..7ccf70b --- /dev/null +++ b/libc/arch-mips/bionic/vfork.S
@@ -0,0 +1,66 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/sched.h> + +// TODO: mips' uapi signal.h is missing #ifndef __ASSEMBLY__. +// #include <asm/signal.h> +#define SIGCHLD 18 + +ENTRY(vfork) + .set noreorder + .cpload t9 + + // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0 + .set push + .set mips32r2 + rdhwr v0, $29 // v0 = tls; kernel trap on mips32r1 + .set pop + lw v0, REGSZ*1(v0) // v0 = v0[TLS_SLOT_THREAD_ID ie 1] + sw $0, REGSZ*2+4(v0) // v0->cached_pid_ = 0 + + li a0, (CLONE_VM | CLONE_VFORK | SIGCHLD) + li a1, 0 + li a2, 0 + li a3, 0 + subu sp, 8 + sw $0, 16(sp) + li v0, __NR_clone + syscall + addu sp, 8 + bnez a3, 1f + move a0, v0 + + j ra + nop +1: + la t9, __set_errno_internal + j t9 + nop +END(vfork)
diff --git a/libc/arch-mips/include/machine/asm.h b/libc/arch-mips/include/machine/asm.h new file mode 100644 index 0000000..cdc7914 --- /dev/null +++ b/libc/arch-mips/include/machine/asm.h
@@ -0,0 +1,206 @@ +/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */ + +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#ifndef _MIPS64_ASM_H +#define _MIPS64_ASM_H + +#define __bionic_asm_align 4 + +#undef __bionic_asm_custom_entry +#undef __bionic_asm_custom_end +#define __bionic_asm_custom_entry(f) .ent f +#define __bionic_asm_custom_end(f) .end f + +#include <machine/regdef.h> + +#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */ +#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */ +#define _MIPS_ISA_MIPS3 3 /* R4000 */ +#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */ +#define _MIPS_ISA_MIPS5 5 +#define _MIPS_ISA_MIPS32 6 +#define _MIPS_ISA_MIPS64 7 + +#if !defined(ABICALLS) && !defined(_NO_ABICALLS) +#define ABICALLS .abicalls +#endif + +#if defined(ABICALLS) && !defined(_KERNEL) + ABICALLS +#endif + +#if !defined(__MIPSEL__) && !defined(__MIPSEB__) +#error "__MIPSEL__ or __MIPSEB__ must be defined" +#endif +/* + * Define how to access unaligned data word + */ +#if defined(__MIPSEL__) +#define LWLO lwl +#define LWHI lwr +#define SWLO swl +#define SWHI swr +#define LDLO ldl +#define LDHI ldr +#define SDLO sdl +#define SDHI sdr +#endif +#if defined(__MIPSEB__) +#define LWLO lwr +#define LWHI lwl +#define SWLO swr +#define SWHI swl +#define LDLO ldr +#define LDHI ldl +#define SDLO sdr +#define SDHI sdl +#endif + +/* + * Define programming environment for ABI. + */ +#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE) + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +#define NARGSAVE 4 + +#define SETUP_GP \ + .set noreorder; \ + .cpload t9; \ + .set reorder; + +#define SAVE_GP(x) \ + .cprestore x + +#define SETUP_GP64(gpoff, name) +#define RESTORE_GP64 +#endif + +#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32) +#define NARGSAVE 0 + +#define SETUP_GP +#define SAVE_GP(x) +#define SETUP_GP64(gpoff, name) \ + .cpsetup t9, gpoff, name +#define RESTORE_GP64 \ + .cpreturn +#endif + +#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31)) + +#else /* defined(ABICALLS) && !defined(_KERNEL) */ + +#define NARGSAVE 4 +#define SETUP_GP +#define SAVE_GP(x) + +#define ALIGNSZ 16 /* Stack layout alignment */ +#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1)) + +#endif + +/* + * Basic register operations based on selected ISA + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32) +#define REGSZ 4 /* 32 bit mode register size */ +#define LOGREGSZ 2 /* log rsize */ +#define REG_S sw +#define REG_L lw +#define CF_SZ 24 /* Call frame size */ +#define CF_ARGSZ 16 /* Call frame arg size */ +#define CF_RA_OFFS 20 /* Call ra save offset */ +#endif + +#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64) +#define REGSZ 8 /* 64 bit mode register size */ +#define LOGREGSZ 3 /* log rsize */ +#define REG_S sd +#define REG_L ld +#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */ +#define CF_ARGSZ 32 /* Call frame arg size */ +#define CF_RA_OFFS 40 /* Call ra save offset */ +#endif + +#define REGSZ_FP 8 /* 64 bit FP register size */ + +#ifndef __LP64__ +#define PTR_L lw +#define PTR_S sw +#define PTR_SUB sub +#define PTR_ADD add +#define PTR_SUBU subu +#define PTR_ADDU addu +#define LI li +#define LA la +#define PTR_SLL sll +#define PTR_SRL srl +#define PTR_VAL .word +#else +#define PTR_L ld +#define PTR_S sd +#define PTR_ADD dadd +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_ADDU daddu +#define LI dli +#define LA dla +#define PTR_SLL dsll +#define PTR_SRL dsrl +#define PTR_VAL .dword +#endif + +/* + * LEAF(x, fsize) + * + * Declare a leaf routine. + */ +#define LEAF(x, fsize) \ + .align 3; \ + .globl x; \ + .ent x, 0; \ +x: ; \ + .cfi_startproc; \ + .frame sp, fsize, ra; \ + SETUP_GP \ + +/* + * NON_LEAF(x) + * + * Declare a non-leaf routine (a routine that makes other C calls). + */ +#define NON_LEAF(x, fsize, retpc) \ + .align 3; \ + .globl x; \ + .ent x, 0; \ +x: ; \ + .cfi_startproc; \ + .frame sp, fsize, retpc; \ + SETUP_GP \ + +#endif /* !_MIPS_ASM_H */
diff --git a/libc/arch-mips/include/machine/elf_machdep.h b/libc/arch-mips/include/machine/elf_machdep.h new file mode 100644 index 0000000..4db087b --- /dev/null +++ b/libc/arch-mips/include/machine/elf_machdep.h
@@ -0,0 +1,197 @@ +/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ + +#ifndef _MIPS_ELF_MACHDEP_H_ +#define _MIPS_ELF_MACHDEP_H_ + +#ifdef _LP64 +#define ARCH_ELFSIZE 64 /* MD native binary size */ +#else +#define ARCH_ELFSIZE 32 /* MD native binary size */ +#endif + +#if ELFSIZE == 32 +#define ELF32_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF32_MACHDEP_ID EM_MIPS +#elif ELFSIZE == 64 +#define ELF64_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF64_MACHDEP_ID EM_MIPS +#endif + +/* mips relocs. */ + +#define R_MIPS_NONE 0 +#define R_MIPS_16 1 +#define R_MIPS_32 2 +#define R_MIPS_REL32 3 +#define R_MIPS_REL R_MIPS_REL32 +#define R_MIPS_26 4 +#define R_MIPS_HI16 5 /* high 16 bits of symbol value */ +#define R_MIPS_LO16 6 /* low 16 bits of symbol value */ +#define R_MIPS_GPREL16 7 /* GP-relative reference */ +#define R_MIPS_LITERAL 8 /* Reference to literal section */ +#define R_MIPS_GOT16 9 /* Reference to global offset table */ +#define R_MIPS_GOT R_MIPS_GOT16 +#define R_MIPS_PC16 10 /* 16 bit PC relative reference */ +#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */ +#define R_MIPS_CALL R_MIPS_CALL16 +#define R_MIPS_GPREL32 12 + +/* 13, 14, 15 are not defined at this point. */ +#define R_MIPS_UNUSED1 13 +#define R_MIPS_UNUSED2 14 +#define R_MIPS_UNUSED3 15 + +/* + * The remaining relocs are apparently part of the 64-bit Irix ELF ABI. + */ +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 + +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +/* TLS relocations */ + +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ + +#define R_MIPS_max 51 + +#define R_TYPE(name) __CONCAT(R_MIPS_,name) + +#define R_MIPS16_min 100 +#define R_MIPS16_26 100 +#define R_MIPS16_GPREL 101 +#define R_MIPS16_GOT16 102 +#define R_MIPS16_CALL16 103 +#define R_MIPS16_HI16 104 +#define R_MIPS16_LO16 105 +#define R_MIPS16_max 106 + + +/* mips dynamic tags */ + +#define DT_MIPS_RLD_VERSION 0x70000001 +#define DT_MIPS_TIME_STAMP 0x70000002 +#define DT_MIPS_ICHECKSUM 0x70000003 +#define DT_MIPS_IVERSION 0x70000004 +#define DT_MIPS_FLAGS 0x70000005 +#define DT_MIPS_BASE_ADDRESS 0x70000006 +#define DT_MIPS_CONFLICT 0x70000008 +#define DT_MIPS_LIBLIST 0x70000009 +#define DT_MIPS_CONFLICTNO 0x7000000b +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */ +#define DT_MIPS_LIBLISTNO 0x70000010 +#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 +#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */ +#define DT_MIPS_HIPAGENO 0x70000014 +#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */ +#define DT_MIPS_RLD_MAP_REL 0x70000035 /* offset of loader map, used for PIE */ + +/* + * ELF Flags + */ +#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ +#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */ +#define EF_MIPS_ABI2 0x00000020 /* N32 */ + +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */ +#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */ +#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */ + +#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */ +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */ +#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */ +#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */ +#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */ +#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */ + +#define EF_MIPS_ABI 0x0000f000 +#define EF_MIPS_ABI_O32 0x00001000 +#define EF_MIPS_ABI_O64 0x00002000 +#define EF_MIPS_ABI_EABI32 0x00003000 +#define EF_MIPS_ABI_EABI64 0x00004000 + +#if defined(__MIPSEB__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#elif defined(__MIPSEL__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB +#elif !defined(HAVE_NBTOOL_CONFIG_H) +#error neither __MIPSEL__ nor __MIPSEB__ are defined. +#endif + +#ifdef _KERNEL +#ifdef _KERNEL_OPT +#include "opt_compat_netbsd.h" +#endif +#ifdef COMPAT_16 +/* + * Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable. + * Tell the kernel ELF exec code not to try relocating the interpreter + * for dynamically-linked ELF binaries. + */ +#define ELF_INTERP_NON_RELOCATABLE +#endif /* COMPAT_16 */ + +/* + * We need to be able to include the ELF header so we can pick out the + * ABI being used. + */ +#ifdef ELFSIZE +#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe) +#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup) +#endif + +struct exec_package; + +int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf32_setup(struct lwp *, void *); + +int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf64_setup(struct lwp *, void *); +#endif /* _KERNEL */ + +#endif /* _MIPS_ELF_MACHDEP_H_ */
diff --git a/libc/arch-mips/include/machine/fenv.h b/libc/arch-mips/include/machine/fenv.h new file mode 100644 index 0000000..689e1cb --- /dev/null +++ b/libc/arch-mips/include/machine/fenv.h
@@ -0,0 +1,98 @@ +/*- + * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ + */ + +/* + Rewritten for Android. +*/ + +/* MIPS FPU floating point control register bits. + * + * 31-25 -> floating point conditions code bits set by FP compare + * instructions + * 24 -> flush denormalized results to zero instead of + * causing unimplemented operation exception. + * 23 -> Condition bit + * 22 -> In conjunction with FS detects denormalized + * operands and replaces them internally with 0. + * 21 -> In conjunction with FS forces denormalized operands + * to the closest normalized value. + * 20-18 -> reserved (read as 0, write with 0) + * 17 -> cause bit for unimplemented operation + * 16 -> cause bit for invalid exception + * 15 -> cause bit for division by zero exception + * 14 -> cause bit for overflow exception + * 13 -> cause bit for underflow exception + * 12 -> cause bit for inexact exception + * 11 -> enable exception for invalid exception + * 10 -> enable exception for division by zero exception + * 9 -> enable exception for overflow exception + * 8 -> enable exception for underflow exception + * 7 -> enable exception for inexact exception + * 6 -> flag invalid exception + * 5 -> flag division by zero exception + * 4 -> flag overflow exception + * 3 -> flag underflow exception + * 2 -> flag inexact exception + * 1-0 -> rounding control + * + * + * Rounding Control: + * 00 - rounding to nearest (RN) + * 01 - rounding toward zero (RZ) + * 10 - rounding (up) toward plus infinity (RP) + * 11 - rounding (down)toward minus infinity (RM) + */ + +#ifndef _MIPS_FENV_H_ +#define _MIPS_FENV_H_ + +#include <sys/types.h> + +__BEGIN_DECLS + +typedef __uint32_t fenv_t; +typedef __uint32_t fexcept_t; + +/* Exception flags */ +#define FE_INVALID 0x40 +#define FE_DIVBYZERO 0x20 +#define FE_OVERFLOW 0x10 +#define FE_UNDERFLOW 0x08 +#define FE_INEXACT 0x04 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ + FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) + +/* Rounding modes */ +#define FE_TONEAREST 0x0000 +#define FE_TOWARDZERO 0x0001 +#define FE_UPWARD 0x0002 +#define FE_DOWNWARD 0x0003 + +__END_DECLS + +#endif /* !_MIPS_FENV_H_ */
diff --git a/libc/arch-mips/include/machine/regdef.h b/libc/arch-mips/include/machine/regdef.h new file mode 100644 index 0000000..3a7cd68 --- /dev/null +++ b/libc/arch-mips/include/machine/regdef.h
@@ -0,0 +1,99 @@ +/* $OpenBSD: regdef.h,v 1.3 2005/08/07 07:29:44 miod Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. This file is derived from the MIPS RISC + * Architecture book by Gerry Kane. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)regdef.h 8.1 (Berkeley) 6/10/93 + */ +#ifndef _MIPS_REGDEF_H_ +#define _MIPS_REGDEF_H_ + +#if (_MIPS_SIM == _ABI64) && !defined(__mips_n64) +#define __mips_n64 1 +#endif +#if (_MIPS_SIM == _ABIN32) && !defined(__mips_n32) +#define __mips_n32 1 +#endif + +#define zero $0 /* always zero */ +#define AT $at /* assembler temp */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#if defined(__mips_n32) || defined(__mips_n64) +#define a4 $8 /* expanded register arguments */ +#define a5 $9 +#define a6 $10 +#define a7 $11 +#define ta0 $8 /* alias */ +#define ta1 $9 +#define ta2 $10 +#define ta3 $11 +#define t0 $12 /* temp registers (not saved across subroutine calls) */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#else +#define t0 $8 /* temp registers (not saved across subroutine calls) */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define ta0 $12 /* alias */ +#define ta1 $13 +#define ta2 $14 +#define ta3 $15 +#endif +#define s0 $16 /* saved across subroutine calls (callee saved) */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* two more temp registers */ +#define t9 $25 +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define s8 $30 /* one more callee saved */ +#define ra $31 /* return address */ + +#endif /* !_MIPS_REGDEF_H_ */
diff --git a/libc/arch-mips/include/machine/setjmp.h b/libc/arch-mips/include/machine/setjmp.h new file mode 100644 index 0000000..4067d51 --- /dev/null +++ b/libc/arch-mips/include/machine/setjmp.h
@@ -0,0 +1,15 @@ +/* $OpenBSD: setjmp.h,v 1.2 2004/08/10 21:10:56 pefo Exp $ */ + +/* Public domain */ + +#ifndef _MIPS_SETJMP_H_ +#define _MIPS_SETJMP_H_ + +#ifdef __LP64__ +#define _JBLEN 25 /* size, in 8-byte longs, of a mips64 jmp_buf/sigjmp_buf */ +#else +#define _JBLEN 157 /* historical size, in 4-byte longs, of a mips32 jmp_buf */ + /* actual used size is 34 */ +#endif + +#endif /* !_MIPS_SETJMP_H_ */
diff --git a/libc/arch-mips/include/sgidefs.h b/libc/arch-mips/include/sgidefs.h new file mode 100644 index 0000000..8b37bf0 --- /dev/null +++ b/libc/arch-mips/include/sgidefs.h
@@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SGIDEFS_H_ +#define _SGIDEFS_H_ + +#include <asm/sgidefs.h> + +#endif /* _SGIDEFS_H_ */
diff --git a/libc/arch-mips/string/memcmp.c b/libc/arch-mips/string/memcmp.c new file mode 100644 index 0000000..8640954 --- /dev/null +++ b/libc/arch-mips/string/memcmp.c
@@ -0,0 +1,51 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include <string.h> + +int memcmp(const void *s1, const void *s2, size_t n) +{ + const unsigned char* p1 = s1; + const unsigned char* end1 = p1 + n; + const unsigned char* p2 = s2; + int d = 0; + + for (;;) { + if (d || p1 >= end1) break; + d = (int)*p1++ - (int)*p2++; + + if (d || p1 >= end1) break; + d = (int)*p1++ - (int)*p2++; + + if (d || p1 >= end1) break; + d = (int)*p1++ - (int)*p2++; + + if (d || p1 >= end1) break; + d = (int)*p1++ - (int)*p2++; + } + return d; +}
diff --git a/libc/arch-mips/string/memcpy.S b/libc/arch-mips/string/memcpy.S new file mode 100644 index 0000000..0b711bd --- /dev/null +++ b/libc/arch-mips/string/memcpy.S
@@ -0,0 +1,852 @@ +/* + * Copyright (c) 2012-2015 + * MIPS Technologies, Inc., California. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef __ANDROID__ +# include <private/bionic_asm.h> +# define USE_MEMMOVE_FOR_OVERLAP +# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#elif _LIBC +# include <sysdep.h> +# include <regdef.h> +# include <sys/asm.h> +# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#elif _COMPILING_NEWLIB +# include "machine/asm.h" +# include "machine/regdef.h" +# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#else +# include <regdef.h> +# include <sys/asm.h> +#endif + +/* Check to see if the MIPS architecture we are compiling for supports + * prefetching. + */ + +#if (__mips == 4) || (__mips == 5) || (__mips == 32) || (__mips == 64) +# ifndef DISABLE_PREFETCH +# define USE_PREFETCH +# endif +#endif + +#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)) +# ifndef DISABLE_DOUBLE +# define USE_DOUBLE +# endif +#endif + + +#if __mips_isa_rev > 5 +# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) +# undef PREFETCH_STORE_HINT +# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED +# endif +# define R6_CODE +#endif + +/* Some asm.h files do not have the L macro definition. */ +#ifndef L +# if _MIPS_SIM == _ABIO32 +# define L(label) $L ## label +# else +# define L(label) .L ## label +# endif +#endif + +/* Some asm.h files do not have the PTR_ADDIU macro definition. */ +#ifndef PTR_ADDIU +# if _MIPS_SIM == _ABIO32 +# define PTR_ADDIU addiu +# else +# define PTR_ADDIU daddiu +# endif +#endif + +/* Some asm.h files do not have the PTR_SRA macro definition. */ +#ifndef PTR_SRA +# if _MIPS_SIM == _ABIO32 +# define PTR_SRA sra +# else +# define PTR_SRA dsra +# endif +#endif + +/* New R6 instructions that may not be in asm.h. */ +#ifndef PTR_LSA +# if _MIPS_SIM == _ABIO32 +# define PTR_LSA lsa +# else +# define PTR_LSA dlsa +# endif +#endif + +/* + * Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load + * prefetches appears to offer a slight preformance advantage. + * + * Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE + * or PREFETCH_STORE_STREAMED offers a large performance advantage + * but PREPAREFORSTORE has some special restrictions to consider. + * + * Prefetch with the 'prepare for store' hint does not copy a memory + * location into the cache, it just allocates a cache line and zeros + * it out. This means that if you do not write to the entire cache + * line before writing it out to memory some data will get zero'ed out + * when the cache line is written back to memory and data will be lost. + * + * Also if you are using this memcpy to copy overlapping buffers it may + * not behave correctly when using the 'prepare for store' hint. If you + * use the 'prepare for store' prefetch on a memory area that is in the + * memcpy source (as well as the memcpy destination), then you will get + * some data zero'ed out before you have a chance to read it and data will + * be lost. + * + * If you are going to use this memcpy routine with the 'prepare for store' + * prefetch you may want to set USE_MEMMOVE_FOR_OVERLAP in order to avoid + * the problem of running memcpy on overlapping buffers. + * + * There are ifdef'ed sections of this memcpy to make sure that it does not + * do prefetches on cache lines that are not going to be completely written. + * This code is only needed and only used when PREFETCH_STORE_HINT is set to + * PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are + * 32 bytes and if the cache line is larger it will not work correctly. + */ + +#ifdef USE_PREFETCH +# define PREFETCH_HINT_LOAD 0 +# define PREFETCH_HINT_STORE 1 +# define PREFETCH_HINT_LOAD_STREAMED 4 +# define PREFETCH_HINT_STORE_STREAMED 5 +# define PREFETCH_HINT_LOAD_RETAINED 6 +# define PREFETCH_HINT_STORE_RETAINED 7 +# define PREFETCH_HINT_WRITEBACK_INVAL 25 +# define PREFETCH_HINT_PREPAREFORSTORE 30 + +/* + * If we have not picked out what hints to use at this point use the + * standard load and store prefetch hints. + */ +# ifndef PREFETCH_STORE_HINT +# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE +# endif +# ifndef PREFETCH_LOAD_HINT +# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD +# endif + +/* + * We double everything when USE_DOUBLE is true so we do 2 prefetches to + * get 64 bytes in that case. The assumption is that each individual + * prefetch brings in 32 bytes. + */ + +# ifdef USE_DOUBLE +# define PREFETCH_CHUNK 64 +# define PREFETCH_FOR_LOAD(chunk, reg) \ + pref PREFETCH_LOAD_HINT, (chunk)*64(reg); \ + pref PREFETCH_LOAD_HINT, ((chunk)*64)+32(reg) +# define PREFETCH_FOR_STORE(chunk, reg) \ + pref PREFETCH_STORE_HINT, (chunk)*64(reg); \ + pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg) +# else +# define PREFETCH_CHUNK 32 +# define PREFETCH_FOR_LOAD(chunk, reg) \ + pref PREFETCH_LOAD_HINT, (chunk)*32(reg) +# define PREFETCH_FOR_STORE(chunk, reg) \ + pref PREFETCH_STORE_HINT, (chunk)*32(reg) +# endif +/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less + * than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size + * of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE + * hint is used, the code will not work correctly. If PREPAREFORSTORE is not + * used then MAX_PREFETCH_SIZE does not matter. */ +# define MAX_PREFETCH_SIZE 128 +/* PREFETCH_LIMIT is set based on the fact that we never use an offset greater + * than 5 on a STORE prefetch and that a single prefetch can never be larger + * than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because + * we actually do two prefetches in that case, one 32 bytes after the other. */ +# ifdef USE_DOUBLE +# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE +# else +# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE +# endif +# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \ + && ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE) +/* We cannot handle this because the initial prefetches may fetch bytes that + * are before the buffer being copied. We start copies with an offset + * of 4 so avoid this situation when using PREPAREFORSTORE. */ +#error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small." +# endif +#else /* USE_PREFETCH not defined */ +# define PREFETCH_FOR_LOAD(offset, reg) +# define PREFETCH_FOR_STORE(offset, reg) +#endif + +/* Allow the routine to be named something else if desired. */ +#ifndef MEMCPY_NAME +# define MEMCPY_NAME memcpy +#endif + +/* We use these 32/64 bit registers as temporaries to do the copying. */ +#define REG0 t0 +#define REG1 t1 +#define REG2 t2 +#define REG3 t3 +#if defined(_MIPS_SIM) && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64) +# define REG4 t4 +# define REG5 t5 +# define REG6 t6 +# define REG7 t7 +#else +# define REG4 ta0 +# define REG5 ta1 +# define REG6 ta2 +# define REG7 ta3 +#endif + +/* We load/store 64 bits at a time when USE_DOUBLE is true. + * The C_ prefix stands for CHUNK and is used to avoid macro name + * conflicts with system header files. */ + +#ifdef USE_DOUBLE +# define C_ST sd +# define C_LD ld +# if __MIPSEB +# define C_LDHI ldl /* high part is left in big-endian */ +# define C_STHI sdl /* high part is left in big-endian */ +# define C_LDLO ldr /* low part is right in big-endian */ +# define C_STLO sdr /* low part is right in big-endian */ +# else +# define C_LDHI ldr /* high part is right in little-endian */ +# define C_STHI sdr /* high part is right in little-endian */ +# define C_LDLO ldl /* low part is left in little-endian */ +# define C_STLO sdl /* low part is left in little-endian */ +# endif +# define C_ALIGN dalign /* r6 align instruction */ +#else +# define C_ST sw +# define C_LD lw +# if __MIPSEB +# define C_LDHI lwl /* high part is left in big-endian */ +# define C_STHI swl /* high part is left in big-endian */ +# define C_LDLO lwr /* low part is right in big-endian */ +# define C_STLO swr /* low part is right in big-endian */ +# else +# define C_LDHI lwr /* high part is right in little-endian */ +# define C_STHI swr /* high part is right in little-endian */ +# define C_LDLO lwl /* low part is left in little-endian */ +# define C_STLO swl /* low part is left in little-endian */ +# endif +# define C_ALIGN align /* r6 align instruction */ +#endif + +/* Bookkeeping values for 32 vs. 64 bit mode. */ +#ifdef USE_DOUBLE +# define NSIZE 8 +# define NSIZEMASK 0x3f +# define NSIZEDMASK 0x7f +#else +# define NSIZE 4 +# define NSIZEMASK 0x1f +# define NSIZEDMASK 0x3f +#endif +#define UNIT(unit) ((unit)*NSIZE) +#define UNITM1(unit) (((unit)*NSIZE)-1) + +#ifdef __ANDROID__ +LEAF(MEMCPY_NAME, 0) +#else +LEAF(MEMCPY_NAME) +#endif + .set nomips16 + .set noreorder +/* + * Below we handle the case where memcpy is called with overlapping src and dst. + * Although memcpy is not required to handle this case, some parts of Android + * like Skia rely on such usage. We call memmove to handle such cases. + */ +#ifdef USE_MEMMOVE_FOR_OVERLAP + PTR_SUBU t0,a0,a1 + PTR_SRA t2,t0,31 + xor t1,t0,t2 + PTR_SUBU t0,t1,t2 + sltu t2,t0,a2 + beq t2,zero,L(memcpy) + nop +#if defined(__LP64__) + daddiu sp,sp,-8 + SETUP_GP64(0,MEMCPY_NAME) + LA t9,memmove + RESTORE_GP64 + jr t9 + daddiu sp,sp,8 +#else + LA t9,memmove + jr t9 + nop +#endif +L(memcpy): +#endif +/* + * If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of + * size, copy dst pointer to v0 for the return value. + */ + slti t2,a2,(2 * NSIZE) + bne t2,zero,L(lastb) +#if defined(RETURN_FIRST_PREFETCH) || defined(RETURN_LAST_PREFETCH) + move v0,zero +#else + move v0,a0 +#endif + +#ifndef R6_CODE + +/* + * If src and dst have different alignments, go to L(unaligned), if they + * have the same alignment (but are not actually aligned) do a partial + * load/store to make them aligned. If they are both already aligned + * we can start copying at L(aligned). + */ + xor t8,a1,a0 + andi t8,t8,(NSIZE-1) /* t8 is a0/a1 word-displacement */ + bne t8,zero,L(unaligned) + PTR_SUBU a3, zero, a0 + + andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ + beq a3,zero,L(aligned) /* if a3=0, it is already aligned */ + PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ + + C_LDHI t8,0(a1) + PTR_ADDU a1,a1,a3 + C_STHI t8,0(a0) + PTR_ADDU a0,a0,a3 + +#else /* R6_CODE */ + +/* + * Align the destination and hope that the source gets aligned too. If it + * doesn't we jump to L(r6_unaligned*) to do unaligned copies using the r6 + * align instruction. + */ + andi t8,a0,7 + lapc t9,L(atable) + PTR_LSA t9,t8,t9,2 + jrc t9 +L(atable): + bc L(lb0) + bc L(lb7) + bc L(lb6) + bc L(lb5) + bc L(lb4) + bc L(lb3) + bc L(lb2) + bc L(lb1) +L(lb7): + lb a3, 6(a1) + sb a3, 6(a0) +L(lb6): + lb a3, 5(a1) + sb a3, 5(a0) +L(lb5): + lb a3, 4(a1) + sb a3, 4(a0) +L(lb4): + lb a3, 3(a1) + sb a3, 3(a0) +L(lb3): + lb a3, 2(a1) + sb a3, 2(a0) +L(lb2): + lb a3, 1(a1) + sb a3, 1(a0) +L(lb1): + lb a3, 0(a1) + sb a3, 0(a0) + + li t9,8 + subu t8,t9,t8 + PTR_SUBU a2,a2,t8 + PTR_ADDU a0,a0,t8 + PTR_ADDU a1,a1,t8 +L(lb0): + + andi t8,a1,(NSIZE-1) + lapc t9,L(jtable) + PTR_LSA t9,t8,t9,2 + jrc t9 +L(jtable): + bc L(aligned) + bc L(r6_unaligned1) + bc L(r6_unaligned2) + bc L(r6_unaligned3) +# ifdef USE_DOUBLE + bc L(r6_unaligned4) + bc L(r6_unaligned5) + bc L(r6_unaligned6) + bc L(r6_unaligned7) +# endif +#endif /* R6_CODE */ + +L(aligned): + +/* + * Now dst/src are both aligned to (word or double word) aligned addresses + * Set a2 to count how many bytes we have to copy after all the 64/128 byte + * chunks are copied and a3 to the dst pointer after all the 64/128 byte + * chunks have been copied. We will loop, incrementing a0 and a1 until a0 + * equals a3. + */ + + andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ + beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ + PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ + +/* When in the loop we may prefetch with the 'prepare to store' hint, + * in this case the a0+x should not be past the "t0-32" address. This + * means: for x=128 the last "safe" a0 address is "t0-160". Alternatively, + * for x=64 the last "safe" a0 address is "t0-96" In the current version we + * will use "prefetch hint,128(a0)", so "t0-160" is the limit. + */ +#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ + PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ +#endif + PREFETCH_FOR_LOAD (0, a1) + PREFETCH_FOR_LOAD (1, a1) + PREFETCH_FOR_LOAD (2, a1) + PREFETCH_FOR_LOAD (3, a1) +#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) + PREFETCH_FOR_STORE (1, a0) + PREFETCH_FOR_STORE (2, a0) + PREFETCH_FOR_STORE (3, a0) +#endif +#if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH) +# if PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE + sltu v1,t9,a0 + bgtz v1,L(skip_set) + nop + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) +L(skip_set): +# else + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1) +# endif +#endif +#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) \ + && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3) +# ifdef USE_DOUBLE + PTR_ADDIU v0,v0,32 +# endif +#endif +L(loop16w): + C_LD t0,UNIT(0)(a1) +#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ + bgtz v1,L(skip_pref) +#endif + C_LD t1,UNIT(1)(a1) +#ifndef R6_CODE + PREFETCH_FOR_STORE (4, a0) + PREFETCH_FOR_STORE (5, a0) +#else + PREFETCH_FOR_STORE (2, a0) +#endif +#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5) +# ifdef USE_DOUBLE + PTR_ADDIU v0,v0,32 +# endif +#endif +L(skip_pref): + C_LD REG2,UNIT(2)(a1) + C_LD REG3,UNIT(3)(a1) + C_LD REG4,UNIT(4)(a1) + C_LD REG5,UNIT(5)(a1) + C_LD REG6,UNIT(6)(a1) + C_LD REG7,UNIT(7)(a1) +#ifndef R6_CODE + PREFETCH_FOR_LOAD (4, a1) +#else + PREFETCH_FOR_LOAD (3, a1) +#endif + C_ST t0,UNIT(0)(a0) + C_ST t1,UNIT(1)(a0) + C_ST REG2,UNIT(2)(a0) + C_ST REG3,UNIT(3)(a0) + C_ST REG4,UNIT(4)(a0) + C_ST REG5,UNIT(5)(a0) + C_ST REG6,UNIT(6)(a0) + C_ST REG7,UNIT(7)(a0) + + C_LD t0,UNIT(8)(a1) + C_LD t1,UNIT(9)(a1) + C_LD REG2,UNIT(10)(a1) + C_LD REG3,UNIT(11)(a1) + C_LD REG4,UNIT(12)(a1) + C_LD REG5,UNIT(13)(a1) + C_LD REG6,UNIT(14)(a1) + C_LD REG7,UNIT(15)(a1) +#ifndef R6_CODE + PREFETCH_FOR_LOAD (5, a1) +#endif + C_ST t0,UNIT(8)(a0) + C_ST t1,UNIT(9)(a0) + C_ST REG2,UNIT(10)(a0) + C_ST REG3,UNIT(11)(a0) + C_ST REG4,UNIT(12)(a0) + C_ST REG5,UNIT(13)(a0) + C_ST REG6,UNIT(14)(a0) + C_ST REG7,UNIT(15)(a0) + PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ + bne a0,a3,L(loop16w) + PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ + move a2,t8 + +/* Here we have src and dest word-aligned but less than 64-bytes or + * 128 bytes to go. Check for a 32(64) byte chunk and copy if if there + * is one. Otherwise jump down to L(chk1w) to handle the tail end of + * the copy. + */ + +L(chkw): + PREFETCH_FOR_LOAD (0, a1) + andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ + /* The t8 is the reminder count past 32-bytes */ + beq a2,t8,L(chk1w) /* When a2=t8, no 32-byte chunk */ + nop + C_LD t0,UNIT(0)(a1) + C_LD t1,UNIT(1)(a1) + C_LD REG2,UNIT(2)(a1) + C_LD REG3,UNIT(3)(a1) + C_LD REG4,UNIT(4)(a1) + C_LD REG5,UNIT(5)(a1) + C_LD REG6,UNIT(6)(a1) + C_LD REG7,UNIT(7)(a1) + PTR_ADDIU a1,a1,UNIT(8) + C_ST t0,UNIT(0)(a0) + C_ST t1,UNIT(1)(a0) + C_ST REG2,UNIT(2)(a0) + C_ST REG3,UNIT(3)(a0) + C_ST REG4,UNIT(4)(a0) + C_ST REG5,UNIT(5)(a0) + C_ST REG6,UNIT(6)(a0) + C_ST REG7,UNIT(7)(a0) + PTR_ADDIU a0,a0,UNIT(8) + +/* + * Here we have less than 32(64) bytes to copy. Set up for a loop to + * copy one word (or double word) at a time. Set a2 to count how many + * bytes we have to copy after all the word (or double word) chunks are + * copied and a3 to the dst pointer after all the (d)word chunks have + * been copied. We will loop, incrementing a0 and a1 until a0 equals a3. + */ +L(chk1w): + andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ + beq a2,t8,L(lastb) + PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ + +/* copying in words (4-byte or 8-byte chunks) */ +L(wordCopy_loop): + C_LD REG3,UNIT(0)(a1) + PTR_ADDIU a0,a0,UNIT(1) + PTR_ADDIU a1,a1,UNIT(1) + bne a0,a3,L(wordCopy_loop) + C_ST REG3,UNIT(-1)(a0) + +/* Copy the last 8 (or 16) bytes */ +L(lastb): + blez a2,L(leave) + PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ +L(lastbloop): + lb v1,0(a1) + PTR_ADDIU a0,a0,1 + PTR_ADDIU a1,a1,1 + bne a0,a3,L(lastbloop) + sb v1,-1(a0) +L(leave): + j ra + nop + +#ifndef R6_CODE +/* + * UNALIGNED case, got here with a3 = "negu a0" + * This code is nearly identical to the aligned code above + * but only the destination (not the source) gets aligned + * so we need to do partial loads of the source followed + * by normal stores to the destination (once we have aligned + * the destination). + */ + +L(unaligned): + andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ + beqz a3,L(ua_chk16w) /* if a3=0, it is already aligned */ + PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ + + C_LDHI v1,UNIT(0)(a1) + C_LDLO v1,UNITM1(1)(a1) + PTR_ADDU a1,a1,a3 + C_STHI v1,UNIT(0)(a0) + PTR_ADDU a0,a0,a3 + +/* + * Now the destination (but not the source) is aligned + * Set a2 to count how many bytes we have to copy after all the 64/128 byte + * chunks are copied and a3 to the dst pointer after all the 64/128 byte + * chunks have been copied. We will loop, incrementing a0 and a1 until a0 + * equals a3. + */ + +L(ua_chk16w): + andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ + beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */ + PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ + +# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ + PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ +# endif + PREFETCH_FOR_LOAD (0, a1) + PREFETCH_FOR_LOAD (1, a1) + PREFETCH_FOR_LOAD (2, a1) +# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) + PREFETCH_FOR_STORE (1, a0) + PREFETCH_FOR_STORE (2, a0) + PREFETCH_FOR_STORE (3, a0) +# endif +# if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH) +# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + sltu v1,t9,a0 + bgtz v1,L(ua_skip_set) + nop + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) +L(ua_skip_set): +# else + PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1) +# endif +# endif +L(ua_loop16w): + PREFETCH_FOR_LOAD (3, a1) + C_LDHI t0,UNIT(0)(a1) + C_LDHI t1,UNIT(1)(a1) + C_LDHI REG2,UNIT(2)(a1) +# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + sltu v1,t9,a0 + bgtz v1,L(ua_skip_pref) +# endif + C_LDHI REG3,UNIT(3)(a1) + PREFETCH_FOR_STORE (4, a0) + PREFETCH_FOR_STORE (5, a0) +L(ua_skip_pref): + C_LDHI REG4,UNIT(4)(a1) + C_LDHI REG5,UNIT(5)(a1) + C_LDHI REG6,UNIT(6)(a1) + C_LDHI REG7,UNIT(7)(a1) + C_LDLO t0,UNITM1(1)(a1) + C_LDLO t1,UNITM1(2)(a1) + C_LDLO REG2,UNITM1(3)(a1) + C_LDLO REG3,UNITM1(4)(a1) + C_LDLO REG4,UNITM1(5)(a1) + C_LDLO REG5,UNITM1(6)(a1) + C_LDLO REG6,UNITM1(7)(a1) + C_LDLO REG7,UNITM1(8)(a1) + PREFETCH_FOR_LOAD (4, a1) + C_ST t0,UNIT(0)(a0) + C_ST t1,UNIT(1)(a0) + C_ST REG2,UNIT(2)(a0) + C_ST REG3,UNIT(3)(a0) + C_ST REG4,UNIT(4)(a0) + C_ST REG5,UNIT(5)(a0) + C_ST REG6,UNIT(6)(a0) + C_ST REG7,UNIT(7)(a0) + C_LDHI t0,UNIT(8)(a1) + C_LDHI t1,UNIT(9)(a1) + C_LDHI REG2,UNIT(10)(a1) + C_LDHI REG3,UNIT(11)(a1) + C_LDHI REG4,UNIT(12)(a1) + C_LDHI REG5,UNIT(13)(a1) + C_LDHI REG6,UNIT(14)(a1) + C_LDHI REG7,UNIT(15)(a1) + C_LDLO t0,UNITM1(9)(a1) + C_LDLO t1,UNITM1(10)(a1) + C_LDLO REG2,UNITM1(11)(a1) + C_LDLO REG3,UNITM1(12)(a1) + C_LDLO REG4,UNITM1(13)(a1) + C_LDLO REG5,UNITM1(14)(a1) + C_LDLO REG6,UNITM1(15)(a1) + C_LDLO REG7,UNITM1(16)(a1) + PREFETCH_FOR_LOAD (5, a1) + C_ST t0,UNIT(8)(a0) + C_ST t1,UNIT(9)(a0) + C_ST REG2,UNIT(10)(a0) + C_ST REG3,UNIT(11)(a0) + C_ST REG4,UNIT(12)(a0) + C_ST REG5,UNIT(13)(a0) + C_ST REG6,UNIT(14)(a0) + C_ST REG7,UNIT(15)(a0) + PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ + bne a0,a3,L(ua_loop16w) + PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ + move a2,t8 + +/* Here we have src and dest word-aligned but less than 64-bytes or + * 128 bytes to go. Check for a 32(64) byte chunk and copy if if there + * is one. Otherwise jump down to L(ua_chk1w) to handle the tail end of + * the copy. */ + +L(ua_chkw): + PREFETCH_FOR_LOAD (0, a1) + andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ + /* t8 is the reminder count past 32-bytes */ + beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */ + nop + C_LDHI t0,UNIT(0)(a1) + C_LDHI t1,UNIT(1)(a1) + C_LDHI REG2,UNIT(2)(a1) + C_LDHI REG3,UNIT(3)(a1) + C_LDHI REG4,UNIT(4)(a1) + C_LDHI REG5,UNIT(5)(a1) + C_LDHI REG6,UNIT(6)(a1) + C_LDHI REG7,UNIT(7)(a1) + C_LDLO t0,UNITM1(1)(a1) + C_LDLO t1,UNITM1(2)(a1) + C_LDLO REG2,UNITM1(3)(a1) + C_LDLO REG3,UNITM1(4)(a1) + C_LDLO REG4,UNITM1(5)(a1) + C_LDLO REG5,UNITM1(6)(a1) + C_LDLO REG6,UNITM1(7)(a1) + C_LDLO REG7,UNITM1(8)(a1) + PTR_ADDIU a1,a1,UNIT(8) + C_ST t0,UNIT(0)(a0) + C_ST t1,UNIT(1)(a0) + C_ST REG2,UNIT(2)(a0) + C_ST REG3,UNIT(3)(a0) + C_ST REG4,UNIT(4)(a0) + C_ST REG5,UNIT(5)(a0) + C_ST REG6,UNIT(6)(a0) + C_ST REG7,UNIT(7)(a0) + PTR_ADDIU a0,a0,UNIT(8) +/* + * Here we have less than 32(64) bytes to copy. Set up for a loop to + * copy one word (or double word) at a time. + */ +L(ua_chk1w): + andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ + beq a2,t8,L(ua_smallCopy) + PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ + +/* copying in words (4-byte or 8-byte chunks) */ +L(ua_wordCopy_loop): + C_LDHI v1,UNIT(0)(a1) + C_LDLO v1,UNITM1(1)(a1) + PTR_ADDIU a0,a0,UNIT(1) + PTR_ADDIU a1,a1,UNIT(1) + bne a0,a3,L(ua_wordCopy_loop) + C_ST v1,UNIT(-1)(a0) + +/* Copy the last 8 (or 16) bytes */ +L(ua_smallCopy): + beqz a2,L(leave) + PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ +L(ua_smallCopy_loop): + lb v1,0(a1) + PTR_ADDIU a0,a0,1 + PTR_ADDIU a1,a1,1 + bne a0,a3,L(ua_smallCopy_loop) + sb v1,-1(a0) + + j ra + nop + +#else /* R6_CODE */ + +# if __MIPSEB +# define SWAP_REGS(X,Y) X, Y +# define ALIGN_OFFSET(N) (N) +# else +# define SWAP_REGS(X,Y) Y, X +# define ALIGN_OFFSET(N) (NSIZE-N) +# endif +# define R6_UNALIGNED_WORD_COPY(BYTEOFFSET) \ + andi REG7, a2, (NSIZE-1);/* REG7 is # of bytes to by bytes. */ \ + beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \ + PTR_SUBU a3, a2, REG7; /* a3 is number of bytes to be copied in */ \ + /* (d)word chunks. */ \ + move a2, REG7; /* a2 is # of bytes to copy byte by byte */ \ + /* after word loop is finished. */ \ + PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \ + PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \ + PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \ + C_LD t0, UNIT(0)(REG2); /* Load first part of source. */ \ +L(r6_ua_wordcopy##BYTEOFFSET): \ + C_LD t1, UNIT(1)(REG2); /* Load second part of source. */ \ + C_ALIGN REG3, SWAP_REGS(t1,t0), ALIGN_OFFSET(BYTEOFFSET); \ + PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \ + PTR_ADDIU REG2, REG2, UNIT(1); /* Increment aligned source pointer.*/ \ + move t0, t1; /* Move second part of source to first. */ \ + bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \ + C_ST REG3, UNIT(-1)(a0); \ + j L(lastb); \ + nop + + /* We are generating R6 code, the destination is 4 byte aligned and + the source is not 4 byte aligned. t8 is 1, 2, or 3 depending on the + alignment of the source. */ + +L(r6_unaligned1): + R6_UNALIGNED_WORD_COPY(1) +L(r6_unaligned2): + R6_UNALIGNED_WORD_COPY(2) +L(r6_unaligned3): + R6_UNALIGNED_WORD_COPY(3) +# ifdef USE_DOUBLE +L(r6_unaligned4): + R6_UNALIGNED_WORD_COPY(4) +L(r6_unaligned5): + R6_UNALIGNED_WORD_COPY(5) +L(r6_unaligned6): + R6_UNALIGNED_WORD_COPY(6) +L(r6_unaligned7): + R6_UNALIGNED_WORD_COPY(7) +# endif +#endif /* R6_CODE */ + + .set at + .set reorder +END(MEMCPY_NAME) +#ifndef __ANDROID__ +# ifdef _LIBC +libc_hidden_builtin_def (MEMCPY_NAME) +# endif +#endif
diff --git a/libc/arch-mips/string/memset.S b/libc/arch-mips/string/memset.S new file mode 100644 index 0000000..7ea6753 --- /dev/null +++ b/libc/arch-mips/string/memset.S
@@ -0,0 +1,448 @@ +/* + * Copyright (c) 2013 + * MIPS Technologies, Inc., California. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef __ANDROID__ +# include <private/bionic_asm.h> +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#elif _LIBC +# include <sysdep.h> +# include <regdef.h> +# include <sys/asm.h> +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#elif _COMPILING_NEWLIB +# include "machine/asm.h" +# include "machine/regdef.h" +# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE +#else +# include <regdef.h> +# include <sys/asm.h> +#endif + +/* Check to see if the MIPS architecture we are compiling for supports + prefetching. */ + +#if (__mips == 4) || (__mips == 5) || (__mips == 32) || (__mips == 64) +# ifndef DISABLE_PREFETCH +# define USE_PREFETCH +# endif +#endif + +#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)) +# ifndef DISABLE_DOUBLE +# define USE_DOUBLE +# endif +#endif + +#ifndef USE_DOUBLE +# ifndef DISABLE_DOUBLE_ALIGN +# define DOUBLE_ALIGN +# endif +#endif + +/* Some asm.h files do not have the L macro definition. */ +#ifndef L +# if _MIPS_SIM == _ABIO32 +# define L(label) $L ## label +# else +# define L(label) .L ## label +# endif +#endif + +/* Some asm.h files do not have the PTR_ADDIU macro definition. */ +#ifndef PTR_ADDIU +# if _MIPS_SIM == _ABIO32 +# define PTR_ADDIU addiu +# else +# define PTR_ADDIU daddiu +# endif +#endif + +/* New R6 instructions that may not be in asm.h. */ +#ifndef PTR_LSA +# if _MIPS_SIM == _ABIO32 +# define PTR_LSA lsa +# else +# define PTR_LSA dlsa +# endif +#endif + +/* Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE + or PREFETCH_STORE_STREAMED offers a large performance advantage + but PREPAREFORSTORE has some special restrictions to consider. + + Prefetch with the 'prepare for store' hint does not copy a memory + location into the cache, it just allocates a cache line and zeros + it out. This means that if you do not write to the entire cache + line before writing it out to memory some data will get zero'ed out + when the cache line is written back to memory and data will be lost. + + There are ifdef'ed sections of this memcpy to make sure that it does not + do prefetches on cache lines that are not going to be completely written. + This code is only needed and only used when PREFETCH_STORE_HINT is set to + PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are + less than MAX_PREFETCH_SIZE bytes and if the cache line is larger it will + not work correctly. */ + +#ifdef USE_PREFETCH +# define PREFETCH_HINT_STORE 1 +# define PREFETCH_HINT_STORE_STREAMED 5 +# define PREFETCH_HINT_STORE_RETAINED 7 +# define PREFETCH_HINT_PREPAREFORSTORE 30 + +/* If we have not picked out what hints to use at this point use the + standard load and store prefetch hints. */ +# ifndef PREFETCH_STORE_HINT +# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE +# endif + +/* We double everything when USE_DOUBLE is true so we do 2 prefetches to + get 64 bytes in that case. The assumption is that each individual + prefetch brings in 32 bytes. */ +# ifdef USE_DOUBLE +# define PREFETCH_CHUNK 64 +# define PREFETCH_FOR_STORE(chunk, reg) \ + pref PREFETCH_STORE_HINT, (chunk)*64(reg); \ + pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg) +# else +# define PREFETCH_CHUNK 32 +# define PREFETCH_FOR_STORE(chunk, reg) \ + pref PREFETCH_STORE_HINT, (chunk)*32(reg) +# endif + +/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less + than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size + of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE + hint is used, the code will not work correctly. If PREPAREFORSTORE is not + used than MAX_PREFETCH_SIZE does not matter. */ +# define MAX_PREFETCH_SIZE 128 +/* PREFETCH_LIMIT is set based on the fact that we never use an offset greater + than 5 on a STORE prefetch and that a single prefetch can never be larger + than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because + we actually do two prefetches in that case, one 32 bytes after the other. */ +# ifdef USE_DOUBLE +# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE +# else +# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE +# endif + +# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \ + && ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE) +/* We cannot handle this because the initial prefetches may fetch bytes that + are before the buffer being copied. We start copies with an offset + of 4 so avoid this situation when using PREPAREFORSTORE. */ +# error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small." +# endif +#else /* USE_PREFETCH not defined */ +# define PREFETCH_FOR_STORE(offset, reg) +#endif + +#if __mips_isa_rev > 5 +# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) +# undef PREFETCH_STORE_HINT +# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED +# endif +# define R6_CODE +#endif + +/* We load/store 64 bits at a time when USE_DOUBLE is true. + The C_ prefix stands for CHUNK and is used to avoid macro name + conflicts with system header files. */ + +#ifdef USE_DOUBLE +# define C_ST sd +# if __MIPSEB +# define C_STHI sdl /* high part is left in big-endian */ +# else +# define C_STHI sdr /* high part is right in little-endian */ +# endif +#else +# define C_ST sw +# if __MIPSEB +# define C_STHI swl /* high part is left in big-endian */ +# else +# define C_STHI swr /* high part is right in little-endian */ +# endif +#endif + +/* Bookkeeping values for 32 vs. 64 bit mode. */ +#ifdef USE_DOUBLE +# define NSIZE 8 +# define NSIZEMASK 0x3f +# define NSIZEDMASK 0x7f +#else +# define NSIZE 4 +# define NSIZEMASK 0x1f +# define NSIZEDMASK 0x3f +#endif +#define UNIT(unit) ((unit)*NSIZE) +#define UNITM1(unit) (((unit)*NSIZE)-1) + +#ifdef __ANDROID__ +LEAF(__memset_chk,0) +#else +LEAF(__memset_chk) +#endif + .set noreorder + sltu t2, a3, a2 + beq t2, zero, memset + nop + .cpsetup t9, t8, __memset_chk + LA t9, __memset_chk_fail + jr t9 + nop + .set reorder +END(__memset_chk) + +#ifdef __ANDROID__ +LEAF(memset,0) +#else +LEAF(memset) +#endif + + .set nomips16 + .set noreorder +/* If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of + size, copy dst pointer to v0 for the return value. */ + slti t2,a2,(2 * NSIZE) + bne t2,zero,L(lastb) + move v0,a0 + +/* If memset value is not zero, we copy it to all the bytes in a 32 or 64 + bit word. */ + beq a1,zero,L(set0) /* If memset value is zero no smear */ + PTR_SUBU a3,zero,a0 + nop + + /* smear byte into 32 or 64 bit word */ +#if ((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2) +# ifdef USE_DOUBLE + dins a1, a1, 8, 8 /* Replicate fill byte into half-word. */ + dins a1, a1, 16, 16 /* Replicate fill byte into word. */ + dins a1, a1, 32, 32 /* Replicate fill byte into dbl word. */ +# else + ins a1, a1, 8, 8 /* Replicate fill byte into half-word. */ + ins a1, a1, 16, 16 /* Replicate fill byte into word. */ +# endif +#else +# ifdef USE_DOUBLE + and a1,0xff + dsll t2,a1,8 + or a1,t2 + dsll t2,a1,16 + or a1,t2 + dsll t2,a1,32 + or a1,t2 +# else + and a1,0xff + sll t2,a1,8 + or a1,t2 + sll t2,a1,16 + or a1,t2 +# endif +#endif + +/* If the destination address is not aligned do a partial store to get it + aligned. If it is already aligned just jump to L(aligned). */ +L(set0): +#ifndef R6_CODE + andi t2,a3,(NSIZE-1) /* word-unaligned address? */ + beq t2,zero,L(aligned) /* t2 is the unalignment count */ + PTR_SUBU a2,a2,t2 + C_STHI a1,0(a0) + PTR_ADDU a0,a0,t2 +#else /* R6_CODE */ + andi t2,a0,(NSIZE-1) + lapc t9,L(atable) + PTR_LSA t9,t2,t9,2 + jrc t9 +L(atable): + bc L(aligned) +# ifdef USE_DOUBLE + bc L(lb7) + bc L(lb6) + bc L(lb5) + bc L(lb4) +# endif + bc L(lb3) + bc L(lb2) + bc L(lb1) +L(lb7): + sb a1,6(a0) +L(lb6): + sb a1,5(a0) +L(lb5): + sb a1,4(a0) +L(lb4): + sb a1,3(a0) +L(lb3): + sb a1,2(a0) +L(lb2): + sb a1,1(a0) +L(lb1): + sb a1,0(a0) + + li t9,NSIZE + subu t2,t9,t2 + PTR_SUBU a2,a2,t2 + PTR_ADDU a0,a0,t2 +#endif /* R6_CODE */ + +L(aligned): +/* If USE_DOUBLE is not set we may still want to align the data on a 16 + byte boundry instead of an 8 byte boundry to maximize the opportunity + of proAptiv chips to do memory bonding (combining two sequential 4 + byte stores into one 8 byte store). We know there are at least 4 bytes + left to store or we would have jumped to L(lastb) earlier in the code. */ +#ifdef DOUBLE_ALIGN + andi t2,a3,4 + beq t2,zero,L(double_aligned) + PTR_SUBU a2,a2,t2 + sw a1,0(a0) + PTR_ADDU a0,a0,t2 +L(double_aligned): +#endif + +/* Now the destination is aligned to (word or double word) aligned address + Set a2 to count how many bytes we have to copy after all the 64/128 byte + chunks are copied and a3 to the dest pointer after all the 64/128 byte + chunks have been copied. We will loop, incrementing a0 until it equals + a3. */ + andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ + beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ + PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ + +/* When in the loop we may prefetch with the 'prepare to store' hint, + in this case the a0+x should not be past the "t0-32" address. This + means: for x=128 the last "safe" a0 address is "t0-160". Alternatively, + for x=64 the last "safe" a0 address is "t0-96" In the current version we + will use "prefetch hint,128(a0)", so "t0-160" is the limit. */ +#if defined(USE_PREFETCH) \ + && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ + PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ +#endif +#if defined(USE_PREFETCH) \ + && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) + PREFETCH_FOR_STORE (1, a0) + PREFETCH_FOR_STORE (2, a0) + PREFETCH_FOR_STORE (3, a0) +#endif + +L(loop16w): +#if defined(USE_PREFETCH) \ + && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) + sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ + bgtz v1,L(skip_pref) + nop +#endif +#ifndef R6_CODE + PREFETCH_FOR_STORE (4, a0) + PREFETCH_FOR_STORE (5, a0) +#else + PREFETCH_FOR_STORE (2, a0) +#endif +L(skip_pref): + C_ST a1,UNIT(0)(a0) + C_ST a1,UNIT(1)(a0) + C_ST a1,UNIT(2)(a0) + C_ST a1,UNIT(3)(a0) + C_ST a1,UNIT(4)(a0) + C_ST a1,UNIT(5)(a0) + C_ST a1,UNIT(6)(a0) + C_ST a1,UNIT(7)(a0) + C_ST a1,UNIT(8)(a0) + C_ST a1,UNIT(9)(a0) + C_ST a1,UNIT(10)(a0) + C_ST a1,UNIT(11)(a0) + C_ST a1,UNIT(12)(a0) + C_ST a1,UNIT(13)(a0) + C_ST a1,UNIT(14)(a0) + C_ST a1,UNIT(15)(a0) + PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ + bne a0,a3,L(loop16w) + nop + move a2,t8 + +/* Here we have dest word-aligned but less than 64-bytes or 128 bytes to go. + Check for a 32(64) byte chunk and copy if if there is one. Otherwise + jump down to L(chk1w) to handle the tail end of the copy. */ +L(chkw): + andi t8,a2,NSIZEMASK /* is there a 32-byte/64-byte chunk. */ + /* the t8 is the reminder count past 32-bytes */ + beq a2,t8,L(chk1w)/* when a2==t8, no 32-byte chunk */ + nop + C_ST a1,UNIT(0)(a0) + C_ST a1,UNIT(1)(a0) + C_ST a1,UNIT(2)(a0) + C_ST a1,UNIT(3)(a0) + C_ST a1,UNIT(4)(a0) + C_ST a1,UNIT(5)(a0) + C_ST a1,UNIT(6)(a0) + C_ST a1,UNIT(7)(a0) + PTR_ADDIU a0,a0,UNIT(8) + +/* Here we have less than 32(64) bytes to set. Set up for a loop to + copy one word (or double word) at a time. Set a2 to count how many + bytes we have to copy after all the word (or double word) chunks are + copied and a3 to the dest pointer after all the (d)word chunks have + been copied. We will loop, incrementing a0 until a0 equals a3. */ +L(chk1w): + andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ + beq a2,t8,L(lastb) + PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ + +/* copying in words (4-byte or 8 byte chunks) */ +L(wordCopy_loop): + PTR_ADDIU a0,a0,UNIT(1) + bne a0,a3,L(wordCopy_loop) + C_ST a1,UNIT(-1)(a0) + +/* Copy the last 8 (or 16) bytes */ +L(lastb): + blez a2,L(leave) + PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ +L(lastbloop): + PTR_ADDIU a0,a0,1 + bne a0,a3,L(lastbloop) + sb a1,-1(a0) +L(leave): + j ra + nop + + .set at + .set reorder +END(memset) +#ifndef __ANDROID__ +# ifdef _LIBC +libc_hidden_builtin_def (memset) +libc_hidden_builtin_def (__memset_chk) +# endif +#endif
diff --git a/libc/arch-mips/string/mips-string-ops.h b/libc/arch-mips/string/mips-string-ops.h new file mode 100644 index 0000000..50f7e3a --- /dev/null +++ b/libc/arch-mips/string/mips-string-ops.h
@@ -0,0 +1,148 @@ +/* + * Copyright (c) 2010 MIPS Technologies, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with + * the distribution. + * * Neither the name of MIPS Technologies Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_STRING_OPS_H +#define __MIPS_STRING_OPS_H + /* This definition of the byte bitfields uses the + assumption that the layout of the bitfields is + equivalent to the layout in memory. Generally, + for the MIPS ABIs, this is true. If you compile + the strcmp.c file with -DSMOKE_TEST_NEW_STRCMP, + this assumption will be tested. + + Also, regardless of char signedness, ANSI C dictates that + strcmp() treats each character as unsigned char. For + strlen and the like, signedness doesn't matter. + + Also, this code assumes that there are 8-bits per 'char'. */ + +#if __mips64 +typedef struct bits +{ + unsigned B0:8, B1:8, B2:8, B3:8, B4:8, B5:8, B6:8, B7:8; +} bits_t; +#else +typedef struct bits +{ + unsigned B0:8, B1:8, B2:8, B3:8; +} bits_t; +#endif + +#ifndef _ULW + /* for MIPS GCC, there is no unaligned builtins - so this code forces + the compiler to treat the pointer access as unaligned. */ +struct ulw +{ + unsigned b; +} __attribute__ ((packed)); + +#define _ULW(__x) ((struct ulw *) ((char *)(&__x)))->b; +#endif + +/* This union assumes that small structures can be in registers. If + not, then memory accesses will be done - not optimal, but ok. */ +typedef union +{ + unsigned v; + bits_t b; +} bitfields_t; + +#ifndef detect_zero +/* __mips_dsp, __mips_dspr2, and __mips64 are predefined by + the compiler, based on command line options. */ +#if (__mips_dsp || __mips_dspr2) && !__mips64 +#define __mips_using_dsp 1 + +/* DSP 4-lane (8 unsigned bits per line) subtract and saturate + * Intrinsic operation. How this works: + * Given a 4-byte string of "ABC\0", subtract this as + * an unsigned integer from 0x01010101: + * 0x01010101 + * - 0x41424300 + * ----------- + ( 0xbfbebe01 <-- answer without saturation + * 0x00000001 <-- answer with saturation + * When this 4-lane vector is treated as an unsigned int value, + * a non-zero answer indicates the presence of a zero in the + * original 4-byte argument. */ + +typedef signed char v4i8 __attribute__ ((vector_size (4))); + +#define detect_zero(__x,__y,__01s,__80s)\ + ((unsigned) __builtin_mips_subu_s_qb((v4i8) __01s,(v4i8) __x)) + + /* sets all 4 lanes to requested byte. */ +#define set_byte_lanes(__x) ((unsigned) __builtin_mips_repl_qb(__x)) + + /* sets all 4 lanes to 0x01. */ +#define def_and_set_01(__x) unsigned __x = (unsigned) __builtin_mips_repl_qb(0x01) + + /* sets all 4 lanes to 0x80. Not needed when subu_s.qb used. */ +#define def_and_set_80(__x) /* do nothing */ + +#else + /* this version, originally published in the 80's, uses + a reverse-carry-set like determination of the zero byte. + The steps are, for __x = 0x31ff0001: + __x - _01s = 0x30fdff00 + ~__x = 0xce00fffe + ((__x - _01s) & ~__x) = 0x0000ff00 + x & _80s = 0x00008000 <- byte 3 was zero + Some implementaions naively assume that characters are + always 7-bit unsigned ASCII. With that assumption, the + "& ~x" is usually discarded. Since character strings + are 8-bit, the and is needed to catch the case of + a false positive when the byte is 0x80. */ + +#define detect_zero(__x,__y,_01s,_80s)\ + ((unsigned) (((__x) - _01s) & ~(__x)) & _80s) + +#if __mips64 +#define def_and_set_80(__x) unsigned __x = 0x8080808080808080ul +#define def_and_set_01(__x) unsigned __x = 0x0101010101010101ul +#else +#define def_and_set_80(__x) unsigned __x = 0x80808080ul +#define def_and_set_01(__x) unsigned __x = 0x01010101ul +#endif + +#endif +#endif + +/* dealing with 'void *' conversions without using extra variables. */ +#define get_byte(__x,__idx) (((unsigned char *) (__x))[__idx]) +#define set_byte(__x,__idx,__fill) ((unsigned char *) (__x))[__idx] = (__fill) +#define get_word(__x,__idx) (((unsigned *) (__x))[__idx]) +#define set_word(__x,__idx,__fill) ((unsigned *) (__x))[__idx] = (__fill) +#define inc_ptr_as(__type,__x,__inc) __x = (void *) (((__type) __x) + (__inc)) +#define cvt_ptr_to(__type,__x) ((__type) (__x)) + +#endif
diff --git a/libc/arch-mips/string/mips_strlen.c b/libc/arch-mips/string/mips_strlen.c new file mode 100644 index 0000000..45fc4b4 --- /dev/null +++ b/libc/arch-mips/string/mips_strlen.c
@@ -0,0 +1,224 @@ +/* + * Copyright (c) 2010 MIPS Technologies, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with + * the distribution. + * * Neither the name of MIPS Technologies Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include "mips-string-ops.h" + +#define do_strlen_word(__av) {\ + if (detect_zero(x,x,_01s,_80s)) break;\ + x = __av;\ + cnt += sizeof (unsigned);\ + } + +#define do_strlen_byte(__x) {\ + if ((bx.b.B##__x) == 0) break;\ + ++cnt;\ + } + +#if SMOKE_TEST_MIPS_STRLEN +#define strlen my_strlen +#endif + +size_t +strlen (const char *_a) +{ + int cnt = 0; + unsigned x; + + /* align the string to word boundary so we can do word at a time. */ + if ((cvt_ptr_to (unsigned, _a) & (sizeof (unsigned) - 1)) != 0) + { + if ((cvt_ptr_to (unsigned, _a) & 1) != 0) + { + if (get_byte (_a, 0) == 0) + return cnt; + /* set bit 1 so 2-bytes are checked and incremented. */ + inc_ptr_as (char *, _a, 1); + ++cnt; + } + if ((cvt_ptr_to (unsigned, _a) & 2) != 0) + { + if (get_byte (_a, 0) == 0) + return cnt + 0; + if (get_byte (_a, 1) == 0) + return cnt + 1; + inc_ptr_as (char *, _a, 2); + cnt += 2; + } + } + +#if __mips64 +#error strlen: mips64 check for 4-byte alignment not implemented. +#endif + + if (1) + { + def_and_set_01 (_01s); + def_and_set_80 (_80s); + + /* as advantagous as it is to performance, this code cannot pre-load + the following word, nor can it prefetch the next line at the start + of the loop since the string can be at the end of a page with the + following page unmapped. There are tests in the suite to catch + any attempt to go beyond the current word. */ + x = get_word (_a, 0); + while (1) + { + /* doing 8 words should cover most strings. */ + do_strlen_word (get_word (_a, 1)); + do_strlen_word (get_word (_a, 2)); + do_strlen_word (get_word (_a, 3)); + do_strlen_word (get_word (_a, 4)); + do_strlen_word (get_word (_a, 5)); + do_strlen_word (get_word (_a, 6)); + do_strlen_word (get_word (_a, 7)); + do_strlen_word (get_word (_a, 8)); + inc_ptr_as (unsigned *, _a, 8); + } + } + while (1) + { + /* pull apart the last word processed and find the zero. */ + bitfields_t bx; + bx.v = x; +#if __mips64 + do_strlen_byte (0); + do_strlen_byte (1); + do_strlen_byte (2); + do_strlen_byte (3); + do_strlen_byte (4); + do_strlen_byte (5); + do_strlen_byte (6); +#else + do_strlen_byte (0); + do_strlen_byte (1); + do_strlen_byte (2); +#endif + /* last byte is zero */ + break; + } + return cnt; +} + +#undef do_strlen_byte +#undef do_strlen_word + +#if SMOKE_TEST_MIPS_STRLEN +#include <stdio.h> +char str1[] = "DHRYSTONE PROGRAM, 1'ST STRING"; +char str2[] = "DHRYSTONE PROGRAM, 2'ST STRING"; + +char str3[] = "another string"; +char str4[] = "another"; + +char str5[] = "somes tring"; +char str6[] = "somes_tring"; + +char str7[16], str8[16]; + +static char * +chk (unsigned mine, unsigned libs, int *errors) +{ + static char answer[1024]; + char *result = mine == libs ? "PASS" : "FAIL"; + sprintf (answer, "new_strlen=%d: lib_strlen=%d: %s!", mine, libs, result); + if (mine != libs) + (*errors)++; + return answer; +} + +int +main (int argc, char **argv) +{ + int errors = 0; + /* set -1 in one position */ + str6[5] = 0xff; + /* set zero in same position with junk in following 3 */ + str7[0] = str8[0] = 0; + str7[1] = 0xff; + str7[2] = 'a'; + str7[3] = 2; + str8[1] = 's'; + str8[2] = -2; + str8[3] = 0; + + fprintf (stderr, "========== mips_strlen%s test...\n", + argv[0] ? argv[0] : "unknown strlen"); +#define P(__x,__y) {\ + int a = my_strlen(__x + __y);\ + int b = (strlen)(__x + __y) /* library version */;\ + fprintf(stderr,"%s+%d: %s\n",#__x,__y,chk(a,b,&errors));\ + } + + P (str1, 0); + P (str1, 1); + P (str1, 2); + P (str1, 3); + + P (str2, 0); + P (str2, 1); + P (str2, 2); + P (str2, 3); + + P (str3, 0); + P (str3, 1); + P (str3, 2); + P (str3, 3); + + P (str4, 0); + P (str4, 1); + P (str4, 2); + P (str4, 3); + + P (str5, 0); + P (str5, 1); + P (str5, 2); + P (str5, 3); + + P (str6, 0); + P (str6, 1); + P (str6, 2); + P (str6, 3); + + P (str7, 0); + P (str7, 1); + P (str7, 2); + P (str7, 3); + + P (str8, 0); + P (str8, 1); + P (str8, 2); + P (str8, 3); + + return errors; +} +#endif
diff --git a/libc/arch-mips/string/strcmp.S b/libc/arch-mips/string/strcmp.S new file mode 100644 index 0000000..2b67f5a --- /dev/null +++ b/libc/arch-mips/string/strcmp.S
@@ -0,0 +1,260 @@ +/* + * Copyright (c) 2014 + * Imagination Technologies Limited. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY IMAGINATION TECHNOLOGIES LIMITED ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL IMAGINATION TECHNOLOGIES LIMITED BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef __ANDROID__ +# include <private/bionic_asm.h> +#elif _LIBC +# include <sysdep.h> +# include <regdef.h> +# include <sys/asm.h> +#elif _COMPILING_NEWLIB +# include "machine/asm.h" +# include "machine/regdef.h" +#else +# include <regdef.h> +# include <sys/asm.h> +#endif + +/* Technically strcmp should not read past the end of the strings being + compared. We will read a full word that may contain excess bits beyond + the NULL string terminator but unless ENABLE_READAHEAD is set, we will not + read the next word after the end of string. Setting ENABLE_READAHEAD will + improve performance but is technically illegal based on the definition of + strcmp. */ +#ifdef ENABLE_READAHEAD +# define DELAY_READ +#else +# define DELAY_READ nop +#endif + +/* Testing on a little endian machine showed using CLZ was a + performance loss, so we are not turning it on by default. */ +#if defined(ENABLE_CLZ) && (__mips_isa_rev > 1) +# define USE_CLZ +#endif + +/* Some asm.h files do not have the L macro definition. */ +#ifndef L +# if _MIPS_SIM == _ABIO32 +# define L(label) $L ## label +# else +# define L(label) .L ## label +# endif +#endif + +/* Some asm.h files do not have the PTR_ADDIU macro definition. */ +#ifndef PTR_ADDIU +# if _MIPS_SIM == _ABIO32 +# define PTR_ADDIU addiu +# else +# define PTR_ADDIU daddiu +# endif +#endif + +/* Allow the routine to be named something else if desired. */ +#ifndef STRCMP_NAME +# define STRCMP_NAME strcmp +#endif + +#ifdef __ANDROID__ +LEAF(STRCMP_NAME, 0) +#else +LEAF(STRCMP_NAME) +#endif + .set nomips16 + .set noreorder + + or t0, a0, a1 + andi t0,0x3 + bne t0, zero, L(byteloop) + +/* Both strings are 4 byte aligned at this point. */ + + lui t8, 0x0101 + ori t8, t8, 0x0101 + lui t9, 0x7f7f + ori t9, 0x7f7f + +#define STRCMP32(OFFSET) \ + lw v0, OFFSET(a0); \ + lw v1, OFFSET(a1); \ + subu t0, v0, t8; \ + bne v0, v1, L(worddiff); \ + nor t1, v0, t9; \ + and t0, t0, t1; \ + bne t0, zero, L(returnzero) + +L(wordloop): + STRCMP32(0) + DELAY_READ + STRCMP32(4) + DELAY_READ + STRCMP32(8) + DELAY_READ + STRCMP32(12) + DELAY_READ + STRCMP32(16) + DELAY_READ + STRCMP32(20) + DELAY_READ + STRCMP32(24) + DELAY_READ + STRCMP32(28) + PTR_ADDIU a0, a0, 32 + b L(wordloop) + PTR_ADDIU a1, a1, 32 + +L(returnzero): + j ra + move v0, zero + +L(worddiff): +#ifdef USE_CLZ + subu t0, v0, t8 + nor t1, v0, t9 + and t1, t0, t1 + xor t0, v0, v1 + or t0, t0, t1 +# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + wsbh t0, t0 + rotr t0, t0, 16 +# endif + clz t1, t0 + and t1, 0xf8 +# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + neg t1 + addu t1, 24 +# endif + rotrv v0, v0, t1 + rotrv v1, v1, t1 + and v0, v0, 0xff + and v1, v1, 0xff + j ra + subu v0, v0, v1 +#else /* USE_CLZ */ +# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + andi t0, v0, 0xff + beq t0, zero, L(wexit01) + andi t1, v1, 0xff + bne t0, t1, L(wexit01) + + srl t8, v0, 8 + srl t9, v1, 8 + andi t8, t8, 0xff + beq t8, zero, L(wexit89) + andi t9, t9, 0xff + bne t8, t9, L(wexit89) + + srl t0, v0, 16 + srl t1, v1, 16 + andi t0, t0, 0xff + beq t0, zero, L(wexit01) + andi t1, t1, 0xff + bne t0, t1, L(wexit01) + + srl t8, v0, 24 + srl t9, v1, 24 +# else /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ + srl t0, v0, 24 + beq t0, zero, L(wexit01) + srl t1, v1, 24 + bne t0, t1, L(wexit01) + + srl t8, v0, 16 + srl t9, v1, 16 + andi t8, t8, 0xff + beq t8, zero, L(wexit89) + andi t9, t9, 0xff + bne t8, t9, L(wexit89) + + srl t0, v0, 8 + srl t1, v1, 8 + andi t0, t0, 0xff + beq t0, zero, L(wexit01) + andi t1, t1, 0xff + bne t0, t1, L(wexit01) + + andi t8, v0, 0xff + andi t9, v1, 0xff +# endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ + +L(wexit89): + j ra + subu v0, t8, t9 +L(wexit01): + j ra + subu v0, t0, t1 +#endif /* USE_CLZ */ + +/* It might seem better to do the 'beq' instruction between the two 'lbu' + instructions so that the nop is not needed but testing showed that this + code is actually faster (based on glibc strcmp test). */ +#define BYTECMP01(OFFSET) \ + lbu v0, OFFSET(a0); \ + lbu v1, OFFSET(a1); \ + beq v0, zero, L(bexit01); \ + nop; \ + bne v0, v1, L(bexit01) + +#define BYTECMP89(OFFSET) \ + lbu t8, OFFSET(a0); \ + lbu t9, OFFSET(a1); \ + beq t8, zero, L(bexit89); \ + nop; \ + bne t8, t9, L(bexit89) + +L(byteloop): + BYTECMP01(0) + BYTECMP89(1) + BYTECMP01(2) + BYTECMP89(3) + BYTECMP01(4) + BYTECMP89(5) + BYTECMP01(6) + BYTECMP89(7) + PTR_ADDIU a0, a0, 8 + b L(byteloop) + PTR_ADDIU a1, a1, 8 + +L(bexit01): + j ra + subu v0, v0, v1 +L(bexit89): + j ra + subu v0, t8, t9 + + .set at + .set reorder + +END(STRCMP_NAME) +#ifndef __ANDROID__ +# ifdef _LIBC +libc_hidden_builtin_def (STRCMP_NAME) +# endif +#endif
diff --git a/libc/arch-mips/string/strlen.c b/libc/arch-mips/string/strlen.c new file mode 100644 index 0000000..7e0e27b --- /dev/null +++ b/libc/arch-mips/string/strlen.c
@@ -0,0 +1,43 @@ +/* $OpenBSD: strlen.c,v 1.8 2014/06/10 04:17:37 deraadt Exp $ */ + +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <string.h> + +size_t +strlen(const char *str) +{ + const char *s; + + for (s = str; *s; ++s) + ; + return (s - str); +} +
diff --git a/libc/arch-mips/syscalls/___clock_nanosleep.S b/libc/arch-mips/syscalls/___clock_nanosleep.S new file mode 100644 index 0000000..4879489 --- /dev/null +++ b/libc/arch-mips/syscalls/___clock_nanosleep.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___clock_nanosleep) + .set noreorder + .cpload t9 + li v0, __NR_clock_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___clock_nanosleep) +.hidden ___clock_nanosleep
diff --git a/libc/arch-mips/syscalls/___close.S b/libc/arch-mips/syscalls/___close.S new file mode 100644 index 0000000..356cfd6 --- /dev/null +++ b/libc/arch-mips/syscalls/___close.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___close) + .set noreorder + .cpload t9 + li v0, __NR_close + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___close) +.hidden ___close
diff --git a/libc/arch-mips/syscalls/___faccessat.S b/libc/arch-mips/syscalls/___faccessat.S new file mode 100644 index 0000000..4e11bae --- /dev/null +++ b/libc/arch-mips/syscalls/___faccessat.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___faccessat) + .set noreorder + .cpload t9 + li v0, __NR_faccessat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___faccessat) +.hidden ___faccessat
diff --git a/libc/arch-mips/syscalls/___fchmod.S b/libc/arch-mips/syscalls/___fchmod.S new file mode 100644 index 0000000..ac102ec --- /dev/null +++ b/libc/arch-mips/syscalls/___fchmod.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmod) + .set noreorder + .cpload t9 + li v0, __NR_fchmod + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___fchmod) +.hidden ___fchmod
diff --git a/libc/arch-mips/syscalls/___fchmodat.S b/libc/arch-mips/syscalls/___fchmodat.S new file mode 100644 index 0000000..d581efa --- /dev/null +++ b/libc/arch-mips/syscalls/___fchmodat.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmodat) + .set noreorder + .cpload t9 + li v0, __NR_fchmodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___fchmodat) +.hidden ___fchmodat
diff --git a/libc/arch-mips/syscalls/___fgetxattr.S b/libc/arch-mips/syscalls/___fgetxattr.S new file mode 100644 index 0000000..50ab69c --- /dev/null +++ b/libc/arch-mips/syscalls/___fgetxattr.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fgetxattr) + .set noreorder + .cpload t9 + li v0, __NR_fgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___fgetxattr) +.hidden ___fgetxattr
diff --git a/libc/arch-mips/syscalls/___flistxattr.S b/libc/arch-mips/syscalls/___flistxattr.S new file mode 100644 index 0000000..5a4a53d --- /dev/null +++ b/libc/arch-mips/syscalls/___flistxattr.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___flistxattr) + .set noreorder + .cpload t9 + li v0, __NR_flistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___flistxattr) +.hidden ___flistxattr
diff --git a/libc/arch-mips/syscalls/___fsetxattr.S b/libc/arch-mips/syscalls/___fsetxattr.S new file mode 100644 index 0000000..0312921 --- /dev/null +++ b/libc/arch-mips/syscalls/___fsetxattr.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fsetxattr) + .set noreorder + .cpload t9 + li v0, __NR_fsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___fsetxattr) +.hidden ___fsetxattr
diff --git a/libc/arch-mips/syscalls/___mremap.S b/libc/arch-mips/syscalls/___mremap.S new file mode 100644 index 0000000..82e2eb3 --- /dev/null +++ b/libc/arch-mips/syscalls/___mremap.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___mremap) + .set noreorder + .cpload t9 + li v0, __NR_mremap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___mremap) +.hidden ___mremap
diff --git a/libc/arch-mips/syscalls/___rt_sigqueueinfo.S b/libc/arch-mips/syscalls/___rt_sigqueueinfo.S new file mode 100644 index 0000000..95af36f --- /dev/null +++ b/libc/arch-mips/syscalls/___rt_sigqueueinfo.S
@@ -0,0 +1,20 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___rt_sigqueueinfo) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigqueueinfo + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(___rt_sigqueueinfo) +.hidden ___rt_sigqueueinfo
diff --git a/libc/arch-mips/syscalls/__accept4.S b/libc/arch-mips/syscalls/__accept4.S new file mode 100644 index 0000000..72df04f --- /dev/null +++ b/libc/arch-mips/syscalls/__accept4.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + .set noreorder + .cpload t9 + li v0, __NR_accept4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__accept4)
diff --git a/libc/arch-mips/syscalls/__brk.S b/libc/arch-mips/syscalls/__brk.S new file mode 100644 index 0000000..8472663 --- /dev/null +++ b/libc/arch-mips/syscalls/__brk.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + .set noreorder + .cpload t9 + li v0, __NR_brk + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__brk)
diff --git a/libc/arch-mips/syscalls/__connect.S b/libc/arch-mips/syscalls/__connect.S new file mode 100644 index 0000000..38c1b9b --- /dev/null +++ b/libc/arch-mips/syscalls/__connect.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + .set noreorder + .cpload t9 + li v0, __NR_connect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__connect)
diff --git a/libc/arch-mips/syscalls/__epoll_pwait.S b/libc/arch-mips/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..3aed9bc --- /dev/null +++ b/libc/arch-mips/syscalls/__epoll_pwait.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + .set noreorder + .cpload t9 + li v0, __NR_epoll_pwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__epoll_pwait)
diff --git a/libc/arch-mips/syscalls/__exit.S b/libc/arch-mips/syscalls/__exit.S new file mode 100644 index 0000000..7349804 --- /dev/null +++ b/libc/arch-mips/syscalls/__exit.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + .set noreorder + .cpload t9 + li v0, __NR_exit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__exit)
diff --git a/libc/arch-mips/syscalls/__fadvise64.S b/libc/arch-mips/syscalls/__fadvise64.S new file mode 100644 index 0000000..abacbb2 --- /dev/null +++ b/libc/arch-mips/syscalls/__fadvise64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fadvise64) + .set noreorder + .cpload t9 + li v0, __NR_fadvise64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__fadvise64)
diff --git a/libc/arch-mips/syscalls/__fcntl64.S b/libc/arch-mips/syscalls/__fcntl64.S new file mode 100644 index 0000000..2734be2 --- /dev/null +++ b/libc/arch-mips/syscalls/__fcntl64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fcntl64) + .set noreorder + .cpload t9 + li v0, __NR_fcntl64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__fcntl64)
diff --git a/libc/arch-mips/syscalls/__fstatfs64.S b/libc/arch-mips/syscalls/__fstatfs64.S new file mode 100644 index 0000000..e08cf7e --- /dev/null +++ b/libc/arch-mips/syscalls/__fstatfs64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fstatfs64) + .set noreorder + .cpload t9 + li v0, __NR_fstatfs64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__fstatfs64)
diff --git a/libc/arch-mips/syscalls/__getcpu.S b/libc/arch-mips/syscalls/__getcpu.S new file mode 100644 index 0000000..262f440 --- /dev/null +++ b/libc/arch-mips/syscalls/__getcpu.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + .set noreorder + .cpload t9 + li v0, __NR_getcpu + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__getcpu)
diff --git a/libc/arch-mips/syscalls/__getcwd.S b/libc/arch-mips/syscalls/__getcwd.S new file mode 100644 index 0000000..ca6ec7c --- /dev/null +++ b/libc/arch-mips/syscalls/__getcwd.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + .set noreorder + .cpload t9 + li v0, __NR_getcwd + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__getcwd)
diff --git a/libc/arch-mips/syscalls/__getdents64.S b/libc/arch-mips/syscalls/__getdents64.S new file mode 100644 index 0000000..fe7ef86 --- /dev/null +++ b/libc/arch-mips/syscalls/__getdents64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + .set noreorder + .cpload t9 + li v0, __NR_getdents64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__getdents64)
diff --git a/libc/arch-mips/syscalls/__getpid.S b/libc/arch-mips/syscalls/__getpid.S new file mode 100644 index 0000000..f5ab049 --- /dev/null +++ b/libc/arch-mips/syscalls/__getpid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + .set noreorder + .cpload t9 + li v0, __NR_getpid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__getpid)
diff --git a/libc/arch-mips/syscalls/__getpriority.S b/libc/arch-mips/syscalls/__getpriority.S new file mode 100644 index 0000000..ef6235d --- /dev/null +++ b/libc/arch-mips/syscalls/__getpriority.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + .set noreorder + .cpload t9 + li v0, __NR_getpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__getpriority)
diff --git a/libc/arch-mips/syscalls/__ioctl.S b/libc/arch-mips/syscalls/__ioctl.S new file mode 100644 index 0000000..27716e8 --- /dev/null +++ b/libc/arch-mips/syscalls/__ioctl.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + .set noreorder + .cpload t9 + li v0, __NR_ioctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__ioctl)
diff --git a/libc/arch-mips/syscalls/__llseek.S b/libc/arch-mips/syscalls/__llseek.S new file mode 100644 index 0000000..e0cb321 --- /dev/null +++ b/libc/arch-mips/syscalls/__llseek.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__llseek) + .set noreorder + .cpload t9 + li v0, __NR__llseek + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__llseek)
diff --git a/libc/arch-mips/syscalls/__mmap2.S b/libc/arch-mips/syscalls/__mmap2.S new file mode 100644 index 0000000..8175b31 --- /dev/null +++ b/libc/arch-mips/syscalls/__mmap2.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__mmap2) + .set noreorder + .cpload t9 + li v0, __NR_mmap2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__mmap2)
diff --git a/libc/arch-mips/syscalls/__openat.S b/libc/arch-mips/syscalls/__openat.S new file mode 100644 index 0000000..c0c3cdf --- /dev/null +++ b/libc/arch-mips/syscalls/__openat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + .set noreorder + .cpload t9 + li v0, __NR_openat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__openat)
diff --git a/libc/arch-mips/syscalls/__ppoll.S b/libc/arch-mips/syscalls/__ppoll.S new file mode 100644 index 0000000..75dbbc8 --- /dev/null +++ b/libc/arch-mips/syscalls/__ppoll.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + .set noreorder + .cpload t9 + li v0, __NR_ppoll + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__ppoll)
diff --git a/libc/arch-mips/syscalls/__preadv64.S b/libc/arch-mips/syscalls/__preadv64.S new file mode 100644 index 0000000..a46b869 --- /dev/null +++ b/libc/arch-mips/syscalls/__preadv64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__preadv64) + .set noreorder + .cpload t9 + li v0, __NR_preadv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__preadv64)
diff --git a/libc/arch-mips/syscalls/__pselect6.S b/libc/arch-mips/syscalls/__pselect6.S new file mode 100644 index 0000000..d028156 --- /dev/null +++ b/libc/arch-mips/syscalls/__pselect6.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + .set noreorder + .cpload t9 + li v0, __NR_pselect6 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__pselect6)
diff --git a/libc/arch-mips/syscalls/__ptrace.S b/libc/arch-mips/syscalls/__ptrace.S new file mode 100644 index 0000000..c5d91fb --- /dev/null +++ b/libc/arch-mips/syscalls/__ptrace.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + .set noreorder + .cpload t9 + li v0, __NR_ptrace + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__ptrace)
diff --git a/libc/arch-mips/syscalls/__pwritev64.S b/libc/arch-mips/syscalls/__pwritev64.S new file mode 100644 index 0000000..1222942 --- /dev/null +++ b/libc/arch-mips/syscalls/__pwritev64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pwritev64) + .set noreorder + .cpload t9 + li v0, __NR_pwritev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__pwritev64)
diff --git a/libc/arch-mips/syscalls/__reboot.S b/libc/arch-mips/syscalls/__reboot.S new file mode 100644 index 0000000..c01f7fb --- /dev/null +++ b/libc/arch-mips/syscalls/__reboot.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + .set noreorder + .cpload t9 + li v0, __NR_reboot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__reboot)
diff --git a/libc/arch-mips/syscalls/__rt_sigaction.S b/libc/arch-mips/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..7fa37fd --- /dev/null +++ b/libc/arch-mips/syscalls/__rt_sigaction.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigaction + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__rt_sigaction)
diff --git a/libc/arch-mips/syscalls/__rt_sigpending.S b/libc/arch-mips/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..b80b311 --- /dev/null +++ b/libc/arch-mips/syscalls/__rt_sigpending.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigpending + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__rt_sigpending)
diff --git a/libc/arch-mips/syscalls/__rt_sigprocmask.S b/libc/arch-mips/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..e2a39eb --- /dev/null +++ b/libc/arch-mips/syscalls/__rt_sigprocmask.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigprocmask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__rt_sigprocmask)
diff --git a/libc/arch-mips/syscalls/__rt_sigsuspend.S b/libc/arch-mips/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..e91c53f --- /dev/null +++ b/libc/arch-mips/syscalls/__rt_sigsuspend.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigsuspend + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__rt_sigsuspend)
diff --git a/libc/arch-mips/syscalls/__rt_sigtimedwait.S b/libc/arch-mips/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..0b4195f --- /dev/null +++ b/libc/arch-mips/syscalls/__rt_sigtimedwait.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + .set noreorder + .cpload t9 + li v0, __NR_rt_sigtimedwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__rt_sigtimedwait)
diff --git a/libc/arch-mips/syscalls/__sched_getaffinity.S b/libc/arch-mips/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..b09f404 --- /dev/null +++ b/libc/arch-mips/syscalls/__sched_getaffinity.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + .set noreorder + .cpload t9 + li v0, __NR_sched_getaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__sched_getaffinity)
diff --git a/libc/arch-mips/syscalls/__set_tid_address.S b/libc/arch-mips/syscalls/__set_tid_address.S new file mode 100644 index 0000000..8ca0716 --- /dev/null +++ b/libc/arch-mips/syscalls/__set_tid_address.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + .set noreorder + .cpload t9 + li v0, __NR_set_tid_address + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__set_tid_address)
diff --git a/libc/arch-mips/syscalls/__set_tls.S b/libc/arch-mips/syscalls/__set_tls.S new file mode 100644 index 0000000..1f9eba5 --- /dev/null +++ b/libc/arch-mips/syscalls/__set_tls.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tls) + .set noreorder + .cpload t9 + li v0, __NR_set_thread_area + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__set_tls)
diff --git a/libc/arch-mips/syscalls/__sigaction.S b/libc/arch-mips/syscalls/__sigaction.S new file mode 100644 index 0000000..0886e95 --- /dev/null +++ b/libc/arch-mips/syscalls/__sigaction.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sigaction) + .set noreorder + .cpload t9 + li v0, __NR_sigaction + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__sigaction)
diff --git a/libc/arch-mips/syscalls/__signalfd4.S b/libc/arch-mips/syscalls/__signalfd4.S new file mode 100644 index 0000000..8e5717e --- /dev/null +++ b/libc/arch-mips/syscalls/__signalfd4.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + .set noreorder + .cpload t9 + li v0, __NR_signalfd4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__signalfd4)
diff --git a/libc/arch-mips/syscalls/__socket.S b/libc/arch-mips/syscalls/__socket.S new file mode 100644 index 0000000..c933355 --- /dev/null +++ b/libc/arch-mips/syscalls/__socket.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + .set noreorder + .cpload t9 + li v0, __NR_socket + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__socket)
diff --git a/libc/arch-mips/syscalls/__statfs64.S b/libc/arch-mips/syscalls/__statfs64.S new file mode 100644 index 0000000..ed4dcdb --- /dev/null +++ b/libc/arch-mips/syscalls/__statfs64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__statfs64) + .set noreorder + .cpload t9 + li v0, __NR_statfs64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__statfs64)
diff --git a/libc/arch-mips/syscalls/__sync_file_range.S b/libc/arch-mips/syscalls/__sync_file_range.S new file mode 100644 index 0000000..79d41e0 --- /dev/null +++ b/libc/arch-mips/syscalls/__sync_file_range.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sync_file_range) + .set noreorder + .cpload t9 + li v0, __NR_sync_file_range + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__sync_file_range)
diff --git a/libc/arch-mips/syscalls/__timer_create.S b/libc/arch-mips/syscalls/__timer_create.S new file mode 100644 index 0000000..ef50749 --- /dev/null +++ b/libc/arch-mips/syscalls/__timer_create.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + .set noreorder + .cpload t9 + li v0, __NR_timer_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__timer_create)
diff --git a/libc/arch-mips/syscalls/__timer_delete.S b/libc/arch-mips/syscalls/__timer_delete.S new file mode 100644 index 0000000..5993ace --- /dev/null +++ b/libc/arch-mips/syscalls/__timer_delete.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + .set noreorder + .cpload t9 + li v0, __NR_timer_delete + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__timer_delete)
diff --git a/libc/arch-mips/syscalls/__timer_getoverrun.S b/libc/arch-mips/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..31234e5 --- /dev/null +++ b/libc/arch-mips/syscalls/__timer_getoverrun.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + .set noreorder + .cpload t9 + li v0, __NR_timer_getoverrun + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__timer_getoverrun)
diff --git a/libc/arch-mips/syscalls/__timer_gettime.S b/libc/arch-mips/syscalls/__timer_gettime.S new file mode 100644 index 0000000..38800d3 --- /dev/null +++ b/libc/arch-mips/syscalls/__timer_gettime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + .set noreorder + .cpload t9 + li v0, __NR_timer_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__timer_gettime)
diff --git a/libc/arch-mips/syscalls/__timer_settime.S b/libc/arch-mips/syscalls/__timer_settime.S new file mode 100644 index 0000000..73cea73 --- /dev/null +++ b/libc/arch-mips/syscalls/__timer_settime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + .set noreorder + .cpload t9 + li v0, __NR_timer_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__timer_settime)
diff --git a/libc/arch-mips/syscalls/__waitid.S b/libc/arch-mips/syscalls/__waitid.S new file mode 100644 index 0000000..9d17f8f --- /dev/null +++ b/libc/arch-mips/syscalls/__waitid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + .set noreorder + .cpload t9 + li v0, __NR_waitid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(__waitid)
diff --git a/libc/arch-mips/syscalls/_exit.S b/libc/arch-mips/syscalls/_exit.S new file mode 100644 index 0000000..6e97aac --- /dev/null +++ b/libc/arch-mips/syscalls/_exit.S
@@ -0,0 +1,21 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + .set noreorder + .cpload t9 + li v0, __NR_exit_group + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(_exit) + +ALIAS_SYMBOL(_Exit, _exit)
diff --git a/libc/arch-mips/syscalls/_flush_cache.S b/libc/arch-mips/syscalls/_flush_cache.S new file mode 100644 index 0000000..a4030e9 --- /dev/null +++ b/libc/arch-mips/syscalls/_flush_cache.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_flush_cache) + .set noreorder + .cpload t9 + li v0, __NR_cacheflush + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(_flush_cache)
diff --git a/libc/arch-mips/syscalls/acct.S b/libc/arch-mips/syscalls/acct.S new file mode 100644 index 0000000..e3a5ccd --- /dev/null +++ b/libc/arch-mips/syscalls/acct.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + .set noreorder + .cpload t9 + li v0, __NR_acct + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(acct)
diff --git a/libc/arch-mips/syscalls/adjtimex.S b/libc/arch-mips/syscalls/adjtimex.S new file mode 100644 index 0000000..fef215f --- /dev/null +++ b/libc/arch-mips/syscalls/adjtimex.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(adjtimex) + .set noreorder + .cpload t9 + li v0, __NR_adjtimex + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(adjtimex)
diff --git a/libc/arch-mips/syscalls/bind.S b/libc/arch-mips/syscalls/bind.S new file mode 100644 index 0000000..78fe2bb --- /dev/null +++ b/libc/arch-mips/syscalls/bind.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + .set noreorder + .cpload t9 + li v0, __NR_bind + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(bind)
diff --git a/libc/arch-mips/syscalls/capget.S b/libc/arch-mips/syscalls/capget.S new file mode 100644 index 0000000..0cbb626 --- /dev/null +++ b/libc/arch-mips/syscalls/capget.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + .set noreorder + .cpload t9 + li v0, __NR_capget + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(capget)
diff --git a/libc/arch-mips/syscalls/capset.S b/libc/arch-mips/syscalls/capset.S new file mode 100644 index 0000000..e811080 --- /dev/null +++ b/libc/arch-mips/syscalls/capset.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + .set noreorder + .cpload t9 + li v0, __NR_capset + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(capset)
diff --git a/libc/arch-mips/syscalls/chdir.S b/libc/arch-mips/syscalls/chdir.S new file mode 100644 index 0000000..82b7a2b --- /dev/null +++ b/libc/arch-mips/syscalls/chdir.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + .set noreorder + .cpload t9 + li v0, __NR_chdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(chdir)
diff --git a/libc/arch-mips/syscalls/chroot.S b/libc/arch-mips/syscalls/chroot.S new file mode 100644 index 0000000..e6a29fc --- /dev/null +++ b/libc/arch-mips/syscalls/chroot.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + .set noreorder + .cpload t9 + li v0, __NR_chroot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(chroot)
diff --git a/libc/arch-mips/syscalls/clock_adjtime.S b/libc/arch-mips/syscalls/clock_adjtime.S new file mode 100644 index 0000000..f8a4ce2 --- /dev/null +++ b/libc/arch-mips/syscalls/clock_adjtime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_adjtime) + .set noreorder + .cpload t9 + li v0, __NR_clock_adjtime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(clock_adjtime)
diff --git a/libc/arch-mips/syscalls/clock_getres.S b/libc/arch-mips/syscalls/clock_getres.S new file mode 100644 index 0000000..ac7c5c6 --- /dev/null +++ b/libc/arch-mips/syscalls/clock_getres.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + .set noreorder + .cpload t9 + li v0, __NR_clock_getres + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(clock_getres)
diff --git a/libc/arch-mips/syscalls/clock_gettime.S b/libc/arch-mips/syscalls/clock_gettime.S new file mode 100644 index 0000000..d227a06 --- /dev/null +++ b/libc/arch-mips/syscalls/clock_gettime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_gettime) + .set noreorder + .cpload t9 + li v0, __NR_clock_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(clock_gettime)
diff --git a/libc/arch-mips/syscalls/clock_settime.S b/libc/arch-mips/syscalls/clock_settime.S new file mode 100644 index 0000000..193bdc2 --- /dev/null +++ b/libc/arch-mips/syscalls/clock_settime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + .set noreorder + .cpload t9 + li v0, __NR_clock_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(clock_settime)
diff --git a/libc/arch-mips/syscalls/delete_module.S b/libc/arch-mips/syscalls/delete_module.S new file mode 100644 index 0000000..8c01c06 --- /dev/null +++ b/libc/arch-mips/syscalls/delete_module.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + .set noreorder + .cpload t9 + li v0, __NR_delete_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(delete_module)
diff --git a/libc/arch-mips/syscalls/dup.S b/libc/arch-mips/syscalls/dup.S new file mode 100644 index 0000000..b4dcd70 --- /dev/null +++ b/libc/arch-mips/syscalls/dup.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + .set noreorder + .cpload t9 + li v0, __NR_dup + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(dup)
diff --git a/libc/arch-mips/syscalls/dup3.S b/libc/arch-mips/syscalls/dup3.S new file mode 100644 index 0000000..1d9c236 --- /dev/null +++ b/libc/arch-mips/syscalls/dup3.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + .set noreorder + .cpload t9 + li v0, __NR_dup3 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(dup3)
diff --git a/libc/arch-mips/syscalls/epoll_create1.S b/libc/arch-mips/syscalls/epoll_create1.S new file mode 100644 index 0000000..8754879 --- /dev/null +++ b/libc/arch-mips/syscalls/epoll_create1.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + .set noreorder + .cpload t9 + li v0, __NR_epoll_create1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(epoll_create1)
diff --git a/libc/arch-mips/syscalls/epoll_ctl.S b/libc/arch-mips/syscalls/epoll_ctl.S new file mode 100644 index 0000000..14c9202 --- /dev/null +++ b/libc/arch-mips/syscalls/epoll_ctl.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + .set noreorder + .cpload t9 + li v0, __NR_epoll_ctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(epoll_ctl)
diff --git a/libc/arch-mips/syscalls/eventfd.S b/libc/arch-mips/syscalls/eventfd.S new file mode 100644 index 0000000..6494dbc --- /dev/null +++ b/libc/arch-mips/syscalls/eventfd.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + .set noreorder + .cpload t9 + li v0, __NR_eventfd2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(eventfd)
diff --git a/libc/arch-mips/syscalls/execve.S b/libc/arch-mips/syscalls/execve.S new file mode 100644 index 0000000..2d20b51 --- /dev/null +++ b/libc/arch-mips/syscalls/execve.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + .set noreorder + .cpload t9 + li v0, __NR_execve + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(execve)
diff --git a/libc/arch-mips/syscalls/fallocate64.S b/libc/arch-mips/syscalls/fallocate64.S new file mode 100644 index 0000000..5f05513 --- /dev/null +++ b/libc/arch-mips/syscalls/fallocate64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate64) + .set noreorder + .cpload t9 + li v0, __NR_fallocate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fallocate64)
diff --git a/libc/arch-mips/syscalls/fchdir.S b/libc/arch-mips/syscalls/fchdir.S new file mode 100644 index 0000000..d683baa --- /dev/null +++ b/libc/arch-mips/syscalls/fchdir.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + .set noreorder + .cpload t9 + li v0, __NR_fchdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fchdir)
diff --git a/libc/arch-mips/syscalls/fchown.S b/libc/arch-mips/syscalls/fchown.S new file mode 100644 index 0000000..1ac9451 --- /dev/null +++ b/libc/arch-mips/syscalls/fchown.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + .set noreorder + .cpload t9 + li v0, __NR_fchown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fchown)
diff --git a/libc/arch-mips/syscalls/fchownat.S b/libc/arch-mips/syscalls/fchownat.S new file mode 100644 index 0000000..be1a021 --- /dev/null +++ b/libc/arch-mips/syscalls/fchownat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + .set noreorder + .cpload t9 + li v0, __NR_fchownat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fchownat)
diff --git a/libc/arch-mips/syscalls/fdatasync.S b/libc/arch-mips/syscalls/fdatasync.S new file mode 100644 index 0000000..24d6541 --- /dev/null +++ b/libc/arch-mips/syscalls/fdatasync.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + .set noreorder + .cpload t9 + li v0, __NR_fdatasync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fdatasync)
diff --git a/libc/arch-mips/syscalls/flock.S b/libc/arch-mips/syscalls/flock.S new file mode 100644 index 0000000..8d70c9e --- /dev/null +++ b/libc/arch-mips/syscalls/flock.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + .set noreorder + .cpload t9 + li v0, __NR_flock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(flock)
diff --git a/libc/arch-mips/syscalls/fremovexattr.S b/libc/arch-mips/syscalls/fremovexattr.S new file mode 100644 index 0000000..fba2d6d --- /dev/null +++ b/libc/arch-mips/syscalls/fremovexattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + .set noreorder + .cpload t9 + li v0, __NR_fremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fremovexattr)
diff --git a/libc/arch-mips/syscalls/fstat64.S b/libc/arch-mips/syscalls/fstat64.S new file mode 100644 index 0000000..16e2791 --- /dev/null +++ b/libc/arch-mips/syscalls/fstat64.S
@@ -0,0 +1,21 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstat64) + .set noreorder + .cpload t9 + li v0, __NR_fstat64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fstat64) + +ALIAS_SYMBOL(fstat, fstat64)
diff --git a/libc/arch-mips/syscalls/fstatat64.S b/libc/arch-mips/syscalls/fstatat64.S new file mode 100644 index 0000000..ebcf6b0 --- /dev/null +++ b/libc/arch-mips/syscalls/fstatat64.S
@@ -0,0 +1,21 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatat64) + .set noreorder + .cpload t9 + li v0, __NR_fstatat64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fstatat64) + +ALIAS_SYMBOL(fstatat, fstatat64)
diff --git a/libc/arch-mips/syscalls/fsync.S b/libc/arch-mips/syscalls/fsync.S new file mode 100644 index 0000000..819f0f2 --- /dev/null +++ b/libc/arch-mips/syscalls/fsync.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + .set noreorder + .cpload t9 + li v0, __NR_fsync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(fsync)
diff --git a/libc/arch-mips/syscalls/ftruncate64.S b/libc/arch-mips/syscalls/ftruncate64.S new file mode 100644 index 0000000..059ff77 --- /dev/null +++ b/libc/arch-mips/syscalls/ftruncate64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate64) + .set noreorder + .cpload t9 + li v0, __NR_ftruncate64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(ftruncate64)
diff --git a/libc/arch-mips/syscalls/getegid.S b/libc/arch-mips/syscalls/getegid.S new file mode 100644 index 0000000..8ae2d1e --- /dev/null +++ b/libc/arch-mips/syscalls/getegid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + .set noreorder + .cpload t9 + li v0, __NR_getegid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getegid)
diff --git a/libc/arch-mips/syscalls/geteuid.S b/libc/arch-mips/syscalls/geteuid.S new file mode 100644 index 0000000..cf5cf6c --- /dev/null +++ b/libc/arch-mips/syscalls/geteuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + .set noreorder + .cpload t9 + li v0, __NR_geteuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(geteuid)
diff --git a/libc/arch-mips/syscalls/getgid.S b/libc/arch-mips/syscalls/getgid.S new file mode 100644 index 0000000..9bd1fc3 --- /dev/null +++ b/libc/arch-mips/syscalls/getgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + .set noreorder + .cpload t9 + li v0, __NR_getgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getgid)
diff --git a/libc/arch-mips/syscalls/getgroups.S b/libc/arch-mips/syscalls/getgroups.S new file mode 100644 index 0000000..2eda185 --- /dev/null +++ b/libc/arch-mips/syscalls/getgroups.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + .set noreorder + .cpload t9 + li v0, __NR_getgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getgroups)
diff --git a/libc/arch-mips/syscalls/getitimer.S b/libc/arch-mips/syscalls/getitimer.S new file mode 100644 index 0000000..2e382c7 --- /dev/null +++ b/libc/arch-mips/syscalls/getitimer.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + .set noreorder + .cpload t9 + li v0, __NR_getitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getitimer)
diff --git a/libc/arch-mips/syscalls/getpeername.S b/libc/arch-mips/syscalls/getpeername.S new file mode 100644 index 0000000..8642798 --- /dev/null +++ b/libc/arch-mips/syscalls/getpeername.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + .set noreorder + .cpload t9 + li v0, __NR_getpeername + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getpeername)
diff --git a/libc/arch-mips/syscalls/getpgid.S b/libc/arch-mips/syscalls/getpgid.S new file mode 100644 index 0000000..562b9ce --- /dev/null +++ b/libc/arch-mips/syscalls/getpgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + .set noreorder + .cpload t9 + li v0, __NR_getpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getpgid)
diff --git a/libc/arch-mips/syscalls/getppid.S b/libc/arch-mips/syscalls/getppid.S new file mode 100644 index 0000000..afff0b9 --- /dev/null +++ b/libc/arch-mips/syscalls/getppid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + .set noreorder + .cpload t9 + li v0, __NR_getppid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getppid)
diff --git a/libc/arch-mips/syscalls/getresgid.S b/libc/arch-mips/syscalls/getresgid.S new file mode 100644 index 0000000..248d3f9 --- /dev/null +++ b/libc/arch-mips/syscalls/getresgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + .set noreorder + .cpload t9 + li v0, __NR_getresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getresgid)
diff --git a/libc/arch-mips/syscalls/getresuid.S b/libc/arch-mips/syscalls/getresuid.S new file mode 100644 index 0000000..924b6cd --- /dev/null +++ b/libc/arch-mips/syscalls/getresuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + .set noreorder + .cpload t9 + li v0, __NR_getresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getresuid)
diff --git a/libc/arch-mips/syscalls/getrlimit.S b/libc/arch-mips/syscalls/getrlimit.S new file mode 100644 index 0000000..19570d6 --- /dev/null +++ b/libc/arch-mips/syscalls/getrlimit.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + .set noreorder + .cpload t9 + li v0, __NR_getrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getrlimit)
diff --git a/libc/arch-mips/syscalls/getrusage.S b/libc/arch-mips/syscalls/getrusage.S new file mode 100644 index 0000000..75bc8bc --- /dev/null +++ b/libc/arch-mips/syscalls/getrusage.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + .set noreorder + .cpload t9 + li v0, __NR_getrusage + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getrusage)
diff --git a/libc/arch-mips/syscalls/getsid.S b/libc/arch-mips/syscalls/getsid.S new file mode 100644 index 0000000..6436ecd --- /dev/null +++ b/libc/arch-mips/syscalls/getsid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + .set noreorder + .cpload t9 + li v0, __NR_getsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getsid)
diff --git a/libc/arch-mips/syscalls/getsockname.S b/libc/arch-mips/syscalls/getsockname.S new file mode 100644 index 0000000..ffadd92 --- /dev/null +++ b/libc/arch-mips/syscalls/getsockname.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + .set noreorder + .cpload t9 + li v0, __NR_getsockname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getsockname)
diff --git a/libc/arch-mips/syscalls/getsockopt.S b/libc/arch-mips/syscalls/getsockopt.S new file mode 100644 index 0000000..6ebe15e --- /dev/null +++ b/libc/arch-mips/syscalls/getsockopt.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + .set noreorder + .cpload t9 + li v0, __NR_getsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getsockopt)
diff --git a/libc/arch-mips/syscalls/gettimeofday.S b/libc/arch-mips/syscalls/gettimeofday.S new file mode 100644 index 0000000..672faa3 --- /dev/null +++ b/libc/arch-mips/syscalls/gettimeofday.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(gettimeofday) + .set noreorder + .cpload t9 + li v0, __NR_gettimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(gettimeofday)
diff --git a/libc/arch-mips/syscalls/getuid.S b/libc/arch-mips/syscalls/getuid.S new file mode 100644 index 0000000..5858632 --- /dev/null +++ b/libc/arch-mips/syscalls/getuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + .set noreorder + .cpload t9 + li v0, __NR_getuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getuid)
diff --git a/libc/arch-mips/syscalls/getxattr.S b/libc/arch-mips/syscalls/getxattr.S new file mode 100644 index 0000000..28c7fe6 --- /dev/null +++ b/libc/arch-mips/syscalls/getxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + .set noreorder + .cpload t9 + li v0, __NR_getxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(getxattr)
diff --git a/libc/arch-mips/syscalls/init_module.S b/libc/arch-mips/syscalls/init_module.S new file mode 100644 index 0000000..989614a --- /dev/null +++ b/libc/arch-mips/syscalls/init_module.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + .set noreorder + .cpload t9 + li v0, __NR_init_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(init_module)
diff --git a/libc/arch-mips/syscalls/inotify_add_watch.S b/libc/arch-mips/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..7d3315f --- /dev/null +++ b/libc/arch-mips/syscalls/inotify_add_watch.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + .set noreorder + .cpload t9 + li v0, __NR_inotify_add_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(inotify_add_watch)
diff --git a/libc/arch-mips/syscalls/inotify_init1.S b/libc/arch-mips/syscalls/inotify_init1.S new file mode 100644 index 0000000..e4ec266 --- /dev/null +++ b/libc/arch-mips/syscalls/inotify_init1.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + .set noreorder + .cpload t9 + li v0, __NR_inotify_init1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(inotify_init1)
diff --git a/libc/arch-mips/syscalls/inotify_rm_watch.S b/libc/arch-mips/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..eec9856 --- /dev/null +++ b/libc/arch-mips/syscalls/inotify_rm_watch.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + .set noreorder + .cpload t9 + li v0, __NR_inotify_rm_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(inotify_rm_watch)
diff --git a/libc/arch-mips/syscalls/kill.S b/libc/arch-mips/syscalls/kill.S new file mode 100644 index 0000000..415da73 --- /dev/null +++ b/libc/arch-mips/syscalls/kill.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + .set noreorder + .cpload t9 + li v0, __NR_kill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(kill)
diff --git a/libc/arch-mips/syscalls/klogctl.S b/libc/arch-mips/syscalls/klogctl.S new file mode 100644 index 0000000..123d8a0 --- /dev/null +++ b/libc/arch-mips/syscalls/klogctl.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + .set noreorder + .cpload t9 + li v0, __NR_syslog + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(klogctl)
diff --git a/libc/arch-mips/syscalls/lgetxattr.S b/libc/arch-mips/syscalls/lgetxattr.S new file mode 100644 index 0000000..a9916d9 --- /dev/null +++ b/libc/arch-mips/syscalls/lgetxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + .set noreorder + .cpload t9 + li v0, __NR_lgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(lgetxattr)
diff --git a/libc/arch-mips/syscalls/linkat.S b/libc/arch-mips/syscalls/linkat.S new file mode 100644 index 0000000..a05a995 --- /dev/null +++ b/libc/arch-mips/syscalls/linkat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + .set noreorder + .cpload t9 + li v0, __NR_linkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(linkat)
diff --git a/libc/arch-mips/syscalls/listen.S b/libc/arch-mips/syscalls/listen.S new file mode 100644 index 0000000..7bb2ec8 --- /dev/null +++ b/libc/arch-mips/syscalls/listen.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + .set noreorder + .cpload t9 + li v0, __NR_listen + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(listen)
diff --git a/libc/arch-mips/syscalls/listxattr.S b/libc/arch-mips/syscalls/listxattr.S new file mode 100644 index 0000000..c160178 --- /dev/null +++ b/libc/arch-mips/syscalls/listxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + .set noreorder + .cpload t9 + li v0, __NR_listxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(listxattr)
diff --git a/libc/arch-mips/syscalls/llistxattr.S b/libc/arch-mips/syscalls/llistxattr.S new file mode 100644 index 0000000..9bf05b0 --- /dev/null +++ b/libc/arch-mips/syscalls/llistxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + .set noreorder + .cpload t9 + li v0, __NR_llistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(llistxattr)
diff --git a/libc/arch-mips/syscalls/lremovexattr.S b/libc/arch-mips/syscalls/lremovexattr.S new file mode 100644 index 0000000..fe73ddb --- /dev/null +++ b/libc/arch-mips/syscalls/lremovexattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + .set noreorder + .cpload t9 + li v0, __NR_lremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(lremovexattr)
diff --git a/libc/arch-mips/syscalls/lseek.S b/libc/arch-mips/syscalls/lseek.S new file mode 100644 index 0000000..6d6b4e5 --- /dev/null +++ b/libc/arch-mips/syscalls/lseek.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + .set noreorder + .cpload t9 + li v0, __NR_lseek + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(lseek)
diff --git a/libc/arch-mips/syscalls/lsetxattr.S b/libc/arch-mips/syscalls/lsetxattr.S new file mode 100644 index 0000000..69ea0a2 --- /dev/null +++ b/libc/arch-mips/syscalls/lsetxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + .set noreorder + .cpload t9 + li v0, __NR_lsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(lsetxattr)
diff --git a/libc/arch-mips/syscalls/madvise.S b/libc/arch-mips/syscalls/madvise.S new file mode 100644 index 0000000..7d67b80 --- /dev/null +++ b/libc/arch-mips/syscalls/madvise.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + .set noreorder + .cpload t9 + li v0, __NR_madvise + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(madvise)
diff --git a/libc/arch-mips/syscalls/mincore.S b/libc/arch-mips/syscalls/mincore.S new file mode 100644 index 0000000..96f5e29 --- /dev/null +++ b/libc/arch-mips/syscalls/mincore.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + .set noreorder + .cpload t9 + li v0, __NR_mincore + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mincore)
diff --git a/libc/arch-mips/syscalls/mkdirat.S b/libc/arch-mips/syscalls/mkdirat.S new file mode 100644 index 0000000..55dd976 --- /dev/null +++ b/libc/arch-mips/syscalls/mkdirat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + .set noreorder + .cpload t9 + li v0, __NR_mkdirat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mkdirat)
diff --git a/libc/arch-mips/syscalls/mknodat.S b/libc/arch-mips/syscalls/mknodat.S new file mode 100644 index 0000000..1a03a8e --- /dev/null +++ b/libc/arch-mips/syscalls/mknodat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + .set noreorder + .cpload t9 + li v0, __NR_mknodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mknodat)
diff --git a/libc/arch-mips/syscalls/mlock.S b/libc/arch-mips/syscalls/mlock.S new file mode 100644 index 0000000..3cf7c1b --- /dev/null +++ b/libc/arch-mips/syscalls/mlock.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + .set noreorder + .cpload t9 + li v0, __NR_mlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mlock)
diff --git a/libc/arch-mips/syscalls/mlockall.S b/libc/arch-mips/syscalls/mlockall.S new file mode 100644 index 0000000..3b90f41 --- /dev/null +++ b/libc/arch-mips/syscalls/mlockall.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + .set noreorder + .cpload t9 + li v0, __NR_mlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mlockall)
diff --git a/libc/arch-mips/syscalls/mount.S b/libc/arch-mips/syscalls/mount.S new file mode 100644 index 0000000..fdf299f --- /dev/null +++ b/libc/arch-mips/syscalls/mount.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + .set noreorder + .cpload t9 + li v0, __NR_mount + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mount)
diff --git a/libc/arch-mips/syscalls/mprotect.S b/libc/arch-mips/syscalls/mprotect.S new file mode 100644 index 0000000..5618310 --- /dev/null +++ b/libc/arch-mips/syscalls/mprotect.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + .set noreorder + .cpload t9 + li v0, __NR_mprotect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(mprotect)
diff --git a/libc/arch-mips/syscalls/msync.S b/libc/arch-mips/syscalls/msync.S new file mode 100644 index 0000000..fb7462d --- /dev/null +++ b/libc/arch-mips/syscalls/msync.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + .set noreorder + .cpload t9 + li v0, __NR_msync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(msync)
diff --git a/libc/arch-mips/syscalls/munlock.S b/libc/arch-mips/syscalls/munlock.S new file mode 100644 index 0000000..6c65c02 --- /dev/null +++ b/libc/arch-mips/syscalls/munlock.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + .set noreorder + .cpload t9 + li v0, __NR_munlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(munlock)
diff --git a/libc/arch-mips/syscalls/munlockall.S b/libc/arch-mips/syscalls/munlockall.S new file mode 100644 index 0000000..e30dddc --- /dev/null +++ b/libc/arch-mips/syscalls/munlockall.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + .set noreorder + .cpload t9 + li v0, __NR_munlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(munlockall)
diff --git a/libc/arch-mips/syscalls/munmap.S b/libc/arch-mips/syscalls/munmap.S new file mode 100644 index 0000000..903edde --- /dev/null +++ b/libc/arch-mips/syscalls/munmap.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + .set noreorder + .cpload t9 + li v0, __NR_munmap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(munmap)
diff --git a/libc/arch-mips/syscalls/nanosleep.S b/libc/arch-mips/syscalls/nanosleep.S new file mode 100644 index 0000000..8dae88b --- /dev/null +++ b/libc/arch-mips/syscalls/nanosleep.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + .set noreorder + .cpload t9 + li v0, __NR_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(nanosleep)
diff --git a/libc/arch-mips/syscalls/personality.S b/libc/arch-mips/syscalls/personality.S new file mode 100644 index 0000000..2f51d39 --- /dev/null +++ b/libc/arch-mips/syscalls/personality.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + .set noreorder + .cpload t9 + li v0, __NR_personality + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(personality)
diff --git a/libc/arch-mips/syscalls/pipe2.S b/libc/arch-mips/syscalls/pipe2.S new file mode 100644 index 0000000..b06309c --- /dev/null +++ b/libc/arch-mips/syscalls/pipe2.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + .set noreorder + .cpload t9 + li v0, __NR_pipe2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(pipe2)
diff --git a/libc/arch-mips/syscalls/prctl.S b/libc/arch-mips/syscalls/prctl.S new file mode 100644 index 0000000..71544ee --- /dev/null +++ b/libc/arch-mips/syscalls/prctl.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + .set noreorder + .cpload t9 + li v0, __NR_prctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(prctl)
diff --git a/libc/arch-mips/syscalls/pread64.S b/libc/arch-mips/syscalls/pread64.S new file mode 100644 index 0000000..9e7248b --- /dev/null +++ b/libc/arch-mips/syscalls/pread64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + .set noreorder + .cpload t9 + li v0, __NR_pread64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(pread64)
diff --git a/libc/arch-mips/syscalls/prlimit64.S b/libc/arch-mips/syscalls/prlimit64.S new file mode 100644 index 0000000..ca913df --- /dev/null +++ b/libc/arch-mips/syscalls/prlimit64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + .set noreorder + .cpload t9 + li v0, __NR_prlimit64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(prlimit64)
diff --git a/libc/arch-mips/syscalls/process_vm_readv.S b/libc/arch-mips/syscalls/process_vm_readv.S new file mode 100644 index 0000000..22b74f0 --- /dev/null +++ b/libc/arch-mips/syscalls/process_vm_readv.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_readv) + .set noreorder + .cpload t9 + li v0, __NR_process_vm_readv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(process_vm_readv)
diff --git a/libc/arch-mips/syscalls/process_vm_writev.S b/libc/arch-mips/syscalls/process_vm_writev.S new file mode 100644 index 0000000..dd1dc4b --- /dev/null +++ b/libc/arch-mips/syscalls/process_vm_writev.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_writev) + .set noreorder + .cpload t9 + li v0, __NR_process_vm_writev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(process_vm_writev)
diff --git a/libc/arch-mips/syscalls/pwrite64.S b/libc/arch-mips/syscalls/pwrite64.S new file mode 100644 index 0000000..ac206aa --- /dev/null +++ b/libc/arch-mips/syscalls/pwrite64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + .set noreorder + .cpload t9 + li v0, __NR_pwrite64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(pwrite64)
diff --git a/libc/arch-mips/syscalls/quotactl.S b/libc/arch-mips/syscalls/quotactl.S new file mode 100644 index 0000000..fef336a --- /dev/null +++ b/libc/arch-mips/syscalls/quotactl.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(quotactl) + .set noreorder + .cpload t9 + li v0, __NR_quotactl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(quotactl)
diff --git a/libc/arch-mips/syscalls/read.S b/libc/arch-mips/syscalls/read.S new file mode 100644 index 0000000..1355b66 --- /dev/null +++ b/libc/arch-mips/syscalls/read.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + .set noreorder + .cpload t9 + li v0, __NR_read + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(read)
diff --git a/libc/arch-mips/syscalls/readahead.S b/libc/arch-mips/syscalls/readahead.S new file mode 100644 index 0000000..b28df08 --- /dev/null +++ b/libc/arch-mips/syscalls/readahead.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + .set noreorder + .cpload t9 + li v0, __NR_readahead + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(readahead)
diff --git a/libc/arch-mips/syscalls/readlinkat.S b/libc/arch-mips/syscalls/readlinkat.S new file mode 100644 index 0000000..5cf84a2 --- /dev/null +++ b/libc/arch-mips/syscalls/readlinkat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + .set noreorder + .cpload t9 + li v0, __NR_readlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(readlinkat)
diff --git a/libc/arch-mips/syscalls/readv.S b/libc/arch-mips/syscalls/readv.S new file mode 100644 index 0000000..57952a0 --- /dev/null +++ b/libc/arch-mips/syscalls/readv.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + .set noreorder + .cpload t9 + li v0, __NR_readv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(readv)
diff --git a/libc/arch-mips/syscalls/recvfrom.S b/libc/arch-mips/syscalls/recvfrom.S new file mode 100644 index 0000000..707ba4b --- /dev/null +++ b/libc/arch-mips/syscalls/recvfrom.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + .set noreorder + .cpload t9 + li v0, __NR_recvfrom + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(recvfrom)
diff --git a/libc/arch-mips/syscalls/recvmmsg.S b/libc/arch-mips/syscalls/recvmmsg.S new file mode 100644 index 0000000..796d0d8 --- /dev/null +++ b/libc/arch-mips/syscalls/recvmmsg.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + .set noreorder + .cpload t9 + li v0, __NR_recvmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(recvmmsg)
diff --git a/libc/arch-mips/syscalls/recvmsg.S b/libc/arch-mips/syscalls/recvmsg.S new file mode 100644 index 0000000..fdcac32 --- /dev/null +++ b/libc/arch-mips/syscalls/recvmsg.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + .set noreorder + .cpload t9 + li v0, __NR_recvmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(recvmsg)
diff --git a/libc/arch-mips/syscalls/removexattr.S b/libc/arch-mips/syscalls/removexattr.S new file mode 100644 index 0000000..d99e1ae --- /dev/null +++ b/libc/arch-mips/syscalls/removexattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + .set noreorder + .cpload t9 + li v0, __NR_removexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(removexattr)
diff --git a/libc/arch-mips/syscalls/renameat.S b/libc/arch-mips/syscalls/renameat.S new file mode 100644 index 0000000..c865d74 --- /dev/null +++ b/libc/arch-mips/syscalls/renameat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + .set noreorder + .cpload t9 + li v0, __NR_renameat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(renameat)
diff --git a/libc/arch-mips/syscalls/sched_get_priority_max.S b/libc/arch-mips/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..1c73af6 --- /dev/null +++ b/libc/arch-mips/syscalls/sched_get_priority_max.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + .set noreorder + .cpload t9 + li v0, __NR_sched_get_priority_max + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_get_priority_max)
diff --git a/libc/arch-mips/syscalls/sched_get_priority_min.S b/libc/arch-mips/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..b69b72b --- /dev/null +++ b/libc/arch-mips/syscalls/sched_get_priority_min.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + .set noreorder + .cpload t9 + li v0, __NR_sched_get_priority_min + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_get_priority_min)
diff --git a/libc/arch-mips/syscalls/sched_getparam.S b/libc/arch-mips/syscalls/sched_getparam.S new file mode 100644 index 0000000..387257a --- /dev/null +++ b/libc/arch-mips/syscalls/sched_getparam.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + .set noreorder + .cpload t9 + li v0, __NR_sched_getparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_getparam)
diff --git a/libc/arch-mips/syscalls/sched_getscheduler.S b/libc/arch-mips/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..9b293db --- /dev/null +++ b/libc/arch-mips/syscalls/sched_getscheduler.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + .set noreorder + .cpload t9 + li v0, __NR_sched_getscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_getscheduler)
diff --git a/libc/arch-mips/syscalls/sched_rr_get_interval.S b/libc/arch-mips/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..3d7b8a8 --- /dev/null +++ b/libc/arch-mips/syscalls/sched_rr_get_interval.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + .set noreorder + .cpload t9 + li v0, __NR_sched_rr_get_interval + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_rr_get_interval)
diff --git a/libc/arch-mips/syscalls/sched_setaffinity.S b/libc/arch-mips/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..a0e9f6c --- /dev/null +++ b/libc/arch-mips/syscalls/sched_setaffinity.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + .set noreorder + .cpload t9 + li v0, __NR_sched_setaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_setaffinity)
diff --git a/libc/arch-mips/syscalls/sched_setparam.S b/libc/arch-mips/syscalls/sched_setparam.S new file mode 100644 index 0000000..a8a8982 --- /dev/null +++ b/libc/arch-mips/syscalls/sched_setparam.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + .set noreorder + .cpload t9 + li v0, __NR_sched_setparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_setparam)
diff --git a/libc/arch-mips/syscalls/sched_setscheduler.S b/libc/arch-mips/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..a2cd7fa --- /dev/null +++ b/libc/arch-mips/syscalls/sched_setscheduler.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + .set noreorder + .cpload t9 + li v0, __NR_sched_setscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_setscheduler)
diff --git a/libc/arch-mips/syscalls/sched_yield.S b/libc/arch-mips/syscalls/sched_yield.S new file mode 100644 index 0000000..295266f --- /dev/null +++ b/libc/arch-mips/syscalls/sched_yield.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + .set noreorder + .cpload t9 + li v0, __NR_sched_yield + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sched_yield)
diff --git a/libc/arch-mips/syscalls/sendfile.S b/libc/arch-mips/syscalls/sendfile.S new file mode 100644 index 0000000..5e5e887 --- /dev/null +++ b/libc/arch-mips/syscalls/sendfile.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + .set noreorder + .cpload t9 + li v0, __NR_sendfile + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sendfile)
diff --git a/libc/arch-mips/syscalls/sendfile64.S b/libc/arch-mips/syscalls/sendfile64.S new file mode 100644 index 0000000..78f1908 --- /dev/null +++ b/libc/arch-mips/syscalls/sendfile64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile64) + .set noreorder + .cpload t9 + li v0, __NR_sendfile64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sendfile64)
diff --git a/libc/arch-mips/syscalls/sendmmsg.S b/libc/arch-mips/syscalls/sendmmsg.S new file mode 100644 index 0000000..1dc7576 --- /dev/null +++ b/libc/arch-mips/syscalls/sendmmsg.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + .set noreorder + .cpload t9 + li v0, __NR_sendmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sendmmsg)
diff --git a/libc/arch-mips/syscalls/sendmsg.S b/libc/arch-mips/syscalls/sendmsg.S new file mode 100644 index 0000000..88c653e --- /dev/null +++ b/libc/arch-mips/syscalls/sendmsg.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + .set noreorder + .cpload t9 + li v0, __NR_sendmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sendmsg)
diff --git a/libc/arch-mips/syscalls/sendto.S b/libc/arch-mips/syscalls/sendto.S new file mode 100644 index 0000000..ef3fa9f --- /dev/null +++ b/libc/arch-mips/syscalls/sendto.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + .set noreorder + .cpload t9 + li v0, __NR_sendto + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sendto)
diff --git a/libc/arch-mips/syscalls/setdomainname.S b/libc/arch-mips/syscalls/setdomainname.S new file mode 100644 index 0000000..ec0504c --- /dev/null +++ b/libc/arch-mips/syscalls/setdomainname.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setdomainname) + .set noreorder + .cpload t9 + li v0, __NR_setdomainname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setdomainname)
diff --git a/libc/arch-mips/syscalls/setfsgid.S b/libc/arch-mips/syscalls/setfsgid.S new file mode 100644 index 0000000..158d2c0 --- /dev/null +++ b/libc/arch-mips/syscalls/setfsgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + .set noreorder + .cpload t9 + li v0, __NR_setfsgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setfsgid)
diff --git a/libc/arch-mips/syscalls/setfsuid.S b/libc/arch-mips/syscalls/setfsuid.S new file mode 100644 index 0000000..f76fd17 --- /dev/null +++ b/libc/arch-mips/syscalls/setfsuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + .set noreorder + .cpload t9 + li v0, __NR_setfsuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setfsuid)
diff --git a/libc/arch-mips/syscalls/setgid.S b/libc/arch-mips/syscalls/setgid.S new file mode 100644 index 0000000..44127cd --- /dev/null +++ b/libc/arch-mips/syscalls/setgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + .set noreorder + .cpload t9 + li v0, __NR_setgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setgid)
diff --git a/libc/arch-mips/syscalls/setgroups.S b/libc/arch-mips/syscalls/setgroups.S new file mode 100644 index 0000000..be4dc13 --- /dev/null +++ b/libc/arch-mips/syscalls/setgroups.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + .set noreorder + .cpload t9 + li v0, __NR_setgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setgroups)
diff --git a/libc/arch-mips/syscalls/sethostname.S b/libc/arch-mips/syscalls/sethostname.S new file mode 100644 index 0000000..2987b52 --- /dev/null +++ b/libc/arch-mips/syscalls/sethostname.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sethostname) + .set noreorder + .cpload t9 + li v0, __NR_sethostname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sethostname)
diff --git a/libc/arch-mips/syscalls/setitimer.S b/libc/arch-mips/syscalls/setitimer.S new file mode 100644 index 0000000..968b453 --- /dev/null +++ b/libc/arch-mips/syscalls/setitimer.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + .set noreorder + .cpload t9 + li v0, __NR_setitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setitimer)
diff --git a/libc/arch-mips/syscalls/setns.S b/libc/arch-mips/syscalls/setns.S new file mode 100644 index 0000000..a9270ec --- /dev/null +++ b/libc/arch-mips/syscalls/setns.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + .set noreorder + .cpload t9 + li v0, __NR_setns + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setns)
diff --git a/libc/arch-mips/syscalls/setpgid.S b/libc/arch-mips/syscalls/setpgid.S new file mode 100644 index 0000000..d2db62f --- /dev/null +++ b/libc/arch-mips/syscalls/setpgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + .set noreorder + .cpload t9 + li v0, __NR_setpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setpgid)
diff --git a/libc/arch-mips/syscalls/setpriority.S b/libc/arch-mips/syscalls/setpriority.S new file mode 100644 index 0000000..9b68335 --- /dev/null +++ b/libc/arch-mips/syscalls/setpriority.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + .set noreorder + .cpload t9 + li v0, __NR_setpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setpriority)
diff --git a/libc/arch-mips/syscalls/setregid.S b/libc/arch-mips/syscalls/setregid.S new file mode 100644 index 0000000..6b7474c --- /dev/null +++ b/libc/arch-mips/syscalls/setregid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + .set noreorder + .cpload t9 + li v0, __NR_setregid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setregid)
diff --git a/libc/arch-mips/syscalls/setresgid.S b/libc/arch-mips/syscalls/setresgid.S new file mode 100644 index 0000000..223a0d0 --- /dev/null +++ b/libc/arch-mips/syscalls/setresgid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + .set noreorder + .cpload t9 + li v0, __NR_setresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setresgid)
diff --git a/libc/arch-mips/syscalls/setresuid.S b/libc/arch-mips/syscalls/setresuid.S new file mode 100644 index 0000000..1f99682 --- /dev/null +++ b/libc/arch-mips/syscalls/setresuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + .set noreorder + .cpload t9 + li v0, __NR_setresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setresuid)
diff --git a/libc/arch-mips/syscalls/setreuid.S b/libc/arch-mips/syscalls/setreuid.S new file mode 100644 index 0000000..fa9c3d2 --- /dev/null +++ b/libc/arch-mips/syscalls/setreuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + .set noreorder + .cpload t9 + li v0, __NR_setreuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setreuid)
diff --git a/libc/arch-mips/syscalls/setrlimit.S b/libc/arch-mips/syscalls/setrlimit.S new file mode 100644 index 0000000..016e24c --- /dev/null +++ b/libc/arch-mips/syscalls/setrlimit.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + .set noreorder + .cpload t9 + li v0, __NR_setrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setrlimit)
diff --git a/libc/arch-mips/syscalls/setsid.S b/libc/arch-mips/syscalls/setsid.S new file mode 100644 index 0000000..9f3cb48 --- /dev/null +++ b/libc/arch-mips/syscalls/setsid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + .set noreorder + .cpload t9 + li v0, __NR_setsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setsid)
diff --git a/libc/arch-mips/syscalls/setsockopt.S b/libc/arch-mips/syscalls/setsockopt.S new file mode 100644 index 0000000..b2368a1 --- /dev/null +++ b/libc/arch-mips/syscalls/setsockopt.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + .set noreorder + .cpload t9 + li v0, __NR_setsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setsockopt)
diff --git a/libc/arch-mips/syscalls/settimeofday.S b/libc/arch-mips/syscalls/settimeofday.S new file mode 100644 index 0000000..e3a5a06 --- /dev/null +++ b/libc/arch-mips/syscalls/settimeofday.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + .set noreorder + .cpload t9 + li v0, __NR_settimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(settimeofday)
diff --git a/libc/arch-mips/syscalls/setuid.S b/libc/arch-mips/syscalls/setuid.S new file mode 100644 index 0000000..ff3da0a --- /dev/null +++ b/libc/arch-mips/syscalls/setuid.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + .set noreorder + .cpload t9 + li v0, __NR_setuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setuid)
diff --git a/libc/arch-mips/syscalls/setxattr.S b/libc/arch-mips/syscalls/setxattr.S new file mode 100644 index 0000000..5b3a241 --- /dev/null +++ b/libc/arch-mips/syscalls/setxattr.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + .set noreorder + .cpload t9 + li v0, __NR_setxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(setxattr)
diff --git a/libc/arch-mips/syscalls/shutdown.S b/libc/arch-mips/syscalls/shutdown.S new file mode 100644 index 0000000..5db046f --- /dev/null +++ b/libc/arch-mips/syscalls/shutdown.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + .set noreorder + .cpload t9 + li v0, __NR_shutdown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(shutdown)
diff --git a/libc/arch-mips/syscalls/sigaltstack.S b/libc/arch-mips/syscalls/sigaltstack.S new file mode 100644 index 0000000..f543759 --- /dev/null +++ b/libc/arch-mips/syscalls/sigaltstack.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + .set noreorder + .cpload t9 + li v0, __NR_sigaltstack + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sigaltstack)
diff --git a/libc/arch-mips/syscalls/socketpair.S b/libc/arch-mips/syscalls/socketpair.S new file mode 100644 index 0000000..7f85da3 --- /dev/null +++ b/libc/arch-mips/syscalls/socketpair.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + .set noreorder + .cpload t9 + li v0, __NR_socketpair + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(socketpair)
diff --git a/libc/arch-mips/syscalls/splice.S b/libc/arch-mips/syscalls/splice.S new file mode 100644 index 0000000..a55b7e8 --- /dev/null +++ b/libc/arch-mips/syscalls/splice.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + .set noreorder + .cpload t9 + li v0, __NR_splice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(splice)
diff --git a/libc/arch-mips/syscalls/swapoff.S b/libc/arch-mips/syscalls/swapoff.S new file mode 100644 index 0000000..ce782d0 --- /dev/null +++ b/libc/arch-mips/syscalls/swapoff.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + .set noreorder + .cpload t9 + li v0, __NR_swapoff + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(swapoff)
diff --git a/libc/arch-mips/syscalls/swapon.S b/libc/arch-mips/syscalls/swapon.S new file mode 100644 index 0000000..127c3a8 --- /dev/null +++ b/libc/arch-mips/syscalls/swapon.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + .set noreorder + .cpload t9 + li v0, __NR_swapon + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(swapon)
diff --git a/libc/arch-mips/syscalls/symlinkat.S b/libc/arch-mips/syscalls/symlinkat.S new file mode 100644 index 0000000..b0690a4 --- /dev/null +++ b/libc/arch-mips/syscalls/symlinkat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + .set noreorder + .cpload t9 + li v0, __NR_symlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(symlinkat)
diff --git a/libc/arch-mips/syscalls/sync.S b/libc/arch-mips/syscalls/sync.S new file mode 100644 index 0000000..8858e74 --- /dev/null +++ b/libc/arch-mips/syscalls/sync.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sync) + .set noreorder + .cpload t9 + li v0, __NR_sync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sync)
diff --git a/libc/arch-mips/syscalls/sysinfo.S b/libc/arch-mips/syscalls/sysinfo.S new file mode 100644 index 0000000..beefc0e --- /dev/null +++ b/libc/arch-mips/syscalls/sysinfo.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sysinfo) + .set noreorder + .cpload t9 + li v0, __NR_sysinfo + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(sysinfo)
diff --git a/libc/arch-mips/syscalls/tee.S b/libc/arch-mips/syscalls/tee.S new file mode 100644 index 0000000..1115907 --- /dev/null +++ b/libc/arch-mips/syscalls/tee.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tee) + .set noreorder + .cpload t9 + li v0, __NR_tee + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(tee)
diff --git a/libc/arch-mips/syscalls/tgkill.S b/libc/arch-mips/syscalls/tgkill.S new file mode 100644 index 0000000..bea211d --- /dev/null +++ b/libc/arch-mips/syscalls/tgkill.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tgkill) + .set noreorder + .cpload t9 + li v0, __NR_tgkill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(tgkill)
diff --git a/libc/arch-mips/syscalls/timerfd_create.S b/libc/arch-mips/syscalls/timerfd_create.S new file mode 100644 index 0000000..116c628 --- /dev/null +++ b/libc/arch-mips/syscalls/timerfd_create.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_create) + .set noreorder + .cpload t9 + li v0, __NR_timerfd_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(timerfd_create)
diff --git a/libc/arch-mips/syscalls/timerfd_gettime.S b/libc/arch-mips/syscalls/timerfd_gettime.S new file mode 100644 index 0000000..df7138c --- /dev/null +++ b/libc/arch-mips/syscalls/timerfd_gettime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_gettime) + .set noreorder + .cpload t9 + li v0, __NR_timerfd_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(timerfd_gettime)
diff --git a/libc/arch-mips/syscalls/timerfd_settime.S b/libc/arch-mips/syscalls/timerfd_settime.S new file mode 100644 index 0000000..2bfadb9 --- /dev/null +++ b/libc/arch-mips/syscalls/timerfd_settime.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_settime) + .set noreorder + .cpload t9 + li v0, __NR_timerfd_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(timerfd_settime)
diff --git a/libc/arch-mips/syscalls/times.S b/libc/arch-mips/syscalls/times.S new file mode 100644 index 0000000..90ce97f --- /dev/null +++ b/libc/arch-mips/syscalls/times.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(times) + .set noreorder + .cpload t9 + li v0, __NR_times + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(times)
diff --git a/libc/arch-mips/syscalls/truncate.S b/libc/arch-mips/syscalls/truncate.S new file mode 100644 index 0000000..6800705 --- /dev/null +++ b/libc/arch-mips/syscalls/truncate.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate) + .set noreorder + .cpload t9 + li v0, __NR_truncate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(truncate)
diff --git a/libc/arch-mips/syscalls/truncate64.S b/libc/arch-mips/syscalls/truncate64.S new file mode 100644 index 0000000..870e735 --- /dev/null +++ b/libc/arch-mips/syscalls/truncate64.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate64) + .set noreorder + .cpload t9 + li v0, __NR_truncate64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(truncate64)
diff --git a/libc/arch-mips/syscalls/umask.S b/libc/arch-mips/syscalls/umask.S new file mode 100644 index 0000000..ccf4292 --- /dev/null +++ b/libc/arch-mips/syscalls/umask.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umask) + .set noreorder + .cpload t9 + li v0, __NR_umask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(umask)
diff --git a/libc/arch-mips/syscalls/umount2.S b/libc/arch-mips/syscalls/umount2.S new file mode 100644 index 0000000..65a7129 --- /dev/null +++ b/libc/arch-mips/syscalls/umount2.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umount2) + .set noreorder + .cpload t9 + li v0, __NR_umount2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(umount2)
diff --git a/libc/arch-mips/syscalls/uname.S b/libc/arch-mips/syscalls/uname.S new file mode 100644 index 0000000..f540b3a --- /dev/null +++ b/libc/arch-mips/syscalls/uname.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(uname) + .set noreorder + .cpload t9 + li v0, __NR_uname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(uname)
diff --git a/libc/arch-mips/syscalls/unlinkat.S b/libc/arch-mips/syscalls/unlinkat.S new file mode 100644 index 0000000..001f9cf --- /dev/null +++ b/libc/arch-mips/syscalls/unlinkat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unlinkat) + .set noreorder + .cpload t9 + li v0, __NR_unlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(unlinkat)
diff --git a/libc/arch-mips/syscalls/unshare.S b/libc/arch-mips/syscalls/unshare.S new file mode 100644 index 0000000..13ca452 --- /dev/null +++ b/libc/arch-mips/syscalls/unshare.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unshare) + .set noreorder + .cpload t9 + li v0, __NR_unshare + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(unshare)
diff --git a/libc/arch-mips/syscalls/utimensat.S b/libc/arch-mips/syscalls/utimensat.S new file mode 100644 index 0000000..14e5a10 --- /dev/null +++ b/libc/arch-mips/syscalls/utimensat.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(utimensat) + .set noreorder + .cpload t9 + li v0, __NR_utimensat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(utimensat)
diff --git a/libc/arch-mips/syscalls/vmsplice.S b/libc/arch-mips/syscalls/vmsplice.S new file mode 100644 index 0000000..0191f53 --- /dev/null +++ b/libc/arch-mips/syscalls/vmsplice.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(vmsplice) + .set noreorder + .cpload t9 + li v0, __NR_vmsplice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(vmsplice)
diff --git a/libc/arch-mips/syscalls/wait4.S b/libc/arch-mips/syscalls/wait4.S new file mode 100644 index 0000000..8a12533 --- /dev/null +++ b/libc/arch-mips/syscalls/wait4.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(wait4) + .set noreorder + .cpload t9 + li v0, __NR_wait4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(wait4)
diff --git a/libc/arch-mips/syscalls/write.S b/libc/arch-mips/syscalls/write.S new file mode 100644 index 0000000..62dc36f --- /dev/null +++ b/libc/arch-mips/syscalls/write.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(write) + .set noreorder + .cpload t9 + li v0, __NR_write + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(write)
diff --git a/libc/arch-mips/syscalls/writev.S b/libc/arch-mips/syscalls/writev.S new file mode 100644 index 0000000..d8d6616 --- /dev/null +++ b/libc/arch-mips/syscalls/writev.S
@@ -0,0 +1,19 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(writev) + .set noreorder + .cpload t9 + li v0, __NR_writev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + la t9,__set_errno_internal + j t9 + nop + .set reorder +END(writev)
diff --git a/libc/arch-mips64/bionic/__bionic_clone.S b/libc/arch-mips64/bionic/__bionic_clone.S new file mode 100644 index 0000000..0d266ee --- /dev/null +++ b/libc/arch-mips64/bionic/__bionic_clone.S
@@ -0,0 +1,101 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/errno.h> +#include <linux/sched.h> + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(NARGSAVE,0) +FRAME_ARG = 0*REGSZ +FRAME_FN = 1*REGSZ +#else +FRAMESZ = MKFSIZ(0,3) +FRAME_GP = FRAMESZ-1*REGSZ +FRAME_ARG = FRAMESZ-2*REGSZ +FRAME_FN = FRAMESZ-3*REGSZ +#endif + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); +LEAF(__bionic_clone, FRAMESZ) + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(FRAME_GP,__bionic_clone) + SAVE_GP(FRAME_GP) + + # set up child stack + PTR_SUBU a1,FRAMESZ +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + PTR_L t0,FRAMESZ+5*REGSZ(sp) # fn + PRL_L t1,FRAMESZ+6*REGSZ(sp) # arg + PTR_S t0,FRAME_FN(a1) # fn + PTR_S t1,FRAME_ARG(a1) # arg +#else + PTR_L t0,FRAME_GP(sp) # copy gp to child stack + PTR_S t0,FRAME_GP(a1) + PTR_S a5,FRAME_FN(a1) # fn + PTR_S a6,FRAME_ARG(a1) # arg +# endif + + # remainder of arguments are correct for clone system call + LI v0,__NR_clone + syscall + + move a0,v0 + bnez a3,.L__error_bc + + beqz v0,.L__thread_start_bc + + RESTORE_GP64 + PTR_ADDU sp,FRAMESZ + j ra + +.L__thread_start_bc: + # Clear return address in child so we don't unwind further. + li ra,0 + + # void __start_thread(int (*func)(void*), void *arg) + PTR_L a0,FRAME_FN(sp) # fn + PTR_L a1,FRAME_ARG(sp) # arg + LA t9,__start_thread + RESTORE_GP64 + /* + * For O32 etc the child stack must have space for a0..a3 to be stored + * For N64 etc, the child stack can be restored to the original value + */ +#if !((_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)) + PTR_ADDU sp,FRAMESZ +#endif + j t9 + +.L__error_bc: + LA t9,__set_errno_internal + RESTORE_GP64 + PTR_ADDU sp,FRAMESZ + j t9 + END(__bionic_clone) +.hidden __bionic_clone
diff --git a/libc/arch-mips64/bionic/_exit_with_stack_teardown.S b/libc/arch-mips64/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..fcf8cc1 --- /dev/null +++ b/libc/arch-mips64/bionic/_exit_with_stack_teardown.S
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + li v0, __NR_munmap + syscall + // If munmap failed, we ignore the failure and exit anyway. + + li a0, 0 + li v0, __NR_exit + syscall + // The exit syscall does not return. +END(_exit_with_stack_teardown)
diff --git a/libc/arch-mips64/bionic/crtbegin.c b/libc/arch-mips64/bionic/crtbegin.c new file mode 100644 index 0000000..bdd423b --- /dev/null +++ b/libc/arch-mips64/bionic/crtbegin.c
@@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "../../bionic/libc_init_common.h" +#include <stddef.h> +#include <stdint.h> + +__attribute__ ((section (".preinit_array"))) +void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".init_array"))) +void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".fini_array"))) +void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1; + + +__LIBC_HIDDEN__ void do_mips_start(void *raw_args) { + structors_array_t array; + array.preinit_array = &__PREINIT_ARRAY__; + array.init_array = &__INIT_ARRAY__; + array.fini_array = &__FINI_ARRAY__; + + __libc_init(raw_args, NULL, &main, &array); +} + +/* + * This function prepares the return address with a branch-and-link + * instruction (bal) and then uses a .cpsetup to compute the Global + * Offset Table (GOT) pointer ($gp). The $gp is then used to load + * the address of _do_mips_start() into $t9 just before calling it. + * Terminating the stack with a NULL return address. + */ +__asm__ ( +" .set push \n" +" \n" +" .text \n" +" .align 4 \n" +" .type __start,@function \n" +" .globl __start \n" +" .globl _start \n" +" \n" +" .ent __start \n" +"__start: \n" +" _start: \n" +" .frame $sp,32,$0 \n" +" .mask 0x80000000,-8 \n" +" \n" +" move $a0, $sp \n" +" daddiu $sp, $sp, -32 \n" +" \n" +" .set noreorder \n" +" bal 1f \n" +" nop \n" +"1: \n" +" .cpsetup $ra,16,1b \n" +" .set reorder \n" +" \n" +" sd $0, 24($sp) \n" +" jal do_mips_start \n" +" \n" +"2: b 2b \n" +" .end __start \n" +" \n" +" .set pop \n" +); + +#include "../../arch-common/bionic/__dso_handle.h" +#include "../../arch-common/bionic/atexit.h" +#include "../../arch-common/bionic/pthread_atfork.h"
diff --git a/libc/arch-mips64/bionic/setjmp.S b/libc/arch-mips64/bionic/setjmp.S new file mode 120000 index 0000000..b117bb6 --- /dev/null +++ b/libc/arch-mips64/bionic/setjmp.S
@@ -0,0 +1 @@ +../../arch-mips/bionic/setjmp.S \ No newline at end of file
diff --git a/libc/arch-mips64/bionic/stat.cpp b/libc/arch-mips64/bionic/stat.cpp new file mode 100644 index 0000000..29a50ed --- /dev/null +++ b/libc/arch-mips64/bionic/stat.cpp
@@ -0,0 +1,89 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/stat.h> +#include <sys/types.h> +#include <sys/syscall.h> +#include <unistd.h> + +struct kernel_stat { + unsigned int st_dev; + unsigned int st_pad0[3]; + unsigned long st_ino; + mode_t st_mode; + __u32 st_nlink; + uid_t st_uid; + gid_t st_gid; + unsigned int st_rdev; + unsigned int st_pad1[3]; + __kernel_off_t st_size; + unsigned int _st_atime; + unsigned int st_atime_nsec; + unsigned int _st_mtime; + unsigned int st_mtime_nsec; + unsigned int _st_ctime; + unsigned int st_ctime_nsec; + unsigned int st_blksize; + unsigned int st_pad2; + unsigned long st_blocks; +}; + +static void copy_stat(struct stat* st, struct kernel_stat* s) { + st->st_dev = static_cast<dev_t>(s->st_dev); + st->st_ino = static_cast<ino_t>(s->st_ino); + st->st_mode = static_cast<mode_t>(s->st_mode); + st->st_nlink = static_cast<nlink_t>(s->st_nlink); + st->st_uid = static_cast<uid_t>(s->st_uid); + st->st_gid = static_cast<gid_t>(s->st_gid); + st->st_rdev = static_cast<dev_t>(s->st_rdev); + st->st_size = static_cast<off_t>(s->st_size); + st->st_blksize = static_cast<int>(s->st_blksize); + st->st_blocks = static_cast<long>(s->st_blocks); + st->st_atim.tv_sec = static_cast<time_t>(s->_st_atime); + st->st_atim.tv_nsec = static_cast<long>(s->st_atime_nsec); + st->st_mtim.tv_sec = static_cast<time_t>(s->_st_mtime); + st->st_mtim.tv_nsec = static_cast<long>(s->st_mtime_nsec); + st->st_ctim.tv_sec = static_cast<time_t>(s->_st_ctime); + st->st_ctim.tv_nsec = static_cast<long>(s->st_ctime_nsec); +} + +int fstat(int fp, struct stat* st) { + kernel_stat s; + int ret = syscall(__NR_fstat, fp, &s); + copy_stat(st, &s); + return ret; +} +__strong_alias(fstat64, fstat); + +int fstatat(int dirfd, const char* pathname, struct stat* buf, int flags) { + kernel_stat s; + int ret = syscall(__NR_newfstatat, dirfd, pathname, &s, flags); + copy_stat(buf, &s); + return ret; +} +__strong_alias(fstatat64, fstatat);
diff --git a/libc/arch-mips64/bionic/syscall.S b/libc/arch-mips64/bionic/syscall.S new file mode 100644 index 0000000..4c739fd --- /dev/null +++ b/libc/arch-mips64/bionic/syscall.S
@@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(6,0) +#else +FRAMESZ = MKFSIZ(0,1) +FRAME_GP = FRAMESZ-1*REGSZ +#endif + +LEAF(syscall,FRAMESZ) + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(FRAME_GP,syscall) + SAVE_GP(FRAME_GP) + move v0, a0 # syscall number to v0 + move a0, a1 # shift args down + move a1, a2 + move a2, a3 +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + REG_L a3, FRAMESZ+4*REGSZ(sp) + REG_L t0, FRAMESZ+5*REGSZ(sp) + REG_L t1, FRAMESZ+6*REGSZ(sp) + REG_S t0, 4*REGSZ(sp) + REG_S t1, 5*REGSZ(sp) +#else + move a3, a4 + move a4, a5 + move a5, a6 +#endif + syscall + move a0, v0 + bnez a3, 1f + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j ra +1: + LA t9,__set_errno_internal + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j t9 + END(syscall)
diff --git a/libc/arch-mips64/bionic/vfork.S b/libc/arch-mips64/bionic/vfork.S new file mode 100644 index 0000000..e0a39ed --- /dev/null +++ b/libc/arch-mips64/bionic/vfork.S
@@ -0,0 +1,77 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/sched.h> + +// TODO: mips' uapi signal.h is missing #ifndef __ASSEMBLY__. +// #include <asm/signal.h> +#define SIGCHLD 18 + + .text + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(5,0) +#else +FRAMESZ = MKFSIZ(0,0) +#endif + +LEAF(vfork,FRAMESZ) +#if FRAMESZ!=0 + PTR_SUBU sp, FRAMESZ +#endif + SETUP_GP64(a5, vfork) + + // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0 + rdhwr v0, $29 // v0 = tls + REG_L v0, REGSZ*1(v0) // v0 = v0[TLS_SLOT_THREAD_ID ie 1] + sw $0, REGSZ*2+4(v0) // v0->cached_pid_ = 0 + + LI a0, (CLONE_VM | CLONE_VFORK | SIGCHLD) + move a1, $0 + move a2, $0 + move a3, $0 +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + REG_S $0, 4*REGSZ(sp) +#else + move a4, $0 +#endif + LI v0, __NR_clone + syscall +#if FRAMESZ!=0 + PTR_ADDU sp,FRAMESZ +#endif + move a0, v0 + bnez a3, 1f + RESTORE_GP64 + j ra +1: + LA t9,__set_errno_internal + RESTORE_GP64 + j t9 + END(vfork)
diff --git a/libc/arch-mips64/include b/libc/arch-mips64/include new file mode 120000 index 0000000..fabbe8a --- /dev/null +++ b/libc/arch-mips64/include
@@ -0,0 +1 @@ +../arch-mips/include \ No newline at end of file
diff --git a/libc/arch-mips64/syscalls/___clock_nanosleep.S b/libc/arch-mips64/syscalls/___clock_nanosleep.S new file mode 100644 index 0000000..e9fb316 --- /dev/null +++ b/libc/arch-mips64/syscalls/___clock_nanosleep.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___clock_nanosleep) + .set push + .set noreorder + li v0, __NR_clock_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___clock_nanosleep) +.hidden ___clock_nanosleep
diff --git a/libc/arch-mips64/syscalls/___close.S b/libc/arch-mips64/syscalls/___close.S new file mode 100644 index 0000000..f1ce708 --- /dev/null +++ b/libc/arch-mips64/syscalls/___close.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___close) + .set push + .set noreorder + li v0, __NR_close + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___close) +.hidden ___close
diff --git a/libc/arch-mips64/syscalls/___faccessat.S b/libc/arch-mips64/syscalls/___faccessat.S new file mode 100644 index 0000000..240625f --- /dev/null +++ b/libc/arch-mips64/syscalls/___faccessat.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___faccessat) + .set push + .set noreorder + li v0, __NR_faccessat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___faccessat) +.hidden ___faccessat
diff --git a/libc/arch-mips64/syscalls/___fchmod.S b/libc/arch-mips64/syscalls/___fchmod.S new file mode 100644 index 0000000..7c16c54 --- /dev/null +++ b/libc/arch-mips64/syscalls/___fchmod.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmod) + .set push + .set noreorder + li v0, __NR_fchmod + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___fchmod) +.hidden ___fchmod
diff --git a/libc/arch-mips64/syscalls/___fchmodat.S b/libc/arch-mips64/syscalls/___fchmodat.S new file mode 100644 index 0000000..50f108e --- /dev/null +++ b/libc/arch-mips64/syscalls/___fchmodat.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmodat) + .set push + .set noreorder + li v0, __NR_fchmodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___fchmodat) +.hidden ___fchmodat
diff --git a/libc/arch-mips64/syscalls/___fgetxattr.S b/libc/arch-mips64/syscalls/___fgetxattr.S new file mode 100644 index 0000000..935b080 --- /dev/null +++ b/libc/arch-mips64/syscalls/___fgetxattr.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fgetxattr) + .set push + .set noreorder + li v0, __NR_fgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___fgetxattr) +.hidden ___fgetxattr
diff --git a/libc/arch-mips64/syscalls/___flistxattr.S b/libc/arch-mips64/syscalls/___flistxattr.S new file mode 100644 index 0000000..586bcf7 --- /dev/null +++ b/libc/arch-mips64/syscalls/___flistxattr.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___flistxattr) + .set push + .set noreorder + li v0, __NR_flistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___flistxattr) +.hidden ___flistxattr
diff --git a/libc/arch-mips64/syscalls/___fsetxattr.S b/libc/arch-mips64/syscalls/___fsetxattr.S new file mode 100644 index 0000000..c02f406 --- /dev/null +++ b/libc/arch-mips64/syscalls/___fsetxattr.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fsetxattr) + .set push + .set noreorder + li v0, __NR_fsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___fsetxattr) +.hidden ___fsetxattr
diff --git a/libc/arch-mips64/syscalls/___mremap.S b/libc/arch-mips64/syscalls/___mremap.S new file mode 100644 index 0000000..5004d50 --- /dev/null +++ b/libc/arch-mips64/syscalls/___mremap.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___mremap) + .set push + .set noreorder + li v0, __NR_mremap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___mremap) +.hidden ___mremap
diff --git a/libc/arch-mips64/syscalls/___rt_sigqueueinfo.S b/libc/arch-mips64/syscalls/___rt_sigqueueinfo.S new file mode 100644 index 0000000..1503f51 --- /dev/null +++ b/libc/arch-mips64/syscalls/___rt_sigqueueinfo.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___rt_sigqueueinfo) + .set push + .set noreorder + li v0, __NR_rt_sigqueueinfo + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(___rt_sigqueueinfo) +.hidden ___rt_sigqueueinfo
diff --git a/libc/arch-mips64/syscalls/__accept4.S b/libc/arch-mips64/syscalls/__accept4.S new file mode 100644 index 0000000..ed9b6c7 --- /dev/null +++ b/libc/arch-mips64/syscalls/__accept4.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + .set push + .set noreorder + li v0, __NR_accept4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__accept4) +.hidden __accept4
diff --git a/libc/arch-mips64/syscalls/__brk.S b/libc/arch-mips64/syscalls/__brk.S new file mode 100644 index 0000000..e1f89c7 --- /dev/null +++ b/libc/arch-mips64/syscalls/__brk.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + .set push + .set noreorder + li v0, __NR_brk + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__brk) +.hidden __brk
diff --git a/libc/arch-mips64/syscalls/__connect.S b/libc/arch-mips64/syscalls/__connect.S new file mode 100644 index 0000000..8c44464 --- /dev/null +++ b/libc/arch-mips64/syscalls/__connect.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + .set push + .set noreorder + li v0, __NR_connect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__connect) +.hidden __connect
diff --git a/libc/arch-mips64/syscalls/__epoll_pwait.S b/libc/arch-mips64/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..5dfb380 --- /dev/null +++ b/libc/arch-mips64/syscalls/__epoll_pwait.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + .set push + .set noreorder + li v0, __NR_epoll_pwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__epoll_pwait) +.hidden __epoll_pwait
diff --git a/libc/arch-mips64/syscalls/__exit.S b/libc/arch-mips64/syscalls/__exit.S new file mode 100644 index 0000000..2d5e03d --- /dev/null +++ b/libc/arch-mips64/syscalls/__exit.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + .set push + .set noreorder + li v0, __NR_exit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__exit) +.hidden __exit
diff --git a/libc/arch-mips64/syscalls/__fadvise64.S b/libc/arch-mips64/syscalls/__fadvise64.S new file mode 100644 index 0000000..90aceb0 --- /dev/null +++ b/libc/arch-mips64/syscalls/__fadvise64.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fadvise64) + .set push + .set noreorder + li v0, __NR_fadvise64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__fadvise64) +.hidden __fadvise64
diff --git a/libc/arch-mips64/syscalls/__fstatfs.S b/libc/arch-mips64/syscalls/__fstatfs.S new file mode 100644 index 0000000..8766e22 --- /dev/null +++ b/libc/arch-mips64/syscalls/__fstatfs.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fstatfs) + .set push + .set noreorder + li v0, __NR_fstatfs + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__fstatfs) +.hidden __fstatfs
diff --git a/libc/arch-mips64/syscalls/__getcpu.S b/libc/arch-mips64/syscalls/__getcpu.S new file mode 100644 index 0000000..a16c21e --- /dev/null +++ b/libc/arch-mips64/syscalls/__getcpu.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + .set push + .set noreorder + li v0, __NR_getcpu + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getcpu) +.hidden __getcpu
diff --git a/libc/arch-mips64/syscalls/__getcwd.S b/libc/arch-mips64/syscalls/__getcwd.S new file mode 100644 index 0000000..53eeb68 --- /dev/null +++ b/libc/arch-mips64/syscalls/__getcwd.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + .set push + .set noreorder + li v0, __NR_getcwd + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getcwd) +.hidden __getcwd
diff --git a/libc/arch-mips64/syscalls/__getdents64.S b/libc/arch-mips64/syscalls/__getdents64.S new file mode 100644 index 0000000..3720b8e --- /dev/null +++ b/libc/arch-mips64/syscalls/__getdents64.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + .set push + .set noreorder + li v0, __NR_getdents64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getdents64) +.hidden __getdents64
diff --git a/libc/arch-mips64/syscalls/__getpid.S b/libc/arch-mips64/syscalls/__getpid.S new file mode 100644 index 0000000..6d5d926 --- /dev/null +++ b/libc/arch-mips64/syscalls/__getpid.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + .set push + .set noreorder + li v0, __NR_getpid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getpid) +.hidden __getpid
diff --git a/libc/arch-mips64/syscalls/__getpriority.S b/libc/arch-mips64/syscalls/__getpriority.S new file mode 100644 index 0000000..19327ab --- /dev/null +++ b/libc/arch-mips64/syscalls/__getpriority.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + .set push + .set noreorder + li v0, __NR_getpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getpriority) +.hidden __getpriority
diff --git a/libc/arch-mips64/syscalls/__ioctl.S b/libc/arch-mips64/syscalls/__ioctl.S new file mode 100644 index 0000000..7fad0d1 --- /dev/null +++ b/libc/arch-mips64/syscalls/__ioctl.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + .set push + .set noreorder + li v0, __NR_ioctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ioctl) +.hidden __ioctl
diff --git a/libc/arch-mips64/syscalls/__openat.S b/libc/arch-mips64/syscalls/__openat.S new file mode 100644 index 0000000..d3ac13a --- /dev/null +++ b/libc/arch-mips64/syscalls/__openat.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + .set push + .set noreorder + li v0, __NR_openat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__openat) +.hidden __openat
diff --git a/libc/arch-mips64/syscalls/__ppoll.S b/libc/arch-mips64/syscalls/__ppoll.S new file mode 100644 index 0000000..4e6fb8a --- /dev/null +++ b/libc/arch-mips64/syscalls/__ppoll.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + .set push + .set noreorder + li v0, __NR_ppoll + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ppoll) +.hidden __ppoll
diff --git a/libc/arch-mips64/syscalls/__pselect6.S b/libc/arch-mips64/syscalls/__pselect6.S new file mode 100644 index 0000000..6d49d1c --- /dev/null +++ b/libc/arch-mips64/syscalls/__pselect6.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + .set push + .set noreorder + li v0, __NR_pselect6 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__pselect6) +.hidden __pselect6
diff --git a/libc/arch-mips64/syscalls/__ptrace.S b/libc/arch-mips64/syscalls/__ptrace.S new file mode 100644 index 0000000..5a3ce16 --- /dev/null +++ b/libc/arch-mips64/syscalls/__ptrace.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + .set push + .set noreorder + li v0, __NR_ptrace + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ptrace) +.hidden __ptrace
diff --git a/libc/arch-mips64/syscalls/__reboot.S b/libc/arch-mips64/syscalls/__reboot.S new file mode 100644 index 0000000..587310d --- /dev/null +++ b/libc/arch-mips64/syscalls/__reboot.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + .set push + .set noreorder + li v0, __NR_reboot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__reboot) +.hidden __reboot
diff --git a/libc/arch-mips64/syscalls/__rt_sigaction.S b/libc/arch-mips64/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..7dd3cae --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigaction.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + .set push + .set noreorder + li v0, __NR_rt_sigaction + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigaction) +.hidden __rt_sigaction
diff --git a/libc/arch-mips64/syscalls/__rt_sigpending.S b/libc/arch-mips64/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..68ae39a --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigpending.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + .set push + .set noreorder + li v0, __NR_rt_sigpending + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigpending) +.hidden __rt_sigpending
diff --git a/libc/arch-mips64/syscalls/__rt_sigprocmask.S b/libc/arch-mips64/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..54620e9 --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigprocmask.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + .set push + .set noreorder + li v0, __NR_rt_sigprocmask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigprocmask) +.hidden __rt_sigprocmask
diff --git a/libc/arch-mips64/syscalls/__rt_sigsuspend.S b/libc/arch-mips64/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..ea15def --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigsuspend.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + .set push + .set noreorder + li v0, __NR_rt_sigsuspend + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigsuspend) +.hidden __rt_sigsuspend
diff --git a/libc/arch-mips64/syscalls/__rt_sigtimedwait.S b/libc/arch-mips64/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..177f17c --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigtimedwait.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + .set push + .set noreorder + li v0, __NR_rt_sigtimedwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigtimedwait) +.hidden __rt_sigtimedwait
diff --git a/libc/arch-mips64/syscalls/__sched_getaffinity.S b/libc/arch-mips64/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..2081706 --- /dev/null +++ b/libc/arch-mips64/syscalls/__sched_getaffinity.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + .set push + .set noreorder + li v0, __NR_sched_getaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__sched_getaffinity) +.hidden __sched_getaffinity
diff --git a/libc/arch-mips64/syscalls/__set_tid_address.S b/libc/arch-mips64/syscalls/__set_tid_address.S new file mode 100644 index 0000000..cd966dd --- /dev/null +++ b/libc/arch-mips64/syscalls/__set_tid_address.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + .set push + .set noreorder + li v0, __NR_set_tid_address + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__set_tid_address) +.hidden __set_tid_address
diff --git a/libc/arch-mips64/syscalls/__set_tls.S b/libc/arch-mips64/syscalls/__set_tls.S new file mode 100644 index 0000000..cc98150 --- /dev/null +++ b/libc/arch-mips64/syscalls/__set_tls.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tls) + .set push + .set noreorder + li v0, __NR_set_thread_area + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__set_tls) +.hidden __set_tls
diff --git a/libc/arch-mips64/syscalls/__signalfd4.S b/libc/arch-mips64/syscalls/__signalfd4.S new file mode 100644 index 0000000..ea6eef1 --- /dev/null +++ b/libc/arch-mips64/syscalls/__signalfd4.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + .set push + .set noreorder + li v0, __NR_signalfd4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__signalfd4) +.hidden __signalfd4
diff --git a/libc/arch-mips64/syscalls/__socket.S b/libc/arch-mips64/syscalls/__socket.S new file mode 100644 index 0000000..a499359 --- /dev/null +++ b/libc/arch-mips64/syscalls/__socket.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + .set push + .set noreorder + li v0, __NR_socket + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__socket) +.hidden __socket
diff --git a/libc/arch-mips64/syscalls/__statfs.S b/libc/arch-mips64/syscalls/__statfs.S new file mode 100644 index 0000000..52db4e2 --- /dev/null +++ b/libc/arch-mips64/syscalls/__statfs.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__statfs) + .set push + .set noreorder + li v0, __NR_statfs + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__statfs) +.hidden __statfs
diff --git a/libc/arch-mips64/syscalls/__sync_file_range.S b/libc/arch-mips64/syscalls/__sync_file_range.S new file mode 100644 index 0000000..e22c36e --- /dev/null +++ b/libc/arch-mips64/syscalls/__sync_file_range.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sync_file_range) + .set push + .set noreorder + li v0, __NR_sync_file_range + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__sync_file_range) +.hidden __sync_file_range
diff --git a/libc/arch-mips64/syscalls/__timer_create.S b/libc/arch-mips64/syscalls/__timer_create.S new file mode 100644 index 0000000..c66d8f9 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_create.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + .set push + .set noreorder + li v0, __NR_timer_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_create) +.hidden __timer_create
diff --git a/libc/arch-mips64/syscalls/__timer_delete.S b/libc/arch-mips64/syscalls/__timer_delete.S new file mode 100644 index 0000000..45cf5e8 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_delete.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + .set push + .set noreorder + li v0, __NR_timer_delete + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_delete) +.hidden __timer_delete
diff --git a/libc/arch-mips64/syscalls/__timer_getoverrun.S b/libc/arch-mips64/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..8a73160 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_getoverrun.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + .set push + .set noreorder + li v0, __NR_timer_getoverrun + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_getoverrun) +.hidden __timer_getoverrun
diff --git a/libc/arch-mips64/syscalls/__timer_gettime.S b/libc/arch-mips64/syscalls/__timer_gettime.S new file mode 100644 index 0000000..32ee5bf --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_gettime.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + .set push + .set noreorder + li v0, __NR_timer_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_gettime) +.hidden __timer_gettime
diff --git a/libc/arch-mips64/syscalls/__timer_settime.S b/libc/arch-mips64/syscalls/__timer_settime.S new file mode 100644 index 0000000..59764d8 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_settime.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + .set push + .set noreorder + li v0, __NR_timer_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_settime) +.hidden __timer_settime
diff --git a/libc/arch-mips64/syscalls/__waitid.S b/libc/arch-mips64/syscalls/__waitid.S new file mode 100644 index 0000000..5ee090d --- /dev/null +++ b/libc/arch-mips64/syscalls/__waitid.S
@@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + .set push + .set noreorder + li v0, __NR_waitid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__waitid) +.hidden __waitid
diff --git a/libc/arch-mips64/syscalls/_exit.S b/libc/arch-mips64/syscalls/_exit.S new file mode 100644 index 0000000..37f8119 --- /dev/null +++ b/libc/arch-mips64/syscalls/_exit.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + .set push + .set noreorder + li v0, __NR_exit_group + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(_exit) + +ALIAS_SYMBOL(_Exit, _exit)
diff --git a/libc/arch-mips64/syscalls/acct.S b/libc/arch-mips64/syscalls/acct.S new file mode 100644 index 0000000..ff728dc --- /dev/null +++ b/libc/arch-mips64/syscalls/acct.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + .set push + .set noreorder + li v0, __NR_acct + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(acct)
diff --git a/libc/arch-mips64/syscalls/adjtimex.S b/libc/arch-mips64/syscalls/adjtimex.S new file mode 100644 index 0000000..57b012c --- /dev/null +++ b/libc/arch-mips64/syscalls/adjtimex.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(adjtimex) + .set push + .set noreorder + li v0, __NR_adjtimex + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(adjtimex)
diff --git a/libc/arch-mips64/syscalls/bind.S b/libc/arch-mips64/syscalls/bind.S new file mode 100644 index 0000000..9c2b5b8 --- /dev/null +++ b/libc/arch-mips64/syscalls/bind.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + .set push + .set noreorder + li v0, __NR_bind + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(bind)
diff --git a/libc/arch-mips64/syscalls/capget.S b/libc/arch-mips64/syscalls/capget.S new file mode 100644 index 0000000..9d05438 --- /dev/null +++ b/libc/arch-mips64/syscalls/capget.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + .set push + .set noreorder + li v0, __NR_capget + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(capget)
diff --git a/libc/arch-mips64/syscalls/capset.S b/libc/arch-mips64/syscalls/capset.S new file mode 100644 index 0000000..e947028 --- /dev/null +++ b/libc/arch-mips64/syscalls/capset.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + .set push + .set noreorder + li v0, __NR_capset + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(capset)
diff --git a/libc/arch-mips64/syscalls/chdir.S b/libc/arch-mips64/syscalls/chdir.S new file mode 100644 index 0000000..14b22c9 --- /dev/null +++ b/libc/arch-mips64/syscalls/chdir.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + .set push + .set noreorder + li v0, __NR_chdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(chdir)
diff --git a/libc/arch-mips64/syscalls/chroot.S b/libc/arch-mips64/syscalls/chroot.S new file mode 100644 index 0000000..e805f51 --- /dev/null +++ b/libc/arch-mips64/syscalls/chroot.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + .set push + .set noreorder + li v0, __NR_chroot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(chroot)
diff --git a/libc/arch-mips64/syscalls/clock_adjtime.S b/libc/arch-mips64/syscalls/clock_adjtime.S new file mode 100644 index 0000000..206e9fd --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_adjtime.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_adjtime) + .set push + .set noreorder + li v0, __NR_clock_adjtime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_adjtime)
diff --git a/libc/arch-mips64/syscalls/clock_getres.S b/libc/arch-mips64/syscalls/clock_getres.S new file mode 100644 index 0000000..41003a0 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_getres.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + .set push + .set noreorder + li v0, __NR_clock_getres + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_getres)
diff --git a/libc/arch-mips64/syscalls/clock_gettime.S b/libc/arch-mips64/syscalls/clock_gettime.S new file mode 100644 index 0000000..0813560 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_gettime.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_gettime) + .set push + .set noreorder + li v0, __NR_clock_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_gettime)
diff --git a/libc/arch-mips64/syscalls/clock_settime.S b/libc/arch-mips64/syscalls/clock_settime.S new file mode 100644 index 0000000..77b6ae4 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_settime.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + .set push + .set noreorder + li v0, __NR_clock_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_settime)
diff --git a/libc/arch-mips64/syscalls/delete_module.S b/libc/arch-mips64/syscalls/delete_module.S new file mode 100644 index 0000000..8396537 --- /dev/null +++ b/libc/arch-mips64/syscalls/delete_module.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + .set push + .set noreorder + li v0, __NR_delete_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(delete_module)
diff --git a/libc/arch-mips64/syscalls/dup.S b/libc/arch-mips64/syscalls/dup.S new file mode 100644 index 0000000..d1ca5e7 --- /dev/null +++ b/libc/arch-mips64/syscalls/dup.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + .set push + .set noreorder + li v0, __NR_dup + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(dup)
diff --git a/libc/arch-mips64/syscalls/dup3.S b/libc/arch-mips64/syscalls/dup3.S new file mode 100644 index 0000000..5601f31 --- /dev/null +++ b/libc/arch-mips64/syscalls/dup3.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + .set push + .set noreorder + li v0, __NR_dup3 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(dup3)
diff --git a/libc/arch-mips64/syscalls/epoll_create1.S b/libc/arch-mips64/syscalls/epoll_create1.S new file mode 100644 index 0000000..11f1ceb --- /dev/null +++ b/libc/arch-mips64/syscalls/epoll_create1.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + .set push + .set noreorder + li v0, __NR_epoll_create1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(epoll_create1)
diff --git a/libc/arch-mips64/syscalls/epoll_ctl.S b/libc/arch-mips64/syscalls/epoll_ctl.S new file mode 100644 index 0000000..9eba605 --- /dev/null +++ b/libc/arch-mips64/syscalls/epoll_ctl.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + .set push + .set noreorder + li v0, __NR_epoll_ctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(epoll_ctl)
diff --git a/libc/arch-mips64/syscalls/eventfd.S b/libc/arch-mips64/syscalls/eventfd.S new file mode 100644 index 0000000..5cd63e4 --- /dev/null +++ b/libc/arch-mips64/syscalls/eventfd.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + .set push + .set noreorder + li v0, __NR_eventfd2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(eventfd)
diff --git a/libc/arch-mips64/syscalls/execve.S b/libc/arch-mips64/syscalls/execve.S new file mode 100644 index 0000000..bcd5d60 --- /dev/null +++ b/libc/arch-mips64/syscalls/execve.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + .set push + .set noreorder + li v0, __NR_execve + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(execve)
diff --git a/libc/arch-mips64/syscalls/fallocate.S b/libc/arch-mips64/syscalls/fallocate.S new file mode 100644 index 0000000..14e25a0 --- /dev/null +++ b/libc/arch-mips64/syscalls/fallocate.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate) + .set push + .set noreorder + li v0, __NR_fallocate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fallocate) + +ALIAS_SYMBOL(fallocate64, fallocate)
diff --git a/libc/arch-mips64/syscalls/fchdir.S b/libc/arch-mips64/syscalls/fchdir.S new file mode 100644 index 0000000..e05625c --- /dev/null +++ b/libc/arch-mips64/syscalls/fchdir.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + .set push + .set noreorder + li v0, __NR_fchdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchdir)
diff --git a/libc/arch-mips64/syscalls/fchown.S b/libc/arch-mips64/syscalls/fchown.S new file mode 100644 index 0000000..5dc33c0 --- /dev/null +++ b/libc/arch-mips64/syscalls/fchown.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + .set push + .set noreorder + li v0, __NR_fchown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchown)
diff --git a/libc/arch-mips64/syscalls/fchownat.S b/libc/arch-mips64/syscalls/fchownat.S new file mode 100644 index 0000000..f4cefe0 --- /dev/null +++ b/libc/arch-mips64/syscalls/fchownat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + .set push + .set noreorder + li v0, __NR_fchownat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchownat)
diff --git a/libc/arch-mips64/syscalls/fcntl.S b/libc/arch-mips64/syscalls/fcntl.S new file mode 100644 index 0000000..dabc65b --- /dev/null +++ b/libc/arch-mips64/syscalls/fcntl.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fcntl) + .set push + .set noreorder + li v0, __NR_fcntl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fcntl)
diff --git a/libc/arch-mips64/syscalls/fdatasync.S b/libc/arch-mips64/syscalls/fdatasync.S new file mode 100644 index 0000000..52be110 --- /dev/null +++ b/libc/arch-mips64/syscalls/fdatasync.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + .set push + .set noreorder + li v0, __NR_fdatasync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fdatasync)
diff --git a/libc/arch-mips64/syscalls/flock.S b/libc/arch-mips64/syscalls/flock.S new file mode 100644 index 0000000..d74a5db --- /dev/null +++ b/libc/arch-mips64/syscalls/flock.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + .set push + .set noreorder + li v0, __NR_flock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(flock)
diff --git a/libc/arch-mips64/syscalls/fremovexattr.S b/libc/arch-mips64/syscalls/fremovexattr.S new file mode 100644 index 0000000..417be4a --- /dev/null +++ b/libc/arch-mips64/syscalls/fremovexattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + .set push + .set noreorder + li v0, __NR_fremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fremovexattr)
diff --git a/libc/arch-mips64/syscalls/fsync.S b/libc/arch-mips64/syscalls/fsync.S new file mode 100644 index 0000000..7056e36 --- /dev/null +++ b/libc/arch-mips64/syscalls/fsync.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + .set push + .set noreorder + li v0, __NR_fsync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fsync)
diff --git a/libc/arch-mips64/syscalls/ftruncate.S b/libc/arch-mips64/syscalls/ftruncate.S new file mode 100644 index 0000000..063e8f3 --- /dev/null +++ b/libc/arch-mips64/syscalls/ftruncate.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate) + .set push + .set noreorder + li v0, __NR_ftruncate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(ftruncate) + +ALIAS_SYMBOL(ftruncate64, ftruncate)
diff --git a/libc/arch-mips64/syscalls/getegid.S b/libc/arch-mips64/syscalls/getegid.S new file mode 100644 index 0000000..439c6f0 --- /dev/null +++ b/libc/arch-mips64/syscalls/getegid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + .set push + .set noreorder + li v0, __NR_getegid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getegid)
diff --git a/libc/arch-mips64/syscalls/geteuid.S b/libc/arch-mips64/syscalls/geteuid.S new file mode 100644 index 0000000..5619dc6 --- /dev/null +++ b/libc/arch-mips64/syscalls/geteuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + .set push + .set noreorder + li v0, __NR_geteuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(geteuid)
diff --git a/libc/arch-mips64/syscalls/getgid.S b/libc/arch-mips64/syscalls/getgid.S new file mode 100644 index 0000000..777be1a --- /dev/null +++ b/libc/arch-mips64/syscalls/getgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + .set push + .set noreorder + li v0, __NR_getgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getgid)
diff --git a/libc/arch-mips64/syscalls/getgroups.S b/libc/arch-mips64/syscalls/getgroups.S new file mode 100644 index 0000000..93c4fa1 --- /dev/null +++ b/libc/arch-mips64/syscalls/getgroups.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + .set push + .set noreorder + li v0, __NR_getgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getgroups)
diff --git a/libc/arch-mips64/syscalls/getitimer.S b/libc/arch-mips64/syscalls/getitimer.S new file mode 100644 index 0000000..fe78a97 --- /dev/null +++ b/libc/arch-mips64/syscalls/getitimer.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + .set push + .set noreorder + li v0, __NR_getitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getitimer)
diff --git a/libc/arch-mips64/syscalls/getpeername.S b/libc/arch-mips64/syscalls/getpeername.S new file mode 100644 index 0000000..121f1a6 --- /dev/null +++ b/libc/arch-mips64/syscalls/getpeername.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + .set push + .set noreorder + li v0, __NR_getpeername + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getpeername)
diff --git a/libc/arch-mips64/syscalls/getpgid.S b/libc/arch-mips64/syscalls/getpgid.S new file mode 100644 index 0000000..19dc77f --- /dev/null +++ b/libc/arch-mips64/syscalls/getpgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + .set push + .set noreorder + li v0, __NR_getpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getpgid)
diff --git a/libc/arch-mips64/syscalls/getppid.S b/libc/arch-mips64/syscalls/getppid.S new file mode 100644 index 0000000..d00f309 --- /dev/null +++ b/libc/arch-mips64/syscalls/getppid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + .set push + .set noreorder + li v0, __NR_getppid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getppid)
diff --git a/libc/arch-mips64/syscalls/getresgid.S b/libc/arch-mips64/syscalls/getresgid.S new file mode 100644 index 0000000..18cb5a1 --- /dev/null +++ b/libc/arch-mips64/syscalls/getresgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + .set push + .set noreorder + li v0, __NR_getresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getresgid)
diff --git a/libc/arch-mips64/syscalls/getresuid.S b/libc/arch-mips64/syscalls/getresuid.S new file mode 100644 index 0000000..c217bf7 --- /dev/null +++ b/libc/arch-mips64/syscalls/getresuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + .set push + .set noreorder + li v0, __NR_getresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getresuid)
diff --git a/libc/arch-mips64/syscalls/getrlimit.S b/libc/arch-mips64/syscalls/getrlimit.S new file mode 100644 index 0000000..5e2a82a --- /dev/null +++ b/libc/arch-mips64/syscalls/getrlimit.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + .set push + .set noreorder + li v0, __NR_getrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getrlimit) + +ALIAS_SYMBOL(getrlimit64, getrlimit)
diff --git a/libc/arch-mips64/syscalls/getrusage.S b/libc/arch-mips64/syscalls/getrusage.S new file mode 100644 index 0000000..4bf557e --- /dev/null +++ b/libc/arch-mips64/syscalls/getrusage.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + .set push + .set noreorder + li v0, __NR_getrusage + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getrusage)
diff --git a/libc/arch-mips64/syscalls/getsid.S b/libc/arch-mips64/syscalls/getsid.S new file mode 100644 index 0000000..030c91d --- /dev/null +++ b/libc/arch-mips64/syscalls/getsid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + .set push + .set noreorder + li v0, __NR_getsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsid)
diff --git a/libc/arch-mips64/syscalls/getsockname.S b/libc/arch-mips64/syscalls/getsockname.S new file mode 100644 index 0000000..88a9426 --- /dev/null +++ b/libc/arch-mips64/syscalls/getsockname.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + .set push + .set noreorder + li v0, __NR_getsockname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsockname)
diff --git a/libc/arch-mips64/syscalls/getsockopt.S b/libc/arch-mips64/syscalls/getsockopt.S new file mode 100644 index 0000000..08ee634 --- /dev/null +++ b/libc/arch-mips64/syscalls/getsockopt.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + .set push + .set noreorder + li v0, __NR_getsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsockopt)
diff --git a/libc/arch-mips64/syscalls/gettimeofday.S b/libc/arch-mips64/syscalls/gettimeofday.S new file mode 100644 index 0000000..3a6d417 --- /dev/null +++ b/libc/arch-mips64/syscalls/gettimeofday.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(gettimeofday) + .set push + .set noreorder + li v0, __NR_gettimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(gettimeofday)
diff --git a/libc/arch-mips64/syscalls/getuid.S b/libc/arch-mips64/syscalls/getuid.S new file mode 100644 index 0000000..3d5f940 --- /dev/null +++ b/libc/arch-mips64/syscalls/getuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + .set push + .set noreorder + li v0, __NR_getuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getuid)
diff --git a/libc/arch-mips64/syscalls/getxattr.S b/libc/arch-mips64/syscalls/getxattr.S new file mode 100644 index 0000000..1c443f2 --- /dev/null +++ b/libc/arch-mips64/syscalls/getxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + .set push + .set noreorder + li v0, __NR_getxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getxattr)
diff --git a/libc/arch-mips64/syscalls/init_module.S b/libc/arch-mips64/syscalls/init_module.S new file mode 100644 index 0000000..3e2f074 --- /dev/null +++ b/libc/arch-mips64/syscalls/init_module.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + .set push + .set noreorder + li v0, __NR_init_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(init_module)
diff --git a/libc/arch-mips64/syscalls/inotify_add_watch.S b/libc/arch-mips64/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..bffdad8 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_add_watch.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + .set push + .set noreorder + li v0, __NR_inotify_add_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_add_watch)
diff --git a/libc/arch-mips64/syscalls/inotify_init1.S b/libc/arch-mips64/syscalls/inotify_init1.S new file mode 100644 index 0000000..c70d101 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_init1.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + .set push + .set noreorder + li v0, __NR_inotify_init1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_init1)
diff --git a/libc/arch-mips64/syscalls/inotify_rm_watch.S b/libc/arch-mips64/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..d893787 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_rm_watch.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + .set push + .set noreorder + li v0, __NR_inotify_rm_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_rm_watch)
diff --git a/libc/arch-mips64/syscalls/kill.S b/libc/arch-mips64/syscalls/kill.S new file mode 100644 index 0000000..475b615 --- /dev/null +++ b/libc/arch-mips64/syscalls/kill.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + .set push + .set noreorder + li v0, __NR_kill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(kill)
diff --git a/libc/arch-mips64/syscalls/klogctl.S b/libc/arch-mips64/syscalls/klogctl.S new file mode 100644 index 0000000..98b9f0b --- /dev/null +++ b/libc/arch-mips64/syscalls/klogctl.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + .set push + .set noreorder + li v0, __NR_syslog + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(klogctl)
diff --git a/libc/arch-mips64/syscalls/lgetxattr.S b/libc/arch-mips64/syscalls/lgetxattr.S new file mode 100644 index 0000000..55d7c42 --- /dev/null +++ b/libc/arch-mips64/syscalls/lgetxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + .set push + .set noreorder + li v0, __NR_lgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lgetxattr)
diff --git a/libc/arch-mips64/syscalls/linkat.S b/libc/arch-mips64/syscalls/linkat.S new file mode 100644 index 0000000..df749eb --- /dev/null +++ b/libc/arch-mips64/syscalls/linkat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + .set push + .set noreorder + li v0, __NR_linkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(linkat)
diff --git a/libc/arch-mips64/syscalls/listen.S b/libc/arch-mips64/syscalls/listen.S new file mode 100644 index 0000000..195cade --- /dev/null +++ b/libc/arch-mips64/syscalls/listen.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + .set push + .set noreorder + li v0, __NR_listen + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(listen)
diff --git a/libc/arch-mips64/syscalls/listxattr.S b/libc/arch-mips64/syscalls/listxattr.S new file mode 100644 index 0000000..30b0f2b --- /dev/null +++ b/libc/arch-mips64/syscalls/listxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + .set push + .set noreorder + li v0, __NR_listxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(listxattr)
diff --git a/libc/arch-mips64/syscalls/llistxattr.S b/libc/arch-mips64/syscalls/llistxattr.S new file mode 100644 index 0000000..d349116 --- /dev/null +++ b/libc/arch-mips64/syscalls/llistxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + .set push + .set noreorder + li v0, __NR_llistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(llistxattr)
diff --git a/libc/arch-mips64/syscalls/lremovexattr.S b/libc/arch-mips64/syscalls/lremovexattr.S new file mode 100644 index 0000000..db4e4d3 --- /dev/null +++ b/libc/arch-mips64/syscalls/lremovexattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + .set push + .set noreorder + li v0, __NR_lremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lremovexattr)
diff --git a/libc/arch-mips64/syscalls/lseek.S b/libc/arch-mips64/syscalls/lseek.S new file mode 100644 index 0000000..3bfc29d --- /dev/null +++ b/libc/arch-mips64/syscalls/lseek.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + .set push + .set noreorder + li v0, __NR_lseek + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lseek) + +ALIAS_SYMBOL(lseek64, lseek)
diff --git a/libc/arch-mips64/syscalls/lsetxattr.S b/libc/arch-mips64/syscalls/lsetxattr.S new file mode 100644 index 0000000..c161eb3 --- /dev/null +++ b/libc/arch-mips64/syscalls/lsetxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + .set push + .set noreorder + li v0, __NR_lsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lsetxattr)
diff --git a/libc/arch-mips64/syscalls/madvise.S b/libc/arch-mips64/syscalls/madvise.S new file mode 100644 index 0000000..88f3830 --- /dev/null +++ b/libc/arch-mips64/syscalls/madvise.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + .set push + .set noreorder + li v0, __NR_madvise + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(madvise)
diff --git a/libc/arch-mips64/syscalls/mincore.S b/libc/arch-mips64/syscalls/mincore.S new file mode 100644 index 0000000..695c9b2 --- /dev/null +++ b/libc/arch-mips64/syscalls/mincore.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + .set push + .set noreorder + li v0, __NR_mincore + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mincore)
diff --git a/libc/arch-mips64/syscalls/mkdirat.S b/libc/arch-mips64/syscalls/mkdirat.S new file mode 100644 index 0000000..71cdfd1 --- /dev/null +++ b/libc/arch-mips64/syscalls/mkdirat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + .set push + .set noreorder + li v0, __NR_mkdirat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mkdirat)
diff --git a/libc/arch-mips64/syscalls/mknodat.S b/libc/arch-mips64/syscalls/mknodat.S new file mode 100644 index 0000000..9943e49 --- /dev/null +++ b/libc/arch-mips64/syscalls/mknodat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + .set push + .set noreorder + li v0, __NR_mknodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mknodat)
diff --git a/libc/arch-mips64/syscalls/mlock.S b/libc/arch-mips64/syscalls/mlock.S new file mode 100644 index 0000000..081f12b --- /dev/null +++ b/libc/arch-mips64/syscalls/mlock.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + .set push + .set noreorder + li v0, __NR_mlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mlock)
diff --git a/libc/arch-mips64/syscalls/mlockall.S b/libc/arch-mips64/syscalls/mlockall.S new file mode 100644 index 0000000..0e158f4 --- /dev/null +++ b/libc/arch-mips64/syscalls/mlockall.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + .set push + .set noreorder + li v0, __NR_mlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mlockall)
diff --git a/libc/arch-mips64/syscalls/mmap.S b/libc/arch-mips64/syscalls/mmap.S new file mode 100644 index 0000000..cc53eb2 --- /dev/null +++ b/libc/arch-mips64/syscalls/mmap.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mmap) + .set push + .set noreorder + li v0, __NR_mmap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mmap) + +ALIAS_SYMBOL(mmap64, mmap)
diff --git a/libc/arch-mips64/syscalls/mount.S b/libc/arch-mips64/syscalls/mount.S new file mode 100644 index 0000000..50c7541 --- /dev/null +++ b/libc/arch-mips64/syscalls/mount.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + .set push + .set noreorder + li v0, __NR_mount + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mount)
diff --git a/libc/arch-mips64/syscalls/mprotect.S b/libc/arch-mips64/syscalls/mprotect.S new file mode 100644 index 0000000..d755489 --- /dev/null +++ b/libc/arch-mips64/syscalls/mprotect.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + .set push + .set noreorder + li v0, __NR_mprotect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mprotect)
diff --git a/libc/arch-mips64/syscalls/msync.S b/libc/arch-mips64/syscalls/msync.S new file mode 100644 index 0000000..efe31c1 --- /dev/null +++ b/libc/arch-mips64/syscalls/msync.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + .set push + .set noreorder + li v0, __NR_msync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(msync)
diff --git a/libc/arch-mips64/syscalls/munlock.S b/libc/arch-mips64/syscalls/munlock.S new file mode 100644 index 0000000..44b930a --- /dev/null +++ b/libc/arch-mips64/syscalls/munlock.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + .set push + .set noreorder + li v0, __NR_munlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munlock)
diff --git a/libc/arch-mips64/syscalls/munlockall.S b/libc/arch-mips64/syscalls/munlockall.S new file mode 100644 index 0000000..ffeb5e1 --- /dev/null +++ b/libc/arch-mips64/syscalls/munlockall.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + .set push + .set noreorder + li v0, __NR_munlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munlockall)
diff --git a/libc/arch-mips64/syscalls/munmap.S b/libc/arch-mips64/syscalls/munmap.S new file mode 100644 index 0000000..cd0c05c --- /dev/null +++ b/libc/arch-mips64/syscalls/munmap.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + .set push + .set noreorder + li v0, __NR_munmap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munmap)
diff --git a/libc/arch-mips64/syscalls/nanosleep.S b/libc/arch-mips64/syscalls/nanosleep.S new file mode 100644 index 0000000..bdaf256 --- /dev/null +++ b/libc/arch-mips64/syscalls/nanosleep.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + .set push + .set noreorder + li v0, __NR_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(nanosleep)
diff --git a/libc/arch-mips64/syscalls/personality.S b/libc/arch-mips64/syscalls/personality.S new file mode 100644 index 0000000..6a12c95 --- /dev/null +++ b/libc/arch-mips64/syscalls/personality.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + .set push + .set noreorder + li v0, __NR_personality + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(personality)
diff --git a/libc/arch-mips64/syscalls/pipe2.S b/libc/arch-mips64/syscalls/pipe2.S new file mode 100644 index 0000000..1b08a45 --- /dev/null +++ b/libc/arch-mips64/syscalls/pipe2.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + .set push + .set noreorder + li v0, __NR_pipe2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pipe2)
diff --git a/libc/arch-mips64/syscalls/prctl.S b/libc/arch-mips64/syscalls/prctl.S new file mode 100644 index 0000000..61bb7c2 --- /dev/null +++ b/libc/arch-mips64/syscalls/prctl.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + .set push + .set noreorder + li v0, __NR_prctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(prctl)
diff --git a/libc/arch-mips64/syscalls/pread64.S b/libc/arch-mips64/syscalls/pread64.S new file mode 100644 index 0000000..7965ba9 --- /dev/null +++ b/libc/arch-mips64/syscalls/pread64.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + .set push + .set noreorder + li v0, __NR_pread64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pread64) + +ALIAS_SYMBOL(pread, pread64)
diff --git a/libc/arch-mips64/syscalls/preadv.S b/libc/arch-mips64/syscalls/preadv.S new file mode 100644 index 0000000..df43a8d --- /dev/null +++ b/libc/arch-mips64/syscalls/preadv.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(preadv) + .set push + .set noreorder + li v0, __NR_preadv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(preadv) + +ALIAS_SYMBOL(preadv64, preadv)
diff --git a/libc/arch-mips64/syscalls/prlimit64.S b/libc/arch-mips64/syscalls/prlimit64.S new file mode 100644 index 0000000..e04a5b6 --- /dev/null +++ b/libc/arch-mips64/syscalls/prlimit64.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + .set push + .set noreorder + li v0, __NR_prlimit64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(prlimit64) + +ALIAS_SYMBOL(prlimit, prlimit64)
diff --git a/libc/arch-mips64/syscalls/process_vm_readv.S b/libc/arch-mips64/syscalls/process_vm_readv.S new file mode 100644 index 0000000..f3c7372 --- /dev/null +++ b/libc/arch-mips64/syscalls/process_vm_readv.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_readv) + .set push + .set noreorder + li v0, __NR_process_vm_readv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(process_vm_readv)
diff --git a/libc/arch-mips64/syscalls/process_vm_writev.S b/libc/arch-mips64/syscalls/process_vm_writev.S new file mode 100644 index 0000000..0e8140b --- /dev/null +++ b/libc/arch-mips64/syscalls/process_vm_writev.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_writev) + .set push + .set noreorder + li v0, __NR_process_vm_writev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(process_vm_writev)
diff --git a/libc/arch-mips64/syscalls/pwrite64.S b/libc/arch-mips64/syscalls/pwrite64.S new file mode 100644 index 0000000..97e0183 --- /dev/null +++ b/libc/arch-mips64/syscalls/pwrite64.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + .set push + .set noreorder + li v0, __NR_pwrite64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pwrite64) + +ALIAS_SYMBOL(pwrite, pwrite64)
diff --git a/libc/arch-mips64/syscalls/pwritev.S b/libc/arch-mips64/syscalls/pwritev.S new file mode 100644 index 0000000..f55cec0 --- /dev/null +++ b/libc/arch-mips64/syscalls/pwritev.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwritev) + .set push + .set noreorder + li v0, __NR_pwritev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pwritev) + +ALIAS_SYMBOL(pwritev64, pwritev)
diff --git a/libc/arch-mips64/syscalls/quotactl.S b/libc/arch-mips64/syscalls/quotactl.S new file mode 100644 index 0000000..861947c --- /dev/null +++ b/libc/arch-mips64/syscalls/quotactl.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(quotactl) + .set push + .set noreorder + li v0, __NR_quotactl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(quotactl)
diff --git a/libc/arch-mips64/syscalls/read.S b/libc/arch-mips64/syscalls/read.S new file mode 100644 index 0000000..74d39df --- /dev/null +++ b/libc/arch-mips64/syscalls/read.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + .set push + .set noreorder + li v0, __NR_read + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(read)
diff --git a/libc/arch-mips64/syscalls/readahead.S b/libc/arch-mips64/syscalls/readahead.S new file mode 100644 index 0000000..ae511d9 --- /dev/null +++ b/libc/arch-mips64/syscalls/readahead.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + .set push + .set noreorder + li v0, __NR_readahead + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readahead)
diff --git a/libc/arch-mips64/syscalls/readlinkat.S b/libc/arch-mips64/syscalls/readlinkat.S new file mode 100644 index 0000000..473a946 --- /dev/null +++ b/libc/arch-mips64/syscalls/readlinkat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + .set push + .set noreorder + li v0, __NR_readlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readlinkat)
diff --git a/libc/arch-mips64/syscalls/readv.S b/libc/arch-mips64/syscalls/readv.S new file mode 100644 index 0000000..daa800c --- /dev/null +++ b/libc/arch-mips64/syscalls/readv.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + .set push + .set noreorder + li v0, __NR_readv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readv)
diff --git a/libc/arch-mips64/syscalls/recvfrom.S b/libc/arch-mips64/syscalls/recvfrom.S new file mode 100644 index 0000000..4c9b5fa --- /dev/null +++ b/libc/arch-mips64/syscalls/recvfrom.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + .set push + .set noreorder + li v0, __NR_recvfrom + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvfrom)
diff --git a/libc/arch-mips64/syscalls/recvmmsg.S b/libc/arch-mips64/syscalls/recvmmsg.S new file mode 100644 index 0000000..817250c --- /dev/null +++ b/libc/arch-mips64/syscalls/recvmmsg.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + .set push + .set noreorder + li v0, __NR_recvmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvmmsg)
diff --git a/libc/arch-mips64/syscalls/recvmsg.S b/libc/arch-mips64/syscalls/recvmsg.S new file mode 100644 index 0000000..877899d --- /dev/null +++ b/libc/arch-mips64/syscalls/recvmsg.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + .set push + .set noreorder + li v0, __NR_recvmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvmsg)
diff --git a/libc/arch-mips64/syscalls/removexattr.S b/libc/arch-mips64/syscalls/removexattr.S new file mode 100644 index 0000000..c9d8a0e --- /dev/null +++ b/libc/arch-mips64/syscalls/removexattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + .set push + .set noreorder + li v0, __NR_removexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(removexattr)
diff --git a/libc/arch-mips64/syscalls/renameat.S b/libc/arch-mips64/syscalls/renameat.S new file mode 100644 index 0000000..16b9333 --- /dev/null +++ b/libc/arch-mips64/syscalls/renameat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + .set push + .set noreorder + li v0, __NR_renameat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(renameat)
diff --git a/libc/arch-mips64/syscalls/sched_get_priority_max.S b/libc/arch-mips64/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..67e2675 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_get_priority_max.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + .set push + .set noreorder + li v0, __NR_sched_get_priority_max + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_get_priority_max)
diff --git a/libc/arch-mips64/syscalls/sched_get_priority_min.S b/libc/arch-mips64/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..957f523 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_get_priority_min.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + .set push + .set noreorder + li v0, __NR_sched_get_priority_min + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_get_priority_min)
diff --git a/libc/arch-mips64/syscalls/sched_getparam.S b/libc/arch-mips64/syscalls/sched_getparam.S new file mode 100644 index 0000000..77bb4eb --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_getparam.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + .set push + .set noreorder + li v0, __NR_sched_getparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_getparam)
diff --git a/libc/arch-mips64/syscalls/sched_getscheduler.S b/libc/arch-mips64/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..324fa21 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_getscheduler.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + .set push + .set noreorder + li v0, __NR_sched_getscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_getscheduler)
diff --git a/libc/arch-mips64/syscalls/sched_rr_get_interval.S b/libc/arch-mips64/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..3019554 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_rr_get_interval.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + .set push + .set noreorder + li v0, __NR_sched_rr_get_interval + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_rr_get_interval)
diff --git a/libc/arch-mips64/syscalls/sched_setaffinity.S b/libc/arch-mips64/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..1520902 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setaffinity.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + .set push + .set noreorder + li v0, __NR_sched_setaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setaffinity)
diff --git a/libc/arch-mips64/syscalls/sched_setparam.S b/libc/arch-mips64/syscalls/sched_setparam.S new file mode 100644 index 0000000..a37b15c --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setparam.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + .set push + .set noreorder + li v0, __NR_sched_setparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setparam)
diff --git a/libc/arch-mips64/syscalls/sched_setscheduler.S b/libc/arch-mips64/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..ea4c6c4 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setscheduler.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + .set push + .set noreorder + li v0, __NR_sched_setscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setscheduler)
diff --git a/libc/arch-mips64/syscalls/sched_yield.S b/libc/arch-mips64/syscalls/sched_yield.S new file mode 100644 index 0000000..5d86ea5 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_yield.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + .set push + .set noreorder + li v0, __NR_sched_yield + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_yield)
diff --git a/libc/arch-mips64/syscalls/sendfile.S b/libc/arch-mips64/syscalls/sendfile.S new file mode 100644 index 0000000..a50459e --- /dev/null +++ b/libc/arch-mips64/syscalls/sendfile.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + .set push + .set noreorder + li v0, __NR_sendfile + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendfile) + +ALIAS_SYMBOL(sendfile64, sendfile)
diff --git a/libc/arch-mips64/syscalls/sendmmsg.S b/libc/arch-mips64/syscalls/sendmmsg.S new file mode 100644 index 0000000..4a8d855 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendmmsg.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + .set push + .set noreorder + li v0, __NR_sendmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendmmsg)
diff --git a/libc/arch-mips64/syscalls/sendmsg.S b/libc/arch-mips64/syscalls/sendmsg.S new file mode 100644 index 0000000..519dce4 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendmsg.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + .set push + .set noreorder + li v0, __NR_sendmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendmsg)
diff --git a/libc/arch-mips64/syscalls/sendto.S b/libc/arch-mips64/syscalls/sendto.S new file mode 100644 index 0000000..84efc09 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendto.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + .set push + .set noreorder + li v0, __NR_sendto + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendto)
diff --git a/libc/arch-mips64/syscalls/setdomainname.S b/libc/arch-mips64/syscalls/setdomainname.S new file mode 100644 index 0000000..6cee88e --- /dev/null +++ b/libc/arch-mips64/syscalls/setdomainname.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setdomainname) + .set push + .set noreorder + li v0, __NR_setdomainname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setdomainname)
diff --git a/libc/arch-mips64/syscalls/setfsgid.S b/libc/arch-mips64/syscalls/setfsgid.S new file mode 100644 index 0000000..db1bd7f --- /dev/null +++ b/libc/arch-mips64/syscalls/setfsgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + .set push + .set noreorder + li v0, __NR_setfsgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setfsgid)
diff --git a/libc/arch-mips64/syscalls/setfsuid.S b/libc/arch-mips64/syscalls/setfsuid.S new file mode 100644 index 0000000..4254b18 --- /dev/null +++ b/libc/arch-mips64/syscalls/setfsuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + .set push + .set noreorder + li v0, __NR_setfsuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setfsuid)
diff --git a/libc/arch-mips64/syscalls/setgid.S b/libc/arch-mips64/syscalls/setgid.S new file mode 100644 index 0000000..166a6d6 --- /dev/null +++ b/libc/arch-mips64/syscalls/setgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + .set push + .set noreorder + li v0, __NR_setgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setgid)
diff --git a/libc/arch-mips64/syscalls/setgroups.S b/libc/arch-mips64/syscalls/setgroups.S new file mode 100644 index 0000000..24649f7 --- /dev/null +++ b/libc/arch-mips64/syscalls/setgroups.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + .set push + .set noreorder + li v0, __NR_setgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setgroups)
diff --git a/libc/arch-mips64/syscalls/sethostname.S b/libc/arch-mips64/syscalls/sethostname.S new file mode 100644 index 0000000..2f132a2 --- /dev/null +++ b/libc/arch-mips64/syscalls/sethostname.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sethostname) + .set push + .set noreorder + li v0, __NR_sethostname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sethostname)
diff --git a/libc/arch-mips64/syscalls/setitimer.S b/libc/arch-mips64/syscalls/setitimer.S new file mode 100644 index 0000000..5764573 --- /dev/null +++ b/libc/arch-mips64/syscalls/setitimer.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + .set push + .set noreorder + li v0, __NR_setitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setitimer)
diff --git a/libc/arch-mips64/syscalls/setns.S b/libc/arch-mips64/syscalls/setns.S new file mode 100644 index 0000000..6b6178f --- /dev/null +++ b/libc/arch-mips64/syscalls/setns.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + .set push + .set noreorder + li v0, __NR_setns + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setns)
diff --git a/libc/arch-mips64/syscalls/setpgid.S b/libc/arch-mips64/syscalls/setpgid.S new file mode 100644 index 0000000..233f784 --- /dev/null +++ b/libc/arch-mips64/syscalls/setpgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + .set push + .set noreorder + li v0, __NR_setpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setpgid)
diff --git a/libc/arch-mips64/syscalls/setpriority.S b/libc/arch-mips64/syscalls/setpriority.S new file mode 100644 index 0000000..d88a2ff --- /dev/null +++ b/libc/arch-mips64/syscalls/setpriority.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + .set push + .set noreorder + li v0, __NR_setpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setpriority)
diff --git a/libc/arch-mips64/syscalls/setregid.S b/libc/arch-mips64/syscalls/setregid.S new file mode 100644 index 0000000..c82b4fd --- /dev/null +++ b/libc/arch-mips64/syscalls/setregid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + .set push + .set noreorder + li v0, __NR_setregid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setregid)
diff --git a/libc/arch-mips64/syscalls/setresgid.S b/libc/arch-mips64/syscalls/setresgid.S new file mode 100644 index 0000000..90b2939 --- /dev/null +++ b/libc/arch-mips64/syscalls/setresgid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + .set push + .set noreorder + li v0, __NR_setresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setresgid)
diff --git a/libc/arch-mips64/syscalls/setresuid.S b/libc/arch-mips64/syscalls/setresuid.S new file mode 100644 index 0000000..501ac5d --- /dev/null +++ b/libc/arch-mips64/syscalls/setresuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + .set push + .set noreorder + li v0, __NR_setresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setresuid)
diff --git a/libc/arch-mips64/syscalls/setreuid.S b/libc/arch-mips64/syscalls/setreuid.S new file mode 100644 index 0000000..1b3203c --- /dev/null +++ b/libc/arch-mips64/syscalls/setreuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + .set push + .set noreorder + li v0, __NR_setreuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setreuid)
diff --git a/libc/arch-mips64/syscalls/setrlimit.S b/libc/arch-mips64/syscalls/setrlimit.S new file mode 100644 index 0000000..be6fdc3 --- /dev/null +++ b/libc/arch-mips64/syscalls/setrlimit.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + .set push + .set noreorder + li v0, __NR_setrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setrlimit) + +ALIAS_SYMBOL(setrlimit64, setrlimit)
diff --git a/libc/arch-mips64/syscalls/setsid.S b/libc/arch-mips64/syscalls/setsid.S new file mode 100644 index 0000000..6d872d3 --- /dev/null +++ b/libc/arch-mips64/syscalls/setsid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + .set push + .set noreorder + li v0, __NR_setsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setsid)
diff --git a/libc/arch-mips64/syscalls/setsockopt.S b/libc/arch-mips64/syscalls/setsockopt.S new file mode 100644 index 0000000..b2fc736 --- /dev/null +++ b/libc/arch-mips64/syscalls/setsockopt.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + .set push + .set noreorder + li v0, __NR_setsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setsockopt)
diff --git a/libc/arch-mips64/syscalls/settimeofday.S b/libc/arch-mips64/syscalls/settimeofday.S new file mode 100644 index 0000000..9f1acfe --- /dev/null +++ b/libc/arch-mips64/syscalls/settimeofday.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + .set push + .set noreorder + li v0, __NR_settimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(settimeofday)
diff --git a/libc/arch-mips64/syscalls/setuid.S b/libc/arch-mips64/syscalls/setuid.S new file mode 100644 index 0000000..dcd39ff --- /dev/null +++ b/libc/arch-mips64/syscalls/setuid.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + .set push + .set noreorder + li v0, __NR_setuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setuid)
diff --git a/libc/arch-mips64/syscalls/setxattr.S b/libc/arch-mips64/syscalls/setxattr.S new file mode 100644 index 0000000..4a1b87a --- /dev/null +++ b/libc/arch-mips64/syscalls/setxattr.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + .set push + .set noreorder + li v0, __NR_setxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setxattr)
diff --git a/libc/arch-mips64/syscalls/shutdown.S b/libc/arch-mips64/syscalls/shutdown.S new file mode 100644 index 0000000..d654288 --- /dev/null +++ b/libc/arch-mips64/syscalls/shutdown.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + .set push + .set noreorder + li v0, __NR_shutdown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(shutdown)
diff --git a/libc/arch-mips64/syscalls/sigaltstack.S b/libc/arch-mips64/syscalls/sigaltstack.S new file mode 100644 index 0000000..92778c1 --- /dev/null +++ b/libc/arch-mips64/syscalls/sigaltstack.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + .set push + .set noreorder + li v0, __NR_sigaltstack + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sigaltstack)
diff --git a/libc/arch-mips64/syscalls/socketpair.S b/libc/arch-mips64/syscalls/socketpair.S new file mode 100644 index 0000000..8fbf7a8 --- /dev/null +++ b/libc/arch-mips64/syscalls/socketpair.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + .set push + .set noreorder + li v0, __NR_socketpair + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(socketpair)
diff --git a/libc/arch-mips64/syscalls/splice.S b/libc/arch-mips64/syscalls/splice.S new file mode 100644 index 0000000..ea745cf --- /dev/null +++ b/libc/arch-mips64/syscalls/splice.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + .set push + .set noreorder + li v0, __NR_splice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(splice)
diff --git a/libc/arch-mips64/syscalls/swapoff.S b/libc/arch-mips64/syscalls/swapoff.S new file mode 100644 index 0000000..8c0048d --- /dev/null +++ b/libc/arch-mips64/syscalls/swapoff.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + .set push + .set noreorder + li v0, __NR_swapoff + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(swapoff)
diff --git a/libc/arch-mips64/syscalls/swapon.S b/libc/arch-mips64/syscalls/swapon.S new file mode 100644 index 0000000..e8f6ff2 --- /dev/null +++ b/libc/arch-mips64/syscalls/swapon.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + .set push + .set noreorder + li v0, __NR_swapon + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(swapon)
diff --git a/libc/arch-mips64/syscalls/symlinkat.S b/libc/arch-mips64/syscalls/symlinkat.S new file mode 100644 index 0000000..592b8e2 --- /dev/null +++ b/libc/arch-mips64/syscalls/symlinkat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + .set push + .set noreorder + li v0, __NR_symlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(symlinkat)
diff --git a/libc/arch-mips64/syscalls/sync.S b/libc/arch-mips64/syscalls/sync.S new file mode 100644 index 0000000..8997c1b --- /dev/null +++ b/libc/arch-mips64/syscalls/sync.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sync) + .set push + .set noreorder + li v0, __NR_sync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sync)
diff --git a/libc/arch-mips64/syscalls/sysinfo.S b/libc/arch-mips64/syscalls/sysinfo.S new file mode 100644 index 0000000..a54e158 --- /dev/null +++ b/libc/arch-mips64/syscalls/sysinfo.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sysinfo) + .set push + .set noreorder + li v0, __NR_sysinfo + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sysinfo)
diff --git a/libc/arch-mips64/syscalls/tee.S b/libc/arch-mips64/syscalls/tee.S new file mode 100644 index 0000000..99cf84b --- /dev/null +++ b/libc/arch-mips64/syscalls/tee.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tee) + .set push + .set noreorder + li v0, __NR_tee + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(tee)
diff --git a/libc/arch-mips64/syscalls/tgkill.S b/libc/arch-mips64/syscalls/tgkill.S new file mode 100644 index 0000000..f37f792 --- /dev/null +++ b/libc/arch-mips64/syscalls/tgkill.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tgkill) + .set push + .set noreorder + li v0, __NR_tgkill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(tgkill)
diff --git a/libc/arch-mips64/syscalls/timerfd_create.S b/libc/arch-mips64/syscalls/timerfd_create.S new file mode 100644 index 0000000..0e53a15 --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_create.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_create) + .set push + .set noreorder + li v0, __NR_timerfd_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_create)
diff --git a/libc/arch-mips64/syscalls/timerfd_gettime.S b/libc/arch-mips64/syscalls/timerfd_gettime.S new file mode 100644 index 0000000..26d6832 --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_gettime.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_gettime) + .set push + .set noreorder + li v0, __NR_timerfd_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_gettime)
diff --git a/libc/arch-mips64/syscalls/timerfd_settime.S b/libc/arch-mips64/syscalls/timerfd_settime.S new file mode 100644 index 0000000..b06290e --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_settime.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_settime) + .set push + .set noreorder + li v0, __NR_timerfd_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_settime)
diff --git a/libc/arch-mips64/syscalls/times.S b/libc/arch-mips64/syscalls/times.S new file mode 100644 index 0000000..fa7f64f --- /dev/null +++ b/libc/arch-mips64/syscalls/times.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(times) + .set push + .set noreorder + li v0, __NR_times + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(times)
diff --git a/libc/arch-mips64/syscalls/truncate.S b/libc/arch-mips64/syscalls/truncate.S new file mode 100644 index 0000000..b832796 --- /dev/null +++ b/libc/arch-mips64/syscalls/truncate.S
@@ -0,0 +1,27 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate) + .set push + .set noreorder + li v0, __NR_truncate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(truncate) + +ALIAS_SYMBOL(truncate64, truncate)
diff --git a/libc/arch-mips64/syscalls/umask.S b/libc/arch-mips64/syscalls/umask.S new file mode 100644 index 0000000..9349030 --- /dev/null +++ b/libc/arch-mips64/syscalls/umask.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umask) + .set push + .set noreorder + li v0, __NR_umask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(umask)
diff --git a/libc/arch-mips64/syscalls/umount2.S b/libc/arch-mips64/syscalls/umount2.S new file mode 100644 index 0000000..cc9ad16 --- /dev/null +++ b/libc/arch-mips64/syscalls/umount2.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umount2) + .set push + .set noreorder + li v0, __NR_umount2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(umount2)
diff --git a/libc/arch-mips64/syscalls/uname.S b/libc/arch-mips64/syscalls/uname.S new file mode 100644 index 0000000..16157da --- /dev/null +++ b/libc/arch-mips64/syscalls/uname.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(uname) + .set push + .set noreorder + li v0, __NR_uname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(uname)
diff --git a/libc/arch-mips64/syscalls/unlinkat.S b/libc/arch-mips64/syscalls/unlinkat.S new file mode 100644 index 0000000..4b11679 --- /dev/null +++ b/libc/arch-mips64/syscalls/unlinkat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unlinkat) + .set push + .set noreorder + li v0, __NR_unlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(unlinkat)
diff --git a/libc/arch-mips64/syscalls/unshare.S b/libc/arch-mips64/syscalls/unshare.S new file mode 100644 index 0000000..2c82fea --- /dev/null +++ b/libc/arch-mips64/syscalls/unshare.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unshare) + .set push + .set noreorder + li v0, __NR_unshare + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(unshare)
diff --git a/libc/arch-mips64/syscalls/utimensat.S b/libc/arch-mips64/syscalls/utimensat.S new file mode 100644 index 0000000..48da938 --- /dev/null +++ b/libc/arch-mips64/syscalls/utimensat.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(utimensat) + .set push + .set noreorder + li v0, __NR_utimensat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(utimensat)
diff --git a/libc/arch-mips64/syscalls/vmsplice.S b/libc/arch-mips64/syscalls/vmsplice.S new file mode 100644 index 0000000..3bcae74 --- /dev/null +++ b/libc/arch-mips64/syscalls/vmsplice.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(vmsplice) + .set push + .set noreorder + li v0, __NR_vmsplice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(vmsplice)
diff --git a/libc/arch-mips64/syscalls/wait4.S b/libc/arch-mips64/syscalls/wait4.S new file mode 100644 index 0000000..f9c3974 --- /dev/null +++ b/libc/arch-mips64/syscalls/wait4.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(wait4) + .set push + .set noreorder + li v0, __NR_wait4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(wait4)
diff --git a/libc/arch-mips64/syscalls/write.S b/libc/arch-mips64/syscalls/write.S new file mode 100644 index 0000000..ef9b19e --- /dev/null +++ b/libc/arch-mips64/syscalls/write.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(write) + .set push + .set noreorder + li v0, __NR_write + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(write)
diff --git a/libc/arch-mips64/syscalls/writev.S b/libc/arch-mips64/syscalls/writev.S new file mode 100644 index 0000000..d103d71 --- /dev/null +++ b/libc/arch-mips64/syscalls/writev.S
@@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(writev) + .set push + .set noreorder + li v0, __NR_writev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(writev)
diff --git a/libc/arch-x86/atom/string/cache.h b/libc/arch-x86/atom/string/cache.h new file mode 100644 index 0000000..823bb1e --- /dev/null +++ b/libc/arch-x86/atom/string/cache.h
@@ -0,0 +1,36 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Values are optimized for Atom */ +#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */ +#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */ + +#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2) +#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)
diff --git a/libc/arch-x86/atom/string/sse2-memchr-atom.S b/libc/arch-x86/atom/string/sse2-memchr-atom.S new file mode 100644 index 0000000..013af9b --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-memchr-atom.S
@@ -0,0 +1,556 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define ENTRANCE PUSH (%edi); +#define PARMS 8 +#define RETURN POP (%edi); ret; CFI_PUSH (%edi); + +#define STR1 PARMS +#define STR2 STR1+4 +#define LEN STR2+4 + + .text +ENTRY (memchr) + ENTRANCE + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + mov LEN(%esp), %edx + test %edx, %edx + jz L(return_null) + + punpcklbw %xmm1, %xmm1 + mov %ecx, %edi + punpcklbw %xmm1, %xmm1 + + and $63, %ecx + pshufd $0, %xmm1, %xmm1 + cmp $48, %ecx + ja L(crosscache) + + movdqu (%edi), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(match_case2_prolog) + + sub $16, %edx + jbe L(return_null) + lea 16(%edi), %edi + and $15, %ecx + and $-16, %edi + add %ecx, %edx + sub $64, %edx + jbe L(exit_loop) + jmp L(loop_prolog) + + .p2align 4 +L(crosscache): + and $15, %ecx + and $-16, %edi + movdqa (%edi), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + sar %cl, %eax + test %eax, %eax + + jnz L(match_case2_prolog1) + lea -16(%edx), %edx + add %ecx, %edx + jle L(return_null) + lea 16(%edi), %edi + sub $64, %edx + jbe L(exit_loop) + + .p2align 4 +L(loop_prolog): + movdqa (%edi), %xmm0 + pcmpeqb %xmm1, %xmm0 + xor %ecx, %ecx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 16(%edi), %xmm2 + pcmpeqb %xmm1, %xmm2 + lea 16(%ecx), %ecx + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 32(%edi), %xmm3 + pcmpeqb %xmm1, %xmm3 + lea 16(%ecx), %ecx + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 48(%edi), %xmm4 + pcmpeqb %xmm1, %xmm4 + lea 16(%ecx), %ecx + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(match_case1) + + lea 64(%edi), %edi + sub $64, %edx + jbe L(exit_loop) + + movdqa (%edi), %xmm0 + pcmpeqb %xmm1, %xmm0 + xor %ecx, %ecx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 16(%edi), %xmm2 + pcmpeqb %xmm1, %xmm2 + lea 16(%ecx), %ecx + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 32(%edi), %xmm3 + pcmpeqb %xmm1, %xmm3 + lea 16(%ecx), %ecx + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(match_case1) + + movdqa 48(%edi), %xmm4 + pcmpeqb %xmm1, %xmm4 + lea 16(%ecx), %ecx + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(match_case1) + + lea 64(%edi), %edi + mov %edi, %ecx + and $-64, %edi + and $63, %ecx + add %ecx, %edx + + .p2align 4 +L(align64_loop): + sub $64, %edx + jbe L(exit_loop) + movdqa (%edi), %xmm0 + movdqa 16(%edi), %xmm2 + movdqa 32(%edi), %xmm3 + movdqa 48(%edi), %xmm4 + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm1, %xmm2 + pcmpeqb %xmm1, %xmm3 + pcmpeqb %xmm1, %xmm4 + + pmaxub %xmm0, %xmm3 + pmaxub %xmm2, %xmm4 + pmaxub %xmm3, %xmm4 + add $64, %edi + pmovmskb %xmm4, %eax + + test %eax, %eax + jz L(align64_loop) + + sub $64, %edi + + pmovmskb %xmm0, %eax + xor %ecx, %ecx + test %eax, %eax + jnz L(match_case1) + + pmovmskb %xmm2, %eax + lea 16(%ecx), %ecx + test %eax, %eax + jnz L(match_case1) + + movdqa 32(%edi), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + lea 16(%ecx), %ecx + test %eax, %eax + jnz L(match_case1) + + pcmpeqb 48(%edi), %xmm1 + pmovmskb %xmm1, %eax + lea 16(%ecx), %ecx + + .p2align 4 +L(match_case1): + add %ecx, %edi + test %al, %al + jz L(match_case1_high) + mov %al, %cl + and $15, %cl + jz L(match_case1_8) + test $0x01, %al + jnz L(exit_case1_1) + test $0x02, %al + jnz L(exit_case1_2) + test $0x04, %al + jnz L(exit_case1_3) + lea 3(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_8): + test $0x10, %al + jnz L(exit_case1_5) + test $0x20, %al + jnz L(exit_case1_6) + test $0x40, %al + jnz L(exit_case1_7) + lea 7(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_high): + mov %ah, %ch + and $15, %ch + jz L(match_case1_high_8) + test $0x01, %ah + jnz L(exit_case1_9) + test $0x02, %ah + jnz L(exit_case1_10) + test $0x04, %ah + jnz L(exit_case1_11) + lea 11(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_high_8): + test $0x10, %ah + jnz L(exit_case1_13) + test $0x20, %ah + jnz L(exit_case1_14) + test $0x40, %ah + jnz L(exit_case1_15) + lea 15(%edi), %eax + RETURN + + .p2align 4 +L(exit_loop): + add $64, %edx + + movdqa (%edi), %xmm0 + pcmpeqb %xmm1, %xmm0 + xor %ecx, %ecx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(match_case2) + cmp $16, %edx + jbe L(return_null) + + movdqa 16(%edi), %xmm2 + pcmpeqb %xmm1, %xmm2 + lea 16(%ecx), %ecx + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(match_case2) + cmp $32, %edx + jbe L(return_null) + + movdqa 32(%edi), %xmm3 + pcmpeqb %xmm1, %xmm3 + lea 16(%ecx), %ecx + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(match_case2) + cmp $48, %edx + jbe L(return_null) + + pcmpeqb 48(%edi), %xmm1 + lea 16(%ecx), %ecx + pmovmskb %xmm1, %eax + test %eax, %eax + jnz L(match_case2) + + xor %eax, %eax + RETURN + + .p2align 4 +L(exit_case1_1): + mov %edi, %eax + RETURN + + .p2align 4 +L(exit_case1_2): + lea 1(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_3): + lea 2(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_5): + lea 4(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_6): + lea 5(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_7): + lea 6(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_9): + lea 8(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_10): + lea 9(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_11): + lea 10(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_13): + lea 12(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_14): + lea 13(%edi), %eax + RETURN + + .p2align 4 +L(exit_case1_15): + lea 14(%edi), %eax + RETURN + + .p2align 4 +L(match_case2): + sub %ecx, %edx +L(match_case2_prolog1): + add %ecx, %edi +L(match_case2_prolog): + test %al, %al + jz L(match_case2_high) + mov %al, %cl + and $15, %cl + jz L(match_case2_8) + test $0x01, %al + jnz L(exit_case2_1) + test $0x02, %al + jnz L(exit_case2_2) + test $0x04, %al + jnz L(exit_case2_3) + sub $4, %edx + jb L(return_null) + lea 3(%edi), %eax + RETURN + + .p2align 4 +L(match_case2_8): + test $0x10, %al + jnz L(exit_case2_5) + test $0x20, %al + jnz L(exit_case2_6) + test $0x40, %al + jnz L(exit_case2_7) + sub $8, %edx + jb L(return_null) + lea 7(%edi), %eax + RETURN + + .p2align 4 +L(match_case2_high): + mov %ah, %ch + and $15, %ch + jz L(match_case2_high_8) + test $0x01, %ah + jnz L(exit_case2_9) + test $0x02, %ah + jnz L(exit_case2_10) + test $0x04, %ah + jnz L(exit_case2_11) + sub $12, %edx + jb L(return_null) + lea 11(%edi), %eax + RETURN + + .p2align 4 +L(match_case2_high_8): + test $0x10, %ah + jnz L(exit_case2_13) + test $0x20, %ah + jnz L(exit_case2_14) + test $0x40, %ah + jnz L(exit_case2_15) + sub $16, %edx + jb L(return_null) + lea 15(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_1): + mov %edi, %eax + RETURN + + .p2align 4 +L(exit_case2_2): + sub $2, %edx + jb L(return_null) + lea 1(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_3): + sub $3, %edx + jb L(return_null) + lea 2(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_5): + sub $5, %edx + jb L(return_null) + lea 4(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_6): + sub $6, %edx + jb L(return_null) + lea 5(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_7): + sub $7, %edx + jb L(return_null) + lea 6(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_9): + sub $9, %edx + jb L(return_null) + lea 8(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_10): + sub $10, %edx + jb L(return_null) + lea 9(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_11): + sub $11, %edx + jb L(return_null) + lea 10(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_13): + sub $13, %edx + jb L(return_null) + lea 12(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_14): + sub $14, %edx + jb L(return_null) + lea 13(%edi), %eax + RETURN + + .p2align 4 +L(exit_case2_15): + sub $15, %edx + jb L(return_null) + lea 14(%edi), %eax + RETURN + .p2align 4 +L(return_null): + xor %eax, %eax + RETURN +END (memchr)
diff --git a/libc/arch-x86/atom/string/sse2-memrchr-atom.S b/libc/arch-x86/atom/string/sse2-memrchr-atom.S new file mode 100644 index 0000000..1aa1a1a --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-memrchr-atom.S
@@ -0,0 +1,778 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 4 +#define STR1 PARMS +#define STR2 STR1+4 +#define LEN STR2+4 + + .text +ENTRY (memrchr) + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + mov LEN(%esp), %edx + + test %edx, %edx + jz L(return_null) + sub $16, %edx + jbe L(length_less16) + + punpcklbw %xmm1, %xmm1 + add %edx, %ecx + punpcklbw %xmm1, %xmm1 + + movdqu (%ecx), %xmm0 + pshufd $0, %xmm1, %xmm1 + pcmpeqb %xmm1, %xmm0 + + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(exit_dispatch) + + sub $64, %ecx + mov %ecx, %eax + and $15, %eax + jz L(loop_prolog) + + add $16, %ecx + add $16, %edx + and $-16, %ecx + sub %eax, %edx + + .p2align 4 +/* Loop start on aligned string. */ +L(loop_prolog): + sub $64, %edx + jbe L(exit_loop) + + movdqa 48(%ecx), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches48) + + movdqa 32(%ecx), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 16(%ecx), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches16) + + movdqa (%ecx), %xmm4 + pcmpeqb %xmm1, %xmm4 + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(exit_dispatch) + + sub $64, %ecx + sub $64, %edx + jbe L(exit_loop) + + movdqa 48(%ecx), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches48) + + movdqa 32(%ecx), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 16(%ecx), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches16) + + movdqa (%ecx), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(exit_dispatch) + + mov %ecx, %eax + and $63, %eax + test %eax, %eax + jz L(align64_loop) + + add $64, %ecx + add $64, %edx + and $-64, %ecx + sub %eax, %edx + + .p2align 4 +L(align64_loop): + sub $64, %ecx + sub $64, %edx + jbe L(exit_loop) + + movdqa (%ecx), %xmm0 + movdqa 16(%ecx), %xmm2 + movdqa 32(%ecx), %xmm3 + movdqa 48(%ecx), %xmm4 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm1, %xmm2 + pcmpeqb %xmm1, %xmm3 + pcmpeqb %xmm1, %xmm4 + + pmaxub %xmm3, %xmm0 + pmaxub %xmm4, %xmm2 + pmaxub %xmm0, %xmm2 + pmovmskb %xmm2, %eax + + test %eax, %eax + jz L(align64_loop) + + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(matches48) + + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 16(%ecx), %xmm2 + + pcmpeqb %xmm1, %xmm2 + pcmpeqb (%ecx), %xmm1 + + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + pmovmskb %xmm1, %eax + test %ah, %ah + jnz L(exit_dispatch_high) + mov %al, %dl + and $15 << 4, %dl + jnz L(exit_dispatch_8) + test $0x08, %al + jnz L(exit_4) + test $0x04, %al + jnz L(exit_3) + test $0x02, %al + jnz L(exit_2) + mov %ecx, %eax + ret + + .p2align 4 +L(exit_loop): + add $64, %edx + cmp $32, %edx + jbe L(exit_loop_32) + + movdqa 48(%ecx), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches48) + + movdqa 32(%ecx), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 16(%ecx), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches16_1) + cmp $48, %edx + jbe L(return_null) + + pcmpeqb (%ecx), %xmm1 + pmovmskb %xmm1, %eax + test %eax, %eax + jnz L(matches0_1) + xor %eax, %eax + ret + + .p2align 4 +L(exit_loop_32): + movdqa 48(%ecx), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches48_1) + cmp $16, %edx + jbe L(return_null) + + pcmpeqb 32(%ecx), %xmm1 + pmovmskb %xmm1, %eax + test %eax, %eax + jnz L(matches32_1) + xor %eax, %eax + ret + + .p2align 4 +L(matches16): + lea 16(%ecx), %ecx + test %ah, %ah + jnz L(exit_dispatch_high) + mov %al, %dl + and $15 << 4, %dl + jnz L(exit_dispatch_8) + test $0x08, %al + jnz L(exit_4) + test $0x04, %al + jnz L(exit_3) + test $0x02, %al + jnz L(exit_2) + mov %ecx, %eax + ret + + .p2align 4 +L(matches32): + lea 32(%ecx), %ecx + test %ah, %ah + jnz L(exit_dispatch_high) + mov %al, %dl + and $15 << 4, %dl + jnz L(exit_dispatch_8) + test $0x08, %al + jnz L(exit_4) + test $0x04, %al + jnz L(exit_3) + test $0x02, %al + jnz L(exit_2) + mov %ecx, %eax + ret + + .p2align 4 +L(matches48): + lea 48(%ecx), %ecx + + .p2align 4 +L(exit_dispatch): + test %ah, %ah + jnz L(exit_dispatch_high) + mov %al, %dl + and $15 << 4, %dl + jnz L(exit_dispatch_8) + test $0x08, %al + jnz L(exit_4) + test $0x04, %al + jnz L(exit_3) + test $0x02, %al + jnz L(exit_2) + mov %ecx, %eax + ret + + .p2align 4 +L(exit_dispatch_8): + test $0x80, %al + jnz L(exit_8) + test $0x40, %al + jnz L(exit_7) + test $0x20, %al + jnz L(exit_6) + lea 4(%ecx), %eax + ret + + .p2align 4 +L(exit_dispatch_high): + mov %ah, %dh + and $15 << 4, %dh + jnz L(exit_dispatch_high_8) + test $0x08, %ah + jnz L(exit_12) + test $0x04, %ah + jnz L(exit_11) + test $0x02, %ah + jnz L(exit_10) + lea 8(%ecx), %eax + ret + + .p2align 4 +L(exit_dispatch_high_8): + test $0x80, %ah + jnz L(exit_16) + test $0x40, %ah + jnz L(exit_15) + test $0x20, %ah + jnz L(exit_14) + lea 12(%ecx), %eax + ret + + .p2align 4 +L(exit_2): + lea 1(%ecx), %eax + ret + + .p2align 4 +L(exit_3): + lea 2(%ecx), %eax + ret + + .p2align 4 +L(exit_4): + lea 3(%ecx), %eax + ret + + .p2align 4 +L(exit_6): + lea 5(%ecx), %eax + ret + + .p2align 4 +L(exit_7): + lea 6(%ecx), %eax + ret + + .p2align 4 +L(exit_8): + lea 7(%ecx), %eax + ret + + .p2align 4 +L(exit_10): + lea 9(%ecx), %eax + ret + + .p2align 4 +L(exit_11): + lea 10(%ecx), %eax + ret + + .p2align 4 +L(exit_12): + lea 11(%ecx), %eax + ret + + .p2align 4 +L(exit_14): + lea 13(%ecx), %eax + ret + + .p2align 4 +L(exit_15): + lea 14(%ecx), %eax + ret + + .p2align 4 +L(exit_16): + lea 15(%ecx), %eax + ret + + .p2align 4 +L(matches0_1): + lea -64(%edx), %edx + + test %ah, %ah + jnz L(exit_dispatch_1_high) + mov %al, %ah + and $15 << 4, %ah + jnz L(exit_dispatch_1_8) + test $0x08, %al + jnz L(exit_1_4) + test $0x04, %al + jnz L(exit_1_3) + test $0x02, %al + jnz L(exit_1_2) + + add $0, %edx + jl L(return_null) + mov %ecx, %eax + ret + + .p2align 4 +L(matches16_1): + lea -48(%edx), %edx + lea 16(%ecx), %ecx + + test %ah, %ah + jnz L(exit_dispatch_1_high) + mov %al, %ah + and $15 << 4, %ah + jnz L(exit_dispatch_1_8) + test $0x08, %al + jnz L(exit_1_4) + test $0x04, %al + jnz L(exit_1_3) + test $0x02, %al + jnz L(exit_1_2) + + add $0, %edx + jl L(return_null) + mov %ecx, %eax + ret + + .p2align 4 +L(matches32_1): + lea -32(%edx), %edx + lea 32(%ecx), %ecx + + test %ah, %ah + jnz L(exit_dispatch_1_high) + mov %al, %ah + and $15 << 4, %ah + jnz L(exit_dispatch_1_8) + test $0x08, %al + jnz L(exit_1_4) + test $0x04, %al + jnz L(exit_1_3) + test $0x02, %al + jnz L(exit_1_2) + + add $0, %edx + jl L(return_null) + mov %ecx, %eax + ret + + .p2align 4 +L(matches48_1): + lea -16(%edx), %edx + lea 48(%ecx), %ecx + + .p2align 4 +L(exit_dispatch_1): + test %ah, %ah + jnz L(exit_dispatch_1_high) + mov %al, %ah + and $15 << 4, %ah + jnz L(exit_dispatch_1_8) + test $0x08, %al + jnz L(exit_1_4) + test $0x04, %al + jnz L(exit_1_3) + test $0x02, %al + jnz L(exit_1_2) + + add $0, %edx + jl L(return_null) + mov %ecx, %eax + ret + + .p2align 4 +L(exit_dispatch_1_8): + test $0x80, %al + jnz L(exit_1_8) + test $0x40, %al + jnz L(exit_1_7) + test $0x20, %al + jnz L(exit_1_6) + + add $4, %edx + jl L(return_null) + lea 4(%ecx), %eax + ret + + .p2align 4 +L(exit_dispatch_1_high): + mov %ah, %al + and $15 << 4, %al + jnz L(exit_dispatch_1_high_8) + test $0x08, %ah + jnz L(exit_1_12) + test $0x04, %ah + jnz L(exit_1_11) + test $0x02, %ah + jnz L(exit_1_10) + + add $8, %edx + jl L(return_null) + lea 8(%ecx), %eax + ret + + .p2align 4 +L(exit_dispatch_1_high_8): + test $0x80, %ah + jnz L(exit_1_16) + test $0x40, %ah + jnz L(exit_1_15) + test $0x20, %ah + jnz L(exit_1_14) + + add $12, %edx + jl L(return_null) + lea 12(%ecx), %eax + ret + + .p2align 4 +L(exit_1_2): + add $1, %edx + jl L(return_null) + lea 1(%ecx), %eax + ret + + .p2align 4 +L(exit_1_3): + add $2, %edx + jl L(return_null) + lea 2(%ecx), %eax + ret + + .p2align 4 +L(exit_1_4): + add $3, %edx + jl L(return_null) + lea 3(%ecx), %eax + ret + + .p2align 4 +L(exit_1_6): + add $5, %edx + jl L(return_null) + lea 5(%ecx), %eax + ret + + .p2align 4 +L(exit_1_7): + add $6, %edx + jl L(return_null) + lea 6(%ecx), %eax + ret + + .p2align 4 +L(exit_1_8): + add $7, %edx + jl L(return_null) + lea 7(%ecx), %eax + ret + + .p2align 4 +L(exit_1_10): + add $9, %edx + jl L(return_null) + lea 9(%ecx), %eax + ret + + .p2align 4 +L(exit_1_11): + add $10, %edx + jl L(return_null) + lea 10(%ecx), %eax + ret + + .p2align 4 +L(exit_1_12): + add $11, %edx + jl L(return_null) + lea 11(%ecx), %eax + ret + + .p2align 4 +L(exit_1_14): + add $13, %edx + jl L(return_null) + lea 13(%ecx), %eax + ret + + .p2align 4 +L(exit_1_15): + add $14, %edx + jl L(return_null) + lea 14(%ecx), %eax + ret + + .p2align 4 +L(exit_1_16): + add $15, %edx + jl L(return_null) + lea 15(%ecx), %eax + ret + + .p2align 4 +L(return_null): + xor %eax, %eax + ret + + .p2align 4 +L(length_less16_offset0): + mov %dl, %cl + pcmpeqb (%eax), %xmm1 + + mov $1, %edx + sal %cl, %edx + sub $1, %edx + + mov %eax, %ecx + pmovmskb %xmm1, %eax + + and %edx, %eax + test %eax, %eax + jnz L(exit_dispatch) + + xor %eax, %eax + ret + + .p2align 4 +L(length_less16): + punpcklbw %xmm1, %xmm1 + add $16, %edx + punpcklbw %xmm1, %xmm1 + + mov %ecx, %eax + pshufd $0, %xmm1, %xmm1 + + and $15, %ecx + jz L(length_less16_offset0) + + PUSH (%edi) + + mov %cl, %dh + add %dl, %dh + and $-16, %eax + + sub $16, %dh + ja L(length_less16_part2) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edi + + sar %cl, %edi + add %ecx, %eax + mov %dl, %cl + + mov $1, %edx + sal %cl, %edx + sub $1, %edx + + and %edx, %edi + test %edi, %edi + jz L(ret_null) + + bsr %edi, %edi + add %edi, %eax + POP (%edi) + ret + + CFI_PUSH (%edi) + + .p2align 4 +L(length_less16_part2): + movdqa 16(%eax), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %edi + + mov %cl, %ch + + mov %dh, %cl + mov $1, %edx + sal %cl, %edx + sub $1, %edx + + and %edx, %edi + + test %edi, %edi + jnz L(length_less16_part2_return) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edi + + mov %ch, %cl + sar %cl, %edi + test %edi, %edi + jz L(ret_null) + + bsr %edi, %edi + add %edi, %eax + xor %ch, %ch + add %ecx, %eax + POP (%edi) + ret + + CFI_PUSH (%edi) + + .p2align 4 +L(length_less16_part2_return): + bsr %edi, %edi + lea 16(%eax, %edi), %eax + POP (%edi) + ret + + CFI_PUSH (%edi) + + .p2align 4 +L(ret_null): + xor %eax, %eax + POP (%edi) + ret + +END (memrchr)
diff --git a/libc/arch-x86/atom/string/sse2-memset-atom.S b/libc/arch-x86/atom/string/sse2-memset-atom.S new file mode 100644 index 0000000..4e211ca --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-memset-atom.S
@@ -0,0 +1,842 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <private/bionic_asm.h> + +#include "cache.h" + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef ALIGN +# define ALIGN(n) .p2align n +#endif + +#define CFI_PUSH(REG) \ + .cfi_adjust_cfa_offset 4; \ + .cfi_rel_offset REG, 0 + +#define CFI_POP(REG) \ + .cfi_adjust_cfa_offset -4; \ + .cfi_restore REG + +#define PUSH(REG) pushl REG; CFI_PUSH(REG) +#define POP(REG) popl REG; CFI_POP(REG) + +#define PARMS 8 /* Preserve EBX. */ +#define DST PARMS +#define CHR (DST+4) +#define LEN (CHR+4) +#define CHK_DST_LEN (LEN+4) +#define SETRTNVAL movl DST(%esp), %eax + +#define ENTRANCE PUSH(%ebx); +#define RETURN_END POP(%ebx); ret +#define RETURN RETURN_END; CFI_PUSH(%ebx) +#define JMPTBL(I, B) I - B + +/* Load an entry in a jump table into EBX and branch to it. TABLE is a + jump table with relative offsets. */ +# define BRANCH_TO_JMPTBL_ENTRY(TABLE) \ + /* We first load PC into EBX. */ \ + call __x86.get_pc_thunk.bx; \ + /* Get the address of the jump table. */ \ + add $(TABLE - .), %ebx; \ + /* Get the entry and convert the relative offset to the \ + absolute address. */ \ + add (%ebx,%ecx,4), %ebx; \ + add %ecx, %edx; \ + /* We loaded the jump table and adjusted EDX. Go. */ \ + jmp *%ebx + + .section .gnu.linkonce.t.__x86.get_pc_thunk.bx,"ax",@progbits + .globl __x86.get_pc_thunk.bx + .hidden __x86.get_pc_thunk.bx + ALIGN(4) + .type __x86.get_pc_thunk.bx,@function +__x86.get_pc_thunk.bx: + movl (%esp), %ebx + ret + +ENTRY(__memset_chk) + ENTRANCE + + movl LEN(%esp), %ecx + cmpl CHK_DST_LEN(%esp), %ecx + jna L(memset_length_loaded) + + POP(%ebx) // Undo ENTRANCE without returning. + jmp __memset_chk_fail +END(__memset_chk) + + .section .text.sse2,"ax",@progbits + ALIGN(4) +ENTRY(memset) + ENTRANCE + + movl LEN(%esp), %ecx +L(memset_length_loaded): + movzbl CHR(%esp), %eax + movb %al, %ah + /* Fill the whole EAX with pattern. */ + movl %eax, %edx + shl $16, %eax + or %edx, %eax + movl DST(%esp), %edx + cmp $32, %ecx + jae L(32bytesormore) + +L(write_less32bytes): + BRANCH_TO_JMPTBL_ENTRY(L(table_less_32bytes)) + + + .pushsection .rodata.sse2,"a",@progbits + ALIGN(2) +L(table_less_32bytes): + .int JMPTBL(L(write_0bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_1bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_2bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_3bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_4bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_5bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_6bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_7bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_8bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_9bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_10bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_11bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_12bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_13bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_14bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_15bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_16bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_17bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_18bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_19bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_20bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_21bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_22bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_23bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_24bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_25bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_26bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_27bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_28bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_29bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_30bytes), L(table_less_32bytes)) + .int JMPTBL(L(write_31bytes), L(table_less_32bytes)) + .popsection + + ALIGN(4) +L(write_28bytes): + movl %eax, -28(%edx) +L(write_24bytes): + movl %eax, -24(%edx) +L(write_20bytes): + movl %eax, -20(%edx) +L(write_16bytes): + movl %eax, -16(%edx) +L(write_12bytes): + movl %eax, -12(%edx) +L(write_8bytes): + movl %eax, -8(%edx) +L(write_4bytes): + movl %eax, -4(%edx) +L(write_0bytes): + SETRTNVAL + RETURN + + ALIGN(4) +L(write_29bytes): + movl %eax, -29(%edx) +L(write_25bytes): + movl %eax, -25(%edx) +L(write_21bytes): + movl %eax, -21(%edx) +L(write_17bytes): + movl %eax, -17(%edx) +L(write_13bytes): + movl %eax, -13(%edx) +L(write_9bytes): + movl %eax, -9(%edx) +L(write_5bytes): + movl %eax, -5(%edx) +L(write_1bytes): + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(write_30bytes): + movl %eax, -30(%edx) +L(write_26bytes): + movl %eax, -26(%edx) +L(write_22bytes): + movl %eax, -22(%edx) +L(write_18bytes): + movl %eax, -18(%edx) +L(write_14bytes): + movl %eax, -14(%edx) +L(write_10bytes): + movl %eax, -10(%edx) +L(write_6bytes): + movl %eax, -6(%edx) +L(write_2bytes): + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(write_31bytes): + movl %eax, -31(%edx) +L(write_27bytes): + movl %eax, -27(%edx) +L(write_23bytes): + movl %eax, -23(%edx) +L(write_19bytes): + movl %eax, -19(%edx) +L(write_15bytes): + movl %eax, -15(%edx) +L(write_11bytes): + movl %eax, -11(%edx) +L(write_7bytes): + movl %eax, -7(%edx) +L(write_3bytes): + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +/* ECX > 32 and EDX is 4 byte aligned. */ +L(32bytesormore): + /* Fill xmm0 with the pattern. */ + movd %eax, %xmm0 + pshufd $0, %xmm0, %xmm0 + testl $0xf, %edx + jz L(aligned_16) +/* ECX > 32 and EDX is not 16 byte aligned. */ +L(not_aligned_16): + movdqu %xmm0, (%edx) + movl %edx, %eax + and $-16, %edx + add $16, %edx + sub %edx, %eax + add %eax, %ecx + movd %xmm0, %eax + + ALIGN(4) +L(aligned_16): + cmp $128, %ecx + jae L(128bytesormore) + +L(aligned_16_less128bytes): + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + ALIGN(4) +L(128bytesormore): + PUSH(%ebx) + mov $SHARED_CACHE_SIZE, %ebx + cmp %ebx, %ecx + jae L(128bytesormore_nt_start) + + + POP(%ebx) +# define RESTORE_EBX_STATE CFI_PUSH(%ebx) + cmp $DATA_CACHE_SIZE, %ecx + + jae L(128bytes_L2_normal) + subl $128, %ecx +L(128bytesormore_normal): + sub $128, %ecx + movdqa %xmm0, (%edx) + movdqa %xmm0, 0x10(%edx) + movdqa %xmm0, 0x20(%edx) + movdqa %xmm0, 0x30(%edx) + movdqa %xmm0, 0x40(%edx) + movdqa %xmm0, 0x50(%edx) + movdqa %xmm0, 0x60(%edx) + movdqa %xmm0, 0x70(%edx) + lea 128(%edx), %edx + jb L(128bytesless_normal) + + + sub $128, %ecx + movdqa %xmm0, (%edx) + movdqa %xmm0, 0x10(%edx) + movdqa %xmm0, 0x20(%edx) + movdqa %xmm0, 0x30(%edx) + movdqa %xmm0, 0x40(%edx) + movdqa %xmm0, 0x50(%edx) + movdqa %xmm0, 0x60(%edx) + movdqa %xmm0, 0x70(%edx) + lea 128(%edx), %edx + jae L(128bytesormore_normal) + +L(128bytesless_normal): + add $128, %ecx + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + ALIGN(4) +L(128bytes_L2_normal): + prefetcht0 0x380(%edx) + prefetcht0 0x3c0(%edx) + sub $128, %ecx + movdqa %xmm0, (%edx) + movaps %xmm0, 0x10(%edx) + movaps %xmm0, 0x20(%edx) + movaps %xmm0, 0x30(%edx) + movaps %xmm0, 0x40(%edx) + movaps %xmm0, 0x50(%edx) + movaps %xmm0, 0x60(%edx) + movaps %xmm0, 0x70(%edx) + add $128, %edx + cmp $128, %ecx + jae L(128bytes_L2_normal) + +L(128bytesless_L2_normal): + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + RESTORE_EBX_STATE +L(128bytesormore_nt_start): + sub %ebx, %ecx + mov %ebx, %eax + and $0x7f, %eax + add %eax, %ecx + movd %xmm0, %eax + ALIGN(4) +L(128bytesormore_shared_cache_loop): + prefetcht0 0x3c0(%edx) + prefetcht0 0x380(%edx) + sub $0x80, %ebx + movdqa %xmm0, (%edx) + movdqa %xmm0, 0x10(%edx) + movdqa %xmm0, 0x20(%edx) + movdqa %xmm0, 0x30(%edx) + movdqa %xmm0, 0x40(%edx) + movdqa %xmm0, 0x50(%edx) + movdqa %xmm0, 0x60(%edx) + movdqa %xmm0, 0x70(%edx) + add $0x80, %edx + cmp $0x80, %ebx + jae L(128bytesormore_shared_cache_loop) + cmp $0x80, %ecx + jb L(shared_cache_loop_end) + ALIGN(4) +L(128bytesormore_nt): + sub $0x80, %ecx + movntdq %xmm0, (%edx) + movntdq %xmm0, 0x10(%edx) + movntdq %xmm0, 0x20(%edx) + movntdq %xmm0, 0x30(%edx) + movntdq %xmm0, 0x40(%edx) + movntdq %xmm0, 0x50(%edx) + movntdq %xmm0, 0x60(%edx) + movntdq %xmm0, 0x70(%edx) + add $0x80, %edx + cmp $0x80, %ecx + jae L(128bytesormore_nt) + sfence +L(shared_cache_loop_end): + POP(%ebx) + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + + .pushsection .rodata.sse2,"a",@progbits + ALIGN(2) +L(table_16_128bytes): + .int JMPTBL(L(aligned_16_0bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_1bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_2bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_3bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_4bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_5bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_6bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_7bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_8bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_9bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_10bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_11bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_12bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_13bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_14bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_15bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_16bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_17bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_18bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_19bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_20bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_21bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_22bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_23bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_24bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_25bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_26bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_27bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_28bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_29bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_30bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_31bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_32bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_33bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_34bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_35bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_36bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_37bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_38bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_39bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_40bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_41bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_42bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_43bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_44bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_45bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_46bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_47bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_48bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_49bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_50bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_51bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_52bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_53bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_54bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_55bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_56bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_57bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_58bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_59bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_60bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_61bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_62bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_63bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_64bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_65bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_66bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_67bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_68bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_69bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_70bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_71bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_72bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_73bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_74bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_75bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_76bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_77bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_78bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_79bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_80bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_81bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_82bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_83bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_84bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_85bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_86bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_87bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_88bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_89bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_90bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_91bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_92bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_93bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_94bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_95bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_96bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_97bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_98bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_99bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_100bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_101bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_102bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_103bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_104bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_105bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_106bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_107bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_108bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_109bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_110bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_111bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_112bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_113bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_114bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_115bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_116bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_117bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_118bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_119bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_120bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_121bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_122bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_123bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_124bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_125bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_126bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_127bytes), L(table_16_128bytes)) + .popsection + + ALIGN(4) +L(aligned_16_112bytes): + movdqa %xmm0, -112(%edx) +L(aligned_16_96bytes): + movdqa %xmm0, -96(%edx) +L(aligned_16_80bytes): + movdqa %xmm0, -80(%edx) +L(aligned_16_64bytes): + movdqa %xmm0, -64(%edx) +L(aligned_16_48bytes): + movdqa %xmm0, -48(%edx) +L(aligned_16_32bytes): + movdqa %xmm0, -32(%edx) +L(aligned_16_16bytes): + movdqa %xmm0, -16(%edx) +L(aligned_16_0bytes): + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_113bytes): + movdqa %xmm0, -113(%edx) +L(aligned_16_97bytes): + movdqa %xmm0, -97(%edx) +L(aligned_16_81bytes): + movdqa %xmm0, -81(%edx) +L(aligned_16_65bytes): + movdqa %xmm0, -65(%edx) +L(aligned_16_49bytes): + movdqa %xmm0, -49(%edx) +L(aligned_16_33bytes): + movdqa %xmm0, -33(%edx) +L(aligned_16_17bytes): + movdqa %xmm0, -17(%edx) +L(aligned_16_1bytes): + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_114bytes): + movdqa %xmm0, -114(%edx) +L(aligned_16_98bytes): + movdqa %xmm0, -98(%edx) +L(aligned_16_82bytes): + movdqa %xmm0, -82(%edx) +L(aligned_16_66bytes): + movdqa %xmm0, -66(%edx) +L(aligned_16_50bytes): + movdqa %xmm0, -50(%edx) +L(aligned_16_34bytes): + movdqa %xmm0, -34(%edx) +L(aligned_16_18bytes): + movdqa %xmm0, -18(%edx) +L(aligned_16_2bytes): + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_115bytes): + movdqa %xmm0, -115(%edx) +L(aligned_16_99bytes): + movdqa %xmm0, -99(%edx) +L(aligned_16_83bytes): + movdqa %xmm0, -83(%edx) +L(aligned_16_67bytes): + movdqa %xmm0, -67(%edx) +L(aligned_16_51bytes): + movdqa %xmm0, -51(%edx) +L(aligned_16_35bytes): + movdqa %xmm0, -35(%edx) +L(aligned_16_19bytes): + movdqa %xmm0, -19(%edx) +L(aligned_16_3bytes): + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_116bytes): + movdqa %xmm0, -116(%edx) +L(aligned_16_100bytes): + movdqa %xmm0, -100(%edx) +L(aligned_16_84bytes): + movdqa %xmm0, -84(%edx) +L(aligned_16_68bytes): + movdqa %xmm0, -68(%edx) +L(aligned_16_52bytes): + movdqa %xmm0, -52(%edx) +L(aligned_16_36bytes): + movdqa %xmm0, -36(%edx) +L(aligned_16_20bytes): + movdqa %xmm0, -20(%edx) +L(aligned_16_4bytes): + movl %eax, -4(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_117bytes): + movdqa %xmm0, -117(%edx) +L(aligned_16_101bytes): + movdqa %xmm0, -101(%edx) +L(aligned_16_85bytes): + movdqa %xmm0, -85(%edx) +L(aligned_16_69bytes): + movdqa %xmm0, -69(%edx) +L(aligned_16_53bytes): + movdqa %xmm0, -53(%edx) +L(aligned_16_37bytes): + movdqa %xmm0, -37(%edx) +L(aligned_16_21bytes): + movdqa %xmm0, -21(%edx) +L(aligned_16_5bytes): + movl %eax, -5(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_118bytes): + movdqa %xmm0, -118(%edx) +L(aligned_16_102bytes): + movdqa %xmm0, -102(%edx) +L(aligned_16_86bytes): + movdqa %xmm0, -86(%edx) +L(aligned_16_70bytes): + movdqa %xmm0, -70(%edx) +L(aligned_16_54bytes): + movdqa %xmm0, -54(%edx) +L(aligned_16_38bytes): + movdqa %xmm0, -38(%edx) +L(aligned_16_22bytes): + movdqa %xmm0, -22(%edx) +L(aligned_16_6bytes): + movl %eax, -6(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_119bytes): + movdqa %xmm0, -119(%edx) +L(aligned_16_103bytes): + movdqa %xmm0, -103(%edx) +L(aligned_16_87bytes): + movdqa %xmm0, -87(%edx) +L(aligned_16_71bytes): + movdqa %xmm0, -71(%edx) +L(aligned_16_55bytes): + movdqa %xmm0, -55(%edx) +L(aligned_16_39bytes): + movdqa %xmm0, -39(%edx) +L(aligned_16_23bytes): + movdqa %xmm0, -23(%edx) +L(aligned_16_7bytes): + movl %eax, -7(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_120bytes): + movdqa %xmm0, -120(%edx) +L(aligned_16_104bytes): + movdqa %xmm0, -104(%edx) +L(aligned_16_88bytes): + movdqa %xmm0, -88(%edx) +L(aligned_16_72bytes): + movdqa %xmm0, -72(%edx) +L(aligned_16_56bytes): + movdqa %xmm0, -56(%edx) +L(aligned_16_40bytes): + movdqa %xmm0, -40(%edx) +L(aligned_16_24bytes): + movdqa %xmm0, -24(%edx) +L(aligned_16_8bytes): + movq %xmm0, -8(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_121bytes): + movdqa %xmm0, -121(%edx) +L(aligned_16_105bytes): + movdqa %xmm0, -105(%edx) +L(aligned_16_89bytes): + movdqa %xmm0, -89(%edx) +L(aligned_16_73bytes): + movdqa %xmm0, -73(%edx) +L(aligned_16_57bytes): + movdqa %xmm0, -57(%edx) +L(aligned_16_41bytes): + movdqa %xmm0, -41(%edx) +L(aligned_16_25bytes): + movdqa %xmm0, -25(%edx) +L(aligned_16_9bytes): + movq %xmm0, -9(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_122bytes): + movdqa %xmm0, -122(%edx) +L(aligned_16_106bytes): + movdqa %xmm0, -106(%edx) +L(aligned_16_90bytes): + movdqa %xmm0, -90(%edx) +L(aligned_16_74bytes): + movdqa %xmm0, -74(%edx) +L(aligned_16_58bytes): + movdqa %xmm0, -58(%edx) +L(aligned_16_42bytes): + movdqa %xmm0, -42(%edx) +L(aligned_16_26bytes): + movdqa %xmm0, -26(%edx) +L(aligned_16_10bytes): + movq %xmm0, -10(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_123bytes): + movdqa %xmm0, -123(%edx) +L(aligned_16_107bytes): + movdqa %xmm0, -107(%edx) +L(aligned_16_91bytes): + movdqa %xmm0, -91(%edx) +L(aligned_16_75bytes): + movdqa %xmm0, -75(%edx) +L(aligned_16_59bytes): + movdqa %xmm0, -59(%edx) +L(aligned_16_43bytes): + movdqa %xmm0, -43(%edx) +L(aligned_16_27bytes): + movdqa %xmm0, -27(%edx) +L(aligned_16_11bytes): + movq %xmm0, -11(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_124bytes): + movdqa %xmm0, -124(%edx) +L(aligned_16_108bytes): + movdqa %xmm0, -108(%edx) +L(aligned_16_92bytes): + movdqa %xmm0, -92(%edx) +L(aligned_16_76bytes): + movdqa %xmm0, -76(%edx) +L(aligned_16_60bytes): + movdqa %xmm0, -60(%edx) +L(aligned_16_44bytes): + movdqa %xmm0, -44(%edx) +L(aligned_16_28bytes): + movdqa %xmm0, -28(%edx) +L(aligned_16_12bytes): + movq %xmm0, -12(%edx) + movl %eax, -4(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_125bytes): + movdqa %xmm0, -125(%edx) +L(aligned_16_109bytes): + movdqa %xmm0, -109(%edx) +L(aligned_16_93bytes): + movdqa %xmm0, -93(%edx) +L(aligned_16_77bytes): + movdqa %xmm0, -77(%edx) +L(aligned_16_61bytes): + movdqa %xmm0, -61(%edx) +L(aligned_16_45bytes): + movdqa %xmm0, -45(%edx) +L(aligned_16_29bytes): + movdqa %xmm0, -29(%edx) +L(aligned_16_13bytes): + movq %xmm0, -13(%edx) + movl %eax, -5(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_126bytes): + movdqa %xmm0, -126(%edx) +L(aligned_16_110bytes): + movdqa %xmm0, -110(%edx) +L(aligned_16_94bytes): + movdqa %xmm0, -94(%edx) +L(aligned_16_78bytes): + movdqa %xmm0, -78(%edx) +L(aligned_16_62bytes): + movdqa %xmm0, -62(%edx) +L(aligned_16_46bytes): + movdqa %xmm0, -46(%edx) +L(aligned_16_30bytes): + movdqa %xmm0, -30(%edx) +L(aligned_16_14bytes): + movq %xmm0, -14(%edx) + movl %eax, -6(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_127bytes): + movdqa %xmm0, -127(%edx) +L(aligned_16_111bytes): + movdqa %xmm0, -111(%edx) +L(aligned_16_95bytes): + movdqa %xmm0, -95(%edx) +L(aligned_16_79bytes): + movdqa %xmm0, -79(%edx) +L(aligned_16_63bytes): + movdqa %xmm0, -63(%edx) +L(aligned_16_47bytes): + movdqa %xmm0, -47(%edx) +L(aligned_16_31bytes): + movdqa %xmm0, -31(%edx) +L(aligned_16_15bytes): + movq %xmm0, -15(%edx) + movl %eax, -7(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN_END + +END(memset)
diff --git a/libc/arch-x86/atom/string/sse2-strchr-atom.S b/libc/arch-x86/atom/string/sse2-strchr-atom.S new file mode 100644 index 0000000..e325181 --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-strchr-atom.S
@@ -0,0 +1,391 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 8 +#define ENTRANCE PUSH(%edi) +#define RETURN POP (%edi); ret; CFI_PUSH (%edi); + + +#define STR1 PARMS +#define STR2 STR1+4 + + .text +ENTRY (strchr) + + ENTRANCE + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + + pxor %xmm2, %xmm2 + mov %ecx, %edi + punpcklbw %xmm1, %xmm1 + punpcklbw %xmm1, %xmm1 + /* ECX has OFFSET. */ + and $15, %ecx + pshufd $0, %xmm1, %xmm1 + je L(loop) + +/* Handle unaligned string. */ + and $-16, %edi + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + /* Find where NULL is. */ + pmovmskb %xmm2, %edx + /* Check if there is a match. */ + pmovmskb %xmm0, %eax + /* Remove the leading bytes. */ + sarl %cl, %edx + sarl %cl, %eax + test %eax, %eax + jz L(unaligned_no_match) + add %ecx, %edi + test %edx, %edx + jz L(match_case1) + jmp L(match_case2) + + .p2align 4 +L(unaligned_no_match): + test %edx, %edx + jne L(return_null) + + pxor %xmm2, %xmm2 + add $16, %edi + + .p2align 4 +/* Loop start on aligned string. */ +L(loop): + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + test %edx, %edx + jnz L(return_null) + add $16, %edi + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + test %edx, %edx + jnz L(return_null) + add $16, %edi + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + test %edx, %edx + jnz L(return_null) + add $16, %edi + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + test %edx, %edx + jnz L(return_null) + add $16, %edi + jmp L(loop) + +L(matches): + /* There is a match. First find where NULL is. */ + test %edx, %edx + jz L(match_case1) + + .p2align 4 +L(match_case2): + test %al, %al + jz L(match_higth_case2) + + mov %al, %cl + and $15, %cl + jnz L(match_case2_4) + + mov %dl, %ch + and $15, %ch + jnz L(return_null) + + test $0x10, %al + jnz L(Exit5) + test $0x10, %dl + jnz L(return_null) + test $0x20, %al + jnz L(Exit6) + test $0x20, %dl + jnz L(return_null) + test $0x40, %al + jnz L(Exit7) + test $0x40, %dl + jnz L(return_null) + lea 7(%edi), %eax + RETURN + + .p2align 4 +L(match_case2_4): + test $0x01, %al + jnz L(Exit1) + test $0x01, %dl + jnz L(return_null) + test $0x02, %al + jnz L(Exit2) + test $0x02, %dl + jnz L(return_null) + test $0x04, %al + jnz L(Exit3) + test $0x04, %dl + jnz L(return_null) + lea 3(%edi), %eax + RETURN + + .p2align 4 +L(match_higth_case2): + test %dl, %dl + jnz L(return_null) + + mov %ah, %cl + and $15, %cl + jnz L(match_case2_12) + + mov %dh, %ch + and $15, %ch + jnz L(return_null) + + test $0x10, %ah + jnz L(Exit13) + test $0x10, %dh + jnz L(return_null) + test $0x20, %ah + jnz L(Exit14) + test $0x20, %dh + jnz L(return_null) + test $0x40, %ah + jnz L(Exit15) + test $0x40, %dh + jnz L(return_null) + lea 15(%edi), %eax + RETURN + + .p2align 4 +L(match_case2_12): + test $0x01, %ah + jnz L(Exit9) + test $0x01, %dh + jnz L(return_null) + test $0x02, %ah + jnz L(Exit10) + test $0x02, %dh + jnz L(return_null) + test $0x04, %ah + jnz L(Exit11) + test $0x04, %dh + jnz L(return_null) + lea 11(%edi), %eax + RETURN + + .p2align 4 +L(match_case1): + test %al, %al + jz L(match_higth_case1) + + test $0x01, %al + jnz L(Exit1) + test $0x02, %al + jnz L(Exit2) + test $0x04, %al + jnz L(Exit3) + test $0x08, %al + jnz L(Exit4) + test $0x10, %al + jnz L(Exit5) + test $0x20, %al + jnz L(Exit6) + test $0x40, %al + jnz L(Exit7) + lea 7(%edi), %eax + RETURN + + .p2align 4 +L(match_higth_case1): + test $0x01, %ah + jnz L(Exit9) + test $0x02, %ah + jnz L(Exit10) + test $0x04, %ah + jnz L(Exit11) + test $0x08, %ah + jnz L(Exit12) + test $0x10, %ah + jnz L(Exit13) + test $0x20, %ah + jnz L(Exit14) + test $0x40, %ah + jnz L(Exit15) + lea 15(%edi), %eax + RETURN + + .p2align 4 +L(Exit1): + lea (%edi), %eax + RETURN + + .p2align 4 +L(Exit2): + lea 1(%edi), %eax + RETURN + + .p2align 4 +L(Exit3): + lea 2(%edi), %eax + RETURN + + .p2align 4 +L(Exit4): + lea 3(%edi), %eax + RETURN + + .p2align 4 +L(Exit5): + lea 4(%edi), %eax + RETURN + + .p2align 4 +L(Exit6): + lea 5(%edi), %eax + RETURN + + .p2align 4 +L(Exit7): + lea 6(%edi), %eax + RETURN + + .p2align 4 +L(Exit9): + lea 8(%edi), %eax + RETURN + + .p2align 4 +L(Exit10): + lea 9(%edi), %eax + RETURN + + .p2align 4 +L(Exit11): + lea 10(%edi), %eax + RETURN + + .p2align 4 +L(Exit12): + lea 11(%edi), %eax + RETURN + + .p2align 4 +L(Exit13): + lea 12(%edi), %eax + RETURN + + .p2align 4 +L(Exit14): + lea 13(%edi), %eax + RETURN + + .p2align 4 +L(Exit15): + lea 14(%edi), %eax + RETURN + + .p2align 4 +L(return_null): + xor %eax, %eax + RETURN + +END (strchr)
diff --git a/libc/arch-x86/atom/string/sse2-strlen-atom.S b/libc/arch-x86/atom/string/sse2-strlen-atom.S new file mode 100644 index 0000000..81768fb --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-strlen-atom.S
@@ -0,0 +1,749 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef USE_AS_STRCAT + +# ifndef STRLEN +# define STRLEN strlen +# endif + +# ifndef L +# define L(label) .L##label +# endif + +# ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +# endif + +# ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +# endif + +/* calee safe register only for strnlen is required */ + +# ifdef USE_AS_STRNLEN +# ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +# endif + +# ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +# endif + +# ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +# endif +# endif + +# ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +# endif + +# ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +# endif + +# define PARMS 4 +# define STR PARMS +# define RETURN ret + +# ifdef USE_AS_STRNLEN +# define LEN PARMS + 8 +# define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +# define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +# define PUSH(REG) pushl REG; CFI_PUSH (REG) +# define POP(REG) popl REG; CFI_POP (REG) +# undef RETURN +# define RETURN POP (%edi); ret; CFI_PUSH(%edi); +# endif + + .text +ENTRY (STRLEN) + mov STR(%esp), %edx +# ifdef USE_AS_STRNLEN + PUSH (%edi) + movl LEN(%esp), %edi + sub $4, %edi + jbe L(len_less4_prolog) +# endif +#endif + xor %eax, %eax + cmpb $0, (%edx) + jz L(exit_tail0) + cmpb $0, 1(%edx) + jz L(exit_tail1) + cmpb $0, 2(%edx) + jz L(exit_tail2) + cmpb $0, 3(%edx) + jz L(exit_tail3) + +#ifdef USE_AS_STRNLEN + sub $4, %edi + jbe L(len_less8_prolog) +#endif + + cmpb $0, 4(%edx) + jz L(exit_tail4) + cmpb $0, 5(%edx) + jz L(exit_tail5) + cmpb $0, 6(%edx) + jz L(exit_tail6) + cmpb $0, 7(%edx) + jz L(exit_tail7) + +#ifdef USE_AS_STRNLEN + sub $4, %edi + jbe L(len_less12_prolog) +#endif + + cmpb $0, 8(%edx) + jz L(exit_tail8) + cmpb $0, 9(%edx) + jz L(exit_tail9) + cmpb $0, 10(%edx) + jz L(exit_tail10) + cmpb $0, 11(%edx) + jz L(exit_tail11) + +#ifdef USE_AS_STRNLEN + sub $4, %edi + jbe L(len_less16_prolog) +#endif + + cmpb $0, 12(%edx) + jz L(exit_tail12) + cmpb $0, 13(%edx) + jz L(exit_tail13) + cmpb $0, 14(%edx) + jz L(exit_tail14) + cmpb $0, 15(%edx) + jz L(exit_tail15) + + pxor %xmm0, %xmm0 + lea 16(%edx), %eax + mov %eax, %ecx + and $-16, %eax + +#ifdef USE_AS_STRNLEN + and $15, %edx + add %edx, %edi + sub $64, %edi + jbe L(len_less64) +#endif + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + pxor %xmm1, %xmm1 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + pxor %xmm2, %xmm2 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + pxor %xmm3, %xmm3 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + +#ifdef USE_AS_STRNLEN + sub $64, %edi + jbe L(len_less64) +#endif + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + +#ifdef USE_AS_STRNLEN + sub $64, %edi + jbe L(len_less64) +#endif + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + +#ifdef USE_AS_STRNLEN + sub $64, %edi + jbe L(len_less64) +#endif + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + +#ifdef USE_AS_STRNLEN + mov %eax, %edx + and $63, %edx + add %edx, %edi +#endif + + and $-0x40, %eax + + .p2align 4 +L(aligned_64_loop): +#ifdef USE_AS_STRNLEN + sub $64, %edi + jbe L(len_less64) +#endif + movaps (%eax), %xmm0 + movaps 16(%eax), %xmm1 + movaps 32(%eax), %xmm2 + movaps 48(%eax), %xmm6 + pminub %xmm1, %xmm0 + pminub %xmm6, %xmm2 + pminub %xmm0, %xmm2 + pcmpeqb %xmm3, %xmm2 + pmovmskb %xmm2, %edx + lea 64(%eax), %eax + test %edx, %edx + jz L(aligned_64_loop) + + pcmpeqb -64(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 48(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb -32(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm6, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx +L(exit): + sub %ecx, %eax + test %dl, %dl + jz L(exit_high) + + mov %dl, %cl + and $15, %cl + jz L(exit_8) + test $0x01, %dl + jnz L(exit_tail0) + test $0x02, %dl + jnz L(exit_tail1) + test $0x04, %dl + jnz L(exit_tail2) + add $3, %eax + RETURN + + .p2align 4 +L(exit_8): + test $0x10, %dl + jnz L(exit_tail4) + test $0x20, %dl + jnz L(exit_tail5) + test $0x40, %dl + jnz L(exit_tail6) + add $7, %eax + RETURN + + .p2align 4 +L(exit_high): + mov %dh, %ch + and $15, %ch + jz L(exit_high_8) + test $0x01, %dh + jnz L(exit_tail8) + test $0x02, %dh + jnz L(exit_tail9) + test $0x04, %dh + jnz L(exit_tail10) + add $11, %eax + RETURN + + .p2align 4 +L(exit_high_8): + test $0x10, %dh + jnz L(exit_tail12) + test $0x20, %dh + jnz L(exit_tail13) + test $0x40, %dh + jnz L(exit_tail14) + add $15, %eax +L(exit_tail0): + RETURN + +#ifdef USE_AS_STRNLEN + + .p2align 4 +L(len_less64): + pxor %xmm0, %xmm0 + add $64, %edi + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + pxor %xmm1, %xmm1 + lea 16(%eax), %eax + test %edx, %edx + jnz L(strnlen_exit) + + sub $16, %edi + jbe L(return_start_len) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(strnlen_exit) + + sub $16, %edi + jbe L(return_start_len) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(strnlen_exit) + + sub $16, %edi + jbe L(return_start_len) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(strnlen_exit) + +#ifndef USE_AS_STRLCAT + movl LEN(%esp), %eax + RETURN +#else + jmp L(return_start_len) +#endif + + .p2align 4 +L(strnlen_exit): + sub %ecx, %eax + + test %dl, %dl + jz L(strnlen_exit_high) + mov %dl, %cl + and $15, %cl + jz L(strnlen_exit_8) + test $0x01, %dl + jnz L(exit_tail0) + test $0x02, %dl + jnz L(strnlen_exit_tail1) + test $0x04, %dl + jnz L(strnlen_exit_tail2) + sub $4, %edi + jb L(return_start_len) + lea 3(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_8): + test $0x10, %dl + jnz L(strnlen_exit_tail4) + test $0x20, %dl + jnz L(strnlen_exit_tail5) + test $0x40, %dl + jnz L(strnlen_exit_tail6) + sub $8, %edi + jb L(return_start_len) + lea 7(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_high): + mov %dh, %ch + and $15, %ch + jz L(strnlen_exit_high_8) + test $0x01, %dh + jnz L(strnlen_exit_tail8) + test $0x02, %dh + jnz L(strnlen_exit_tail9) + test $0x04, %dh + jnz L(strnlen_exit_tail10) + sub $12, %edi + jb L(return_start_len) + lea 11(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_high_8): + test $0x10, %dh + jnz L(strnlen_exit_tail12) + test $0x20, %dh + jnz L(strnlen_exit_tail13) + test $0x40, %dh + jnz L(strnlen_exit_tail14) + sub $16, %edi + jb L(return_start_len) + lea 15(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail1): + sub $2, %edi + jb L(return_start_len) + lea 1(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail2): + sub $3, %edi + jb L(return_start_len) + lea 2(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail4): + sub $5, %edi + jb L(return_start_len) + lea 4(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail5): + sub $6, %edi + jb L(return_start_len) + lea 5(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail6): + sub $7, %edi + jb L(return_start_len) + lea 6(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail8): + sub $9, %edi + jb L(return_start_len) + lea 8(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail9): + sub $10, %edi + jb L(return_start_len) + lea 9(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail10): + sub $11, %edi + jb L(return_start_len) + lea 10(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail12): + sub $13, %edi + jb L(return_start_len) + lea 12(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail13): + sub $14, %edi + jb L(return_start_len) + lea 13(%eax), %eax + RETURN + + .p2align 4 +L(strnlen_exit_tail14): + sub $15, %edi + jb L(return_start_len) + lea 14(%eax), %eax + RETURN + +#ifndef USE_AS_STRLCAT + .p2align 4 +L(return_start_len): + movl LEN(%esp), %eax + RETURN +#endif + +/* for prolog only */ + + .p2align 4 +L(len_less4_prolog): + xor %eax, %eax + + add $4, %edi + jz L(exit_tail0) + + cmpb $0, (%edx) + jz L(exit_tail0) + cmp $1, %edi + je L(exit_tail1) + + cmpb $0, 1(%edx) + jz L(exit_tail1) + cmp $2, %edi + je L(exit_tail2) + + cmpb $0, 2(%edx) + jz L(exit_tail2) + cmp $3, %edi + je L(exit_tail3) + + cmpb $0, 3(%edx) + jz L(exit_tail3) + mov %edi, %eax + RETURN + + .p2align 4 +L(len_less8_prolog): + add $4, %edi + + cmpb $0, 4(%edx) + jz L(exit_tail4) + cmp $1, %edi + je L(exit_tail5) + + cmpb $0, 5(%edx) + jz L(exit_tail5) + cmp $2, %edi + je L(exit_tail6) + + cmpb $0, 6(%edx) + jz L(exit_tail6) + cmp $3, %edi + je L(exit_tail7) + + cmpb $0, 7(%edx) + jz L(exit_tail7) + mov $8, %eax + RETURN + + + .p2align 4 +L(len_less12_prolog): + add $4, %edi + + cmpb $0, 8(%edx) + jz L(exit_tail8) + cmp $1, %edi + je L(exit_tail9) + + cmpb $0, 9(%edx) + jz L(exit_tail9) + cmp $2, %edi + je L(exit_tail10) + + cmpb $0, 10(%edx) + jz L(exit_tail10) + cmp $3, %edi + je L(exit_tail11) + + cmpb $0, 11(%edx) + jz L(exit_tail11) + mov $12, %eax + RETURN + + .p2align 4 +L(len_less16_prolog): + add $4, %edi + + cmpb $0, 12(%edx) + jz L(exit_tail12) + cmp $1, %edi + je L(exit_tail13) + + cmpb $0, 13(%edx) + jz L(exit_tail13) + cmp $2, %edi + je L(exit_tail14) + + cmpb $0, 14(%edx) + jz L(exit_tail14) + cmp $3, %edi + je L(exit_tail15) + + cmpb $0, 15(%edx) + jz L(exit_tail15) + mov $16, %eax + RETURN +#endif + + .p2align 4 +L(exit_tail1): + add $1, %eax + RETURN + +L(exit_tail2): + add $2, %eax + RETURN + +L(exit_tail3): + add $3, %eax + RETURN + +L(exit_tail4): + add $4, %eax + RETURN + +L(exit_tail5): + add $5, %eax + RETURN + +L(exit_tail6): + add $6, %eax + RETURN + +L(exit_tail7): + add $7, %eax + RETURN + +L(exit_tail8): + add $8, %eax + RETURN + +L(exit_tail9): + add $9, %eax + RETURN + +L(exit_tail10): + add $10, %eax + RETURN + +L(exit_tail11): + add $11, %eax + RETURN + +L(exit_tail12): + add $12, %eax + RETURN + +L(exit_tail13): + add $13, %eax + RETURN + +L(exit_tail14): + add $14, %eax + RETURN + +L(exit_tail15): + add $15, %eax +#ifndef USE_AS_STRCAT + RETURN +END (STRLEN) +#endif
diff --git a/libc/arch-x86/atom/string/sse2-strnlen-atom.S b/libc/arch-x86/atom/string/sse2-strnlen-atom.S new file mode 100644 index 0000000..1f89b4e --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-strnlen-atom.S
@@ -0,0 +1,33 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STRNLEN 1 +#define STRLEN strnlen +#include "sse2-strlen-atom.S"
diff --git a/libc/arch-x86/atom/string/sse2-strrchr-atom.S b/libc/arch-x86/atom/string/sse2-strrchr-atom.S new file mode 100644 index 0000000..e916bc1 --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-strrchr-atom.S
@@ -0,0 +1,753 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 8 +#define ENTRANCE PUSH(%edi); +#define RETURN POP (%edi); ret; CFI_PUSH (%edi); + +#define STR1 PARMS +#define STR2 STR1+4 + + .text +ENTRY (strrchr) + + ENTRANCE + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + + pxor %xmm2, %xmm2 + mov %ecx, %edi + punpcklbw %xmm1, %xmm1 + punpcklbw %xmm1, %xmm1 + /* ECX has OFFSET. */ + and $63, %ecx + pshufd $0, %xmm1, %xmm1 + cmp $48, %ecx + ja L(crosscache) + +/* unaligned string. */ + movdqu (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + pcmpeqb %xmm1, %xmm0 + /* Find where NULL is. */ + pmovmskb %xmm2, %ecx + /* Check if there is a match. */ + pmovmskb %xmm0, %eax + add $16, %edi + + test %eax, %eax + jnz L(unaligned_match1) + + test %ecx, %ecx + jnz L(return_null) + + and $-16, %edi + + PUSH (%esi) + PUSH (%ebx) + + xor %ebx, %ebx + jmp L(loop) + + CFI_POP (%esi) + CFI_POP (%ebx) + + .p2align 4 +L(unaligned_match1): + test %ecx, %ecx + jnz L(prolog_find_zero_1) + + PUSH (%esi) + PUSH (%ebx) + + mov %eax, %ebx + mov %edi, %esi + and $-16, %edi + jmp L(loop) + + CFI_POP (%esi) + CFI_POP (%ebx) + + .p2align 4 +L(crosscache): +/* Hancle unaligned string. */ + and $15, %ecx + and $-16, %edi + pxor %xmm3, %xmm3 + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm3 + pcmpeqb %xmm1, %xmm0 + /* Find where NULL is. */ + pmovmskb %xmm3, %edx + /* Check if there is a match. */ + pmovmskb %xmm0, %eax + /* Remove the leading bytes. */ + shr %cl, %edx + shr %cl, %eax + add $16, %edi + + test %eax, %eax + jnz L(unaligned_match) + + test %edx, %edx + jnz L(return_null) + + PUSH (%esi) + PUSH (%ebx) + + xor %ebx, %ebx + jmp L(loop) + + CFI_POP (%esi) + CFI_POP (%ebx) + + .p2align 4 +L(unaligned_match): + test %edx, %edx + jnz L(prolog_find_zero) + + PUSH (%esi) + PUSH (%ebx) + + mov %eax, %ebx + lea (%edi, %ecx), %esi + +/* Loop start on aligned string. */ + .p2align 4 +L(loop): + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + add $16, %edi + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %ecx + pmovmskb %xmm0, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + add $16, %edi + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %ecx + pmovmskb %xmm0, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + add $16, %edi + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %ecx + pmovmskb %xmm0, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm0 + pcmpeqb %xmm0, %xmm2 + add $16, %edi + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm2, %ecx + pmovmskb %xmm0, %eax + or %eax, %ecx + jz L(loop) + +L(matches): + test %eax, %eax + jnz L(match) +L(return_value): + test %ebx, %ebx + jz L(return_null_1) + mov %ebx, %eax + mov %esi, %edi + + POP (%ebx) + POP (%esi) + + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(return_null_1): + POP (%ebx) + POP (%esi) + + xor %eax, %eax + RETURN + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(match): + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(find_zero) + mov %eax, %ebx + mov %edi, %esi + jmp L(loop) + + .p2align 4 +L(find_zero): + test %cl, %cl + jz L(find_zero_high) + mov %cl, %dl + and $15, %dl + jz L(find_zero_8) + test $0x01, %cl + jnz L(FindZeroExit1) + test $0x02, %cl + jnz L(FindZeroExit2) + test $0x04, %cl + jnz L(FindZeroExit3) + and $(1 << 4) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_8): + test $0x10, %cl + jnz L(FindZeroExit5) + test $0x20, %cl + jnz L(FindZeroExit6) + test $0x40, %cl + jnz L(FindZeroExit7) + and $(1 << 8) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_high): + mov %ch, %dh + and $15, %dh + jz L(find_zero_high_8) + test $0x01, %ch + jnz L(FindZeroExit9) + test $0x02, %ch + jnz L(FindZeroExit10) + test $0x04, %ch + jnz L(FindZeroExit11) + and $(1 << 12) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_high_8): + test $0x10, %ch + jnz L(FindZeroExit13) + test $0x20, %ch + jnz L(FindZeroExit14) + test $0x40, %ch + jnz L(FindZeroExit15) + and $(1 << 16) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit1): + and $1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit2): + and $(1 << 2) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit3): + and $(1 << 3) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit5): + and $(1 << 5) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit6): + and $(1 << 6) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit7): + and $(1 << 7) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit9): + and $(1 << 9) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit10): + and $(1 << 10) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit11): + and $(1 << 11) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit13): + and $(1 << 13) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit14): + and $(1 << 14) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + jmp L(match_case1) + + CFI_PUSH (%ebx) + CFI_PUSH (%esi) + + .p2align 4 +L(FindZeroExit15): + and $(1 << 15) - 1, %eax + jz L(return_value) + + POP (%ebx) + POP (%esi) + + .p2align 4 +L(match_case1): + test %ah, %ah + jnz L(match_case1_high) + mov %al, %dl + and $15 << 4, %dl + jnz L(match_case1_8) + test $0x08, %al + jnz L(Exit4) + test $0x04, %al + jnz L(Exit3) + test $0x02, %al + jnz L(Exit2) + lea -16(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_8): + test $0x80, %al + jnz L(Exit8) + test $0x40, %al + jnz L(Exit7) + test $0x20, %al + jnz L(Exit6) + lea -12(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_high): + mov %ah, %dh + and $15 << 4, %dh + jnz L(match_case1_high_8) + test $0x08, %ah + jnz L(Exit12) + test $0x04, %ah + jnz L(Exit11) + test $0x02, %ah + jnz L(Exit10) + lea -8(%edi), %eax + RETURN + + .p2align 4 +L(match_case1_high_8): + test $0x80, %ah + jnz L(Exit16) + test $0x40, %ah + jnz L(Exit15) + test $0x20, %ah + jnz L(Exit14) + lea -4(%edi), %eax + RETURN + + .p2align 4 +L(Exit2): + lea -15(%edi), %eax + RETURN + + .p2align 4 +L(Exit3): + lea -14(%edi), %eax + RETURN + + .p2align 4 +L(Exit4): + lea -13(%edi), %eax + RETURN + + .p2align 4 +L(Exit6): + lea -11(%edi), %eax + RETURN + + .p2align 4 +L(Exit7): + lea -10(%edi), %eax + RETURN + + .p2align 4 +L(Exit8): + lea -9(%edi), %eax + RETURN + + .p2align 4 +L(Exit10): + lea -7(%edi), %eax + RETURN + + .p2align 4 +L(Exit11): + lea -6(%edi), %eax + RETURN + + .p2align 4 +L(Exit12): + lea -5(%edi), %eax + RETURN + + .p2align 4 +L(Exit14): + lea -3(%edi), %eax + RETURN + + .p2align 4 +L(Exit15): + lea -2(%edi), %eax + RETURN + + .p2align 4 +L(Exit16): + lea -1(%edi), %eax + RETURN + +/* Return NULL. */ + .p2align 4 +L(return_null): + xor %eax, %eax + RETURN + + .p2align 4 +L(prolog_find_zero): + add %ecx, %edi + mov %edx, %ecx +L(prolog_find_zero_1): + test %cl, %cl + jz L(prolog_find_zero_high) + mov %cl, %dl + and $15, %dl + jz L(prolog_find_zero_8) + test $0x01, %cl + jnz L(PrologFindZeroExit1) + test $0x02, %cl + jnz L(PrologFindZeroExit2) + test $0x04, %cl + jnz L(PrologFindZeroExit3) + and $(1 << 4) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(prolog_find_zero_8): + test $0x10, %cl + jnz L(PrologFindZeroExit5) + test $0x20, %cl + jnz L(PrologFindZeroExit6) + test $0x40, %cl + jnz L(PrologFindZeroExit7) + and $(1 << 8) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(prolog_find_zero_high): + mov %ch, %dh + and $15, %dh + jz L(prolog_find_zero_high_8) + test $0x01, %ch + jnz L(PrologFindZeroExit9) + test $0x02, %ch + jnz L(PrologFindZeroExit10) + test $0x04, %ch + jnz L(PrologFindZeroExit11) + and $(1 << 12) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(prolog_find_zero_high_8): + test $0x10, %ch + jnz L(PrologFindZeroExit13) + test $0x20, %ch + jnz L(PrologFindZeroExit14) + test $0x40, %ch + jnz L(PrologFindZeroExit15) + and $(1 << 16) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit1): + and $1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit2): + and $(1 << 2) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit3): + and $(1 << 3) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit5): + and $(1 << 5) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit6): + and $(1 << 6) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit7): + and $(1 << 7) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit9): + and $(1 << 9) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit10): + and $(1 << 10) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit11): + and $(1 << 11) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit13): + and $(1 << 13) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit14): + and $(1 << 14) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + + .p2align 4 +L(PrologFindZeroExit15): + and $(1 << 15) - 1, %eax + jnz L(match_case1) + xor %eax, %eax + RETURN + +END (strrchr)
diff --git a/libc/arch-x86/atom/string/sse2-wcschr-atom.S b/libc/arch-x86/atom/string/sse2-wcschr-atom.S new file mode 100644 index 0000000..729302b --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-wcschr-atom.S
@@ -0,0 +1,267 @@ +/* +Copyright (c) 2011 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 4 + + +#define STR1 PARMS +#define STR2 STR1+4 + + .text +ENTRY (wcschr) + + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + + mov %ecx, %eax + punpckldq %xmm1, %xmm1 + pxor %xmm2, %xmm2 + punpckldq %xmm1, %xmm1 + + and $63, %eax + cmp $48, %eax + ja L(cross_cache) + + movdqu (%ecx), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + or %eax, %edx + jnz L(matches) + and $-16, %ecx + jmp L(loop) + + .p2align 4 +L(cross_cache): + PUSH (%edi) + mov %ecx, %edi + mov %eax, %ecx + and $-16, %edi + and $15, %ecx + movdqa (%edi), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + + sarl %cl, %edx + sarl %cl, %eax + test %eax, %eax + jz L(unaligned_no_match) + + add %edi, %ecx + POP (%edi) + + test %edx, %edx + jz L(match_case1) + test %al, %al + jz L(match_higth_case2) + test $15, %al + jnz L(match_case2_4) + test $15, %dl + jnz L(return_null) + lea 4(%ecx), %eax + ret + + CFI_PUSH (%edi) + + .p2align 4 +L(unaligned_no_match): + mov %edi, %ecx + POP (%edi) + + test %edx, %edx + jnz L(return_null) + + pxor %xmm2, %xmm2 + +/* Loop start on aligned string. */ + .p2align 4 +L(loop): + add $16, %ecx + movdqa (%ecx), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + or %eax, %edx + jnz L(matches) + add $16, %ecx + + movdqa (%ecx), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + or %eax, %edx + jnz L(matches) + add $16, %ecx + + movdqa (%ecx), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + or %eax, %edx + jnz L(matches) + add $16, %ecx + + movdqa (%ecx), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %edx + pmovmskb %xmm0, %eax + or %eax, %edx + jz L(loop) + + .p2align 4 +L(matches): + pmovmskb %xmm2, %edx + test %eax, %eax + jz L(return_null) + test %edx, %edx + jz L(match_case1) + + .p2align 4 +L(match_case2): + test %al, %al + jz L(match_higth_case2) + test $15, %al + jnz L(match_case2_4) + test $15, %dl + jnz L(return_null) + lea 4(%ecx), %eax + ret + + .p2align 4 +L(match_case2_4): + mov %ecx, %eax + ret + + .p2align 4 +L(match_higth_case2): + test %dl, %dl + jnz L(return_null) + test $15, %ah + jnz L(match_case2_12) + test $15, %dh + jnz L(return_null) + lea 12(%ecx), %eax + ret + + .p2align 4 +L(match_case2_12): + lea 8(%ecx), %eax + ret + + .p2align 4 +L(match_case1): + test %al, %al + jz L(match_higth_case1) + + test $0x01, %al + jnz L(exit0) + lea 4(%ecx), %eax + ret + + .p2align 4 +L(match_higth_case1): + test $0x01, %ah + jnz L(exit3) + lea 12(%ecx), %eax + ret + + .p2align 4 +L(exit0): + mov %ecx, %eax + ret + + .p2align 4 +L(exit3): + lea 8(%ecx), %eax + ret + + .p2align 4 +L(return_null): + xor %eax, %eax + ret + +END (wcschr)
diff --git a/libc/arch-x86/atom/string/sse2-wcscmp-atom.S b/libc/arch-x86/atom/string/sse2-wcscmp-atom.S new file mode 100644 index 0000000..8867d28 --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-wcscmp-atom.S
@@ -0,0 +1,1062 @@ +/* +Copyright (c) 2011 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define ENTRANCE PUSH(%esi); PUSH(%edi) +#define RETURN POP(%edi); POP(%esi); ret; CFI_PUSH(%esi); CFI_PUSH(%edi); +#define PARMS 4 +#define STR1 PARMS +#define STR2 STR1+4 + + .text +ENTRY (wcscmp) +/* + * This implementation uses SSE to compare up to 16 bytes at a time. +*/ + mov STR1(%esp), %edx + mov STR2(%esp), %eax + + mov (%eax), %ecx + cmp %ecx, (%edx) + jne L(neq) + test %ecx, %ecx + jz L(eq) + + mov 4(%eax), %ecx + cmp %ecx, 4(%edx) + jne L(neq) + test %ecx, %ecx + jz L(eq) + + mov 8(%eax), %ecx + cmp %ecx, 8(%edx) + jne L(neq) + test %ecx, %ecx + jz L(eq) + + mov 12(%eax), %ecx + cmp %ecx, 12(%edx) + jne L(neq) + test %ecx, %ecx + jz L(eq) + + ENTRANCE + add $16, %eax + add $16, %edx + + mov %eax, %esi + mov %edx, %edi + pxor %xmm0, %xmm0 /* clear %xmm0 for null char checks */ + mov %al, %ch + mov %dl, %cl + and $63, %eax /* esi alignment in cache line */ + and $63, %edx /* edi alignment in cache line */ + and $15, %cl + jz L(continue_00) + cmp $16, %edx + jb L(continue_0) + cmp $32, %edx + jb L(continue_16) + cmp $48, %edx + jb L(continue_32) + +L(continue_48): + and $15, %ch + jz L(continue_48_00) + cmp $16, %eax + jb L(continue_0_48) + cmp $32, %eax + jb L(continue_16_48) + cmp $48, %eax + jb L(continue_32_48) + + .p2align 4 +L(continue_48_48): + mov (%esi), %ecx + cmp %ecx, (%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + movdqu 16(%edi), %xmm1 + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%edi), %xmm1 + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + movdqu 48(%edi), %xmm1 + movdqu 48(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_48_48) + +L(continue_0): + and $15, %ch + jz L(continue_0_00) + cmp $16, %eax + jb L(continue_0_0) + cmp $32, %eax + jb L(continue_0_16) + cmp $48, %eax + jb L(continue_0_32) + + .p2align 4 +L(continue_0_48): + mov (%esi), %ecx + cmp %ecx, (%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + movdqu 16(%edi), %xmm1 + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%edi), %xmm1 + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + mov 48(%esi), %ecx + cmp %ecx, 48(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 52(%esi), %ecx + cmp %ecx, 52(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 56(%esi), %ecx + cmp %ecx, 56(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 60(%esi), %ecx + cmp %ecx, 60(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + add $64, %esi + add $64, %edi + jmp L(continue_0_48) + + .p2align 4 +L(continue_00): + and $15, %ch + jz L(continue_00_00) + cmp $16, %eax + jb L(continue_00_0) + cmp $32, %eax + jb L(continue_00_16) + cmp $48, %eax + jb L(continue_00_32) + + .p2align 4 +L(continue_00_48): + pcmpeqd (%edi), %xmm0 + mov (%edi), %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(less4_double_words1) + + cmp (%esi), %eax + jne L(nequal) + + mov 4(%edi), %eax + cmp 4(%esi), %eax + jne L(nequal) + + mov 8(%edi), %eax + cmp 8(%esi), %eax + jne L(nequal) + + mov 12(%edi), %eax + cmp 12(%esi), %eax + jne L(nequal) + + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 32(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + movdqu 48(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 48(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_00_48) + + .p2align 4 +L(continue_32): + and $15, %ch + jz L(continue_32_00) + cmp $16, %eax + jb L(continue_0_32) + cmp $32, %eax + jb L(continue_16_32) + cmp $48, %eax + jb L(continue_32_32) + + .p2align 4 +L(continue_32_48): + mov (%esi), %ecx + cmp %ecx, (%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 16(%esi), %ecx + cmp %ecx, 16(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 20(%esi), %ecx + cmp %ecx, 20(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 24(%esi), %ecx + cmp %ecx, 24(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 28(%esi), %ecx + cmp %ecx, 28(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + movdqu 32(%edi), %xmm1 + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + movdqu 48(%edi), %xmm1 + movdqu 48(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_32_48) + + .p2align 4 +L(continue_16): + and $15, %ch + jz L(continue_16_00) + cmp $16, %eax + jb L(continue_0_16) + cmp $32, %eax + jb L(continue_16_16) + cmp $48, %eax + jb L(continue_16_32) + + .p2align 4 +L(continue_16_48): + mov (%esi), %ecx + cmp %ecx, (%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + movdqu 16(%edi), %xmm1 + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + mov 32(%esi), %ecx + cmp %ecx, 32(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 36(%esi), %ecx + cmp %ecx, 36(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 40(%esi), %ecx + cmp %ecx, 40(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 44(%esi), %ecx + cmp %ecx, 44(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + movdqu 48(%edi), %xmm1 + movdqu 48(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_16_48) + + .p2align 4 +L(continue_00_00): + movdqa (%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd (%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqa 16(%edi), %xmm3 + pcmpeqd %xmm3, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%esi), %xmm3 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm3 /* packed sub of comparison results*/ + pmovmskb %xmm3, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqa 32(%edi), %xmm5 + pcmpeqd %xmm5, %xmm0 /* Any null double_word? */ + pcmpeqd 32(%esi), %xmm5 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm5 /* packed sub of comparison results*/ + pmovmskb %xmm5, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + movdqa 48(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 48(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_00_00) + + .p2align 4 +L(continue_00_32): + movdqu (%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd (%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + add $16, %esi + add $16, %edi + jmp L(continue_00_48) + + .p2align 4 +L(continue_00_16): + movdqu (%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd (%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + add $32, %esi + add $32, %edi + jmp L(continue_00_48) + + .p2align 4 +L(continue_00_0): + movdqu (%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd (%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm2, %xmm0 /* Any null double_word? */ + pcmpeqd 32(%edi), %xmm2 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm2 /* packed sub of comparison results*/ + pmovmskb %xmm2, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + add $48, %esi + add $48, %edi + jmp L(continue_00_48) + + .p2align 4 +L(continue_48_00): + pcmpeqd (%esi), %xmm0 + mov (%edi), %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(less4_double_words1) + + cmp (%esi), %eax + jne L(nequal) + + mov 4(%edi), %eax + cmp 4(%esi), %eax + jne L(nequal) + + mov 8(%edi), %eax + cmp 8(%esi), %eax + jne L(nequal) + + mov 12(%edi), %eax + cmp 12(%esi), %eax + jne L(nequal) + + movdqu 16(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 32(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + movdqu 48(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 48(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_48) + + add $64, %esi + add $64, %edi + jmp L(continue_48_00) + + .p2align 4 +L(continue_32_00): + movdqu (%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd (%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + add $16, %esi + add $16, %edi + jmp L(continue_48_00) + + .p2align 4 +L(continue_16_00): + movdqu (%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd (%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + add $32, %esi + add $32, %edi + jmp L(continue_48_00) + + .p2align 4 +L(continue_0_00): + movdqu (%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd (%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 16(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%edi), %xmm1 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd 32(%esi), %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + add $48, %esi + add $48, %edi + jmp L(continue_48_00) + + .p2align 4 +L(continue_32_32): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + add $16, %esi + add $16, %edi + jmp L(continue_48_48) + + .p2align 4 +L(continue_16_16): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%edi), %xmm3 + movdqu 16(%esi), %xmm4 + pcmpeqd %xmm3, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm4, %xmm3 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm3 /* packed sub of comparison results*/ + pmovmskb %xmm3, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + add $32, %esi + add $32, %edi + jmp L(continue_48_48) + + .p2align 4 +L(continue_0_0): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%edi), %xmm3 + movdqu 16(%esi), %xmm4 + pcmpeqd %xmm3, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm4, %xmm3 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm3 /* packed sub of comparison results*/ + pmovmskb %xmm3, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + movdqu 32(%edi), %xmm1 + movdqu 32(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_32) + + add $48, %esi + add $48, %edi + jmp L(continue_48_48) + + .p2align 4 +L(continue_0_16): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + movdqu 16(%edi), %xmm1 + movdqu 16(%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words_16) + + add $32, %esi + add $32, %edi + jmp L(continue_32_48) + + .p2align 4 +L(continue_0_32): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + add $16, %esi + add $16, %edi + jmp L(continue_16_48) + + .p2align 4 +L(continue_16_32): + movdqu (%edi), %xmm1 + movdqu (%esi), %xmm2 + pcmpeqd %xmm1, %xmm0 /* Any null double_word? */ + pcmpeqd %xmm2, %xmm1 /* compare first 4 double_words for equality */ + psubb %xmm0, %xmm1 /* packed sub of comparison results*/ + pmovmskb %xmm1, %edx + sub $0xffff, %edx /* if first 4 double_words are same, edx == 0xffff */ + jnz L(less4_double_words) + + add $16, %esi + add $16, %edi + jmp L(continue_32_48) + + .p2align 4 +L(less4_double_words1): + cmp (%esi), %eax + jne L(nequal) + test %eax, %eax + jz L(equal) + + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + test %ecx, %ecx + jz L(equal) + + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + xor %eax, %eax + RETURN + + .p2align 4 +L(less4_double_words): + xor %eax, %eax + test %dl, %dl + jz L(next_two_double_words) + and $15, %dl + jz L(second_double_word) + mov (%esi), %ecx + cmp %ecx, (%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(second_double_word): + mov 4(%esi), %ecx + cmp %ecx, 4(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(next_two_double_words): + and $15, %dh + jz L(fourth_double_word) + mov 8(%esi), %ecx + cmp %ecx, 8(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(fourth_double_word): + mov 12(%esi), %ecx + cmp %ecx, 12(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(less4_double_words_16): + xor %eax, %eax + test %dl, %dl + jz L(next_two_double_words_16) + and $15, %dl + jz L(second_double_word_16) + mov 16(%esi), %ecx + cmp %ecx, 16(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(second_double_word_16): + mov 20(%esi), %ecx + cmp %ecx, 20(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(next_two_double_words_16): + and $15, %dh + jz L(fourth_double_word_16) + mov 24(%esi), %ecx + cmp %ecx, 24(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(fourth_double_word_16): + mov 28(%esi), %ecx + cmp %ecx, 28(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(less4_double_words_32): + xor %eax, %eax + test %dl, %dl + jz L(next_two_double_words_32) + and $15, %dl + jz L(second_double_word_32) + mov 32(%esi), %ecx + cmp %ecx, 32(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(second_double_word_32): + mov 36(%esi), %ecx + cmp %ecx, 36(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(next_two_double_words_32): + and $15, %dh + jz L(fourth_double_word_32) + mov 40(%esi), %ecx + cmp %ecx, 40(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(fourth_double_word_32): + mov 44(%esi), %ecx + cmp %ecx, 44(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(less4_double_words_48): + xor %eax, %eax + test %dl, %dl + jz L(next_two_double_words_48) + and $15, %dl + jz L(second_double_word_48) + mov 48(%esi), %ecx + cmp %ecx, 48(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(second_double_word_48): + mov 52(%esi), %ecx + cmp %ecx, 52(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(next_two_double_words_48): + and $15, %dh + jz L(fourth_double_word_48) + mov 56(%esi), %ecx + cmp %ecx, 56(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(fourth_double_word_48): + mov 60(%esi), %ecx + cmp %ecx, 60(%edi) + jne L(nequal) + RETURN + + .p2align 4 +L(nequal): + mov $1, %eax + jg L(return) + neg %eax + RETURN + + .p2align 4 +L(return): + RETURN + + .p2align 4 +L(equal): + xorl %eax, %eax + RETURN + + CFI_POP (%edi) + CFI_POP (%esi) + + .p2align 4 +L(neq): + mov $1, %eax + jg L(neq_bigger) + neg %eax + +L(neq_bigger): + ret + + .p2align 4 +L(eq): + xorl %eax, %eax + ret + +END (wcscmp) +
diff --git a/libc/arch-x86/atom/string/sse2-wcslen-atom.S b/libc/arch-x86/atom/string/sse2-wcslen-atom.S new file mode 100644 index 0000000..2f10db4 --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-wcslen-atom.S
@@ -0,0 +1,306 @@ +/* +Copyright (c) 2011 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef USE_AS_WCSCAT + +# ifndef L +# define L(label) .L##label +# endif + +# ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +# endif + +# ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +# endif + +# ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +# endif + +# ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +# endif + +# define PARMS 4 +# define STR PARMS +# define RETURN ret + + .text +ENTRY (wcslen) + mov STR(%esp), %edx +#endif + cmpl $0, (%edx) + jz L(exit_tail0) + cmpl $0, 4(%edx) + jz L(exit_tail1) + cmpl $0, 8(%edx) + jz L(exit_tail2) + cmpl $0, 12(%edx) + jz L(exit_tail3) + cmpl $0, 16(%edx) + jz L(exit_tail4) + cmpl $0, 20(%edx) + jz L(exit_tail5) + cmpl $0, 24(%edx) + jz L(exit_tail6) + cmpl $0, 28(%edx) + jz L(exit_tail7) + + pxor %xmm0, %xmm0 + + lea 32(%edx), %eax + lea -16(%eax), %ecx + and $-16, %eax + + pcmpeqd (%eax), %xmm0 + pmovmskb %xmm0, %edx + pxor %xmm1, %xmm1 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm1 + pmovmskb %xmm1, %edx + pxor %xmm2, %xmm2 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm2 + pmovmskb %xmm2, %edx + pxor %xmm3, %xmm3 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqd (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + and $-0x40, %eax + + .p2align 4 +L(aligned_64_loop): + movaps (%eax), %xmm0 + movaps 16(%eax), %xmm1 + movaps 32(%eax), %xmm2 + movaps 48(%eax), %xmm6 + + pminub %xmm1, %xmm0 + pminub %xmm6, %xmm2 + pminub %xmm0, %xmm2 + pcmpeqd %xmm3, %xmm2 + pmovmskb %xmm2, %edx + lea 64(%eax), %eax + test %edx, %edx + jz L(aligned_64_loop) + + pcmpeqd -64(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 48(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqd %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqd -32(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqd %xmm6, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + jmp L(aligned_64_loop) + + .p2align 4 +L(exit): + sub %ecx, %eax + shr $2, %eax + test %dl, %dl + jz L(exit_high) + + mov %dl, %cl + and $15, %cl + jz L(exit_1) + RETURN + + .p2align 4 +L(exit_high): + mov %dh, %ch + and $15, %ch + jz L(exit_3) + add $2, %eax + RETURN + + .p2align 4 +L(exit_1): + add $1, %eax + RETURN + + .p2align 4 +L(exit_3): + add $3, %eax + RETURN + + .p2align 4 +L(exit_tail0): + xor %eax, %eax + RETURN + + .p2align 4 +L(exit_tail1): + mov $1, %eax + RETURN + + .p2align 4 +L(exit_tail2): + mov $2, %eax + RETURN + + .p2align 4 +L(exit_tail3): + mov $3, %eax + RETURN + + .p2align 4 +L(exit_tail4): + mov $4, %eax + RETURN + + .p2align 4 +L(exit_tail5): + mov $5, %eax + RETURN + + .p2align 4 +L(exit_tail6): + mov $6, %eax + RETURN + + .p2align 4 +L(exit_tail7): + mov $7, %eax +#ifndef USE_AS_WCSCAT + RETURN + +END (wcslen) +#endif
diff --git a/libc/arch-x86/atom/string/sse2-wcsrchr-atom.S b/libc/arch-x86/atom/string/sse2-wcsrchr-atom.S new file mode 100644 index 0000000..1a55df2 --- /dev/null +++ b/libc/arch-x86/atom/string/sse2-wcsrchr-atom.S
@@ -0,0 +1,402 @@ +/* +Copyright (c) 2011 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 8 +#define ENTRANCE PUSH(%edi); +#define RETURN POP(%edi); ret; CFI_PUSH(%edi); + +#define STR1 PARMS +#define STR2 STR1+4 + + .text +ENTRY (wcsrchr) + + ENTRANCE + mov STR1(%esp), %ecx + movd STR2(%esp), %xmm1 + + mov %ecx, %edi + punpckldq %xmm1, %xmm1 + pxor %xmm2, %xmm2 + punpckldq %xmm1, %xmm1 + +/* ECX has OFFSET. */ + and $63, %ecx + cmp $48, %ecx + ja L(crosscache) + +/* unaligned string. */ + movdqu (%edi), %xmm0 + pcmpeqd %xmm0, %xmm2 + pcmpeqd %xmm1, %xmm0 +/* Find where NULL is. */ + pmovmskb %xmm2, %ecx +/* Check if there is a match. */ + pmovmskb %xmm0, %eax + add $16, %edi + + test %eax, %eax + jnz L(unaligned_match1) + + test %ecx, %ecx + jnz L(return_null) + + and $-16, %edi + + PUSH (%esi) + + xor %edx, %edx + jmp L(loop) + + CFI_POP (%esi) + + .p2align 4 +L(unaligned_match1): + test %ecx, %ecx + jnz L(prolog_find_zero_1) + + PUSH (%esi) + +/* Save current match */ + mov %eax, %edx + mov %edi, %esi + and $-16, %edi + jmp L(loop) + + CFI_POP (%esi) + + .p2align 4 +L(crosscache): +/* Hancle unaligned string. */ + and $15, %ecx + and $-16, %edi + pxor %xmm3, %xmm3 + movdqa (%edi), %xmm0 + pcmpeqd %xmm0, %xmm3 + pcmpeqd %xmm1, %xmm0 +/* Find where NULL is. */ + pmovmskb %xmm3, %edx +/* Check if there is a match. */ + pmovmskb %xmm0, %eax +/* Remove the leading bytes. */ + shr %cl, %edx + shr %cl, %eax + add $16, %edi + + test %eax, %eax + jnz L(unaligned_match) + + test %edx, %edx + jnz L(return_null) + + PUSH (%esi) + + xor %edx, %edx + jmp L(loop) + + CFI_POP (%esi) + + .p2align 4 +L(unaligned_match): + test %edx, %edx + jnz L(prolog_find_zero) + + PUSH (%esi) + + mov %eax, %edx + lea (%edi, %ecx), %esi + +/* Loop start on aligned string. */ + .p2align 4 +L(loop): + movdqa (%edi), %xmm0 + pcmpeqd %xmm0, %xmm2 + add $16, %edi + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm2, %ecx + pmovmskb %xmm0, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm3 + pcmpeqd %xmm3, %xmm2 + add $16, %edi + pcmpeqd %xmm1, %xmm3 + pmovmskb %xmm2, %ecx + pmovmskb %xmm3, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm4 + pcmpeqd %xmm4, %xmm2 + add $16, %edi + pcmpeqd %xmm1, %xmm4 + pmovmskb %xmm2, %ecx + pmovmskb %xmm4, %eax + or %eax, %ecx + jnz L(matches) + + movdqa (%edi), %xmm5 + pcmpeqd %xmm5, %xmm2 + add $16, %edi + pcmpeqd %xmm1, %xmm5 + pmovmskb %xmm2, %ecx + pmovmskb %xmm5, %eax + or %eax, %ecx + jz L(loop) + + .p2align 4 +L(matches): + test %eax, %eax + jnz L(match) +L(return_value): + test %edx, %edx + jz L(return_null_1) + mov %edx, %eax + mov %esi, %edi + + POP (%esi) + + test %ah, %ah + jnz L(match_third_or_fourth_wchar) + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(return_null_1): + POP (%esi) + + xor %eax, %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(match): + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(find_zero) +/* save match info */ + mov %eax, %edx + mov %edi, %esi + jmp L(loop) + + .p2align 4 +L(find_zero): + test %cl, %cl + jz L(find_zero_in_third_or_fourth_wchar) + test $15, %cl + jz L(find_zero_in_second_wchar) + and $1, %eax + jz L(return_value) + + POP (%esi) + + lea -16(%edi), %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_in_second_wchar): + and $(1 << 5) - 1, %eax + jz L(return_value) + + POP (%esi) + + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_in_third_or_fourth_wchar): + test $15, %ch + jz L(find_zero_in_fourth_wchar) + and $(1 << 9) - 1, %eax + jz L(return_value) + + POP (%esi) + + test %ah, %ah + jnz L(match_third_wchar) + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(find_zero_in_fourth_wchar): + + POP (%esi) + + test %ah, %ah + jnz L(match_third_or_fourth_wchar) + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(match_second_wchar): + lea -12(%edi), %eax + RETURN + + .p2align 4 +L(match_third_or_fourth_wchar): + test $15 << 4, %ah + jnz L(match_fourth_wchar) + lea -8(%edi), %eax + RETURN + + .p2align 4 +L(match_third_wchar): + lea -8(%edi), %eax + RETURN + + .p2align 4 +L(match_fourth_wchar): + lea -4(%edi), %eax + RETURN + + .p2align 4 +L(return_null): + xor %eax, %eax + RETURN + + .p2align 4 +L(prolog_find_zero): + add %ecx, %edi + mov %edx, %ecx +L(prolog_find_zero_1): + test %cl, %cl + jz L(prolog_find_zero_in_third_or_fourth_wchar) + test $15, %cl + jz L(prolog_find_zero_in_second_wchar) + and $1, %eax + jz L(return_null) + + lea -16(%edi), %eax + RETURN + + .p2align 4 +L(prolog_find_zero_in_second_wchar): + and $(1 << 5) - 1, %eax + jz L(return_null) + + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + .p2align 4 +L(prolog_find_zero_in_third_or_fourth_wchar): + test $15, %ch + jz L(prolog_find_zero_in_fourth_wchar) + and $(1 << 9) - 1, %eax + jz L(return_null) + + test %ah, %ah + jnz L(match_third_wchar) + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + + .p2align 4 +L(prolog_find_zero_in_fourth_wchar): + test %ah, %ah + jnz L(match_third_or_fourth_wchar) + test $15 << 4, %al + jnz L(match_second_wchar) + lea -16(%edi), %eax + RETURN + +END (wcsrchr)
diff --git a/libc/arch-x86/atom/string/ssse3-memcmp-atom.S b/libc/arch-x86/atom/string/ssse3-memcmp-atom.S new file mode 100644 index 0000000..0387084 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-memcmp-atom.S
@@ -0,0 +1,2496 @@ +/* +Copyright (c) 2010, 2011, 2012, 2013 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef cfi_remember_state +# define cfi_remember_state .cfi_remember_state +#endif + +#ifndef cfi_restore_state +# define cfi_restore_state .cfi_restore_state +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#ifndef MEMCMP +# define MEMCMP memcmp +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 4 +#define BLK1 PARMS +#define BLK2 BLK1+4 +#define LEN BLK2+4 +#define RETURN_END POP (%edi); POP (%esi); POP (%ebx); ret +#define RETURN RETURN_END; cfi_restore_state; cfi_remember_state + +/* Warning! + wmemcmp has to use SIGNED comparison for elements. + memcmp has to use UNSIGNED comparison for elemnts. +*/ + + .text +ENTRY (MEMCMP) + movl LEN(%esp), %ecx + +#ifdef USE_WCHAR + shl $2, %ecx + jz L(zero) +#elif defined USE_UTF16 + shl $1, %ecx + jz L(zero) +#endif + + movl BLK1(%esp), %eax + cmp $48, %ecx + movl BLK2(%esp), %edx + jae L(48bytesormore) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $1, %ecx + jbe L(less1bytes) +#endif + + PUSH (%ebx) + add %ecx, %edx + add %ecx, %eax + jmp L(less48bytes) + + CFI_POP (%ebx) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + .p2align 4 +L(less1bytes): + jb L(zero) + movb (%eax), %cl + cmp (%edx), %cl + je L(zero) + mov $1, %eax + ja L(1bytesend) + neg %eax +L(1bytesend): + ret +#endif + + .p2align 4 +L(zero): + xor %eax, %eax + ret + + .p2align 4 +L(48bytesormore): + PUSH (%ebx) + PUSH (%esi) + PUSH (%edi) + cfi_remember_state + movdqu (%eax), %xmm3 + movdqu (%edx), %xmm0 + movl %eax, %edi + movl %edx, %esi + pcmpeqb %xmm0, %xmm3 + pmovmskb %xmm3, %edx + lea 16(%edi), %edi + + sub $0xffff, %edx + lea 16(%esi), %esi + jnz L(less16bytes) + mov %edi, %edx + and $0xf, %edx + xor %edx, %edi + sub %edx, %esi + add %edx, %ecx + mov %esi, %edx + and $0xf, %edx + jz L(shr_0) + xor %edx, %esi + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $8, %edx + jae L(next_unaligned_table) + cmp $0, %edx + je L(shr_0) + cmp $1, %edx + je L(shr_1) + cmp $2, %edx + je L(shr_2) + cmp $3, %edx + je L(shr_3) + cmp $4, %edx + je L(shr_4) + cmp $5, %edx + je L(shr_5) + cmp $6, %edx + je L(shr_6) + jmp L(shr_7) + + .p2align 2 +L(next_unaligned_table): + cmp $8, %edx + je L(shr_8) + cmp $9, %edx + je L(shr_9) + cmp $10, %edx + je L(shr_10) + cmp $11, %edx + je L(shr_11) + cmp $12, %edx + je L(shr_12) + cmp $13, %edx + je L(shr_13) + cmp $14, %edx + je L(shr_14) + jmp L(shr_15) +#elif defined(USE_WCHAR) + cmp $0, %edx + je L(shr_0) + cmp $4, %edx + je L(shr_4) + cmp $8, %edx + je L(shr_8) + jmp L(shr_12) +#elif defined(USE_UTF16) + cmp $0, %edx + je L(shr_0) + cmp $2, %edx + je L(shr_2) + cmp $4, %edx + je L(shr_4) + cmp $6, %edx + je L(shr_6) + cmp $8, %edx + je L(shr_8) + cmp $10, %edx + je L(shr_10) + cmp $12, %edx + je L(shr_12) + jmp L(shr_14) +#endif + + .p2align 4 +L(shr_0): + cmp $80, %ecx + jae L(shr_0_gobble) + lea -48(%ecx), %ecx + xor %eax, %eax + movaps (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + movaps 16(%esi), %xmm2 + pcmpeqb 16(%edi), %xmm2 + pand %xmm1, %xmm2 + pmovmskb %xmm2, %edx + add $32, %edi + add $32, %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea (%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_0_gobble): + lea -48(%ecx), %ecx + movdqa (%esi), %xmm0 + xor %eax, %eax + pcmpeqb (%edi), %xmm0 + sub $32, %ecx + movdqa 16(%esi), %xmm2 + pcmpeqb 16(%edi), %xmm2 +L(shr_0_gobble_loop): + pand %xmm0, %xmm2 + sub $32, %ecx + pmovmskb %xmm2, %edx + movdqa %xmm0, %xmm1 + movdqa 32(%esi), %xmm0 + movdqa 48(%esi), %xmm2 + sbb $0xffff, %edx + pcmpeqb 32(%edi), %xmm0 + pcmpeqb 48(%edi), %xmm2 + lea 32(%edi), %edi + lea 32(%esi), %esi + jz L(shr_0_gobble_loop) + + pand %xmm0, %xmm2 + cmp $0, %ecx + jge L(shr_0_gobble_loop_next) + inc %edx + add $32, %ecx +L(shr_0_gobble_loop_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm2, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea (%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_1): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_1_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $1,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $1,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 1(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_1_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $1,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $1,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_1_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $1,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $1,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_1_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_1_gobble_next) + inc %edx + add $32, %ecx +L(shr_1_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 1(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + + +#if !defined(USE_WCHAR) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_2): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_2_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $2,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $2,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 2(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_2_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $2,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $2,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_2_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $2,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $2,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_2_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_2_gobble_next) + inc %edx + add $32, %ecx +L(shr_2_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 2(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_3): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_3_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $3,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $3,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 3(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_3_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $3,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $3,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_3_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $3,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $3,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_3_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_3_gobble_next) + inc %edx + add $32, %ecx +L(shr_3_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 3(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_4): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_4_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $4,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $4,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 4(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_4_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $4,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $4,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_4_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $4,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $4,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_4_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_4_gobble_next) + inc %edx + add $32, %ecx +L(shr_4_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 4(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_5): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_5_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $5,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $5,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 5(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_5_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $5,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $5,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_5_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $5,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $5,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_5_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_5_gobble_next) + inc %edx + add $32, %ecx +L(shr_5_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 5(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_6): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_6_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $6,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $6,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 6(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_6_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $6,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $6,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_6_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $6,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $6,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_6_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_6_gobble_next) + inc %edx + add $32, %ecx +L(shr_6_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 6(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_7): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_7_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $7,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $7,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 7(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_7_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $7,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $7,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_7_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $7,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $7,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_7_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_7_gobble_next) + inc %edx + add $32, %ecx +L(shr_7_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 7(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_8): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_8_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $8,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $8,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 8(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_8_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $8,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $8,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_8_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $8,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $8,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_8_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_8_gobble_next) + inc %edx + add $32, %ecx +L(shr_8_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 8(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_9): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_9_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $9,(%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $9,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 9(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_9_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $9,(%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $9,16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_9_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $9,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $9,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_9_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_9_gobble_next) + inc %edx + add $32, %ecx +L(shr_9_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 9(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_10): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_10_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $10, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $10,%xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 10(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_10_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $10, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $10, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_10_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $10,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $10,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_10_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_10_gobble_next) + inc %edx + add $32, %ecx +L(shr_10_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 10(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_11): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_11_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $11, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $11, %xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 11(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_11_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $11, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $11, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_11_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $11,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $11,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_11_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_11_gobble_next) + inc %edx + add $32, %ecx +L(shr_11_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 11(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_12): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_12_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $12, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $12, %xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 12(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_12_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $12, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $12, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_12_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $12,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $12,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_12_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_12_gobble_next) + inc %edx + add $32, %ecx +L(shr_12_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 12(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_13): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_13_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $13, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $13, %xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 13(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_13_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $13, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $13, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_13_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $13,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $13,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_13_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_13_gobble_next) + inc %edx + add $32, %ecx +L(shr_13_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 13(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_14): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_14_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $14, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $14, %xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 14(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_14_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $14, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $14, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_14_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $14,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $14,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_14_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_14_gobble_next) + inc %edx + add $32, %ecx +L(shr_14_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 14(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_15): + cmp $80, %ecx + lea -48(%ecx), %ecx + mov %edx, %eax + jae L(shr_15_gobble) + + movdqa 16(%esi), %xmm1 + movdqa %xmm1, %xmm2 + palignr $15, (%esi), %xmm1 + pcmpeqb (%edi), %xmm1 + + movdqa 32(%esi), %xmm3 + palignr $15, %xmm2, %xmm3 + pcmpeqb 16(%edi), %xmm3 + + pand %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + lea (%ecx, %edi,1), %eax + lea 15(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(shr_15_gobble): + sub $32, %ecx + movdqa 16(%esi), %xmm0 + palignr $15, (%esi), %xmm0 + pcmpeqb (%edi), %xmm0 + + movdqa 32(%esi), %xmm3 + palignr $15, 16(%esi), %xmm3 + pcmpeqb 16(%edi), %xmm3 + +L(shr_15_gobble_loop): + pand %xmm0, %xmm3 + sub $32, %ecx + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + + movdqa 64(%esi), %xmm3 + palignr $15,48(%esi), %xmm3 + sbb $0xffff, %edx + movdqa 48(%esi), %xmm0 + palignr $15,32(%esi), %xmm0 + pcmpeqb 32(%edi), %xmm0 + lea 32(%esi), %esi + pcmpeqb 48(%edi), %xmm3 + + lea 32(%edi), %edi + jz L(shr_15_gobble_loop) + pand %xmm0, %xmm3 + + cmp $0, %ecx + jge L(shr_15_gobble_next) + inc %edx + add $32, %ecx +L(shr_15_gobble_next): + test %edx, %edx + jnz L(exit) + + pmovmskb %xmm3, %edx + movdqa %xmm0, %xmm1 + lea 32(%edi), %edi + lea 32(%esi), %esi + sub $0xffff, %edx + jnz L(exit) + + lea (%ecx, %edi,1), %eax + lea 15(%ecx, %esi,1), %edx + POP (%edi) + POP (%esi) + jmp L(less48bytes) +#endif + + cfi_restore_state + cfi_remember_state + .p2align 4 +L(exit): + pmovmskb %xmm1, %ebx + sub $0xffff, %ebx + jz L(first16bytes) + lea -16(%esi), %esi + lea -16(%edi), %edi + mov %ebx, %edx + +L(first16bytes): + add %eax, %esi +L(less16bytes): + +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + test %dl, %dl + jz L(next_24_bytes) + + test $0x01, %dl + jnz L(Byte16) + + test $0x02, %dl + jnz L(Byte17) + + test $0x04, %dl + jnz L(Byte18) + + test $0x08, %dl + jnz L(Byte19) + + test $0x10, %dl + jnz L(Byte20) + + test $0x20, %dl + jnz L(Byte21) + + test $0x40, %dl + jnz L(Byte22) +L(Byte23): + movzbl -9(%edi), %eax + movzbl -9(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte16): + movzbl -16(%edi), %eax + movzbl -16(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte17): + movzbl -15(%edi), %eax + movzbl -15(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte18): + movzbl -14(%edi), %eax + movzbl -14(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte19): + movzbl -13(%edi), %eax + movzbl -13(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte20): + movzbl -12(%edi), %eax + movzbl -12(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte21): + movzbl -11(%edi), %eax + movzbl -11(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(Byte22): + movzbl -10(%edi), %eax + movzbl -10(%esi), %edx + sub %edx, %eax + RETURN + + .p2align 4 +L(next_24_bytes): + lea 8(%edi), %edi + lea 8(%esi), %esi + test $0x01, %dh + jnz L(Byte16) + + test $0x02, %dh + jnz L(Byte17) + + test $0x04, %dh + jnz L(Byte18) + + test $0x08, %dh + jnz L(Byte19) + + test $0x10, %dh + jnz L(Byte20) + + test $0x20, %dh + jnz L(Byte21) + + test $0x40, %dh + jnz L(Byte22) + + .p2align 4 +L(Byte31): + movzbl -9(%edi), %eax + movzbl -9(%esi), %edx + sub %edx, %eax + RETURN_END +#elif defined(USE_AS_WMEMCMP) + +/* special for wmemcmp */ + test %dl, %dl + jz L(next_two_double_words) + and $15, %dl + jz L(second_double_word) + mov -16(%edi), %ecx + cmp -16(%esi), %ecx + mov $1, %eax + jg L(nequal_bigger) + neg %eax + RETURN + + .p2align 4 +L(second_double_word): + mov -12(%edi), %ecx + cmp -12(%esi), %ecx + mov $1, %eax + jg L(nequal_bigger) + neg %eax + RETURN + + .p2align 4 +L(next_two_double_words): + and $15, %dh + jz L(fourth_double_word) + mov -8(%edi), %ecx + cmp -8(%esi), %ecx + mov $1, %eax + jg L(nequal_bigger) + neg %eax + RETURN + + .p2align 4 +L(fourth_double_word): + mov -4(%edi), %ecx + cmp -4(%esi), %ecx + mov $1, %eax + jg L(nequal_bigger) + neg %eax + RETURN + + .p2align 4 +L(nequal_bigger): + RETURN_END + +#elif defined(USE_AS_MEMCMP16) + +/* special for __memcmp16 */ + test %dl, %dl + jz L(next_four_words) + test $15, %dl + jz L(second_two_words) + test $3, %dl + jz L(second_word) + movzwl -16(%edi), %eax + movzwl -16(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(second_word): + movzwl -14(%edi), %eax + movzwl -14(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(second_two_words): + test $63, %dl + jz L(fourth_word) + movzwl -12(%edi), %eax + movzwl -12(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(fourth_word): + movzwl -10(%edi), %eax + movzwl -10(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(next_four_words): + test $15, %dh + jz L(fourth_two_words) + test $3, %dh + jz L(sixth_word) + movzwl -8(%edi), %eax + movzwl -8(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(sixth_word): + movzwl -6(%edi), %eax + movzwl -6(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(fourth_two_words): + test $63, %dh + jz L(eighth_word) + movzwl -4(%edi), %eax + movzwl -4(%esi), %ebx + subl %ebx, %eax + RETURN + + .p2align 4 +L(eighth_word): + movzwl -2(%edi), %eax + movzwl -2(%esi), %ebx + subl %ebx, %eax + RETURN +#else +# error Unreachable preprocessor case +#endif + + CFI_PUSH (%ebx) + + .p2align 4 +L(more8bytes): + cmp $16, %ecx + jae L(more16bytes) + cmp $8, %ecx + je L(8bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $9, %ecx + je L(9bytes) + cmp $10, %ecx + je L(10bytes) + cmp $11, %ecx + je L(11bytes) + cmp $12, %ecx + je L(12bytes) + cmp $13, %ecx + je L(13bytes) + cmp $14, %ecx + je L(14bytes) + jmp L(15bytes) +#elif defined(USE_WCHAR) && !defined(USE_UTF16) + jmp L(12bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $10, %ecx + je L(10bytes) + cmp $12, %ecx + je L(12bytes) + jmp L(14bytes) +#else +# error Unreachable preprocessor case +#endif + + .p2align 4 +L(more16bytes): + cmp $24, %ecx + jae L(more24bytes) + cmp $16, %ecx + je L(16bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $17, %ecx + je L(17bytes) + cmp $18, %ecx + je L(18bytes) + cmp $19, %ecx + je L(19bytes) + cmp $20, %ecx + je L(20bytes) + cmp $21, %ecx + je L(21bytes) + cmp $22, %ecx + je L(22bytes) + jmp L(23bytes) +#elif defined(USE_WCHAR) && !defined(USE_UTF16) + jmp L(20bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $18, %ecx + je L(18bytes) + cmp $20, %ecx + je L(20bytes) + jmp L(22bytes) +#else +# error Unreachable preprocessor case +#endif + + .p2align 4 +L(more24bytes): + cmp $32, %ecx + jae L(more32bytes) + cmp $24, %ecx + je L(24bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $25, %ecx + je L(25bytes) + cmp $26, %ecx + je L(26bytes) + cmp $27, %ecx + je L(27bytes) + cmp $28, %ecx + je L(28bytes) + cmp $29, %ecx + je L(29bytes) + cmp $30, %ecx + je L(30bytes) + jmp L(31bytes) +#elif defined(USE_WCHAR) && !defined(USE_UTF16) + jmp L(28bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $26, %ecx + je L(26bytes) + cmp $28, %ecx + je L(28bytes) + jmp L(30bytes) +#else +# error Unreachable preprocessor case +#endif + + .p2align 4 +L(more32bytes): + cmp $40, %ecx + jae L(more40bytes) + cmp $32, %ecx + je L(32bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $33, %ecx + je L(33bytes) + cmp $34, %ecx + je L(34bytes) + cmp $35, %ecx + je L(35bytes) + cmp $36, %ecx + je L(36bytes) + cmp $37, %ecx + je L(37bytes) + cmp $38, %ecx + je L(38bytes) + jmp L(39bytes) +#elif defined(USE_WCHAR) && !defined(USE_UTF16) + jmp L(36bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $34, %ecx + je L(34bytes) + cmp $36, %ecx + je L(36bytes) + jmp L(38bytes) +#else +# error Unreachable preprocessor case +#endif + + .p2align 4 +L(less48bytes): + cmp $8, %ecx + jae L(more8bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $2, %ecx + je L(2bytes) + cmp $3, %ecx + je L(3bytes) + cmp $4, %ecx + je L(4bytes) + cmp $5, %ecx + je L(5bytes) + cmp $6, %ecx + je L(6bytes) + jmp L(7bytes) +#elif defined(USE_WCHAR) && !defined(USE_UTF16) + jmp L(4bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $2, %ecx + je L(2bytes) + cmp $4, %ecx + je L(4bytes) + jmp L(6bytes) +#else +# error Unreachable preprocessor case +#endif + + .p2align 4 +L(more40bytes): + cmp $40, %ecx + je L(40bytes) +#if !defined(USE_WCHAR) && !defined(USE_UTF16) + cmp $41, %ecx + je L(41bytes) + cmp $42, %ecx + je L(42bytes) + cmp $43, %ecx + je L(43bytes) + cmp $44, %ecx + je L(44bytes) + cmp $45, %ecx + je L(45bytes) + cmp $46, %ecx + je L(46bytes) + jmp L(47bytes) +#elif defined(USE_UTF16) && !defined(USE_WCHAR) + cmp $42, %ecx + je L(42bytes) + cmp $44, %ecx + je L(44bytes) + jmp L(46bytes) +#endif + +#if !defined(USE_AS_WMEMCMP) && !defined(USE_AS_MEMCMP16) + .p2align 4 +L(44bytes): + mov -44(%eax), %ecx + mov -44(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(40bytes): + mov -40(%eax), %ecx + mov -40(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(36bytes): + mov -36(%eax), %ecx + mov -36(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(32bytes): + mov -32(%eax), %ecx + mov -32(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(28bytes): + mov -28(%eax), %ecx + mov -28(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(24bytes): + mov -24(%eax), %ecx + mov -24(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(20bytes): + mov -20(%eax), %ecx + mov -20(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(16bytes): + mov -16(%eax), %ecx + mov -16(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(12bytes): + mov -12(%eax), %ecx + mov -12(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(8bytes): + mov -8(%eax), %ecx + mov -8(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(4bytes): + mov -4(%eax), %ecx + mov -4(%edx), %ebx + cmp %ebx, %ecx + mov $0, %eax + jne L(find_diff) + POP (%ebx) + ret + CFI_PUSH (%ebx) +#elif defined(USE_AS_WMEMCMP) + + .p2align 4 +L(44bytes): + mov -44(%eax), %ecx + cmp -44(%edx), %ecx + jne L(find_diff) +L(40bytes): + mov -40(%eax), %ecx + cmp -40(%edx), %ecx + jne L(find_diff) +L(36bytes): + mov -36(%eax), %ecx + cmp -36(%edx), %ecx + jne L(find_diff) +L(32bytes): + mov -32(%eax), %ecx + cmp -32(%edx), %ecx + jne L(find_diff) +L(28bytes): + mov -28(%eax), %ecx + cmp -28(%edx), %ecx + jne L(find_diff) +L(24bytes): + mov -24(%eax), %ecx + cmp -24(%edx), %ecx + jne L(find_diff) +L(20bytes): + mov -20(%eax), %ecx + cmp -20(%edx), %ecx + jne L(find_diff) +L(16bytes): + mov -16(%eax), %ecx + cmp -16(%edx), %ecx + jne L(find_diff) +L(12bytes): + mov -12(%eax), %ecx + cmp -12(%edx), %ecx + jne L(find_diff) +L(8bytes): + mov -8(%eax), %ecx + cmp -8(%edx), %ecx + jne L(find_diff) +L(4bytes): + mov -4(%eax), %ecx + xor %eax, %eax + cmp -4(%edx), %ecx + jne L(find_diff) + POP (%ebx) + ret + CFI_PUSH (%ebx) +#elif defined USE_AS_MEMCMP16 + + .p2align 4 +L(46bytes): + movzwl -46(%eax), %ecx + movzwl -46(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(44bytes): + movzwl -44(%eax), %ecx + movzwl -44(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(42bytes): + movzwl -42(%eax), %ecx + movzwl -42(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(40bytes): + movzwl -40(%eax), %ecx + movzwl -40(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(38bytes): + movzwl -38(%eax), %ecx + movzwl -38(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(36bytes): + movzwl -36(%eax), %ecx + movzwl -36(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(34bytes): + movzwl -34(%eax), %ecx + movzwl -34(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(32bytes): + movzwl -32(%eax), %ecx + movzwl -32(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(30bytes): + movzwl -30(%eax), %ecx + movzwl -30(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(28bytes): + movzwl -28(%eax), %ecx + movzwl -28(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(26bytes): + movzwl -26(%eax), %ecx + movzwl -26(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(24bytes): + movzwl -24(%eax), %ecx + movzwl -24(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(22bytes): + movzwl -22(%eax), %ecx + movzwl -22(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(20bytes): + movzwl -20(%eax), %ecx + movzwl -20(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(18bytes): + movzwl -18(%eax), %ecx + movzwl -18(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(16bytes): + movzwl -16(%eax), %ecx + movzwl -16(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(14bytes): + movzwl -14(%eax), %ecx + movzwl -14(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(12bytes): + movzwl -12(%eax), %ecx + movzwl -12(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(10bytes): + movzwl -10(%eax), %ecx + movzwl -10(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(8bytes): + movzwl -8(%eax), %ecx + movzwl -8(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(6bytes): + movzwl -6(%eax), %ecx + movzwl -6(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(4bytes): + movzwl -4(%eax), %ecx + movzwl -4(%edx), %ebx + subl %ebx, %ecx + jne L(memcmp16_exit) +L(2bytes): + movzwl -2(%eax), %eax + movzwl -2(%edx), %ebx + subl %ebx, %eax + POP (%ebx) + ret + CFI_PUSH (%ebx) +#else +# error Unreachable preprocessor case +#endif + +#if !defined(USE_AS_WMEMCMP) && !defined(USE_AS_MEMCMP16) + + .p2align 4 +L(45bytes): + mov -45(%eax), %ecx + mov -45(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(41bytes): + mov -41(%eax), %ecx + mov -41(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(37bytes): + mov -37(%eax), %ecx + mov -37(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(33bytes): + mov -33(%eax), %ecx + mov -33(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(29bytes): + mov -29(%eax), %ecx + mov -29(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(25bytes): + mov -25(%eax), %ecx + mov -25(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(21bytes): + mov -21(%eax), %ecx + mov -21(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(17bytes): + mov -17(%eax), %ecx + mov -17(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(13bytes): + mov -13(%eax), %ecx + mov -13(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(9bytes): + mov -9(%eax), %ecx + mov -9(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(5bytes): + mov -5(%eax), %ecx + mov -5(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzbl -1(%eax), %ecx + cmp -1(%edx), %cl + mov $0, %eax + jne L(end) + POP (%ebx) + ret + CFI_PUSH (%ebx) + + .p2align 4 +L(46bytes): + mov -46(%eax), %ecx + mov -46(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(42bytes): + mov -42(%eax), %ecx + mov -42(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(38bytes): + mov -38(%eax), %ecx + mov -38(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(34bytes): + mov -34(%eax), %ecx + mov -34(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(30bytes): + mov -30(%eax), %ecx + mov -30(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(26bytes): + mov -26(%eax), %ecx + mov -26(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(22bytes): + mov -22(%eax), %ecx + mov -22(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(18bytes): + mov -18(%eax), %ecx + mov -18(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(14bytes): + mov -14(%eax), %ecx + mov -14(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(10bytes): + mov -10(%eax), %ecx + mov -10(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(6bytes): + mov -6(%eax), %ecx + mov -6(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(2bytes): + movzwl -2(%eax), %ecx + movzwl -2(%edx), %ebx + cmp %bl, %cl + jne L(end) + cmp %bh, %ch + mov $0, %eax + jne L(end) + POP (%ebx) + ret + CFI_PUSH (%ebx) + + .p2align 4 +L(47bytes): + movl -47(%eax), %ecx + movl -47(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(43bytes): + movl -43(%eax), %ecx + movl -43(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(39bytes): + movl -39(%eax), %ecx + movl -39(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(35bytes): + movl -35(%eax), %ecx + movl -35(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(31bytes): + movl -31(%eax), %ecx + movl -31(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(27bytes): + movl -27(%eax), %ecx + movl -27(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(23bytes): + movl -23(%eax), %ecx + movl -23(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(19bytes): + movl -19(%eax), %ecx + movl -19(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(15bytes): + movl -15(%eax), %ecx + movl -15(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(11bytes): + movl -11(%eax), %ecx + movl -11(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(7bytes): + movl -7(%eax), %ecx + movl -7(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(3bytes): + movzwl -3(%eax), %ecx + movzwl -3(%edx), %ebx + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + movzbl -1(%eax), %eax + cmpb -1(%edx), %al + mov $0, %eax + jne L(end) + POP (%ebx) + ret + CFI_PUSH (%ebx) + + .p2align 4 +L(find_diff): + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + shr $16,%ecx + shr $16,%ebx + cmp %bl, %cl + jne L(end) + cmp %bx, %cx + + .p2align 4 +L(end): + POP (%ebx) + mov $1, %eax + ja L(bigger) + neg %eax +L(bigger): + ret +#elif defined(USE_AS_WMEMCMP) + + .p2align 4 +L(find_diff): + POP (%ebx) + mov $1, %eax + jg L(find_diff_bigger) + neg %eax + ret + + .p2align 4 +L(find_diff_bigger): + ret + +#elif defined(USE_AS_MEMCMP16) + + .p2align 4 +L(memcmp16_exit): + POP (%ebx) + mov %ecx, %eax + ret +#else +# error Unreachable preprocessor case +#endif +END (MEMCMP)
diff --git a/libc/arch-x86/atom/string/ssse3-memcpy-atom.S b/libc/arch-x86/atom/string/ssse3-memcpy-atom.S new file mode 100644 index 0000000..4b2fb8e --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-memcpy-atom.S
@@ -0,0 +1,3124 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "cache.h" + +#ifndef MEMCPY +# define MEMCPY memcpy +#endif + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define DEST PARMS +#define SRC DEST+4 +#define LEN SRC+4 + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#if (defined SHARED || defined __PIC__) +# define PARMS 8 /* Preserve EBX. */ +# define ENTRANCE PUSH (%ebx); +# define RETURN_END POP (%ebx); ret +# define RETURN RETURN_END; CFI_PUSH (%ebx) +# define JMPTBL(I, B) I - B + +# define SETUP_PIC_REG(x) call __x86.get_pc_thunk.x + +/* Load an entry in a jump table into EBX and branch to it. TABLE is a + jump table with relative offsets. INDEX is a register contains the + index into the jump table. SCALE is the scale of INDEX. */ + +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ + /* We first load PC into EBX. */ \ + SETUP_PIC_REG(bx); \ + /* Get the address of the jump table. */ \ + addl $(TABLE - .), %ebx; \ + /* Get the entry and convert the relative offset to the \ + absolute address. */ \ + addl (%ebx, INDEX, SCALE), %ebx; \ + /* We loaded the jump table. Go. */ \ + jmp *%ebx +#else + +# define PARMS 4 +# define ENTRANCE +# define RETURN_END ret +# define RETURN RETURN_END +# define JMPTBL(I, B) I + +/* Branch to an entry in a jump table. TABLE is a jump table with + absolute offsets. INDEX is a register contains the index into the + jump table. SCALE is the scale of INDEX. */ + +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ + jmp *TABLE(, INDEX, SCALE) +#endif + + .section .text.ssse3,"ax",@progbits +ENTRY (MEMCPY) + ENTRANCE + movl LEN(%esp), %ecx + movl SRC(%esp), %eax + movl DEST(%esp), %edx + +#ifdef USE_AS_MEMMOVE + cmp %eax, %edx + jb L(copy_forward) + je L(fwd_write_0bytes) + cmp $32, %ecx + jae L(memmove_bwd) + jmp L(bk_write_less32bytes_2) + + .p2align 4 +L(memmove_bwd): + add %ecx, %eax + cmp %eax, %edx + movl SRC(%esp), %eax + jb L(copy_backward) + +L(copy_forward): +#endif + cmp $48, %ecx + jae L(48bytesormore) + +L(fwd_write_less32bytes): +#ifndef USE_AS_MEMMOVE + cmp %dl, %al + jb L(bk_write) +#endif + add %ecx, %edx + add %ecx, %eax + BRANCH_TO_JMPTBL_ENTRY (L(table_48bytes_fwd), %ecx, 4) +#ifndef USE_AS_MEMMOVE + .p2align 4 +L(bk_write): + BRANCH_TO_JMPTBL_ENTRY (L(table_48_bytes_bwd), %ecx, 4) +#endif + + .p2align 4 +L(48bytesormore): +#ifndef USE_AS_MEMMOVE + movlpd (%eax), %xmm0 + movlpd 8(%eax), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) +#else + movdqu (%eax), %xmm0 +#endif + PUSH (%edi) + movl %edx, %edi + and $-16, %edx + add $16, %edx + sub %edx, %edi + add %edi, %ecx + sub %edi, %eax + +#ifdef SHARED_CACHE_SIZE_HALF + cmp $SHARED_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_shared_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_shared_cache_size_half, %ecx +# endif +#endif + + mov %eax, %edi + jae L(large_page) + and $0xf, %edi + jz L(shl_0) + BRANCH_TO_JMPTBL_ENTRY (L(shl_table), %edi, 4) + + .p2align 4 +L(shl_0): +#ifdef USE_AS_MEMMOVE + movl DEST+4(%esp), %edi + movdqu %xmm0, (%edi) +#endif + xor %edi, %edi + cmp $127, %ecx + ja L(shl_0_gobble) + lea -32(%ecx), %ecx + + .p2align 4 +L(shl_0_loop): + movdqa (%eax, %edi), %xmm0 + movdqa 16(%eax, %edi), %xmm1 + sub $32, %ecx + movdqa %xmm0, (%edx, %edi) + movdqa %xmm1, 16(%edx, %edi) + lea 32(%edi), %edi + jb L(shl_0_end) + + movdqa (%eax, %edi), %xmm0 + movdqa 16(%eax, %edi), %xmm1 + sub $32, %ecx + movdqa %xmm0, (%edx, %edi) + movdqa %xmm1, 16(%edx, %edi) + lea 32(%edi), %edi + jb L(shl_0_end) + + movdqa (%eax, %edi), %xmm0 + movdqa 16(%eax, %edi), %xmm1 + sub $32, %ecx + movdqa %xmm0, (%edx, %edi) + movdqa %xmm1, 16(%edx, %edi) + lea 32(%edi), %edi + jb L(shl_0_end) + + movdqa (%eax, %edi), %xmm0 + movdqa 16(%eax, %edi), %xmm1 + sub $32, %ecx + movdqa %xmm0, (%edx, %edi) + movdqa %xmm1, 16(%edx, %edi) + lea 32(%edi), %edi + +L(shl_0_end): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + add %edi, %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY (L(table_48bytes_fwd_align), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_0_gobble): +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + POP (%edi) + lea -128(%ecx), %ecx + jae L(shl_0_gobble_mem_loop) + + .p2align 4 +L(shl_0_gobble_cache_loop): + movdqa (%eax), %xmm0 + movdqa 0x10(%eax), %xmm1 + movdqa 0x20(%eax), %xmm2 + movdqa 0x30(%eax), %xmm3 + movdqa 0x40(%eax), %xmm4 + movdqa 0x50(%eax), %xmm5 + movdqa 0x60(%eax), %xmm6 + movdqa 0x70(%eax), %xmm7 + lea 0x80(%eax), %eax + sub $128, %ecx + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + movdqa %xmm2, 0x20(%edx) + movdqa %xmm3, 0x30(%edx) + movdqa %xmm4, 0x40(%edx) + movdqa %xmm5, 0x50(%edx) + movdqa %xmm6, 0x60(%edx) + movdqa %xmm7, 0x70(%edx) + lea 0x80(%edx), %edx + + jae L(shl_0_gobble_cache_loop) + cmp $-0x40, %ecx + lea 0x80(%ecx), %ecx + jl L(shl_0_cache_less_64bytes) + + movdqa (%eax), %xmm0 + sub $0x40, %ecx + movdqa 0x10(%eax), %xmm1 + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + movdqa 0x20(%eax), %xmm0 + movdqa 0x30(%eax), %xmm1 + add $0x40, %eax + movdqa %xmm0, 0x20(%edx) + movdqa %xmm1, 0x30(%edx) + add $0x40, %edx + +L(shl_0_cache_less_64bytes): + cmp $0x20, %ecx + jb L(shl_0_cache_less_32bytes) + movdqa (%eax), %xmm0 + sub $0x20, %ecx + movdqa 0x10(%eax), %xmm1 + add $0x20, %eax + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + add $0x20, %edx + +L(shl_0_cache_less_32bytes): + cmp $0x10, %ecx + jb L(shl_0_cache_less_16bytes) + sub $0x10, %ecx + movdqa (%eax), %xmm0 + add $0x10, %eax + movdqa %xmm0, (%edx) + add $0x10, %edx + +L(shl_0_cache_less_16bytes): + add %ecx, %edx + add %ecx, %eax + BRANCH_TO_JMPTBL_ENTRY (L(table_48bytes_fwd), %ecx, 4) + + .p2align 4 +L(shl_0_gobble_mem_loop): + prefetcht0 0x1c0(%eax) + prefetcht0 0x280(%eax) + prefetcht0 0x1c0(%edx) + + movdqa (%eax), %xmm0 + movdqa 0x10(%eax), %xmm1 + movdqa 0x20(%eax), %xmm2 + movdqa 0x30(%eax), %xmm3 + movdqa 0x40(%eax), %xmm4 + movdqa 0x50(%eax), %xmm5 + movdqa 0x60(%eax), %xmm6 + movdqa 0x70(%eax), %xmm7 + lea 0x80(%eax), %eax + sub $0x80, %ecx + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + movdqa %xmm2, 0x20(%edx) + movdqa %xmm3, 0x30(%edx) + movdqa %xmm4, 0x40(%edx) + movdqa %xmm5, 0x50(%edx) + movdqa %xmm6, 0x60(%edx) + movdqa %xmm7, 0x70(%edx) + lea 0x80(%edx), %edx + + jae L(shl_0_gobble_mem_loop) + cmp $-0x40, %ecx + lea 0x80(%ecx), %ecx + jl L(shl_0_mem_less_64bytes) + + movdqa (%eax), %xmm0 + sub $0x40, %ecx + movdqa 0x10(%eax), %xmm1 + + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + + movdqa 0x20(%eax), %xmm0 + movdqa 0x30(%eax), %xmm1 + add $0x40, %eax + + movdqa %xmm0, 0x20(%edx) + movdqa %xmm1, 0x30(%edx) + add $0x40, %edx + +L(shl_0_mem_less_64bytes): + cmp $0x20, %ecx + jb L(shl_0_mem_less_32bytes) + movdqa (%eax), %xmm0 + sub $0x20, %ecx + movdqa 0x10(%eax), %xmm1 + add $0x20, %eax + movdqa %xmm0, (%edx) + movdqa %xmm1, 0x10(%edx) + add $0x20, %edx + +L(shl_0_mem_less_32bytes): + cmp $0x10, %ecx + jb L(shl_0_mem_less_16bytes) + sub $0x10, %ecx + movdqa (%eax), %xmm0 + add $0x10, %eax + movdqa %xmm0, (%edx) + add $0x10, %edx + +L(shl_0_mem_less_16bytes): + add %ecx, %edx + add %ecx, %eax + BRANCH_TO_JMPTBL_ENTRY (L(table_48bytes_fwd_align), %ecx, 4) + + .p2align 4 +L(shl_1): +#ifndef USE_AS_MEMMOVE + movaps -1(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -1(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_1_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl1LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 15(%eax), %xmm2 + movaps 31(%eax), %xmm3 + movaps 47(%eax), %xmm4 + movaps 63(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $1, %xmm4, %xmm5 + palignr $1, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $1, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $1, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl1LoopStart) + +L(Shl1LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 15(%eax), %xmm2 + movaps 31(%eax), %xmm3 + palignr $1, %xmm2, %xmm3 + palignr $1, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_1_no_prefetch): + lea -32(%ecx), %ecx + lea -1(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_1_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $1, %xmm2, %xmm3 + palignr $1, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_1_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $1, %xmm2, %xmm3 + palignr $1, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_1_no_prefetch_loop) + +L(sh_1_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 1(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_2): +#ifndef USE_AS_MEMMOVE + movaps -2(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -2(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_2_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl2LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 14(%eax), %xmm2 + movaps 30(%eax), %xmm3 + movaps 46(%eax), %xmm4 + movaps 62(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $2, %xmm4, %xmm5 + palignr $2, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $2, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $2, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl2LoopStart) + +L(Shl2LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 14(%eax), %xmm2 + movaps 30(%eax), %xmm3 + palignr $2, %xmm2, %xmm3 + palignr $2, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_2_no_prefetch): + lea -32(%ecx), %ecx + lea -2(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_2_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $2, %xmm2, %xmm3 + palignr $2, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_2_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $2, %xmm2, %xmm3 + palignr $2, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_2_no_prefetch_loop) + +L(sh_2_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 2(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_3): +#ifndef USE_AS_MEMMOVE + movaps -3(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -3(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_3_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl3LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 13(%eax), %xmm2 + movaps 29(%eax), %xmm3 + movaps 45(%eax), %xmm4 + movaps 61(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $3, %xmm4, %xmm5 + palignr $3, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $3, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $3, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl3LoopStart) + +L(Shl3LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 13(%eax), %xmm2 + movaps 29(%eax), %xmm3 + palignr $3, %xmm2, %xmm3 + palignr $3, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_3_no_prefetch): + lea -32(%ecx), %ecx + lea -3(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_3_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $3, %xmm2, %xmm3 + palignr $3, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jb L(sh_3_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $3, %xmm2, %xmm3 + palignr $3, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jae L(sh_3_no_prefetch_loop) + +L(sh_3_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 3(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_4): +#ifndef USE_AS_MEMMOVE + movaps -4(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -4(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_4_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl4LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 12(%eax), %xmm2 + movaps 28(%eax), %xmm3 + movaps 44(%eax), %xmm4 + movaps 60(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $4, %xmm4, %xmm5 + palignr $4, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $4, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $4, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl4LoopStart) + +L(Shl4LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 12(%eax), %xmm2 + movaps 28(%eax), %xmm3 + palignr $4, %xmm2, %xmm3 + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_4_no_prefetch): + lea -32(%ecx), %ecx + lea -4(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_4_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $4, %xmm2, %xmm3 + palignr $4, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jb L(sh_4_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $4, %xmm2, %xmm3 + palignr $4, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jae L(sh_4_no_prefetch_loop) + +L(sh_4_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 4(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_5): +#ifndef USE_AS_MEMMOVE + movaps -5(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -5(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_5_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl5LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 11(%eax), %xmm2 + movaps 27(%eax), %xmm3 + movaps 43(%eax), %xmm4 + movaps 59(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $5, %xmm4, %xmm5 + palignr $5, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $5, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $5, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl5LoopStart) + +L(Shl5LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 11(%eax), %xmm2 + movaps 27(%eax), %xmm3 + palignr $5, %xmm2, %xmm3 + palignr $5, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_5_no_prefetch): + lea -32(%ecx), %ecx + lea -5(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_5_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $5, %xmm2, %xmm3 + palignr $5, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jb L(sh_5_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $5, %xmm2, %xmm3 + palignr $5, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jae L(sh_5_no_prefetch_loop) + +L(sh_5_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 5(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_6): +#ifndef USE_AS_MEMMOVE + movaps -6(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -6(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_6_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl6LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 10(%eax), %xmm2 + movaps 26(%eax), %xmm3 + movaps 42(%eax), %xmm4 + movaps 58(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $6, %xmm4, %xmm5 + palignr $6, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $6, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $6, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl6LoopStart) + +L(Shl6LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 10(%eax), %xmm2 + movaps 26(%eax), %xmm3 + palignr $6, %xmm2, %xmm3 + palignr $6, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_6_no_prefetch): + lea -32(%ecx), %ecx + lea -6(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_6_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $6, %xmm2, %xmm3 + palignr $6, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jb L(sh_6_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $6, %xmm2, %xmm3 + palignr $6, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + + jae L(sh_6_no_prefetch_loop) + +L(sh_6_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 6(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_7): +#ifndef USE_AS_MEMMOVE + movaps -7(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -7(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_7_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl7LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 9(%eax), %xmm2 + movaps 25(%eax), %xmm3 + movaps 41(%eax), %xmm4 + movaps 57(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $7, %xmm4, %xmm5 + palignr $7, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $7, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $7, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl7LoopStart) + +L(Shl7LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 9(%eax), %xmm2 + movaps 25(%eax), %xmm3 + palignr $7, %xmm2, %xmm3 + palignr $7, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_7_no_prefetch): + lea -32(%ecx), %ecx + lea -7(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_7_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $7, %xmm2, %xmm3 + palignr $7, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_7_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $7, %xmm2, %xmm3 + palignr $7, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_7_no_prefetch_loop) + +L(sh_7_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 7(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_8): +#ifndef USE_AS_MEMMOVE + movaps -8(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -8(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_8_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl8LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 8(%eax), %xmm2 + movaps 24(%eax), %xmm3 + movaps 40(%eax), %xmm4 + movaps 56(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $8, %xmm4, %xmm5 + palignr $8, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $8, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $8, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl8LoopStart) + +L(LoopLeave8): + add $32, %ecx + jle L(shl_end_0) + + movaps 8(%eax), %xmm2 + movaps 24(%eax), %xmm3 + palignr $8, %xmm2, %xmm3 + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_8_no_prefetch): + lea -32(%ecx), %ecx + lea -8(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_8_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $8, %xmm2, %xmm3 + palignr $8, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_8_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $8, %xmm2, %xmm3 + palignr $8, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_8_no_prefetch_loop) + +L(sh_8_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 8(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_9): +#ifndef USE_AS_MEMMOVE + movaps -9(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -9(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_9_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl9LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 7(%eax), %xmm2 + movaps 23(%eax), %xmm3 + movaps 39(%eax), %xmm4 + movaps 55(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $9, %xmm4, %xmm5 + palignr $9, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $9, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $9, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl9LoopStart) + +L(Shl9LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 7(%eax), %xmm2 + movaps 23(%eax), %xmm3 + palignr $9, %xmm2, %xmm3 + palignr $9, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_9_no_prefetch): + lea -32(%ecx), %ecx + lea -9(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_9_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $9, %xmm2, %xmm3 + palignr $9, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_9_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $9, %xmm2, %xmm3 + palignr $9, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_9_no_prefetch_loop) + +L(sh_9_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 9(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_10): +#ifndef USE_AS_MEMMOVE + movaps -10(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -10(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_10_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl10LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 6(%eax), %xmm2 + movaps 22(%eax), %xmm3 + movaps 38(%eax), %xmm4 + movaps 54(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $10, %xmm4, %xmm5 + palignr $10, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $10, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $10, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl10LoopStart) + +L(Shl10LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 6(%eax), %xmm2 + movaps 22(%eax), %xmm3 + palignr $10, %xmm2, %xmm3 + palignr $10, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_10_no_prefetch): + lea -32(%ecx), %ecx + lea -10(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_10_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $10, %xmm2, %xmm3 + palignr $10, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_10_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $10, %xmm2, %xmm3 + palignr $10, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_10_no_prefetch_loop) + +L(sh_10_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 10(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_11): +#ifndef USE_AS_MEMMOVE + movaps -11(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -11(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_11_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl11LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 5(%eax), %xmm2 + movaps 21(%eax), %xmm3 + movaps 37(%eax), %xmm4 + movaps 53(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $11, %xmm4, %xmm5 + palignr $11, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $11, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $11, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl11LoopStart) + +L(Shl11LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 5(%eax), %xmm2 + movaps 21(%eax), %xmm3 + palignr $11, %xmm2, %xmm3 + palignr $11, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_11_no_prefetch): + lea -32(%ecx), %ecx + lea -11(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_11_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $11, %xmm2, %xmm3 + palignr $11, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_11_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $11, %xmm2, %xmm3 + palignr $11, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_11_no_prefetch_loop) + +L(sh_11_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 11(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_12): +#ifndef USE_AS_MEMMOVE + movaps -12(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -12(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_12_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl12LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 4(%eax), %xmm2 + movaps 20(%eax), %xmm3 + movaps 36(%eax), %xmm4 + movaps 52(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $12, %xmm4, %xmm5 + palignr $12, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $12, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $12, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl12LoopStart) + +L(Shl12LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 4(%eax), %xmm2 + movaps 20(%eax), %xmm3 + palignr $12, %xmm2, %xmm3 + palignr $12, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_12_no_prefetch): + lea -32(%ecx), %ecx + lea -12(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_12_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $12, %xmm2, %xmm3 + palignr $12, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_12_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $12, %xmm2, %xmm3 + palignr $12, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_12_no_prefetch_loop) + +L(sh_12_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 12(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_13): +#ifndef USE_AS_MEMMOVE + movaps -13(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -13(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_13_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl13LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 3(%eax), %xmm2 + movaps 19(%eax), %xmm3 + movaps 35(%eax), %xmm4 + movaps 51(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $13, %xmm4, %xmm5 + palignr $13, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $13, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $13, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl13LoopStart) + +L(Shl13LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 3(%eax), %xmm2 + movaps 19(%eax), %xmm3 + palignr $13, %xmm2, %xmm3 + palignr $13, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_13_no_prefetch): + lea -32(%ecx), %ecx + lea -13(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_13_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $13, %xmm2, %xmm3 + palignr $13, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_13_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $13, %xmm2, %xmm3 + palignr $13, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_13_no_prefetch_loop) + +L(sh_13_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 13(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_14): +#ifndef USE_AS_MEMMOVE + movaps -14(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -14(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_14_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl14LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 2(%eax), %xmm2 + movaps 18(%eax), %xmm3 + movaps 34(%eax), %xmm4 + movaps 50(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $14, %xmm4, %xmm5 + palignr $14, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $14, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $14, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl14LoopStart) + +L(Shl14LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 2(%eax), %xmm2 + movaps 18(%eax), %xmm3 + palignr $14, %xmm2, %xmm3 + palignr $14, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_14_no_prefetch): + lea -32(%ecx), %ecx + lea -14(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_14_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $14, %xmm2, %xmm3 + palignr $14, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_14_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $14, %xmm2, %xmm3 + palignr $14, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_14_no_prefetch_loop) + +L(sh_14_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 14(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_15): +#ifndef USE_AS_MEMMOVE + movaps -15(%eax), %xmm1 +#else + movl DEST+4(%esp), %edi + movaps -15(%eax), %xmm1 + movdqu %xmm0, (%edi) +#endif +#ifdef DATA_CACHE_SIZE_HALF + cmp $DATA_CACHE_SIZE_HALF, %ecx +#else +# if (defined SHARED || defined __PIC__) + SETUP_PIC_REG(bx) + add $_GLOBAL_OFFSET_TABLE_, %ebx + cmp __x86_data_cache_size_half@GOTOFF(%ebx), %ecx +# else + cmp __x86_data_cache_size_half, %ecx +# endif +#endif + jb L(sh_15_no_prefetch) + + lea -64(%ecx), %ecx + + .p2align 4 +L(Shl15LoopStart): + prefetcht0 0x1c0(%eax) + prefetcht0 0x1c0(%edx) + movaps 1(%eax), %xmm2 + movaps 17(%eax), %xmm3 + movaps 33(%eax), %xmm4 + movaps 49(%eax), %xmm5 + movaps %xmm5, %xmm7 + palignr $15, %xmm4, %xmm5 + palignr $15, %xmm3, %xmm4 + movaps %xmm5, 48(%edx) + palignr $15, %xmm2, %xmm3 + lea 64(%eax), %eax + palignr $15, %xmm1, %xmm2 + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm7, %xmm1 + movaps %xmm2, (%edx) + lea 64(%edx), %edx + sub $64, %ecx + ja L(Shl15LoopStart) + +L(Shl15LoopLeave): + add $32, %ecx + jle L(shl_end_0) + + movaps 1(%eax), %xmm2 + movaps 17(%eax), %xmm3 + palignr $15, %xmm2, %xmm3 + palignr $15, %xmm1, %xmm2 + + movaps %xmm2, (%edx) + movaps %xmm3, 16(%edx) + lea 32(%edx, %ecx), %edx + lea 32(%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(sh_15_no_prefetch): + lea -32(%ecx), %ecx + lea -15(%eax), %eax + xor %edi, %edi + + .p2align 4 +L(sh_15_no_prefetch_loop): + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm4 + palignr $15, %xmm2, %xmm3 + palignr $15, %xmm1, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jb L(sh_15_end_no_prefetch_loop) + + movdqa 16(%eax, %edi), %xmm2 + sub $32, %ecx + movdqa 32(%eax, %edi), %xmm3 + movdqa %xmm3, %xmm1 + palignr $15, %xmm2, %xmm3 + palignr $15, %xmm4, %xmm2 + lea 32(%edi), %edi + movdqa %xmm2, -32(%edx, %edi) + movdqa %xmm3, -16(%edx, %edi) + jae L(sh_15_no_prefetch_loop) + +L(sh_15_end_no_prefetch_loop): + lea 32(%ecx), %ecx + add %ecx, %edi + add %edi, %edx + lea 15(%edi, %eax), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(shl_end_0): + lea 32(%ecx), %ecx + lea (%edx, %ecx), %edx + lea (%eax, %ecx), %eax + POP (%edi) + BRANCH_TO_JMPTBL_ENTRY(L(table_48bytes_fwd), %ecx, 4) + + .p2align 4 +L(fwd_write_44bytes): + movq -44(%eax), %xmm0 + movq %xmm0, -44(%edx) +L(fwd_write_36bytes): + movq -36(%eax), %xmm0 + movq %xmm0, -36(%edx) +L(fwd_write_28bytes): + movq -28(%eax), %xmm0 + movq %xmm0, -28(%edx) +L(fwd_write_20bytes): + movq -20(%eax), %xmm0 + movq %xmm0, -20(%edx) +L(fwd_write_12bytes): + movq -12(%eax), %xmm0 + movq %xmm0, -12(%edx) +L(fwd_write_4bytes): + movl -4(%eax), %ecx + movl %ecx, -4(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_40bytes): + movq -40(%eax), %xmm0 + movq %xmm0, -40(%edx) +L(fwd_write_32bytes): + movq -32(%eax), %xmm0 + movq %xmm0, -32(%edx) +L(fwd_write_24bytes): + movq -24(%eax), %xmm0 + movq %xmm0, -24(%edx) +L(fwd_write_16bytes): + movq -16(%eax), %xmm0 + movq %xmm0, -16(%edx) +L(fwd_write_8bytes): + movq -8(%eax), %xmm0 + movq %xmm0, -8(%edx) +L(fwd_write_0bytes): +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_5bytes): + movl -5(%eax), %ecx + movl -4(%eax), %eax + movl %ecx, -5(%edx) + movl %eax, -4(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_45bytes): + movq -45(%eax), %xmm0 + movq %xmm0, -45(%edx) +L(fwd_write_37bytes): + movq -37(%eax), %xmm0 + movq %xmm0, -37(%edx) +L(fwd_write_29bytes): + movq -29(%eax), %xmm0 + movq %xmm0, -29(%edx) +L(fwd_write_21bytes): + movq -21(%eax), %xmm0 + movq %xmm0, -21(%edx) +L(fwd_write_13bytes): + movq -13(%eax), %xmm0 + movq %xmm0, -13(%edx) + movl -5(%eax), %ecx + movl %ecx, -5(%edx) + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_41bytes): + movq -41(%eax), %xmm0 + movq %xmm0, -41(%edx) +L(fwd_write_33bytes): + movq -33(%eax), %xmm0 + movq %xmm0, -33(%edx) +L(fwd_write_25bytes): + movq -25(%eax), %xmm0 + movq %xmm0, -25(%edx) +L(fwd_write_17bytes): + movq -17(%eax), %xmm0 + movq %xmm0, -17(%edx) +L(fwd_write_9bytes): + movq -9(%eax), %xmm0 + movq %xmm0, -9(%edx) +L(fwd_write_1bytes): + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_46bytes): + movq -46(%eax), %xmm0 + movq %xmm0, -46(%edx) +L(fwd_write_38bytes): + movq -38(%eax), %xmm0 + movq %xmm0, -38(%edx) +L(fwd_write_30bytes): + movq -30(%eax), %xmm0 + movq %xmm0, -30(%edx) +L(fwd_write_22bytes): + movq -22(%eax), %xmm0 + movq %xmm0, -22(%edx) +L(fwd_write_14bytes): + movq -14(%eax), %xmm0 + movq %xmm0, -14(%edx) +L(fwd_write_6bytes): + movl -6(%eax), %ecx + movl %ecx, -6(%edx) + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_42bytes): + movq -42(%eax), %xmm0 + movq %xmm0, -42(%edx) +L(fwd_write_34bytes): + movq -34(%eax), %xmm0 + movq %xmm0, -34(%edx) +L(fwd_write_26bytes): + movq -26(%eax), %xmm0 + movq %xmm0, -26(%edx) +L(fwd_write_18bytes): + movq -18(%eax), %xmm0 + movq %xmm0, -18(%edx) +L(fwd_write_10bytes): + movq -10(%eax), %xmm0 + movq %xmm0, -10(%edx) +L(fwd_write_2bytes): + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_47bytes): + movq -47(%eax), %xmm0 + movq %xmm0, -47(%edx) +L(fwd_write_39bytes): + movq -39(%eax), %xmm0 + movq %xmm0, -39(%edx) +L(fwd_write_31bytes): + movq -31(%eax), %xmm0 + movq %xmm0, -31(%edx) +L(fwd_write_23bytes): + movq -23(%eax), %xmm0 + movq %xmm0, -23(%edx) +L(fwd_write_15bytes): + movq -15(%eax), %xmm0 + movq %xmm0, -15(%edx) +L(fwd_write_7bytes): + movl -7(%eax), %ecx + movl %ecx, -7(%edx) + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_43bytes): + movq -43(%eax), %xmm0 + movq %xmm0, -43(%edx) +L(fwd_write_35bytes): + movq -35(%eax), %xmm0 + movq %xmm0, -35(%edx) +L(fwd_write_27bytes): + movq -27(%eax), %xmm0 + movq %xmm0, -27(%edx) +L(fwd_write_19bytes): + movq -19(%eax), %xmm0 + movq %xmm0, -19(%edx) +L(fwd_write_11bytes): + movq -11(%eax), %xmm0 + movq %xmm0, -11(%edx) +L(fwd_write_3bytes): + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_40bytes_align): + movdqa -40(%eax), %xmm0 + movdqa %xmm0, -40(%edx) +L(fwd_write_24bytes_align): + movdqa -24(%eax), %xmm0 + movdqa %xmm0, -24(%edx) +L(fwd_write_8bytes_align): + movq -8(%eax), %xmm0 + movq %xmm0, -8(%edx) +L(fwd_write_0bytes_align): +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_32bytes_align): + movdqa -32(%eax), %xmm0 + movdqa %xmm0, -32(%edx) +L(fwd_write_16bytes_align): + movdqa -16(%eax), %xmm0 + movdqa %xmm0, -16(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_5bytes_align): + movl -5(%eax), %ecx + movl -4(%eax), %eax + movl %ecx, -5(%edx) + movl %eax, -4(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_45bytes_align): + movdqa -45(%eax), %xmm0 + movdqa %xmm0, -45(%edx) +L(fwd_write_29bytes_align): + movdqa -29(%eax), %xmm0 + movdqa %xmm0, -29(%edx) +L(fwd_write_13bytes_align): + movq -13(%eax), %xmm0 + movq %xmm0, -13(%edx) + movl -5(%eax), %ecx + movl %ecx, -5(%edx) + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_37bytes_align): + movdqa -37(%eax), %xmm0 + movdqa %xmm0, -37(%edx) +L(fwd_write_21bytes_align): + movdqa -21(%eax), %xmm0 + movdqa %xmm0, -21(%edx) + movl -5(%eax), %ecx + movl %ecx, -5(%edx) + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_41bytes_align): + movdqa -41(%eax), %xmm0 + movdqa %xmm0, -41(%edx) +L(fwd_write_25bytes_align): + movdqa -25(%eax), %xmm0 + movdqa %xmm0, -25(%edx) +L(fwd_write_9bytes_align): + movq -9(%eax), %xmm0 + movq %xmm0, -9(%edx) +L(fwd_write_1bytes_align): + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_33bytes_align): + movdqa -33(%eax), %xmm0 + movdqa %xmm0, -33(%edx) +L(fwd_write_17bytes_align): + movdqa -17(%eax), %xmm0 + movdqa %xmm0, -17(%edx) + movzbl -1(%eax), %ecx + movb %cl, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_46bytes_align): + movdqa -46(%eax), %xmm0 + movdqa %xmm0, -46(%edx) +L(fwd_write_30bytes_align): + movdqa -30(%eax), %xmm0 + movdqa %xmm0, -30(%edx) +L(fwd_write_14bytes_align): + movq -14(%eax), %xmm0 + movq %xmm0, -14(%edx) +L(fwd_write_6bytes_align): + movl -6(%eax), %ecx + movl %ecx, -6(%edx) + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_38bytes_align): + movdqa -38(%eax), %xmm0 + movdqa %xmm0, -38(%edx) +L(fwd_write_22bytes_align): + movdqa -22(%eax), %xmm0 + movdqa %xmm0, -22(%edx) + movl -6(%eax), %ecx + movl %ecx, -6(%edx) + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_42bytes_align): + movdqa -42(%eax), %xmm0 + movdqa %xmm0, -42(%edx) +L(fwd_write_26bytes_align): + movdqa -26(%eax), %xmm0 + movdqa %xmm0, -26(%edx) +L(fwd_write_10bytes_align): + movq -10(%eax), %xmm0 + movq %xmm0, -10(%edx) +L(fwd_write_2bytes_align): + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_34bytes_align): + movdqa -34(%eax), %xmm0 + movdqa %xmm0, -34(%edx) +L(fwd_write_18bytes_align): + movdqa -18(%eax), %xmm0 + movdqa %xmm0, -18(%edx) + movzwl -2(%eax), %ecx + movw %cx, -2(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_47bytes_align): + movdqa -47(%eax), %xmm0 + movdqa %xmm0, -47(%edx) +L(fwd_write_31bytes_align): + movdqa -31(%eax), %xmm0 + movdqa %xmm0, -31(%edx) +L(fwd_write_15bytes_align): + movq -15(%eax), %xmm0 + movq %xmm0, -15(%edx) +L(fwd_write_7bytes_align): + movl -7(%eax), %ecx + movl %ecx, -7(%edx) + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_39bytes_align): + movdqa -39(%eax), %xmm0 + movdqa %xmm0, -39(%edx) +L(fwd_write_23bytes_align): + movdqa -23(%eax), %xmm0 + movdqa %xmm0, -23(%edx) + movl -7(%eax), %ecx + movl %ecx, -7(%edx) + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_43bytes_align): + movdqa -43(%eax), %xmm0 + movdqa %xmm0, -43(%edx) +L(fwd_write_27bytes_align): + movdqa -27(%eax), %xmm0 + movdqa %xmm0, -27(%edx) +L(fwd_write_11bytes_align): + movq -11(%eax), %xmm0 + movq %xmm0, -11(%edx) +L(fwd_write_3bytes_align): + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_35bytes_align): + movdqa -35(%eax), %xmm0 + movdqa %xmm0, -35(%edx) +L(fwd_write_19bytes_align): + movdqa -19(%eax), %xmm0 + movdqa %xmm0, -19(%edx) + movzwl -3(%eax), %ecx + movzbl -1(%eax), %eax + movw %cx, -3(%edx) + movb %al, -1(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_44bytes_align): + movdqa -44(%eax), %xmm0 + movdqa %xmm0, -44(%edx) +L(fwd_write_28bytes_align): + movdqa -28(%eax), %xmm0 + movdqa %xmm0, -28(%edx) +L(fwd_write_12bytes_align): + movq -12(%eax), %xmm0 + movq %xmm0, -12(%edx) +L(fwd_write_4bytes_align): + movl -4(%eax), %ecx + movl %ecx, -4(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN + + .p2align 4 +L(fwd_write_36bytes_align): + movdqa -36(%eax), %xmm0 + movdqa %xmm0, -36(%edx) +L(fwd_write_20bytes_align): + movdqa -20(%eax), %xmm0 + movdqa %xmm0, -20(%edx) + movl -4(%eax), %ecx + movl %ecx, -4(%edx) +#ifdef USE_AS_MEMPCPY + movl %edx, %eax +#else + movl DEST(%esp), %eax +#endif + RETURN_END + + CFI_PUSH (%edi) + + .p2align 4 +L(large_page): + movdqu (%eax), %xmm1 +#ifdef USE_AS_MEMMOVE + movl DEST+4(%esp), %edi + movdqu %xmm0, (%edi) +#endif + lea 16(%eax), %eax + movntdq %xmm1, (%edx) + lea 16(%edx), %edx + lea -0x90(%ecx), %ecx + POP (%edi) + + .p2align 4 +L(large_page_loop): + movdqu (%eax), %xmm0 + movdqu 0x10(%eax), %xmm1 + movdqu 0x20(%eax), %xmm2 + movdqu 0x30(%eax), %xmm3 + movdqu 0x40(%eax), %xmm4 + movdqu 0x50(%eax), %xmm5 + movdqu 0x60(%eax), %xmm6 + movdqu 0x70(%eax), %xmm7 + lea 0x80(%eax), %eax + + sub $0x80, %ecx + movntdq %xmm0, (%edx) + movntdq %xmm1, 0x10(%edx) + movntdq %xmm2, 0x20(%edx) + movntdq %xmm3, 0x30(%edx) + movntdq %xmm4, 0x40(%edx) + movntdq %xmm5, 0x50(%edx) + movntdq %xmm6, 0x60(%edx) + movntdq %xmm7, 0x70(%edx) + lea 0x80(%edx), %edx + jae L(large_page_loop) + cmp $-0x40, %ecx + lea 0x80(%ecx), %ecx + jl L(large_page_less_64bytes) + + movdqu (%eax), %xmm0 + movdqu 0x10(%eax), %xmm1 + movdqu 0x20(%eax), %xmm2 + movdqu 0x30(%eax), %xmm3 + lea 0x40(%eax), %eax + + movntdq %xmm0, (%edx) + movntdq %xmm1, 0x10(%edx) + movntdq %xmm2, 0x20(%edx) + movntdq %xmm3, 0x30(%edx) + lea 0x40(%edx), %edx + sub $0x40, %ecx +L(large_page_less_64bytes): + cmp $32, %ecx + jb L(large_page_less_32bytes) + movdqu (%eax), %xmm0 + movdqu 0x10(%eax), %xmm1 + lea 0x20(%eax), %eax + movntdq %xmm0, (%edx) + movntdq %xmm1, 0x10(%edx) + lea 0x20(%edx), %edx + sub $0x20, %ecx +L(large_page_less_32bytes): + add %ecx, %edx + add %ecx, %eax + sfence + BRANCH_TO_JMPTBL_ENTRY (L(table_48bytes_fwd), %ecx, 4) + + .p2align 4 +L(bk_write_44bytes): + movq 36(%eax), %xmm0 + movq %xmm0, 36(%edx) +L(bk_write_36bytes): + movq 28(%eax), %xmm0 + movq %xmm0, 28(%edx) +L(bk_write_28bytes): + movq 20(%eax), %xmm0 + movq %xmm0, 20(%edx) +L(bk_write_20bytes): + movq 12(%eax), %xmm0 + movq %xmm0, 12(%edx) +L(bk_write_12bytes): + movq 4(%eax), %xmm0 + movq %xmm0, 4(%edx) +L(bk_write_4bytes): + movl (%eax), %ecx + movl %ecx, (%edx) +L(bk_write_0bytes): + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_40bytes): + movq 32(%eax), %xmm0 + movq %xmm0, 32(%edx) +L(bk_write_32bytes): + movq 24(%eax), %xmm0 + movq %xmm0, 24(%edx) +L(bk_write_24bytes): + movq 16(%eax), %xmm0 + movq %xmm0, 16(%edx) +L(bk_write_16bytes): + movq 8(%eax), %xmm0 + movq %xmm0, 8(%edx) +L(bk_write_8bytes): + movq (%eax), %xmm0 + movq %xmm0, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_45bytes): + movq 37(%eax), %xmm0 + movq %xmm0, 37(%edx) +L(bk_write_37bytes): + movq 29(%eax), %xmm0 + movq %xmm0, 29(%edx) +L(bk_write_29bytes): + movq 21(%eax), %xmm0 + movq %xmm0, 21(%edx) +L(bk_write_21bytes): + movq 13(%eax), %xmm0 + movq %xmm0, 13(%edx) +L(bk_write_13bytes): + movq 5(%eax), %xmm0 + movq %xmm0, 5(%edx) +L(bk_write_5bytes): + movl 1(%eax), %ecx + movl %ecx, 1(%edx) +L(bk_write_1bytes): + movzbl (%eax), %ecx + movb %cl, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_41bytes): + movq 33(%eax), %xmm0 + movq %xmm0, 33(%edx) +L(bk_write_33bytes): + movq 25(%eax), %xmm0 + movq %xmm0, 25(%edx) +L(bk_write_25bytes): + movq 17(%eax), %xmm0 + movq %xmm0, 17(%edx) +L(bk_write_17bytes): + movq 9(%eax), %xmm0 + movq %xmm0, 9(%edx) +L(bk_write_9bytes): + movq 1(%eax), %xmm0 + movq %xmm0, 1(%edx) + movzbl (%eax), %ecx + movb %cl, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_46bytes): + movq 38(%eax), %xmm0 + movq %xmm0, 38(%edx) +L(bk_write_38bytes): + movq 30(%eax), %xmm0 + movq %xmm0, 30(%edx) +L(bk_write_30bytes): + movq 22(%eax), %xmm0 + movq %xmm0, 22(%edx) +L(bk_write_22bytes): + movq 14(%eax), %xmm0 + movq %xmm0, 14(%edx) +L(bk_write_14bytes): + movq 6(%eax), %xmm0 + movq %xmm0, 6(%edx) +L(bk_write_6bytes): + movl 2(%eax), %ecx + movl %ecx, 2(%edx) + movzwl (%eax), %ecx + movw %cx, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_42bytes): + movq 34(%eax), %xmm0 + movq %xmm0, 34(%edx) +L(bk_write_34bytes): + movq 26(%eax), %xmm0 + movq %xmm0, 26(%edx) +L(bk_write_26bytes): + movq 18(%eax), %xmm0 + movq %xmm0, 18(%edx) +L(bk_write_18bytes): + movq 10(%eax), %xmm0 + movq %xmm0, 10(%edx) +L(bk_write_10bytes): + movq 2(%eax), %xmm0 + movq %xmm0, 2(%edx) +L(bk_write_2bytes): + movzwl (%eax), %ecx + movw %cx, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_47bytes): + movq 39(%eax), %xmm0 + movq %xmm0, 39(%edx) +L(bk_write_39bytes): + movq 31(%eax), %xmm0 + movq %xmm0, 31(%edx) +L(bk_write_31bytes): + movq 23(%eax), %xmm0 + movq %xmm0, 23(%edx) +L(bk_write_23bytes): + movq 15(%eax), %xmm0 + movq %xmm0, 15(%edx) +L(bk_write_15bytes): + movq 7(%eax), %xmm0 + movq %xmm0, 7(%edx) +L(bk_write_7bytes): + movl 3(%eax), %ecx + movl %ecx, 3(%edx) + movzwl 1(%eax), %ecx + movw %cx, 1(%edx) + movzbl (%eax), %eax + movb %al, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN + + .p2align 4 +L(bk_write_43bytes): + movq 35(%eax), %xmm0 + movq %xmm0, 35(%edx) +L(bk_write_35bytes): + movq 27(%eax), %xmm0 + movq %xmm0, 27(%edx) +L(bk_write_27bytes): + movq 19(%eax), %xmm0 + movq %xmm0, 19(%edx) +L(bk_write_19bytes): + movq 11(%eax), %xmm0 + movq %xmm0, 11(%edx) +L(bk_write_11bytes): + movq 3(%eax), %xmm0 + movq %xmm0, 3(%edx) +L(bk_write_3bytes): + movzwl 1(%eax), %ecx + movw %cx, 1(%edx) + movzbl (%eax), %eax + movb %al, (%edx) + movl DEST(%esp), %eax +#ifdef USE_AS_MEMPCPY + movl LEN(%esp), %ecx + add %ecx, %eax +#endif + RETURN_END + + + .pushsection .rodata.ssse3,"a",@progbits + .p2align 2 +L(table_48bytes_fwd): + .int JMPTBL (L(fwd_write_0bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_1bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_2bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_3bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_4bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_5bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_6bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_7bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_8bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_9bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_10bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_11bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_12bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_13bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_14bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_15bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_16bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_17bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_18bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_19bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_20bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_21bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_22bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_23bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_24bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_25bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_26bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_27bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_28bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_29bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_30bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_31bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_32bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_33bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_34bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_35bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_36bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_37bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_38bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_39bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_40bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_41bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_42bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_43bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_44bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_45bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_46bytes), L(table_48bytes_fwd)) + .int JMPTBL (L(fwd_write_47bytes), L(table_48bytes_fwd)) + + .p2align 2 +L(table_48bytes_fwd_align): + .int JMPTBL (L(fwd_write_0bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_1bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_2bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_3bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_4bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_5bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_6bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_7bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_8bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_9bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_10bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_11bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_12bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_13bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_14bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_15bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_16bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_17bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_18bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_19bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_20bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_21bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_22bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_23bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_24bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_25bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_26bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_27bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_28bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_29bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_30bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_31bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_32bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_33bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_34bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_35bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_36bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_37bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_38bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_39bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_40bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_41bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_42bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_43bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_44bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_45bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_46bytes_align), L(table_48bytes_fwd_align)) + .int JMPTBL (L(fwd_write_47bytes_align), L(table_48bytes_fwd_align)) + + .p2align 2 +L(shl_table): + .int JMPTBL (L(shl_0), L(shl_table)) + .int JMPTBL (L(shl_1), L(shl_table)) + .int JMPTBL (L(shl_2), L(shl_table)) + .int JMPTBL (L(shl_3), L(shl_table)) + .int JMPTBL (L(shl_4), L(shl_table)) + .int JMPTBL (L(shl_5), L(shl_table)) + .int JMPTBL (L(shl_6), L(shl_table)) + .int JMPTBL (L(shl_7), L(shl_table)) + .int JMPTBL (L(shl_8), L(shl_table)) + .int JMPTBL (L(shl_9), L(shl_table)) + .int JMPTBL (L(shl_10), L(shl_table)) + .int JMPTBL (L(shl_11), L(shl_table)) + .int JMPTBL (L(shl_12), L(shl_table)) + .int JMPTBL (L(shl_13), L(shl_table)) + .int JMPTBL (L(shl_14), L(shl_table)) + .int JMPTBL (L(shl_15), L(shl_table)) + + .p2align 2 +L(table_48_bytes_bwd): + .int JMPTBL (L(bk_write_0bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_1bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_2bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_3bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_4bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_5bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_6bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_7bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_8bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_9bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_10bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_11bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_12bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_13bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_14bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_15bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_16bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_17bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_18bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_19bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_20bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_21bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_22bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_23bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_24bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_25bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_26bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_27bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_28bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_29bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_30bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_31bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_32bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_33bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_34bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_35bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_36bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_37bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_38bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_39bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_40bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_41bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_42bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_43bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_44bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_45bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_46bytes), L(table_48_bytes_bwd)) + .int JMPTBL (L(bk_write_47bytes), L(table_48_bytes_bwd)) + + .popsection + +#ifdef USE_AS_MEMMOVE + .p2align 4 +L(copy_backward): + PUSH (%edi) + movl %eax, %edi + lea (%ecx,%edx,1),%edx + lea (%ecx,%edi,1),%edi + testl $0x3, %edx + jnz L(bk_align) + +L(bk_aligned_4): + cmp $64, %ecx + jae L(bk_write_more64bytes) + +L(bk_write_64bytesless): + cmp $32, %ecx + jb L(bk_write_less32bytes) + +L(bk_write_more32bytes): + /* Copy 32 bytes at a time. */ + sub $32, %ecx + movq -8(%edi), %xmm0 + movq %xmm0, -8(%edx) + movq -16(%edi), %xmm0 + movq %xmm0, -16(%edx) + movq -24(%edi), %xmm0 + movq %xmm0, -24(%edx) + movq -32(%edi), %xmm0 + movq %xmm0, -32(%edx) + sub $32, %edx + sub $32, %edi + +L(bk_write_less32bytes): + movl %edi, %eax + sub %ecx, %edx + sub %ecx, %eax + POP (%edi) +L(bk_write_less32bytes_2): + BRANCH_TO_JMPTBL_ENTRY (L(table_48_bytes_bwd), %ecx, 4) + + CFI_PUSH (%edi) + + .p2align 4 +L(bk_align): + cmp $8, %ecx + jbe L(bk_write_less32bytes) + testl $1, %edx + /* We get here only if (EDX & 3 ) != 0 so if (EDX & 1) ==0, + then (EDX & 2) must be != 0. */ + jz L(bk_got2) + sub $1, %edi + sub $1, %ecx + sub $1, %edx + movzbl (%edi), %eax + movb %al, (%edx) + + testl $2, %edx + jz L(bk_aligned_4) + +L(bk_got2): + sub $2, %edi + sub $2, %ecx + sub $2, %edx + movzwl (%edi), %eax + movw %ax, (%edx) + jmp L(bk_aligned_4) + + .p2align 4 +L(bk_write_more64bytes): + /* Check alignment of last byte. */ + testl $15, %edx + jz L(bk_ssse3_cpy_pre) + +/* EDX is aligned 4 bytes, but not 16 bytes. */ +L(bk_ssse3_align): + sub $4, %edi + sub $4, %ecx + sub $4, %edx + movl (%edi), %eax + movl %eax, (%edx) + + testl $15, %edx + jz L(bk_ssse3_cpy_pre) + + sub $4, %edi + sub $4, %ecx + sub $4, %edx + movl (%edi), %eax + movl %eax, (%edx) + + testl $15, %edx + jz L(bk_ssse3_cpy_pre) + + sub $4, %edi + sub $4, %ecx + sub $4, %edx + movl (%edi), %eax + movl %eax, (%edx) + +L(bk_ssse3_cpy_pre): + cmp $64, %ecx + jb L(bk_write_more32bytes) + + .p2align 4 +L(bk_ssse3_cpy): + sub $64, %edi + sub $64, %ecx + sub $64, %edx + movdqu 0x30(%edi), %xmm3 + movdqa %xmm3, 0x30(%edx) + movdqu 0x20(%edi), %xmm2 + movdqa %xmm2, 0x20(%edx) + movdqu 0x10(%edi), %xmm1 + movdqa %xmm1, 0x10(%edx) + movdqu (%edi), %xmm0 + movdqa %xmm0, (%edx) + cmp $64, %ecx + jae L(bk_ssse3_cpy) + jmp L(bk_write_64bytesless) + +#endif + +END (MEMCPY)
diff --git a/libc/arch-x86/atom/string/ssse3-memmove-atom.S b/libc/arch-x86/atom/string/ssse3-memmove-atom.S new file mode 100644 index 0000000..be85596 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-memmove-atom.S
@@ -0,0 +1,34 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#define MEMCPY memmove +#define USE_AS_MEMMOVE +#include "ssse3-memcpy-atom.S"
diff --git a/libc/arch-x86/atom/string/ssse3-strcat-atom.S b/libc/arch-x86/atom/string/ssse3-strcat-atom.S new file mode 100644 index 0000000..d9b6129 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strcat-atom.S
@@ -0,0 +1,620 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef cfi_remember_state +# define cfi_remember_state .cfi_remember_state +#endif + +#ifndef cfi_restore_state +# define cfi_restore_state .cfi_restore_state +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#ifndef STRCAT +# define STRCAT strcat +#endif + +#define PARMS 4 +#define STR1 PARMS+4 +#define STR2 STR1+4 + +#ifdef USE_AS_STRNCAT +# define LEN STR2+8 +#endif + +#define USE_AS_STRCAT + + .section .text.ssse3,"ax",@progbits +ENTRY (STRCAT) + PUSH (%edi) + mov STR1(%esp), %edi + mov %edi, %edx + +#define RETURN jmp L(StrcpyAtom) +#include "sse2-strlen-atom.S" + +L(StrcpyAtom): + mov STR2(%esp), %ecx + lea (%edi, %eax), %edx +#ifdef USE_AS_STRNCAT + PUSH (%ebx) + mov LEN(%esp), %ebx + test %ebx, %ebx + jz L(StrncatExit0) + cmp $8, %ebx + jbe L(StrncpyExit8Bytes) +#endif + cmpb $0, (%ecx) + jz L(Exit1) + cmpb $0, 1(%ecx) + jz L(Exit2) + cmpb $0, 2(%ecx) + jz L(Exit3) + cmpb $0, 3(%ecx) + jz L(Exit4) + cmpb $0, 4(%ecx) + jz L(Exit5) + cmpb $0, 5(%ecx) + jz L(Exit6) + cmpb $0, 6(%ecx) + jz L(Exit7) + cmpb $0, 7(%ecx) + jz L(Exit8) + cmpb $0, 8(%ecx) + jz L(Exit9) +#ifdef USE_AS_STRNCAT + cmp $16, %ebx + jb L(StrncpyExit15Bytes) +#endif + cmpb $0, 9(%ecx) + jz L(Exit10) + cmpb $0, 10(%ecx) + jz L(Exit11) + cmpb $0, 11(%ecx) + jz L(Exit12) + cmpb $0, 12(%ecx) + jz L(Exit13) + cmpb $0, 13(%ecx) + jz L(Exit14) + cmpb $0, 14(%ecx) + jz L(Exit15) + cmpb $0, 15(%ecx) + jz L(Exit16) +#ifdef USE_AS_STRNCAT + cmp $16, %ebx + je L(StrncatExit16) + +# define RETURN1 POP (%ebx); POP (%edi); ret; \ + CFI_PUSH (%ebx); CFI_PUSH (%edi) +# define USE_AS_STRNCPY +#else +# define RETURN1 POP(%edi); ret; CFI_PUSH(%edi) +#endif +#include "ssse3-strcpy-atom.S" + + .p2align 4 +L(CopyFrom1To16Bytes): + add %esi, %edx + add %esi, %ecx + + POP (%esi) + test %al, %al + jz L(ExitHigh) + test $0x01, %al + jnz L(Exit1) + test $0x02, %al + jnz L(Exit2) + test $0x04, %al + jnz L(Exit3) + test $0x08, %al + jnz L(Exit4) + test $0x10, %al + jnz L(Exit5) + test $0x20, %al + jnz L(Exit6) + test $0x40, %al + jnz L(Exit7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh): + test $0x01, %ah + jnz L(Exit9) + test $0x02, %ah + jnz L(Exit10) + test $0x04, %ah + jnz L(Exit11) + test $0x08, %ah + jnz L(Exit12) + test $0x10, %ah + jnz L(Exit13) + test $0x20, %ah + jnz L(Exit14) + test $0x40, %ah + jnz L(Exit15) + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit1): + movb %bh, 1(%edx) +L(Exit1): + movb (%ecx), %al + movb %al, (%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit2): + movb %bh, 2(%edx) +L(Exit2): + movw (%ecx), %ax + movw %ax, (%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit3): + movb %bh, 3(%edx) +L(Exit3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit4): + movb %bh, 4(%edx) +L(Exit4): + movl (%ecx), %eax + movl %eax, (%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit5): + movb %bh, 5(%edx) +L(Exit5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit6): + movb %bh, 6(%edx) +L(Exit6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit7): + movb %bh, 7(%edx) +L(Exit7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit8): + movb %bh, 8(%edx) +L(Exit8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit9): + movb %bh, 9(%edx) +L(Exit9): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit10): + movb %bh, 10(%edx) +L(Exit10): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit11): + movb %bh, 11(%edx) +L(Exit11): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit12): + movb %bh, 12(%edx) +L(Exit12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit13): + movb %bh, 13(%edx) +L(Exit13): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit14): + movb %bh, 14(%edx) +L(Exit14): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit15): + movb %bh, 15(%edx) +L(Exit15): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit16): + movb %bh, 16(%edx) +L(Exit16): + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + movl %edi, %eax + RETURN1 + +#ifdef USE_AS_STRNCPY + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2): + add $16, %ebx + add %esi, %ecx + lea (%esi, %edx), %esi + lea -9(%ebx), %edx + and $1<<7, %dh + or %al, %dh + lea (%esi), %edx + POP (%esi) + jz L(ExitHighCase2) + + test $0x01, %al + jnz L(Exit1) + cmp $1, %ebx + je L(StrncatExit1) + test $0x02, %al + jnz L(Exit2) + cmp $2, %ebx + je L(StrncatExit2) + test $0x04, %al + jnz L(Exit3) + cmp $3, %ebx + je L(StrncatExit3) + test $0x08, %al + jnz L(Exit4) + cmp $4, %ebx + je L(StrncatExit4) + test $0x10, %al + jnz L(Exit5) + cmp $5, %ebx + je L(StrncatExit5) + test $0x20, %al + jnz L(Exit6) + cmp $6, %ebx + je L(StrncatExit6) + test $0x40, %al + jnz L(Exit7) + cmp $7, %ebx + je L(StrncatExit7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + lea 7(%edx), %eax + cmpb $1, (%eax) + sbb $-1, %eax + xor %cl, %cl + movb %cl, (%eax) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHighCase2): + test $0x01, %ah + jnz L(Exit9) + cmp $9, %ebx + je L(StrncatExit9) + test $0x02, %ah + jnz L(Exit10) + cmp $10, %ebx + je L(StrncatExit10) + test $0x04, %ah + jnz L(Exit11) + cmp $11, %ebx + je L(StrncatExit11) + test $0x8, %ah + jnz L(Exit12) + cmp $12, %ebx + je L(StrncatExit12) + test $0x10, %ah + jnz L(Exit13) + cmp $13, %ebx + je L(StrncatExit13) + test $0x20, %ah + jnz L(Exit14) + cmp $14, %ebx + je L(StrncatExit14) + test $0x40, %ah + jnz L(Exit15) + cmp $15, %ebx + je L(StrncatExit15) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 8(%ecx), %xmm1 + movlpd %xmm1, 8(%edx) + movl %edi, %eax + RETURN1 + + CFI_PUSH(%esi) + +L(CopyFrom1To16BytesCase2OrCase3): + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + + .p2align 4 +L(CopyFrom1To16BytesCase3): + add $16, %ebx + add %esi, %edx + add %esi, %ecx + + POP (%esi) + + cmp $8, %ebx + ja L(ExitHighCase3) + cmp $1, %ebx + je L(StrncatExit1) + cmp $2, %ebx + je L(StrncatExit2) + cmp $3, %ebx + je L(StrncatExit3) + cmp $4, %ebx + je L(StrncatExit4) + cmp $5, %ebx + je L(StrncatExit5) + cmp $6, %ebx + je L(StrncatExit6) + cmp $7, %ebx + je L(StrncatExit7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb %bh, 8(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHighCase3): + cmp $9, %ebx + je L(StrncatExit9) + cmp $10, %ebx + je L(StrncatExit10) + cmp $11, %ebx + je L(StrncatExit11) + cmp $12, %ebx + je L(StrncatExit12) + cmp $13, %ebx + je L(StrncatExit13) + cmp $14, %ebx + je L(StrncatExit14) + cmp $15, %ebx + je L(StrncatExit15) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 8(%ecx), %xmm1 + movlpd %xmm1, 8(%edx) + movb %bh, 16(%edx) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncatExit0): + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncpyExit15Bytes): + cmp $9, %ebx + je L(StrncatExit9) + cmpb $0, 9(%ecx) + jz L(Exit10) + cmp $10, %ebx + je L(StrncatExit10) + cmpb $0, 10(%ecx) + jz L(Exit11) + cmp $11, %ebx + je L(StrncatExit11) + cmpb $0, 11(%ecx) + jz L(Exit12) + cmp $12, %ebx + je L(StrncatExit12) + cmpb $0, 12(%ecx) + jz L(Exit13) + cmp $13, %ebx + je L(StrncatExit13) + cmpb $0, 13(%ecx) + jz L(Exit14) + cmp $14, %ebx + je L(StrncatExit14) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + lea 14(%edx), %eax + cmpb $1, (%eax) + sbb $-1, %eax + movb %bh, (%eax) + movl %edi, %eax + RETURN1 + + .p2align 4 +L(StrncpyExit8Bytes): + cmpb $0, (%ecx) + jz L(Exit1) + cmp $1, %ebx + je L(StrncatExit1) + cmpb $0, 1(%ecx) + jz L(Exit2) + cmp $2, %ebx + je L(StrncatExit2) + cmpb $0, 2(%ecx) + jz L(Exit3) + cmp $3, %ebx + je L(StrncatExit3) + cmpb $0, 3(%ecx) + jz L(Exit4) + cmp $4, %ebx + je L(StrncatExit4) + cmpb $0, 4(%ecx) + jz L(Exit5) + cmp $5, %ebx + je L(StrncatExit5) + cmpb $0, 5(%ecx) + jz L(Exit6) + cmp $6, %ebx + je L(StrncatExit6) + cmpb $0, 6(%ecx) + jz L(Exit7) + cmp $7, %ebx + je L(StrncatExit7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + lea 7(%edx), %eax + cmpb $1, (%eax) + sbb $-1, %eax + movb %bh, (%eax) + movl %edi, %eax + RETURN1 + +#endif +END (STRCAT)
diff --git a/libc/arch-x86/atom/string/ssse3-strcmp-atom.S b/libc/arch-x86/atom/string/ssse3-strcmp-atom.S new file mode 100644 index 0000000..ee253b9 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strcmp-atom.S
@@ -0,0 +1,2275 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef cfi_remember_state +# define cfi_remember_state .cfi_remember_state +#endif + +#ifndef cfi_restore_state +# define cfi_restore_state .cfi_restore_state +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#ifndef USE_AS_STRNCMP +# define STR1 4 +# define STR2 STR1+4 +# define RETURN ret + +# define UPDATE_STRNCMP_COUNTER +#else +# define STR1 8 +# define STR2 STR1+4 +# define CNT STR2+4 +# define RETURN POP (%ebp); ret; CFI_PUSH (%ebp) + +# define UPDATE_STRNCMP_COUNTER \ + /* calculate left number to compare */ \ + mov $16, %esi; \ + sub %ecx, %esi; \ + cmpl %esi, %ebp; \ + jbe L(more8byteseq); \ + sub %esi, %ebp +#endif + +#ifndef STRCMP +# define STRCMP strcmp +#endif + + .section .text.ssse3,"ax",@progbits +ENTRY (STRCMP) +#ifdef USE_AS_STRNCMP + PUSH (%ebp) + cfi_remember_state +#endif + movl STR1(%esp), %edx + movl STR2(%esp), %eax +#ifdef USE_AS_STRNCMP + movl CNT(%esp), %ebp + cmpl $16, %ebp + jb L(less16bytes_sncmp) + jmp L(more16bytes) +#endif + + movzbl (%eax), %ecx + cmpb %cl, (%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 1(%eax), %ecx + cmpb %cl, 1(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 2(%eax), %ecx + cmpb %cl, 2(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 3(%eax), %ecx + cmpb %cl, 3(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 4(%eax), %ecx + cmpb %cl, 4(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 5(%eax), %ecx + cmpb %cl, 5(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 6(%eax), %ecx + cmpb %cl, 6(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + movzbl 7(%eax), %ecx + cmpb %cl, 7(%edx) + jne L(neq) + cmpl $0, %ecx + je L(eq) + + add $8, %edx + add $8, %eax +#ifdef USE_AS_STRNCMP + cmpl $8, %ebp + lea -8(%ebp), %ebp + je L(eq) +L(more16bytes): +#endif + movl %edx, %ecx + and $0xfff, %ecx + cmpl $0xff0, %ecx + ja L(crosspage) + mov %eax, %ecx + and $0xfff, %ecx + cmpl $0xff0, %ecx + ja L(crosspage) + pxor %xmm0, %xmm0 + movlpd (%eax), %xmm1 + movlpd (%edx), %xmm2 + movhpd 8(%eax), %xmm1 + movhpd 8(%edx), %xmm2 + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %ecx + sub $0xffff, %ecx + jnz L(less16bytes) +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(eq) +#endif + add $16, %eax + add $16, %edx + +L(crosspage): + + PUSH (%ebx) + PUSH (%edi) + PUSH (%esi) + + movl %edx, %edi + movl %eax, %ecx + and $0xf, %ecx + and $0xf, %edi + xor %ecx, %eax + xor %edi, %edx + xor %ebx, %ebx + cmpl %edi, %ecx + je L(ashr_0) + ja L(bigger) + or $0x20, %ebx + xchg %edx, %eax + xchg %ecx, %edi +L(bigger): + lea 15(%edi), %edi + sub %ecx, %edi + cmpl $8, %edi + jle L(ashr_less_8) + cmpl $14, %edi + je L(ashr_15) + cmpl $13, %edi + je L(ashr_14) + cmpl $12, %edi + je L(ashr_13) + cmpl $11, %edi + je L(ashr_12) + cmpl $10, %edi + je L(ashr_11) + cmpl $9, %edi + je L(ashr_10) +L(ashr_less_8): + je L(ashr_9) + cmpl $7, %edi + je L(ashr_8) + cmpl $6, %edi + je L(ashr_7) + cmpl $5, %edi + je L(ashr_6) + cmpl $4, %edi + je L(ashr_5) + cmpl $3, %edi + je L(ashr_4) + cmpl $2, %edi + je L(ashr_3) + cmpl $1, %edi + je L(ashr_2) + cmpl $0, %edi + je L(ashr_1) + +/* + * The following cases will be handled by ashr_0 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(0~15) n(0~15) 15(15+ n-n) ashr_0 + */ + .p2align 4 +L(ashr_0): + mov $0xffff, %esi + movdqa (%eax), %xmm1 + pxor %xmm0, %xmm0 + pcmpeqb %xmm1, %xmm0 + pcmpeqb (%edx), %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + mov %ecx, %edi + jne L(less32bytes) + UPDATE_STRNCMP_COUNTER + mov $0x10, %ebx + mov $0x10, %ecx + pxor %xmm0, %xmm0 + .p2align 4 +L(loop_ashr_0): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + jmp L(loop_ashr_0) + +/* + * The following cases will be handled by ashr_1 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(15) n -15 0(15 +(n-15) - n) ashr_1 + */ + .p2align 4 +L(ashr_1): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $15, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -15(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $1, %ebx + lea 1(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_1): + add $16, %edi + jg L(nibble_ashr_1) + +L(gobble_ashr_1): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $1, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_1) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $1, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_1) + + .p2align 4 +L(nibble_ashr_1): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfffe, %esi + jnz L(ashr_1_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $15, %ebp + jbe L(ashr_1_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_1) + + .p2align 4 +L(ashr_1_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $1, %xmm0 + psrldq $1, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_2 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(14~15) n -14 1(15 +(n-14) - n) ashr_2 + */ + .p2align 4 +L(ashr_2): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $14, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -14(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $2, %ebx + lea 2(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_2): + add $16, %edi + jg L(nibble_ashr_2) + +L(gobble_ashr_2): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $2, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_2) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $2, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_2) + + .p2align 4 +L(nibble_ashr_2): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfffc, %esi + jnz L(ashr_2_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $14, %ebp + jbe L(ashr_2_exittail) +#endif + + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_2) + + .p2align 4 +L(ashr_2_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $2, %xmm0 + psrldq $2, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_3 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(13~15) n -13 2(15 +(n-13) - n) ashr_3 + */ + .p2align 4 +L(ashr_3): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $13, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -13(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $3, %ebx + lea 3(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_3): + add $16, %edi + jg L(nibble_ashr_3) + +L(gobble_ashr_3): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $3, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_3) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $3, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_3) + + .p2align 4 +L(nibble_ashr_3): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfff8, %esi + jnz L(ashr_3_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $13, %ebp + jbe L(ashr_3_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_3) + + .p2align 4 +L(ashr_3_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $3, %xmm0 + psrldq $3, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_4 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(12~15) n -12 3(15 +(n-12) - n) ashr_4 + */ + .p2align 4 +L(ashr_4): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $12, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -12(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $4, %ebx + lea 4(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_4): + add $16, %edi + jg L(nibble_ashr_4) + +L(gobble_ashr_4): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $4, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_4) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $4, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_4) + + .p2align 4 +L(nibble_ashr_4): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfff0, %esi + jnz L(ashr_4_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $12, %ebp + jbe L(ashr_4_exittail) +#endif + + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_4) + + .p2align 4 +L(ashr_4_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $4, %xmm0 + psrldq $4, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_5 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(11~15) n -11 4(15 +(n-11) - n) ashr_5 + */ + .p2align 4 +L(ashr_5): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $11, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -11(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $5, %ebx + lea 5(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_5): + add $16, %edi + jg L(nibble_ashr_5) + +L(gobble_ashr_5): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $5, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_5) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $5, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_5) + + .p2align 4 +L(nibble_ashr_5): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xffe0, %esi + jnz L(ashr_5_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $11, %ebp + jbe L(ashr_5_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_5) + + .p2align 4 +L(ashr_5_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $5, %xmm0 + psrldq $5, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_6 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(10~15) n -10 5(15 +(n-10) - n) ashr_6 + */ + + .p2align 4 +L(ashr_6): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $10, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -10(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $6, %ebx + lea 6(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_6): + add $16, %edi + jg L(nibble_ashr_6) + +L(gobble_ashr_6): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $6, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_6) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $6, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_6) + + .p2align 4 +L(nibble_ashr_6): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xffc0, %esi + jnz L(ashr_6_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $10, %ebp + jbe L(ashr_6_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_6) + + .p2align 4 +L(ashr_6_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $6, %xmm0 + psrldq $6, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_7 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(9~15) n - 9 6(15 +(n-9) - n) ashr_7 + */ + + .p2align 4 +L(ashr_7): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $9, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -9(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $7, %ebx + lea 8(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_7): + add $16, %edi + jg L(nibble_ashr_7) + +L(gobble_ashr_7): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $7, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_7) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $7, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_7) + + .p2align 4 +L(nibble_ashr_7): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xff80, %esi + jnz L(ashr_7_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $9, %ebp + jbe L(ashr_7_exittail) +#endif + pxor %xmm0, %xmm0 + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_7) + + .p2align 4 +L(ashr_7_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $7, %xmm0 + psrldq $7, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_8 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(8~15) n - 8 7(15 +(n-8) - n) ashr_8 + */ + .p2align 4 +L(ashr_8): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $8, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -8(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $8, %ebx + lea 8(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_8): + add $16, %edi + jg L(nibble_ashr_8) + +L(gobble_ashr_8): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $8, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_8) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $8, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_8) + + .p2align 4 +L(nibble_ashr_8): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xff00, %esi + jnz L(ashr_8_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $8, %ebp + jbe L(ashr_8_exittail) +#endif + pxor %xmm0, %xmm0 + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_8) + + .p2align 4 +L(ashr_8_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $8, %xmm0 + psrldq $8, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_9 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(7~15) n - 7 8(15 +(n-7) - n) ashr_9 + */ + .p2align 4 +L(ashr_9): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $7, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -7(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $9, %ebx + lea 9(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_9): + add $16, %edi + jg L(nibble_ashr_9) + +L(gobble_ashr_9): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $9, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_9) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $9, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_9) + + .p2align 4 +L(nibble_ashr_9): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfe00, %esi + jnz L(ashr_9_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $7, %ebp + jbe L(ashr_9_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_9) + + .p2align 4 +L(ashr_9_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $9, %xmm0 + psrldq $9, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_10 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(6~15) n - 6 9(15 +(n-6) - n) ashr_10 + */ + .p2align 4 +L(ashr_10): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $6, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -6(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $10, %ebx + lea 10(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_10): + add $16, %edi + jg L(nibble_ashr_10) + +L(gobble_ashr_10): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $10, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_10) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $10, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_10) + + .p2align 4 +L(nibble_ashr_10): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xfc00, %esi + jnz L(ashr_10_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $6, %ebp + jbe L(ashr_10_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_10) + + .p2align 4 +L(ashr_10_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $10, %xmm0 + psrldq $10, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_11 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(5~15) n - 5 10(15 +(n-5) - n) ashr_11 + */ + .p2align 4 +L(ashr_11): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $5, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -5(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $11, %ebx + lea 11(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_11): + add $16, %edi + jg L(nibble_ashr_11) + +L(gobble_ashr_11): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $11, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_11) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $11, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_11) + + .p2align 4 +L(nibble_ashr_11): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xf800, %esi + jnz L(ashr_11_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $5, %ebp + jbe L(ashr_11_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_11) + + .p2align 4 +L(ashr_11_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $11, %xmm0 + psrldq $11, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_12 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(4~15) n - 4 11(15 +(n-4) - n) ashr_12 + */ + .p2align 4 +L(ashr_12): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $4, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -4(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $12, %ebx + lea 12(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_12): + add $16, %edi + jg L(nibble_ashr_12) + +L(gobble_ashr_12): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $12, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_12) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $12, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_12) + + .p2align 4 +L(nibble_ashr_12): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xf000, %esi + jnz L(ashr_12_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $4, %ebp + jbe L(ashr_12_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_12) + + .p2align 4 +L(ashr_12_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $12, %xmm0 + psrldq $12, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_13 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(3~15) n - 3 12(15 +(n-3) - n) ashr_13 + */ + .p2align 4 +L(ashr_13): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $3, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -3(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $13, %ebx + lea 13(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_13): + add $16, %edi + jg L(nibble_ashr_13) + +L(gobble_ashr_13): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $13, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_13) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $13, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_13) + + .p2align 4 +L(nibble_ashr_13): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xe000, %esi + jnz L(ashr_13_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $3, %ebp + jbe L(ashr_13_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_13) + + .p2align 4 +L(ashr_13_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $13, %xmm0 + psrldq $13, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_14 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(2~15) n - 2 13(15 +(n-2) - n) ashr_14 + */ + .p2align 4 +L(ashr_14): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $2, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -2(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $14, %ebx + lea 14(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_14): + add $16, %edi + jg L(nibble_ashr_14) + +L(gobble_ashr_14): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $14, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_14) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $14, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_14) + + .p2align 4 +L(nibble_ashr_14): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0xc000, %esi + jnz L(ashr_14_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $2, %ebp + jbe L(ashr_14_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_14) + + .p2align 4 +L(ashr_14_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $14, %xmm0 + psrldq $14, %xmm3 + jmp L(aftertail) + +/* + * The following cases will be handled by ashr_14 + * ecx(offset of esi) eax(offset of edi) relative offset corresponding case + * n(1~15) n - 1 14(15 +(n-1) - n) ashr_15 + */ + + .p2align 4 +L(ashr_15): + mov $0xffff, %esi + pxor %xmm0, %xmm0 + movdqa (%edx), %xmm2 + movdqa (%eax), %xmm1 + pcmpeqb %xmm1, %xmm0 + pslldq $1, %xmm2 + pcmpeqb %xmm1, %xmm2 + psubb %xmm0, %xmm2 + pmovmskb %xmm2, %edi + shr %cl, %esi + shr %cl, %edi + sub %edi, %esi + lea -1(%ecx), %edi + jnz L(less32bytes) + + UPDATE_STRNCMP_COUNTER + + movdqa (%edx), %xmm3 + pxor %xmm0, %xmm0 + mov $16, %ecx + or $15, %ebx + lea 15(%edx), %edi + and $0xfff, %edi + sub $0x1000, %edi + + .p2align 4 +L(loop_ashr_15): + add $16, %edi + jg L(nibble_ashr_15) + +L(gobble_ashr_15): + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $15, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + + add $16, %edi + jg L(nibble_ashr_15) + + movdqa (%eax, %ecx), %xmm1 + movdqa (%edx, %ecx), %xmm2 + movdqa %xmm2, %xmm4 + + palignr $15, %xmm3, %xmm2 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm2, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + sub $0xffff, %esi + jnz L(exit) + +#ifdef USE_AS_STRNCMP + cmpl $16, %ebp + lea -16(%ebp), %ebp + jbe L(more8byteseq) +#endif + add $16, %ecx + movdqa %xmm4, %xmm3 + jmp L(loop_ashr_15) + + .p2align 4 +L(nibble_ashr_15): + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %esi + test $0x8000, %esi + jnz L(ashr_15_exittail) + +#ifdef USE_AS_STRNCMP + cmpl $1, %ebp + jbe L(ashr_15_exittail) +#endif + pxor %xmm0, %xmm0 + sub $0x1000, %edi + jmp L(gobble_ashr_15) + + .p2align 4 +L(ashr_15_exittail): + movdqa (%eax, %ecx), %xmm1 + psrldq $15, %xmm0 + psrldq $15, %xmm3 + jmp L(aftertail) + + .p2align 4 +L(aftertail): + pcmpeqb %xmm3, %xmm1 + psubb %xmm0, %xmm1 + pmovmskb %xmm1, %esi + not %esi +L(exit): + mov %ebx, %edi + and $0x1f, %edi + lea -16(%edi, %ecx), %edi +L(less32bytes): + add %edi, %edx + add %ecx, %eax + test $0x20, %ebx + jz L(ret2) + xchg %eax, %edx + + .p2align 4 +L(ret2): + mov %esi, %ecx + POP (%esi) + POP (%edi) + POP (%ebx) +L(less16bytes): + test %cl, %cl + jz L(2next_8_bytes) + + test $0x01, %cl + jnz L(Byte0) + + test $0x02, %cl + jnz L(Byte1) + + test $0x04, %cl + jnz L(Byte2) + + test $0x08, %cl + jnz L(Byte3) + + test $0x10, %cl + jnz L(Byte4) + + test $0x20, %cl + jnz L(Byte5) + + test $0x40, %cl + jnz L(Byte6) +#ifdef USE_AS_STRNCMP + cmpl $7, %ebp + jbe L(eq) +#endif + + movzbl 7(%eax), %ecx + movzbl 7(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte0): +#ifdef USE_AS_STRNCMP + cmpl $0, %ebp + jbe L(eq) +#endif + movzbl (%eax), %ecx + movzbl (%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte1): +#ifdef USE_AS_STRNCMP + cmpl $1, %ebp + jbe L(eq) +#endif + movzbl 1(%eax), %ecx + movzbl 1(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte2): +#ifdef USE_AS_STRNCMP + cmpl $2, %ebp + jbe L(eq) +#endif + movzbl 2(%eax), %ecx + movzbl 2(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte3): +#ifdef USE_AS_STRNCMP + cmpl $3, %ebp + jbe L(eq) +#endif + movzbl 3(%eax), %ecx + movzbl 3(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte4): +#ifdef USE_AS_STRNCMP + cmpl $4, %ebp + jbe L(eq) +#endif + movzbl 4(%eax), %ecx + movzbl 4(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte5): +#ifdef USE_AS_STRNCMP + cmpl $5, %ebp + jbe L(eq) +#endif + movzbl 5(%eax), %ecx + movzbl 5(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(Byte6): +#ifdef USE_AS_STRNCMP + cmpl $6, %ebp + jbe L(eq) +#endif + movzbl 6(%eax), %ecx + movzbl 6(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(2next_8_bytes): + add $8, %eax + add $8, %edx +#ifdef USE_AS_STRNCMP + cmpl $8, %ebp + lea -8(%ebp), %ebp + jbe L(eq) +#endif + + test $0x01, %ch + jnz L(Byte0) + + test $0x02, %ch + jnz L(Byte1) + + test $0x04, %ch + jnz L(Byte2) + + test $0x08, %ch + jnz L(Byte3) + + test $0x10, %ch + jnz L(Byte4) + + test $0x20, %ch + jnz L(Byte5) + + test $0x40, %ch + jnz L(Byte6) + +#ifdef USE_AS_STRNCMP + cmpl $7, %ebp + jbe L(eq) +#endif + movzbl 7(%eax), %ecx + movzbl 7(%edx), %eax + + sub %ecx, %eax + RETURN + + .p2align 4 +L(neq): + mov $1, %eax + ja L(neq_bigger) + neg %eax +L(neq_bigger): + RETURN + +#ifdef USE_AS_STRNCMP + .p2align 4 +L(more8byteseq): + POP (%esi) + POP (%edi) + POP (%ebx) +#endif + +L(eq): + +#ifdef USE_AS_STRNCMP + POP (%ebp) +#endif + xorl %eax, %eax + ret + +#ifdef USE_AS_STRNCMP + cfi_restore_state + + .p2align 4 +L(less16bytes_sncmp): + test %ebp, %ebp + jz L(eq) + + movzbl (%eax), %ecx + cmpb %cl, (%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $1, %ebp + je L(eq) + + movzbl 1(%eax), %ecx + cmpb %cl, 1(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $2, %ebp + je L(eq) + + movzbl 2(%eax), %ecx + cmpb %cl, 2(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $3, %ebp + je L(eq) + + movzbl 3(%eax), %ecx + cmpb %cl, 3(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $4, %ebp + je L(eq) + + movzbl 4(%eax), %ecx + cmpb %cl, 4(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $5, %ebp + je L(eq) + + movzbl 5(%eax), %ecx + cmpb %cl, 5(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $6, %ebp + je L(eq) + + movzbl 6(%eax), %ecx + cmpb %cl, 6(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $7, %ebp + je L(eq) + + movzbl 7(%eax), %ecx + cmpb %cl, 7(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + + cmpl $8, %ebp + je L(eq) + + movzbl 8(%eax), %ecx + cmpb %cl, 8(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $9, %ebp + je L(eq) + + movzbl 9(%eax), %ecx + cmpb %cl, 9(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $10, %ebp + je L(eq) + + movzbl 10(%eax), %ecx + cmpb %cl, 10(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $11, %ebp + je L(eq) + + movzbl 11(%eax), %ecx + cmpb %cl, 11(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + + cmpl $12, %ebp + je L(eq) + + movzbl 12(%eax), %ecx + cmpb %cl, 12(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $13, %ebp + je L(eq) + + movzbl 13(%eax), %ecx + cmpb %cl, 13(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $14, %ebp + je L(eq) + + movzbl 14(%eax), %ecx + cmpb %cl, 14(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + cmpl $15, %ebp + je L(eq) + + movzbl 15(%eax), %ecx + cmpb %cl, 15(%edx) + jne L(neq) + test %cl, %cl + je L(eq) + + POP (%ebp) + xor %eax, %eax + ret +#endif + +END (STRCMP)
diff --git a/libc/arch-x86/atom/string/ssse3-strcpy-atom.S b/libc/arch-x86/atom/string/ssse3-strcpy-atom.S new file mode 100644 index 0000000..3690b0d --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strcpy-atom.S
@@ -0,0 +1,3955 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef USE_AS_STRCAT + +# ifndef L +# define L(label) .L##label +# endif + +# ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +# endif + +# ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +# endif + +# ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +# endif + +# ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +# endif + +# ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +# endif + +# ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +# endif + +# ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +# endif + +# define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +# define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +# define PUSH(REG) pushl REG; CFI_PUSH (REG) +# define POP(REG) popl REG; CFI_POP (REG) + +# ifndef STRCPY +# define STRCPY strcpy +# endif + +# ifdef USE_AS_STRNCPY +# define PARMS 8 +# define ENTRANCE PUSH (%ebx) +# define RETURN POP (%ebx); ret; CFI_PUSH (%ebx); +# define RETURN1 POP (%edi); POP (%ebx); ret; CFI_PUSH (%ebx); CFI_PUSH (%edi) +# else +# define PARMS 4 +# define ENTRANCE +# define RETURN ret +# define RETURN1 POP (%edi); ret; CFI_PUSH (%edi) +# endif + +# ifdef USE_AS_STPCPY +# define SAVE_RESULT(n) lea n(%edx), %eax +# define SAVE_RESULT_TAIL(n) lea n(%edx), %eax +# else +# define SAVE_RESULT(n) movl %edi, %eax +# define SAVE_RESULT_TAIL(n) movl %edx, %eax +# endif + +# define STR1 PARMS +# define STR2 STR1+4 +# define LEN STR2+4 + +/* In this code following instructions are used for copying: + movb - 1 byte + movw - 2 byte + movl - 4 byte + movlpd - 8 byte + movaps - 16 byte - requires 16 byte alignment + of sourse and destination adresses. +*/ + +.text +ENTRY (STRCPY) + ENTRANCE + mov STR1(%esp), %edx + mov STR2(%esp), %ecx +# ifdef USE_AS_STRNCPY + movl LEN(%esp), %ebx + cmp $8, %ebx + jbe L(StrncpyExit8Bytes) +# endif + cmpb $0, (%ecx) + jz L(ExitTail1) + cmpb $0, 1(%ecx) + jz L(ExitTail2) + cmpb $0, 2(%ecx) + jz L(ExitTail3) + cmpb $0, 3(%ecx) + jz L(ExitTail4) + cmpb $0, 4(%ecx) + jz L(ExitTail5) + cmpb $0, 5(%ecx) + jz L(ExitTail6) + cmpb $0, 6(%ecx) + jz L(ExitTail7) + cmpb $0, 7(%ecx) + jz L(ExitTail8) +# ifdef USE_AS_STRNCPY + cmp $16, %ebx + jb L(StrncpyExit15Bytes) +# endif + cmpb $0, 8(%ecx) + jz L(ExitTail9) + cmpb $0, 9(%ecx) + jz L(ExitTail10) + cmpb $0, 10(%ecx) + jz L(ExitTail11) + cmpb $0, 11(%ecx) + jz L(ExitTail12) + cmpb $0, 12(%ecx) + jz L(ExitTail13) + cmpb $0, 13(%ecx) + jz L(ExitTail14) + cmpb $0, 14(%ecx) + jz L(ExitTail15) +# if defined USE_AS_STRNCPY && !defined USE_AS_STRLCPY + cmp $16, %ebx + je L(ExitTail16) +# endif + cmpb $0, 15(%ecx) + jz L(ExitTail16) + +# if defined USE_AS_STRNCPY && defined USE_AS_STRLCPY + cmp $16, %ebx + je L(StrlcpyExitTail16) +# endif + + PUSH (%edi) +# ifndef USE_AS_STRLCPY + mov %edx, %edi +# else + mov %ecx, %edi +# endif +#endif + PUSH (%esi) +#ifdef USE_AS_STRNCPY + mov %ecx, %esi + sub $16, %ebx + and $0xf, %esi + +/* add 16 bytes ecx_offset to ebx */ + + add %esi, %ebx +#endif + lea 16(%ecx), %esi + and $-16, %esi + pxor %xmm0, %xmm0 + movlpd (%ecx), %xmm1 + movlpd %xmm1, (%edx) + + pcmpeqb (%esi), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm1, 8(%edx) + + pmovmskb %xmm0, %eax + sub %ecx, %esi + +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + mov %edx, %eax + lea 16(%edx), %edx + and $-16, %edx + sub %edx, %eax + +#ifdef USE_AS_STRNCPY + add %eax, %esi + lea -1(%esi), %esi + and $1<<31, %esi + test %esi, %esi + jnz L(ContinueCopy) + lea 16(%ebx), %ebx + +L(ContinueCopy): +#endif + sub %eax, %ecx + mov %ecx, %eax + and $0xf, %eax + mov $0, %esi + +/* case: ecx_offset == edx_offset */ + + jz L(Align16Both) + + cmp $8, %eax + jae L(ShlHigh8) + cmp $1, %eax + je L(Shl1) + cmp $2, %eax + je L(Shl2) + cmp $3, %eax + je L(Shl3) + cmp $4, %eax + je L(Shl4) + cmp $5, %eax + je L(Shl5) + cmp $6, %eax + je L(Shl6) + jmp L(Shl7) + +L(ShlHigh8): + je L(Shl8) + cmp $9, %eax + je L(Shl9) + cmp $10, %eax + je L(Shl10) + cmp $11, %eax + je L(Shl11) + cmp $12, %eax + je L(Shl12) + cmp $13, %eax + je L(Shl13) + cmp $14, %eax + je L(Shl14) + jmp L(Shl15) + +L(Align16Both): + movaps (%ecx), %xmm1 + movaps 16(%ecx), %xmm2 + movaps %xmm1, (%edx) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm3 + movaps %xmm2, (%edx, %esi) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm4 + movaps %xmm3, (%edx, %esi) + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm1 + movaps %xmm4, (%edx, %esi) + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm2 + movaps %xmm1, (%edx, %esi) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm3 + movaps %xmm2, (%edx, %esi) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) +#endif + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps %xmm3, (%edx, %esi) + mov %ecx, %eax + lea 16(%ecx, %esi), %ecx + and $-0x40, %ecx + sub %ecx, %eax + sub %eax, %edx +#ifdef USE_AS_STRNCPY + lea 112(%ebx, %eax), %ebx +#endif + mov $-0x40, %esi + +L(Aligned64Loop): + movaps (%ecx), %xmm2 + movaps 32(%ecx), %xmm3 + movaps %xmm2, %xmm4 + movaps 16(%ecx), %xmm5 + movaps %xmm3, %xmm6 + movaps 48(%ecx), %xmm7 + pminub %xmm5, %xmm2 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + lea 64(%edx), %edx + pcmpeqb %xmm0, %xmm3 + lea 64(%ecx), %ecx + pmovmskb %xmm3, %eax +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeaveCase2OrCase3) +#endif + test %eax, %eax + jnz L(Aligned64Leave) + movaps %xmm4, -64(%edx) + movaps %xmm5, -48(%edx) + movaps %xmm6, -32(%edx) + movaps %xmm7, -16(%edx) + jmp L(Aligned64Loop) + +L(Aligned64Leave): +#ifdef USE_AS_STRNCPY + lea 48(%ebx), %ebx +#endif + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqb %xmm5, %xmm0 +#ifdef USE_AS_STRNCPY + lea -16(%ebx), %ebx +#endif + pmovmskb %xmm0, %eax + movaps %xmm4, -64(%edx) + lea 16(%esi), %esi + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqb %xmm6, %xmm0 +#ifdef USE_AS_STRNCPY + lea -16(%ebx), %ebx +#endif + pmovmskb %xmm0, %eax + movaps %xmm5, -48(%edx) + lea 16(%esi), %esi + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps %xmm6, -32(%edx) + pcmpeqb %xmm7, %xmm0 +#ifdef USE_AS_STRNCPY + lea -16(%ebx), %ebx +#endif + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl1): + movaps -1(%ecx), %xmm1 + movaps 15(%ecx), %xmm2 +L(Shl1Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit1Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl1LoopExit) + + palignr $1, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 31(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit1Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl1LoopExit) + + palignr $1, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 31(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit1Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl1LoopExit) + + palignr $1, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 31(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit1Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl1LoopExit) + + palignr $1, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 31(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -15(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -1(%ecx), %xmm1 + +L(Shl1LoopStart): + movaps 15(%ecx), %xmm2 + movaps 31(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 47(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 63(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $1, %xmm4, %xmm5 + palignr $1, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl1Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave1) +#endif + palignr $1, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $1, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl1LoopStart) + +L(Shl1LoopExit): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + mov $15, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl2): + movaps -2(%ecx), %xmm1 + movaps 14(%ecx), %xmm2 +L(Shl2Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit2Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl2LoopExit) + + palignr $2, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 30(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit2Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl2LoopExit) + + palignr $2, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 30(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit2Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl2LoopExit) + + palignr $2, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 30(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit2Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl2LoopExit) + + palignr $2, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 30(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -14(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -2(%ecx), %xmm1 + +L(Shl2LoopStart): + movaps 14(%ecx), %xmm2 + movaps 30(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 46(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 62(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $2, %xmm4, %xmm5 + palignr $2, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl2Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave2) +#endif + palignr $2, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $2, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl2LoopStart) + +L(Shl2LoopExit): + movlpd (%ecx), %xmm0 + movlpd 6(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 6(%edx) + mov $14, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl3): + movaps -3(%ecx), %xmm1 + movaps 13(%ecx), %xmm2 +L(Shl3Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit3Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl3LoopExit) + + palignr $3, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 29(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit3Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl3LoopExit) + + palignr $3, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 29(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit3Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl3LoopExit) + + palignr $3, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 29(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit3Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl3LoopExit) + + palignr $3, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 29(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -13(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -3(%ecx), %xmm1 + +L(Shl3LoopStart): + movaps 13(%ecx), %xmm2 + movaps 29(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 45(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 61(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $3, %xmm4, %xmm5 + palignr $3, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl3Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave3) +#endif + palignr $3, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $3, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl3LoopStart) + +L(Shl3LoopExit): + movlpd (%ecx), %xmm0 + movlpd 5(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 5(%edx) + mov $13, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl4): + movaps -4(%ecx), %xmm1 + movaps 12(%ecx), %xmm2 +L(Shl4Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit4Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit4Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit4Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit4Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 28(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -12(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -4(%ecx), %xmm1 + +L(Shl4LoopStart): + movaps 12(%ecx), %xmm2 + movaps 28(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 44(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 60(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $4, %xmm4, %xmm5 + palignr $4, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl4Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave4) +#endif + palignr $4, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $4, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl4LoopStart) + +L(Shl4LoopExit): + movlpd (%ecx), %xmm0 + movl 8(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 8(%edx) + mov $12, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl5): + movaps -5(%ecx), %xmm1 + movaps 11(%ecx), %xmm2 +L(Shl5Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit5Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl5LoopExit) + + palignr $5, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 27(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit5Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl5LoopExit) + + palignr $5, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 27(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit5Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl5LoopExit) + + palignr $5, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 27(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit5Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl5LoopExit) + + palignr $5, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 27(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -11(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -5(%ecx), %xmm1 + +L(Shl5LoopStart): + movaps 11(%ecx), %xmm2 + movaps 27(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 43(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 59(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $5, %xmm4, %xmm5 + palignr $5, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl5Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave5) +#endif + palignr $5, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $5, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl5LoopStart) + +L(Shl5LoopExit): + movlpd (%ecx), %xmm0 + movl 7(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 7(%edx) + mov $11, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl6): + movaps -6(%ecx), %xmm1 + movaps 10(%ecx), %xmm2 +L(Shl6Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit6Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl6LoopExit) + + palignr $6, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 26(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit6Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl6LoopExit) + + palignr $6, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 26(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit6Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl6LoopExit) + + palignr $6, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 26(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit6Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl6LoopExit) + + palignr $6, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 26(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -10(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -6(%ecx), %xmm1 + +L(Shl6LoopStart): + movaps 10(%ecx), %xmm2 + movaps 26(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 42(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 58(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $6, %xmm4, %xmm5 + palignr $6, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl6Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave6) +#endif + palignr $6, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $6, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl6LoopStart) + +L(Shl6LoopExit): + movlpd (%ecx), %xmm0 + movl 6(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 6(%edx) + mov $10, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl7): + movaps -7(%ecx), %xmm1 + movaps 9(%ecx), %xmm2 +L(Shl7Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit7Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl7LoopExit) + + palignr $7, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 25(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit7Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl7LoopExit) + + palignr $7, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 25(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit7Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl7LoopExit) + + palignr $7, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 25(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit7Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl7LoopExit) + + palignr $7, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 25(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -9(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -7(%ecx), %xmm1 + +L(Shl7LoopStart): + movaps 9(%ecx), %xmm2 + movaps 25(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 41(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 57(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $7, %xmm4, %xmm5 + palignr $7, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl7Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave7) +#endif + palignr $7, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $7, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl7LoopStart) + +L(Shl7LoopExit): + movlpd (%ecx), %xmm0 + movl 5(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 5(%edx) + mov $9, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl8): + movaps -8(%ecx), %xmm1 + movaps 8(%ecx), %xmm2 +L(Shl8Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit8Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit8Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit8Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit8Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 24(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -8(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -8(%ecx), %xmm1 + +L(Shl8LoopStart): + movaps 8(%ecx), %xmm2 + movaps 24(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 40(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 56(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $8, %xmm4, %xmm5 + palignr $8, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl8Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave8) +#endif + palignr $8, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $8, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl8LoopStart) + +L(Shl8LoopExit): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + mov $8, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl9): + movaps -9(%ecx), %xmm1 + movaps 7(%ecx), %xmm2 +L(Shl9Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit9Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl9LoopExit) + + palignr $9, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 23(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit9Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl9LoopExit) + + palignr $9, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 23(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit9Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl9LoopExit) + + palignr $9, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 23(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit9Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl9LoopExit) + + palignr $9, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 23(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -7(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -9(%ecx), %xmm1 + +L(Shl9LoopStart): + movaps 7(%ecx), %xmm2 + movaps 23(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 39(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 55(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $9, %xmm4, %xmm5 + palignr $9, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl9Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave9) +#endif + palignr $9, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $9, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl9LoopStart) + +L(Shl9LoopExit): + movlpd -1(%ecx), %xmm0 + movlpd %xmm0, -1(%edx) + mov $7, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl10): + movaps -10(%ecx), %xmm1 + movaps 6(%ecx), %xmm2 +L(Shl10Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit10Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl10LoopExit) + + palignr $10, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 22(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit10Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl10LoopExit) + + palignr $10, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 22(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit10Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl10LoopExit) + + palignr $10, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 22(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit10Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl10LoopExit) + + palignr $10, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 22(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -6(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -10(%ecx), %xmm1 + +L(Shl10LoopStart): + movaps 6(%ecx), %xmm2 + movaps 22(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 38(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 54(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $10, %xmm4, %xmm5 + palignr $10, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl10Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave10) +#endif + palignr $10, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $10, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl10LoopStart) + +L(Shl10LoopExit): + movlpd -2(%ecx), %xmm0 + movlpd %xmm0, -2(%edx) + mov $6, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl11): + movaps -11(%ecx), %xmm1 + movaps 5(%ecx), %xmm2 +L(Shl11Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit11Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl11LoopExit) + + palignr $11, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 21(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit11Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl11LoopExit) + + palignr $11, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 21(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit11Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl11LoopExit) + + palignr $11, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 21(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit11Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl11LoopExit) + + palignr $11, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 21(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -5(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -11(%ecx), %xmm1 + +L(Shl11LoopStart): + movaps 5(%ecx), %xmm2 + movaps 21(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 37(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 53(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $11, %xmm4, %xmm5 + palignr $11, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl11Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave11) +#endif + palignr $11, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $11, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl11LoopStart) + +L(Shl11LoopExit): + movlpd -3(%ecx), %xmm0 + movlpd %xmm0, -3(%edx) + mov $5, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl12): + movaps -12(%ecx), %xmm1 + movaps 4(%ecx), %xmm2 +L(Shl12Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit12Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit12Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit12Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit12Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 20(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -4(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -12(%ecx), %xmm1 + +L(Shl12LoopStart): + movaps 4(%ecx), %xmm2 + movaps 20(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 36(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 52(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $12, %xmm4, %xmm5 + palignr $12, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl12Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave12) +#endif + palignr $12, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $12, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl12LoopStart) + +L(Shl12LoopExit): + movl (%ecx), %esi + movl %esi, (%edx) + mov $4, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl13): + movaps -13(%ecx), %xmm1 + movaps 3(%ecx), %xmm2 +L(Shl13Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit13Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl13LoopExit) + + palignr $13, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 19(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit13Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl13LoopExit) + + palignr $13, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 19(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit13Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl13LoopExit) + + palignr $13, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 19(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit13Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl13LoopExit) + + palignr $13, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 19(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -3(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -13(%ecx), %xmm1 + +L(Shl13LoopStart): + movaps 3(%ecx), %xmm2 + movaps 19(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 35(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 51(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $13, %xmm4, %xmm5 + palignr $13, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl13Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave13) +#endif + palignr $13, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $13, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl13LoopStart) + +L(Shl13LoopExit): + movl -1(%ecx), %esi + movl %esi, -1(%edx) + mov $3, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl14): + movaps -14(%ecx), %xmm1 + movaps 2(%ecx), %xmm2 +L(Shl14Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit14Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl14LoopExit) + + palignr $14, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 18(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit14Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl14LoopExit) + + palignr $14, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 18(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit14Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl14LoopExit) + + palignr $14, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 18(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit14Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl14LoopExit) + + palignr $14, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 18(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -2(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -14(%ecx), %xmm1 + +L(Shl14LoopStart): + movaps 2(%ecx), %xmm2 + movaps 18(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 34(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 50(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $14, %xmm4, %xmm5 + palignr $14, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl14Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave14) +#endif + palignr $14, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $14, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl14LoopStart) + +L(Shl14LoopExit): + movl -2(%ecx), %esi + movl %esi, -2(%edx) + mov $2, %esi + jmp L(CopyFrom1To16Bytes) + + .p2align 4 +L(Shl15): + movaps -15(%ecx), %xmm1 + movaps 1(%ecx), %xmm2 +L(Shl15Start): + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit15Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl15LoopExit) + + palignr $15, %xmm1, %xmm2 + movaps %xmm3, %xmm1 + movaps %xmm2, (%edx) + movaps 17(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit15Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl15LoopExit) + + palignr $15, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 17(%ecx), %xmm2 + movaps %xmm3, %xmm1 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit15Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl15LoopExit) + + palignr $15, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 17(%ecx), %xmm2 + + pcmpeqb %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(StrncpyExit15Case2OrCase3) +#endif + test %eax, %eax + jnz L(Shl15LoopExit) + + palignr $15, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 17(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -1(%ecx), %ecx + sub %eax, %edx +#ifdef USE_AS_STRNCPY + add %eax, %ebx +#endif + movaps -15(%ecx), %xmm1 + +L(Shl15LoopStart): + movaps 1(%ecx), %xmm2 + movaps 17(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 33(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 49(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqb %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $15, %xmm4, %xmm5 + palignr $15, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl15Start) +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(StrncpyLeave15) +#endif + palignr $15, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $15, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl15LoopStart) + +L(Shl15LoopExit): + movl -3(%ecx), %esi + movl %esi, -3(%edx) + mov $1, %esi +#if defined USE_AS_STRCAT || defined USE_AS_STRLCPY + jmp L(CopyFrom1To16Bytes) +#endif + + +#if !defined USE_AS_STRCAT && !defined USE_AS_STRLCPY + + .p2align 4 +L(CopyFrom1To16Bytes): +# ifdef USE_AS_STRNCPY + add $16, %ebx +# endif + add %esi, %edx + add %esi, %ecx + + POP (%esi) + test %al, %al + jz L(ExitHigh8) + +L(CopyFrom1To16BytesLess8): + mov %al, %ah + and $15, %ah + jz L(ExitHigh4) + + test $0x01, %al + jnz L(Exit1) + test $0x02, %al + jnz L(Exit2) + test $0x04, %al + jnz L(Exit3) + + .p2align 4 +L(Exit4): + movl (%ecx), %eax + movl %eax, (%edx) + SAVE_RESULT (3) +# ifdef USE_AS_STRNCPY + sub $4, %ebx + lea 4(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(ExitHigh4): + test $0x10, %al + jnz L(Exit5) + test $0x20, %al + jnz L(Exit6) + test $0x40, %al + jnz L(Exit7) + + .p2align 4 +L(Exit8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + SAVE_RESULT (7) +# ifdef USE_AS_STRNCPY + sub $8, %ebx + lea 8(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(ExitHigh8): + mov %ah, %al + and $15, %al + jz L(ExitHigh12) + + test $0x01, %ah + jnz L(Exit9) + test $0x02, %ah + jnz L(Exit10) + test $0x04, %ah + jnz L(Exit11) + + .p2align 4 +L(Exit12): + movlpd (%ecx), %xmm0 + movl 8(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 8(%edx) + SAVE_RESULT (11) +# ifdef USE_AS_STRNCPY + sub $12, %ebx + lea 12(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(ExitHigh12): + test $0x10, %ah + jnz L(Exit13) + test $0x20, %ah + jnz L(Exit14) + test $0x40, %ah + jnz L(Exit15) + + .p2align 4 +L(Exit16): + movdqu (%ecx), %xmm0 + movdqu %xmm0, (%edx) + SAVE_RESULT (15) +# ifdef USE_AS_STRNCPY + sub $16, %ebx + lea 16(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + +# ifdef USE_AS_STRNCPY + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2): + add $16, %ebx + add %esi, %ecx + add %esi, %edx + + POP (%esi) + + test %al, %al + jz L(ExitHighCase2) + + cmp $8, %ebx + ja L(CopyFrom1To16BytesLess8) + + test $0x01, %al + jnz L(Exit1) + cmp $1, %ebx + je L(Exit1) + test $0x02, %al + jnz L(Exit2) + cmp $2, %ebx + je L(Exit2) + test $0x04, %al + jnz L(Exit3) + cmp $3, %ebx + je L(Exit3) + test $0x08, %al + jnz L(Exit4) + cmp $4, %ebx + je L(Exit4) + test $0x10, %al + jnz L(Exit5) + cmp $5, %ebx + je L(Exit5) + test $0x20, %al + jnz L(Exit6) + cmp $6, %ebx + je L(Exit6) + test $0x40, %al + jnz L(Exit7) + cmp $7, %ebx + je L(Exit7) + jmp L(Exit8) + + .p2align 4 +L(ExitHighCase2): + cmp $8, %ebx + jbe L(CopyFrom1To16BytesLess8Case3) + + test $0x01, %ah + jnz L(Exit9) + cmp $9, %ebx + je L(Exit9) + test $0x02, %ah + jnz L(Exit10) + cmp $10, %ebx + je L(Exit10) + test $0x04, %ah + jnz L(Exit11) + cmp $11, %ebx + je L(Exit11) + test $0x8, %ah + jnz L(Exit12) + cmp $12, %ebx + je L(Exit12) + test $0x10, %ah + jnz L(Exit13) + cmp $13, %ebx + je L(Exit13) + test $0x20, %ah + jnz L(Exit14) + cmp $14, %ebx + je L(Exit14) + test $0x40, %ah + jnz L(Exit15) + cmp $15, %ebx + je L(Exit15) + jmp L(Exit16) + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2OrCase3): + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + + .p2align 4 +L(CopyFrom1To16BytesCase3): + add $16, %ebx + add %esi, %edx + add %esi, %ecx + + POP (%esi) + + cmp $8, %ebx + ja L(ExitHigh8Case3) + +L(CopyFrom1To16BytesLess8Case3): + cmp $4, %ebx + ja L(ExitHigh4Case3) + + cmp $1, %ebx + je L(Exit1) + cmp $2, %ebx + je L(Exit2) + cmp $3, %ebx + je L(Exit3) + movl (%ecx), %eax + movl %eax, (%edx) + SAVE_RESULT (4) + RETURN1 + + .p2align 4 +L(ExitHigh4Case3): + cmp $5, %ebx + je L(Exit5) + cmp $6, %ebx + je L(Exit6) + cmp $7, %ebx + je L(Exit7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + SAVE_RESULT (8) + RETURN1 + + .p2align 4 +L(ExitHigh8Case3): + cmp $12, %ebx + ja L(ExitHigh12Case3) + + cmp $9, %ebx + je L(Exit9) + cmp $10, %ebx + je L(Exit10) + cmp $11, %ebx + je L(Exit11) + movlpd (%ecx), %xmm0 + movl 8(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 8(%edx) + SAVE_RESULT (12) + RETURN1 + + .p2align 4 +L(ExitHigh12Case3): + cmp $13, %ebx + je L(Exit13) + cmp $14, %ebx + je L(Exit14) + cmp $15, %ebx + je L(Exit15) + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + SAVE_RESULT (16) + RETURN1 + +# endif + + .p2align 4 +L(Exit1): + movb (%ecx), %al + movb %al, (%edx) + SAVE_RESULT (0) +# ifdef USE_AS_STRNCPY + sub $1, %ebx + lea 1(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit2): + movw (%ecx), %ax + movw %ax, (%edx) + SAVE_RESULT (1) +# ifdef USE_AS_STRNCPY + sub $2, %ebx + lea 2(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + SAVE_RESULT (2) +# ifdef USE_AS_STRNCPY + sub $3, %ebx + lea 3(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + SAVE_RESULT (4) +# ifdef USE_AS_STRNCPY + sub $5, %ebx + lea 5(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + SAVE_RESULT (5) +# ifdef USE_AS_STRNCPY + sub $6, %ebx + lea 6(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + SAVE_RESULT (6) +# ifdef USE_AS_STRNCPY + sub $7, %ebx + lea 7(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit9): + movlpd (%ecx), %xmm0 + movb 8(%ecx), %al + movlpd %xmm0, (%edx) + movb %al, 8(%edx) + SAVE_RESULT (8) +# ifdef USE_AS_STRNCPY + sub $9, %ebx + lea 9(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit10): + movlpd (%ecx), %xmm0 + movw 8(%ecx), %ax + movlpd %xmm0, (%edx) + movw %ax, 8(%edx) + SAVE_RESULT (9) +# ifdef USE_AS_STRNCPY + sub $10, %ebx + lea 10(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit11): + movlpd (%ecx), %xmm0 + movl 7(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 7(%edx) + SAVE_RESULT (10) +# ifdef USE_AS_STRNCPY + sub $11, %ebx + lea 11(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit13): + movlpd (%ecx), %xmm0 + movlpd 5(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 5(%edx) + SAVE_RESULT (12) +# ifdef USE_AS_STRNCPY + sub $13, %ebx + lea 13(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit14): + movlpd (%ecx), %xmm0 + movlpd 6(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 6(%edx) + SAVE_RESULT (13) +# ifdef USE_AS_STRNCPY + sub $14, %ebx + lea 14(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + + .p2align 4 +L(Exit15): + movlpd (%ecx), %xmm0 + movlpd 7(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 7(%edx) + SAVE_RESULT (14) +# ifdef USE_AS_STRNCPY + sub $15, %ebx + lea 15(%edx), %ecx + jnz L(StrncpyFillTailWithZero1) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN1 + +CFI_POP (%edi) + +# ifdef USE_AS_STRNCPY + .p2align 4 +L(Fill0): + RETURN + + .p2align 4 +L(Fill1): + movb %dl, (%ecx) + RETURN + + .p2align 4 +L(Fill2): + movw %dx, (%ecx) + RETURN + + .p2align 4 +L(Fill3): + movw %dx, (%ecx) + movb %dl, 2(%ecx) + RETURN + + .p2align 4 +L(Fill4): + movl %edx, (%ecx) + RETURN + + .p2align 4 +L(Fill5): + movl %edx, (%ecx) + movb %dl, 4(%ecx) + RETURN + + .p2align 4 +L(Fill6): + movl %edx, (%ecx) + movw %dx, 4(%ecx) + RETURN + + .p2align 4 +L(Fill7): + movl %edx, (%ecx) + movl %edx, 3(%ecx) + RETURN + + .p2align 4 +L(Fill8): + movlpd %xmm0, (%ecx) + RETURN + + .p2align 4 +L(Fill9): + movlpd %xmm0, (%ecx) + movb %dl, 8(%ecx) + RETURN + + .p2align 4 +L(Fill10): + movlpd %xmm0, (%ecx) + movw %dx, 8(%ecx) + RETURN + + .p2align 4 +L(Fill11): + movlpd %xmm0, (%ecx) + movl %edx, 7(%ecx) + RETURN + + .p2align 4 +L(Fill12): + movlpd %xmm0, (%ecx) + movl %edx, 8(%ecx) + RETURN + + .p2align 4 +L(Fill13): + movlpd %xmm0, (%ecx) + movlpd %xmm0, 5(%ecx) + RETURN + + .p2align 4 +L(Fill14): + movlpd %xmm0, (%ecx) + movlpd %xmm0, 6(%ecx) + RETURN + + .p2align 4 +L(Fill15): + movlpd %xmm0, (%ecx) + movlpd %xmm0, 7(%ecx) + RETURN + + .p2align 4 +L(Fill16): + movlpd %xmm0, (%ecx) + movlpd %xmm0, 8(%ecx) + RETURN + + .p2align 4 +L(StrncpyFillExit1): + lea 16(%ebx), %ebx +L(FillFrom1To16Bytes): + test %ebx, %ebx + jz L(Fill0) + cmp $16, %ebx + je L(Fill16) + cmp $8, %ebx + je L(Fill8) + jg L(FillMore8) + cmp $4, %ebx + je L(Fill4) + jg L(FillMore4) + cmp $2, %ebx + jl L(Fill1) + je L(Fill2) + jg L(Fill3) +L(FillMore8): /* but less than 16 */ + cmp $12, %ebx + je L(Fill12) + jl L(FillLess12) + cmp $14, %ebx + jl L(Fill13) + je L(Fill14) + jg L(Fill15) +L(FillMore4): /* but less than 8 */ + cmp $6, %ebx + jl L(Fill5) + je L(Fill6) + jg L(Fill7) +L(FillLess12): /* but more than 8 */ + cmp $10, %ebx + jl L(Fill9) + je L(Fill10) + jmp L(Fill11) + + CFI_PUSH(%edi) + + .p2align 4 +L(StrncpyFillTailWithZero1): + POP (%edi) +L(StrncpyFillTailWithZero): + pxor %xmm0, %xmm0 + xor %edx, %edx + sub $16, %ebx + jbe L(StrncpyFillExit1) + + movlpd %xmm0, (%ecx) + movlpd %xmm0, 8(%ecx) + + lea 16(%ecx), %ecx + + mov %ecx, %edx + and $0xf, %edx + sub %edx, %ecx + add %edx, %ebx + xor %edx, %edx + sub $64, %ebx + jb L(StrncpyFillLess64) + +L(StrncpyFillLoopMovdqa): + movdqa %xmm0, (%ecx) + movdqa %xmm0, 16(%ecx) + movdqa %xmm0, 32(%ecx) + movdqa %xmm0, 48(%ecx) + lea 64(%ecx), %ecx + sub $64, %ebx + jae L(StrncpyFillLoopMovdqa) + +L(StrncpyFillLess64): + add $32, %ebx + jl L(StrncpyFillLess32) + movdqa %xmm0, (%ecx) + movdqa %xmm0, 16(%ecx) + lea 32(%ecx), %ecx + sub $16, %ebx + jl L(StrncpyFillExit1) + movdqa %xmm0, (%ecx) + lea 16(%ecx), %ecx + jmp L(FillFrom1To16Bytes) + +L(StrncpyFillLess32): + add $16, %ebx + jl L(StrncpyFillExit1) + movdqa %xmm0, (%ecx) + lea 16(%ecx), %ecx + jmp L(FillFrom1To16Bytes) +# endif + + .p2align 4 +L(ExitTail1): + movb (%ecx), %al + movb %al, (%edx) + SAVE_RESULT_TAIL (0) +# ifdef USE_AS_STRNCPY + sub $1, %ebx + lea 1(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail2): + movw (%ecx), %ax + movw %ax, (%edx) + SAVE_RESULT_TAIL (1) +# ifdef USE_AS_STRNCPY + sub $2, %ebx + lea 2(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + SAVE_RESULT_TAIL (2) +# ifdef USE_AS_STRNCPY + sub $3, %ebx + lea 3(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail4): + movl (%ecx), %eax + movl %eax, (%edx) + SAVE_RESULT_TAIL (3) +# ifdef USE_AS_STRNCPY + sub $4, %ebx + lea 4(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + SAVE_RESULT_TAIL (4) +# ifdef USE_AS_STRNCPY + sub $5, %ebx + lea 5(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + SAVE_RESULT_TAIL (5) +# ifdef USE_AS_STRNCPY + sub $6, %ebx + lea 6(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + SAVE_RESULT_TAIL (6) +# ifdef USE_AS_STRNCPY + sub $7, %ebx + lea 7(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + SAVE_RESULT_TAIL (7) +# ifdef USE_AS_STRNCPY + sub $8, %ebx + lea 8(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# endif + RETURN + + .p2align 4 +L(ExitTail9): + movlpd (%ecx), %xmm0 + movb 8(%ecx), %al + movlpd %xmm0, (%edx) + movb %al, 8(%edx) + SAVE_RESULT_TAIL (8) +# ifdef USE_AS_STRNCPY + sub $9, %ebx + lea 9(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail10): + movlpd (%ecx), %xmm0 + movw 8(%ecx), %ax + movlpd %xmm0, (%edx) + movw %ax, 8(%edx) + SAVE_RESULT_TAIL (9) +# ifdef USE_AS_STRNCPY + sub $10, %ebx + lea 10(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail11): + movlpd (%ecx), %xmm0 + movl 7(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 7(%edx) + SAVE_RESULT_TAIL (10) +# ifdef USE_AS_STRNCPY + sub $11, %ebx + lea 11(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail12): + movlpd (%ecx), %xmm0 + movl 8(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 8(%edx) + SAVE_RESULT_TAIL (11) +# ifdef USE_AS_STRNCPY + sub $12, %ebx + lea 12(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail13): + movlpd (%ecx), %xmm0 + movlpd 5(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 5(%edx) + SAVE_RESULT_TAIL (12) +# ifdef USE_AS_STRNCPY + sub $13, %ebx + lea 13(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail14): + movlpd (%ecx), %xmm0 + movlpd 6(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 6(%edx) + SAVE_RESULT_TAIL (13) +# ifdef USE_AS_STRNCPY + sub $14, %ebx + lea 14(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN + + .p2align 4 +L(ExitTail15): + movlpd (%ecx), %xmm0 + movlpd 7(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 7(%edx) + SAVE_RESULT_TAIL (14) +# ifdef USE_AS_STRNCPY + sub $15, %ebx + lea 15(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# endif + RETURN + + .p2align 4 +L(ExitTail16): + movdqu (%ecx), %xmm0 + movdqu %xmm0, (%edx) + SAVE_RESULT_TAIL (15) +# ifdef USE_AS_STRNCPY + sub $16, %ebx + lea 16(%edx), %ecx + jnz L(StrncpyFillTailWithZero) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif +# endif + RETURN +#endif + +#ifdef USE_AS_STRNCPY +# if !defined(USE_AS_STRCAT) && !defined(USE_AS_STRLCPY) + CFI_PUSH (%esi) + CFI_PUSH (%edi) +# endif + .p2align 4 +L(StrncpyLeaveCase2OrCase3): + test %eax, %eax + jnz L(Aligned64LeaveCase2) + +L(Aligned64LeaveCase3): + add $48, %ebx + jle L(CopyFrom1To16BytesCase3) + movaps %xmm4, -64(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase3) + movaps %xmm5, -48(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase3) + movaps %xmm6, -32(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx + jmp L(CopyFrom1To16BytesCase3) + +L(Aligned64LeaveCase2): + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %eax + add $48, %ebx + jle L(CopyFrom1To16BytesCase2OrCase3) + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqb %xmm5, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm4, -64(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqb %xmm6, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm5, -48(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqb %xmm7, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm6, -32(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx + jmp L(CopyFrom1To16BytesCase2) + +/*--------------------------------------------------*/ + .p2align 4 +L(StrncpyExit1Case2OrCase3): + movlpd (%ecx), %xmm0 + movlpd 7(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 7(%edx) + mov $15, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit2Case2OrCase3): + movlpd (%ecx), %xmm0 + movlpd 6(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 6(%edx) + mov $14, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit3Case2OrCase3): + movlpd (%ecx), %xmm0 + movlpd 5(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 5(%edx) + mov $13, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit4Case2OrCase3): + movlpd (%ecx), %xmm0 + movl 8(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 8(%edx) + mov $12, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit5Case2OrCase3): + movlpd (%ecx), %xmm0 + movl 7(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 7(%edx) + mov $11, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit6Case2OrCase3): + movlpd (%ecx), %xmm0 + movl 6(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 6(%edx) + mov $10, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit7Case2OrCase3): + movlpd (%ecx), %xmm0 + movl 5(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 5(%edx) + mov $9, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit8Case2OrCase3): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + mov $8, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit9Case2OrCase3): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + mov $7, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit10Case2OrCase3): + movlpd -1(%ecx), %xmm0 + movlpd %xmm0, -1(%edx) + mov $6, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit11Case2OrCase3): + movlpd -2(%ecx), %xmm0 + movlpd %xmm0, -2(%edx) + mov $5, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit12Case2OrCase3): + movl (%ecx), %esi + movl %esi, (%edx) + mov $4, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit13Case2OrCase3): + movl -1(%ecx), %esi + movl %esi, -1(%edx) + mov $3, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit14Case2OrCase3): + movl -2(%ecx), %esi + movl %esi, -2(%edx) + mov $2, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + + .p2align 4 +L(StrncpyExit15Case2OrCase3): + movl -3(%ecx), %esi + movl %esi, -3(%edx) + mov $1, %esi + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave1): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit1) + palignr $1, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 31(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit1) + palignr $1, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit1) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit1) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit1): + lea 15(%edx, %esi), %edx + lea 15(%ecx, %esi), %ecx + movdqu -16(%ecx), %xmm0 + xor %esi, %esi + movdqu %xmm0, -16(%edx) + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave2): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit2) + palignr $2, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 30(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit2) + palignr $2, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit2) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit2) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit2): + lea 14(%edx, %esi), %edx + lea 14(%ecx, %esi), %ecx + movdqu -16(%ecx), %xmm0 + xor %esi, %esi + movdqu %xmm0, -16(%edx) + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave3): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit3) + palignr $3, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 29(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit3) + palignr $3, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit3) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit3) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit3): + lea 13(%edx, %esi), %edx + lea 13(%ecx, %esi), %ecx + movdqu -16(%ecx), %xmm0 + xor %esi, %esi + movdqu %xmm0, -16(%edx) + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave4): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit4) + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit4) + palignr $4, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit4) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit4) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit4): + lea 12(%edx, %esi), %edx + lea 12(%ecx, %esi), %ecx + movlpd -12(%ecx), %xmm0 + movl -4(%ecx), %eax + movlpd %xmm0, -12(%edx) + movl %eax, -4(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave5): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit5) + palignr $5, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 27(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit5) + palignr $5, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit5) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit5) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit5): + lea 11(%edx, %esi), %edx + lea 11(%ecx, %esi), %ecx + movlpd -11(%ecx), %xmm0 + movl -4(%ecx), %eax + movlpd %xmm0, -11(%edx) + movl %eax, -4(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave6): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit6) + palignr $6, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 26(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit6) + palignr $6, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit6) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit6) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit6): + lea 10(%edx, %esi), %edx + lea 10(%ecx, %esi), %ecx + + movlpd -10(%ecx), %xmm0 + movw -2(%ecx), %ax + movlpd %xmm0, -10(%edx) + movw %ax, -2(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave7): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit7) + palignr $7, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 25(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit7) + palignr $7, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit7) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit7) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit7): + lea 9(%edx, %esi), %edx + lea 9(%ecx, %esi), %ecx + + movlpd -9(%ecx), %xmm0 + movb -1(%ecx), %ah + movlpd %xmm0, -9(%edx) + movb %ah, -1(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave8): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit8) + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit8) + palignr $8, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit8) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit8) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit8): + lea 8(%edx, %esi), %edx + lea 8(%ecx, %esi), %ecx + movlpd -8(%ecx), %xmm0 + movlpd %xmm0, -8(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave9): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit9) + palignr $9, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 23(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit9) + palignr $9, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit9) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit9) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit9): + lea 7(%edx, %esi), %edx + lea 7(%ecx, %esi), %ecx + + movlpd -8(%ecx), %xmm0 + movlpd %xmm0, -8(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave10): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit10) + palignr $10, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 22(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit10) + palignr $10, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit10) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit10) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit10): + lea 6(%edx, %esi), %edx + lea 6(%ecx, %esi), %ecx + + movlpd -8(%ecx), %xmm0 + movlpd %xmm0, -8(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave11): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit11) + palignr $11, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 21(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit11) + palignr $11, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit11) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit11) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit11): + lea 5(%edx, %esi), %edx + lea 5(%ecx, %esi), %ecx + movl -5(%ecx), %esi + movb -1(%ecx), %ah + movl %esi, -5(%edx) + movb %ah, -1(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave12): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit12) + palignr $12, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit12) + palignr $12, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit12) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit12) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit12): + lea 4(%edx, %esi), %edx + lea 4(%ecx, %esi), %ecx + movl -4(%ecx), %eax + movl %eax, -4(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave13): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit13) + palignr $13, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 19(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit13) + palignr $13, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit13) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit13) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit13): + lea 3(%edx, %esi), %edx + lea 3(%ecx, %esi), %ecx + + movl -4(%ecx), %eax + movl %eax, -4(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave14): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit14) + palignr $14, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 18(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit14) + palignr $14, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit14) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit14) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit14): + lea 2(%edx, %esi), %edx + lea 2(%ecx, %esi), %ecx + movw -2(%ecx), %ax + movw %ax, -2(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) + +L(StrncpyLeave15): + movaps %xmm2, %xmm3 + add $48, %ebx + jle L(StrncpyExit15) + palignr $15, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 17(%ecx), %xmm2 + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit15) + palignr $15, %xmm3, %xmm2 + movaps %xmm2, 16(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit15) + movaps %xmm4, 32(%edx) + lea 16(%esi), %esi + sub $16, %ebx + jbe L(StrncpyExit15) + movaps %xmm5, 48(%edx) + lea 16(%esi), %esi + lea -16(%ebx), %ebx +L(StrncpyExit15): + lea 1(%edx, %esi), %edx + lea 1(%ecx, %esi), %ecx + movb -1(%ecx), %ah + movb %ah, -1(%edx) + xor %esi, %esi + jmp L(CopyFrom1To16BytesCase3) +#endif + +#if !defined USE_AS_STRCAT && ! defined USE_AS_STRLCPY +# ifdef USE_AS_STRNCPY + CFI_POP (%esi) + CFI_POP (%edi) + + .p2align 4 +L(ExitTail0): + movl %edx, %eax + RETURN + + .p2align 4 +L(StrncpyExit15Bytes): + cmp $12, %ebx + jbe L(StrncpyExit12Bytes) + cmpb $0, 8(%ecx) + jz L(ExitTail9) + cmpb $0, 9(%ecx) + jz L(ExitTail10) + cmpb $0, 10(%ecx) + jz L(ExitTail11) + cmpb $0, 11(%ecx) + jz L(ExitTail12) + cmp $13, %ebx + je L(ExitTail13) + cmpb $0, 12(%ecx) + jz L(ExitTail13) + cmp $14, %ebx + je L(ExitTail14) + cmpb $0, 13(%ecx) + jz L(ExitTail14) + movlpd (%ecx), %xmm0 + movlpd 7(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 7(%edx) +# ifdef USE_AS_STPCPY + lea 14(%edx), %eax + cmpb $1, (%eax) + sbb $-1, %eax +# else + movl %edx, %eax +# endif + RETURN + + .p2align 4 +L(StrncpyExit12Bytes): + cmp $9, %ebx + je L(ExitTail9) + cmpb $0, 8(%ecx) + jz L(ExitTail9) + cmp $10, %ebx + je L(ExitTail10) + cmpb $0, 9(%ecx) + jz L(ExitTail10) + cmp $11, %ebx + je L(ExitTail11) + cmpb $0, 10(%ecx) + jz L(ExitTail11) + movlpd (%ecx), %xmm0 + movl 8(%ecx), %eax + movlpd %xmm0, (%edx) + movl %eax, 8(%edx) + SAVE_RESULT_TAIL (11) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif + RETURN + + .p2align 4 +L(StrncpyExit8Bytes): + cmp $4, %ebx + jbe L(StrncpyExit4Bytes) + cmpb $0, (%ecx) + jz L(ExitTail1) + cmpb $0, 1(%ecx) + jz L(ExitTail2) + cmpb $0, 2(%ecx) + jz L(ExitTail3) + cmpb $0, 3(%ecx) + jz L(ExitTail4) + + cmp $5, %ebx + je L(ExitTail5) + cmpb $0, 4(%ecx) + jz L(ExitTail5) + cmp $6, %ebx + je L(ExitTail6) + cmpb $0, 5(%ecx) + jz L(ExitTail6) + cmp $7, %ebx + je L(ExitTail7) + cmpb $0, 6(%ecx) + jz L(ExitTail7) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) +# ifdef USE_AS_STPCPY + lea 7(%edx), %eax + cmpb $1, (%eax) + sbb $-1, %eax +# else + movl %edx, %eax +# endif + RETURN + + .p2align 4 +L(StrncpyExit4Bytes): + test %ebx, %ebx + jz L(ExitTail0) + cmp $1, %ebx + je L(ExitTail1) + cmpb $0, (%ecx) + jz L(ExitTail1) + cmp $2, %ebx + je L(ExitTail2) + cmpb $0, 1(%ecx) + jz L(ExitTail2) + cmp $3, %ebx + je L(ExitTail3) + cmpb $0, 2(%ecx) + jz L(ExitTail3) + movl (%ecx), %eax + movl %eax, (%edx) + SAVE_RESULT_TAIL (3) +# ifdef USE_AS_STPCPY + cmpb $1, (%eax) + sbb $-1, %eax +# endif + RETURN +# endif + +END (STRCPY) +#endif
diff --git a/libc/arch-x86/atom/string/ssse3-strlcat-atom.S b/libc/arch-x86/atom/string/ssse3-strlcat-atom.S new file mode 100644 index 0000000..daaf254 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strlcat-atom.S
@@ -0,0 +1,1225 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Optimized strlcat with SSSE3 */ + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) +#define L(label) .L##Prolog_##label + +#define DST 4 +#define SRC DST+8 +#define LEN SRC+4 + + .text +ENTRY (strlcat) + mov DST(%esp), %edx + PUSH (%ebx) + mov LEN(%esp), %ebx + sub $4, %ebx + jbe L(len_less4_prolog) + +#define RETURN jmp L(StrcpyStep) +#define edi ebx + +#define USE_AS_STRNLEN +#define USE_AS_STRCAT +#define USE_AS_STRLCAT + +#include "sse2-strlen-atom.S" + + .p2align 4 +L(StrcpyStep): + +#undef edi +#undef L +#define L(label) .L##label +#undef RETURN +#define RETURN POP (%ebx); ret; CFI_PUSH (%ebx); +#define RETURN1 POP (%edi); POP (%ebx); ret; CFI_PUSH (%ebx); CFI_PUSH (%edi) + + movl SRC(%esp), %ecx + movl LEN(%esp), %ebx + + cmp %eax, %ebx + je L(CalculateLengthOfSrcProlog) + sub %eax, %ebx + + test %ebx, %ebx + jz L(CalculateLengthOfSrcProlog) + + mov DST + 4(%esp), %edx + + PUSH (%edi) + add %eax, %edx + mov %ecx, %edi + sub %eax, %edi + + cmp $8, %ebx + jbe L(StrncpyExit8Bytes) + + cmpb $0, (%ecx) + jz L(Exit1) + cmpb $0, 1(%ecx) + jz L(Exit2) + cmpb $0, 2(%ecx) + jz L(Exit3) + cmpb $0, 3(%ecx) + jz L(Exit4) + cmpb $0, 4(%ecx) + jz L(Exit5) + cmpb $0, 5(%ecx) + jz L(Exit6) + cmpb $0, 6(%ecx) + jz L(Exit7) + cmpb $0, 7(%ecx) + jz L(Exit8) + cmp $16, %ebx + jb L(StrncpyExit15Bytes) + cmpb $0, 8(%ecx) + jz L(Exit9) + cmpb $0, 9(%ecx) + jz L(Exit10) + cmpb $0, 10(%ecx) + jz L(Exit11) + cmpb $0, 11(%ecx) + jz L(Exit12) + cmpb $0, 12(%ecx) + jz L(Exit13) + cmpb $0, 13(%ecx) + jz L(Exit14) + cmpb $0, 14(%ecx) + jz L(Exit15) + cmpb $0, 15(%ecx) + jz L(Exit16) + cmp $16, %ebx + je L(StrlcpyExit16) + +#define USE_AS_STRNCPY +#include "ssse3-strcpy-atom.S" + + .p2align 4 +L(CopyFrom1To16Bytes): + add %esi, %edx + add %esi, %ecx + + POP (%esi) + test %al, %al + jz L(ExitHigh8) + +L(CopyFrom1To16BytesLess8): + mov %al, %ah + and $15, %ah + jz L(ExitHigh4) + + test $0x01, %al + jnz L(Exit1) + test $0x02, %al + jnz L(Exit2) + test $0x04, %al + jnz L(Exit3) +L(Exit4): + movl (%ecx), %eax + movl %eax, (%edx) + + lea 3(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh4): + test $0x10, %al + jnz L(Exit5) + test $0x20, %al + jnz L(Exit6) + test $0x40, %al + jnz L(Exit7) +L(Exit8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + lea 7(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh8): + mov %ah, %al + and $15, %al + jz L(ExitHigh12) + + test $0x01, %ah + jnz L(Exit9) + test $0x02, %ah + jnz L(Exit10) + test $0x04, %ah + jnz L(Exit11) +L(Exit12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + lea 11(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh12): + test $0x10, %ah + jnz L(Exit13) + test $0x20, %ah + jnz L(Exit14) + test $0x40, %ah + jnz L(Exit15) +L(Exit16): + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + + lea 15(%ecx), %eax + sub %edi, %eax + RETURN1 + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2): + add $16, %ebx + add %esi, %ecx + add %esi, %edx + + POP (%esi) + + test %al, %al + jz L(ExitHighCase2) + + cmp $8, %ebx + ja L(CopyFrom1To16BytesLess8) + + test $0x01, %al + jnz L(Exit1) + cmp $1, %ebx + je L(StrlcpyExit1) + test $0x02, %al + jnz L(Exit2) + cmp $2, %ebx + je L(StrlcpyExit2) + test $0x04, %al + jnz L(Exit3) + cmp $3, %ebx + je L(StrlcpyExit3) + test $0x08, %al + jnz L(Exit4) + cmp $4, %ebx + je L(StrlcpyExit4) + test $0x10, %al + jnz L(Exit5) + cmp $5, %ebx + je L(StrlcpyExit5) + test $0x20, %al + jnz L(Exit6) + cmp $6, %ebx + je L(StrlcpyExit6) + test $0x40, %al + jnz L(Exit7) + cmp $7, %ebx + je L(StrlcpyExit7) + test $0x80, %al + jnz L(Exit8) + jmp L(StrlcpyExit8) + + .p2align 4 +L(ExitHighCase2): + cmp $8, %ebx + jbe L(CopyFrom1To16BytesLess8Case3) + + test $0x01, %ah + jnz L(Exit9) + cmp $9, %ebx + je L(StrlcpyExit9) + test $0x02, %ah + jnz L(Exit10) + cmp $10, %ebx + je L(StrlcpyExit10) + test $0x04, %ah + jnz L(Exit11) + cmp $11, %ebx + je L(StrlcpyExit11) + test $0x8, %ah + jnz L(Exit12) + cmp $12, %ebx + je L(StrlcpyExit12) + test $0x10, %ah + jnz L(Exit13) + cmp $13, %ebx + je L(StrlcpyExit13) + test $0x20, %ah + jnz L(Exit14) + cmp $14, %ebx + je L(StrlcpyExit14) + test $0x40, %ah + jnz L(Exit15) + cmp $15, %ebx + je L(StrlcpyExit15) + test $0x80, %ah + jnz L(Exit16) + jmp L(StrlcpyExit16) + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2OrCase3): + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + + .p2align 4 +L(CopyFrom1To16BytesCase3): + add $16, %ebx + add %esi, %edx + add %esi, %ecx + + POP (%esi) + + cmp $8, %ebx + ja L(ExitHigh8Case3) + +L(CopyFrom1To16BytesLess8Case3): + cmp $4, %ebx + ja L(ExitHigh4Case3) + + cmp $1, %ebx + je L(StrlcpyExit1) + cmp $2, %ebx + je L(StrlcpyExit2) + cmp $3, %ebx + je L(StrlcpyExit3) +L(StrlcpyExit4): + movb %bh, 3(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + lea 4(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh4Case3): + cmp $5, %ebx + je L(StrlcpyExit5) + cmp $6, %ebx + je L(StrlcpyExit6) + cmp $7, %ebx + je L(StrlcpyExit7) +L(StrlcpyExit8): + movb %bh, 7(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + lea 8(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh8Case3): + cmp $12, %ebx + ja L(ExitHigh12Case3) + + cmp $9, %ebx + je L(StrlcpyExit9) + cmp $10, %ebx + je L(StrlcpyExit10) + cmp $11, %ebx + je L(StrlcpyExit11) +L(StrlcpyExit12): + movb %bh, 11(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + lea 12(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh12Case3): + cmp $13, %ebx + je L(StrlcpyExit13) + cmp $14, %ebx + je L(StrlcpyExit14) + cmp $15, %ebx + je L(StrlcpyExit15) +L(StrlcpyExit16): + movb %bh, 15(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + lea 16(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(StrlcpyExit1): + movb %bh, (%edx) + + lea 1(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit1): + movb (%ecx), %al + movb %al, (%edx) + + mov %ecx, %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit2): + movb %bh, 1(%edx) + movb (%ecx), %al + movb %al, (%edx) + + lea 2(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit2): + movw (%ecx), %ax + movw %ax, (%edx) + movl %edi, %eax + + lea 1(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit3): + movb %bh, 2(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + + lea 3(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + lea 2(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit5): + movb %bh, 4(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl %edi, %eax + + lea 5(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + lea 4(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit6): + movb %bh, 5(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + lea 6(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + lea 5(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit7): + movb %bh, 6(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + lea 7(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + lea 6(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit9): + movb %bh, 8(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + lea 9(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit9): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + lea 8(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit10): + movb %bh, 9(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + lea 10(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit10): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + lea 9(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit11): + movb %bh, 10(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + lea 11(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit11): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + lea 10(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit13): + movb %bh, 12(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + lea 13(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit13): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + lea 12(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit14): + movb %bh, 13(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + lea 14(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit14): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + lea 13(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit15): + movb %bh, 14(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + lea 15(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit15): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + lea 14(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrncpyExit15Bytes): + cmp $12, %ebx + ja L(StrncpyExit15Bytes1) + + cmpb $0, 8(%ecx) + jz L(Exit9) + cmp $9, %ebx + je L(StrlcpyExit9) + + cmpb $0, 9(%ecx) + jz L(Exit10) + cmp $10, %ebx + je L(StrlcpyExit10) + + cmpb $0, 10(%ecx) + jz L(Exit11) + cmp $11, %ebx + je L(StrlcpyExit11) + + cmpb $0, 11(%ecx) + jz L(Exit12) + jmp L(StrlcpyExit12) + + .p2align 4 +L(StrncpyExit15Bytes1): + cmpb $0, 8(%ecx) + jz L(Exit9) + cmpb $0, 9(%ecx) + jz L(Exit10) + cmpb $0, 10(%ecx) + jz L(Exit11) + cmpb $0, 11(%ecx) + jz L(Exit12) + + cmpb $0, 12(%ecx) + jz L(Exit13) + cmp $13, %ebx + je L(StrlcpyExit13) + + cmpb $0, 13(%ecx) + jz L(Exit14) + cmp $14, %ebx + je L(StrlcpyExit14) + + cmpb $0, 14(%ecx) + jz L(Exit15) + jmp L(StrlcpyExit15) + + .p2align 4 +L(StrncpyExit8Bytes): + cmp $4, %ebx + ja L(StrncpyExit8Bytes1) + + cmpb $0, (%ecx) + jz L(Exit1) + cmp $1, %ebx + je L(StrlcpyExit1) + + cmpb $0, 1(%ecx) + jz L(Exit2) + cmp $2, %ebx + je L(StrlcpyExit2) + + cmpb $0, 2(%ecx) + jz L(Exit3) + cmp $3, %ebx + je L(StrlcpyExit3) + + cmpb $0, 3(%ecx) + jz L(Exit4) + jmp L(StrlcpyExit4) + + .p2align 4 +L(StrncpyExit8Bytes1): + cmpb $0, (%ecx) + jz L(Exit1) + cmpb $0, 1(%ecx) + jz L(Exit2) + cmpb $0, 2(%ecx) + jz L(Exit3) + cmpb $0, 3(%ecx) + jz L(Exit4) + + cmpb $0, 4(%ecx) + jz L(Exit5) + cmp $5, %ebx + je L(StrlcpyExit5) + + cmpb $0, 5(%ecx) + jz L(Exit6) + cmp $6, %ebx + je L(StrlcpyExit6) + + cmpb $0, 6(%ecx) + jz L(Exit7) + cmp $7, %ebx + je L(StrlcpyExit7) + + cmpb $0, 7(%ecx) + jz L(Exit8) + jmp L(StrlcpyExit8) + + CFI_POP (%edi) + + + .p2align 4 +L(Prolog_return_start_len): + movl LEN(%esp), %ebx + movl SRC(%esp), %ecx +L(CalculateLengthOfSrcProlog): + mov %ecx, %edx + sub %ebx, %ecx + + .p2align 4 +L(CalculateLengthOfSrc): + cmpb $0, (%edx) + jz L(exit_tail0) + cmpb $0, 1(%edx) + jz L(exit_tail1) + cmpb $0, 2(%edx) + jz L(exit_tail2) + cmpb $0, 3(%edx) + jz L(exit_tail3) + + cmpb $0, 4(%edx) + jz L(exit_tail4) + cmpb $0, 5(%edx) + jz L(exit_tail5) + cmpb $0, 6(%edx) + jz L(exit_tail6) + cmpb $0, 7(%edx) + jz L(exit_tail7) + + cmpb $0, 8(%edx) + jz L(exit_tail8) + cmpb $0, 9(%edx) + jz L(exit_tail9) + cmpb $0, 10(%edx) + jz L(exit_tail10) + cmpb $0, 11(%edx) + jz L(exit_tail11) + + cmpb $0, 12(%edx) + jz L(exit_tail12) + cmpb $0, 13(%edx) + jz L(exit_tail13) + cmpb $0, 14(%edx) + jz L(exit_tail14) + cmpb $0, 15(%edx) + jz L(exit_tail15) + + pxor %xmm0, %xmm0 + lea 16(%edx), %eax + add $16, %ecx + and $-16, %eax + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + pxor %xmm1, %xmm1 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + pxor %xmm2, %xmm2 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + pxor %xmm3, %xmm3 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + and $-0x40, %eax + + .p2align 4 +L(aligned_64_loop): + movaps (%eax), %xmm0 + movaps 16(%eax), %xmm1 + movaps 32(%eax), %xmm2 + movaps 48(%eax), %xmm6 + pminub %xmm1, %xmm0 + pminub %xmm6, %xmm2 + pminub %xmm0, %xmm2 + pcmpeqb %xmm3, %xmm2 + pmovmskb %xmm2, %edx + lea 64(%eax), %eax + test %edx, %edx + jz L(aligned_64_loop) + + pcmpeqb -64(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 48(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb -32(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm6, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + + .p2align 4 +L(exit): + sub %ecx, %eax + test %dl, %dl + jz L(exit_more_8) + + mov %dl, %cl + and $15, %cl + jz L(exit_more_4) + test $0x01, %dl + jnz L(exit_0) + test $0x02, %dl + jnz L(exit_1) + test $0x04, %dl + jnz L(exit_2) + add $3, %eax + RETURN + + .p2align 4 +L(exit_more_4): + test $0x10, %dl + jnz L(exit_4) + test $0x20, %dl + jnz L(exit_5) + test $0x40, %dl + jnz L(exit_6) + add $7, %eax + RETURN + + .p2align 4 +L(exit_more_8): + mov %dh, %ch + and $15, %ch + jz L(exit_more_12) + test $0x01, %dh + jnz L(exit_8) + test $0x02, %dh + jnz L(exit_9) + test $0x04, %dh + jnz L(exit_10) + add $11, %eax + RETURN + + .p2align 4 +L(exit_more_12): + test $0x10, %dh + jnz L(exit_12) + test $0x20, %dh + jnz L(exit_13) + test $0x40, %dh + jnz L(exit_14) + add $15, %eax +L(exit_0): + RETURN + + .p2align 4 +L(exit_1): + add $1, %eax + RETURN + +L(exit_2): + add $2, %eax + RETURN + +L(exit_3): + add $3, %eax + RETURN + +L(exit_4): + add $4, %eax + RETURN + +L(exit_5): + add $5, %eax + RETURN + +L(exit_6): + add $6, %eax + RETURN + +L(exit_7): + add $7, %eax + RETURN + +L(exit_8): + add $8, %eax + RETURN + +L(exit_9): + add $9, %eax + RETURN + +L(exit_10): + add $10, %eax + RETURN + +L(exit_11): + add $11, %eax + RETURN + +L(exit_12): + add $12, %eax + RETURN + +L(exit_13): + add $13, %eax + RETURN + +L(exit_14): + add $14, %eax + RETURN + +L(exit_15): + add $15, %eax + RETURN + +L(exit_tail0): + mov %edx, %eax + sub %ecx, %eax + RETURN + + .p2align 4 +L(exit_tail1): + lea 1(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail2): + lea 2(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail3): + lea 3(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail4): + lea 4(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail5): + lea 5(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail6): + lea 6(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail7): + lea 7(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail8): + lea 8(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail9): + lea 9(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail10): + lea 10(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail11): + lea 11(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail12): + lea 12(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail13): + lea 13(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail14): + lea 14(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail15): + lea 15(%edx), %eax + sub %ecx, %eax + RETURN + +END (strlcat)
diff --git a/libc/arch-x86/atom/string/ssse3-strlcpy-atom.S b/libc/arch-x86/atom/string/ssse3-strlcpy-atom.S new file mode 100644 index 0000000..cdb17cc --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strlcpy-atom.S
@@ -0,0 +1,1403 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STRNCPY +#define STRCPY strlcpy +#define STRLEN strlcpy +#define USE_AS_STRLCPY +#include "ssse3-strcpy-atom.S" + + .p2align 4 +L(CopyFrom1To16Bytes): + add %esi, %edx + add %esi, %ecx + + POP (%esi) + test %al, %al + jz L(ExitHigh8) + +L(CopyFrom1To16BytesLess8): + mov %al, %ah + and $15, %ah + jz L(ExitHigh4) + + test $0x01, %al + jnz L(Exit1) + test $0x02, %al + jnz L(Exit2) + test $0x04, %al + jnz L(Exit3) +L(Exit4): + movl (%ecx), %eax + movl %eax, (%edx) + + lea 3(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh4): + test $0x10, %al + jnz L(Exit5) + test $0x20, %al + jnz L(Exit6) + test $0x40, %al + jnz L(Exit7) +L(Exit8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + lea 7(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh8): + mov %ah, %al + and $15, %al + jz L(ExitHigh12) + + test $0x01, %ah + jnz L(Exit9) + test $0x02, %ah + jnz L(Exit10) + test $0x04, %ah + jnz L(Exit11) +L(Exit12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + lea 11(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(ExitHigh12): + test $0x10, %ah + jnz L(Exit13) + test $0x20, %ah + jnz L(Exit14) + test $0x40, %ah + jnz L(Exit15) +L(Exit16): + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + + lea 15(%ecx), %eax + sub %edi, %eax + RETURN1 + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2): + add $16, %ebx + add %esi, %ecx + add %esi, %edx + + POP (%esi) + + test %al, %al + jz L(ExitHighCase2) + + cmp $8, %ebx + ja L(CopyFrom1To16BytesLess8) + + test $0x01, %al + jnz L(Exit1) + cmp $1, %ebx + je L(StrlcpyExit1) + test $0x02, %al + jnz L(Exit2) + cmp $2, %ebx + je L(StrlcpyExit2) + test $0x04, %al + jnz L(Exit3) + cmp $3, %ebx + je L(StrlcpyExit3) + test $0x08, %al + jnz L(Exit4) + cmp $4, %ebx + je L(StrlcpyExit4) + test $0x10, %al + jnz L(Exit5) + cmp $5, %ebx + je L(StrlcpyExit5) + test $0x20, %al + jnz L(Exit6) + cmp $6, %ebx + je L(StrlcpyExit6) + test $0x40, %al + jnz L(Exit7) + cmp $7, %ebx + je L(StrlcpyExit7) + test $0x80, %al + jnz L(Exit8) + jmp L(StrlcpyExit8) + + .p2align 4 +L(ExitHighCase2): + cmp $8, %ebx + jbe L(CopyFrom1To16BytesLess8Case3) + + test $0x01, %ah + jnz L(Exit9) + cmp $9, %ebx + je L(StrlcpyExit9) + test $0x02, %ah + jnz L(Exit10) + cmp $10, %ebx + je L(StrlcpyExit10) + test $0x04, %ah + jnz L(Exit11) + cmp $11, %ebx + je L(StrlcpyExit11) + test $0x8, %ah + jnz L(Exit12) + cmp $12, %ebx + je L(StrlcpyExit12) + test $0x10, %ah + jnz L(Exit13) + cmp $13, %ebx + je L(StrlcpyExit13) + test $0x20, %ah + jnz L(Exit14) + cmp $14, %ebx + je L(StrlcpyExit14) + test $0x40, %ah + jnz L(Exit15) + cmp $15, %ebx + je L(StrlcpyExit15) + test $0x80, %ah + jnz L(Exit16) + jmp L(StrlcpyExit16) + + CFI_PUSH(%esi) + + .p2align 4 +L(CopyFrom1To16BytesCase2OrCase3): + test %eax, %eax + jnz L(CopyFrom1To16BytesCase2) + + .p2align 4 +L(CopyFrom1To16BytesCase3): + add $16, %ebx + add %esi, %edx + add %esi, %ecx + + POP (%esi) + + cmp $8, %ebx + ja L(ExitHigh8Case3) + +L(CopyFrom1To16BytesLess8Case3): + cmp $4, %ebx + ja L(ExitHigh4Case3) + + cmp $1, %ebx + je L(StrlcpyExit1) + cmp $2, %ebx + je L(StrlcpyExit2) + cmp $3, %ebx + je L(StrlcpyExit3) +L(StrlcpyExit4): + movb %bh, 3(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + lea 4(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh4Case3): + cmp $5, %ebx + je L(StrlcpyExit5) + cmp $6, %ebx + je L(StrlcpyExit6) + cmp $7, %ebx + je L(StrlcpyExit7) +L(StrlcpyExit8): + movb %bh, 7(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + lea 8(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh8Case3): + cmp $12, %ebx + ja L(ExitHigh12Case3) + + cmp $9, %ebx + je L(StrlcpyExit9) + cmp $10, %ebx + je L(StrlcpyExit10) + cmp $11, %ebx + je L(StrlcpyExit11) +L(StrlcpyExit12): + movb %bh, 11(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + lea 12(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(ExitHigh12Case3): + cmp $13, %ebx + je L(StrlcpyExit13) + cmp $14, %ebx + je L(StrlcpyExit14) + cmp $15, %ebx + je L(StrlcpyExit15) +L(StrlcpyExit16): + movb %bh, 15(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + lea 16(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(StrlcpyExit1): + movb %bh, (%edx) + + lea 1(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit1): + movb (%ecx), %al + movb %al, (%edx) + + mov %ecx, %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit2): + movb %bh, 1(%edx) + movb (%ecx), %al + movb %al, (%edx) + + lea 2(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit2): + movw (%ecx), %ax + movw %ax, (%edx) + movl %edi, %eax + + lea 1(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit3): + movb %bh, 2(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + + lea 3(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + lea 2(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit5): + movb %bh, 4(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl %edi, %eax + + lea 5(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + lea 4(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit6): + movb %bh, 5(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + lea 6(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + lea 5(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit7): + movb %bh, 6(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + lea 7(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + lea 6(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit9): + movb %bh, 8(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + lea 9(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit9): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + lea 8(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit10): + movb %bh, 9(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + lea 10(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit10): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + lea 9(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit11): + movb %bh, 10(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + lea 11(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit11): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + lea 10(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit13): + movb %bh, 12(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + lea 13(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit13): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + lea 12(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit14): + movb %bh, 13(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + lea 14(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit14): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + lea 13(%ecx), %eax + sub %edi, %eax + RETURN1 + + .p2align 4 +L(StrlcpyExit15): + movb %bh, 14(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + lea 15(%ecx), %edx + mov %edi, %ecx + POP (%edi) + jmp L(CalculateLengthOfSrc) + CFI_PUSH (%edi) + + .p2align 4 +L(Exit15): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + lea 14(%ecx), %eax + sub %edi, %eax + RETURN1 + + CFI_POP (%edi) + + .p2align 4 +L(StrlcpyExit0): + movl $0, %eax + RETURN + + .p2align 4 +L(StrncpyExit15Bytes): + cmp $12, %ebx + ja L(StrncpyExit15Bytes1) + + cmpb $0, 8(%ecx) + jz L(ExitTail9) + cmp $9, %ebx + je L(StrlcpyExitTail9) + + cmpb $0, 9(%ecx) + jz L(ExitTail10) + cmp $10, %ebx + je L(StrlcpyExitTail10) + + cmpb $0, 10(%ecx) + jz L(ExitTail11) + cmp $11, %ebx + je L(StrlcpyExitTail11) + + cmpb $0, 11(%ecx) + jz L(ExitTail12) + + movb %bh, 11(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + lea 12(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(StrncpyExit15Bytes1): + cmpb $0, 8(%ecx) + jz L(ExitTail9) + cmpb $0, 9(%ecx) + jz L(ExitTail10) + cmpb $0, 10(%ecx) + jz L(ExitTail11) + cmpb $0, 11(%ecx) + jz L(ExitTail12) + + cmpb $0, 12(%ecx) + jz L(ExitTail13) + cmp $13, %ebx + je L(StrlcpyExitTail13) + + cmpb $0, 13(%ecx) + jz L(ExitTail14) + cmp $14, %ebx + je L(StrlcpyExitTail14) + + cmpb $0, 14(%ecx) + jz L(ExitTail15) + + movb %bh, 14(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + lea 15(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(StrncpyExit8Bytes): + cmp $4, %ebx + ja L(StrncpyExit8Bytes1) + + test %ebx, %ebx + jz L(StrlcpyExitTail0) + + cmpb $0, (%ecx) + jz L(ExitTail1) + cmp $1, %ebx + je L(StrlcpyExitTail1) + + cmpb $0, 1(%ecx) + jz L(ExitTail2) + cmp $2, %ebx + je L(StrlcpyExitTail2) + + cmpb $0, 2(%ecx) + jz L(ExitTail3) + cmp $3, %ebx + je L(StrlcpyExitTail3) + + cmpb $0, 3(%ecx) + jz L(ExitTail4) + + movb %bh, 3(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + lea 4(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(StrncpyExit8Bytes1): + cmpb $0, (%ecx) + jz L(ExitTail1) + cmpb $0, 1(%ecx) + jz L(ExitTail2) + cmpb $0, 2(%ecx) + jz L(ExitTail3) + cmpb $0, 3(%ecx) + jz L(ExitTail4) + + cmpb $0, 4(%ecx) + jz L(ExitTail5) + cmp $5, %ebx + je L(StrlcpyExitTail5) + + cmpb $0, 5(%ecx) + jz L(ExitTail6) + cmp $6, %ebx + je L(StrlcpyExitTail6) + + cmpb $0, 6(%ecx) + jz L(ExitTail7) + cmp $7, %ebx + je L(StrlcpyExitTail7) + + cmpb $0, 7(%ecx) + jz L(ExitTail8) + + movb %bh, 7(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + lea 8(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(StrlcpyExitTail0): + mov %ecx, %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(StrlcpyExitTail1): + movb %bh, (%edx) + + lea 1(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail1): + movb (%ecx), %al + movb %al, (%edx) + + mov $0, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail2): + movb %bh, 1(%edx) + movb (%ecx), %al + movb %al, (%edx) + + lea 2(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail2): + movw (%ecx), %ax + movw %ax, (%edx) + movl %edx, %eax + + mov $1, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail3): + movb %bh, 2(%edx) + movw (%ecx), %ax + movw %ax, (%edx) + + lea 3(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail3): + movw (%ecx), %ax + movw %ax, (%edx) + movb 2(%ecx), %al + movb %al, 2(%edx) + + mov $2, %eax + RETURN + + .p2align 4 +L(ExitTail4): + movl (%ecx), %eax + movl %eax, (%edx) + + mov $3, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail5): + movb %bh, 4(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movl %edx, %eax + + lea 5(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail5): + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + mov $4, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail6): + movb %bh, 5(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movb 4(%ecx), %al + movb %al, 4(%edx) + + lea 6(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail6): + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + mov $5, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail7): + movb %bh, 6(%edx) + movl (%ecx), %eax + movl %eax, (%edx) + movw 4(%ecx), %ax + movw %ax, 4(%edx) + + lea 7(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail7): + movl (%ecx), %eax + movl %eax, (%edx) + movl 3(%ecx), %eax + movl %eax, 3(%edx) + + mov $6, %eax + RETURN + + .p2align 4 +L(ExitTail8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + mov $7, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail9): + movb %bh, 8(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + + lea 9(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail9): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + mov $8, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail10): + movb %bh, 9(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movb 8(%ecx), %al + movb %al, 8(%edx) + + lea 10(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail10): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + mov $9, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail11): + movb %bh, 10(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movw 8(%ecx), %ax + movw %ax, 8(%edx) + + lea 11(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail11): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 7(%ecx), %eax + movl %eax, 7(%edx) + + mov $10, %eax + RETURN + + .p2align 4 +L(ExitTail12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + mov $11, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail13): + movb %bh, 12(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + + lea 13(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail13): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + mov $12, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail14): + movb %bh, 13(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 5(%ecx), %xmm0 + movlpd %xmm0, 5(%edx) + + lea 14(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail14): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 6(%ecx), %xmm0 + movlpd %xmm0, 6(%edx) + + mov $13, %eax + RETURN + + .p2align 4 +L(ExitTail15): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + mov $14, %eax + RETURN + + .p2align 4 +L(StrlcpyExitTail16): + movb %bh, 15(%edx) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movlpd 7(%ecx), %xmm0 + movlpd %xmm0, 7(%edx) + + lea 16(%ecx), %edx + jmp L(CalculateLengthOfSrc) + + .p2align 4 +L(ExitTail16): + movlpd (%ecx), %xmm0 + movlpd 8(%ecx), %xmm1 + movlpd %xmm0, (%edx) + movlpd %xmm1, 8(%edx) + + mov $15, %eax + RETURN + + .p2align 4 +L(CalculateLengthOfSrc): + xor %eax, %eax + cmpb $0, (%edx) + jz L(exit_tail0) + cmpb $0, 1(%edx) + jz L(exit_tail1) + cmpb $0, 2(%edx) + jz L(exit_tail2) + cmpb $0, 3(%edx) + jz L(exit_tail3) + + cmpb $0, 4(%edx) + jz L(exit_tail4) + cmpb $0, 5(%edx) + jz L(exit_tail5) + cmpb $0, 6(%edx) + jz L(exit_tail6) + cmpb $0, 7(%edx) + jz L(exit_tail7) + + cmpb $0, 8(%edx) + jz L(exit_tail8) + cmpb $0, 9(%edx) + jz L(exit_tail9) + cmpb $0, 10(%edx) + jz L(exit_tail10) + cmpb $0, 11(%edx) + jz L(exit_tail11) + + cmpb $0, 12(%edx) + jz L(exit_tail12) + cmpb $0, 13(%edx) + jz L(exit_tail13) + cmpb $0, 14(%edx) + jz L(exit_tail14) + cmpb $0, 15(%edx) + jz L(exit_tail15) + + pxor %xmm0, %xmm0 + lea 16(%edx), %eax + add $16, %ecx + and $-16, %eax + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + pxor %xmm1, %xmm1 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + pxor %xmm2, %xmm2 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + pxor %xmm3, %xmm3 + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm0 + pmovmskb %xmm0, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm1 + pmovmskb %xmm1, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm2 + pmovmskb %xmm2, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + pcmpeqb (%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 16(%eax), %eax + test %edx, %edx + jnz L(exit) + + and $-0x40, %eax + + .p2align 4 +L(aligned_64_loop): + movaps (%eax), %xmm0 + movaps 16(%eax), %xmm1 + movaps 32(%eax), %xmm2 + movaps 48(%eax), %xmm6 + pminub %xmm1, %xmm0 + pminub %xmm6, %xmm2 + pminub %xmm0, %xmm2 + pcmpeqb %xmm3, %xmm2 + pmovmskb %xmm2, %edx + lea 64(%eax), %eax + test %edx, %edx + jz L(aligned_64_loop) + + pcmpeqb -64(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea 48(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb -32(%eax), %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + test %edx, %edx + jnz L(exit) + + pcmpeqb %xmm6, %xmm3 + pmovmskb %xmm3, %edx + lea -16(%ecx), %ecx + + .p2align 4 +L(exit): + sub %ecx, %eax + test %dl, %dl + jz L(exit_more_8) + + mov %dl, %cl + and $15, %cl + jz L(exit_more_4) + test $0x01, %dl + jnz L(exit_0) + test $0x02, %dl + jnz L(exit_1) + test $0x04, %dl + jnz L(exit_2) + add $3, %eax + RETURN + + .p2align 4 +L(exit_more_4): + test $0x10, %dl + jnz L(exit_4) + test $0x20, %dl + jnz L(exit_5) + test $0x40, %dl + jnz L(exit_6) + add $7, %eax + RETURN + + .p2align 4 +L(exit_more_8): + mov %dh, %ch + and $15, %ch + jz L(exit_more_12) + test $0x01, %dh + jnz L(exit_8) + test $0x02, %dh + jnz L(exit_9) + test $0x04, %dh + jnz L(exit_10) + add $11, %eax + RETURN + + .p2align 4 +L(exit_more_12): + test $0x10, %dh + jnz L(exit_12) + test $0x20, %dh + jnz L(exit_13) + test $0x40, %dh + jnz L(exit_14) + add $15, %eax +L(exit_0): + RETURN + + .p2align 4 +L(exit_1): + add $1, %eax + RETURN + +L(exit_2): + add $2, %eax + RETURN + +L(exit_3): + add $3, %eax + RETURN + +L(exit_4): + add $4, %eax + RETURN + +L(exit_5): + add $5, %eax + RETURN + +L(exit_6): + add $6, %eax + RETURN + +L(exit_7): + add $7, %eax + RETURN + +L(exit_8): + add $8, %eax + RETURN + +L(exit_9): + add $9, %eax + RETURN + +L(exit_10): + add $10, %eax + RETURN + +L(exit_11): + add $11, %eax + RETURN + +L(exit_12): + add $12, %eax + RETURN + +L(exit_13): + add $13, %eax + RETURN + +L(exit_14): + add $14, %eax + RETURN + +L(exit_15): + add $15, %eax + RETURN + +L(exit_tail0): + mov %edx, %eax + sub %ecx, %eax + RETURN + + .p2align 4 +L(exit_tail1): + lea 1(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail2): + lea 2(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail3): + lea 3(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail4): + lea 4(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail5): + lea 5(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail6): + lea 6(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail7): + lea 7(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail8): + lea 8(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail9): + lea 9(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail10): + lea 10(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail11): + lea 11(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail12): + lea 12(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail13): + lea 13(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail14): + lea 14(%edx), %eax + sub %ecx, %eax + RETURN + +L(exit_tail15): + lea 15(%edx), %eax + sub %ecx, %eax + RETURN + +END (STRCPY) +
diff --git a/libc/arch-x86/atom/string/ssse3-strncat-atom.S b/libc/arch-x86/atom/string/ssse3-strncat-atom.S new file mode 100644 index 0000000..5618771 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strncat-atom.S
@@ -0,0 +1,34 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define STRCAT strncat +#define USE_AS_STRNCAT + +#include "ssse3-strcat-atom.S"
diff --git a/libc/arch-x86/atom/string/ssse3-strncmp-atom.S b/libc/arch-x86/atom/string/ssse3-strncmp-atom.S new file mode 100644 index 0000000..4762d7e --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strncmp-atom.S
@@ -0,0 +1,35 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#define USE_AS_STRNCMP +#define STRCMP strncmp +#include "ssse3-strcmp-atom.S" +
diff --git a/libc/arch-x86/atom/string/ssse3-strncpy-atom.S b/libc/arch-x86/atom/string/ssse3-strncpy-atom.S new file mode 100644 index 0000000..0948b6d --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-strncpy-atom.S
@@ -0,0 +1,33 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STRNCPY +#define STRCPY strncpy +#include "ssse3-strcpy-atom.S"
diff --git a/libc/arch-x86/atom/string/ssse3-wcscat-atom.S b/libc/arch-x86/atom/string/ssse3-wcscat-atom.S new file mode 100644 index 0000000..8a389a3 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-wcscat-atom.S
@@ -0,0 +1,114 @@ +/* +Copyright (c) 2011 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 4 +#define STR1 PARMS+4 +#define STR2 STR1+4 + +#define USE_AS_WCSCAT + +.text +ENTRY (wcscat) + PUSH (%edi) + mov STR1(%esp), %edi + mov %edi, %edx + +#define RETURN jmp L(WcscpyAtom) +#include "sse2-wcslen-atom.S" + +L(WcscpyAtom): + shl $2, %eax + mov STR2(%esp), %ecx + lea (%edi, %eax), %edx + + cmpl $0, (%ecx) + jz L(Exit4) + cmpl $0, 4(%ecx) + jz L(Exit8) + cmpl $0, 8(%ecx) + jz L(Exit12) + cmpl $0, 12(%ecx) + jz L(Exit16) + +#undef RETURN +#define RETURN POP(%edi); ret; CFI_PUSH(%edi) +#include "ssse3-wcscpy-atom.S" + +END (wcscat)
diff --git a/libc/arch-x86/atom/string/ssse3-wcscpy-atom.S b/libc/arch-x86/atom/string/ssse3-wcscpy-atom.S new file mode 100644 index 0000000..27cb61e --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-wcscpy-atom.S
@@ -0,0 +1,652 @@ +/* +Copyright (c) 2011, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef USE_AS_WCSCAT + +# ifndef L +# define L(label) .L##label +# endif + +# ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +# endif + +# ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +# endif + +# ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +# endif + +# ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +# endif + +# ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +# endif + +# ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +# endif + +# ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +# endif + +# define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +# define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +# define PUSH(REG) pushl REG; CFI_PUSH (REG) +# define POP(REG) popl REG; CFI_POP (REG) + +# define PARMS 4 +# define RETURN POP (%edi); ret; CFI_PUSH (%edi) + +# define STR1 PARMS +# define STR2 STR1+4 +# define LEN STR2+4 + +.text +ENTRY (wcscpy) + mov STR1(%esp), %edx + mov STR2(%esp), %ecx + + cmpl $0, (%ecx) + jz L(ExitTail4) + cmpl $0, 4(%ecx) + jz L(ExitTail8) + cmpl $0, 8(%ecx) + jz L(ExitTail12) + cmpl $0, 12(%ecx) + jz L(ExitTail16) + + PUSH (%edi) + mov %edx, %edi +#endif + PUSH (%esi) + lea 16(%ecx), %esi + + and $-16, %esi + + pxor %xmm0, %xmm0 + pcmpeqd (%esi), %xmm0 + movdqu (%ecx), %xmm1 + movdqu %xmm1, (%edx) + + pmovmskb %xmm0, %eax + sub %ecx, %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + mov %edx, %eax + lea 16(%edx), %edx + and $-16, %edx + sub %edx, %eax + + sub %eax, %ecx + mov %ecx, %eax + and $0xf, %eax + mov $0, %esi + + jz L(Align16Both) + cmp $4, %eax + je L(Shl4) + cmp $8, %eax + je L(Shl8) + jmp L(Shl12) + +L(Align16Both): + movaps (%ecx), %xmm1 + movaps 16(%ecx), %xmm2 + movaps %xmm1, (%edx) + pcmpeqd %xmm2, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm3 + movaps %xmm2, (%edx, %esi) + pcmpeqd %xmm3, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm4 + movaps %xmm3, (%edx, %esi) + pcmpeqd %xmm4, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm1 + movaps %xmm4, (%edx, %esi) + pcmpeqd %xmm1, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm2 + movaps %xmm1, (%edx, %esi) + pcmpeqd %xmm2, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps 16(%ecx, %esi), %xmm3 + movaps %xmm2, (%edx, %esi) + pcmpeqd %xmm3, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps %xmm3, (%edx, %esi) + mov %ecx, %eax + lea 16(%ecx, %esi), %ecx + and $-0x40, %ecx + sub %ecx, %eax + sub %eax, %edx + + mov $-0x40, %esi + +L(Aligned64Loop): + movaps (%ecx), %xmm2 + movaps 32(%ecx), %xmm3 + movaps %xmm2, %xmm4 + movaps 16(%ecx), %xmm5 + movaps %xmm3, %xmm6 + movaps 48(%ecx), %xmm7 + pminub %xmm5, %xmm2 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + lea 64(%edx), %edx + pcmpeqd %xmm0, %xmm3 + lea 64(%ecx), %ecx + pmovmskb %xmm3, %eax + + test %eax, %eax + jnz L(Aligned64Leave) + movaps %xmm4, -64(%edx) + movaps %xmm5, -48(%edx) + movaps %xmm6, -32(%edx) + movaps %xmm7, -16(%edx) + jmp L(Aligned64Loop) + +L(Aligned64Leave): + pcmpeqd %xmm4, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqd %xmm5, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm4, -64(%edx) + lea 16(%esi), %esi + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + pcmpeqd %xmm6, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm5, -48(%edx) + lea 16(%esi), %esi + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + movaps %xmm6, -32(%edx) + pcmpeqd %xmm7, %xmm0 + pmovmskb %xmm0, %eax + lea 16(%esi), %esi + test %eax, %eax + jnz L(CopyFrom1To16Bytes) + + mov $-0x40, %esi + movaps %xmm7, -16(%edx) + jmp L(Aligned64Loop) + + .p2align 4 +L(Shl4): + movaps -4(%ecx), %xmm1 + movaps 12(%ecx), %xmm2 +L(Shl4Start): + pcmpeqd %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm1 + + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm3, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 28(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + + test %eax, %eax + jnz L(Shl4LoopExit) + + palignr $4, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 28(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -12(%ecx), %ecx + sub %eax, %edx + + movaps -4(%ecx), %xmm1 + +L(Shl4LoopStart): + movaps 12(%ecx), %xmm2 + movaps 28(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 44(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 60(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqd %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $4, %xmm4, %xmm5 + palignr $4, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl4Start) + + palignr $4, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $4, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl4LoopStart) + +L(Shl4LoopExit): + movlpd (%ecx), %xmm0 + movl 8(%ecx), %esi + movlpd %xmm0, (%edx) + movl %esi, 8(%edx) + POP (%esi) + add $12, %edx + add $12, %ecx + test %al, %al + jz L(ExitHigh) + test $0x01, %al + jnz L(Exit4) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edi, %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(Shl8): + movaps -8(%ecx), %xmm1 + movaps 8(%ecx), %xmm2 +L(Shl8Start): + pcmpeqd %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm1 + + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm3, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 24(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + + test %eax, %eax + jnz L(Shl8LoopExit) + + palignr $8, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 24(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -8(%ecx), %ecx + sub %eax, %edx + + movaps -8(%ecx), %xmm1 + +L(Shl8LoopStart): + movaps 8(%ecx), %xmm2 + movaps 24(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 40(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 56(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqd %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $8, %xmm4, %xmm5 + palignr $8, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl8Start) + + palignr $8, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $8, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl8LoopStart) + +L(Shl8LoopExit): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + POP (%esi) + add $8, %edx + add $8, %ecx + test %al, %al + jz L(ExitHigh) + test $0x01, %al + jnz L(Exit4) + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edi, %eax + RETURN + + CFI_PUSH (%esi) + + .p2align 4 +L(Shl12): + movaps -12(%ecx), %xmm1 + movaps 4(%ecx), %xmm2 +L(Shl12Start): + pcmpeqd %xmm2, %xmm0 + pmovmskb %xmm0, %eax + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm1 + + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm3, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + movaps %xmm2, %xmm3 + + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm1, %xmm2 + movaps %xmm2, (%edx) + movaps 20(%ecx), %xmm2 + + pcmpeqd %xmm2, %xmm0 + lea 16(%edx), %edx + pmovmskb %xmm0, %eax + lea 16(%ecx), %ecx + + test %eax, %eax + jnz L(Shl12LoopExit) + + palignr $12, %xmm3, %xmm2 + movaps %xmm2, (%edx) + lea 20(%ecx), %ecx + lea 16(%edx), %edx + + mov %ecx, %eax + and $-0x40, %ecx + sub %ecx, %eax + lea -4(%ecx), %ecx + sub %eax, %edx + + movaps -12(%ecx), %xmm1 + +L(Shl12LoopStart): + movaps 4(%ecx), %xmm2 + movaps 20(%ecx), %xmm3 + movaps %xmm3, %xmm6 + movaps 36(%ecx), %xmm4 + movaps %xmm4, %xmm7 + movaps 52(%ecx), %xmm5 + pminub %xmm2, %xmm6 + pminub %xmm5, %xmm7 + pminub %xmm6, %xmm7 + pcmpeqd %xmm0, %xmm7 + pmovmskb %xmm7, %eax + movaps %xmm5, %xmm7 + palignr $12, %xmm4, %xmm5 + palignr $12, %xmm3, %xmm4 + test %eax, %eax + jnz L(Shl12Start) + + palignr $12, %xmm2, %xmm3 + lea 64(%ecx), %ecx + palignr $12, %xmm1, %xmm2 + movaps %xmm7, %xmm1 + movaps %xmm5, 48(%edx) + movaps %xmm4, 32(%edx) + movaps %xmm3, 16(%edx) + movaps %xmm2, (%edx) + lea 64(%edx), %edx + jmp L(Shl12LoopStart) + +L(Shl12LoopExit): + movl (%ecx), %esi + movl %esi, (%edx) + mov $4, %esi + + .p2align 4 +L(CopyFrom1To16Bytes): + add %esi, %edx + add %esi, %ecx + + POP (%esi) + test %al, %al + jz L(ExitHigh) + test $0x01, %al + jnz L(Exit4) +L(Exit8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edi, %eax + RETURN + + .p2align 4 +L(ExitHigh): + test $0x01, %ah + jnz L(Exit12) +L(Exit16): + movdqu (%ecx), %xmm0 + movdqu %xmm0, (%edx) + movl %edi, %eax + RETURN + + .p2align 4 +L(Exit4): + movl (%ecx), %eax + movl %eax, (%edx) + movl %edi, %eax + RETURN + + .p2align 4 +L(Exit12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + movl %edi, %eax + RETURN + +CFI_POP (%edi) + + .p2align 4 +L(ExitTail4): + movl (%ecx), %eax + movl %eax, (%edx) + movl %edx, %eax + ret + + .p2align 4 +L(ExitTail8): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl %edx, %eax + ret + + .p2align 4 +L(ExitTail12): + movlpd (%ecx), %xmm0 + movlpd %xmm0, (%edx) + movl 8(%ecx), %eax + movl %eax, 8(%edx) + movl %edx, %eax + ret + + .p2align 4 +L(ExitTail16): + movdqu (%ecx), %xmm0 + movdqu %xmm0, (%edx) + movl %edx, %eax + ret + +#ifndef USE_AS_WCSCAT +END (wcscpy) +#endif
diff --git a/libc/arch-x86/atom/string/ssse3-wmemcmp-atom.S b/libc/arch-x86/atom/string/ssse3-wmemcmp-atom.S new file mode 100644 index 0000000..2c3fa02 --- /dev/null +++ b/libc/arch-x86/atom/string/ssse3-wmemcmp-atom.S
@@ -0,0 +1,35 @@ +/* +Copyright (c) 2011, 2012, 2013 Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define MEMCMP wmemcmp + +#define USE_WCHAR +#define USE_AS_WMEMCMP 1 +#include "ssse3-memcmp-atom.S"
diff --git a/libc/arch-x86/bionic/__bionic_clone.S b/libc/arch-x86/bionic/__bionic_clone.S new file mode 100644 index 0000000..1a6f642 --- /dev/null +++ b/libc/arch-x86/bionic/__bionic_clone.S
@@ -0,0 +1,65 @@ +#include <private/bionic_asm.h> + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); +ENTRY(__bionic_clone) + pushl %ebx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + # Load system call arguments into registers. + movl 16(%esp), %ebx # flags + movl 20(%esp), %ecx # child_stack + movl 24(%esp), %edx # parent_tid + movl 28(%esp), %esi # tls + movl 32(%esp), %edi # child_tid + + # Copy 'fn' and 'arg' onto the child stack + movl 36(%esp), %eax # Read 'fn'. + movl %eax, -16(%ecx) # Write 'fn'. + movl 40(%esp), %eax # Read 'arg'. + movl %eax, -12(%ecx) # Write 'arg'. + subl $16, %ecx + + # Make the system call. + movl $__NR_clone, %eax + int $0x80 + + # Check result. + testl %eax, %eax + jz .L_bc_child + jg .L_bc_parent + + # An error occurred, so set errno and return -1. + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp + jmp .L_bc_return + +.L_bc_child: + # We don't want anyone to unwind past this point. + .cfi_undefined %eip + call __start_thread + hlt + +.L_bc_parent: + # We're the parent; nothing to do. +.L_bc_return: + popl %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + popl %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + popl %ebx + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + ret +END(__bionic_clone) +.hidden __bionic_clone
diff --git a/libc/arch-x86/bionic/__restore.S b/libc/arch-x86/bionic/__restore.S new file mode 100644 index 0000000..cb18fd0 --- /dev/null +++ b/libc/arch-x86/bionic/__restore.S
@@ -0,0 +1,135 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// DWARF constants. +#define DW_CFA_def_cfa_expression 0x0f +#define DW_CFA_expression 0x10 +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_sdata4 0x0b +#define DW_OP_breg4 0x74 +#define DW_OP_deref 0x06 + +// Offsets into struct sigcontext. +#define OFFSET_EDI 16 +#define OFFSET_ESI 20 +#define OFFSET_EBP 24 +#define OFFSET_ESP 28 +#define OFFSET_EBX 32 +#define OFFSET_EDX 36 +#define OFFSET_ECX 40 +#define OFFSET_EAX 44 +#define OFFSET_EIP 56 + +// Non-standard DWARF constants for the x86 registers. +#define DW_x86_REG_EAX 0 +#define DW_x86_REG_ECX 1 +#define DW_x86_REG_EDX 2 +#define DW_x86_REG_EBX 3 +#define DW_x86_REG_EBP 5 +#define DW_x86_REG_ESI 6 +#define DW_x86_REG_EDI 7 +#define DW_x86_REG_EIP 8 + +#define cfi_signal_frame_start(f) \ +.section .eh_frame,"a",@progbits; \ +.L ## f ## _START_EH_FRAME: \ + .long 2f - 1f; /* CIE length. */ \ +1:.long 0; /* CIE ID. */ \ + .byte 1; /* Version. */ \ + .string "zRS"; /* Augmentation string. */ \ + .uleb128 1; /* Code alignment factor. */ \ + .sleb128 -4; /* Data alignment factor. */ \ + .uleb128 DW_x86_REG_EIP; /* Return address register. */ \ + .uleb128 1; /* 1 byte of augmentation data. */ \ + .byte (DW_EH_PE_pcrel|DW_EH_PE_sdata4); /* FDE encoding. */ \ + .align 8; \ +2: \ + .long .L ## f ## _END_FDE - .L ## f ## _START_FDE; /* FDE length. */ \ +.L ## f ## _START_FDE: \ + .long .L ## f ## _START_FDE - .L ## f ## _START_EH_FRAME; /* CIE location. */ \ + .long (.L ## f ## _START - 1) - .; /* pcrel start address (see FDE encoding above). */ \ + .long .L ## f ## _END - (.L ## f ## _START - 1); /* Function this FDE applies to. */ \ + .uleb128 0; /* FDE augmentation length. */ \ + +#define cfi_signal_frame_end(f) \ +.L ## f ## _END_FDE: \ + +#define cfi_def_cfa(offset) \ + .byte DW_CFA_def_cfa_expression; \ + .uleb128 2f-1f; \ +1:.byte DW_OP_breg4; \ + .sleb128 offset; \ + .byte DW_OP_deref; \ +2: \ + +#define cfi_offset(reg_number,offset) \ + .byte DW_CFA_expression; \ + .uleb128 reg_number; \ + .uleb128 2f-1f; \ +1:.byte DW_OP_breg4; \ + .sleb128 offset; \ +2: \ + +ENTRY_PRIVATE(__restore) +.L__restore_START: + popl %eax + movl $__NR_sigreturn, %eax + int $0x80 +.L__restore_END: +END(__restore) +cfi_signal_frame_start(__restore) + cfi_def_cfa(OFFSET_ESP + 4) + cfi_offset(DW_x86_REG_EDI, OFFSET_EDI + 4) + cfi_offset(DW_x86_REG_ESI, OFFSET_ESI + 4) + cfi_offset(DW_x86_REG_EBP, OFFSET_EBP + 4) + cfi_offset(DW_x86_REG_EBX, OFFSET_EBX + 4) + cfi_offset(DW_x86_REG_EDX, OFFSET_EDX + 4) + cfi_offset(DW_x86_REG_ECX, OFFSET_ECX + 4) + cfi_offset(DW_x86_REG_EAX, OFFSET_EAX + 4) + cfi_offset(DW_x86_REG_EIP, OFFSET_EIP + 4) +cfi_signal_frame_end(__restore) + +ENTRY_PRIVATE(__restore_rt) +.L__restore_rt_START: + movl $__NR_rt_sigreturn, %eax + int $0x80 +.L__restore_rt_END: +END(__restore_rt) +cfi_signal_frame_start(__restore_rt) + cfi_def_cfa(OFFSET_ESP + 160) + cfi_offset(DW_x86_REG_EDI, OFFSET_EDI + 160) + cfi_offset(DW_x86_REG_ESI, OFFSET_ESI + 160) + cfi_offset(DW_x86_REG_EBP, OFFSET_EBP + 160) + cfi_offset(DW_x86_REG_EBX, OFFSET_EBX + 160) + cfi_offset(DW_x86_REG_EDX, OFFSET_EDX + 160) + cfi_offset(DW_x86_REG_ECX, OFFSET_ECX + 160) + cfi_offset(DW_x86_REG_EAX, OFFSET_EAX + 160) + cfi_offset(DW_x86_REG_EIP, OFFSET_EIP + 160) +cfi_signal_frame_end(__restore_rt)
diff --git a/libc/arch-x86/bionic/__set_tls.cpp b/libc/arch-x86/bionic/__set_tls.cpp new file mode 100644 index 0000000..b26fd56 --- /dev/null +++ b/libc/arch-x86/bionic/__set_tls.cpp
@@ -0,0 +1,74 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> +#include <pthread.h> +#include <stdbool.h> + +#include <asm/ldt.h> + +extern "C" int __set_thread_area(struct user_desc*); + +__LIBC_HIDDEN__ void __init_user_desc(struct user_desc* result, bool allocate, void* base_addr) { + if (allocate) { + // Let the kernel choose. + result->entry_number = -1; + } else { + // Get the existing entry number from %gs. + uint32_t gs; + __asm__ __volatile__("movw %%gs, %w0" : "=q"(gs) /*output*/); + result->entry_number = (gs & 0xffff) >> 3; + } + + result->base_addr = reinterpret_cast<uintptr_t>(base_addr); + + result->limit = 0xfffff; + + result->seg_32bit = 1; + result->contents = MODIFY_LDT_CONTENTS_DATA; + result->read_exec_only = 0; + result->limit_in_pages = 1; + result->seg_not_present = 0; + result->useable = 1; +} + +extern "C" __LIBC_HIDDEN__ int __set_tls(void* ptr) { + struct user_desc tls_descriptor; + __init_user_desc(&tls_descriptor, true, ptr); + + int rc = __set_thread_area(&tls_descriptor); + if (rc != -1) { + // Change %gs to be new GDT entry. + uint16_t table_indicator = 0; // GDT + uint16_t rpl = 3; // Requested privilege level + uint16_t selector = (tls_descriptor.entry_number << 3) | table_indicator | rpl; + __asm__ __volatile__("movw %w0, %%gs" : /*output*/ : "q"(selector) /*input*/ : /*clobber*/); + } + + return rc; +}
diff --git a/libc/arch-x86/bionic/__stack_chk_fail_local.h b/libc/arch-x86/bionic/__stack_chk_fail_local.h new file mode 100644 index 0000000..0b0fd7f --- /dev/null +++ b/libc/arch-x86/bionic/__stack_chk_fail_local.h
@@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> + +/* + __stack_chk_fail routine is runtime part of stack protector compiler + feature. It's implemented in libc and represents die routine when stack + corruption is detected. + + Calls are generated by compiler and injected into user functions when + -fstack-protector* options are used. + + __stack_chk_fail_local is wrapper for __stack_chk_fail. Compiler generates + wrapper calls instead for PIC code only and only on IA32 for optimization + purpose (see gcc/config/i386/i386.c). Wrapper body is always included into + executable or library. This is the idea of optimization. + + Glibc is doing this via libc_nonshared.a which is linked automatically + everytime with libc.so. In bionic we have to bring it within crtfiles + because libc.so is real library and not a link script like libc.so at glibc. + + For x86_64 or non-PIC code compiler always generates __stack_chk_fail calls. +*/ + +#ifdef __i386__ +extern void __stack_chk_fail(); + +__LIBC_HIDDEN__ void __stack_chk_fail_local() { + __stack_chk_fail(); +} +#endif
diff --git a/libc/arch-x86/bionic/_exit_with_stack_teardown.S b/libc/arch-x86/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..ce8c2ea --- /dev/null +++ b/libc/arch-x86/bionic/_exit_with_stack_teardown.S
@@ -0,0 +1,16 @@ +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + // We can trash registers because this function never returns. + mov 4(%esp), %ebx // stackBase + mov 8(%esp), %ecx // stackSize + mov $__NR_munmap, %eax + int $0x80 + // If munmap failed, we ignore the failure and exit anyway. + + mov $0, %ebx // status + movl $__NR_exit, %eax + int $0x80 + // The exit syscall does not return. +END(_exit_with_stack_teardown)
diff --git a/libc/arch-x86/bionic/atexit.h b/libc/arch-x86/bionic/atexit.h new file mode 100644 index 0000000..bc776a8 --- /dev/null +++ b/libc/arch-x86/bionic/atexit.h
@@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern void *__dso_handle; + +__attribute__ ((visibility ("hidden"))) +int atexit(void (*func)(void)) +{ + return (__cxa_atexit((void (*)(void *))func, (void *)0, &__dso_handle)); +}
diff --git a/libc/arch-x86/bionic/libgcc_compat.c b/libc/arch-x86/bionic/libgcc_compat.c new file mode 100644 index 0000000..1a0f566 --- /dev/null +++ b/libc/arch-x86/bionic/libgcc_compat.c
@@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern char __divdi3; +extern char __moddi3; +extern char __popcountsi2; +extern char __udivdi3; +extern char __umoddi3; + +void* __bionic_libgcc_compat_symbols[] = { + &__divdi3, + &__moddi3, + &__popcountsi2, + &__udivdi3, + &__umoddi3, +};
diff --git a/libc/arch-x86/bionic/setjmp.S b/libc/arch-x86/bionic/setjmp.S new file mode 100644 index 0000000..efb6459 --- /dev/null +++ b/libc/arch-x86/bionic/setjmp.S
@@ -0,0 +1,208 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// The internal structure of a jmp_buf is totally private. +// Current layout (changes from release to release): +// +// word name description +// 0 edx registers +// 1 ebx +// 2 esp +// 3 ebp +// 4 esi +// 5 edi +// 6 sigmask signal mask (not used with _setjmp / _longjmp) +// 7 sigflag/cookie setjmp cookie in top 31 bits, signal mask flag in low bit +// 8 checksum checksum of the core registers, to give better error messages. +// 9 reserved + +#define _JB_EDX 0 +#define _JB_EBX 1 +#define _JB_ESP 2 +#define _JB_EBP 3 +#define _JB_ESI 4 +#define _JB_EDI 5 +#define _JB_SIGMASK 6 +#define _JB_SIGFLAG 7 +#define _JB_CHECKSUM 8 + +.macro m_mangle_registers reg + xorl \reg,%edx + xorl \reg,%ebx + xorl \reg,%esp + xorl \reg,%ebp + xorl \reg,%esi + xorl \reg,%edi +.endm + +.macro m_unmangle_registers reg + m_mangle_registers \reg +.endm + +.macro m_calculate_checksum dst, src + movl $0, \dst + .irp i,0,1,2,3,4,5 + xorl (\i*4)(\src), \dst + .endr +.endm + +ENTRY(setjmp) + movl 4(%esp),%ecx + mov $1,%eax + jmp .L_sigsetjmp +END(setjmp) + +ENTRY(_setjmp) + movl 4(%esp),%ecx + movl $0,%eax + jmp .L_sigsetjmp +END(_setjmp) + +ENTRY(sigsetjmp) + movl 4(%esp),%ecx + movl 8(%esp),%eax + +.L_sigsetjmp: + PIC_PROLOGUE + pushl %eax + call PIC_PLT(__bionic_setjmp_cookie_get) + addl $4,%esp + PIC_EPILOGUE + + // Record the setjmp cookie and whether or not we're saving the signal mask. + movl %eax,(_JB_SIGFLAG * 4)(%ecx) + + // Do we need to save the signal mask? + testl $1,%eax + jz 1f + + // Get the current signal mask. + PIC_PROLOGUE + pushl $0 + call PIC_PLT(sigblock) + addl $4,%esp + PIC_EPILOGUE + + // Save the signal mask. + movl 4(%esp),%ecx + movl %eax,(_JB_SIGMASK * 4)(%ecx) + +1: + // Fetch the setjmp cookie and clear the signal flag bit. + movl (_JB_SIGFLAG * 4)(%ecx),%eax + andl $-2,%eax + + // Save the callee-save registers. + movl 0(%esp),%edx + m_mangle_registers %eax + movl %edx,(_JB_EDX * 4)(%ecx) + movl %ebx,(_JB_EBX * 4)(%ecx) + movl %esp,(_JB_ESP * 4)(%ecx) + movl %ebp,(_JB_EBP * 4)(%ecx) + movl %esi,(_JB_ESI * 4)(%ecx) + movl %edi,(_JB_EDI * 4)(%ecx) + m_unmangle_registers %eax + + m_calculate_checksum %eax, %ecx + movl %eax, (_JB_CHECKSUM * 4)(%ecx) + + xorl %eax,%eax + ret +END(sigsetjmp) + +ENTRY(siglongjmp) + movl 4(%esp),%edx + + // Check the checksum before doing anything. + m_calculate_checksum %eax, %edx + xorl (_JB_CHECKSUM * 4)(%edx), %eax + jnz 3f + + // Do we have a signal mask to restore? + movl (_JB_SIGFLAG * 4)(%edx), %eax + testl $1,%eax + jz 1f + + // Restore the signal mask. + PIC_PROLOGUE + pushl (_JB_SIGMASK * 4)(%edx) + call PIC_PLT(sigsetmask) + addl $4,%esp + PIC_EPILOGUE + +1: + // Restore the callee-save registers. + movl 4(%esp),%edx + movl 8(%esp),%eax + + movl (_JB_SIGFLAG * 4)(%edx),%ecx + andl $-2,%ecx + + movl %ecx,%ebx + movl %ecx,%esp + movl %ecx,%ebp + movl %ecx,%esi + movl %ecx,%edi + xorl (_JB_EDX * 4)(%edx),%ecx + xorl (_JB_EBX * 4)(%edx),%ebx + xorl (_JB_ESP * 4)(%edx),%esp + xorl (_JB_EBP * 4)(%edx),%ebp + xorl (_JB_ESI * 4)(%edx),%esi + xorl (_JB_EDI * 4)(%edx),%edi + + PIC_PROLOGUE + pushl %eax + pushl %ecx + pushl (_JB_SIGFLAG * 4)(%edx) + call PIC_PLT(__bionic_setjmp_cookie_check) + addl $4,%esp + popl %ecx + popl %eax + PIC_EPILOGUE + + testl %eax,%eax + jnz 2f + incl %eax +2: + movl %ecx,0(%esp) + ret + +3: + PIC_PROLOGUE + pushl (_JB_SIGMASK * 4)(%edx) + call PIC_PLT(__bionic_setjmp_checksum_mismatch) +END(siglongjmp) + +ALIAS_SYMBOL(longjmp, siglongjmp) +ALIAS_SYMBOL(_longjmp, siglongjmp)
diff --git a/libc/arch-x86/bionic/syscall.S b/libc/arch-x86/bionic/syscall.S new file mode 100644 index 0000000..12402ac --- /dev/null +++ b/libc/arch-x86/bionic/syscall.S
@@ -0,0 +1,73 @@ +/* + * Generic syscall call. + * Upon entry: + * %eax: system call number - caller save + * %ebx: arg0 to system call - callee save + * %ecx: arg1 - caller save + * %edx: arg2 - caller save + * %esi: arg3 - callee save + * %edi: arg4 - callee save + * %ebp: arg5 - callee save + */ + +#include <private/bionic_asm.h> + +ENTRY(syscall) + # Push the callee save registers. + push %ebx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebx, 0 + push %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + push %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + push %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + # Get and save the system call entry address. + call __kernel_syscall + push %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + # Load all the arguments from the calling frame. + # (Not all will be valid, depending on the syscall.) + mov 24(%esp),%eax + mov 28(%esp),%ebx + mov 32(%esp),%ecx + mov 36(%esp),%edx + mov 40(%esp),%esi + mov 44(%esp),%edi + mov 48(%esp),%ebp + + # Make the system call. + call *(%esp) + addl $4, %esp + + # Error? + cmpl $-MAX_ERRNO, %eax + jb 1f + # Yes, so set errno. + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + # Restore the callee save registers. + pop %ebp + .cfi_adjust_cfa_offset -4 + .cfi_restore ebp + pop %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + pop %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + pop %ebx + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + ret +END(syscall)
diff --git a/libc/arch-x86/bionic/vfork.S b/libc/arch-x86/bionic/vfork.S new file mode 100644 index 0000000..5c71b8d --- /dev/null +++ b/libc/arch-x86/bionic/vfork.S
@@ -0,0 +1,52 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// This custom code preserves the return address across the system call. + +ENTRY(vfork) + popl %ecx // Grab the return address. + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0 + movl %gs:0, %eax + movl 4(%eax), %eax + movl $0, 12(%eax) + + movl $__NR_vfork, %eax + int $0x80 + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal +1: + jmp *%ecx // Jump to the stored return address. +END(vfork)
diff --git a/libc/arch-x86/generic/string/memcmp.S b/libc/arch-x86/generic/string/memcmp.S new file mode 100644 index 0000000..ef36b4f --- /dev/null +++ b/libc/arch-x86/generic/string/memcmp.S
@@ -0,0 +1,44 @@ +/* $OpenBSD: memcmp.S,v 1.4 2005/08/07 11:30:38 espie Exp $ */ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + */ + +#include <private/bionic_asm.h> + +ENTRY(memcmp) + pushl %edi + pushl %esi + movl 12(%esp),%edi + movl 16(%esp),%esi + cld /* set compare direction forward */ + + movl 20(%esp),%ecx /* compare by words */ + shrl $2,%ecx + repe + cmpsl + jne L5 /* do we match so far? */ + + movl 20(%esp),%ecx /* compare remainder by bytes */ + andl $3,%ecx + repe + cmpsb + jne L6 /* do we match? */ + + xorl %eax,%eax /* we match, return zero */ + popl %esi + popl %edi + ret + +L5: movl $4,%ecx /* We know that one of the next */ + subl %ecx,%edi /* four pairs of bytes do not */ + subl %ecx,%esi /* match. */ + repe + cmpsb +L6: movzbl -1(%edi),%eax /* Perform unsigned comparison */ + movzbl -1(%esi),%edx + subl %edx,%eax + popl %esi + popl %edi + ret +END(memcmp)
diff --git a/libc/arch-x86/generic/string/strcat.S b/libc/arch-x86/generic/string/strcat.S new file mode 100644 index 0000000..49e8eee --- /dev/null +++ b/libc/arch-x86/generic/string/strcat.S
@@ -0,0 +1,74 @@ +/* $OpenBSD: strcat.S,v 1.8 2005/08/07 11:30:38 espie Exp $ */ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + */ + +#include <private/bionic_asm.h> + +#if defined(APIWARN) +#APP + .section .gnu.warning.strcat + .ascii "warning: strcat() is almost always misused, please use strlcat()" +#NO_APP +#endif + +/* + * NOTE: I've unrolled the loop eight times: large enough to make a + * significant difference, and small enough not to totally trash the + * cache. + */ + +ENTRY(strcat) + pushl %edi /* save edi */ + movl 8(%esp),%edi /* dst address */ + movl 12(%esp),%edx /* src address */ + pushl %edi /* push destination address */ + + cld /* set search forward */ + xorl %eax,%eax /* set search for null terminator */ + movl $-1,%ecx /* set search for lots of characters */ + repne /* search! */ + scasb + + leal -1(%edi),%ecx /* correct dst address */ + + .align 2,0x90 +L1: movb (%edx),%al /* unroll loop, but not too much */ + movb %al,(%ecx) + testb %al,%al + jz L2 + movb 1(%edx),%al + movb %al,1(%ecx) + testb %al,%al + jz L2 + movb 2(%edx),%al + movb %al,2(%ecx) + testb %al,%al + jz L2 + movb 3(%edx),%al + movb %al,3(%ecx) + testb %al,%al + jz L2 + movb 4(%edx),%al + movb %al,4(%ecx) + testb %al,%al + jz L2 + movb 5(%edx),%al + movb %al,5(%ecx) + testb %al,%al + jz L2 + movb 6(%edx),%al + movb %al,6(%ecx) + testb %al,%al + jz L2 + movb 7(%edx),%al + movb %al,7(%ecx) + addl $8,%edx + addl $8,%ecx + testb %al,%al + jnz L1 +L2: popl %eax /* pop destination address */ + popl %edi /* restore edi */ + ret +END(strcat)
diff --git a/libc/arch-x86/generic/string/strcmp.S b/libc/arch-x86/generic/string/strcmp.S new file mode 100644 index 0000000..580f4d5 --- /dev/null +++ b/libc/arch-x86/generic/string/strcmp.S
@@ -0,0 +1,82 @@ +/* $OpenBSD: strcmp.S,v 1.3 2005/08/07 11:30:38 espie Exp $ */ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + */ + +#include <private/bionic_asm.h> + +/* + * NOTE: I've unrolled the loop eight times: large enough to make a + * significant difference, and small enough not to totally trash the + * cache. + */ + +ENTRY(strcmp) + movl 0x04(%esp),%eax + movl 0x08(%esp),%edx + jmp L2 /* Jump into the loop! */ + + .align 2,0x90 +L1: incl %eax + incl %edx +L2: movb (%eax),%cl + testb %cl,%cl /* null terminator??? */ + jz L3 + cmpb %cl,(%edx) /* chars match??? */ + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + jne L3 + incl %eax + incl %edx + movb (%eax),%cl + testb %cl,%cl + jz L3 + cmpb %cl,(%edx) + je L1 + .align 2, 0x90 +L3: movzbl (%eax),%eax /* unsigned comparison */ + movzbl (%edx),%edx + subl %edx,%eax + ret +END(strcmp)
diff --git a/libc/arch-x86/generic/string/strncmp.S b/libc/arch-x86/generic/string/strncmp.S new file mode 100644 index 0000000..9ba83a1 --- /dev/null +++ b/libc/arch-x86/generic/string/strncmp.S
@@ -0,0 +1,114 @@ +/* $OpenBSD: strncmp.S,v 1.3 2005/08/07 11:30:38 espie Exp $ */ +/* + * Written by J.T. Conklin <jtc@netbsd.org>. + * Public domain. + */ + +#include <private/bionic_asm.h> + +/* + * NOTE: I've unrolled the loop eight times: large enough to make a + * significant difference, and small enough not to totally trash the + * cache. + */ + +ENTRY(strncmp) + pushl %ebx + movl 8(%esp),%eax + movl 12(%esp),%ecx + movl 16(%esp),%edx + testl %edx,%edx + jmp L2 /* Jump into the loop! */ + + .align 2,0x90 +L1: incl %eax + incl %ecx + decl %edx +L2: jz L4 /* strings are equal */ + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + jne L3 + + incl %eax + incl %ecx + decl %edx + jz L4 + movb (%eax),%bl + testb %bl,%bl + jz L3 + cmpb %bl,(%ecx) + je L1 + + .align 2,0x90 +L3: movzbl (%eax),%eax /* unsigned comparision */ + movzbl (%ecx),%ecx + subl %ecx,%eax + popl %ebx + ret + .align 2,0x90 +L4: xorl %eax,%eax + popl %ebx + ret +END(strncmp)
diff --git a/libc/arch-x86/include/machine/asm.h b/libc/arch-x86/include/machine/asm.h new file mode 100644 index 0000000..943f9dd --- /dev/null +++ b/libc/arch-x86/include/machine/asm.h
@@ -0,0 +1,54 @@ +/* $NetBSD: asm.h,v 1.40 2011/06/16 13:16:20 joerg Exp $ */ + +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)asm.h 5.5 (Berkeley) 5/7/91 + */ + +#ifndef _I386_ASM_H_ +#define _I386_ASM_H_ + +#define PIC_PROLOGUE \ + pushl %ebx; \ + call 666f; \ +666: \ + popl %ebx; \ + addl $_GLOBAL_OFFSET_TABLE_+[.-666b], %ebx +#define PIC_EPILOGUE \ + popl %ebx +#define PIC_PLT(x) x@PLT +#define PIC_GOT(x) x@GOT(%ebx) +#define PIC_GOTOFF(x) x@GOTOFF(%ebx) + +#define __bionic_asm_align 16 + +#endif /* !_I386_ASM_H_ */
diff --git a/libc/arch-x86/include/machine/elf_machdep.h b/libc/arch-x86/include/machine/elf_machdep.h new file mode 100644 index 0000000..4bce933 --- /dev/null +++ b/libc/arch-x86/include/machine/elf_machdep.h
@@ -0,0 +1,64 @@ +/* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */ + +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#define ELF32_MACHDEP_ID_CASES \ + case EM_386: \ + case EM_486: \ + break; + +#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ +#define ELF64_MACHDEP_ID_CASES \ + /* no 64-bit ELF machine types supported */ + +#define ELF32_MACHDEP_ID EM_386 + +#define ARCH_ELFSIZE 32 /* MD native binary size */ + +/* i386 relocations */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 + +/* TLS relocations */ +#define R_386_TLS_TPOFF 14 +#define R_386_TLS_IE 15 +#define R_386_TLS_GOTIE 16 +#define R_386_TLS_LE 17 +#define R_386_TLS_GD 18 +#define R_386_TLS_LDM 19 + +/* The following relocations are GNU extensions. */ +#define R_386_16 20 +#define R_386_PC16 21 +#define R_386_8 22 +#define R_386_PC8 23 + +/* More TLS relocations */ +#define R_386_TLS_GD_32 24 +#define R_386_TLS_GD_PUSH 25 +#define R_386_TLS_GD_CALL 26 +#define R_386_TLS_GD_POP 27 +#define R_386_TLS_LDM_32 28 +#define R_386_TLS_LDM_PUSH 29 +#define R_386_TLS_LDM_CALL 30 +#define R_386_TLS_LDM_POP 31 +#define R_386_TLS_LDO_32 32 +#define R_386_TLS_IE_32 33 +#define R_386_TLS_LE_32 34 +#define R_386_TLS_DTPMOD32 35 +#define R_386_TLS_DTPOFF32 36 +#define R_386_TLS_TPOFF32 37 +#define R_386_TLS_GOTDESC 39 +#define R_386_TLS_DESC_CALL 40 +#define R_386_TLS_DESC 41 +#define R_386_IRELATIVE 42 + +#define R_TYPE(name) __CONCAT(R_386_,name)
diff --git a/libc/arch-x86/include/machine/fenv.h b/libc/arch-x86/include/machine/fenv.h new file mode 100644 index 0000000..de45add --- /dev/null +++ b/libc/arch-x86/include/machine/fenv.h
@@ -0,0 +1,69 @@ +/*- + * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/msun/i387/fenv.h,v 1.4 2005/03/17 22:21:46 das Exp $ + */ + +#ifndef _I387_FENV_H_ +#define _I387_FENV_H_ + +#include <sys/types.h> + +__BEGIN_DECLS + +/* + * To preserve binary compatibility with FreeBSD 5.3, we pack the + * mxcsr into some reserved fields, rather than changing sizeof(fenv_t). + */ +typedef struct { + __uint16_t __control; + __uint16_t __mxcsr_hi; + __uint16_t __status; + __uint16_t __mxcsr_lo; + __uint32_t __tag; + char __other[16]; +} fenv_t; + +typedef __uint16_t fexcept_t; + +/* Exception flags */ +#define FE_INVALID 0x01 +#define FE_DENORMAL 0x02 +#define FE_DIVBYZERO 0x04 +#define FE_OVERFLOW 0x08 +#define FE_UNDERFLOW 0x10 +#define FE_INEXACT 0x20 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_DENORMAL | FE_INEXACT | \ + FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) + +/* Rounding modes */ +#define FE_TONEAREST 0x0000 +#define FE_DOWNWARD 0x0400 +#define FE_UPWARD 0x0800 +#define FE_TOWARDZERO 0x0c00 + +__END_DECLS + +#endif /* !I387_FENV_H_ */
diff --git a/libc/arch-x86/include/machine/setjmp.h b/libc/arch-x86/include/machine/setjmp.h new file mode 100644 index 0000000..ded095d --- /dev/null +++ b/libc/arch-x86/include/machine/setjmp.h
@@ -0,0 +1,8 @@ +/* $OpenBSD: setjmp.h,v 1.2 2000/08/05 22:07:32 niklas Exp $ */ +/* $NetBSD: setjmp.h,v 1.1 1994/12/20 10:36:43 cgd Exp $ */ + +/* + * machine/setjmp.h: machine dependent setjmp-related information. + */ + +#define _JBLEN 10 /* size, in longs, of a jmp_buf */
diff --git a/libc/arch-x86/silvermont/string/cache.h b/libc/arch-x86/silvermont/string/cache.h new file mode 100644 index 0000000..c342b1c --- /dev/null +++ b/libc/arch-x86/silvermont/string/cache.h
@@ -0,0 +1,36 @@ +/* +Copyright (c) 2010, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/* Values are optimized for Silvermont */ +#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */ +#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */ + +#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2) +#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)
diff --git a/libc/arch-x86/silvermont/string/sse2-memcpy-slm.S b/libc/arch-x86/silvermont/string/sse2-memcpy-slm.S new file mode 100644 index 0000000..1b305c7 --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-memcpy-slm.S
@@ -0,0 +1,308 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "cache.h" + +#ifndef MEMCPY +# define MEMCPY memcpy +#endif + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define DEST PARMS +#define SRC DEST+4 +#define LEN SRC+4 + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 8 /* Preserve EBX. */ +#define ENTRANCE PUSH (%ebx); +#define RETURN_END POP (%ebx); ret +#define RETURN RETURN_END; CFI_PUSH (%ebx) + + .section .text.sse2,"ax",@progbits +ENTRY (MEMCPY) + ENTRANCE + movl LEN(%esp), %ecx + movl SRC(%esp), %eax + movl DEST(%esp), %edx + + cmp %eax, %edx + je L(return) + + cmp $16, %ecx + jbe L(len_0_16_bytes) + + cmp $SHARED_CACHE_SIZE_HALF, %ecx + jae L(large_page) + + movdqu (%eax), %xmm0 + movdqu -16(%eax, %ecx), %xmm1 + cmpl $32, %ecx + movdqu %xmm0, (%edx) + movdqu %xmm1, -16(%edx, %ecx) + jbe L(return) + + movdqu 16(%eax), %xmm0 + movdqu -32(%eax, %ecx), %xmm1 + cmpl $64, %ecx + movdqu %xmm0, 16(%edx) + movdqu %xmm1, -32(%edx, %ecx) + jbe L(return) + + movdqu 32(%eax), %xmm0 + movdqu 48(%eax), %xmm1 + movdqu -48(%eax, %ecx), %xmm2 + movdqu -64(%eax, %ecx), %xmm3 + cmpl $128, %ecx + movdqu %xmm0, 32(%edx) + movdqu %xmm1, 48(%edx) + movdqu %xmm2, -48(%edx, %ecx) + movdqu %xmm3, -64(%edx, %ecx) + jbe L(return) + +/* Now the main loop: we align the address of the destination. */ + leal 64(%edx), %ebx + andl $-64, %ebx + + addl %edx, %ecx + andl $-64, %ecx + + subl %edx, %eax + +/* We should stop two iterations before the termination + (in order not to misprefetch). */ + subl $64, %ecx + cmpl %ebx, %ecx + je L(main_loop_just_one_iteration) + + subl $64, %ecx + cmpl %ebx, %ecx + je L(main_loop_last_two_iterations) + + + .p2align 4 +L(main_loop_cache): + + prefetcht0 128(%ebx, %eax) + + movdqu (%ebx, %eax), %xmm0 + movdqu 16(%ebx, %eax), %xmm1 + movdqu 32(%ebx, %eax), %xmm2 + movdqu 48(%ebx, %eax), %xmm3 + movdqa %xmm0, (%ebx) + movdqa %xmm1, 16(%ebx) + movdqa %xmm2, 32(%ebx) + movdqa %xmm3, 48(%ebx) + lea 64(%ebx), %ebx + cmpl %ebx, %ecx + jne L(main_loop_cache) + +L(main_loop_last_two_iterations): + movdqu (%ebx, %eax), %xmm0 + movdqu 16(%ebx, %eax), %xmm1 + movdqu 32(%ebx, %eax), %xmm2 + movdqu 48(%ebx, %eax), %xmm3 + movdqu 64(%ebx, %eax), %xmm4 + movdqu 80(%ebx, %eax), %xmm5 + movdqu 96(%ebx, %eax), %xmm6 + movdqu 112(%ebx, %eax), %xmm7 + movdqa %xmm0, (%ebx) + movdqa %xmm1, 16(%ebx) + movdqa %xmm2, 32(%ebx) + movdqa %xmm3, 48(%ebx) + movdqa %xmm4, 64(%ebx) + movdqa %xmm5, 80(%ebx) + movdqa %xmm6, 96(%ebx) + movdqa %xmm7, 112(%ebx) + jmp L(return) + +L(main_loop_just_one_iteration): + movdqu (%ebx, %eax), %xmm0 + movdqu 16(%ebx, %eax), %xmm1 + movdqu 32(%ebx, %eax), %xmm2 + movdqu 48(%ebx, %eax), %xmm3 + movdqa %xmm0, (%ebx) + movdqa %xmm1, 16(%ebx) + movdqa %xmm2, 32(%ebx) + movdqa %xmm3, 48(%ebx) + jmp L(return) + +L(large_page): + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu 32(%eax), %xmm2 + movdqu 48(%eax), %xmm3 + movdqu -64(%eax, %ecx), %xmm4 + movdqu -48(%eax, %ecx), %xmm5 + movdqu -32(%eax, %ecx), %xmm6 + movdqu -16(%eax, %ecx), %xmm7 + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, 32(%edx) + movdqu %xmm3, 48(%edx) + movdqu %xmm4, -64(%edx, %ecx) + movdqu %xmm5, -48(%edx, %ecx) + movdqu %xmm6, -32(%edx, %ecx) + movdqu %xmm7, -16(%edx, %ecx) + + movdqu 64(%eax), %xmm0 + movdqu 80(%eax), %xmm1 + movdqu 96(%eax), %xmm2 + movdqu 112(%eax), %xmm3 + movdqu -128(%eax, %ecx), %xmm4 + movdqu -112(%eax, %ecx), %xmm5 + movdqu -96(%eax, %ecx), %xmm6 + movdqu -80(%eax, %ecx), %xmm7 + movdqu %xmm0, 64(%edx) + movdqu %xmm1, 80(%edx) + movdqu %xmm2, 96(%edx) + movdqu %xmm3, 112(%edx) + movdqu %xmm4, -128(%edx, %ecx) + movdqu %xmm5, -112(%edx, %ecx) + movdqu %xmm6, -96(%edx, %ecx) + movdqu %xmm7, -80(%edx, %ecx) + +/* Now the main loop with non temporal stores. We align + the address of the destination. */ + leal 128(%edx), %ebx + andl $-128, %ebx + + addl %edx, %ecx + andl $-128, %ecx + + subl %edx, %eax + + .p2align 4 +L(main_loop_large_page): + movdqu (%ebx, %eax), %xmm0 + movdqu 16(%ebx, %eax), %xmm1 + movdqu 32(%ebx, %eax), %xmm2 + movdqu 48(%ebx, %eax), %xmm3 + movdqu 64(%ebx, %eax), %xmm4 + movdqu 80(%ebx, %eax), %xmm5 + movdqu 96(%ebx, %eax), %xmm6 + movdqu 112(%ebx, %eax), %xmm7 + movntdq %xmm0, (%ebx) + movntdq %xmm1, 16(%ebx) + movntdq %xmm2, 32(%ebx) + movntdq %xmm3, 48(%ebx) + movntdq %xmm4, 64(%ebx) + movntdq %xmm5, 80(%ebx) + movntdq %xmm6, 96(%ebx) + movntdq %xmm7, 112(%ebx) + lea 128(%ebx), %ebx + cmpl %ebx, %ecx + jne L(main_loop_large_page) + sfence + jmp L(return) + +L(len_0_16_bytes): + testb $24, %cl + jne L(len_9_16_bytes) + testb $4, %cl + .p2align 4,,5 + jne L(len_5_8_bytes) + testl %ecx, %ecx + .p2align 4,,2 + je L(return) + movzbl (%eax), %ebx + testb $2, %cl + movb %bl, (%edx) + je L(return) + movzwl -2(%eax,%ecx), %ebx + movw %bx, -2(%edx,%ecx) + jmp L(return) + +L(len_9_16_bytes): + movq (%eax), %xmm0 + movq -8(%eax, %ecx), %xmm1 + movq %xmm0, (%edx) + movq %xmm1, -8(%edx, %ecx) + jmp L(return) + +L(len_5_8_bytes): + movl (%eax), %ebx + movl %ebx, (%edx) + movl -4(%eax,%ecx), %ebx + movl %ebx, -4(%edx,%ecx) + jmp L(return) + +L(return): + movl %edx, %eax + RETURN + +END (MEMCPY)
diff --git a/libc/arch-x86/silvermont/string/sse2-memmove-slm.S b/libc/arch-x86/silvermont/string/sse2-memmove-slm.S new file mode 100644 index 0000000..bf9f85d --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-memmove-slm.S
@@ -0,0 +1,539 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "cache.h" + +#ifndef MEMMOVE +# define MEMMOVE memmove +#endif + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define DEST PARMS +#define SRC DEST+4 +#define LEN SRC+4 + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 8 /* Preserve EBX. */ +#define ENTRANCE PUSH (%ebx); +#define RETURN_END POP (%ebx); ret +#define RETURN RETURN_END; CFI_PUSH (%ebx) + + .section .text.sse2,"ax",@progbits +ENTRY (MEMMOVE) + ENTRANCE + movl LEN(%esp), %ecx + movl SRC(%esp), %eax + movl DEST(%esp), %edx + +/* Check whether we should copy backward or forward. */ + cmp %eax, %edx + je L(mm_return) + jg L(mm_len_0_or_more_backward) + +/* Now do checks for lengths. We do [0..16], [0..32], [0..64], [0..128] + separately. */ + cmp $16, %ecx + jbe L(mm_len_0_16_bytes_forward) + + cmpl $32, %ecx + ja L(mm_len_32_or_more_forward) + +/* Copy [0..32] and return. */ + movdqu (%eax), %xmm0 + movdqu -16(%eax, %ecx), %xmm1 + movdqu %xmm0, (%edx) + movdqu %xmm1, -16(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_32_or_more_forward): + cmpl $64, %ecx + ja L(mm_len_64_or_more_forward) + +/* Copy [0..64] and return. */ + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu -16(%eax, %ecx), %xmm2 + movdqu -32(%eax, %ecx), %xmm3 + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, -16(%edx, %ecx) + movdqu %xmm3, -32(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_64_or_more_forward): + cmpl $128, %ecx + ja L(mm_len_128_or_more_forward) + +/* Copy [0..128] and return. */ + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu 32(%eax), %xmm2 + movdqu 48(%eax), %xmm3 + movdqu -64(%eax, %ecx), %xmm4 + movdqu -48(%eax, %ecx), %xmm5 + movdqu -32(%eax, %ecx), %xmm6 + movdqu -16(%eax, %ecx), %xmm7 + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, 32(%edx) + movdqu %xmm3, 48(%edx) + movdqu %xmm4, -64(%edx, %ecx) + movdqu %xmm5, -48(%edx, %ecx) + movdqu %xmm6, -32(%edx, %ecx) + movdqu %xmm7, -16(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_128_or_more_forward): + PUSH (%esi) + PUSH (%edi) + +/* Aligning the address of destination. */ + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu 32(%eax), %xmm2 + movdqu 48(%eax), %xmm3 + + leal 64(%edx), %edi + andl $-64, %edi + subl %edx, %eax + + movdqu (%eax, %edi), %xmm4 + movdqu 16(%eax, %edi), %xmm5 + movdqu 32(%eax, %edi), %xmm6 + movdqu 48(%eax, %edi), %xmm7 + + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, 32(%edx) + movdqu %xmm3, 48(%edx) + movdqa %xmm4, (%edi) + movaps %xmm5, 16(%edi) + movaps %xmm6, 32(%edi) + movaps %xmm7, 48(%edi) + addl $64, %edi + + leal (%edx, %ecx), %ebx + andl $-64, %ebx + cmp %edi, %ebx + jbe L(mm_copy_remaining_forward) + + cmp $SHARED_CACHE_SIZE_HALF, %ecx + jae L(mm_large_page_loop_forward) + + .p2align 4 +L(mm_main_loop_forward): + + prefetcht0 128(%eax, %edi) + + movdqu (%eax, %edi), %xmm0 + movdqu 16(%eax, %edi), %xmm1 + movdqu 32(%eax, %edi), %xmm2 + movdqu 48(%eax, %edi), %xmm3 + movdqa %xmm0, (%edi) + movaps %xmm1, 16(%edi) + movaps %xmm2, 32(%edi) + movaps %xmm3, 48(%edi) + leal 64(%edi), %edi + cmp %edi, %ebx + ja L(mm_main_loop_forward) + +L(mm_copy_remaining_forward): + addl %edx, %ecx + subl %edi, %ecx +/* We copied all up till %edi position in the dst. + In %ecx now is how many bytes are left to copy. + Now we need to advance %esi. */ + leal (%edi, %eax), %esi + +L(mm_remaining_0_64_bytes_forward): + cmp $32, %ecx + ja L(mm_remaining_33_64_bytes_forward) + cmp $16, %ecx + ja L(mm_remaining_17_32_bytes_forward) + testl %ecx, %ecx + .p2align 4,,2 + je L(mm_return_pop_all) + + cmpb $8, %cl + ja L(mm_remaining_9_16_bytes_forward) + cmpb $4, %cl + .p2align 4,,5 + ja L(mm_remaining_5_8_bytes_forward) + cmpb $2, %cl + .p2align 4,,1 + ja L(mm_remaining_3_4_bytes_forward) + movzbl -1(%esi,%ecx), %eax + movzbl (%esi), %ebx + movb %al, -1(%edi,%ecx) + movb %bl, (%edi) + jmp L(mm_return_pop_all) + +L(mm_remaining_33_64_bytes_forward): + movdqu (%esi), %xmm0 + movdqu 16(%esi), %xmm1 + movdqu -32(%esi, %ecx), %xmm2 + movdqu -16(%esi, %ecx), %xmm3 + movdqu %xmm0, (%edi) + movdqu %xmm1, 16(%edi) + movdqu %xmm2, -32(%edi, %ecx) + movdqu %xmm3, -16(%edi, %ecx) + jmp L(mm_return_pop_all) + +L(mm_remaining_17_32_bytes_forward): + movdqu (%esi), %xmm0 + movdqu -16(%esi, %ecx), %xmm1 + movdqu %xmm0, (%edi) + movdqu %xmm1, -16(%edi, %ecx) + jmp L(mm_return_pop_all) + +L(mm_remaining_9_16_bytes_forward): + movq (%esi), %xmm0 + movq -8(%esi, %ecx), %xmm1 + movq %xmm0, (%edi) + movq %xmm1, -8(%edi, %ecx) + jmp L(mm_return_pop_all) + +L(mm_remaining_5_8_bytes_forward): + movl (%esi), %eax + movl -4(%esi,%ecx), %ebx + movl %eax, (%edi) + movl %ebx, -4(%edi,%ecx) + jmp L(mm_return_pop_all) + +L(mm_remaining_3_4_bytes_forward): + movzwl -2(%esi,%ecx), %eax + movzwl (%esi), %ebx + movw %ax, -2(%edi,%ecx) + movw %bx, (%edi) + jmp L(mm_return_pop_all) + +L(mm_len_0_16_bytes_forward): + testb $24, %cl + jne L(mm_len_9_16_bytes_forward) + testb $4, %cl + .p2align 4,,5 + jne L(mm_len_5_8_bytes_forward) + testl %ecx, %ecx + .p2align 4,,2 + je L(mm_return) + testb $2, %cl + .p2align 4,,1 + jne L(mm_len_2_4_bytes_forward) + movzbl -1(%eax,%ecx), %ebx + movzbl (%eax), %eax + movb %bl, -1(%edx,%ecx) + movb %al, (%edx) + jmp L(mm_return) + +L(mm_len_2_4_bytes_forward): + movzwl -2(%eax,%ecx), %ebx + movzwl (%eax), %eax + movw %bx, -2(%edx,%ecx) + movw %ax, (%edx) + jmp L(mm_return) + +L(mm_len_5_8_bytes_forward): + movl (%eax), %ebx + movl -4(%eax,%ecx), %eax + movl %ebx, (%edx) + movl %eax, -4(%edx,%ecx) + jmp L(mm_return) + +L(mm_len_9_16_bytes_forward): + movq (%eax), %xmm0 + movq -8(%eax, %ecx), %xmm1 + movq %xmm0, (%edx) + movq %xmm1, -8(%edx, %ecx) + jmp L(mm_return) + + CFI_POP (%edi) + CFI_POP (%esi) + +L(mm_recalc_len): +/* Compute in %ecx how many bytes are left to copy after + the main loop stops. */ + movl %ebx, %ecx + subl %edx, %ecx +/* The code for copying backwards. */ +L(mm_len_0_or_more_backward): + +/* Now do checks for lengths. We do [0..16], [16..32], [32..64], [64..128] + separately. */ + cmp $16, %ecx + jbe L(mm_len_0_16_bytes_backward) + + cmpl $32, %ecx + jg L(mm_len_32_or_more_backward) + +/* Copy [0..32] and return. */ + movdqu (%eax), %xmm0 + movdqu -16(%eax, %ecx), %xmm1 + movdqu %xmm0, (%edx) + movdqu %xmm1, -16(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_32_or_more_backward): + cmpl $64, %ecx + jg L(mm_len_64_or_more_backward) + +/* Copy [0..64] and return. */ + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu -16(%eax, %ecx), %xmm2 + movdqu -32(%eax, %ecx), %xmm3 + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, -16(%edx, %ecx) + movdqu %xmm3, -32(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_64_or_more_backward): + cmpl $128, %ecx + jg L(mm_len_128_or_more_backward) + +/* Copy [0..128] and return. */ + movdqu (%eax), %xmm0 + movdqu 16(%eax), %xmm1 + movdqu 32(%eax), %xmm2 + movdqu 48(%eax), %xmm3 + movdqu -64(%eax, %ecx), %xmm4 + movdqu -48(%eax, %ecx), %xmm5 + movdqu -32(%eax, %ecx), %xmm6 + movdqu -16(%eax, %ecx), %xmm7 + movdqu %xmm0, (%edx) + movdqu %xmm1, 16(%edx) + movdqu %xmm2, 32(%edx) + movdqu %xmm3, 48(%edx) + movdqu %xmm4, -64(%edx, %ecx) + movdqu %xmm5, -48(%edx, %ecx) + movdqu %xmm6, -32(%edx, %ecx) + movdqu %xmm7, -16(%edx, %ecx) + jmp L(mm_return) + +L(mm_len_128_or_more_backward): + PUSH (%esi) + PUSH (%edi) + +/* Aligning the address of destination. We need to save + 16 bits from the source in order not to overwrite them. */ + movdqu -16(%eax, %ecx), %xmm0 + movdqu -32(%eax, %ecx), %xmm1 + movdqu -48(%eax, %ecx), %xmm2 + movdqu -64(%eax, %ecx), %xmm3 + + leal (%edx, %ecx), %edi + andl $-64, %edi + + movl %eax, %esi + subl %edx, %esi + + movdqu -16(%edi, %esi), %xmm4 + movdqu -32(%edi, %esi), %xmm5 + movdqu -48(%edi, %esi), %xmm6 + movdqu -64(%edi, %esi), %xmm7 + + movdqu %xmm0, -16(%edx, %ecx) + movdqu %xmm1, -32(%edx, %ecx) + movdqu %xmm2, -48(%edx, %ecx) + movdqu %xmm3, -64(%edx, %ecx) + movdqa %xmm4, -16(%edi) + movdqa %xmm5, -32(%edi) + movdqa %xmm6, -48(%edi) + movdqa %xmm7, -64(%edi) + leal -64(%edi), %edi + + leal 64(%edx), %ebx + andl $-64, %ebx + + cmp %edi, %ebx + jae L(mm_main_loop_backward_end) + + cmp $SHARED_CACHE_SIZE_HALF, %ecx + jae L(mm_large_page_loop_backward) + + .p2align 4 +L(mm_main_loop_backward): + + prefetcht0 -128(%edi, %esi) + + movdqu -64(%edi, %esi), %xmm0 + movdqu -48(%edi, %esi), %xmm1 + movdqu -32(%edi, %esi), %xmm2 + movdqu -16(%edi, %esi), %xmm3 + movdqa %xmm0, -64(%edi) + movdqa %xmm1, -48(%edi) + movdqa %xmm2, -32(%edi) + movdqa %xmm3, -16(%edi) + leal -64(%edi), %edi + cmp %edi, %ebx + jb L(mm_main_loop_backward) +L(mm_main_loop_backward_end): + POP (%edi) + POP (%esi) + jmp L(mm_recalc_len) + +/* Copy [0..16] and return. */ +L(mm_len_0_16_bytes_backward): + testb $24, %cl + jnz L(mm_len_9_16_bytes_backward) + testb $4, %cl + .p2align 4,,5 + jnz L(mm_len_5_8_bytes_backward) + testl %ecx, %ecx + .p2align 4,,2 + je L(mm_return) + testb $2, %cl + .p2align 4,,1 + jne L(mm_len_3_4_bytes_backward) + movzbl -1(%eax,%ecx), %ebx + movzbl (%eax), %eax + movb %bl, -1(%edx,%ecx) + movb %al, (%edx) + jmp L(mm_return) + +L(mm_len_3_4_bytes_backward): + movzwl -2(%eax,%ecx), %ebx + movzwl (%eax), %eax + movw %bx, -2(%edx,%ecx) + movw %ax, (%edx) + jmp L(mm_return) + +L(mm_len_9_16_bytes_backward): + PUSH (%esi) + movl -4(%eax,%ecx), %ebx + movl -8(%eax,%ecx), %esi + movl %ebx, -4(%edx,%ecx) + movl %esi, -8(%edx,%ecx) + subl $8, %ecx + POP (%esi) + jmp L(mm_len_0_16_bytes_backward) + +L(mm_len_5_8_bytes_backward): + movl (%eax), %ebx + movl -4(%eax,%ecx), %eax + movl %ebx, (%edx) + movl %eax, -4(%edx,%ecx) + +L(mm_return): + movl %edx, %eax + RETURN + +L(mm_return_pop_all): + movl %edx, %eax + POP (%edi) + POP (%esi) + RETURN + +/* Big length copy forward part. */ + + .p2align 4 +L(mm_large_page_loop_forward): + movdqu (%eax, %edi), %xmm0 + movdqu 16(%eax, %edi), %xmm1 + movdqu 32(%eax, %edi), %xmm2 + movdqu 48(%eax, %edi), %xmm3 + movntdq %xmm0, (%edi) + movntdq %xmm1, 16(%edi) + movntdq %xmm2, 32(%edi) + movntdq %xmm3, 48(%edi) + leal 64(%edi), %edi + cmp %edi, %ebx + ja L(mm_large_page_loop_forward) + sfence + jmp L(mm_copy_remaining_forward) + +/* Big length copy backward part. */ + .p2align 4 +L(mm_large_page_loop_backward): + movdqu -64(%edi, %esi), %xmm0 + movdqu -48(%edi, %esi), %xmm1 + movdqu -32(%edi, %esi), %xmm2 + movdqu -16(%edi, %esi), %xmm3 + movntdq %xmm0, -64(%edi) + movntdq %xmm1, -48(%edi) + movntdq %xmm2, -32(%edi) + movntdq %xmm3, -16(%edi) + leal -64(%edi), %edi + cmp %edi, %ebx + jb L(mm_large_page_loop_backward) + sfence + POP (%edi) + POP (%esi) + jmp L(mm_recalc_len) + +END (MEMMOVE)
diff --git a/libc/arch-x86/silvermont/string/sse2-memset-slm.S b/libc/arch-x86/silvermont/string/sse2-memset-slm.S new file mode 100644 index 0000000..03a552d --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-memset-slm.S
@@ -0,0 +1,761 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include <private/bionic_asm.h> + +#include "cache.h" + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef ALIGN +# define ALIGN(n) .p2align n +#endif + +#define CFI_PUSH(REG) \ + .cfi_adjust_cfa_offset 4; \ + .cfi_rel_offset REG, 0 + +#define CFI_POP(REG) \ + .cfi_adjust_cfa_offset -4; \ + .cfi_restore REG + +#define PUSH(REG) pushl REG; CFI_PUSH(REG) +#define POP(REG) popl REG; CFI_POP(REG) + +#define PARMS 8 /* Preserve EBX. */ +#define DST PARMS +#define CHR (DST+4) +#define LEN (CHR+4) +#define CHK_DST_LEN (LEN+4) +#define SETRTNVAL movl DST(%esp), %eax + +# define ENTRANCE PUSH(%ebx); +# define RETURN_END POP(%ebx); ret +# define RETURN RETURN_END; CFI_PUSH(%ebx) +# define JMPTBL(I, B) I - B + +/* Load an entry in a jump table into EBX and branch to it. TABLE is a + jump table with relative offsets. */ +# define BRANCH_TO_JMPTBL_ENTRY(TABLE) \ + /* We first load PC into EBX. */ \ + call __x86.get_pc_thunk.bx; \ + /* Get the address of the jump table. */ \ + add $(TABLE - .), %ebx; \ + /* Get the entry and convert the relative offset to the \ + absolute address. */ \ + add (%ebx,%ecx,4), %ebx; \ + add %ecx, %edx; \ + /* We loaded the jump table and adjusted EDX. Go. */ \ + jmp *%ebx + + .section .gnu.linkonce.t.__x86.get_pc_thunk.bx,"ax",@progbits + .globl __x86.get_pc_thunk.bx + .hidden __x86.get_pc_thunk.bx + ALIGN(4) + .type __x86.get_pc_thunk.bx,@function +__x86.get_pc_thunk.bx: + movl (%esp), %ebx + ret + +ENTRY(__memset_chk) + ENTRANCE + + movl LEN(%esp), %ecx + cmpl CHK_DST_LEN(%esp), %ecx + jna L(memset_length_loaded) + + POP(%ebx) // Undo ENTRANCE without returning. + jmp __memset_chk_fail +END(__memset_chk) + + .section .text.sse2,"ax",@progbits + ALIGN(4) +ENTRY(memset) + ENTRANCE + + movl LEN(%esp), %ecx +L(memset_length_loaded): + cmp $0, %ecx + ja L(1byteormore) + SETRTNVAL + RETURN + +L(1byteormore): + movzbl CHR(%esp), %eax + movb %al, %ah + /* Fill the whole EAX with pattern. */ + movl %eax, %edx + shl $16, %eax + or %edx, %eax + movl DST(%esp), %edx + cmp $1, %ecx + je L(1byte) + cmp $16, %ecx + jae L(16bytesormore) + + cmp $4, %ecx + jb L(4bytesless) + movl %eax, (%edx) + movl %eax, -4(%edx, %ecx) + cmp $8, %ecx + jb L(8bytesless) + movl %eax, 4(%edx) + movl %eax, -8(%edx, %ecx) +L(8bytesless): + SETRTNVAL + RETURN + +L(4bytesless): + movw %ax, (%edx) + movw %ax, -2(%edx, %ecx) + SETRTNVAL + RETURN + +L(1byte): + movb %al, (%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(16bytesormore): + movd %eax, %xmm0 + pshufd $0, %xmm0, %xmm0 + + cmp $64, %ecx + ja L(64bytesmore) + movdqu %xmm0, (%edx) + movdqu %xmm0, -16(%edx, %ecx) + cmp $32, %ecx + jbe L(32bytesless) + movdqu %xmm0, 16(%edx) + movdqu %xmm0, -32(%edx, %ecx) +L(32bytesless): + SETRTNVAL + RETURN + +L(64bytesmore): + testl $0xf, %edx + jz L(aligned_16) +L(not_aligned_16): + movdqu %xmm0, (%edx) + movl %edx, %eax + and $-16, %edx + add $16, %edx + sub %edx, %eax + add %eax, %ecx + movd %xmm0, %eax + + ALIGN(4) +L(aligned_16): + cmp $128, %ecx + jae L(128bytesormore) + +L(aligned_16_less128bytes): + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + ALIGN(4) +L(128bytesormore): + PUSH(%ebx) + mov $SHARED_CACHE_SIZE, %ebx + cmp %ebx, %ecx + jae L(128bytesormore_nt_start) + + POP(%ebx) + + PUSH(%ebx) + mov $DATA_CACHE_SIZE, %ebx + + cmp %ebx, %ecx + jae L(128bytes_L2_normal) + subl $128, %ecx +L(128bytesormore_normal): + sub $128, %ecx + movdqa %xmm0, (%edx) + movaps %xmm0, 0x10(%edx) + movaps %xmm0, 0x20(%edx) + movaps %xmm0, 0x30(%edx) + movaps %xmm0, 0x40(%edx) + movaps %xmm0, 0x50(%edx) + movaps %xmm0, 0x60(%edx) + movaps %xmm0, 0x70(%edx) + lea 128(%edx), %edx + jb L(128bytesless_normal) + + + sub $128, %ecx + movdqa %xmm0, (%edx) + movaps %xmm0, 0x10(%edx) + movaps %xmm0, 0x20(%edx) + movaps %xmm0, 0x30(%edx) + movaps %xmm0, 0x40(%edx) + movaps %xmm0, 0x50(%edx) + movaps %xmm0, 0x60(%edx) + movaps %xmm0, 0x70(%edx) + lea 128(%edx), %edx + jae L(128bytesormore_normal) + +L(128bytesless_normal): + lea 128(%ecx), %ecx + POP(%ebx) + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + ALIGN(4) +L(128bytes_L2_normal): + prefetchnta 0x380(%edx) + prefetchnta 0x3c0(%edx) + sub $128, %ecx + movdqa %xmm0, (%edx) + movaps %xmm0, 0x10(%edx) + movaps %xmm0, 0x20(%edx) + movaps %xmm0, 0x30(%edx) + movaps %xmm0, 0x40(%edx) + movaps %xmm0, 0x50(%edx) + movaps %xmm0, 0x60(%edx) + movaps %xmm0, 0x70(%edx) + add $128, %edx + cmp $128, %ecx + jae L(128bytes_L2_normal) + +L(128bytesless_L2_normal): + POP(%ebx) + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + +L(128bytesormore_nt_start): + sub %ebx, %ecx + ALIGN(4) +L(128bytesormore_shared_cache_loop): + prefetchnta 0x3c0(%edx) + prefetchnta 0x380(%edx) + sub $0x80, %ebx + movdqa %xmm0, (%edx) + movaps %xmm0, 0x10(%edx) + movaps %xmm0, 0x20(%edx) + movaps %xmm0, 0x30(%edx) + movaps %xmm0, 0x40(%edx) + movaps %xmm0, 0x50(%edx) + movaps %xmm0, 0x60(%edx) + movaps %xmm0, 0x70(%edx) + add $0x80, %edx + cmp $0x80, %ebx + jae L(128bytesormore_shared_cache_loop) + cmp $0x80, %ecx + jb L(shared_cache_loop_end) + ALIGN(4) +L(128bytesormore_nt): + sub $0x80, %ecx + movntdq %xmm0, (%edx) + movntdq %xmm0, 0x10(%edx) + movntdq %xmm0, 0x20(%edx) + movntdq %xmm0, 0x30(%edx) + movntdq %xmm0, 0x40(%edx) + movntdq %xmm0, 0x50(%edx) + movntdq %xmm0, 0x60(%edx) + movntdq %xmm0, 0x70(%edx) + add $0x80, %edx + cmp $0x80, %ecx + jae L(128bytesormore_nt) + sfence +L(shared_cache_loop_end): + POP(%ebx) + BRANCH_TO_JMPTBL_ENTRY(L(table_16_128bytes)) + + + .pushsection .rodata.sse2,"a",@progbits + ALIGN(2) +L(table_16_128bytes): + .int JMPTBL(L(aligned_16_0bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_1bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_2bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_3bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_4bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_5bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_6bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_7bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_8bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_9bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_10bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_11bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_12bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_13bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_14bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_15bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_16bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_17bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_18bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_19bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_20bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_21bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_22bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_23bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_24bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_25bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_26bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_27bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_28bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_29bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_30bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_31bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_32bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_33bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_34bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_35bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_36bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_37bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_38bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_39bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_40bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_41bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_42bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_43bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_44bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_45bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_46bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_47bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_48bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_49bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_50bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_51bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_52bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_53bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_54bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_55bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_56bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_57bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_58bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_59bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_60bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_61bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_62bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_63bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_64bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_65bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_66bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_67bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_68bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_69bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_70bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_71bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_72bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_73bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_74bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_75bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_76bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_77bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_78bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_79bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_80bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_81bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_82bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_83bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_84bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_85bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_86bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_87bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_88bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_89bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_90bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_91bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_92bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_93bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_94bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_95bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_96bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_97bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_98bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_99bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_100bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_101bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_102bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_103bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_104bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_105bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_106bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_107bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_108bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_109bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_110bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_111bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_112bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_113bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_114bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_115bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_116bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_117bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_118bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_119bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_120bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_121bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_122bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_123bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_124bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_125bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_126bytes), L(table_16_128bytes)) + .int JMPTBL(L(aligned_16_127bytes), L(table_16_128bytes)) + .popsection + + ALIGN(4) +L(aligned_16_112bytes): + movdqa %xmm0, -112(%edx) +L(aligned_16_96bytes): + movdqa %xmm0, -96(%edx) +L(aligned_16_80bytes): + movdqa %xmm0, -80(%edx) +L(aligned_16_64bytes): + movdqa %xmm0, -64(%edx) +L(aligned_16_48bytes): + movdqa %xmm0, -48(%edx) +L(aligned_16_32bytes): + movdqa %xmm0, -32(%edx) +L(aligned_16_16bytes): + movdqa %xmm0, -16(%edx) +L(aligned_16_0bytes): + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_113bytes): + movdqa %xmm0, -113(%edx) +L(aligned_16_97bytes): + movdqa %xmm0, -97(%edx) +L(aligned_16_81bytes): + movdqa %xmm0, -81(%edx) +L(aligned_16_65bytes): + movdqa %xmm0, -65(%edx) +L(aligned_16_49bytes): + movdqa %xmm0, -49(%edx) +L(aligned_16_33bytes): + movdqa %xmm0, -33(%edx) +L(aligned_16_17bytes): + movdqa %xmm0, -17(%edx) +L(aligned_16_1bytes): + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_114bytes): + movdqa %xmm0, -114(%edx) +L(aligned_16_98bytes): + movdqa %xmm0, -98(%edx) +L(aligned_16_82bytes): + movdqa %xmm0, -82(%edx) +L(aligned_16_66bytes): + movdqa %xmm0, -66(%edx) +L(aligned_16_50bytes): + movdqa %xmm0, -50(%edx) +L(aligned_16_34bytes): + movdqa %xmm0, -34(%edx) +L(aligned_16_18bytes): + movdqa %xmm0, -18(%edx) +L(aligned_16_2bytes): + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_115bytes): + movdqa %xmm0, -115(%edx) +L(aligned_16_99bytes): + movdqa %xmm0, -99(%edx) +L(aligned_16_83bytes): + movdqa %xmm0, -83(%edx) +L(aligned_16_67bytes): + movdqa %xmm0, -67(%edx) +L(aligned_16_51bytes): + movdqa %xmm0, -51(%edx) +L(aligned_16_35bytes): + movdqa %xmm0, -35(%edx) +L(aligned_16_19bytes): + movdqa %xmm0, -19(%edx) +L(aligned_16_3bytes): + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_116bytes): + movdqa %xmm0, -116(%edx) +L(aligned_16_100bytes): + movdqa %xmm0, -100(%edx) +L(aligned_16_84bytes): + movdqa %xmm0, -84(%edx) +L(aligned_16_68bytes): + movdqa %xmm0, -68(%edx) +L(aligned_16_52bytes): + movdqa %xmm0, -52(%edx) +L(aligned_16_36bytes): + movdqa %xmm0, -36(%edx) +L(aligned_16_20bytes): + movdqa %xmm0, -20(%edx) +L(aligned_16_4bytes): + movl %eax, -4(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_117bytes): + movdqa %xmm0, -117(%edx) +L(aligned_16_101bytes): + movdqa %xmm0, -101(%edx) +L(aligned_16_85bytes): + movdqa %xmm0, -85(%edx) +L(aligned_16_69bytes): + movdqa %xmm0, -69(%edx) +L(aligned_16_53bytes): + movdqa %xmm0, -53(%edx) +L(aligned_16_37bytes): + movdqa %xmm0, -37(%edx) +L(aligned_16_21bytes): + movdqa %xmm0, -21(%edx) +L(aligned_16_5bytes): + movl %eax, -5(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_118bytes): + movdqa %xmm0, -118(%edx) +L(aligned_16_102bytes): + movdqa %xmm0, -102(%edx) +L(aligned_16_86bytes): + movdqa %xmm0, -86(%edx) +L(aligned_16_70bytes): + movdqa %xmm0, -70(%edx) +L(aligned_16_54bytes): + movdqa %xmm0, -54(%edx) +L(aligned_16_38bytes): + movdqa %xmm0, -38(%edx) +L(aligned_16_22bytes): + movdqa %xmm0, -22(%edx) +L(aligned_16_6bytes): + movl %eax, -6(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_119bytes): + movdqa %xmm0, -119(%edx) +L(aligned_16_103bytes): + movdqa %xmm0, -103(%edx) +L(aligned_16_87bytes): + movdqa %xmm0, -87(%edx) +L(aligned_16_71bytes): + movdqa %xmm0, -71(%edx) +L(aligned_16_55bytes): + movdqa %xmm0, -55(%edx) +L(aligned_16_39bytes): + movdqa %xmm0, -39(%edx) +L(aligned_16_23bytes): + movdqa %xmm0, -23(%edx) +L(aligned_16_7bytes): + movl %eax, -7(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_120bytes): + movdqa %xmm0, -120(%edx) +L(aligned_16_104bytes): + movdqa %xmm0, -104(%edx) +L(aligned_16_88bytes): + movdqa %xmm0, -88(%edx) +L(aligned_16_72bytes): + movdqa %xmm0, -72(%edx) +L(aligned_16_56bytes): + movdqa %xmm0, -56(%edx) +L(aligned_16_40bytes): + movdqa %xmm0, -40(%edx) +L(aligned_16_24bytes): + movdqa %xmm0, -24(%edx) +L(aligned_16_8bytes): + movq %xmm0, -8(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_121bytes): + movdqa %xmm0, -121(%edx) +L(aligned_16_105bytes): + movdqa %xmm0, -105(%edx) +L(aligned_16_89bytes): + movdqa %xmm0, -89(%edx) +L(aligned_16_73bytes): + movdqa %xmm0, -73(%edx) +L(aligned_16_57bytes): + movdqa %xmm0, -57(%edx) +L(aligned_16_41bytes): + movdqa %xmm0, -41(%edx) +L(aligned_16_25bytes): + movdqa %xmm0, -25(%edx) +L(aligned_16_9bytes): + movq %xmm0, -9(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_122bytes): + movdqa %xmm0, -122(%edx) +L(aligned_16_106bytes): + movdqa %xmm0, -106(%edx) +L(aligned_16_90bytes): + movdqa %xmm0, -90(%edx) +L(aligned_16_74bytes): + movdqa %xmm0, -74(%edx) +L(aligned_16_58bytes): + movdqa %xmm0, -58(%edx) +L(aligned_16_42bytes): + movdqa %xmm0, -42(%edx) +L(aligned_16_26bytes): + movdqa %xmm0, -26(%edx) +L(aligned_16_10bytes): + movq %xmm0, -10(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_123bytes): + movdqa %xmm0, -123(%edx) +L(aligned_16_107bytes): + movdqa %xmm0, -107(%edx) +L(aligned_16_91bytes): + movdqa %xmm0, -91(%edx) +L(aligned_16_75bytes): + movdqa %xmm0, -75(%edx) +L(aligned_16_59bytes): + movdqa %xmm0, -59(%edx) +L(aligned_16_43bytes): + movdqa %xmm0, -43(%edx) +L(aligned_16_27bytes): + movdqa %xmm0, -27(%edx) +L(aligned_16_11bytes): + movq %xmm0, -11(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_124bytes): + movdqa %xmm0, -124(%edx) +L(aligned_16_108bytes): + movdqa %xmm0, -108(%edx) +L(aligned_16_92bytes): + movdqa %xmm0, -92(%edx) +L(aligned_16_76bytes): + movdqa %xmm0, -76(%edx) +L(aligned_16_60bytes): + movdqa %xmm0, -60(%edx) +L(aligned_16_44bytes): + movdqa %xmm0, -44(%edx) +L(aligned_16_28bytes): + movdqa %xmm0, -28(%edx) +L(aligned_16_12bytes): + movq %xmm0, -12(%edx) + movl %eax, -4(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_125bytes): + movdqa %xmm0, -125(%edx) +L(aligned_16_109bytes): + movdqa %xmm0, -109(%edx) +L(aligned_16_93bytes): + movdqa %xmm0, -93(%edx) +L(aligned_16_77bytes): + movdqa %xmm0, -77(%edx) +L(aligned_16_61bytes): + movdqa %xmm0, -61(%edx) +L(aligned_16_45bytes): + movdqa %xmm0, -45(%edx) +L(aligned_16_29bytes): + movdqa %xmm0, -29(%edx) +L(aligned_16_13bytes): + movq %xmm0, -13(%edx) + movl %eax, -5(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_126bytes): + movdqa %xmm0, -126(%edx) +L(aligned_16_110bytes): + movdqa %xmm0, -110(%edx) +L(aligned_16_94bytes): + movdqa %xmm0, -94(%edx) +L(aligned_16_78bytes): + movdqa %xmm0, -78(%edx) +L(aligned_16_62bytes): + movdqa %xmm0, -62(%edx) +L(aligned_16_46bytes): + movdqa %xmm0, -46(%edx) +L(aligned_16_30bytes): + movdqa %xmm0, -30(%edx) +L(aligned_16_14bytes): + movq %xmm0, -14(%edx) + movl %eax, -6(%edx) + movw %ax, -2(%edx) + SETRTNVAL + RETURN + + ALIGN(4) +L(aligned_16_127bytes): + movdqa %xmm0, -127(%edx) +L(aligned_16_111bytes): + movdqa %xmm0, -111(%edx) +L(aligned_16_95bytes): + movdqa %xmm0, -95(%edx) +L(aligned_16_79bytes): + movdqa %xmm0, -79(%edx) +L(aligned_16_63bytes): + movdqa %xmm0, -63(%edx) +L(aligned_16_47bytes): + movdqa %xmm0, -47(%edx) +L(aligned_16_31bytes): + movdqa %xmm0, -31(%edx) +L(aligned_16_15bytes): + movq %xmm0, -15(%edx) + movl %eax, -7(%edx) + movw %ax, -3(%edx) + movb %al, -1(%edx) + SETRTNVAL + RETURN_END + +END(memset)
diff --git a/libc/arch-x86/silvermont/string/sse2-stpcpy-slm.S b/libc/arch-x86/silvermont/string/sse2-stpcpy-slm.S new file mode 100755 index 0000000..5c43fa5 --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-stpcpy-slm.S
@@ -0,0 +1,33 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STPCPY +#define STRCPY stpcpy +#include "sse2-strcpy-slm.S"
diff --git a/libc/arch-x86/silvermont/string/sse2-stpncpy-slm.S b/libc/arch-x86/silvermont/string/sse2-stpncpy-slm.S new file mode 100644 index 0000000..af5c0d3 --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-stpncpy-slm.S
@@ -0,0 +1,34 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STRNCPY +#define USE_AS_STPCPY +#define STRCPY stpncpy +#include "sse2-strcpy-slm.S"
diff --git a/libc/arch-x86/silvermont/string/sse2-strcpy-slm.S b/libc/arch-x86/silvermont/string/sse2-strcpy-slm.S new file mode 100755 index 0000000..b5d84b5 --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-strcpy-slm.S
@@ -0,0 +1,2157 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#ifndef STRCPY +# define STRCPY strcpy +#endif + +#ifdef USE_AS_STPNCPY +# define USE_AS_STRNCPY +# define USE_AS_STPCPY +#endif + +#ifdef USE_AS_STRNCPY +# define PARMS 16 +# define ENTRANCE PUSH(%ebx); PUSH(%esi); PUSH(%edi) +# define RETURN POP(%edi); POP(%esi); POP(%ebx); ret; CFI_PUSH(%ebx); CFI_PUSH(%edi); CFI_PUSH(%edi); +#else +# define PARMS 12 +# define ENTRANCE PUSH(%esi); PUSH(%edi) +# define RETURN POP(%edi); POP(%esi); ret; CFI_PUSH(%esi); CFI_PUSH(%edi); +#endif + +#define STR1 PARMS +#define STR2 STR1+4 +#define LEN STR2+4 + + +#if (defined SHARED || defined __PIC__) +# define JMPTBL(I, B) I - B + +/* Load an entry in a jump table into ECX and branch to it. TABLE is a + jump table with relative offsets. INDEX is a register contains the + index into the jump table. SCALE is the scale of INDEX. */ + +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ + /* We first load PC into ECX. */ \ + call __x86.get_pc_thunk.cx; \ + /* Get the address of the jump table. */ \ + addl $(TABLE - .), %ecx; \ + /* Get the entry and convert the relative offset to the \ + absolute address. */ \ + addl (%ecx,INDEX,SCALE), %ecx; \ + /* We loaded the jump table and adjuested ECX. Go. */ \ + jmp *%ecx +#else +# define JMPTBL(I, B) I + +/* Branch to an entry in a jump table. TABLE is a jump table with + absolute offsets. INDEX is a register contains the index into the + jump table. SCALE is the scale of INDEX. */ + +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ + jmp *TABLE(,INDEX,SCALE) +#endif + +.text +ENTRY (STRCPY) + ENTRANCE + mov STR1(%esp), %edi + mov STR2(%esp), %esi +#ifdef USE_AS_STRNCPY + movl LEN(%esp), %ebx + test %ebx, %ebx + jz L(ExitZero) +#endif + + mov %esi, %ecx +#ifndef USE_AS_STPCPY + mov %edi, %eax /* save result */ +#endif + and $15, %ecx + jz L(SourceStringAlignmentZero) + + and $-16, %esi + pxor %xmm0, %xmm0 + pxor %xmm1, %xmm1 + + pcmpeqb (%esi), %xmm1 +#ifdef USE_AS_STRNCPY + add %ecx, %ebx +#endif + pmovmskb %xmm1, %edx + shr %cl, %edx +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + cmp $16, %ebx + jbe L(CopyFrom1To16BytesTailCase2OrCase3) +#else + cmp $17, %ebx + jbe L(CopyFrom1To16BytesTailCase2OrCase3) +#endif +#endif + test %edx, %edx + jnz L(CopyFrom1To16BytesTail) + + pcmpeqb 16(%esi), %xmm0 + pmovmskb %xmm0, %edx +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + cmp $32, %ebx + jbe L(CopyFrom1To32BytesCase2OrCase3) +#else + cmp $33, %ebx + jbe L(CopyFrom1To32BytesCase2OrCase3) +#endif +#endif + test %edx, %edx + jnz L(CopyFrom1To32Bytes) + + movdqu (%esi, %ecx), %xmm1 /* copy 16 bytes */ + movdqu %xmm1, (%edi) + + sub %ecx, %edi + mov %edi, %edx + mov $16, %ecx + and $15, %edx + jz L(Align16Both) + +/* If source adress alignment != destination adress alignment */ + .p2align 4 +L(Unalign16Both): + movdqa (%esi, %ecx), %xmm1 + movaps 16(%esi, %ecx), %xmm2 + movdqu %xmm1, (%edi, %ecx) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $48, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm2) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movaps 16(%esi, %ecx), %xmm3 + movdqu %xmm2, (%edi, %ecx) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm3) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movaps 16(%esi, %ecx), %xmm4 + movdqu %xmm3, (%edi, %ecx) + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm4) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movaps 16(%esi, %ecx), %xmm1 + movdqu %xmm4, (%edi, %ecx) + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm1) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movaps 16(%esi, %ecx), %xmm2 + movdqu %xmm1, (%edi, %ecx) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm2) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movaps 16(%esi, %ecx), %xmm3 + movdqu %xmm2, (%edi, %ecx) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm3) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqu %xmm3, (%edi, %ecx) + mov %esi, %edx + lea 16(%esi, %ecx), %esi + and $-0x40, %esi + sub %esi, %edx + sub %edx, %edi +#ifdef USE_AS_STRNCPY + lea 64+64(%ebx, %edx), %ebx +#endif +L(Unaligned64Loop): + movaps (%esi), %xmm2 + movaps %xmm2, %xmm4 + movaps 16(%esi), %xmm5 + movaps 32(%esi), %xmm3 + movaps %xmm3, %xmm6 + movaps 48(%esi), %xmm7 + pminub %xmm5, %xmm2 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + pcmpeqb %xmm0, %xmm3 + pmovmskb %xmm3, %edx +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(UnalignedLeaveCase2OrCase3) +#endif + test %edx, %edx + jnz L(Unaligned64Leave) + +L(Unaligned64Loop_start): + add $64, %edi + add $64, %esi + movdqu %xmm4, -64(%edi) + movaps (%esi), %xmm2 + movdqa %xmm2, %xmm4 + movdqu %xmm5, -48(%edi) + movaps 16(%esi), %xmm5 + pminub %xmm5, %xmm2 + movaps 32(%esi), %xmm3 + movdqu %xmm6, -32(%edi) + movaps %xmm3, %xmm6 + movdqu %xmm7, -16(%edi) + movaps 48(%esi), %xmm7 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(UnalignedLeaveCase2OrCase3) +#endif + test %edx, %edx + jz L(Unaligned64Loop_start) + +L(Unaligned64Leave): + pxor %xmm0, %xmm0 + pxor %xmm1, %xmm1 + + pcmpeqb %xmm4, %xmm0 + pcmpeqb %xmm5, %xmm1 + pmovmskb %xmm0, %edx + pmovmskb %xmm1, %ecx + test %edx, %edx + jnz L(CopyFrom1To16BytesUnaligned_0) + test %ecx, %ecx + jnz L(CopyFrom1To16BytesUnaligned_16) + + pcmpeqb %xmm6, %xmm0 + pcmpeqb %xmm7, %xmm1 + pmovmskb %xmm0, %edx + pmovmskb %xmm1, %ecx + test %edx, %edx + jnz L(CopyFrom1To16BytesUnaligned_32) + + bsf %ecx, %edx + movdqu %xmm4, (%edi) + movdqu %xmm5, 16(%edi) + movdqu %xmm6, 32(%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 48(%edi, %edx), %eax +#endif + movdqu %xmm7, 48(%edi) + add $15, %ebx + sub %edx, %ebx + lea 49(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $48, %esi + add $48, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + +/* If source adress alignment == destination adress alignment */ + +L(SourceStringAlignmentZero): + pxor %xmm0, %xmm0 + movdqa (%esi), %xmm1 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %edx + +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + cmp $16, %ebx + jbe L(CopyFrom1To16BytesTail1Case2OrCase3) +#else + cmp $17, %ebx + jbe L(CopyFrom1To16BytesTail1Case2OrCase3) +#endif +#endif + test %edx, %edx + jnz L(CopyFrom1To16BytesTail1) + + pcmpeqb 16(%esi), %xmm0 + movdqu %xmm1, (%edi) + pmovmskb %xmm0, %edx + +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + cmp $32, %ebx + jbe L(CopyFrom1To32Bytes1Case2OrCase3) +#else + cmp $33, %ebx + jbe L(CopyFrom1To32Bytes1Case2OrCase3) +#endif +#endif + test %edx, %edx + jnz L(CopyFrom1To32Bytes1) + + mov %edi, %edx + mov $16, %ecx + and $15, %edx + jnz L(Unalign16Both) + +L(Align16Both): + movdqa (%esi, %ecx), %xmm1 + movdqa 16(%esi, %ecx), %xmm2 + movdqa %xmm1, (%edi, %ecx) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %edx + add $16, %ecx +#ifdef USE_AS_STRNCPY + sub $48, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm2) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa 16(%esi, %ecx), %xmm3 + movdqa %xmm2, (%edi, %ecx) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm3) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa 16(%esi, %ecx), %xmm4 + movdqa %xmm3, (%edi, %ecx) + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %edx + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm4) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa 16(%esi, %ecx), %xmm1 + movdqa %xmm4, (%edi, %ecx) + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %edx + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm1) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa 16(%esi, %ecx), %xmm2 + movdqa %xmm1, (%edi, %ecx) + pcmpeqb %xmm2, %xmm0 + pmovmskb %xmm0, %edx + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm2) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa 16(%esi, %ecx), %xmm3 + movdqa %xmm2, (%edi, %ecx) + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx + lea 16(%ecx), %ecx +#ifdef USE_AS_STRNCPY + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm3) +#else + test %edx, %edx + jnz L(CopyFrom1To16Bytes) +#endif + + movdqa %xmm3, (%edi, %ecx) + mov %esi, %edx + lea 16(%esi, %ecx), %esi + and $-0x40, %esi + sub %esi, %edx + sub %edx, %edi +#ifdef USE_AS_STRNCPY + lea 64+64(%ebx, %edx), %ebx +#endif +L(Aligned64Loop): + movdqa (%esi), %xmm2 + movdqa %xmm2, %xmm4 + movaps 16(%esi), %xmm5 + movdqa 32(%esi), %xmm3 + movdqa %xmm3, %xmm6 + movaps 48(%esi), %xmm7 + pminub %xmm5, %xmm2 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + pcmpeqb %xmm0, %xmm3 + pmovmskb %xmm3, %edx +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(AlignedLeaveCase2OrCase3) +#endif + test %edx, %edx + jnz L(Aligned64Leave) + +L(Aligned64Loop_start): + add $64, %esi + add $64, %edi + movaps %xmm4, -64(%edi) + movdqa (%esi), %xmm2 + movdqa %xmm2, %xmm4 + movaps %xmm5, -48(%edi) + movaps 16(%esi), %xmm5 + pminub %xmm5, %xmm2 + movaps 32(%esi), %xmm3 + movaps %xmm6, -32(%edi) + movdqa %xmm3, %xmm6 + movaps %xmm7, -16(%edi) + movaps 48(%esi), %xmm7 + pminub %xmm7, %xmm3 + pminub %xmm2, %xmm3 + pcmpeqb %xmm3, %xmm0 + pmovmskb %xmm0, %edx +#ifdef USE_AS_STRNCPY + sub $64, %ebx + jbe L(AlignedLeaveCase2OrCase3) +#endif + test %edx, %edx + jz L(Aligned64Loop_start) + +L(Aligned64Leave): + pxor %xmm0, %xmm0 + pxor %xmm1, %xmm1 + + pcmpeqb %xmm4, %xmm0 + pcmpeqb %xmm5, %xmm1 + pmovmskb %xmm0, %edx + pmovmskb %xmm1, %ecx + test %edx, %edx + jnz L(CopyFrom1To16Bytes_0) + test %ecx, %ecx + jnz L(CopyFrom1To16Bytes_16) + + pcmpeqb %xmm6, %xmm0 + pcmpeqb %xmm7, %xmm1 + pmovmskb %xmm0, %edx + pmovmskb %xmm1, %ecx + test %edx, %edx + jnz L(CopyFrom1To16Bytes_32) + + bsf %ecx, %edx + movdqa %xmm4, (%edi) + movdqa %xmm5, 16(%edi) + movdqa %xmm6, 32(%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 48(%edi, %edx), %eax +#endif + movdqa %xmm7, 48(%edi) + add $15, %ebx + sub %edx, %ebx + lea 49(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $48, %esi + add $48, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + +/*----------------------------------------------------*/ + +/* Case1 */ +#ifndef USE_AS_STRNCPY + .p2align 4 +L(CopyFrom1To16Bytes): + add %ecx, %edi + add %ecx, %esi + bsf %edx, %edx + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + .p2align 4 +L(CopyFrom1To16BytesTail): +#ifdef USE_AS_STRNCPY + sub %ecx, %ebx +#endif + add %ecx, %esi + bsf %edx, %edx + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) + + .p2align 4 +L(CopyFrom1To32Bytes1): + add $16, %esi + add $16, %edi +#ifdef USE_AS_STRNCPY + sub $16, %ebx +#endif +L(CopyFrom1To16BytesTail1): + bsf %edx, %edx + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) + + .p2align 4 +L(CopyFrom1To32Bytes): +#ifdef USE_AS_STRNCPY + sub %ecx, %ebx +#endif + bsf %edx, %edx + add %ecx, %esi + add $16, %edx + sub %ecx, %edx + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) + + .p2align 4 +L(CopyFrom1To16Bytes_0): + bsf %edx, %edx +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea (%edi, %edx), %eax +#endif + movdqa %xmm4, (%edi) + add $63, %ebx + sub %edx, %ebx + lea 1(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + + .p2align 4 +L(CopyFrom1To16Bytes_16): + bsf %ecx, %edx + movdqa %xmm4, (%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 16(%edi, %edx), %eax +#endif + movdqa %xmm5, 16(%edi) + add $47, %ebx + sub %edx, %ebx + lea 17(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $16, %esi + add $16, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + + .p2align 4 +L(CopyFrom1To16Bytes_32): + bsf %edx, %edx + movdqa %xmm4, (%edi) + movdqa %xmm5, 16(%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 32(%edi, %edx), %eax +#endif + movdqa %xmm6, 32(%edi) + add $31, %ebx + sub %edx, %ebx + lea 33(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $32, %esi + add $32, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + + .p2align 4 +L(CopyFrom1To16BytesUnaligned_0): + bsf %edx, %edx +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea (%edi, %edx), %eax +#endif + movdqu %xmm4, (%edi) + add $63, %ebx + sub %edx, %ebx + lea 1(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + + .p2align 4 +L(CopyFrom1To16BytesUnaligned_16): + bsf %ecx, %edx + movdqu %xmm4, (%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 16(%edi, %edx), %eax +#endif + movdqu %xmm5, 16(%edi) + add $47, %ebx + sub %edx, %ebx + lea 17(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $16, %esi + add $16, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + + .p2align 4 +L(CopyFrom1To16BytesUnaligned_32): + bsf %edx, %edx + movdqu %xmm4, (%edi) + movdqu %xmm5, 16(%edi) +#ifdef USE_AS_STRNCPY +#ifdef USE_AS_STPCPY + lea 32(%edi, %edx), %eax +#endif + movdqu %xmm6, 32(%edi) + add $31, %ebx + sub %edx, %ebx + lea 33(%edi, %edx), %edi + jmp L(StrncpyFillTailWithZero) +#else + add $32, %esi + add $32, %edi + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) +#endif + +#ifdef USE_AS_STRNCPY + .p2align 4 +L(CopyFrom1To16BytesXmm6): + movdqa %xmm6, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesXmm5): + movdqa %xmm5, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesXmm4): + movdqa %xmm4, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesXmm3): + movdqa %xmm3, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesXmm2): + movdqa %xmm2, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesXmm1): + movdqa %xmm1, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm6): + movdqu %xmm6, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm5): + movdqu %xmm5, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm4): + movdqu %xmm4, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm3): + movdqu %xmm3, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm1): + movdqu %xmm1, (%edi, %ecx) + jmp L(CopyFrom1To16BytesXmmExit) + + .p2align 4 +L(CopyFrom1To16BytesExit): + BRANCH_TO_JMPTBL_ENTRY (L(ExitTable), %edx, 4) + +/* Case2 */ + + .p2align 4 +L(CopyFrom1To16BytesCase2): + add $16, %ebx + add %ecx, %edi + add %ecx, %esi + bsf %edx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(CopyFrom1To32BytesCase2): + sub %ecx, %ebx + add %ecx, %esi + bsf %edx, %edx + add $16, %edx + sub %ecx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + +L(CopyFrom1To16BytesTailCase2): + sub %ecx, %ebx + add %ecx, %esi + bsf %edx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + +L(CopyFrom1To16BytesTail1Case2): + bsf %edx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + +/* Case2 or Case3, Case3 */ + + .p2align 4 +L(CopyFrom1To16BytesCase2OrCase3): + test %edx, %edx + jnz L(CopyFrom1To16BytesCase2) +L(CopyFrom1To16BytesCase3): + add $16, %ebx + add %ecx, %edi + add %ecx, %esi + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(CopyFrom1To32BytesCase2OrCase3): + test %edx, %edx + jnz L(CopyFrom1To32BytesCase2) + sub %ecx, %ebx + add %ecx, %esi + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(CopyFrom1To16BytesTailCase2OrCase3): + test %edx, %edx + jnz L(CopyFrom1To16BytesTailCase2) + sub %ecx, %ebx + add %ecx, %esi + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(CopyFrom1To32Bytes1Case2OrCase3): + add $16, %edi + add $16, %esi + sub $16, %ebx +L(CopyFrom1To16BytesTail1Case2OrCase3): + test %edx, %edx + jnz L(CopyFrom1To16BytesTail1Case2) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + +#endif + +/*-----------------------------------------------------------------*/ + .p2align 4 +L(Exit0): +#ifdef USE_AS_STPCPY + mov %edi, %eax +#endif + RETURN + + .p2align 4 +L(Exit1): + movb %dh, (%edi) +#ifdef USE_AS_STPCPY + lea (%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $1, %ebx + lea 1(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit2): + movw (%esi), %dx + movw %dx, (%edi) +#ifdef USE_AS_STPCPY + lea 1(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $2, %ebx + lea 2(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit3): + movw (%esi), %cx + movw %cx, (%edi) + movb %dh, 2(%edi) +#ifdef USE_AS_STPCPY + lea 2(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $3, %ebx + lea 3(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit4): + movl (%esi), %edx + movl %edx, (%edi) +#ifdef USE_AS_STPCPY + lea 3(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $4, %ebx + lea 4(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit5): + movl (%esi), %ecx + movb %dh, 4(%edi) + movl %ecx, (%edi) +#ifdef USE_AS_STPCPY + lea 4(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $5, %ebx + lea 5(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit6): + movl (%esi), %ecx + movw 4(%esi), %dx + movl %ecx, (%edi) + movw %dx, 4(%edi) +#ifdef USE_AS_STPCPY + lea 5(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $6, %ebx + lea 6(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit7): + movl (%esi), %ecx + movl 3(%esi), %edx + movl %ecx, (%edi) + movl %edx, 3(%edi) +#ifdef USE_AS_STPCPY + lea 6(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $7, %ebx + lea 7(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit8): + movlpd (%esi), %xmm0 + movlpd %xmm0, (%edi) +#ifdef USE_AS_STPCPY + lea 7(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $8, %ebx + lea 8(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit9): + movlpd (%esi), %xmm0 + movb %dh, 8(%edi) + movlpd %xmm0, (%edi) +#ifdef USE_AS_STPCPY + lea 8(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $9, %ebx + lea 9(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit10): + movlpd (%esi), %xmm0 + movw 8(%esi), %dx + movlpd %xmm0, (%edi) + movw %dx, 8(%edi) +#ifdef USE_AS_STPCPY + lea 9(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $10, %ebx + lea 10(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit11): + movlpd (%esi), %xmm0 + movl 7(%esi), %edx + movlpd %xmm0, (%edi) + movl %edx, 7(%edi) +#ifdef USE_AS_STPCPY + lea 10(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $11, %ebx + lea 11(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit12): + movlpd (%esi), %xmm0 + movl 8(%esi), %edx + movlpd %xmm0, (%edi) + movl %edx, 8(%edi) +#ifdef USE_AS_STPCPY + lea 11(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $12, %ebx + lea 12(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit13): + movlpd (%esi), %xmm0 + movlpd 5(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 5(%edi) +#ifdef USE_AS_STPCPY + lea 12(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $13, %ebx + lea 13(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit14): + movlpd (%esi), %xmm0 + movlpd 6(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 6(%edi) +#ifdef USE_AS_STPCPY + lea 13(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $14, %ebx + lea 14(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit15): + movlpd (%esi), %xmm0 + movlpd 7(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 7(%edi) +#ifdef USE_AS_STPCPY + lea 14(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $15, %ebx + lea 15(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit16): + movdqu (%esi), %xmm0 + movdqu %xmm0, (%edi) +#ifdef USE_AS_STPCPY + lea 15(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $16, %ebx + lea 16(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit17): + movdqu (%esi), %xmm0 + xor %cl, %cl + movdqu %xmm0, (%edi) + movb %cl, 16(%edi) +#ifdef USE_AS_STPCPY + lea 16(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $17, %ebx + lea 17(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit18): + movdqu (%esi), %xmm0 + movw 16(%esi), %cx + movdqu %xmm0, (%edi) + movw %cx, 16(%edi) +#ifdef USE_AS_STPCPY + lea 17(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $18, %ebx + lea 18(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit19): + movdqu (%esi), %xmm0 + movl 15(%esi), %ecx + movdqu %xmm0, (%edi) + movl %ecx, 15(%edi) +#ifdef USE_AS_STPCPY + lea 18(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $19, %ebx + lea 19(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit20): + movdqu (%esi), %xmm0 + movl 16(%esi), %ecx + movdqu %xmm0, (%edi) + movl %ecx, 16(%edi) +#ifdef USE_AS_STPCPY + lea 19(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $20, %ebx + lea 20(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit21): + movdqu (%esi), %xmm0 + movl 16(%esi), %ecx + xor %dl, %dl + movdqu %xmm0, (%edi) + movl %ecx, 16(%edi) + movb %dl, 20(%edi) +#ifdef USE_AS_STPCPY + lea 20(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $21, %ebx + lea 21(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit22): + movdqu (%esi), %xmm0 + movlpd 14(%esi), %xmm3 + movdqu %xmm0, (%edi) + movlpd %xmm3, 14(%edi) +#ifdef USE_AS_STPCPY + lea 21(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $22, %ebx + lea 22(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit23): + movdqu (%esi), %xmm0 + movlpd 15(%esi), %xmm3 + movdqu %xmm0, (%edi) + movlpd %xmm3, 15(%edi) +#ifdef USE_AS_STPCPY + lea 22(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $23, %ebx + lea 23(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit24): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) +#ifdef USE_AS_STPCPY + lea 23(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $24, %ebx + lea 24(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit25): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + xor %cl, %cl + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movb %cl, 24(%edi) +#ifdef USE_AS_STPCPY + lea 24(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $25, %ebx + lea 25(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit26): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movw 24(%esi), %cx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movw %cx, 24(%edi) +#ifdef USE_AS_STPCPY + lea 25(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $26, %ebx + lea 26(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit27): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movl 23(%esi), %ecx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movl %ecx, 23(%edi) +#ifdef USE_AS_STPCPY + lea 26(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $27, %ebx + lea 27(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit28): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movl 24(%esi), %ecx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movl %ecx, 24(%edi) +#ifdef USE_AS_STPCPY + lea 27(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $28, %ebx + lea 28(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit29): + movdqu (%esi), %xmm0 + movdqu 13(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 13(%edi) +#ifdef USE_AS_STPCPY + lea 28(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $29, %ebx + lea 29(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit30): + movdqu (%esi), %xmm0 + movdqu 14(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 14(%edi) +#ifdef USE_AS_STPCPY + lea 29(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $30, %ebx + lea 30(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + + .p2align 4 +L(Exit31): + movdqu (%esi), %xmm0 + movdqu 15(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 15(%edi) +#ifdef USE_AS_STPCPY + lea 30(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $31, %ebx + lea 31(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + + .p2align 4 +L(Exit32): + movdqu (%esi), %xmm0 + movdqu 16(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 16(%edi) +#ifdef USE_AS_STPCPY + lea 31(%edi), %eax +#endif +#ifdef USE_AS_STRNCPY + sub $32, %ebx + lea 32(%edi), %edi + jnz L(StrncpyFillTailWithZero) +#endif + RETURN + +#ifdef USE_AS_STRNCPY + + .p2align 4 +L(StrncpyExit1): + movb (%esi), %dl + movb %dl, (%edi) +#ifdef USE_AS_STPCPY + lea 1(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit2): + movw (%esi), %dx + movw %dx, (%edi) +#ifdef USE_AS_STPCPY + lea 2(%edi), %eax +#endif + RETURN + .p2align 4 +L(StrncpyExit3): + movw (%esi), %cx + movb 2(%esi), %dl + movw %cx, (%edi) + movb %dl, 2(%edi) +#ifdef USE_AS_STPCPY + lea 3(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit4): + movl (%esi), %edx + movl %edx, (%edi) +#ifdef USE_AS_STPCPY + lea 4(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit5): + movl (%esi), %ecx + movb 4(%esi), %dl + movl %ecx, (%edi) + movb %dl, 4(%edi) +#ifdef USE_AS_STPCPY + lea 5(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit6): + movl (%esi), %ecx + movw 4(%esi), %dx + movl %ecx, (%edi) + movw %dx, 4(%edi) +#ifdef USE_AS_STPCPY + lea 6(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit7): + movl (%esi), %ecx + movl 3(%esi), %edx + movl %ecx, (%edi) + movl %edx, 3(%edi) +#ifdef USE_AS_STPCPY + lea 7(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit8): + movlpd (%esi), %xmm0 + movlpd %xmm0, (%edi) +#ifdef USE_AS_STPCPY + lea 8(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit9): + movlpd (%esi), %xmm0 + movb 8(%esi), %dl + movlpd %xmm0, (%edi) + movb %dl, 8(%edi) +#ifdef USE_AS_STPCPY + lea 9(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit10): + movlpd (%esi), %xmm0 + movw 8(%esi), %dx + movlpd %xmm0, (%edi) + movw %dx, 8(%edi) +#ifdef USE_AS_STPCPY + lea 10(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit11): + movlpd (%esi), %xmm0 + movl 7(%esi), %edx + movlpd %xmm0, (%edi) + movl %edx, 7(%edi) +#ifdef USE_AS_STPCPY + lea 11(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit12): + movlpd (%esi), %xmm0 + movl 8(%esi), %edx + movlpd %xmm0, (%edi) + movl %edx, 8(%edi) +#ifdef USE_AS_STPCPY + lea 12(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit13): + movlpd (%esi), %xmm0 + movlpd 5(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 5(%edi) +#ifdef USE_AS_STPCPY + lea 13(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit14): + movlpd (%esi), %xmm0 + movlpd 6(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 6(%edi) +#ifdef USE_AS_STPCPY + lea 14(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit15): + movlpd (%esi), %xmm0 + movlpd 7(%esi), %xmm1 + movlpd %xmm0, (%edi) + movlpd %xmm1, 7(%edi) +#ifdef USE_AS_STPCPY + lea 15(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit16): + movdqu (%esi), %xmm0 + movdqu %xmm0, (%edi) +#ifdef USE_AS_STPCPY + lea 16(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit17): + movdqu (%esi), %xmm0 + movb 16(%esi), %cl + movdqu %xmm0, (%edi) + movb %cl, 16(%edi) +#ifdef USE_AS_STPCPY + lea 17(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit18): + movdqu (%esi), %xmm0 + movw 16(%esi), %cx + movdqu %xmm0, (%edi) + movw %cx, 16(%edi) +#ifdef USE_AS_STPCPY + lea 18(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit19): + movdqu (%esi), %xmm0 + movl 15(%esi), %ecx + movdqu %xmm0, (%edi) + movl %ecx, 15(%edi) +#ifdef USE_AS_STPCPY + lea 19(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit20): + movdqu (%esi), %xmm0 + movl 16(%esi), %ecx + movdqu %xmm0, (%edi) + movl %ecx, 16(%edi) +#ifdef USE_AS_STPCPY + lea 20(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit21): + movdqu (%esi), %xmm0 + movl 16(%esi), %ecx + movb 20(%esi), %dl + movdqu %xmm0, (%edi) + movl %ecx, 16(%edi) + movb %dl, 20(%edi) +#ifdef USE_AS_STPCPY + lea 21(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit22): + movdqu (%esi), %xmm0 + movlpd 14(%esi), %xmm3 + movdqu %xmm0, (%edi) + movlpd %xmm3, 14(%edi) +#ifdef USE_AS_STPCPY + lea 22(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit23): + movdqu (%esi), %xmm0 + movlpd 15(%esi), %xmm3 + movdqu %xmm0, (%edi) + movlpd %xmm3, 15(%edi) +#ifdef USE_AS_STPCPY + lea 23(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit24): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) +#ifdef USE_AS_STPCPY + lea 24(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit25): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movb 24(%esi), %cl + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movb %cl, 24(%edi) +#ifdef USE_AS_STPCPY + lea 25(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit26): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movw 24(%esi), %cx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movw %cx, 24(%edi) +#ifdef USE_AS_STPCPY + lea 26(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit27): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movl 23(%esi), %ecx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movl %ecx, 23(%edi) +#ifdef USE_AS_STPCPY + lea 27(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit28): + movdqu (%esi), %xmm0 + movlpd 16(%esi), %xmm2 + movl 24(%esi), %ecx + movdqu %xmm0, (%edi) + movlpd %xmm2, 16(%edi) + movl %ecx, 24(%edi) +#ifdef USE_AS_STPCPY + lea 28(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit29): + movdqu (%esi), %xmm0 + movdqu 13(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 13(%edi) +#ifdef USE_AS_STPCPY + lea 29(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit30): + movdqu (%esi), %xmm0 + movdqu 14(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 14(%edi) +#ifdef USE_AS_STPCPY + lea 30(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit31): + movdqu (%esi), %xmm0 + movdqu 15(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 15(%edi) +#ifdef USE_AS_STPCPY + lea 31(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit32): + movdqu (%esi), %xmm0 + movdqu 16(%esi), %xmm2 + movdqu %xmm0, (%edi) + movdqu %xmm2, 16(%edi) +#ifdef USE_AS_STPCPY + lea 32(%edi), %eax +#endif + RETURN + + .p2align 4 +L(StrncpyExit33): + movdqu (%esi), %xmm0 + movdqu 16(%esi), %xmm2 + movb 32(%esi), %cl + movdqu %xmm0, (%edi) + movdqu %xmm2, 16(%edi) + movb %cl, 32(%edi) + RETURN + + .p2align 4 +L(Fill0): + RETURN + + .p2align 4 +L(Fill1): + movb %dl, (%edi) + RETURN + + .p2align 4 +L(Fill2): + movw %dx, (%edi) + RETURN + + .p2align 4 +L(Fill3): + movl %edx, -1(%edi) + RETURN + + .p2align 4 +L(Fill4): + movl %edx, (%edi) + RETURN + + .p2align 4 +L(Fill5): + movl %edx, (%edi) + movb %dl, 4(%edi) + RETURN + + .p2align 4 +L(Fill6): + movl %edx, (%edi) + movw %dx, 4(%edi) + RETURN + + .p2align 4 +L(Fill7): + movlpd %xmm0, -1(%edi) + RETURN + + .p2align 4 +L(Fill8): + movlpd %xmm0, (%edi) + RETURN + + .p2align 4 +L(Fill9): + movlpd %xmm0, (%edi) + movb %dl, 8(%edi) + RETURN + + .p2align 4 +L(Fill10): + movlpd %xmm0, (%edi) + movw %dx, 8(%edi) + RETURN + + .p2align 4 +L(Fill11): + movlpd %xmm0, (%edi) + movl %edx, 7(%edi) + RETURN + + .p2align 4 +L(Fill12): + movlpd %xmm0, (%edi) + movl %edx, 8(%edi) + RETURN + + .p2align 4 +L(Fill13): + movlpd %xmm0, (%edi) + movlpd %xmm0, 5(%edi) + RETURN + + .p2align 4 +L(Fill14): + movlpd %xmm0, (%edi) + movlpd %xmm0, 6(%edi) + RETURN + + .p2align 4 +L(Fill15): + movdqu %xmm0, -1(%edi) + RETURN + + .p2align 4 +L(Fill16): + movdqu %xmm0, (%edi) + RETURN + + .p2align 4 +L(CopyFrom1To16BytesUnalignedXmm2): + movdqu %xmm2, (%edi, %ecx) + + .p2align 4 +L(CopyFrom1To16BytesXmmExit): + bsf %edx, %edx + add $15, %ebx + add %ecx, %edi +#ifdef USE_AS_STPCPY + lea (%edi, %edx), %eax +#endif + sub %edx, %ebx + lea 1(%edi, %edx), %edi + + .p2align 4 +L(StrncpyFillTailWithZero): + pxor %xmm0, %xmm0 + xor %edx, %edx + sub $16, %ebx + jbe L(StrncpyFillExit) + + movdqu %xmm0, (%edi) + add $16, %edi + + mov %edi, %esi + and $0xf, %esi + sub %esi, %edi + add %esi, %ebx + sub $64, %ebx + jb L(StrncpyFillLess64) + +L(StrncpyFillLoopMovdqa): + movdqa %xmm0, (%edi) + movdqa %xmm0, 16(%edi) + movdqa %xmm0, 32(%edi) + movdqa %xmm0, 48(%edi) + add $64, %edi + sub $64, %ebx + jae L(StrncpyFillLoopMovdqa) + +L(StrncpyFillLess64): + add $32, %ebx + jl L(StrncpyFillLess32) + movdqa %xmm0, (%edi) + movdqa %xmm0, 16(%edi) + add $32, %edi + sub $16, %ebx + jl L(StrncpyFillExit) + movdqa %xmm0, (%edi) + add $16, %edi + BRANCH_TO_JMPTBL_ENTRY (L(FillTable), %ebx, 4) + +L(StrncpyFillLess32): + add $16, %ebx + jl L(StrncpyFillExit) + movdqa %xmm0, (%edi) + add $16, %edi + BRANCH_TO_JMPTBL_ENTRY (L(FillTable), %ebx, 4) + +L(StrncpyFillExit): + add $16, %ebx + BRANCH_TO_JMPTBL_ENTRY (L(FillTable), %ebx, 4) + + .p2align 4 +L(AlignedLeaveCase2OrCase3): + test %edx, %edx + jnz L(Aligned64LeaveCase2) +L(Aligned64LeaveCase3): + lea 64(%ebx), %ecx + and $-16, %ecx + add $48, %ebx + jl L(CopyFrom1To16BytesCase3) + movdqa %xmm4, (%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqa %xmm5, 16(%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqa %xmm6, 32(%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqa %xmm7, 48(%edi) +#ifdef USE_AS_STPCPY + lea 64(%edi), %eax +#endif + RETURN + + .p2align 4 +L(Aligned64LeaveCase2): + pxor %xmm0, %xmm0 + xor %ecx, %ecx + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %edx + add $48, %ebx + jle L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm4) + + pcmpeqb %xmm5, %xmm0 + pmovmskb %xmm0, %edx + movdqa %xmm4, (%edi) + add $16, %ecx + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm5) + + pcmpeqb %xmm6, %xmm0 + pmovmskb %xmm0, %edx + movdqa %xmm5, 16(%edi) + add $16, %ecx + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesXmm6) + + pcmpeqb %xmm7, %xmm0 + pmovmskb %xmm0, %edx + movdqa %xmm6, 32(%edi) + lea 16(%edi, %ecx), %edi + lea 16(%esi, %ecx), %esi + bsf %edx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(UnalignedLeaveCase2OrCase3): + test %edx, %edx + jnz L(Unaligned64LeaveCase2) +L(Unaligned64LeaveCase3): + lea 64(%ebx), %ecx + and $-16, %ecx + add $48, %ebx + jl L(CopyFrom1To16BytesCase3) + movdqu %xmm4, (%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqu %xmm5, 16(%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqu %xmm6, 32(%edi) + sub $16, %ebx + jb L(CopyFrom1To16BytesCase3) + movdqu %xmm7, 48(%edi) +#ifdef USE_AS_STPCPY + lea 64(%edi), %eax +#endif + RETURN + + .p2align 4 +L(Unaligned64LeaveCase2): + pxor %xmm0, %xmm0 + xor %ecx, %ecx + pcmpeqb %xmm4, %xmm0 + pmovmskb %xmm0, %edx + add $48, %ebx + jle L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm4) + + pcmpeqb %xmm5, %xmm0 + pmovmskb %xmm0, %edx + movdqu %xmm4, (%edi) + add $16, %ecx + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm5) + + pcmpeqb %xmm6, %xmm0 + pmovmskb %xmm0, %edx + movdqu %xmm5, 16(%edi) + add $16, %ecx + sub $16, %ebx + jbe L(CopyFrom1To16BytesCase2OrCase3) + test %edx, %edx + jnz L(CopyFrom1To16BytesUnalignedXmm6) + + pcmpeqb %xmm7, %xmm0 + pmovmskb %xmm0, %edx + movdqu %xmm6, 32(%edi) + lea 16(%edi, %ecx), %edi + lea 16(%esi, %ecx), %esi + bsf %edx, %edx + cmp %ebx, %edx + jb L(CopyFrom1To16BytesExit) + BRANCH_TO_JMPTBL_ENTRY (L(ExitStrncpyTable), %ebx, 4) + + .p2align 4 +L(ExitZero): + movl %edi, %eax + RETURN +#endif + +END (STRCPY) + + .p2align 4 + .section .rodata +L(ExitTable): + .int JMPTBL(L(Exit1), L(ExitTable)) + .int JMPTBL(L(Exit2), L(ExitTable)) + .int JMPTBL(L(Exit3), L(ExitTable)) + .int JMPTBL(L(Exit4), L(ExitTable)) + .int JMPTBL(L(Exit5), L(ExitTable)) + .int JMPTBL(L(Exit6), L(ExitTable)) + .int JMPTBL(L(Exit7), L(ExitTable)) + .int JMPTBL(L(Exit8), L(ExitTable)) + .int JMPTBL(L(Exit9), L(ExitTable)) + .int JMPTBL(L(Exit10), L(ExitTable)) + .int JMPTBL(L(Exit11), L(ExitTable)) + .int JMPTBL(L(Exit12), L(ExitTable)) + .int JMPTBL(L(Exit13), L(ExitTable)) + .int JMPTBL(L(Exit14), L(ExitTable)) + .int JMPTBL(L(Exit15), L(ExitTable)) + .int JMPTBL(L(Exit16), L(ExitTable)) + .int JMPTBL(L(Exit17), L(ExitTable)) + .int JMPTBL(L(Exit18), L(ExitTable)) + .int JMPTBL(L(Exit19), L(ExitTable)) + .int JMPTBL(L(Exit20), L(ExitTable)) + .int JMPTBL(L(Exit21), L(ExitTable)) + .int JMPTBL(L(Exit22), L(ExitTable)) + .int JMPTBL(L(Exit23), L(ExitTable)) + .int JMPTBL(L(Exit24), L(ExitTable)) + .int JMPTBL(L(Exit25), L(ExitTable)) + .int JMPTBL(L(Exit26), L(ExitTable)) + .int JMPTBL(L(Exit27), L(ExitTable)) + .int JMPTBL(L(Exit28), L(ExitTable)) + .int JMPTBL(L(Exit29), L(ExitTable)) + .int JMPTBL(L(Exit30), L(ExitTable)) + .int JMPTBL(L(Exit31), L(ExitTable)) + .int JMPTBL(L(Exit32), L(ExitTable)) +#ifdef USE_AS_STRNCPY +L(ExitStrncpyTable): + .int JMPTBL(L(Exit0), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit1), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit2), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit3), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit4), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit5), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit6), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit7), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit8), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit9), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit10), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit11), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit12), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit13), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit14), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit15), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit16), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit17), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit18), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit19), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit20), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit21), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit22), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit23), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit24), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit25), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit26), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit27), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit28), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit29), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit30), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit31), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit32), L(ExitStrncpyTable)) + .int JMPTBL(L(StrncpyExit33), L(ExitStrncpyTable)) + + .p2align 4 +L(FillTable): + .int JMPTBL(L(Fill0), L(FillTable)) + .int JMPTBL(L(Fill1), L(FillTable)) + .int JMPTBL(L(Fill2), L(FillTable)) + .int JMPTBL(L(Fill3), L(FillTable)) + .int JMPTBL(L(Fill4), L(FillTable)) + .int JMPTBL(L(Fill5), L(FillTable)) + .int JMPTBL(L(Fill6), L(FillTable)) + .int JMPTBL(L(Fill7), L(FillTable)) + .int JMPTBL(L(Fill8), L(FillTable)) + .int JMPTBL(L(Fill9), L(FillTable)) + .int JMPTBL(L(Fill10), L(FillTable)) + .int JMPTBL(L(Fill11), L(FillTable)) + .int JMPTBL(L(Fill12), L(FillTable)) + .int JMPTBL(L(Fill13), L(FillTable)) + .int JMPTBL(L(Fill14), L(FillTable)) + .int JMPTBL(L(Fill15), L(FillTable)) + .int JMPTBL(L(Fill16), L(FillTable)) +#endif
diff --git a/libc/arch-x86/silvermont/string/sse2-strlen-slm.S b/libc/arch-x86/silvermont/string/sse2-strlen-slm.S new file mode 100755 index 0000000..27cc025 --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-strlen-slm.S
@@ -0,0 +1,328 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef STRLEN +# define STRLEN strlen +#endif + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + + .section .text.sse2,"ax",@progbits +ENTRY (STRLEN) + mov 4(%esp), %edx + mov %edx, %ecx + and $0x3f, %ecx + pxor %xmm0, %xmm0 + cmp $0x30, %ecx + ja L(next) + movdqu (%edx), %xmm1 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit_less16) + mov %edx, %eax + and $-16, %eax + jmp L(align16_start) +L(next): + mov %edx, %eax + and $-16, %eax + PUSH (%edi) + pcmpeqb (%eax), %xmm0 + mov $-1, %edi + sub %eax, %ecx + shl %cl, %edi + pmovmskb %xmm0, %ecx + and %edi, %ecx + POP (%edi) + jnz L(exit_unaligned) + pxor %xmm0, %xmm0 +L(align16_start): + pxor %xmm1, %xmm1 + pxor %xmm2, %xmm2 + pxor %xmm3, %xmm3 + pcmpeqb 16(%eax), %xmm0 + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit16) + + pcmpeqb 32(%eax), %xmm1 + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit32) + + pcmpeqb 48(%eax), %xmm2 + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit48) + + pcmpeqb 64(%eax), %xmm3 + pmovmskb %xmm3, %ecx + test %ecx, %ecx + jnz L(exit64) + + pcmpeqb 80(%eax), %xmm0 + add $64, %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit16) + + pcmpeqb 32(%eax), %xmm1 + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit32) + + pcmpeqb 48(%eax), %xmm2 + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit48) + + pcmpeqb 64(%eax), %xmm3 + pmovmskb %xmm3, %ecx + test %ecx, %ecx + jnz L(exit64) + + pcmpeqb 80(%eax), %xmm0 + add $64, %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit16) + + pcmpeqb 32(%eax), %xmm1 + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit32) + + pcmpeqb 48(%eax), %xmm2 + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit48) + + pcmpeqb 64(%eax), %xmm3 + pmovmskb %xmm3, %ecx + test %ecx, %ecx + jnz L(exit64) + + pcmpeqb 80(%eax), %xmm0 + add $64, %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit16) + + pcmpeqb 32(%eax), %xmm1 + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit32) + + pcmpeqb 48(%eax), %xmm2 + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit48) + + pcmpeqb 64(%eax), %xmm3 + pmovmskb %xmm3, %ecx + test %ecx, %ecx + jnz L(exit64) + + + test $0x3f, %eax + jz L(align64_loop) + + pcmpeqb 80(%eax), %xmm0 + add $80, %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit) + + test $0x3f, %eax + jz L(align64_loop) + + pcmpeqb 16(%eax), %xmm1 + add $16, %eax + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit) + + test $0x3f, %eax + jz L(align64_loop) + + pcmpeqb 16(%eax), %xmm2 + add $16, %eax + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit) + + test $0x3f, %eax + jz L(align64_loop) + + pcmpeqb 16(%eax), %xmm3 + add $16, %eax + pmovmskb %xmm3, %ecx + test %ecx, %ecx + jnz L(exit) + + add $16, %eax + .p2align 4 +L(align64_loop): + movaps (%eax), %xmm4 + pminub 16(%eax), %xmm4 + movaps 32(%eax), %xmm5 + pminub 48(%eax), %xmm5 + add $64, %eax + pminub %xmm4, %xmm5 + pcmpeqb %xmm0, %xmm5 + pmovmskb %xmm5, %ecx + test %ecx, %ecx + jz L(align64_loop) + + + pcmpeqb -64(%eax), %xmm0 + sub $80, %eax + pmovmskb %xmm0, %ecx + test %ecx, %ecx + jnz L(exit16) + + pcmpeqb 32(%eax), %xmm1 + pmovmskb %xmm1, %ecx + test %ecx, %ecx + jnz L(exit32) + + pcmpeqb 48(%eax), %xmm2 + pmovmskb %xmm2, %ecx + test %ecx, %ecx + jnz L(exit48) + + pcmpeqb 64(%eax), %xmm3 + pmovmskb %xmm3, %ecx + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + add $64, %eax + ret + + .p2align 4 +L(exit): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + ret + +L(exit_less16): + bsf %ecx, %eax + ret + + .p2align 4 +L(exit_unaligned): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + ret + + .p2align 4 +L(exit16): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + add $16, %eax + ret + + .p2align 4 +L(exit32): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + add $32, %eax + ret + + .p2align 4 +L(exit48): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + add $48, %eax + ret + + .p2align 4 +L(exit64): + sub %edx, %eax + bsf %ecx, %ecx + add %ecx, %eax + add $64, %eax + ret + +END (STRLEN) +
diff --git a/libc/arch-x86/silvermont/string/sse2-strncpy-slm.S b/libc/arch-x86/silvermont/string/sse2-strncpy-slm.S new file mode 100755 index 0000000..591419f --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse2-strncpy-slm.S
@@ -0,0 +1,33 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_STRNCPY +#define STRCPY strncpy +#include "sse2-strcpy-slm.S"
diff --git a/libc/arch-x86/silvermont/string/sse4-memcmp-slm.S b/libc/arch-x86/silvermont/string/sse4-memcmp-slm.S new file mode 100755 index 0000000..e5028ff --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse4-memcmp-slm.S
@@ -0,0 +1,1278 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef L +# define L(label) .L##label +#endif + +#ifndef cfi_startproc +# define cfi_startproc .cfi_startproc +#endif + +#ifndef cfi_endproc +# define cfi_endproc .cfi_endproc +#endif + +#ifndef cfi_rel_offset +# define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off +#endif + +#ifndef cfi_restore +# define cfi_restore(reg) .cfi_restore reg +#endif + +#ifndef cfi_adjust_cfa_offset +# define cfi_adjust_cfa_offset(off) .cfi_adjust_cfa_offset off +#endif + +#ifndef cfi_remember_state +# define cfi_remember_state .cfi_remember_state +#endif + +#ifndef cfi_restore_state +# define cfi_restore_state .cfi_restore_state +#endif + +#ifndef ENTRY +# define ENTRY(name) \ + .type name, @function; \ + .globl name; \ + .p2align 4; \ +name: \ + cfi_startproc +#endif + +#ifndef END +# define END(name) \ + cfi_endproc; \ + .size name, .-name +#endif + +#ifndef MEMCMP +# define MEMCMP memcmp +#endif + +#define CFI_PUSH(REG) \ + cfi_adjust_cfa_offset (4); \ + cfi_rel_offset (REG, 0) + +#define CFI_POP(REG) \ + cfi_adjust_cfa_offset (-4); \ + cfi_restore (REG) + +#define PUSH(REG) pushl REG; CFI_PUSH (REG) +#define POP(REG) popl REG; CFI_POP (REG) + +#define PARMS 4 +#define BLK1 PARMS +#define BLK2 BLK1 + 4 +#define LEN BLK2 + 4 +#define RETURN POP (%ebx); ret; CFI_PUSH (%ebx) + + +#if (defined SHARED || defined __PIC__) +# define JMPTBL(I, B) I - B + +/* Load an entry in a jump table into EBX and branch to it. TABLE is a + jump table with relative offsets. INDEX is a register contains the + index into the jump table. SCALE is the scale of INDEX. */ + +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ +/* We first load PC into EBX. */ \ + call __x86.get_pc_thunk.bx; \ +/* Get the address of the jump table. */ \ + addl $(TABLE - .), %ebx; \ +/* Get the entry and convert the relative offset to the \ + absolute address. */ \ + addl (%ebx,INDEX,SCALE), %ebx; \ +/* We loaded the jump table and adjuested EDX/ESI. Go. */ \ + jmp *%ebx +#else +# define JMPTBL(I, B) I + +/* Load an entry in a jump table into EBX and branch to it. TABLE is a + jump table with relative offsets. INDEX is a register contains the + index into the jump table. SCALE is the scale of INDEX. */ +# define BRANCH_TO_JMPTBL_ENTRY(TABLE, INDEX, SCALE) \ + jmp *TABLE(,INDEX,SCALE) +#endif + + +/* Warning! + wmemcmp has to use SIGNED comparison for elements. + memcmp has to use UNSIGNED comparison for elemnts. +*/ + + .section .text.sse4.2,"ax",@progbits +ENTRY (MEMCMP) + movl BLK1(%esp), %eax + movl BLK2(%esp), %edx + movl LEN(%esp), %ecx + +#ifdef USE_AS_WMEMCMP + shl $2, %ecx + test %ecx, %ecx + jz L(return0) +#else + cmp $1, %ecx + jbe L(less1bytes) +#endif + + pxor %xmm0, %xmm0 + cmp $64, %ecx + ja L(64bytesormore) + cmp $8, %ecx + +#ifndef USE_AS_WMEMCMP + PUSH (%ebx) + jb L(less8bytes) +#else + jb L(less8bytes) + PUSH (%ebx) +#endif + + add %ecx, %edx + add %ecx, %eax + BRANCH_TO_JMPTBL_ENTRY(L(table_64bytes), %ecx, 4) + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(less8bytes): + mov (%eax), %bl + cmpb (%edx), %bl + jne L(nonzero) + + mov 1(%eax), %bl + cmpb 1(%edx), %bl + jne L(nonzero) + + cmp $2, %ecx + jz L(0bytes) + + mov 2(%eax), %bl + cmpb 2(%edx), %bl + jne L(nonzero) + + cmp $3, %ecx + jz L(0bytes) + + mov 3(%eax), %bl + cmpb 3(%edx), %bl + jne L(nonzero) + + cmp $4, %ecx + jz L(0bytes) + + mov 4(%eax), %bl + cmpb 4(%edx), %bl + jne L(nonzero) + + cmp $5, %ecx + jz L(0bytes) + + mov 5(%eax), %bl + cmpb 5(%edx), %bl + jne L(nonzero) + + cmp $6, %ecx + jz L(0bytes) + + mov 6(%eax), %bl + cmpb 6(%edx), %bl + je L(0bytes) + +L(nonzero): + POP (%ebx) + mov $1, %eax + ja L(above) + neg %eax +L(above): + ret + CFI_PUSH (%ebx) +#endif + + .p2align 4 +L(0bytes): + POP (%ebx) + xor %eax, %eax + ret + +#ifdef USE_AS_WMEMCMP + +/* for wmemcmp, case N == 1 */ + + .p2align 4 +L(less8bytes): + mov (%eax), %ecx + cmp (%edx), %ecx + je L(return0) + mov $1, %eax + jg L(find_diff_bigger) + neg %eax + ret + + .p2align 4 +L(find_diff_bigger): + ret + + .p2align 4 +L(return0): + xor %eax, %eax + ret +#endif + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(less1bytes): + jb L(0bytesend) + movzbl (%eax), %eax + movzbl (%edx), %edx + sub %edx, %eax + ret + + .p2align 4 +L(0bytesend): + xor %eax, %eax + ret +#endif + .p2align 4 +L(64bytesormore): + PUSH (%ebx) + mov %ecx, %ebx + mov $64, %ecx + sub $64, %ebx +L(64bytesormore_loop): + movdqu (%eax), %xmm1 + movdqu (%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(find_16diff) + + movdqu 16(%eax), %xmm1 + movdqu 16(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(find_32diff) + + movdqu 32(%eax), %xmm1 + movdqu 32(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(find_48diff) + + movdqu 48(%eax), %xmm1 + movdqu 48(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(find_64diff) + add %ecx, %eax + add %ecx, %edx + sub %ecx, %ebx + jae L(64bytesormore_loop) + add %ebx, %ecx + add %ecx, %edx + add %ecx, %eax + BRANCH_TO_JMPTBL_ENTRY(L(table_64bytes), %ecx, 4) + +#ifdef USE_AS_WMEMCMP + +/* Label needs only for table_64bytes filling */ +L(unreal_case): +/* no code here */ + +#endif + .p2align 4 +L(find_16diff): + sub $16, %ecx +L(find_32diff): + sub $16, %ecx +L(find_48diff): + sub $16, %ecx +L(find_64diff): + add %ecx, %edx + add %ecx, %eax + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(16bytes): + mov -16(%eax), %ecx + mov -16(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(12bytes): + mov -12(%eax), %ecx + mov -12(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(8bytes): + mov -8(%eax), %ecx + mov -8(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(4bytes): + mov -4(%eax), %ecx + mov -4(%edx), %ebx + cmp %ebx, %ecx + mov $0, %eax + jne L(find_diff) + RETURN +#else + .p2align 4 +L(16bytes): + mov -16(%eax), %ecx + cmp -16(%edx), %ecx + jne L(find_diff) +L(12bytes): + mov -12(%eax), %ecx + cmp -12(%edx), %ecx + jne L(find_diff) +L(8bytes): + mov -8(%eax), %ecx + cmp -8(%edx), %ecx + jne L(find_diff) +L(4bytes): + mov -4(%eax), %ecx + cmp -4(%edx), %ecx + mov $0, %eax + jne L(find_diff) + RETURN +#endif + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(49bytes): + movdqu -49(%eax), %xmm1 + movdqu -49(%edx), %xmm2 + mov $-49, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(33bytes): + movdqu -33(%eax), %xmm1 + movdqu -33(%edx), %xmm2 + mov $-33, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(17bytes): + mov -17(%eax), %ecx + mov -17(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(13bytes): + mov -13(%eax), %ecx + mov -13(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(9bytes): + mov -9(%eax), %ecx + mov -9(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(5bytes): + mov -5(%eax), %ecx + mov -5(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzbl -1(%eax), %ecx + cmp -1(%edx), %cl + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(50bytes): + mov $-50, %ebx + movdqu -50(%eax), %xmm1 + movdqu -50(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(34bytes): + mov $-34, %ebx + movdqu -34(%eax), %xmm1 + movdqu -34(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(18bytes): + mov -18(%eax), %ecx + mov -18(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(14bytes): + mov -14(%eax), %ecx + mov -14(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(10bytes): + mov -10(%eax), %ecx + mov -10(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(6bytes): + mov -6(%eax), %ecx + mov -6(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(2bytes): + movzwl -2(%eax), %ecx + movzwl -2(%edx), %ebx + cmp %bl, %cl + jne L(end) + cmp %bh, %ch + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(51bytes): + mov $-51, %ebx + movdqu -51(%eax), %xmm1 + movdqu -51(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(35bytes): + mov $-35, %ebx + movdqu -35(%eax), %xmm1 + movdqu -35(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(19bytes): + movl -19(%eax), %ecx + movl -19(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(15bytes): + movl -15(%eax), %ecx + movl -15(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(11bytes): + movl -11(%eax), %ecx + movl -11(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(7bytes): + movl -7(%eax), %ecx + movl -7(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) +L(3bytes): + movzwl -3(%eax), %ecx + movzwl -3(%edx), %ebx + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) +L(1bytes): + movzbl -1(%eax), %eax + cmpb -1(%edx), %al + mov $0, %eax + jne L(end) + RETURN +#endif + .p2align 4 +L(52bytes): + movdqu -52(%eax), %xmm1 + movdqu -52(%edx), %xmm2 + mov $-52, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(36bytes): + movdqu -36(%eax), %xmm1 + movdqu -36(%edx), %xmm2 + mov $-36, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(20bytes): + movdqu -20(%eax), %xmm1 + movdqu -20(%edx), %xmm2 + mov $-20, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + mov -4(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -4(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -4(%edx), %ecx +#endif + mov $0, %eax + jne L(find_diff) + RETURN + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(53bytes): + movdqu -53(%eax), %xmm1 + movdqu -53(%edx), %xmm2 + mov $-53, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(37bytes): + mov $-37, %ebx + movdqu -37(%eax), %xmm1 + movdqu -37(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(21bytes): + mov $-21, %ebx + movdqu -21(%eax), %xmm1 + movdqu -21(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + mov -5(%eax), %ecx + mov -5(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzbl -1(%eax), %ecx + cmp -1(%edx), %cl + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(54bytes): + movdqu -54(%eax), %xmm1 + movdqu -54(%edx), %xmm2 + mov $-54, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(38bytes): + mov $-38, %ebx + movdqu -38(%eax), %xmm1 + movdqu -38(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(22bytes): + mov $-22, %ebx + movdqu -22(%eax), %xmm1 + movdqu -22(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -6(%eax), %ecx + mov -6(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzwl -2(%eax), %ecx + movzwl -2(%edx), %ebx + cmp %bl, %cl + jne L(end) + cmp %bh, %ch + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(55bytes): + movdqu -55(%eax), %xmm1 + movdqu -55(%edx), %xmm2 + mov $-55, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(39bytes): + mov $-39, %ebx + movdqu -39(%eax), %xmm1 + movdqu -39(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(23bytes): + mov $-23, %ebx + movdqu -23(%eax), %xmm1 + movdqu -23(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + movl -7(%eax), %ecx + movl -7(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzwl -3(%eax), %ecx + movzwl -3(%edx), %ebx + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + movzbl -1(%eax), %eax + cmpb -1(%edx), %al + mov $0, %eax + jne L(end) + RETURN +#endif + .p2align 4 +L(56bytes): + movdqu -56(%eax), %xmm1 + movdqu -56(%edx), %xmm2 + mov $-56, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(40bytes): + mov $-40, %ebx + movdqu -40(%eax), %xmm1 + movdqu -40(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(24bytes): + mov $-24, %ebx + movdqu -24(%eax), %xmm1 + movdqu -24(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -8(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -8(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -8(%edx), %ecx +#endif + jne L(find_diff) + + mov -4(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -4(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -4(%edx), %ecx +#endif + mov $0, %eax + jne L(find_diff) + RETURN + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(57bytes): + movdqu -57(%eax), %xmm1 + movdqu -57(%edx), %xmm2 + mov $-57, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(41bytes): + mov $-41, %ebx + movdqu -41(%eax), %xmm1 + movdqu -41(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(25bytes): + mov $-25, %ebx + movdqu -25(%eax), %xmm1 + movdqu -25(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + mov -9(%eax), %ecx + mov -9(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + mov -5(%eax), %ecx + mov -5(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzbl -1(%eax), %ecx + cmp -1(%edx), %cl + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(58bytes): + movdqu -58(%eax), %xmm1 + movdqu -58(%edx), %xmm2 + mov $-58, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(42bytes): + mov $-42, %ebx + movdqu -42(%eax), %xmm1 + movdqu -42(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(26bytes): + mov $-26, %ebx + movdqu -26(%eax), %xmm1 + movdqu -26(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -10(%eax), %ecx + mov -10(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov -6(%eax), %ecx + mov -6(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + movzwl -2(%eax), %ecx + movzwl -2(%edx), %ebx + cmp %bl, %cl + jne L(end) + cmp %bh, %ch + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(59bytes): + movdqu -59(%eax), %xmm1 + movdqu -59(%edx), %xmm2 + mov $-59, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(43bytes): + mov $-43, %ebx + movdqu -43(%eax), %xmm1 + movdqu -43(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(27bytes): + mov $-27, %ebx + movdqu -27(%eax), %xmm1 + movdqu -27(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + movl -11(%eax), %ecx + movl -11(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movl -7(%eax), %ecx + movl -7(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzwl -3(%eax), %ecx + movzwl -3(%edx), %ebx + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + movzbl -1(%eax), %eax + cmpb -1(%edx), %al + mov $0, %eax + jne L(end) + RETURN +#endif + .p2align 4 +L(60bytes): + movdqu -60(%eax), %xmm1 + movdqu -60(%edx), %xmm2 + mov $-60, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(44bytes): + mov $-44, %ebx + movdqu -44(%eax), %xmm1 + movdqu -44(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(28bytes): + mov $-28, %ebx + movdqu -28(%eax), %xmm1 + movdqu -28(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -12(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -12(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -12(%edx), %ecx +#endif + jne L(find_diff) + + mov -8(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -8(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -8(%edx), %ecx +#endif + jne L(find_diff) + + mov -4(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -4(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -4(%edx), %ecx +#endif + mov $0, %eax + jne L(find_diff) + RETURN + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(61bytes): + movdqu -61(%eax), %xmm1 + movdqu -61(%edx), %xmm2 + mov $-61, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(45bytes): + mov $-45, %ebx + movdqu -45(%eax), %xmm1 + movdqu -45(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(29bytes): + mov $-29, %ebx + movdqu -29(%eax), %xmm1 + movdqu -29(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -13(%eax), %ecx + mov -13(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov -9(%eax), %ecx + mov -9(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov -5(%eax), %ecx + mov -5(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzbl -1(%eax), %ecx + cmp -1(%edx), %cl + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(62bytes): + movdqu -62(%eax), %xmm1 + movdqu -62(%edx), %xmm2 + mov $-62, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(46bytes): + mov $-46, %ebx + movdqu -46(%eax), %xmm1 + movdqu -46(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(30bytes): + mov $-30, %ebx + movdqu -30(%eax), %xmm1 + movdqu -30(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + mov -14(%eax), %ecx + mov -14(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + mov -10(%eax), %ecx + mov -10(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + mov -6(%eax), %ecx + mov -6(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzwl -2(%eax), %ecx + movzwl -2(%edx), %ebx + cmp %bl, %cl + jne L(end) + cmp %bh, %ch + mov $0, %eax + jne L(end) + RETURN + + .p2align 4 +L(63bytes): + movdqu -63(%eax), %xmm1 + movdqu -63(%edx), %xmm2 + mov $-63, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(47bytes): + mov $-47, %ebx + movdqu -47(%eax), %xmm1 + movdqu -47(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(31bytes): + mov $-31, %ebx + movdqu -31(%eax), %xmm1 + movdqu -31(%edx), %xmm2 + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + movl -15(%eax), %ecx + movl -15(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movl -11(%eax), %ecx + movl -11(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movl -7(%eax), %ecx + movl -7(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + movzwl -3(%eax), %ecx + movzwl -3(%edx), %ebx + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + movzbl -1(%eax), %eax + cmpb -1(%edx), %al + mov $0, %eax + jne L(end) + RETURN +#endif + + .p2align 4 +L(64bytes): + movdqu -64(%eax), %xmm1 + movdqu -64(%edx), %xmm2 + mov $-64, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(48bytes): + movdqu -48(%eax), %xmm1 + movdqu -48(%edx), %xmm2 + mov $-48, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) +L(32bytes): + movdqu -32(%eax), %xmm1 + movdqu -32(%edx), %xmm2 + mov $-32, %ebx + pxor %xmm1, %xmm2 + ptest %xmm2, %xmm0 + jnc L(less16bytes) + + mov -16(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -16(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -16(%edx), %ecx +#endif + jne L(find_diff) + + mov -12(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -12(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -12(%edx), %ecx +#endif + jne L(find_diff) + + mov -8(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -8(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -8(%edx), %ecx +#endif + jne L(find_diff) + + mov -4(%eax), %ecx +#ifndef USE_AS_WMEMCMP + mov -4(%edx), %ebx + cmp %ebx, %ecx +#else + cmp -4(%edx), %ecx +#endif + mov $0, %eax + jne L(find_diff) + RETURN + +#ifndef USE_AS_WMEMCMP + .p2align 4 +L(less16bytes): + add %ebx, %eax + add %ebx, %edx + + mov (%eax), %ecx + mov (%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov 4(%eax), %ecx + mov 4(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov 8(%eax), %ecx + mov 8(%edx), %ebx + cmp %ebx, %ecx + jne L(find_diff) + + mov 12(%eax), %ecx + mov 12(%edx), %ebx + cmp %ebx, %ecx + mov $0, %eax + jne L(find_diff) + RETURN +#else + .p2align 4 +L(less16bytes): + add %ebx, %eax + add %ebx, %edx + + mov (%eax), %ecx + cmp (%edx), %ecx + jne L(find_diff) + + mov 4(%eax), %ecx + cmp 4(%edx), %ecx + jne L(find_diff) + + mov 8(%eax), %ecx + cmp 8(%edx), %ecx + jne L(find_diff) + + mov 12(%eax), %ecx + cmp 12(%edx), %ecx + + mov $0, %eax + jne L(find_diff) + RETURN +#endif + + .p2align 4 +L(find_diff): +#ifndef USE_AS_WMEMCMP + cmpb %bl, %cl + jne L(end) + cmp %bx, %cx + jne L(end) + shr $16,%ecx + shr $16,%ebx + cmp %bl, %cl + jne L(end) + cmp %bx, %cx +L(end): + POP (%ebx) + mov $1, %eax + ja L(bigger) + neg %eax +L(bigger): + ret +#else + POP (%ebx) + mov $1, %eax + jg L(bigger) + neg %eax + ret + + .p2align 4 +L(bigger): + ret +#endif +END (MEMCMP) + + .section .rodata.sse4.2,"a",@progbits + .p2align 2 + .type L(table_64bytes), @object +#ifndef USE_AS_WMEMCMP +L(table_64bytes): + .int JMPTBL (L(0bytes), L(table_64bytes)) + .int JMPTBL (L(1bytes), L(table_64bytes)) + .int JMPTBL (L(2bytes), L(table_64bytes)) + .int JMPTBL (L(3bytes), L(table_64bytes)) + .int JMPTBL (L(4bytes), L(table_64bytes)) + .int JMPTBL (L(5bytes), L(table_64bytes)) + .int JMPTBL (L(6bytes), L(table_64bytes)) + .int JMPTBL (L(7bytes), L(table_64bytes)) + .int JMPTBL (L(8bytes), L(table_64bytes)) + .int JMPTBL (L(9bytes), L(table_64bytes)) + .int JMPTBL (L(10bytes), L(table_64bytes)) + .int JMPTBL (L(11bytes), L(table_64bytes)) + .int JMPTBL (L(12bytes), L(table_64bytes)) + .int JMPTBL (L(13bytes), L(table_64bytes)) + .int JMPTBL (L(14bytes), L(table_64bytes)) + .int JMPTBL (L(15bytes), L(table_64bytes)) + .int JMPTBL (L(16bytes), L(table_64bytes)) + .int JMPTBL (L(17bytes), L(table_64bytes)) + .int JMPTBL (L(18bytes), L(table_64bytes)) + .int JMPTBL (L(19bytes), L(table_64bytes)) + .int JMPTBL (L(20bytes), L(table_64bytes)) + .int JMPTBL (L(21bytes), L(table_64bytes)) + .int JMPTBL (L(22bytes), L(table_64bytes)) + .int JMPTBL (L(23bytes), L(table_64bytes)) + .int JMPTBL (L(24bytes), L(table_64bytes)) + .int JMPTBL (L(25bytes), L(table_64bytes)) + .int JMPTBL (L(26bytes), L(table_64bytes)) + .int JMPTBL (L(27bytes), L(table_64bytes)) + .int JMPTBL (L(28bytes), L(table_64bytes)) + .int JMPTBL (L(29bytes), L(table_64bytes)) + .int JMPTBL (L(30bytes), L(table_64bytes)) + .int JMPTBL (L(31bytes), L(table_64bytes)) + .int JMPTBL (L(32bytes), L(table_64bytes)) + .int JMPTBL (L(33bytes), L(table_64bytes)) + .int JMPTBL (L(34bytes), L(table_64bytes)) + .int JMPTBL (L(35bytes), L(table_64bytes)) + .int JMPTBL (L(36bytes), L(table_64bytes)) + .int JMPTBL (L(37bytes), L(table_64bytes)) + .int JMPTBL (L(38bytes), L(table_64bytes)) + .int JMPTBL (L(39bytes), L(table_64bytes)) + .int JMPTBL (L(40bytes), L(table_64bytes)) + .int JMPTBL (L(41bytes), L(table_64bytes)) + .int JMPTBL (L(42bytes), L(table_64bytes)) + .int JMPTBL (L(43bytes), L(table_64bytes)) + .int JMPTBL (L(44bytes), L(table_64bytes)) + .int JMPTBL (L(45bytes), L(table_64bytes)) + .int JMPTBL (L(46bytes), L(table_64bytes)) + .int JMPTBL (L(47bytes), L(table_64bytes)) + .int JMPTBL (L(48bytes), L(table_64bytes)) + .int JMPTBL (L(49bytes), L(table_64bytes)) + .int JMPTBL (L(50bytes), L(table_64bytes)) + .int JMPTBL (L(51bytes), L(table_64bytes)) + .int JMPTBL (L(52bytes), L(table_64bytes)) + .int JMPTBL (L(53bytes), L(table_64bytes)) + .int JMPTBL (L(54bytes), L(table_64bytes)) + .int JMPTBL (L(55bytes), L(table_64bytes)) + .int JMPTBL (L(56bytes), L(table_64bytes)) + .int JMPTBL (L(57bytes), L(table_64bytes)) + .int JMPTBL (L(58bytes), L(table_64bytes)) + .int JMPTBL (L(59bytes), L(table_64bytes)) + .int JMPTBL (L(60bytes), L(table_64bytes)) + .int JMPTBL (L(61bytes), L(table_64bytes)) + .int JMPTBL (L(62bytes), L(table_64bytes)) + .int JMPTBL (L(63bytes), L(table_64bytes)) + .int JMPTBL (L(64bytes), L(table_64bytes)) +#else +L(table_64bytes): + .int JMPTBL (L(0bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(4bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(8bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(12bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(16bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(20bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(24bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(28bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(32bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(36bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(40bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(44bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(48bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(52bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(56bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(60bytes), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(unreal_case), L(table_64bytes)) + .int JMPTBL (L(64bytes), L(table_64bytes)) +#endif
diff --git a/libc/arch-x86/silvermont/string/sse4-wmemcmp-slm.S b/libc/arch-x86/silvermont/string/sse4-wmemcmp-slm.S new file mode 100755 index 0000000..2c350bb --- /dev/null +++ b/libc/arch-x86/silvermont/string/sse4-wmemcmp-slm.S
@@ -0,0 +1,33 @@ +/* +Copyright (c) 2014, Intel Corporation +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + + * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#define USE_AS_WMEMCMP +#define MEMCMP wmemcmp +#include "sse4-memcmp-slm.S"
diff --git a/libc/arch-x86/syscalls/___clock_nanosleep.S b/libc/arch-x86/syscalls/___clock_nanosleep.S new file mode 100644 index 0000000..6998749 --- /dev/null +++ b/libc/arch-x86/syscalls/___clock_nanosleep.S
@@ -0,0 +1,45 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___clock_nanosleep) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_clock_nanosleep, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(___clock_nanosleep) +.hidden ___clock_nanosleep
diff --git a/libc/arch-x86/syscalls/___close.S b/libc/arch-x86/syscalls/___close.S new file mode 100644 index 0000000..b9ebdaa --- /dev/null +++ b/libc/arch-x86/syscalls/___close.S
@@ -0,0 +1,30 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___close) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_close, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(___close) +.hidden ___close
diff --git a/libc/arch-x86/syscalls/___faccessat.S b/libc/arch-x86/syscalls/___faccessat.S new file mode 100644 index 0000000..b92b03d --- /dev/null +++ b/libc/arch-x86/syscalls/___faccessat.S
@@ -0,0 +1,40 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___faccessat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_faccessat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(___faccessat) +.hidden ___faccessat
diff --git a/libc/arch-x86/syscalls/___fchmod.S b/libc/arch-x86/syscalls/___fchmod.S new file mode 100644 index 0000000..92e864c --- /dev/null +++ b/libc/arch-x86/syscalls/___fchmod.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmod) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_fchmod, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(___fchmod) +.hidden ___fchmod
diff --git a/libc/arch-x86/syscalls/___fchmodat.S b/libc/arch-x86/syscalls/___fchmodat.S new file mode 100644 index 0000000..81edf96 --- /dev/null +++ b/libc/arch-x86/syscalls/___fchmodat.S
@@ -0,0 +1,40 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fchmodat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_fchmodat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(___fchmodat) +.hidden ___fchmodat
diff --git a/libc/arch-x86/syscalls/___fgetxattr.S b/libc/arch-x86/syscalls/___fgetxattr.S new file mode 100644 index 0000000..712728d --- /dev/null +++ b/libc/arch-x86/syscalls/___fgetxattr.S
@@ -0,0 +1,45 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fgetxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_fgetxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(___fgetxattr) +.hidden ___fgetxattr
diff --git a/libc/arch-x86/syscalls/___flistxattr.S b/libc/arch-x86/syscalls/___flistxattr.S new file mode 100644 index 0000000..a22ef35 --- /dev/null +++ b/libc/arch-x86/syscalls/___flistxattr.S
@@ -0,0 +1,40 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___flistxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_flistxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(___flistxattr) +.hidden ___flistxattr
diff --git a/libc/arch-x86/syscalls/___fsetxattr.S b/libc/arch-x86/syscalls/___fsetxattr.S new file mode 100644 index 0000000..b90c972 --- /dev/null +++ b/libc/arch-x86/syscalls/___fsetxattr.S
@@ -0,0 +1,50 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___fsetxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_fsetxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(___fsetxattr) +.hidden ___fsetxattr
diff --git a/libc/arch-x86/syscalls/___mremap.S b/libc/arch-x86/syscalls/___mremap.S new file mode 100644 index 0000000..9d9bfcb --- /dev/null +++ b/libc/arch-x86/syscalls/___mremap.S
@@ -0,0 +1,50 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___mremap) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_mremap, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(___mremap) +.hidden ___mremap
diff --git a/libc/arch-x86/syscalls/___rt_sigqueueinfo.S b/libc/arch-x86/syscalls/___rt_sigqueueinfo.S new file mode 100644 index 0000000..e299707 --- /dev/null +++ b/libc/arch-x86/syscalls/___rt_sigqueueinfo.S
@@ -0,0 +1,40 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(___rt_sigqueueinfo) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_rt_sigqueueinfo, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(___rt_sigqueueinfo) +.hidden ___rt_sigqueueinfo
diff --git a/libc/arch-x86/syscalls/__accept4.S b/libc/arch-x86/syscalls/__accept4.S new file mode 100644 index 0000000..112a8a7 --- /dev/null +++ b/libc/arch-x86/syscalls/__accept4.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $18, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__accept4)
diff --git a/libc/arch-x86/syscalls/__brk.S b/libc/arch-x86/syscalls/__brk.S new file mode 100644 index 0000000..bf2f1d2 --- /dev/null +++ b/libc/arch-x86/syscalls/__brk.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_brk, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__brk)
diff --git a/libc/arch-x86/syscalls/__clock_gettime.S b/libc/arch-x86/syscalls/__clock_gettime.S new file mode 100644 index 0000000..0c0c1c4 --- /dev/null +++ b/libc/arch-x86/syscalls/__clock_gettime.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__clock_gettime) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_clock_gettime, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__clock_gettime)
diff --git a/libc/arch-x86/syscalls/__connect.S b/libc/arch-x86/syscalls/__connect.S new file mode 100644 index 0000000..5ea160c --- /dev/null +++ b/libc/arch-x86/syscalls/__connect.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $3, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__connect)
diff --git a/libc/arch-x86/syscalls/__epoll_pwait.S b/libc/arch-x86/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..3750760 --- /dev/null +++ b/libc/arch-x86/syscalls/__epoll_pwait.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_epoll_pwait, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__epoll_pwait)
diff --git a/libc/arch-x86/syscalls/__exit.S b/libc/arch-x86/syscalls/__exit.S new file mode 100644 index 0000000..841c8cf --- /dev/null +++ b/libc/arch-x86/syscalls/__exit.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_exit, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__exit)
diff --git a/libc/arch-x86/syscalls/__fadvise64.S b/libc/arch-x86/syscalls/__fadvise64.S new file mode 100644 index 0000000..d580a61 --- /dev/null +++ b/libc/arch-x86/syscalls/__fadvise64.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fadvise64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_fadvise64_64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__fadvise64)
diff --git a/libc/arch-x86/syscalls/__fcntl64.S b/libc/arch-x86/syscalls/__fcntl64.S new file mode 100644 index 0000000..c886411 --- /dev/null +++ b/libc/arch-x86/syscalls/__fcntl64.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fcntl64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_fcntl64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__fcntl64)
diff --git a/libc/arch-x86/syscalls/__fstatfs64.S b/libc/arch-x86/syscalls/__fstatfs64.S new file mode 100644 index 0000000..2c97435 --- /dev/null +++ b/libc/arch-x86/syscalls/__fstatfs64.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fstatfs64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_fstatfs64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__fstatfs64)
diff --git a/libc/arch-x86/syscalls/__getcpu.S b/libc/arch-x86/syscalls/__getcpu.S new file mode 100644 index 0000000..fde7306 --- /dev/null +++ b/libc/arch-x86/syscalls/__getcpu.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_getcpu, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__getcpu)
diff --git a/libc/arch-x86/syscalls/__getcwd.S b/libc/arch-x86/syscalls/__getcwd.S new file mode 100644 index 0000000..dc0bded --- /dev/null +++ b/libc/arch-x86/syscalls/__getcwd.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_getcwd, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__getcwd)
diff --git a/libc/arch-x86/syscalls/__getdents64.S b/libc/arch-x86/syscalls/__getdents64.S new file mode 100644 index 0000000..4228da2 --- /dev/null +++ b/libc/arch-x86/syscalls/__getdents64.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_getdents64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__getdents64)
diff --git a/libc/arch-x86/syscalls/__getpid.S b/libc/arch-x86/syscalls/__getpid.S new file mode 100644 index 0000000..aa5d343 --- /dev/null +++ b/libc/arch-x86/syscalls/__getpid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_getpid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(__getpid)
diff --git a/libc/arch-x86/syscalls/__getpriority.S b/libc/arch-x86/syscalls/__getpriority.S new file mode 100644 index 0000000..cf2fbc3 --- /dev/null +++ b/libc/arch-x86/syscalls/__getpriority.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_getpriority, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__getpriority)
diff --git a/libc/arch-x86/syscalls/__gettimeofday.S b/libc/arch-x86/syscalls/__gettimeofday.S new file mode 100644 index 0000000..4e24cdd --- /dev/null +++ b/libc/arch-x86/syscalls/__gettimeofday.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__gettimeofday) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_gettimeofday, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__gettimeofday)
diff --git a/libc/arch-x86/syscalls/__ioctl.S b/libc/arch-x86/syscalls/__ioctl.S new file mode 100644 index 0000000..2189638 --- /dev/null +++ b/libc/arch-x86/syscalls/__ioctl.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_ioctl, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__ioctl)
diff --git a/libc/arch-x86/syscalls/__llseek.S b/libc/arch-x86/syscalls/__llseek.S new file mode 100644 index 0000000..9213891 --- /dev/null +++ b/libc/arch-x86/syscalls/__llseek.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__llseek) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR__llseek, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__llseek)
diff --git a/libc/arch-x86/syscalls/__mmap2.S b/libc/arch-x86/syscalls/__mmap2.S new file mode 100644 index 0000000..0904a3d --- /dev/null +++ b/libc/arch-x86/syscalls/__mmap2.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__mmap2) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_mmap2, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__mmap2)
diff --git a/libc/arch-x86/syscalls/__openat.S b/libc/arch-x86/syscalls/__openat.S new file mode 100644 index 0000000..03c03bd --- /dev/null +++ b/libc/arch-x86/syscalls/__openat.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_openat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__openat)
diff --git a/libc/arch-x86/syscalls/__ppoll.S b/libc/arch-x86/syscalls/__ppoll.S new file mode 100644 index 0000000..1a55b03 --- /dev/null +++ b/libc/arch-x86/syscalls/__ppoll.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_ppoll, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__ppoll)
diff --git a/libc/arch-x86/syscalls/__preadv64.S b/libc/arch-x86/syscalls/__preadv64.S new file mode 100644 index 0000000..5db22a3 --- /dev/null +++ b/libc/arch-x86/syscalls/__preadv64.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__preadv64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_preadv, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__preadv64)
diff --git a/libc/arch-x86/syscalls/__pselect6.S b/libc/arch-x86/syscalls/__pselect6.S new file mode 100644 index 0000000..18327fd --- /dev/null +++ b/libc/arch-x86/syscalls/__pselect6.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_pselect6, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__pselect6)
diff --git a/libc/arch-x86/syscalls/__ptrace.S b/libc/arch-x86/syscalls/__ptrace.S new file mode 100644 index 0000000..a522e95 --- /dev/null +++ b/libc/arch-x86/syscalls/__ptrace.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_ptrace, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__ptrace)
diff --git a/libc/arch-x86/syscalls/__pwritev64.S b/libc/arch-x86/syscalls/__pwritev64.S new file mode 100644 index 0000000..19f1865 --- /dev/null +++ b/libc/arch-x86/syscalls/__pwritev64.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pwritev64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_pwritev, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__pwritev64)
diff --git a/libc/arch-x86/syscalls/__reboot.S b/libc/arch-x86/syscalls/__reboot.S new file mode 100644 index 0000000..711a4e6 --- /dev/null +++ b/libc/arch-x86/syscalls/__reboot.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_reboot, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__reboot)
diff --git a/libc/arch-x86/syscalls/__rt_sigaction.S b/libc/arch-x86/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..ebc431d --- /dev/null +++ b/libc/arch-x86/syscalls/__rt_sigaction.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_rt_sigaction, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__rt_sigaction)
diff --git a/libc/arch-x86/syscalls/__rt_sigpending.S b/libc/arch-x86/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..ecf2945 --- /dev/null +++ b/libc/arch-x86/syscalls/__rt_sigpending.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_rt_sigpending, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__rt_sigpending)
diff --git a/libc/arch-x86/syscalls/__rt_sigprocmask.S b/libc/arch-x86/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..cdd0f10 --- /dev/null +++ b/libc/arch-x86/syscalls/__rt_sigprocmask.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_rt_sigprocmask, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__rt_sigprocmask)
diff --git a/libc/arch-x86/syscalls/__rt_sigsuspend.S b/libc/arch-x86/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..ef96949 --- /dev/null +++ b/libc/arch-x86/syscalls/__rt_sigsuspend.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_rt_sigsuspend, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__rt_sigsuspend)
diff --git a/libc/arch-x86/syscalls/__rt_sigtimedwait.S b/libc/arch-x86/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..8205221 --- /dev/null +++ b/libc/arch-x86/syscalls/__rt_sigtimedwait.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_rt_sigtimedwait, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__rt_sigtimedwait)
diff --git a/libc/arch-x86/syscalls/__sched_getaffinity.S b/libc/arch-x86/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..ba658af --- /dev/null +++ b/libc/arch-x86/syscalls/__sched_getaffinity.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_sched_getaffinity, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__sched_getaffinity)
diff --git a/libc/arch-x86/syscalls/__set_thread_area.S b/libc/arch-x86/syscalls/__set_thread_area.S new file mode 100644 index 0000000..7fc04bd --- /dev/null +++ b/libc/arch-x86/syscalls/__set_thread_area.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_thread_area) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_set_thread_area, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__set_thread_area)
diff --git a/libc/arch-x86/syscalls/__set_tid_address.S b/libc/arch-x86/syscalls/__set_tid_address.S new file mode 100644 index 0000000..4301156 --- /dev/null +++ b/libc/arch-x86/syscalls/__set_tid_address.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_set_tid_address, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__set_tid_address)
diff --git a/libc/arch-x86/syscalls/__sigaction.S b/libc/arch-x86/syscalls/__sigaction.S new file mode 100644 index 0000000..6b2b7f3 --- /dev/null +++ b/libc/arch-x86/syscalls/__sigaction.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sigaction) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_sigaction, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__sigaction)
diff --git a/libc/arch-x86/syscalls/__signalfd4.S b/libc/arch-x86/syscalls/__signalfd4.S new file mode 100644 index 0000000..ea817cf --- /dev/null +++ b/libc/arch-x86/syscalls/__signalfd4.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_signalfd4, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__signalfd4)
diff --git a/libc/arch-x86/syscalls/__socket.S b/libc/arch-x86/syscalls/__socket.S new file mode 100644 index 0000000..06d1f1f --- /dev/null +++ b/libc/arch-x86/syscalls/__socket.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $1, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__socket)
diff --git a/libc/arch-x86/syscalls/__statfs64.S b/libc/arch-x86/syscalls/__statfs64.S new file mode 100644 index 0000000..79e1f4b --- /dev/null +++ b/libc/arch-x86/syscalls/__statfs64.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__statfs64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_statfs64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__statfs64)
diff --git a/libc/arch-x86/syscalls/__sync_file_range.S b/libc/arch-x86/syscalls/__sync_file_range.S new file mode 100644 index 0000000..f5bf3ec --- /dev/null +++ b/libc/arch-x86/syscalls/__sync_file_range.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sync_file_range) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_sync_file_range, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__sync_file_range)
diff --git a/libc/arch-x86/syscalls/__timer_create.S b/libc/arch-x86/syscalls/__timer_create.S new file mode 100644 index 0000000..4e16b1c --- /dev/null +++ b/libc/arch-x86/syscalls/__timer_create.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_timer_create, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(__timer_create)
diff --git a/libc/arch-x86/syscalls/__timer_delete.S b/libc/arch-x86/syscalls/__timer_delete.S new file mode 100644 index 0000000..fea422e --- /dev/null +++ b/libc/arch-x86/syscalls/__timer_delete.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_timer_delete, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__timer_delete)
diff --git a/libc/arch-x86/syscalls/__timer_getoverrun.S b/libc/arch-x86/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..e921073 --- /dev/null +++ b/libc/arch-x86/syscalls/__timer_getoverrun.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_timer_getoverrun, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(__timer_getoverrun)
diff --git a/libc/arch-x86/syscalls/__timer_gettime.S b/libc/arch-x86/syscalls/__timer_gettime.S new file mode 100644 index 0000000..4e20356 --- /dev/null +++ b/libc/arch-x86/syscalls/__timer_gettime.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_timer_gettime, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(__timer_gettime)
diff --git a/libc/arch-x86/syscalls/__timer_settime.S b/libc/arch-x86/syscalls/__timer_settime.S new file mode 100644 index 0000000..9b8af34 --- /dev/null +++ b/libc/arch-x86/syscalls/__timer_settime.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_timer_settime, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__timer_settime)
diff --git a/libc/arch-x86/syscalls/__waitid.S b/libc/arch-x86/syscalls/__waitid.S new file mode 100644 index 0000000..f134b42 --- /dev/null +++ b/libc/arch-x86/syscalls/__waitid.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_waitid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(__waitid)
diff --git a/libc/arch-x86/syscalls/_exit.S b/libc/arch-x86/syscalls/_exit.S new file mode 100644 index 0000000..1e89261 --- /dev/null +++ b/libc/arch-x86/syscalls/_exit.S
@@ -0,0 +1,31 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_exit_group, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(_exit) + +ALIAS_SYMBOL(_Exit, _exit)
diff --git a/libc/arch-x86/syscalls/acct.S b/libc/arch-x86/syscalls/acct.S new file mode 100644 index 0000000..48c4c5c --- /dev/null +++ b/libc/arch-x86/syscalls/acct.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_acct, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(acct)
diff --git a/libc/arch-x86/syscalls/adjtimex.S b/libc/arch-x86/syscalls/adjtimex.S new file mode 100644 index 0000000..1b0d8b1 --- /dev/null +++ b/libc/arch-x86/syscalls/adjtimex.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(adjtimex) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_adjtimex, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(adjtimex)
diff --git a/libc/arch-x86/syscalls/bind.S b/libc/arch-x86/syscalls/bind.S new file mode 100644 index 0000000..c1f84da --- /dev/null +++ b/libc/arch-x86/syscalls/bind.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $2, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(bind)
diff --git a/libc/arch-x86/syscalls/capget.S b/libc/arch-x86/syscalls/capget.S new file mode 100644 index 0000000..fafde37 --- /dev/null +++ b/libc/arch-x86/syscalls/capget.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_capget, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(capget)
diff --git a/libc/arch-x86/syscalls/capset.S b/libc/arch-x86/syscalls/capset.S new file mode 100644 index 0000000..28e5338 --- /dev/null +++ b/libc/arch-x86/syscalls/capset.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_capset, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(capset)
diff --git a/libc/arch-x86/syscalls/chdir.S b/libc/arch-x86/syscalls/chdir.S new file mode 100644 index 0000000..4b639eb --- /dev/null +++ b/libc/arch-x86/syscalls/chdir.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_chdir, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(chdir)
diff --git a/libc/arch-x86/syscalls/chroot.S b/libc/arch-x86/syscalls/chroot.S new file mode 100644 index 0000000..8887f86 --- /dev/null +++ b/libc/arch-x86/syscalls/chroot.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_chroot, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(chroot)
diff --git a/libc/arch-x86/syscalls/clock_adjtime.S b/libc/arch-x86/syscalls/clock_adjtime.S new file mode 100644 index 0000000..4ccf1a6 --- /dev/null +++ b/libc/arch-x86/syscalls/clock_adjtime.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_adjtime) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_clock_adjtime, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(clock_adjtime)
diff --git a/libc/arch-x86/syscalls/clock_getres.S b/libc/arch-x86/syscalls/clock_getres.S new file mode 100644 index 0000000..9466e08 --- /dev/null +++ b/libc/arch-x86/syscalls/clock_getres.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_clock_getres, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(clock_getres)
diff --git a/libc/arch-x86/syscalls/clock_settime.S b/libc/arch-x86/syscalls/clock_settime.S new file mode 100644 index 0000000..62dc021 --- /dev/null +++ b/libc/arch-x86/syscalls/clock_settime.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_clock_settime, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(clock_settime)
diff --git a/libc/arch-x86/syscalls/delete_module.S b/libc/arch-x86/syscalls/delete_module.S new file mode 100644 index 0000000..b0c8ff9 --- /dev/null +++ b/libc/arch-x86/syscalls/delete_module.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_delete_module, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(delete_module)
diff --git a/libc/arch-x86/syscalls/dup.S b/libc/arch-x86/syscalls/dup.S new file mode 100644 index 0000000..637cfae --- /dev/null +++ b/libc/arch-x86/syscalls/dup.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_dup, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(dup)
diff --git a/libc/arch-x86/syscalls/dup3.S b/libc/arch-x86/syscalls/dup3.S new file mode 100644 index 0000000..4d08eab --- /dev/null +++ b/libc/arch-x86/syscalls/dup3.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_dup3, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(dup3)
diff --git a/libc/arch-x86/syscalls/epoll_create1.S b/libc/arch-x86/syscalls/epoll_create1.S new file mode 100644 index 0000000..93d1c00 --- /dev/null +++ b/libc/arch-x86/syscalls/epoll_create1.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_epoll_create1, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(epoll_create1)
diff --git a/libc/arch-x86/syscalls/epoll_ctl.S b/libc/arch-x86/syscalls/epoll_ctl.S new file mode 100644 index 0000000..a2d8d27 --- /dev/null +++ b/libc/arch-x86/syscalls/epoll_ctl.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_epoll_ctl, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(epoll_ctl)
diff --git a/libc/arch-x86/syscalls/eventfd.S b/libc/arch-x86/syscalls/eventfd.S new file mode 100644 index 0000000..89f9442 --- /dev/null +++ b/libc/arch-x86/syscalls/eventfd.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_eventfd2, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(eventfd)
diff --git a/libc/arch-x86/syscalls/execve.S b/libc/arch-x86/syscalls/execve.S new file mode 100644 index 0000000..7695635 --- /dev/null +++ b/libc/arch-x86/syscalls/execve.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_execve, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(execve)
diff --git a/libc/arch-x86/syscalls/fallocate64.S b/libc/arch-x86/syscalls/fallocate64.S new file mode 100644 index 0000000..eabc642 --- /dev/null +++ b/libc/arch-x86/syscalls/fallocate64.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_fallocate, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(fallocate64)
diff --git a/libc/arch-x86/syscalls/fchdir.S b/libc/arch-x86/syscalls/fchdir.S new file mode 100644 index 0000000..5701644 --- /dev/null +++ b/libc/arch-x86/syscalls/fchdir.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_fchdir, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(fchdir)
diff --git a/libc/arch-x86/syscalls/fchown.S b/libc/arch-x86/syscalls/fchown.S new file mode 100644 index 0000000..0d41389 --- /dev/null +++ b/libc/arch-x86/syscalls/fchown.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_fchown32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(fchown)
diff --git a/libc/arch-x86/syscalls/fchownat.S b/libc/arch-x86/syscalls/fchownat.S new file mode 100644 index 0000000..56b7777 --- /dev/null +++ b/libc/arch-x86/syscalls/fchownat.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_fchownat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(fchownat)
diff --git a/libc/arch-x86/syscalls/fdatasync.S b/libc/arch-x86/syscalls/fdatasync.S new file mode 100644 index 0000000..6ee9e15 --- /dev/null +++ b/libc/arch-x86/syscalls/fdatasync.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_fdatasync, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(fdatasync)
diff --git a/libc/arch-x86/syscalls/flock.S b/libc/arch-x86/syscalls/flock.S new file mode 100644 index 0000000..b65543d --- /dev/null +++ b/libc/arch-x86/syscalls/flock.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_flock, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(flock)
diff --git a/libc/arch-x86/syscalls/fremovexattr.S b/libc/arch-x86/syscalls/fremovexattr.S new file mode 100644 index 0000000..3511d5d --- /dev/null +++ b/libc/arch-x86/syscalls/fremovexattr.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_fremovexattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(fremovexattr)
diff --git a/libc/arch-x86/syscalls/fstat64.S b/libc/arch-x86/syscalls/fstat64.S new file mode 100644 index 0000000..16eca69 --- /dev/null +++ b/libc/arch-x86/syscalls/fstat64.S
@@ -0,0 +1,36 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstat64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_fstat64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(fstat64) + +ALIAS_SYMBOL(fstat, fstat64)
diff --git a/libc/arch-x86/syscalls/fstatat64.S b/libc/arch-x86/syscalls/fstatat64.S new file mode 100644 index 0000000..402cf60 --- /dev/null +++ b/libc/arch-x86/syscalls/fstatat64.S
@@ -0,0 +1,46 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatat64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_fstatat64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(fstatat64) + +ALIAS_SYMBOL(fstatat, fstatat64)
diff --git a/libc/arch-x86/syscalls/fsync.S b/libc/arch-x86/syscalls/fsync.S new file mode 100644 index 0000000..53aeee6 --- /dev/null +++ b/libc/arch-x86/syscalls/fsync.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_fsync, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(fsync)
diff --git a/libc/arch-x86/syscalls/ftruncate64.S b/libc/arch-x86/syscalls/ftruncate64.S new file mode 100644 index 0000000..2fa792f --- /dev/null +++ b/libc/arch-x86/syscalls/ftruncate64.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_ftruncate64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(ftruncate64)
diff --git a/libc/arch-x86/syscalls/getegid.S b/libc/arch-x86/syscalls/getegid.S new file mode 100644 index 0000000..cb1921e --- /dev/null +++ b/libc/arch-x86/syscalls/getegid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_getegid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(getegid)
diff --git a/libc/arch-x86/syscalls/geteuid.S b/libc/arch-x86/syscalls/geteuid.S new file mode 100644 index 0000000..c08d3ae --- /dev/null +++ b/libc/arch-x86/syscalls/geteuid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_geteuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(geteuid)
diff --git a/libc/arch-x86/syscalls/getgid.S b/libc/arch-x86/syscalls/getgid.S new file mode 100644 index 0000000..9189ae9 --- /dev/null +++ b/libc/arch-x86/syscalls/getgid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_getgid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(getgid)
diff --git a/libc/arch-x86/syscalls/getgroups.S b/libc/arch-x86/syscalls/getgroups.S new file mode 100644 index 0000000..8737d51 --- /dev/null +++ b/libc/arch-x86/syscalls/getgroups.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_getgroups32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getgroups)
diff --git a/libc/arch-x86/syscalls/getitimer.S b/libc/arch-x86/syscalls/getitimer.S new file mode 100644 index 0000000..e088114 --- /dev/null +++ b/libc/arch-x86/syscalls/getitimer.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_getitimer, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getitimer)
diff --git a/libc/arch-x86/syscalls/getpeername.S b/libc/arch-x86/syscalls/getpeername.S new file mode 100644 index 0000000..40bb814 --- /dev/null +++ b/libc/arch-x86/syscalls/getpeername.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $7, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getpeername)
diff --git a/libc/arch-x86/syscalls/getpgid.S b/libc/arch-x86/syscalls/getpgid.S new file mode 100644 index 0000000..9d362e8 --- /dev/null +++ b/libc/arch-x86/syscalls/getpgid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_getpgid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(getpgid)
diff --git a/libc/arch-x86/syscalls/getppid.S b/libc/arch-x86/syscalls/getppid.S new file mode 100644 index 0000000..afb40a1 --- /dev/null +++ b/libc/arch-x86/syscalls/getppid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_getppid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(getppid)
diff --git a/libc/arch-x86/syscalls/getresgid.S b/libc/arch-x86/syscalls/getresgid.S new file mode 100644 index 0000000..131c101 --- /dev/null +++ b/libc/arch-x86/syscalls/getresgid.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_getresgid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(getresgid)
diff --git a/libc/arch-x86/syscalls/getresuid.S b/libc/arch-x86/syscalls/getresuid.S new file mode 100644 index 0000000..94a8767 --- /dev/null +++ b/libc/arch-x86/syscalls/getresuid.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_getresuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(getresuid)
diff --git a/libc/arch-x86/syscalls/getrlimit.S b/libc/arch-x86/syscalls/getrlimit.S new file mode 100644 index 0000000..c686f7c --- /dev/null +++ b/libc/arch-x86/syscalls/getrlimit.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_ugetrlimit, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getrlimit)
diff --git a/libc/arch-x86/syscalls/getrusage.S b/libc/arch-x86/syscalls/getrusage.S new file mode 100644 index 0000000..51d1df1 --- /dev/null +++ b/libc/arch-x86/syscalls/getrusage.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_getrusage, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getrusage)
diff --git a/libc/arch-x86/syscalls/getsid.S b/libc/arch-x86/syscalls/getsid.S new file mode 100644 index 0000000..a4568e6 --- /dev/null +++ b/libc/arch-x86/syscalls/getsid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_getsid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(getsid)
diff --git a/libc/arch-x86/syscalls/getsockname.S b/libc/arch-x86/syscalls/getsockname.S new file mode 100644 index 0000000..0fd5836 --- /dev/null +++ b/libc/arch-x86/syscalls/getsockname.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $6, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getsockname)
diff --git a/libc/arch-x86/syscalls/getsockopt.S b/libc/arch-x86/syscalls/getsockopt.S new file mode 100644 index 0000000..fa6fccf --- /dev/null +++ b/libc/arch-x86/syscalls/getsockopt.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $15, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(getsockopt)
diff --git a/libc/arch-x86/syscalls/getuid.S b/libc/arch-x86/syscalls/getuid.S new file mode 100644 index 0000000..11cc0c6 --- /dev/null +++ b/libc/arch-x86/syscalls/getuid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_getuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(getuid)
diff --git a/libc/arch-x86/syscalls/getxattr.S b/libc/arch-x86/syscalls/getxattr.S new file mode 100644 index 0000000..871362e --- /dev/null +++ b/libc/arch-x86/syscalls/getxattr.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_getxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(getxattr)
diff --git a/libc/arch-x86/syscalls/init_module.S b/libc/arch-x86/syscalls/init_module.S new file mode 100644 index 0000000..0147eee --- /dev/null +++ b/libc/arch-x86/syscalls/init_module.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_init_module, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(init_module)
diff --git a/libc/arch-x86/syscalls/inotify_add_watch.S b/libc/arch-x86/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..f196440 --- /dev/null +++ b/libc/arch-x86/syscalls/inotify_add_watch.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_inotify_add_watch, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(inotify_add_watch)
diff --git a/libc/arch-x86/syscalls/inotify_init1.S b/libc/arch-x86/syscalls/inotify_init1.S new file mode 100644 index 0000000..7f0dcfb --- /dev/null +++ b/libc/arch-x86/syscalls/inotify_init1.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_inotify_init1, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(inotify_init1)
diff --git a/libc/arch-x86/syscalls/inotify_rm_watch.S b/libc/arch-x86/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..595e053 --- /dev/null +++ b/libc/arch-x86/syscalls/inotify_rm_watch.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_inotify_rm_watch, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(inotify_rm_watch)
diff --git a/libc/arch-x86/syscalls/kill.S b/libc/arch-x86/syscalls/kill.S new file mode 100644 index 0000000..4ee56e6 --- /dev/null +++ b/libc/arch-x86/syscalls/kill.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_kill, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(kill)
diff --git a/libc/arch-x86/syscalls/klogctl.S b/libc/arch-x86/syscalls/klogctl.S new file mode 100644 index 0000000..3d07942 --- /dev/null +++ b/libc/arch-x86/syscalls/klogctl.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_syslog, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(klogctl)
diff --git a/libc/arch-x86/syscalls/lgetxattr.S b/libc/arch-x86/syscalls/lgetxattr.S new file mode 100644 index 0000000..659b088 --- /dev/null +++ b/libc/arch-x86/syscalls/lgetxattr.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_lgetxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(lgetxattr)
diff --git a/libc/arch-x86/syscalls/linkat.S b/libc/arch-x86/syscalls/linkat.S new file mode 100644 index 0000000..644172d --- /dev/null +++ b/libc/arch-x86/syscalls/linkat.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_linkat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(linkat)
diff --git a/libc/arch-x86/syscalls/listen.S b/libc/arch-x86/syscalls/listen.S new file mode 100644 index 0000000..ce7c3a9 --- /dev/null +++ b/libc/arch-x86/syscalls/listen.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $4, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(listen)
diff --git a/libc/arch-x86/syscalls/listxattr.S b/libc/arch-x86/syscalls/listxattr.S new file mode 100644 index 0000000..2fe799e --- /dev/null +++ b/libc/arch-x86/syscalls/listxattr.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_listxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(listxattr)
diff --git a/libc/arch-x86/syscalls/llistxattr.S b/libc/arch-x86/syscalls/llistxattr.S new file mode 100644 index 0000000..666d87e --- /dev/null +++ b/libc/arch-x86/syscalls/llistxattr.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_llistxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(llistxattr)
diff --git a/libc/arch-x86/syscalls/lremovexattr.S b/libc/arch-x86/syscalls/lremovexattr.S new file mode 100644 index 0000000..bda772b --- /dev/null +++ b/libc/arch-x86/syscalls/lremovexattr.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_lremovexattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(lremovexattr)
diff --git a/libc/arch-x86/syscalls/lseek.S b/libc/arch-x86/syscalls/lseek.S new file mode 100644 index 0000000..9142b5c --- /dev/null +++ b/libc/arch-x86/syscalls/lseek.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_lseek, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(lseek)
diff --git a/libc/arch-x86/syscalls/lsetxattr.S b/libc/arch-x86/syscalls/lsetxattr.S new file mode 100644 index 0000000..fa977b3 --- /dev/null +++ b/libc/arch-x86/syscalls/lsetxattr.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_lsetxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(lsetxattr)
diff --git a/libc/arch-x86/syscalls/madvise.S b/libc/arch-x86/syscalls/madvise.S new file mode 100644 index 0000000..21f472e --- /dev/null +++ b/libc/arch-x86/syscalls/madvise.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_madvise, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(madvise)
diff --git a/libc/arch-x86/syscalls/mincore.S b/libc/arch-x86/syscalls/mincore.S new file mode 100644 index 0000000..4179c9a --- /dev/null +++ b/libc/arch-x86/syscalls/mincore.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_mincore, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(mincore)
diff --git a/libc/arch-x86/syscalls/mkdirat.S b/libc/arch-x86/syscalls/mkdirat.S new file mode 100644 index 0000000..6a9d94c --- /dev/null +++ b/libc/arch-x86/syscalls/mkdirat.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_mkdirat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(mkdirat)
diff --git a/libc/arch-x86/syscalls/mknodat.S b/libc/arch-x86/syscalls/mknodat.S new file mode 100644 index 0000000..a1fae7f --- /dev/null +++ b/libc/arch-x86/syscalls/mknodat.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_mknodat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(mknodat)
diff --git a/libc/arch-x86/syscalls/mlock.S b/libc/arch-x86/syscalls/mlock.S new file mode 100644 index 0000000..1c57ac0 --- /dev/null +++ b/libc/arch-x86/syscalls/mlock.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_mlock, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(mlock)
diff --git a/libc/arch-x86/syscalls/mlockall.S b/libc/arch-x86/syscalls/mlockall.S new file mode 100644 index 0000000..9f54de3 --- /dev/null +++ b/libc/arch-x86/syscalls/mlockall.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_mlockall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(mlockall)
diff --git a/libc/arch-x86/syscalls/mount.S b/libc/arch-x86/syscalls/mount.S new file mode 100644 index 0000000..4a9f91a --- /dev/null +++ b/libc/arch-x86/syscalls/mount.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_mount, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(mount)
diff --git a/libc/arch-x86/syscalls/mprotect.S b/libc/arch-x86/syscalls/mprotect.S new file mode 100644 index 0000000..5eec550 --- /dev/null +++ b/libc/arch-x86/syscalls/mprotect.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_mprotect, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(mprotect)
diff --git a/libc/arch-x86/syscalls/msync.S b/libc/arch-x86/syscalls/msync.S new file mode 100644 index 0000000..7754da6 --- /dev/null +++ b/libc/arch-x86/syscalls/msync.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_msync, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(msync)
diff --git a/libc/arch-x86/syscalls/munlock.S b/libc/arch-x86/syscalls/munlock.S new file mode 100644 index 0000000..d2ae9f0 --- /dev/null +++ b/libc/arch-x86/syscalls/munlock.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_munlock, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(munlock)
diff --git a/libc/arch-x86/syscalls/munlockall.S b/libc/arch-x86/syscalls/munlockall.S new file mode 100644 index 0000000..e709b8c --- /dev/null +++ b/libc/arch-x86/syscalls/munlockall.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_munlockall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(munlockall)
diff --git a/libc/arch-x86/syscalls/munmap.S b/libc/arch-x86/syscalls/munmap.S new file mode 100644 index 0000000..7ddc5aa --- /dev/null +++ b/libc/arch-x86/syscalls/munmap.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_munmap, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(munmap)
diff --git a/libc/arch-x86/syscalls/nanosleep.S b/libc/arch-x86/syscalls/nanosleep.S new file mode 100644 index 0000000..580f5e1 --- /dev/null +++ b/libc/arch-x86/syscalls/nanosleep.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_nanosleep, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(nanosleep)
diff --git a/libc/arch-x86/syscalls/personality.S b/libc/arch-x86/syscalls/personality.S new file mode 100644 index 0000000..3e003c4 --- /dev/null +++ b/libc/arch-x86/syscalls/personality.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_personality, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(personality)
diff --git a/libc/arch-x86/syscalls/pipe2.S b/libc/arch-x86/syscalls/pipe2.S new file mode 100644 index 0000000..8a93281 --- /dev/null +++ b/libc/arch-x86/syscalls/pipe2.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_pipe2, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(pipe2)
diff --git a/libc/arch-x86/syscalls/prctl.S b/libc/arch-x86/syscalls/prctl.S new file mode 100644 index 0000000..22b4a83 --- /dev/null +++ b/libc/arch-x86/syscalls/prctl.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_prctl, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(prctl)
diff --git a/libc/arch-x86/syscalls/pread64.S b/libc/arch-x86/syscalls/pread64.S new file mode 100644 index 0000000..9002f17 --- /dev/null +++ b/libc/arch-x86/syscalls/pread64.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_pread64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(pread64)
diff --git a/libc/arch-x86/syscalls/prlimit64.S b/libc/arch-x86/syscalls/prlimit64.S new file mode 100644 index 0000000..13f6682 --- /dev/null +++ b/libc/arch-x86/syscalls/prlimit64.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_prlimit64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(prlimit64)
diff --git a/libc/arch-x86/syscalls/process_vm_readv.S b/libc/arch-x86/syscalls/process_vm_readv.S new file mode 100644 index 0000000..e2cd044 --- /dev/null +++ b/libc/arch-x86/syscalls/process_vm_readv.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_readv) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_process_vm_readv, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(process_vm_readv)
diff --git a/libc/arch-x86/syscalls/process_vm_writev.S b/libc/arch-x86/syscalls/process_vm_writev.S new file mode 100644 index 0000000..de0d218 --- /dev/null +++ b/libc/arch-x86/syscalls/process_vm_writev.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(process_vm_writev) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_process_vm_writev, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(process_vm_writev)
diff --git a/libc/arch-x86/syscalls/pwrite64.S b/libc/arch-x86/syscalls/pwrite64.S new file mode 100644 index 0000000..7532729 --- /dev/null +++ b/libc/arch-x86/syscalls/pwrite64.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_pwrite64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(pwrite64)
diff --git a/libc/arch-x86/syscalls/quotactl.S b/libc/arch-x86/syscalls/quotactl.S new file mode 100644 index 0000000..326cf87 --- /dev/null +++ b/libc/arch-x86/syscalls/quotactl.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(quotactl) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_quotactl, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(quotactl)
diff --git a/libc/arch-x86/syscalls/read.S b/libc/arch-x86/syscalls/read.S new file mode 100644 index 0000000..d4b69b5 --- /dev/null +++ b/libc/arch-x86/syscalls/read.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_read, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(read)
diff --git a/libc/arch-x86/syscalls/readahead.S b/libc/arch-x86/syscalls/readahead.S new file mode 100644 index 0000000..8ce22bb --- /dev/null +++ b/libc/arch-x86/syscalls/readahead.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_readahead, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(readahead)
diff --git a/libc/arch-x86/syscalls/readlinkat.S b/libc/arch-x86/syscalls/readlinkat.S new file mode 100644 index 0000000..8b74a4e --- /dev/null +++ b/libc/arch-x86/syscalls/readlinkat.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_readlinkat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(readlinkat)
diff --git a/libc/arch-x86/syscalls/readv.S b/libc/arch-x86/syscalls/readv.S new file mode 100644 index 0000000..a1cb08f --- /dev/null +++ b/libc/arch-x86/syscalls/readv.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_readv, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(readv)
diff --git a/libc/arch-x86/syscalls/recvfrom.S b/libc/arch-x86/syscalls/recvfrom.S new file mode 100644 index 0000000..cedd703 --- /dev/null +++ b/libc/arch-x86/syscalls/recvfrom.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $12, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(recvfrom)
diff --git a/libc/arch-x86/syscalls/recvmmsg.S b/libc/arch-x86/syscalls/recvmmsg.S new file mode 100644 index 0000000..130332a --- /dev/null +++ b/libc/arch-x86/syscalls/recvmmsg.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $19, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(recvmmsg)
diff --git a/libc/arch-x86/syscalls/recvmsg.S b/libc/arch-x86/syscalls/recvmsg.S new file mode 100644 index 0000000..c8d2a08 --- /dev/null +++ b/libc/arch-x86/syscalls/recvmsg.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $17, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(recvmsg)
diff --git a/libc/arch-x86/syscalls/removexattr.S b/libc/arch-x86/syscalls/removexattr.S new file mode 100644 index 0000000..ab7891e --- /dev/null +++ b/libc/arch-x86/syscalls/removexattr.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_removexattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(removexattr)
diff --git a/libc/arch-x86/syscalls/renameat.S b/libc/arch-x86/syscalls/renameat.S new file mode 100644 index 0000000..40caaaf --- /dev/null +++ b/libc/arch-x86/syscalls/renameat.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_renameat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(renameat)
diff --git a/libc/arch-x86/syscalls/sched_get_priority_max.S b/libc/arch-x86/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..637c9dd --- /dev/null +++ b/libc/arch-x86/syscalls/sched_get_priority_max.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_sched_get_priority_max, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(sched_get_priority_max)
diff --git a/libc/arch-x86/syscalls/sched_get_priority_min.S b/libc/arch-x86/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..c38a3aa --- /dev/null +++ b/libc/arch-x86/syscalls/sched_get_priority_min.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_sched_get_priority_min, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(sched_get_priority_min)
diff --git a/libc/arch-x86/syscalls/sched_getparam.S b/libc/arch-x86/syscalls/sched_getparam.S new file mode 100644 index 0000000..09901bd --- /dev/null +++ b/libc/arch-x86/syscalls/sched_getparam.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_sched_getparam, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sched_getparam)
diff --git a/libc/arch-x86/syscalls/sched_getscheduler.S b/libc/arch-x86/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..adc4023 --- /dev/null +++ b/libc/arch-x86/syscalls/sched_getscheduler.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_sched_getscheduler, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(sched_getscheduler)
diff --git a/libc/arch-x86/syscalls/sched_rr_get_interval.S b/libc/arch-x86/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..818f62e --- /dev/null +++ b/libc/arch-x86/syscalls/sched_rr_get_interval.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_sched_rr_get_interval, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sched_rr_get_interval)
diff --git a/libc/arch-x86/syscalls/sched_setaffinity.S b/libc/arch-x86/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..b06d778 --- /dev/null +++ b/libc/arch-x86/syscalls/sched_setaffinity.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_sched_setaffinity, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(sched_setaffinity)
diff --git a/libc/arch-x86/syscalls/sched_setparam.S b/libc/arch-x86/syscalls/sched_setparam.S new file mode 100644 index 0000000..dba5bc2 --- /dev/null +++ b/libc/arch-x86/syscalls/sched_setparam.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_sched_setparam, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sched_setparam)
diff --git a/libc/arch-x86/syscalls/sched_setscheduler.S b/libc/arch-x86/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..466a425 --- /dev/null +++ b/libc/arch-x86/syscalls/sched_setscheduler.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_sched_setscheduler, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(sched_setscheduler)
diff --git a/libc/arch-x86/syscalls/sched_yield.S b/libc/arch-x86/syscalls/sched_yield.S new file mode 100644 index 0000000..b17b14e --- /dev/null +++ b/libc/arch-x86/syscalls/sched_yield.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_sched_yield, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(sched_yield)
diff --git a/libc/arch-x86/syscalls/sendfile.S b/libc/arch-x86/syscalls/sendfile.S new file mode 100644 index 0000000..e091706 --- /dev/null +++ b/libc/arch-x86/syscalls/sendfile.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_sendfile, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(sendfile)
diff --git a/libc/arch-x86/syscalls/sendfile64.S b/libc/arch-x86/syscalls/sendfile64.S new file mode 100644 index 0000000..317c4f4 --- /dev/null +++ b/libc/arch-x86/syscalls/sendfile64.S
@@ -0,0 +1,44 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile64) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 24(%esp), %ebx + mov 28(%esp), %ecx + mov 32(%esp), %edx + mov 36(%esp), %esi + movl $__NR_sendfile64, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(sendfile64)
diff --git a/libc/arch-x86/syscalls/sendmmsg.S b/libc/arch-x86/syscalls/sendmmsg.S new file mode 100644 index 0000000..c0097f8 --- /dev/null +++ b/libc/arch-x86/syscalls/sendmmsg.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $20, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sendmmsg)
diff --git a/libc/arch-x86/syscalls/sendmsg.S b/libc/arch-x86/syscalls/sendmsg.S new file mode 100644 index 0000000..775ebee --- /dev/null +++ b/libc/arch-x86/syscalls/sendmsg.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $16, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sendmsg)
diff --git a/libc/arch-x86/syscalls/sendto.S b/libc/arch-x86/syscalls/sendto.S new file mode 100644 index 0000000..2df5e4f --- /dev/null +++ b/libc/arch-x86/syscalls/sendto.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $11, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sendto)
diff --git a/libc/arch-x86/syscalls/setdomainname.S b/libc/arch-x86/syscalls/setdomainname.S new file mode 100644 index 0000000..8b6afe2 --- /dev/null +++ b/libc/arch-x86/syscalls/setdomainname.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setdomainname) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setdomainname, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setdomainname)
diff --git a/libc/arch-x86/syscalls/setfsgid.S b/libc/arch-x86/syscalls/setfsgid.S new file mode 100644 index 0000000..af4ef89 --- /dev/null +++ b/libc/arch-x86/syscalls/setfsgid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_setfsgid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(setfsgid)
diff --git a/libc/arch-x86/syscalls/setfsuid.S b/libc/arch-x86/syscalls/setfsuid.S new file mode 100644 index 0000000..8001e42 --- /dev/null +++ b/libc/arch-x86/syscalls/setfsuid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_setfsuid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(setfsuid)
diff --git a/libc/arch-x86/syscalls/setgid.S b/libc/arch-x86/syscalls/setgid.S new file mode 100644 index 0000000..c0ddec4 --- /dev/null +++ b/libc/arch-x86/syscalls/setgid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_setgid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(setgid)
diff --git a/libc/arch-x86/syscalls/setgroups.S b/libc/arch-x86/syscalls/setgroups.S new file mode 100644 index 0000000..7bd3bfc --- /dev/null +++ b/libc/arch-x86/syscalls/setgroups.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setgroups32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setgroups)
diff --git a/libc/arch-x86/syscalls/sethostname.S b/libc/arch-x86/syscalls/sethostname.S new file mode 100644 index 0000000..26ff1e7 --- /dev/null +++ b/libc/arch-x86/syscalls/sethostname.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sethostname) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_sethostname, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sethostname)
diff --git a/libc/arch-x86/syscalls/setitimer.S b/libc/arch-x86/syscalls/setitimer.S new file mode 100644 index 0000000..063847b --- /dev/null +++ b/libc/arch-x86/syscalls/setitimer.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_setitimer, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(setitimer)
diff --git a/libc/arch-x86/syscalls/setns.S b/libc/arch-x86/syscalls/setns.S new file mode 100644 index 0000000..28d838e --- /dev/null +++ b/libc/arch-x86/syscalls/setns.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setns, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setns)
diff --git a/libc/arch-x86/syscalls/setpgid.S b/libc/arch-x86/syscalls/setpgid.S new file mode 100644 index 0000000..c5d0d27 --- /dev/null +++ b/libc/arch-x86/syscalls/setpgid.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setpgid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setpgid)
diff --git a/libc/arch-x86/syscalls/setpriority.S b/libc/arch-x86/syscalls/setpriority.S new file mode 100644 index 0000000..17c81c6 --- /dev/null +++ b/libc/arch-x86/syscalls/setpriority.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_setpriority, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(setpriority)
diff --git a/libc/arch-x86/syscalls/setregid.S b/libc/arch-x86/syscalls/setregid.S new file mode 100644 index 0000000..dd8101a --- /dev/null +++ b/libc/arch-x86/syscalls/setregid.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setregid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setregid)
diff --git a/libc/arch-x86/syscalls/setresgid.S b/libc/arch-x86/syscalls/setresgid.S new file mode 100644 index 0000000..6f6de5a --- /dev/null +++ b/libc/arch-x86/syscalls/setresgid.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_setresgid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(setresgid)
diff --git a/libc/arch-x86/syscalls/setresuid.S b/libc/arch-x86/syscalls/setresuid.S new file mode 100644 index 0000000..ab0059c --- /dev/null +++ b/libc/arch-x86/syscalls/setresuid.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_setresuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(setresuid)
diff --git a/libc/arch-x86/syscalls/setreuid.S b/libc/arch-x86/syscalls/setreuid.S new file mode 100644 index 0000000..7fda62e --- /dev/null +++ b/libc/arch-x86/syscalls/setreuid.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setreuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setreuid)
diff --git a/libc/arch-x86/syscalls/setrlimit.S b/libc/arch-x86/syscalls/setrlimit.S new file mode 100644 index 0000000..595633e --- /dev/null +++ b/libc/arch-x86/syscalls/setrlimit.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_setrlimit, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setrlimit)
diff --git a/libc/arch-x86/syscalls/setsid.S b/libc/arch-x86/syscalls/setsid.S new file mode 100644 index 0000000..80ad8a9 --- /dev/null +++ b/libc/arch-x86/syscalls/setsid.S
@@ -0,0 +1,24 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + movl $__NR_setsid, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + ret +END(setsid)
diff --git a/libc/arch-x86/syscalls/setsockopt.S b/libc/arch-x86/syscalls/setsockopt.S new file mode 100644 index 0000000..bca34e1 --- /dev/null +++ b/libc/arch-x86/syscalls/setsockopt.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $14, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(setsockopt)
diff --git a/libc/arch-x86/syscalls/settimeofday.S b/libc/arch-x86/syscalls/settimeofday.S new file mode 100644 index 0000000..31437d0 --- /dev/null +++ b/libc/arch-x86/syscalls/settimeofday.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_settimeofday, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(settimeofday)
diff --git a/libc/arch-x86/syscalls/setuid.S b/libc/arch-x86/syscalls/setuid.S new file mode 100644 index 0000000..2461182 --- /dev/null +++ b/libc/arch-x86/syscalls/setuid.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_setuid32, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(setuid)
diff --git a/libc/arch-x86/syscalls/setxattr.S b/libc/arch-x86/syscalls/setxattr.S new file mode 100644 index 0000000..787891e --- /dev/null +++ b/libc/arch-x86/syscalls/setxattr.S
@@ -0,0 +1,49 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 28(%esp), %ebx + mov 32(%esp), %ecx + mov 36(%esp), %edx + mov 40(%esp), %esi + mov 44(%esp), %edi + movl $__NR_setxattr, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(setxattr)
diff --git a/libc/arch-x86/syscalls/shutdown.S b/libc/arch-x86/syscalls/shutdown.S new file mode 100644 index 0000000..46e5c18 --- /dev/null +++ b/libc/arch-x86/syscalls/shutdown.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $13, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(shutdown)
diff --git a/libc/arch-x86/syscalls/sigaltstack.S b/libc/arch-x86/syscalls/sigaltstack.S new file mode 100644 index 0000000..90eae16 --- /dev/null +++ b/libc/arch-x86/syscalls/sigaltstack.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_sigaltstack, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(sigaltstack)
diff --git a/libc/arch-x86/syscalls/socketpair.S b/libc/arch-x86/syscalls/socketpair.S new file mode 100644 index 0000000..c9c7595 --- /dev/null +++ b/libc/arch-x86/syscalls/socketpair.S
@@ -0,0 +1,35 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov $8, %ebx + mov %esp, %ecx + addl $16, %ecx + movl $__NR_socketcall, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(socketpair)
diff --git a/libc/arch-x86/syscalls/splice.S b/libc/arch-x86/syscalls/splice.S new file mode 100644 index 0000000..2d82a3d --- /dev/null +++ b/libc/arch-x86/syscalls/splice.S
@@ -0,0 +1,54 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + pushl %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + pushl %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + pushl %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 32(%esp), %ebx + mov 36(%esp), %ecx + mov 40(%esp), %edx + mov 44(%esp), %esi + mov 48(%esp), %edi + mov 52(%esp), %ebp + movl $__NR_splice, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebp + popl %edi + popl %esi + popl %edx + popl %ecx + popl %ebx + ret +END(splice)
diff --git a/libc/arch-x86/syscalls/swapoff.S b/libc/arch-x86/syscalls/swapoff.S new file mode 100644 index 0000000..d10a748 --- /dev/null +++ b/libc/arch-x86/syscalls/swapoff.S
@@ -0,0 +1,29 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 12(%esp), %ebx + movl $__NR_swapoff, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ebx + ret +END(swapoff)
diff --git a/libc/arch-x86/syscalls/swapon.S b/libc/arch-x86/syscalls/swapon.S new file mode 100644 index 0000000..dc7db64 --- /dev/null +++ b/libc/arch-x86/syscalls/swapon.S
@@ -0,0 +1,34 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 16(%esp), %ebx + mov 20(%esp), %ecx + movl $__NR_swapon, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %ecx + popl %ebx + ret +END(swapon)
diff --git a/libc/arch-x86/syscalls/symlinkat.S b/libc/arch-x86/syscalls/symlinkat.S new file mode 100644 index 0000000..51b1330 --- /dev/null +++ b/libc/arch-x86/syscalls/symlinkat.S
@@ -0,0 +1,39 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + pushl %ebx + .cfi_def_cfa_offset 8 + .cfi_rel_offset ebx, 0 + pushl %ecx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ecx, 0 + pushl %edx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edx, 0 + + call __kernel_syscall + pushl %eax + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset eax, 0 + + mov 20(%esp), %ebx + mov 24(%esp), %ecx + mov 28(%esp), %edx + movl $__NR_symlinkat, %eax + call *(%esp) + addl $4, %esp + + cmpl $-MAX_ERRNO, %eax + jb 1f + negl %eax + pushl %eax + call __set_errno_internal + addl $4, %esp +1: + popl %edx + popl %ecx + popl %ebx + ret +END(symlinkat)
diff --git a/libc/arch-x86/syscalls/s