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| <h4 class="subsection">9.14.3 i860 Machine Directives</h4> |
| |
| <p><a name="index-machine-directives_002c-i860-1000"></a><a name="index-i860-machine-directives-1001"></a> |
| |
| <a name="index-g_t_0040code_007bdual_007d-directive_002c-i860-1002"></a> |
| <dl><dt><code>.dual</code><dd>Enter dual instruction mode. While this directive is supported, the |
| preferred way to use dual instruction mode is to explicitly code |
| the dual bit with the <code>d.</code> prefix. |
| </dl> |
| |
| |
| <a name="index-g_t_0040code_007benddual_007d-directive_002c-i860-1003"></a> |
| <dl><dt><code>.enddual</code><dd>Exit dual instruction mode. While this directive is supported, the |
| preferred way to use dual instruction mode is to explicitly code |
| the dual bit with the <code>d.</code> prefix. |
| </dl> |
| |
| |
| <a name="index-g_t_0040code_007batmp_007d-directive_002c-i860-1004"></a> |
| <dl><dt><code>.atmp</code><dd>Change the temporary register used when expanding pseudo operations. The |
| default register is <code>r31</code>. |
| </dl> |
| |
| <p>The <code>.dual</code>, <code>.enddual</code>, and <code>.atmp</code> directives are available only in the Intel syntax mode. |
| |
| <p>Both syntaxes allow for the standard <code>.align</code> directive. However, |
| the Intel syntax additionally allows keywords for the alignment |
| parameter: "<code>.align type</code>", where `type' is one of <code>.short</code>, <code>.long</code>, |
| <code>.quad</code>, <code>.single</code>, <code>.double</code> representing alignments of 2, 4, |
| 16, 4, and 8, respectively. |
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