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| <h5 class="subsubsection">9.18.2.1 Register Names</h5> |
| |
| <p><a name="index-LM32-register-names-1072"></a><a name="index-register-names_002c-LM32-1073"></a> |
| LM32 has 32 x 32-bit general purpose registers ‘<samp><span class="samp">r0</span></samp>’, |
| ‘<samp><span class="samp">r1</span></samp>’, ... ‘<samp><span class="samp">r31</span></samp>’. |
| |
| <p>The following aliases are defined: ‘<samp><span class="samp">gp</span></samp>’ - ‘<samp><span class="samp">r26</span></samp>’, |
| ‘<samp><span class="samp">fp</span></samp>’ - ‘<samp><span class="samp">r27</span></samp>’, ‘<samp><span class="samp">sp</span></samp>’ - ‘<samp><span class="samp">r28</span></samp>’, |
| ‘<samp><span class="samp">ra</span></samp>’ - ‘<samp><span class="samp">r29</span></samp>’, ‘<samp><span class="samp">ea</span></samp>’ - ‘<samp><span class="samp">r30</span></samp>’, |
| ‘<samp><span class="samp">ba</span></samp>’ - ‘<samp><span class="samp">r31</span></samp>’. |
| |
| <p>LM32 has the following Control and Status Registers (CSRs). |
| |
| <dl> |
| <dt><code>IE</code><dd>Interrupt enable. |
| <br><dt><code>IM</code><dd>Interrupt mask. |
| <br><dt><code>IP</code><dd>Interrupt pending. |
| <br><dt><code>ICC</code><dd>Instruction cache control. |
| <br><dt><code>DCC</code><dd>Data cache control. |
| <br><dt><code>CC</code><dd>Cycle counter. |
| <br><dt><code>CFG</code><dd>Configuration. |
| <br><dt><code>EBA</code><dd>Exception base address. |
| <br><dt><code>DC</code><dd>Debug control. |
| <br><dt><code>DEBA</code><dd>Debug exception base address. |
| <br><dt><code>JTX</code><dd>JTAG transmit. |
| <br><dt><code>JRX</code><dd>JTAG receive. |
| <br><dt><code>BP0</code><dd>Breakpoint 0. |
| <br><dt><code>BP1</code><dd>Breakpoint 1. |
| <br><dt><code>BP2</code><dd>Breakpoint 2. |
| <br><dt><code>BP3</code><dd>Breakpoint 3. |
| <br><dt><code>WP0</code><dd>Watchpoint 0. |
| <br><dt><code>WP1</code><dd>Watchpoint 1. |
| <br><dt><code>WP2</code><dd>Watchpoint 2. |
| <br><dt><code>WP3</code><dd>Watchpoint 3. |
| </dl> |
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