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| <h5 class="subsubsection">9.42.3.2 Automatic Instruction Alignment</h5> |
| |
| <p><a name="index-alignment-of-_0040code_007bLOOP_007d-instructions-2020"></a><a name="index-alignment-of-branch-targets-2021"></a><a name="index-g_t_0040code_007bLOOP_007d-instructions_002c-alignment-2022"></a><a name="index-branch-target-alignment-2023"></a> |
| The Xtensa assembler will automatically align certain instructions, both |
| to optimize performance and to satisfy architectural requirements. |
| |
| <p>As an optimization to improve performance, the assembler attempts to |
| align branch targets so they do not cross instruction fetch boundaries. |
| (Xtensa processors can be configured with either 32-bit or 64-bit |
| instruction fetch widths.) An |
| instruction immediately following a call is treated as a branch target |
| in this context, because it will be the target of a return from the |
| call. This alignment has the potential to reduce branch penalties at |
| some expense in code size. |
| This optimization is enabled by default. You can disable it with the |
| ‘<samp><span class="samp">--no-target-align</span></samp>’ command-line option (see <a href="Xtensa-Options.html#Xtensa-Options">Command Line Options</a>). |
| |
| <p>The target alignment optimization is done without adding instructions |
| that could increase the execution time of the program. If there are |
| density instructions in the code preceding a target, the assembler can |
| change the target alignment by widening some of those instructions to |
| the equivalent 24-bit instructions. Extra bytes of padding can be |
| inserted immediately following unconditional jump and return |
| instructions. |
| This approach is usually successful in aligning many, but not all, |
| branch targets. |
| |
| <p>The <code>LOOP</code> family of instructions must be aligned such that the |
| first instruction in the loop body does not cross an instruction fetch |
| boundary (e.g., with a 32-bit fetch width, a <code>LOOP</code> instruction |
| must be on either a 1 or 2 mod 4 byte boundary). The assembler knows |
| about this restriction and inserts the minimal number of 2 or 3 byte |
| no-op instructions to satisfy it. When no-op instructions are added, |
| any label immediately preceding the original loop will be moved in order |
| to refer to the loop instruction, not the newly generated no-op |
| instruction. To preserve binary compatibility across processors with |
| different fetch widths, the assembler conservatively assumes a 32-bit |
| fetch width when aligning <code>LOOP</code> instructions (except if the first |
| instruction in the loop is a 64-bit instruction). |
| |
| <p>Previous versions of the assembler automatically aligned <code>ENTRY</code> |
| instructions to 4-byte boundaries, but that alignment is now the |
| programmer's responsibility. |
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