arm-2011.03/share/doc/arm-arm-none-linux-gnueabi/html/gcc/ARM-NEON-Intrinsics.html - nest-cam/v366/arm-none-linux-gnueabi-i686-pc-linux-gnu - Git at Google

 <html lang="en">
 <head>
 <title>ARM NEON Intrinsics - Using the GNU Compiler Collection (GCC)</title>
 <meta http-equiv="Content-Type" content="text/html">
 <meta name="description" content="Using the GNU Compiler Collection (GCC)">
 <meta name="generator" content="makeinfo 4.13">
 <link title="Top" rel="start" href="index.html#Top">
 <link rel="up" href="Target-Builtins.html#Target-Builtins" title="Target Builtins">
 <link rel="prev" href="ARM-iWMMXt-Built_002din-Functions.html#ARM-iWMMXt-Built_002din-Functions" title="ARM iWMMXt Built-in Functions">
 <link rel="next" href="Blackfin-Built_002din-Functions.html#Blackfin-Built_002din-Functions" title="Blackfin Built-in Functions">
 <link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
 <!--
 Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
 2008 Free Software Foundation, Inc.

 Permission is granted to copy, distribute and/or modify this document
 under the terms of the GNU Free Documentation License, Version 1.2 or
 any later version published by the Free Software Foundation; with the
 Invariant Sections being ``Funding Free Software'', the Front-Cover
 Texts being (a) (see below), and with the Back-Cover Texts being (b)
 (see below).  A copy of the license is included in the section entitled
 ``GNU Free Documentation License''.

 (a) The FSF's Front-Cover Text is:

      A GNU Manual

 (b) The FSF's Back-Cover Text is:

      You have freedom to copy and modify this GNU Manual, like GNU
      software.  Copies published by the Free Software Foundation raise
      funds for GNU development.-->
 <meta http-equiv="Content-Style-Type" content="text/css">
 <style type="text/css"><!--
   pre.display { font-family:inherit }
   pre.format  { font-family:inherit }
   pre.smalldisplay { font-family:inherit; font-size:smaller }
   pre.smallformat  { font-family:inherit; font-size:smaller }
   pre.smallexample { font-size:smaller }
   pre.smalllisp    { font-size:smaller }
   span.sc    { font-variant:small-caps }
   span.roman { font-family:serif; font-weight:normal; }
   span.sansserif { font-family:sans-serif; font-weight:normal; }
 --></style>
 <link rel="stylesheet" type="text/css" href="../cs.css">
 </head>
 <body>
 <div class="node">
 <a name="ARM-NEON-Intrinsics"></a>
 <p>
 Next:&nbsp;<a rel="next" accesskey="n" href="Blackfin-Built_002din-Functions.html#Blackfin-Built_002din-Functions">Blackfin Built-in Functions</a>,
 Previous:&nbsp;<a rel="previous" accesskey="p" href="ARM-iWMMXt-Built_002din-Functions.html#ARM-iWMMXt-Built_002din-Functions">ARM iWMMXt Built-in Functions</a>,
 Up:&nbsp;<a rel="up" accesskey="u" href="Target-Builtins.html#Target-Builtins">Target Builtins</a>
 <hr>
 </div>

 <h4 class="subsection">6.52.3 ARM NEON Intrinsics</h4>

 <p>These built-in intrinsics for the ARM Advanced SIMD extension are available
 when the <samp><span class="option">-mfpu=neon</span></samp> switch is used:

 <!-- Copyright (C) 2006 Free Software Foundation, Inc. -->
 <!-- This is part of the GCC manual. -->
 <!-- For copying conditions, see the file gcc.texi. -->
 <!-- This file is generated automatically using gcc/config/arm/neon-docgen.ml -->
 <!-- Please do not edit manually. -->
 <h5 class="subsubsection">6.52.3.1 Addition</h5>

      <ul>
 <li>uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vadd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vadd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vadd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vadd_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vadd_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vadd.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddw.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vhadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrhadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqadd.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vraddhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.2 Multiplication</h5>

      <ul>
 <li>uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmul_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmul_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmul_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vmul_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.p8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.p8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vmull_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vmull_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vmull_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.p8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.3 Multiply-accumulate</h5>

      <ul>
 <li>uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.4 Multiply-subtract</h5>

      <ul>
 <li>uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.5 Subtraction</h5>

      <ul>
 <li>uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vsub_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vsub_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vsub_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vsub_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vsub_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsub.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubw.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vhsub.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqsub.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsubhn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.6 Comparison (equal-to)</h5>

      <ul>
 <li>uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vceq.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.7 Comparison (greater-than-or-equal-to)</h5>

      <ul>
 <li>uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.8 Comparison (less-than-or-equal-to)</h5>

      <ul>
 <li>uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.9 Comparison (greater-than)</h5>

      <ul>
 <li>uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.10 Comparison (less-than)</h5>

      <ul>
 <li>uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.11 Comparison (absolute greater-than-or-equal-to)</h5>

      <ul>
 <li>uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.12 Comparison (absolute less-than-or-equal-to)</h5>

      <ul>
 <li>uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vacge.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.13 Comparison (absolute greater-than)</h5>

      <ul>
 <li>uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.14 Comparison (absolute less-than)</h5>

      <ul>
 <li>uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vacgt.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.15 Test bits</h5>

      <ul>
 <li>uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtst.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.16 Absolute difference</h5>

      <ul>
 <li>uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vabd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vabd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vabd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vabd_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabd.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabdl.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.17 Absolute difference and accumulate</h5>

      <ul>
 <li>uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vaba.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabal.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.18 Maximum</h5>

      <ul>
 <li>uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmax_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmax_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmax_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vmax_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmax.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.19 Minimum</h5>

      <ul>
 <li>uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmin_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmin_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmin_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vmin_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vminq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vminq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vminq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vminq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmin.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.20 Pairwise add</h5>

      <ul>
 <li>uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadd.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vpaddl_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vpaddl_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vpaddl_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vpaddl_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vpaddl_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vpaddl_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x2_t vpaddlq_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vpaddlq_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vpaddlq_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.u8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vpaddlq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vpaddlq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vpaddlq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vpaddl.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.21 Pairwise add, single_opcode widen and accumulate</h5>

      <ul>
 <li>uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.u8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vpadal.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.22 Folding maximum</h5>

      <ul>
 <li>uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmax.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.23 Folding minimum</h5>

      <ul>
 <li>uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vpmin.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.24 Reciprocal step</h5>

      <ul>
 <li>float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecps.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecps.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrts.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrts.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.25 Vector shift left</h5>

      <ul>
 <li>uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vshl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vshl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vshl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vshl_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.26 Vector shift left by constant</h5>

      <ul>
 <li>uint32x2_t vshl_n_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vshl_n_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vshl_n_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vshl_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vshl_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vshl_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vshl_n_u64 (uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vshl_n_s64 (int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vshlq_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vshlq_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vshlq_n_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vshlq_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshl.i64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vqshl_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vqshl_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vqshl_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vqshl_n_s64 (int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vqshlq_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vqshlq_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vqshlq_n_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vqshlq_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshl.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshlu.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vshll_n_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vshll_n_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vshll_n_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.u8 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vshll_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vshll_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vshll_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshll.s8 </code><var>q0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.27 Vector shift right by constant</h5>

      <ul>
 <li>uint32x2_t vshr_n_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vshr_n_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vshr_n_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vshr_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vshr_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vshr_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vshr_n_u64 (uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vshr_n_s64 (int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vshrq_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vshrq_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vshrq_n_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vshrq_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshr.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vrshr_n_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vrshr_n_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vrshr_n_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vrshr_n_s64 (int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vrshrq_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vrshrq_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vrshrq_n_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vrshrq_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshr.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vshrn_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vshrn_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vshrn_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vrshrn_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vrshrn_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vrshrn_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrshrn.i16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.u64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.u32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.u16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vqshrn_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vqshrn_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vqshrn_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrn.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.u64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.u32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.u16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrn.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrun.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrun.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqshrun.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrun.s64 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrun.s32 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrshrun.s16 </code><var>d0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.28 Vector shift right by constant and accumulate</h5>

      <ul>
 <li>uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsra.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.u64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vrsra.s64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.29 Vector shift right and insert</h5>

      <ul>
 <li>uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsri.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.30 Vector shift left and insert</h5>

      <ul>
 <li>uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.64 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.16 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vsli.8 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.31 Absolute value</h5>

      <ul>
 <li>float32x2_t vabs_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vabs_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vabs_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vabs_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vabsq_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vabsq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vabsq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vabsq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vabs.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vqabs_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqabs_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqabs_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqabsq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqabsq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqabsq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqabs.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.32 Negation</h5>

      <ul>
 <li>float32x2_t vneg_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vneg_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vneg_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vneg_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vnegq_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vnegq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vnegq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vnegq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vneg.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vqneg_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vqneg_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vqneg_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vqnegq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vqnegq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vqnegq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqneg.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.33 Bitwise not</h5>

      <ul>
 <li>uint32x2_t vmvn_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmvn_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmvn_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vmvn_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vmvn_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vmvn_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vmvn_p8 (poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmvnq_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmvnq_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmvnq_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vmvnq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vmvnq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vmvnq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vmvnq_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmvn </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.34 Count leading sign bits</h5>

      <ul>
 <li>int32x2_t vcls_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vcls_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vcls_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vclsq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vclsq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vclsq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcls.s8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.35 Count leading zeros</h5>

      <ul>
 <li>uint32x2_t vclz_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vclz_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vclz_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vclz_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vclz_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vclz_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vclzq_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vclzq_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vclzq_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vclzq_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vclzq_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vclzq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vclz.i8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.36 Count number of set bits</h5>

      <ul>
 <li>uint8x8_t vcnt_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vcnt_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vcnt_p8 (poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x16_t vcntq_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vcntq_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vcntq_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vcnt.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.37 Reciprocal estimate</h5>

      <ul>
 <li>float32x2_t vrecpe_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecpe.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrecpe_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecpe.u32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vrecpeq_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecpe.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrecpeq_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrecpe.u32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.38 Reciprocal square-root estimate</h5>

      <ul>
 <li>float32x2_t vrsqrte_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrte.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vrsqrte_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrte.u32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vrsqrteq_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrte.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrsqrteq_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrsqrte.u32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.39 Get lanes from a vector</h5>

      <ul>
 <li>uint32_t vget_lane_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16_t vget_lane_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8_t vget_lane_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32_t vget_lane_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16_t vget_lane_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.s16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int8_t vget_lane_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.s8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32_t vget_lane_f32 (float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16_t vget_lane_p16 (poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8_t vget_lane_p8 (poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64_t vget_lane_u64 (uint64x1_t, const int)
 </ul>

      <ul>
 <li>int64_t vget_lane_s64 (int64x1_t, const int)
 </ul>

      <ul>
 <li>uint32_t vgetq_lane_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16_t vgetq_lane_u16 (uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8_t vgetq_lane_u8 (uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32_t vgetq_lane_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16_t vgetq_lane_s16 (int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.s16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int8_t vgetq_lane_s8 (int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.s8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32_t vgetq_lane_f32 (float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16_t vgetq_lane_p16 (poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u16 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8_t vgetq_lane_p8 (poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.u8 </code><var>r0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64_t vgetq_lane_u64 (uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>r0</var><code>, </code><var>r0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64_t vgetq_lane_s64 (int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>r0</var><code>, </code><var>r0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.40 Set lanes in a vector</h5>

      <ul>
 <li>uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
 </ul>

      <ul>
 <li>int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
 </ul>

      <ul>
 <li>uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.32 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.16 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov.8 </code><var>d0</var><code>[</code><var>0</var><code>], </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>r0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>r0</var><code>, </code><var>r0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.41 Create vector from literal bit pattern</h5>

      <ul>
 <li>uint32x2_t vcreate_u32 (uint64_t)
 </ul>

      <ul>
 <li>uint16x4_t vcreate_u16 (uint64_t)
 </ul>

      <ul>
 <li>uint8x8_t vcreate_u8 (uint64_t)
 </ul>

      <ul>
 <li>int32x2_t vcreate_s32 (uint64_t)
 </ul>

      <ul>
 <li>int16x4_t vcreate_s16 (uint64_t)
 </ul>

      <ul>
 <li>int8x8_t vcreate_s8 (uint64_t)
 </ul>

      <ul>
 <li>uint64x1_t vcreate_u64 (uint64_t)
 </ul>

      <ul>
 <li>int64x1_t vcreate_s64 (uint64_t)
 </ul>

      <ul>
 <li>float32x2_t vcreate_f32 (uint64_t)
 </ul>

      <ul>
 <li>poly16x4_t vcreate_p16 (uint64_t)
 </ul>

      <ul>
 <li>poly8x8_t vcreate_p8 (uint64_t)
 </ul>

 <h5 class="subsubsection">6.52.3.42 Set all lanes to the same value</h5>

      <ul>
 <li>uint32x2_t vdup_n_u32 (uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x4_t vdup_n_u16 (uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x8_t vdup_n_u8 (uint8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x2_t vdup_n_s32 (int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x4_t vdup_n_s16 (int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x8_t vdup_n_s8 (int8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x2_t vdup_n_f32 (float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x4_t vdup_n_p16 (poly16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x8_t vdup_n_p8 (poly8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x1_t vdup_n_u64 (uint64_t)
 </ul>

      <ul>
 <li>int64x1_t vdup_n_s64 (int64_t)
 </ul>

      <ul>
 <li>uint32x4_t vdupq_n_u32 (uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x8_t vdupq_n_u16 (uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x16_t vdupq_n_u8 (uint8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x4_t vdupq_n_s32 (int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x8_t vdupq_n_s16 (int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x16_t vdupq_n_s8 (int8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x4_t vdupq_n_f32 (float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x8_t vdupq_n_p16 (poly16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x16_t vdupq_n_p8 (poly8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x2_t vdupq_n_u64 (uint64_t)
 </ul>

      <ul>
 <li>int64x2_t vdupq_n_s64 (int64_t)
 </ul>

      <ul>
 <li>uint32x2_t vmov_n_u32 (uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmov_n_u16 (uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmov_n_u8 (uint8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x2_t vmov_n_s32 (int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x4_t vmov_n_s16 (int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x8_t vmov_n_s8 (int8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x2_t vmov_n_f32 (float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x4_t vmov_n_p16 (poly16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x8_t vmov_n_p8 (poly8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x1_t vmov_n_u64 (uint64_t)
 </ul>

      <ul>
 <li>int64x1_t vmov_n_s64 (int64_t)
 </ul>

      <ul>
 <li>uint32x4_t vmovq_n_u32 (uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmovq_n_u16 (uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint8x16_t vmovq_n_u8 (uint8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int32x4_t vmovq_n_s32 (int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int16x8_t vmovq_n_s16 (int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>int8x16_t vmovq_n_s8 (int8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>float32x4_t vmovq_n_f32 (float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly16x8_t vmovq_n_p16 (poly16_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>poly8x16_t vmovq_n_p8 (poly8_t)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>r0</var>
 </ul>

      <ul>
 <li>uint64x2_t vmovq_n_u64 (uint64_t)
 </ul>

      <ul>
 <li>int64x2_t vmovq_n_s64 (int64_t)
 </ul>

      <ul>
 <li>uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vdup_lane_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vdup_lane_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8_t vdup_lane_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2_t vdup_lane_f32 (float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
 </ul>

      <ul>
 <li>int64x1_t vdup_lane_s64 (int64x1_t, const int)
 </ul>

      <ul>
 <li>uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vdupq_lane_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vdupq_lane_s16 (int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16_t vdupq_lane_s8 (int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vdupq_lane_f32 (float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.32 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.16 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vdup.8 </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
 </ul>

      <ul>
 <li>int64x2_t vdupq_lane_s64 (int64x1_t, const int)
 </ul>

 <h5 class="subsubsection">6.52.3.43 Combining vectors</h5>

      <ul>
 <li>uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
 </ul>

      <ul>
 <li>uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
 </ul>

      <ul>
 <li>uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
 </ul>

      <ul>
 <li>int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
 </ul>

      <ul>
 <li>int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
 </ul>

      <ul>
 <li>int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
 </ul>

      <ul>
 <li>uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
 </ul>

      <ul>
 <li>poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
 </ul>

      <ul>
 <li>poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
 </ul>

 <h5 class="subsubsection">6.52.3.44 Splitting vectors</h5>

      <ul>
 <li>uint32x2_t vget_high_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>uint16x4_t vget_high_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>uint8x8_t vget_high_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>int32x2_t vget_high_s32 (int32x4_t)
 </ul>

      <ul>
 <li>int16x4_t vget_high_s16 (int16x8_t)
 </ul>

      <ul>
 <li>int8x8_t vget_high_s8 (int8x16_t)
 </ul>

      <ul>
 <li>uint64x1_t vget_high_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int64x1_t vget_high_s64 (int64x2_t)
 </ul>

      <ul>
 <li>float32x2_t vget_high_f32 (float32x4_t)
 </ul>

      <ul>
 <li>poly16x4_t vget_high_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>poly8x8_t vget_high_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>uint32x2_t vget_low_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vget_low_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vget_low_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vget_low_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vget_low_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vget_low_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vget_low_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly16x4_t vget_low_p16 (poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vget_low_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmov </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vget_low_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int64x1_t vget_low_s64 (int64x2_t)
 </ul>

 <h5 class="subsubsection">6.52.3.45 Conversions</h5>

      <ul>
 <li>float32x2_t vcvt_f32_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vcvt_f32_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcvt_u32_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vcvt_s32_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x4_t vcvtq_f32_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vcvtq_f32_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcvtq_u32_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vcvtq_s32_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.u32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.f32.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.u32.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vcvt.s32.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.46 Move, single_opcode narrowing</h5>

      <ul>
 <li>uint32x2_t vmovn_u64 (uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i64 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vmovn_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i32 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vmovn_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i16 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vmovn_s64 (int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i64 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vmovn_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i32 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vmovn_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovn.i16 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqmovn_u64 (uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.u64 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqmovn_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.u32 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqmovn_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.u16 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x2_t vqmovn_s64 (int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.s64 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x4_t vqmovn_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.s32 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x8_t vqmovn_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovn.s16 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint32x2_t vqmovun_s64 (int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovun.s64 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vqmovun_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovun.s32 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vqmovun_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vqmovun.s16 </code><var>d0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.47 Move, single_opcode long</h5>

      <ul>
 <li>uint64x2_t vmovl_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.u32 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vmovl_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.u16 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vmovl_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.u8 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x2_t vmovl_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.s32 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x4_t vmovl_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.s16 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x8_t vmovl_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vmovl.s8 </code><var>q0</var><code>, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.48 Table lookup</h5>

      <ul>
 <li>poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbl.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.49 Extended table lookup</h5>

      <ul>
 <li>poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtbx.8 </code><var>d0</var><code>, {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, </code><var>d0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.50 Multiply, lane</h5>

      <ul>
 <li>float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.51 Long multiply, lane</h5>

      <ul>
 <li>uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.52 Saturating doubling long multiply, lane</h5>

      <ul>
 <li>int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.53 Saturating doubling multiply high, lane</h5>

      <ul>
 <li>int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.54 Multiply-accumulate, lane</h5>

      <ul>
 <li>float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.55 Multiply-subtract, lane</h5>

      <ul>
 <li>float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.56 Vector multiply by scalar</h5>

      <ul>
 <li>float32x2_t vmul_n_f32 (float32x2_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmul_n_s32 (int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmul_n_s16 (int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmul.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.57 Vector long multiply by scalar</h5>

      <ul>
 <li>uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmull_n_s32 (int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmull_n_s16 (int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.58 Vector saturating doubling long multiply by scalar</h5>

      <ul>
 <li>int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmull.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.59 Vector saturating doubling multiply high by scalar</h5>

      <ul>
 <li>int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqrdmulh.s16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.60 Vector multiply-accumulate by scalar</h5>

      <ul>
 <li>float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmla.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlal.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.61 Vector multiply-subtract by scalar</h5>

      <ul>
 <li>float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.f32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmls.i16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.u16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s32 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
 <br><em>Form of expected instruction(s):</em> <code>vqdmlsl.s16 </code><var>q0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>[</code><var>0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.62 Vector extract</h5>

      <ul>
 <li>uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.64 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.32 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.16 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

      <ul>
 <li>poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vext.8 </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var><code>, #</code><var>0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.63 Reverse elements</h5>

      <ul>
 <li>uint32x2_t vrev64_u32 (uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrev64_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrev64_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vrev64_s32 (int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vrev64_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vrev64_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vrev64_f32 (float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly16x4_t vrev64_p16 (poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vrev64_p8 (poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vrev64q_u32 (uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrev64q_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrev64q_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vrev64q_s32 (int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vrev64q_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vrev64q_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vrev64q_f32 (float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.32 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly16x8_t vrev64q_p16 (poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vrev64q_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev64.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x4_t vrev32_u16 (uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vrev32_s16 (int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrev32_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vrev32_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly16x4_t vrev32_p16 (poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vrev32_p8 (poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x8_t vrev32q_u16 (uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vrev32q_s16 (int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrev32q_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vrev32q_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly16x8_t vrev32q_p16 (poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.16 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vrev32q_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev32.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x8_t vrev16_u8 (uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vrev16_s8 (int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vrev16_p8 (poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x16_t vrev16q_u8 (uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vrev16q_s8 (int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vrev16q_p8 (poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vrev16.8 </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.64 Bit selection</h5>

      <ul>
 <li>uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbit </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var> <em>or</em> <code>vbif </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vbsl </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbit </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var> <em>or</em> <code>vbif </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.65 Transpose elements</h5>

      <ul>
 <li>uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vtrn.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

 <h5 class="subsubsection">6.52.3.66 Zip elements</h5>

      <ul>
 <li>uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vzip.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

 <h5 class="subsubsection">6.52.3.67 Unzip elements</h5>

      <ul>
 <li>uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>d0</var><code>, </code><var>d1</var>
 </ul>

      <ul>
 <li>uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.32 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.16 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

      <ul>
 <li>poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vuzp.8 </code><var>q0</var><code>, </code><var>q1</var>
 </ul>

 <h5 class="subsubsection">6.52.3.68 Element/structure loads, VLD1 variants</h5>

      <ul>
 <li>uint32x2_t vld1_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vld1_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8_t vld1_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vld1_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vld1_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8_t vld1_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1_t vld1_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1_t vld1_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2_t vld1_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4_t vld1_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8_t vld1_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vld1q_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vld1q_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16_t vld1q_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vld1q_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vld1q_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16_t vld1q_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vld1q_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vld1q_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vld1q_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8_t vld1q_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16_t vld1q_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2_t vld1_dup_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4_t vld1_dup_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8_t vld1_dup_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2_t vld1_dup_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4_t vld1_dup_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8_t vld1_dup_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2_t vld1_dup_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4_t vld1_dup_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8_t vld1_dup_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1_t vld1_dup_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1_t vld1_dup_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4_t vld1q_dup_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8_t vld1q_dup_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16_t vld1q_dup_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4_t vld1q_dup_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8_t vld1q_dup_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16_t vld1q_dup_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4_t vld1q_dup_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8_t vld1q_dup_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16_t vld1q_dup_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x2_t vld1q_dup_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x2_t vld1q_dup_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.69 Element/structure stores, VST1 variants</h5>

      <ul>
 <li>void vst1_u32 (uint32_t *, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_u16 (uint16_t *, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_u8 (uint8_t *, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_s32 (int32_t *, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_s16 (int16_t *, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_s8 (int8_t *, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_u64 (uint64_t *, uint64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_s64 (int64_t *, int64x1_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_f32 (float32_t *, float32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_p16 (poly16_t *, poly16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_p8 (poly8_t *, poly8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_u32 (uint32_t *, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_u16 (uint16_t *, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_u8 (uint8_t *, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_s32 (int32_t *, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_s16 (int16_t *, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_s8 (int8_t *, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_u64 (uint64_t *, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_s64 (int64_t *, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_f32 (float32_t *, float32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_p16 (poly16_t *, poly16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_p8 (poly8_t *, poly8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_s32 (int32_t *, int32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_s16 (int16_t *, int16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_s8 (int8_t *, int8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_f32 (float32_t *, float32x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_s64 (int64_t *, int64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.32 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.16 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.8 {</code><var>d0</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.70 Element/structure loads, VLD2 variants</h5>

      <ul>
 <li>uint32x2x2_t vld2_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x2_t vld2_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x2_t vld2_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x2_t vld2_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x2_t vld2_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x2_t vld2_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x2_t vld2_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x2_t vld2_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x2_t vld2_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x2_t vld2_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x2_t vld2_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x2_t vld2q_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x2_t vld2q_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16x2_t vld2q_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x2_t vld2q_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x2_t vld2q_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16x2_t vld2q_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x2_t vld2q_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x2_t vld2q_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16x2_t vld2q_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x2_t vld2_dup_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x2_t vld2_dup_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x2_t vld2_dup_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x2_t vld2_dup_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x2_t vld2_dup_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x2_t vld2_dup_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x2_t vld2_dup_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x2_t vld2_dup_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x2_t vld2_dup_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld2.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x2_t vld2_dup_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x2_t vld2_dup_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.71 Element/structure stores, VST2 variants</h5>

      <ul>
 <li>void vst2_u32 (uint32_t *, uint32x2x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_u16 (uint16_t *, uint16x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_u8 (uint8_t *, uint8x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_s32 (int32_t *, int32x2x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_s16 (int16_t *, int16x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_s8 (int8_t *, int8x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_f32 (float32_t *, float32x2x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_p16 (poly16_t *, poly16x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_p8 (poly8_t *, poly8x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_u64 (uint64_t *, uint64x1x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_s64 (int64_t *, int64x1x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_u32 (uint32_t *, uint32x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_u16 (uint16_t *, uint16x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_u8 (uint8_t *, uint8x16x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_s32 (int32_t *, int32x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_s16 (int16_t *, int16x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_s8 (int8_t *, int8x16x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_f32 (float32_t *, float32x4x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_p16 (poly16_t *, poly16x8x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_p8 (poly8_t *, poly8x16x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>, </code><var>d1</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst2.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.72 Element/structure loads, VLD3 variants</h5>

      <ul>
 <li>uint32x2x3_t vld3_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x3_t vld3_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x3_t vld3_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x3_t vld3_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x3_t vld3_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x3_t vld3_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x3_t vld3_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x3_t vld3_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x3_t vld3_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x3_t vld3_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x3_t vld3_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x3_t vld3q_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x3_t vld3q_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16x3_t vld3q_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x3_t vld3q_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x3_t vld3q_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16x3_t vld3q_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x3_t vld3q_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x3_t vld3q_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16x3_t vld3q_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x3_t vld3_dup_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x3_t vld3_dup_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x3_t vld3_dup_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x3_t vld3_dup_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x3_t vld3_dup_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x3_t vld3_dup_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x3_t vld3_dup_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x3_t vld3_dup_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x3_t vld3_dup_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld3.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x3_t vld3_dup_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x3_t vld3_dup_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.73 Element/structure stores, VST3 variants</h5>

      <ul>
 <li>void vst3_u32 (uint32_t *, uint32x2x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_u16 (uint16_t *, uint16x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_u8 (uint8_t *, uint8x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_s32 (int32_t *, int32x2x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_s16 (int16_t *, int16x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_s8 (int8_t *, int8x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_f32 (float32_t *, float32x2x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_p16 (poly16_t *, poly16x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_p8 (poly8_t *, poly8x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_u64 (uint64_t *, uint64x1x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_s64 (int64_t *, int64x1x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_u32 (uint32_t *, uint32x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_u16 (uint16_t *, uint16x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_u8 (uint8_t *, uint8x16x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_s32 (int32_t *, int32x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_s16 (int16_t *, int16x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_s8 (int8_t *, int8x16x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_f32 (float32_t *, float32x4x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_p16 (poly16_t *, poly16x8x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_p8 (poly8_t *, poly8x16x3_t)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst3.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.74 Element/structure loads, VLD4 variants</h5>

      <ul>
 <li>uint32x2x4_t vld4_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x4_t vld4_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x4_t vld4_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x4_t vld4_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x4_t vld4_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x4_t vld4_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x4_t vld4_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x4_t vld4_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x4_t vld4_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x4_t vld4_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x4_t vld4_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x4_t vld4q_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x4_t vld4q_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x16x4_t vld4q_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x4_t vld4q_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x4_t vld4q_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x16x4_t vld4q_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x4_t vld4q_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x4_t vld4q_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x16x4_t vld4q_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint32x2x4_t vld4_dup_u32 (const uint32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint16x4x4_t vld4_dup_u16 (const uint16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint8x8x4_t vld4_dup_u8 (const uint8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int32x2x4_t vld4_dup_s32 (const int32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int16x4x4_t vld4_dup_s16 (const int16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int8x8x4_t vld4_dup_s8 (const int8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>float32x2x4_t vld4_dup_f32 (const float32_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.32 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly16x4x4_t vld4_dup_p16 (const poly16_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.16 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>poly8x8x4_t vld4_dup_p8 (const poly8_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld4.8 {</code><var>d0</var><code>[], </code><var>d1</var><code>[], </code><var>d2</var><code>[], </code><var>d3</var><code>[]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>uint64x1x4_t vld4_dup_u64 (const uint64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>int64x1x4_t vld4_dup_s64 (const int64_t *)
 <br><em>Form of expected instruction(s):</em> <code>vld1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.75 Element/structure stores, VST4 variants</h5>

      <ul>
 <li>void vst4_u32 (uint32_t *, uint32x2x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_u16 (uint16_t *, uint16x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_u8 (uint8_t *, uint8x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_s32 (int32_t *, int32x2x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_s16 (int16_t *, int16x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_s8 (int8_t *, int8x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_f32 (float32_t *, float32x2x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_p16 (poly16_t *, poly16x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_p8 (poly8_t *, poly8x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_u64 (uint64_t *, uint64x1x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_s64 (int64_t *, int64x1x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst1.64 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_u32 (uint32_t *, uint32x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_u16 (uint16_t *, uint16x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_u8 (uint8_t *, uint8x16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_s32 (int32_t *, int32x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_s16 (int16_t *, int16x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_s8 (int8_t *, int8x16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_f32 (float32_t *, float32x4x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_p16 (poly16_t *, poly16x8x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_p8 (poly8_t *, poly8x16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>, </code><var>d1</var><code>, </code><var>d2</var><code>, </code><var>d3</var><code>}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.8 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.32 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

      <ul>
 <li>void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
 <br><em>Form of expected instruction(s):</em> <code>vst4.16 {</code><var>d0</var><code>[</code><var>0</var><code>], </code><var>d1</var><code>[</code><var>0</var><code>], </code><var>d2</var><code>[</code><var>0</var><code>], </code><var>d3</var><code>[</code><var>0</var><code>]}, [</code><var>r0</var><code>]</code>
 </ul>

 <h5 class="subsubsection">6.52.3.76 Logical operations (AND)</h5>

      <ul>
 <li>uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vand_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vand_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vand_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vand_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vandq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vandq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vandq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vandq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vand </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.77 Logical operations (OR)</h5>

      <ul>
 <li>uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vorr_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vorr_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vorr_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vorr_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorr </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.78 Logical operations (exclusive OR)</h5>

      <ul>
 <li>uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t veor_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t veor_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t veor_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t veor_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t veorq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t veorq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t veorq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t veorq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>veor </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.79 Logical operations (AND-NOT)</h5>

      <ul>
 <li>uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vbic_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vbic_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vbic_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vbic_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vbic </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.80 Logical operations (OR-NOT)</h5>

      <ul>
 <li>uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int32x2_t vorn_s32 (int32x2_t, int32x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int16x4_t vorn_s16 (int16x4_t, int16x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>int8x8_t vorn_s8 (int8x8_t, int8x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>d0</var><code>, </code><var>d0</var><code>, </code><var>d0</var>
 </ul>

      <ul>
 <li>uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vorn_s64 (int64x1_t, int64x1_t)
 </ul>

      <ul>
 <li>uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int32x4_t vornq_s32 (int32x4_t, int32x4_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int16x8_t vornq_s16 (int16x8_t, int16x8_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int8x16_t vornq_s8 (int8x16_t, int8x16_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

      <ul>
 <li>int64x2_t vornq_s64 (int64x2_t, int64x2_t)
 <br><em>Form of expected instruction(s):</em> <code>vorn </code><var>q0</var><code>, </code><var>q0</var><code>, </code><var>q0</var>
 </ul>

 <h5 class="subsubsection">6.52.3.81 Reinterpret casts</h5>

      <ul>
 <li>poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_s32 (int32x2_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_s16 (int16x4_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_s8 (int8x8_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_s64 (int64x1_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_f32 (float32x2_t)
 </ul>

      <ul>
 <li>poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
 </ul>

      <ul>
 <li>poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_s32 (int32x2_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_s16 (int16x4_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_s8 (int8x8_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_s64 (int64x1_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_f32 (float32x2_t)
 </ul>

      <ul>
 <li>poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
 </ul>

      <ul>
 <li>poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_s32 (int32x2_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_s16 (int16x4_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_s8 (int8x8_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_s64 (int64x1_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>float32x2_t vreinterpret_f32_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_s32 (int32x4_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_s16 (int16x8_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_s8 (int8x16_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_s64 (int64x2_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_s32 (int32x2_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_s16 (int16x4_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_s8 (int8x8_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_f32 (float32x2_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>int64x1_t vreinterpret_s64_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_s32 (int32x4_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_s16 (int16x8_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_s8 (int8x16_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_f32 (float32x4_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_s32 (int32x2_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_s16 (int16x4_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_s8 (int8x8_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_s64 (int64x1_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_f32 (float32x2_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_s32 (int32x2_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_s16 (int16x4_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_s64 (int64x1_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_f32 (float32x2_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>int8x8_t vreinterpret_s8_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_s32 (int32x4_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_s16 (int16x8_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_s64 (int64x2_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_f32 (float32x4_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_s32 (int32x2_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_s8 (int8x8_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_s64 (int64x1_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_f32 (float32x2_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>int16x4_t vreinterpret_s16_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_s32 (int32x4_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_s8 (int8x16_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_s64 (int64x2_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_f32 (float32x4_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_s16 (int16x4_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_s8 (int8x8_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_s64 (int64x1_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_f32 (float32x2_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>int32x2_t vreinterpret_s32_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_s16 (int16x8_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_s8 (int8x16_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_s64 (int64x2_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_f32 (float32x4_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_s32 (int32x2_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_s16 (int16x4_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_s8 (int8x8_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_s64 (int64x1_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_f32 (float32x2_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_s32 (int32x2_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_s16 (int16x4_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_s8 (int8x8_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_s64 (int64x1_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_f32 (float32x2_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_s32 (int32x2_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_s16 (int16x4_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_s8 (int8x8_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_s64 (int64x1_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_f32 (float32x2_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
 </ul>

      <ul>
 <li>uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
 </ul>

      <ul>
 <li>uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
 </ul>

  </body></html>