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<h3 class="section">D.6 Architecture-Specific Protocol Details</h3>
<p>This section describes how the remote protocol is applied to specific
target architectures. Also see <a href="Standard-Target-Features.html#Standard-Target-Features">Standard Target Features</a>, for
details of XML target descriptions for each architecture.
<h4 class="subsection">D.6.1 ARM</h4>
<h5 class="subsubsection">D.6.1.1 Breakpoint Kinds</h5>
<p>These breakpoint kinds are defined for the &lsquo;<samp><span class="samp">Z0</span></samp>&rsquo; and &lsquo;<samp><span class="samp">Z1</span></samp>&rsquo; packets.
<dl>
<dt><span class="roman">2</span><dd>16-bit Thumb mode breakpoint.
<br><dt><span class="roman">3</span><dd>32-bit Thumb mode (Thumb-2) breakpoint.
<br><dt><span class="roman">4</span><dd>32-bit ARM mode breakpoint.
</dl>
<h4 class="subsection">D.6.2 MIPS</h4>
<h5 class="subsubsection">D.6.2.1 Register Packet Format</h5>
<p>The following <code>g</code>/<code>G</code> packets have previously been defined.
In the below, some thirty-two bit registers are transferred as
sixty-four bits. Those registers should be zero/sign extended (which?)
to fill the space allocated. Register bytes are transferred in target
byte order. The two nibbles within a register byte are transferred
most-significant - least-significant.
<dl>
<dt><span class="roman">MIPS32</span><dd>
All registers are transferred as thirty-two bit quantities in the order:
32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point
registers; fsr; fir; fp.
<br><dt><span class="roman">MIPS64</span><dd>
All registers are transferred as sixty-four bit quantities (including
thirty-two bit registers such as <code>sr</code>). The ordering is the same
as <code>MIPS32</code>.
</dl>
<h5 class="subsubsection">D.6.2.2 Breakpoint Kinds</h5>
<p>These breakpoint kinds are defined for the &lsquo;<samp><span class="samp">Z0</span></samp>&rsquo; and &lsquo;<samp><span class="samp">Z1</span></samp>&rsquo; packets.
<dl>
<dt><span class="roman">2</span><dd>16-bit MIPS16 mode breakpoint.
<br><dt><span class="roman">3</span><dd>16-bit microMIPS mode breakpoint.
<br><dt><span class="roman">4</span><dd>32-bit standard MIPS mode breakpoint.
<br><dt><span class="roman">5</span><dd>32-bit microMIPS mode breakpoint.
</dl>
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