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| Previous: <a rel="previous" accesskey="p" href="M68K-Features.html#M68K-Features">M68K Features</a>, |
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| <h4 class="subsection">G.4.5 PowerPC Features</h4> |
| |
| <p><a name="index-target-descriptions_002c-PowerPC-features-2558"></a> |
| The ‘<samp><span class="samp">org.gnu.gdb.power.core</span></samp>’ feature is required for PowerPC |
| targets. It should contain registers ‘<samp><span class="samp">r0</span></samp>’ through ‘<samp><span class="samp">r31</span></samp>’, |
| ‘<samp><span class="samp">pc</span></samp>’, ‘<samp><span class="samp">msr</span></samp>’, ‘<samp><span class="samp">cr</span></samp>’, ‘<samp><span class="samp">lr</span></samp>’, ‘<samp><span class="samp">ctr</span></samp>’, and |
| ‘<samp><span class="samp">xer</span></samp>’. They may be 32-bit or 64-bit depending on the target. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.fpu</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">f0</span></samp>’ through ‘<samp><span class="samp">f31</span></samp>’ and ‘<samp><span class="samp">fpscr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.altivec</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">vr0</span></samp>’ through ‘<samp><span class="samp">vr31</span></samp>’, ‘<samp><span class="samp">vscr</span></samp>’, |
| and ‘<samp><span class="samp">vrsave</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.vsx</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">vs0h</span></samp>’ through ‘<samp><span class="samp">vs31h</span></samp>’. <span class="sc">gdb</span> |
| will combine these registers with the floating point registers |
| (‘<samp><span class="samp">f0</span></samp>’ through ‘<samp><span class="samp">f31</span></samp>’) and the altivec registers (‘<samp><span class="samp">vr0</span></samp>’ |
| through ‘<samp><span class="samp">vr31</span></samp>’) to present the 128-bit wide registers ‘<samp><span class="samp">vs0</span></samp>’ |
| through ‘<samp><span class="samp">vs63</span></samp>’, the set of vector registers for POWER7. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.spe</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">ev0h</span></samp>’ through ‘<samp><span class="samp">ev31h</span></samp>’, ‘<samp><span class="samp">acc</span></samp>’, and |
| ‘<samp><span class="samp">spefscr</span></samp>’. SPE targets should provide 32-bit registers in |
| ‘<samp><span class="samp">org.gnu.gdb.power.core</span></samp>’ and provide the upper halves in |
| ‘<samp><span class="samp">ev0h</span></samp>’ through ‘<samp><span class="samp">ev31h</span></samp>’. <span class="sc">gdb</span> will combine |
| these to present registers ‘<samp><span class="samp">ev0</span></samp>’ through ‘<samp><span class="samp">ev31</span></samp>’ to the |
| user. |
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