blob: 90be7bd8d041ab43c7eaa519daae56d5b8c44b09 [file] [log] [blame]
/* 4 instruction cycles not accessing cache and TLB are needed after
trapa instruction to avoid an SH-4 silicon bug. */
#define NEED_SYSCALL_INST_PAD
#include_next <lowlevellock.h>