blob: 852f8eed7f3f117a44986a933db1aebb6c206ca0 [file] [log] [blame]
/* 4 instruction cycles not accessing cache and TLB are needed after
trapa instruction to avoid an SH-4 silicon bug. */
#define NEED_SYSCALL_INST_PAD
#include <sysdeps/unix/sysv/linux/sh/sysdep.h>