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nest-open-source / nest-connect / 1.1 / freertos / 7c90e6690c237a358ec83144e0260be7bf66372a / . / FreeRTOS / Demo / CORTEX_SmartFusion2_M2S050_SoftConsole / LiberoOutput / DevelopmentKit_hardware / DEV_KIT_DEMO_top_DataSheet.xml
blob: fafb6c2e7840f3cfc7b6f7c00d98b268952c6672 [file] [log] [blame]
<?xml version="1.0" encoding="ISO-8859-1" ?>
<?xml-stylesheet type="text/xsl" href="datasheet.xsl"?>
<datasheet>
<header>DEV_KIT_DEMO_top</header>
<project-settings>
<fam>SmartFusion2</fam>
<die>M2S050T_ES</die>
<package>896 FBGA</package>
<speed-grade>-1</speed-grade>
<voltage>1.2</voltage>
<hdl-type>Verilog</hdl-type>
<project-description>
</project-description>
<location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_top</location>
<state>GENERATED ( Wed Apr 24 17:06:15 2013 )</state>
<swide-toolchain>SoftConsole workspace generated to D:\Actelprj\SF2_DEVKIT_DEMO\SoftConsole</swide-toolchain>
</project-settings>
<site-map>
</site-map>
<fileset>
<name>HDL File(s)</name>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\axi_interconnect.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\master_stage.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\COREAXI\2.0.103\rtl\vlog\core_obfuscated\slave_stage.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Config\2.0.100\rtl\vlog\core_obfuscated\coresf2config.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\DirectCore\CoreSF2Reset\1.0.101\rtl\vlog\core_obfuscated\coresf2reset.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\Actel\SgCore\OSC\1.0.100\osc_comps.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\CCC_0\DEV_KIT_DEMO_CCC_0_FCCC.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\COREAXI_0\rtl\vlog\core_obfuscated\coreaxi.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\DEV_KIT_DEMO.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO\FABOSC_0\DEV_KIT_DEMO_FABOSC_0_OSC.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_MSS\DEV_KIT_DEMO_MSS_tmp_syn.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\coreparameters_tgi.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\acmtable.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\coreabc.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\debugblk.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructions.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructnvm_bb.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\instructram.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\iram512x9_rtl.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram128x8_smartfusion2.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x16_rtl.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ram256x8_rtl.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\ramblocks.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\COREABC_0\rtl\vlog\core_obfuscated\support.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\DEV_KIT_DEMO_top.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF.v</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\DEV_KIT_DEMO_top\SERDES_IF_0\DEV_KIT_DEMO_top_SERDES_IF_0_SERDES_IF_syn.v</file>
</fileset>
<fileset>
<name>Flash Memory File(s)</name>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc</file>
<file>D:\Actelprj\SF2_DEVKIT_DEMO\component\work\./ENVM/ENVM.efc\D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO_MSS/ENVM/ENVM.efc</file>
</fileset>
<io>
<port-name>USB_ULPI_DATA[3]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[11]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>REFCLK0_P</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[3]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[15]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[10]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>I2C_0_SCL</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>SPI_0_DI</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[1]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD0_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[6]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD3_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[0]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_13_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[8]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>LED_6</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>FF_EXIT</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DIR</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD3_P</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[15]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[6]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_15_M2F</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[8]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>SPI_0_SS0</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD1_P</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_WE_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_CS_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_RESET_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD0_P</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[1]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[6]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MMUART_1_TXD_M2F</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS_N[1]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[9]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[0]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[13]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[5]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>LED_1</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>SPI_0_CLK</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_XCLK</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_RESET_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_4_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[7]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[3]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD1_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[1]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[14]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_STP</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS[1]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ODT</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD0_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD2_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[2]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_1_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>CLK0_PAD</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[12]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>SPI_0_DO</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[14]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_2_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[5]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DM_RDQS[1]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_BA[1]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS_TMATCH_0_IN</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_CLK_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[4]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_CAS_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_8_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS_N[0]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>I2C_1_SDA</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[11]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>DEVRST_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD1_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_BA[2]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_11_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD1_P</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DM_RDQS[0]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS_TMATCH_0_OUT</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_CKE</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MMUART_1_RXD_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQS[0]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_BA[0]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[5]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>I2C_0_SDA</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[13]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_CLK</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD2_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[4]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[12]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[4]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>I2C_1_SCL</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_RAS_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD3_N</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>REFCLK0_N</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_12_F2M</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[10]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_ADDR[2]</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD2_P</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[0]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD2_P</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[2]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_NXT</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>GPIO_14_M2F</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[7]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>MDDR_DQ[9]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>TXD3_P</port-name>
<direction>OUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>RXD0_P</port-name>
<direction>IN</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<io>
<port-name>USB_ULPI_DATA[7]</port-name>
<direction>INOUT</direction>
<pin-number>-</pin-number>
<io-standard>LVCMOS25</io-standard>
</io>
<core type="SpiritModule">
<core-exttype>IP</core-exttype>
<core-type>SpiritModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>DirectCore</core-lib>
<core-intname>COREABC</core-intname>
<core-ver>3.4.101</core-ver>
<core-desc>CoreABC (APB Bus Controller) is a simple, configurable, low gate count, programmable state machine/controller primarily targeted towards the implementation of AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) based designs. It is particularly suitable where:
- a programmable controller is required but a "full blown" CPU such as a Core8051s or Cortex-M1 is not needed or cannot be justified due to cost or resource/size constraints;
- a "full blown" CPU based system requires a CoreABC based programmable "offload engine/coprocessor" subsystem for performance reasons;
- an Actel Fusion system using, for example, CoreAI, CorePWM etc. requires programmable control either as a standalone design or as a Fusion analog "offload engine/coprocessor" for a larger CPU based system.
CoreABC is available through the Libero IDE IP Catalog through which it can be downloaded from a remote web based repository and installed into the user's local vault ready for use. It operates natively within the SmartDesign design entry environment allowing it to be easily instantiated, configured, connected to other IP core instances and generated ready for simulation, synthesis etc.
CoreABC is an AMBA3 APB master which can connect to and manage any APB slave peripherals via an AMBA3 APB bus fabric component such as CoreAPB3.
CoreABC supports a comprehensive assembler based configurable instruction set architecture and extensive and flexible configuration of size and feature options allowing it to be tuned to meet the resource constraints and processing power requirements of a wide variety of applications.
CoreABC supports three program storage modes:
- "Hard" mode: program image stored in an internal ROM implemented in FPGA fabric tiles;
- "Soft" mode: program image stored in Actel FPGA RAM blocks which are initialized at runtime from the binary image stored in Fusion NVM or an external flash memory;
- "NVM" mode (Fusion only): program image stored in and executed directly from Fusion NVM.
</core-desc>
<core-param>
<param-name>NVM with calibration data:</param-name>
<param-value>true</param-value>
<param-hdlname>ACT_CALIBRATIONDATA</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>APB Slot Size:</param-name>
<param-value>64k locations</param-value>
<param-hdlname>APB_AWIDTH</param-hdlname>
<param-hdlvalue>16</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>APB Data Bus Width:</param-name>
<param-value>32</param-value>
<param-hdlname>APB_DWIDTH</param-hdlname>
<param-hdlvalue>32</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Number of APB Slots:</param-name>
<param-value>16</param-value>
<param-hdlname>APB_SDEPTH</param-hdlname>
<param-hdlvalue>16</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Verbose Simulation Log:</param-name>
<param-value>true</param-value>
<param-hdlname>DEBUG</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>APBWRT ACM</param-name>
<param-value>false</param-value>
<param-hdlname>EN_ACM</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>ADD, SUB, DEC, CMPLEQ</param-name>
<param-value>true</param-value>
<param-hdlname>EN_ADD</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>ALU Operations from Memory:</param-name>
<param-value>false</param-value>
<param-hdlname>EN_ALURAM</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>AND, BITCLR, BITTST</param-name>
<param-value>true</param-value>
<param-hdlname>EN_AND</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>CALL, RETURN, RETISR</param-name>
<param-value>true</param-value>
<param-hdlname>EN_CALL</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Supported Data Sources:</param-name>
<param-value>Accumulator and Immediate</param-value>
<param-hdlname>EN_DATAM</param-hdlname>
<param-hdlvalue>2</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>INC</param-name>
<param-value>true</param-value>
<param-hdlname>EN_INC</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>APB Indirect Addressing:</param-name>
<param-value>false</param-value>
<param-hdlname>EN_INDIRECT</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Interrupt Support:</param-name>
<param-value>Disabled</param-value>
<param-hdlname>EN_INT</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>IOREAD</param-name>
<param-value>true</param-value>
<param-hdlname>EN_IOREAD</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>IOWRT</param-name>
<param-value>true</param-value>
<param-hdlname>EN_IOWRT</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>MULT</param-name>
<param-value>Not Implemented</param-value>
<param-hdlname>EN_MULT</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>OR, BITSET</param-name>
<param-value>true</param-value>
<param-hdlname>EN_OR</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>PUSH, POP</param-name>
<param-value>true</param-value>
<param-hdlname>EN_PUSH</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Internal Data/Stack Memory:</param-name>
<param-value>true</param-value>
<param-hdlname>EN_RAM</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>SHL, ROL</param-name>
<param-value>true</param-value>
<param-hdlname>EN_SHL</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>SHR, ROR</param-name>
<param-value>true</param-value>
<param-hdlname>EN_SHR</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>XOR, CMP</param-name>
<param-value>true</param-value>
<param-hdlname>EN_XOR</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>FPGA Family:</param-name>
<param-value>SmartFusion2</param-value>
<param-hdlname>FAMILY</param-hdlname>
<param-hdlvalue>19</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Maximum Number of Instructions:</param-name>
<param-value>64</param-value>
<param-hdlname>ICWIDTH</param-hdlname>
<param-hdlvalue>6</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Number of I/O Flags:</param-name>
<param-value>0</param-value>
<param-hdlname>IFWIDTH</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Number of I/O Inputs:</param-name>
<param-value>1</param-value>
<param-hdlname>IIWIDTH</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Instruction Memory Access</param-name>
<param-value>None</param-value>
<param-hdlname>IMEM_APB_ACCESS</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Initialization Width:</param-name>
<param-value>11</param-value>
<param-hdlname>INITWIDTH</param-hdlname>
<param-hdlvalue>11</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Instruction Store:</param-name>
<param-value>Hard (FPGA Tiles)</param-value>
<param-hdlname>INSMODE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Number of I/O Outputs:</param-name>
<param-value>1</param-value>
<param-hdlname>IOWIDTH</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>ISR Address:</param-name>
<param-value>1</param-value>
<param-hdlname>ISRADDR</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>
</param-name>
<param-value>32</param-value>
<param-hdlname>MAX_NVMDWIDTH</param-hdlname>
<param-hdlvalue>32</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Stack Size:</param-name>
<param-value>16</param-value>
<param-hdlname>STWIDTH</param-hdlname>
<param-hdlvalue>4</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Test Mode:</param-name>
<param-value>User configured code</param-value>
<param-hdlname>TESTMODE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>
</param-name>
<param-value>26</param-value>
<param-hdlname>UNIQ_STRING_LENGTH</param-hdlname>
<param-hdlvalue>26</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Z Register Size (Bits):</param-name>
<param-value>Disabled</param-value>
<param-hdlname>ZRWIDTH</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-name>COREABC_0</core-name>
</core>
<core type="SpiritModule">
<core-exttype>IP</core-exttype>
<core-type>SpiritModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>DirectCore</core-lib>
<core-intname>CoreAPB3</core-intname>
<core-ver>4.0.100</core-ver>
<core-desc>
The CoreAPB3 component implements an APB3 (AMBA3 APB) fabric, which is backwards compatible with APB2 slave peripherals.
There is one APB3 Master interface.
</core-desc>
<core-param>
<param-name>APB Master Data Bus Width</param-name>
<param-value>32-bit</param-value>
<param-hdlname>APB_DWIDTH</param-hdlname>
<param-hdlvalue>32</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 0:</param-name>
<param-value>true</param-value>
<param-hdlname>APBSLOT0ENABLE</param-hdlname>
<param-hdlvalue>1</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 1:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT1ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 2:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT2ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 3:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT3ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 4:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT4ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 5:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT5ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 6:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT6ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 7:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT7ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 8:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT8ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 9:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT9ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 10:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT10ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 11:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT11ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 12:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT12ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 13:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT13ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 14:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT14ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 15:</param-name>
<param-value>false</param-value>
<param-hdlname>APBSLOT15ENABLE</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Indirect Addressing:</param-name>
<param-value>Indirect address sourced from register(s) in slot 4 space</param-value>
<param-hdlname>IADDR_OPTION</param-hdlname>
<param-hdlvalue>6</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Number of address bits driven by master:</param-name>
<param-value>20</param-value>
<param-hdlname>MADDR_BITS</param-hdlname>
<param-hdlvalue>20</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 0:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_0</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 1:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_1</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 2:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_2</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 3:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_3</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 4:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_4</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 5:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_5</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 6:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_6</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 7:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_7</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 8:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_8</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 9:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_9</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 10:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_10</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 11:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_11</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 12:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_12</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 13:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_13</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 14:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_14</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Slot 15:</param-name>
<param-value>false</param-value>
<param-hdlname>SC_15</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-param>
<param-name>Position in slave address of upper 4 bits of master address:</param-name>
<param-value>[19:16] (Ignored if master address width >= 24 bits)</param-value>
<param-hdlname>UPR_NIBBLE_POSN</param-hdlname>
<param-hdlvalue>4</param-hdlvalue>
<param-tag>spirit:hwParameter</param-tag>
</core-param>
<core-name>CoreAPB3_0</core-name>
</core>
<core type="ComponentModule">
<core-type>ComponentModule</core-type>
<core-exttype>SmartDesign</core-exttype>
<core-location>D:/Actelprj/SF2_DEVKIT_DEMO/component/work/DEV_KIT_DEMO</core-location>
<core-name>DEV_KIT_DEMO_0</core-name>
</core>
<core type="SpiritModule">
<core-exttype>IP</core-exttype>
<core-type>SpiritModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>SgCore</core-lib>
<core-intname>SERDES_IF</core-intname>
<core-ver>1.0.100</core-ver>
<core-desc>SmartFusion2 High Speed Serial Interface</core-desc>
<core-name>SERDES_IF_0</core-name>
</core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_CMSIS</core-intname>
<core-ver>2.1.101</core-ver>
<core-desc>SmartFusion2 Cortex Microcontroller Software Interface Standard (CMSIS).
The firmware package provides:
- Cortex-M3 startup code.
- CMSIS standard naming for exception and interrupt handlers.
- CMSIS standard functions for controlling the Cortex-M3 Nested Vectored Interrupt Controller (NVIC).
- peripherals registers description.
- hardware abstraction layer (HAL) for FPGA fabric soft-IP peripherirals.
These files are required by the SmartFusion2 bare metal peripheral drivers to build correctly.
</core-desc>
<core-param>
<param-name>Software Tool Chain:</param-name>
<param-value>SoftConsole</param-value>
<param-hdlname>ToolChain</param-hdlname>
<param-hdlvalue>0</param-hdlvalue>
<param-tag>actel-cc:variantParameter</param-tag>
</core-param>
<core-name>SmartFusion2_CMSIS_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_GPIO_Driver</core-intname>
<core-ver>2.0.101</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) GPIO bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_GPIO_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_HPDMA_Driver</core-intname>
<core-ver>2.0.101</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) High Performance DMA bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_HPDMA_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>
<core-ver>2.0.100</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_I2C_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_I2C_Driver</core-intname>
<core-ver>2.0.100</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) I2C bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_I2C_Driver_1</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_MMUART_Driver</core-intname>
<core-ver>2.0.101</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) MMUART bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_MMUART_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_PDMA_Driver</core-intname>
<core-ver>2.0.102</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) Peripheral DMA bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_PDMA_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_RTC_Driver</core-intname>
<core-ver>2.0.101</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) RTC bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_RTC_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_SPI_Driver</core-intname>
<core-ver>2.0.103</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) SPI bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_SPI_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_System_Services_Driver</core-intname>
<core-ver>2.0.103</core-ver>
<core-desc>SmartFusion2 microsontroller subsystem (MSS) System Services software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_System_Services_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_Timer_Driver</core-intname>
<core-ver>2.0.101</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) Timer bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_Timer_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_USB_Driver</core-intname>
<core-ver>2.1.100</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) USB bare metal software driver.
The firmware package provides:
- MSS USB Device Core Driver
- USB MSC Device Class driver with example project.
- USB CDC Device Class driver with example project.
- USB HID Device Class driver with example project.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_USB_Driver_0</core-name>
</firmware_core>
<firmware_core type="FirmWareModule">
<core-exttype>IP</core-exttype>
<core-type>FirmWareModule</core-type>
<core-vendor>Actel</core-vendor>
<core-lib>Firmware</core-lib>
<core-intname>SmartFusion2_MSS_Watchdog_Driver</core-intname>
<core-ver>2.0.102</core-ver>
<core-desc>SmartFusion2 microcontroller subsystem (MSS) Watchdog bare metal software driver.
This driver requires the SmartFusion2 CMSIS Hardware Abstraction Layer to build correctly.</core-desc>
<core-name>SmartFusion2_MSS_Watchdog_Driver_0</core-name>
</firmware_core>
<memorysystem>
<title>Memory Map for DEV_KIT_DEMO_top</title>
<description>The project contains the following subsystems:</description>
<subsystems>
<subsystem>
<name>CM3</name>
<master>CM3</master>
<master>FABRIC2MSSFIC2</master>
<master>FABRICTOMSSFIC0_APB_BRIDGE</master>
<addressNames>
<count>1</count>
<name>
</name>
</addressNames>
<slave>
<name>FIC32_REGION5</name>
<fullPinName>
</fullPinName>
<remapAddress>0xF0000000</remapAddress>
<fullAddressSpace>0xF0000000 - 0xFFFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>DDR_0_SPACE_3</name>
<fullPinName>
</fullPinName>
<remapAddress>0xD0000000</remapAddress>
<fullAddressSpace>0xD0000000 - 0xDFFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>DDR_0_SPACE_2</name>
<fullPinName>
</fullPinName>
<remapAddress>0xC0000000</remapAddress>
<fullAddressSpace>0xC0000000 - 0xCFFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>DDR_0_SPACE_1</name>
<fullPinName>
</fullPinName>
<remapAddress>0xB0000000</remapAddress>
<fullAddressSpace>0xB0000000 - 0xBFFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>DDR_0_SPACE_0</name>
<fullPinName>
</fullPinName>
<remapAddress>0xA0000000</remapAddress>
<fullAddressSpace>0xA0000000 - 0xAFFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>FIC32_REGION4</name>
<fullPinName>
</fullPinName>
<remapAddress>0x90000000</remapAddress>
<fullAddressSpace>0x90000000 - 0x9FFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>FIC32_REGION3</name>
<fullPinName>
</fullPinName>
<remapAddress>0x80000000</remapAddress>
<fullAddressSpace>0x80000000 - 0x8FFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>AHB2ENVM1_REGISTERS</name>
<fullPinName>
</fullPinName>
<remapAddress>0x600C0000</remapAddress>
<fullAddressSpace>0x600C0000 - 0x600FFFFF</fullAddressSpace>
<range>0x00040000</range>
</slave>
<slave>
<name>AHB2ENVM0_REGISTERS</name>
<fullPinName>
</fullPinName>
<remapAddress>0x60080000</remapAddress>
<fullAddressSpace>0x60080000 - 0x600BFFFF</fullAddressSpace>
<range>0x00040000</range>
</slave>
<slave>
<name>ENVM1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x60040000</remapAddress>
<fullAddressSpace>0x60040000 - 0x6007FFFF</fullAddressSpace>
<range>0x00040000</range>
</slave>
<slave>
<name>ENVM0</name>
<fullPinName>
</fullPinName>
<remapAddress>0x60000000</remapAddress>
<fullAddressSpace>0x60000000 - 0x6003FFFF</fullAddressSpace>
<range>0x00040000</range>
</slave>
<slave>
<name>FIC32_REGION1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x50000000</remapAddress>
<fullAddressSpace>0x50000000 - 0x5FFFFFFF</fullAddressSpace>
<range>0x10000000</range>
</slave>
<slave>
<name>CACHE_BACKDOOR</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40400000</remapAddress>
<fullAddressSpace>0x40400000 - 0x4040FFFF</fullAddressSpace>
<range>0x00010000</range>
</slave>
<slave>
<name>USB</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40043000</remapAddress>
<fullAddressSpace>0x40043000 - 0x40043FFF</fullAddressSpace>
<range>0x00001000</range>
</slave>
<slave>
<name>SYSREG</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40038000</remapAddress>
<fullAddressSpace>0x40038000 - 0x40038FFF</fullAddressSpace>
<range>0x00001000</range>
<memoryMap>
<name>RegisterMap</name>
<addressBlock>
<baseAddress>0x0</baseAddress>
<range format="long">0x1000</range>
<width format="long" id="width">32</width>
<register>
<name>ESRAM_CONFIG</name>
<addressOffset>0x0</addressOffset>
<absoluteAddress>0x40038000</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>F2_ESRAMSIZE</name>
<bitNumber>4:3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_TESTESRAM1REMAP_SYNC</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_TESTREMAPENABLE_SYNC</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>COM_ESRAMFWREMAP</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>ENVM_CONFIG</name>
<addressOffset>0x4</addressOffset>
<absoluteAddress>0x40038004</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>ENVM_SIX_CYCLE</name>
<bitNumber>7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ENVM_PIPE_BYPASS</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_ENVMPOWEREDDOWN</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>COM_ENVMREMAPSIZE</name>
<bitNumber>4:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>ENVM_REMAP_BASE</name>
<addressOffset>0x8</addressOffset>
<absoluteAddress>0x40038008</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>COM_ENVMREMAPBASE</name>
<bitNumber>19:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>ENVM_FAB_REMAP</name>
<addressOffset>0xC</addressOffset>
<absoluteAddress>0x4003800C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>COM_ENVMFABREMAPBASE</name>
<bitNumber>19:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>FAB_PROT_SIZE</name>
<addressOffset>0x10</addressOffset>
<absoluteAddress>0x40038010</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>COM_PROTREGIONSIZE</name>
<bitNumber>4:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>FAB_PROT_BASE</name>
<addressOffset>0x14</addressOffset>
<absoluteAddress>0x40038014</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>COM_PROTREGIONBASE</name>
<bitNumber>31:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>MATRIX_CONFIG</name>
<addressOffset>0x18</addressOffset>
<absoluteAddress>0x40038018</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>COM_WEIGHTEDMODE</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>COM_MASTERENABLE</name>
<bitNumber>2:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>DSS_STATUS</name>
<addressOffset>0x1C</addressOffset>
<absoluteAddress>0x4003801C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>PLLLOCKLOSTINT</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>PLLLOCKINT</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>COM_ERRORSTATUS</name>
<bitNumber>8:4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BROWNOUT3_3VINT</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BROWNOUT1_5VINT</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>WDOGTIMEOUTEVENT</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RTCMATCHEVENT</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CLR_DSS_STATUS</name>
<addressOffset>0x20</addressOffset>
<absoluteAddress>0x40038020</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>CLRPLLLOCKLOSTINT</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>CLRPLLLOCKINT</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>COM_CLEARSTATUS</name>
<bitNumber>8:4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>CLRBROWNOUT3_3VINT</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>CLRBROWNOUT1_5VINT</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>CLRWDOGTIMEOUTEVENT</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>CLRRTCMATCHEVENT</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>FROM_CONFIG</name>
<addressOffset>0x24</addressOffset>
<absoluteAddress>0x40038024</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>SYS_TOPT</name>
<bitNumber>3:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>IAP_CONFIG</name>
<addressOffset>0x28</addressOffset>
<absoluteAddress>0x40038028</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>SYS_FCFG</name>
<bitNumber>2:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>SOFT_INTERRUPT</name>
<addressOffset>0x2C</addressOffset>
<absoluteAddress>0x4003802C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>SOFTINTERRUPT</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>SOFT_RESET</name>
<addressOffset>0x30</addressOffset>
<absoluteAddress>0x40038030</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>PADRESETENABLE</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>USERRESETACTIVE</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FPGA_SOFTRESET</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EXT_SOFTRESET</name>
<bitNumber>16</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>IAP_SOFTRESET</name>
<bitNumber>15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>GPIO_SOFTRESET</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ACE_SOFTRESET</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>I2C1_SOFTRESET</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>I2C0_SOFTRESET</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>SPI1_SOFTRESET</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>SPI0_SOFTRESET</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>UART1_SOFTRESET</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>UART0_SOFTRESET</name>
<bitNumber>7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>TIMER_SOFTRESET</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>PDMA_SOFTRESET</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>MAC_SOFTRESET</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EMC_SOFTRESET</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ESRAM1_SOFTRESET</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ESRAM0_SOFTRESET</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ENVM_SOFTRESET</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>DEVICE_STATUS</name>
<addressOffset>0x34</addressOffset>
<absoluteAddress>0x40038034</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>FPGAGOOD_SYNC</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FPGAPROGRAMMING_SYNC</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_PC_ACCESS_SYNC</name>
<bitNumber>4:3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>VCCIBGOOD_SYNC</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BROWNOUT3_3V_SYNCN</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BROWNOUT1_5V_SYNCN</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>SYSTICK_CONFIG</name>
<addressOffset>0x38</addressOffset>
<absoluteAddress>0x40038038</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>STCLK_DIVISOR</name>
<bitNumber>29:28</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>STCALIB</name>
<bitNumber>25:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>EM_MUX_CONFIG</name>
<addressOffset>0x3C</addressOffset>
<absoluteAddress>0x4003803C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>EM_SEL</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>EM_CONFIG_0</name>
<addressOffset>0x40</addressOffset>
<absoluteAddress>0x40038040</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>EM_CSFE0</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_WENBEN0</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RWPOL0</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PIPEWRN0</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PIPERDN0</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_IDD0</name>
<bitNumber>16:15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_WRITELAT0</name>
<bitNumber>14:11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RDLATREST0</name>
<bitNumber>10:7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RDLATFIRST0</name>
<bitNumber>6:3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PORTSIZE0</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_MEMTYPE0</name>
<bitNumber>1:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>EM_CONFIG_1</name>
<addressOffset>0x44</addressOffset>
<absoluteAddress>0x40038044</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>EM_CSFE1</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_WENBEN1</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RWPOL1</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PIPEWRN1</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PIPERDN1</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_IDD1</name>
<bitNumber>16:15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_WRITELAT1</name>
<bitNumber>14:11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RDLATREST1</name>
<bitNumber>10:7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_RDLATFIRST1</name>
<bitNumber>6:3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_PORTSIZE1</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EM_MEMTYPE1</name>
<bitNumber>1:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CLK_CTRL</name>
<addressOffset>0x48</addressOffset>
<absoluteAddress>0x40038048</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>GLBDIVISOR</name>
<bitNumber>13:12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RTCIF_ACMDIVISOR</name>
<bitNumber>11:8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>ACLKDIVISOR</name>
<bitNumber>7:6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>PCLK1DIVISOR</name>
<bitNumber>5:4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>PCLK0DIVISOR</name>
<bitNumber>3:2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RMIICLKSEL</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CCC_DIV_CONFIG</name>
<addressOffset>0x4C</addressOffset>
<absoluteAddress>0x4003804C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>OCDIVRST</name>
<bitNumber>22</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIVHALF</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIV4</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIV3</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIV2</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIV1</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCDIV0</name>
<bitNumber>16</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIVRST</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIVHALF</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIV4</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIV3</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIV2</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIV1</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBDIV0</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIVRST</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIVHALF</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIV4</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIV3</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIV2</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIV1</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OADIV0</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CCC_MUX_CONFIG</name>
<addressOffset>0x50</addressOffset>
<absoluteAddress>0x40038050</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>MODE</name>
<bitNumber>31:30</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>EN</name>
<bitNumber>29</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>GLMUXCFG1</name>
<bitNumber>27</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>GLMUXCFG0</name>
<bitNumber>26</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>GLMUXSEL1</name>
<bitNumber>25</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>GLMUXSEL0</name>
<bitNumber>24</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BYPASS_PLL3</name>
<bitNumber>22</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCMUX2</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCMUX1</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OCMUX0</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DYNCSEL</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RXCSEL</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>STATCSEL</name>
<bitNumber>16</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BYPASS_PLL2</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBMUX2</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBMUX1</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OBMUX0</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DYNBSEL</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RXBSEL</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>STATBSEL</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BYPASS_PLL1</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OAMUX2</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OAMUX1</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>OAMUX0</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DYNASEL</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RXASEL</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>STATASEL</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CCC_PLL_CONFIG</name>
<addressOffset>0x54</addressOffset>
<absoluteAddress>0x40038054</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>POWERDOWN</name>
<bitNumber>31</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>VCOSEL2</name>
<bitNumber>24</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>VCOSEL1</name>
<bitNumber>23</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>VCOSEL0</name>
<bitNumber>22</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>XDLYSEL</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDLY4</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDLY3</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDLY2</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDLY1</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDLY0</name>
<bitNumber>16</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBSEL1</name>
<bitNumber>15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBSEL0</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV6</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV5</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV4</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV3</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV2</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV1</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FBDIV0</name>
<bitNumber>7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV6</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV5</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV4</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV3</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV2</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV1</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FINDIV0</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CCC_DLY_CONFIG</name>
<addressOffset>0x58</addressOffset>
<absoluteAddress>0x40038058</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>DLYA14</name>
<bitNumber>24</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA13</name>
<bitNumber>23</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA12</name>
<bitNumber>22</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA11</name>
<bitNumber>21</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA10</name>
<bitNumber>20</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA04</name>
<bitNumber>19</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA03</name>
<bitNumber>18</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA02</name>
<bitNumber>17</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA01</name>
<bitNumber>16</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYA00</name>
<bitNumber>15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCC4</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCC3</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCC2</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCC1</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCC0</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCB4</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCB3</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCB2</name>
<bitNumber>7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCB1</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCB0</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCA4</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCA3</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCA2</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCA1</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DLYHCA0</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>CCC_STATUS</name>
<addressOffset>0x5C</addressOffset>
<absoluteAddress>0x4003805C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>PLLLOCK_SYNC</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>VTG_CTRL</name>
<addressOffset>0x64</addressOffset>
<absoluteAddress>0x40038064</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>BGPSMENABLE</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>VBATSELECT</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RTCIF_CLRPUBINT</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RTCIF_VRONENABLE</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>RTCIF_FWVRON</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>FAB_IF</name>
<addressOffset>0x6C</addressOffset>
<absoluteAddress>0x4003806C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>FABCALIBFAIL</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FABCALIBSTART</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_LARGE_CT_XS</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FAB_APB32</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FAB_AHBIF</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>F2_AHBCAPABLE</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>FAB_AHB_BYPASS</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>APB_EXTN</name>
<addressOffset>0x70</addressOffset>
<absoluteAddress>0x40038070</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>APB16_XHOLD</name>
<bitNumber>15:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>LOOPBACK_CTRL</name>
<addressOffset>0x74</addressOffset>
<absoluteAddress>0x40038074</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>DSS_EMACLOOPBACK</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPIOLOOPBACK</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_I2CLOOPBACK</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_SPILOOPBACK</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_UARTLOOPBACK</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>IO_BANK_CONFIG</name>
<addressOffset>0x78</addressOffset>
<absoluteAddress>0x40038078</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>BTWEST</name>
<bitNumber>3:2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>BTEAST</name>
<bitNumber>1:0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
<register>
<name>GPIN_SRC_SEL</name>
<addressOffset>0x7C</addressOffset>
<absoluteAddress>0x4003807C</absoluteAddress>
<size>32</size>
<access>R/W</access>
<resetValue>0x0</resetValue>
<field>
<name>DSS_GPINSOURCE[15]</name>
<bitNumber>15</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[14]</name>
<bitNumber>14</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[13]</name>
<bitNumber>13</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[12]</name>
<bitNumber>12</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[11]</name>
<bitNumber>11</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[10]</name>
<bitNumber>10</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[9]</name>
<bitNumber>9</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[8]</name>
<bitNumber>8</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[7]</name>
<bitNumber>7</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[6]</name>
<bitNumber>6</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[5]</name>
<bitNumber>5</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[4]</name>
<bitNumber>4</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[3]</name>
<bitNumber>3</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[2]</name>
<bitNumber>2</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[1]</name>
<bitNumber>1</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
<field>
<name>DSS_GPINSOURCE[0]</name>
<bitNumber>0</bitNumber>
<access>R/W</access>
<description>
</description>
</field>
</register>
</addressBlock>
</memoryMap>
</slave>
<slave>
<name>CFGM</name>
<fullPinName>DEV_KIT_DEMO_MSS_0:MDDR_APB_SLAVE</fullPinName>
<remapAddress>0x40020800</remapAddress>
<fullAddressSpace>0x40020800 - 0x40020FFF</fullAddressSpace>
<range>0x800</range>
</slave>
<slave>
<name>CORESF2CONFIG_0</name>
<fullPinName>DEV_KIT_DEMO:SDIF1_APBmslave</fullPinName>
<remapAddress>0x4002C000</remapAddress>
<fullAddressSpace>0x4002C000 - 0x4002E3FF</fullAddressSpace>
<range>0x2400</range>
</slave>
<slave>
<name>RTC</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40017000</remapAddress>
<fullAddressSpace>0x40017000 - 0x40017FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>COMBLK</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40016000</remapAddress>
<fullAddressSpace>0x40016000 - 0x40016FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>HDMA</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40014000</remapAddress>
<fullAddressSpace>0x40014000 - 0x40014FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>GPIO</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40013000</remapAddress>
<fullAddressSpace>0x40013000 - 0x40013FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>I2C_1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40012000</remapAddress>
<fullAddressSpace>0x40012000 - 0x40012FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>MMUART_1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40010000</remapAddress>
<fullAddressSpace>0x40010000 - 0x40010FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>H2FINTERRUPT</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40006000</remapAddress>
<fullAddressSpace>0x40006000 - 0x40006FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>WATCHDOG</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40005000</remapAddress>
<fullAddressSpace>0x40005000 - 0x40005FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>TIMER</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40004000</remapAddress>
<fullAddressSpace>0x40004000 - 0x40004FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>PDMA</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40003000</remapAddress>
<fullAddressSpace>0x40003000 - 0x40003FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>I2C_0</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40002000</remapAddress>
<fullAddressSpace>0x40002000 - 0x40002FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>SPI_0</name>
<fullPinName>
</fullPinName>
<remapAddress>0x40001000</remapAddress>
<fullAddressSpace>0x40001000 - 0x40001FFF</fullAddressSpace>
<range>0x1000</range>
</slave>
<slave>
<name>RECYCLED_ESRAM1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x20012000</remapAddress>
<fullAddressSpace>0x20012000 - 0x20013FFF</fullAddressSpace>
<range>0x00002000</range>
</slave>
<slave>
<name>RECYCLED_ESRAM0</name>
<fullPinName>
</fullPinName>
<remapAddress>0x20010000</remapAddress>
<fullAddressSpace>0x20010000 - 0x20011FFF</fullAddressSpace>
<range>0x00002000</range>
</slave>
<slave>
<name>ESRAM1</name>
<fullPinName>
</fullPinName>
<remapAddress>0x20008000</remapAddress>
<fullAddressSpace>0x20008000 - 0x2000FFFF</fullAddressSpace>
<range>0x00008000</range>
</slave>
<slave>
<name>ESRAM0</name>
<fullPinName>
</fullPinName>
<remapAddress>0x00080000</remapAddress>
<fullAddressSpace>0x00080000 - 0x00087FFF</fullAddressSpace>
<range>0x00008000</range>
</slave>
</subsystem>
<subsystem>
<name>COREABC_0</name>
<master>COREABC_0</master>
<addressNames>
<count>1</count>
<name>
</name>
</addressNames>
<slave>
<name>FIC32_0</name>
<fullPinName>DEV_KIT_DEMO_0:FIC_0_APB_SLAVE</fullPinName>
<remapAddress>0x00000000</remapAddress>
<fullAddressSpace>0x00000000 - 0x0000FFFF</fullAddressSpace>
<range>0x00010000</range>
</slave>
</subsystem>
</subsystems>
</memorysystem>
</datasheet>