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nest-open-source / nest-detect / 1.0.1 / freertos / 206cc878b671927e8b1dab34a51b91a5c279eb49 / . / FreeRTOS / Demo / CORTEX_EFMG890F128_IAR / CMSIS / CM3 / DeviceSupport / EnergyMicro / EFM32 / efm32g890f128.h
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/**************************************************************************//**
* @file
* @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM EFM32G890F128
* @author Energy Micro AS
* @version 1.0.2
******************************************************************************
* @section License
* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
******************************************************************************
*
* This source code is the property of Energy Micro AS. The source and compiled
* code may only be used on Energy Micro "EFM32" microcontrollers.
*
* This copyright notice may not be removed from the source code nor changed.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
* obligation to support this Software. Energy Micro AS is providing the
* Software "AS IS", with no express or implied warranties of any kind,
* including, but not limited to, any implied warranties of merchantability
* or fitness for any particular purpose or warranties against infringement
* of any proprietary rights of a third party.
*
* Energy Micro AS will not be liable for any consequential, incidental, or
* special damages, or any other relief, or for any claim by any third party,
* arising from your use of this Software.
*
*****************************************************************************/
#ifndef __EFM32G890F128_H
#define __EFM32G890F128_H
/**************************************************************************//**
*
* @defgroup EFM32G890F128 EFM32G890F128
* @{
*****************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** EFM32G Peripheral Interrupt Numbers **************************************************/
DMA_IRQn = 0, /*!< DMA Interrupt */
GPIO_EVEN_IRQn = 1, /*!< GPIO_EVEN Interrupt */
TIMER0_IRQn = 2, /*!< TIMER0 Interrupt */
USART0_RX_IRQn = 3, /*!< USART0_RX Interrupt */
USART0_TX_IRQn = 4, /*!< USART0_TX Interrupt */
ACMP0_IRQn = 5, /*!< ACMP0 Interrupt */
ADC0_IRQn = 6, /*!< ADC0 Interrupt */
DAC0_IRQn = 7, /*!< DAC0 Interrupt */
I2C0_IRQn = 8, /*!< I2C0 Interrupt */
GPIO_ODD_IRQn = 9, /*!< GPIO_ODD Interrupt */
TIMER1_IRQn = 10, /*!< TIMER1 Interrupt */
TIMER2_IRQn = 11, /*!< TIMER2 Interrupt */
USART1_RX_IRQn = 12, /*!< USART1_RX Interrupt */
USART1_TX_IRQn = 13, /*!< USART1_TX Interrupt */
USART2_RX_IRQn = 14, /*!< USART2_RX Interrupt */
USART2_TX_IRQn = 15, /*!< USART2_TX Interrupt */
UART0_RX_IRQn = 16, /*!< UART0_RX Interrupt */
UART0_TX_IRQn = 17, /*!< UART0_TX Interrupt */
LEUART0_IRQn = 18, /*!< LEUART0 Interrupt */
LEUART1_IRQn = 19, /*!< LEUART1 Interrupt */
LETIMER0_IRQn = 20, /*!< LETIMER0 Interrupt */
PCNT0_IRQn = 21, /*!< PCNT0 Interrupt */
PCNT1_IRQn = 22, /*!< PCNT1 Interrupt */
PCNT2_IRQn = 23, /*!< PCNT2 Interrupt */
RTC_IRQn = 24, /*!< RTC Interrupt */
CMU_IRQn = 25, /*!< CMU Interrupt */
VCMP_IRQn = 26, /*!< VCMP Interrupt */
LCD_IRQn = 27, /*!< LCD Interrupt */
MSC_IRQn = 28, /*!< MSC Interrupt */
AES_IRQn = 29, /*!< AES Interrupt */
} IRQn_Type;
/**************************************************************************//**
* @defgroup EFM32G890F128_Core EFM32G890F128 Core
* @{
*****************************************************************************/
#define __MPU_PRESENT 1 /**< Presence of MPU */
#define __NVIC_PRIO_BITS 3 /**< NVIC intterupt priority bits */
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
/**
* @}
*/
/**************************************************************************//**
* @defgroup EFM32G890F128_Part EFM32G890F128 Part
* @{
******************************************************************************/
#if !defined(EFM32G890F128)
#define EFM32G890F128
#endif
/** Configure part number */
#define PART_NUMBER "EFM32G890F128" /**< Part Number */
/** Memory Base addresses and limits */
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
/** Flash and SRAM limits for EFM32G890F128 */
#define FLASH_SIZE 0x00020000UL /**< Available flash memory */
#define SRAM_SIZE 0x00004000UL /**< Available sram memory */
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
#define DPI_CHAN_COUNT 8 /**< Number of DPI channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
/* Part number capabilities */
#define TIMER_PRESENT
#define TIMER_COUNT 3
#define TIMER_PARAM_DTI(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0)
#define TIMER_PARAM_CCNUM(i) (i == 0 ? 3 : i == 1 ? 3 : i == 2 ? 3 : 0)
#define USART_PRESENT
#define USART_COUNT 3
#define USART_PARAM_SC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)
#define USART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0)
#define USART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)
#define USART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)
#define UART_PRESENT
#define UART_COUNT 1
#define UART_PARAM_SC_AVAILABLE(i) (i == 0 ? 0 : 0)
#define UART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 0 : 0)
#define UART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 0 : 0)
#define UART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 0 : 0)
#define LEUART_PRESENT
#define LEUART_COUNT 2
#define LETIMER_PRESENT
#define LETIMER_COUNT 1
#define PCNT_PRESENT
#define PCNT_COUNT 3
#define PCNT_PARAM_PCNT_WIDTH(i) (i == 0 ? 16 : i == 1 ? 8 : i == 2 ? 8 : 0)
#define I2C_PRESENT
#define I2C_COUNT 1
#define ADC_PRESENT
#define ADC_COUNT 1
#define ADC_PARAM_RES(i) (i == 0 ? 12 : 0)
#define DAC_PRESENT
#define DAC_COUNT 1
#define DAC_PARAM_RES(i) (i == 0 ? 12 : 0)
#define ACMP_PRESENT
#define ACMP_COUNT 2
#define CM3_PRESENT
#define CM3_COUNT 1
#define CM3_FREE_PRESENT
#define CM3_FREE_COUNT 1
#define BUSMATRIX_PRESENT
#define BUSMATRIX_COUNT 1
#define DMEM_PRESENT
#define DMEM_COUNT 1
#define AHB2APB_PRESENT
#define AHB2APB_COUNT 1
#define LE_PRESENT
#define LE_COUNT 1
#define MSC_PRESENT
#define MSC_COUNT 1
#define EMU_PRESENT
#define EMU_COUNT 1
#define RMU_PRESENT
#define RMU_COUNT 1
#define CMU_PRESENT
#define CMU_COUNT 1
#define AES_PRESENT
#define AES_COUNT 1
#define EBI_PRESENT
#define EBI_COUNT 1
#define GPIO_PRESENT
#define GPIO_COUNT 1
#define PRS_PRESENT
#define PRS_COUNT 1
#define DMA_PRESENT
#define DMA_COUNT 1
#define VCMP_PRESENT
#define VCMP_COUNT 1
#define LCD_PRESENT
#define LCD_COUNT 1
#define LCD_PARAM_SEG_NUM 40
#define LCD_PARAM_COM_NUM 4
#define RTC_PRESENT
#define RTC_COUNT 1
#define HFXTAL_PRESENT
#define HFXTAL_COUNT 1
#define LFXTAL_PRESENT
#define LFXTAL_COUNT 1
#define WDOG_PRESENT
#define WDOG_COUNT 1
#define DBG_PRESENT
#define DBG_COUNT 1
#define TMODE_PRESENT
#define TMODE_COUNT 1
#define SCAN_PRESENT
#define SCAN_COUNT 1
/**
* @}
*/
/* Include CMSIS core functionality */
#include "core_cm3.h"
#include "system_efm32.h"
#include <stdint.h>
/**************************************************************************//**
*
* @defgroup EFM32G890F128_Peripheral_TypeDefs EFM32G890F128 Peripheral TypeDefs
* @{
*
*****************************************************************************/
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_MSC
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Memory System Control Register */
__IO uint32_t READCTRL; /**< Read Control Register */
__IO uint32_t WRITECTRL; /**< Write Control Register */
__O uint32_t WRITECMD; /**< Write Command Register */
__IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IO uint32_t WDATA; /**< Write Data Register */
__I uint32_t STATUS; /**< Status Register */
uint32_t RESERVED1[3]; /**< Reserved for future use **/
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
} MSC_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_EMU
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t MEMCTRL; /**< Memory Control Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t ATESTCTRL; /**< Analog Test Control Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IO uint32_t AUXCTRL; /**< Auxiliary Control Register */
} EMU_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_RMU
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__I uint32_t RSTCAUSE; /**< Reset Cause Register */
__O uint32_t CMD; /**< Command Register */
} RMU_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_CMU
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< CMU Control Register */
__IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
__IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
__IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */
__IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */
__IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
__IO uint32_t CALCTRL; /**< Calibration Control Register */
__IO uint32_t CALCNT; /**< Calibration Counter Register */
__O uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
__O uint32_t CMD; /**< Command Register */
__IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
__I uint32_t STATUS; /**< Status Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
__IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
uint32_t RESERVED0[2]; /**< Reserved for future use **/
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 */
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 */
uint32_t RESERVED3[1]; /**< Reserved for future use **/
__IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 */
uint32_t RESERVED4[1]; /**< Reserved for future use **/
__IO uint32_t PCNTCTRL; /**< PCNT Control Register */
__IO uint32_t LCDCTRL; /**< LCD Control Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
} CMU_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_AES
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t DATA; /**< DATA Register */
__IO uint32_t XORDATA; /**< XORDATA Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t KEYLA; /**< KEY Low Register */
__IO uint32_t KEYLB; /**< KEY Low Register */
__IO uint32_t KEYLC; /**< KEY Low Register */
__IO uint32_t KEYLD; /**< KEY Low Register */
__IO uint32_t KEYHA; /**< KEY High Register */
__IO uint32_t KEYHB; /**< KEY High Register */
__IO uint32_t KEYHC; /**< KEY High Register */
__IO uint32_t KEYHD; /**< KEY High Register */
} AES_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_EBI
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t ADDRTIMING; /**< Address Timing Register */
__IO uint32_t RDTIMING; /**< Read Timing Register */
__IO uint32_t WRTIMING; /**< Write Timing Register */
__IO uint32_t POLARITY; /**< Polarity Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} EBI_TypeDef; /** @} */
/**************************************************************************//**
*
* P
*
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Port Control Register */
__IO uint32_t MODEL; /**< Port Pin Mode Low Register */
__IO uint32_t MODEH; /**< Port Pin Mode High Register */
__IO uint32_t DOUT; /**< Port Data Out Register */
__O uint32_t DOUTSET; /**< Port Data Out Set Register */
__O uint32_t DOUTCLR; /**< Port Data Out Clear Register */
__O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
__I uint32_t DIN; /**< Port Data In Register */
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
} GPIO_P_TypeDef;
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_GPIO
* @{
*****************************************************************************/
typedef struct
{
GPIO_P_TypeDef P[6]; /**< Port configuration bits */
uint32_t RESERVED0[10]; /**< Reserved for future use **/
__IO uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
__IO uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
__IO uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
__IO uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__IO uint32_t INSENSE; /**< Input Sense Register */
__IO uint32_t LOCK; /**< Configuration Lock Register */
} GPIO_TypeDef; /** @} */
/**************************************************************************//**
*
* CH
*
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_PRS
* @{
*****************************************************************************/
typedef struct
{
__O uint32_t SWPULSE; /**< Software Pulse Register */
__IO uint32_t SWLEVEL; /**< Software Level Register */
uint32_t RESERVED0[2]; /**< Reserved registers */
PRS_CH_TypeDef CH[8]; /**< Channel registers */
} PRS_TypeDef; /** @} */
/**************************************************************************//**
*
* CH
*
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_DMA
* @{
*****************************************************************************/
typedef struct
{
__I uint32_t STATUS; /**< DMA Status Registers */
__IO uint32_t CONFIG; /**< DMA Configuration Register */
__IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
__I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
__I uint32_t WAITSTATUS; /**< Channel Wait on Request Status Register */
__O uint32_t CHSWREQ; /**< Channel Software Request Register */
__O uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
__O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
__O uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
__O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
__O uint32_t CHENS; /**< Channel Enable Set Register */
__O uint32_t CHENC; /**< Channel Enable Clear Register */
__O uint32_t CHALTS; /**< Channel Alternate Set Register */
__O uint32_t CHALTC; /**< Channel Alternate Clear Register */
__O uint32_t CHPRIS; /**< Channel Priority Set Register */
__O uint32_t CHPRIC; /**< Channel Priority Clear Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t ERRORC; /**< Bus Error Clear Register */
uint32_t RESERVED1[1004]; /**< Reserved for future use **/
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable register */
uint32_t RESERVED2[60]; /**< Reserved registers */
DMA_CH_TypeDef CH[8]; /**< Channel registers */
} DMA_TypeDef; /** @} */
/**************************************************************************//**
*
* CC
*
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< CC Channel Control Register */
__IO uint32_t CCV; /**< CC Channel Value Register */
__I uint32_t CCVP; /**< CC Channel Value Peek Register */
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
} TIMER_CC_TypeDef;
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_TIMER
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t TOP; /**< Counter Top Value Register */
__IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
__IO uint32_t CNT; /**< Counter Value Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
uint32_t RESERVED1[4]; /**< Reserved for future use **/
__IO uint32_t DTCTRL; /**< DTI Control Register */
__IO uint32_t DTTIME; /**< DTI Time Control Register */
__IO uint32_t DTFC; /**< DTI Fault Configuration Register */
__IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
__IO uint32_t DTFAULT; /**< DTI Fault Register */
__O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
__IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
} TIMER_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_USART
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t FRAME; /**< USART Frame Format Register */
__IO uint32_t TRIGCTRL; /**< USART Trigger Control register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< USART Status Register */
__IO uint32_t CLKDIV; /**< Clock Control Register */
__I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
__I uint32_t RXDATA; /**< RX Buffer Data Register */
__I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
__I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
__I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
__I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
__O uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
__O uint32_t TXDATA; /**< TX Buffer Data Register */
__O uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
__O uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t IRCTRL; /**< IrDA Control Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} USART_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_LEUART
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CLKDIV; /**< Clock Control Register */
__IO uint32_t STARTFRAME; /**< Start Frame Register */
__IO uint32_t SIGFRAME; /**< Signal Frame Register */
__I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
__I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
__O uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
__O uint32_t TXDATA; /**< Transmit Buffer Data Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t PULSECTRL; /**< Pulse Control Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IO uint32_t ROUTE; /**< I/O Routing Register */
} LEUART_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_LETIMER
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__I uint32_t CNT; /**< Counter Value Register */
__IO uint32_t COMP0; /**< Compare Value Register 0 */
__IO uint32_t COMP1; /**< Compare Value Register 1 */
__IO uint32_t REP0; /**< Repeat Counter Register 0 */
__IO uint32_t REP1; /**< Repeat Counter Register 1 */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[2]; /**< Reserved for future use **/
__IO uint32_t ROUTE; /**< I/O Routing Register */
} LETIMER_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_PCNT
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__I uint32_t CNT; /**< Counter Value Register */
__I uint32_t TOP; /**< Top Value Register */
__IO uint32_t TOPB; /**< Top Value Buffer Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} PCNT_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_I2C
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATE; /**< State Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CLKDIV; /**< Clock Division Register */
__IO uint32_t SADDR; /**< Slave Address Register */
__IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
__I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
__O uint32_t TXDATA; /**< Transmit Buffer Data Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} I2C_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_ADC
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
__IO uint32_t SCANCTRL; /**< Scan Control Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
__I uint32_t SCANDATA; /**< Scan Conversion Result Data */
__I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
__I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
__IO uint32_t CAL; /**< Calibration Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
__IO uint32_t BIASPROG; /**< Bias Programming Register */
} ADC_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_DAC
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t CH0CTRL; /**< Channel 0 Control Register */
__IO uint32_t CH1CTRL; /**< Channel 1 Control Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t CH0DATA; /**< Channel 0 Data Register */
__IO uint32_t CH1DATA; /**< Channel 1 Data Register */
__O uint32_t COMBDATA; /**< Combined Data Register */
__IO uint32_t CAL; /**< Calibration Register */
__IO uint32_t BIASPROG; /**< Bias Programming Register */
} DAC_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_ACMP
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t INPUTSEL; /**< Input Selection Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t ROUTE; /**< I/O Routing Register */
} ACMP_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_VCMP
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t INPUTSEL; /**< Input Selection Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
} VCMP_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_LCD
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__IO uint32_t DISPCTRL; /**< Display Control Register */
__IO uint32_t SEGEN; /**< Segment Enable Register */
__IO uint32_t BACTRL; /**< Blink and Animation Control Register */
__I uint32_t STATUS; /**< Status Register */
__IO uint32_t AREGA; /**< Animation Register A */
__IO uint32_t AREGB; /**< Animation Register B */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[5]; /**< Reserved for future use **/
__IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
__IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
__IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
__IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
__IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
__IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
__IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
__IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} LCD_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_RTC
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__I uint32_t CNT; /**< Counter Value Register */
__IO uint32_t COMP0; /**< Compare Value Register 0 */
__IO uint32_t COMP1; /**< Compare Value Register 1 */
__I uint32_t IF; /**< Interrupt Flag Register */
__O uint32_t IFS; /**< Interrupt Flag Set Register */
__O uint32_t IFC; /**< Interrupt Flag Clear Register */
__IO uint32_t IEN; /**< Interrupt Enable Register */
__IO uint32_t FREEZE; /**< Freeze Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} RTC_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_WDOG
* @{
*****************************************************************************/
typedef struct
{
__IO uint32_t CTRL; /**< Control Register */
__O uint32_t CMD; /**< Command Register */
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
} WDOG_TypeDef; /** @} */
/**
* @}
*/
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_DEVINFO
* @{
*****************************************************************************/
typedef struct
{
__I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
__I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
__I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
__I uint32_t PART; /**< Part description */
} DEVINFO_TypeDef; /** @} */
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_CALIBRATE
* @{
*****************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */
typedef struct
{
__I uint32_t ADDRESS; /**< Address of calibration register */
__I uint32_t VALUE; /**< Default value for calibration register */
} CALIBRATE_TypeDef; /** @} */
/** Special calibration registers */
#define HFRCO_CALIBH (*(volatile uint32_t *) 0x0FE081DCUL) /**< Calibration value for HFRCO 28 Mhz */
#define HFRCO_CALIBL (*(volatile uint32_t *) 0x0FE081E0UL) /**< Calibration value for HFRCO 1/7/11/21 Mhz */
#define ADC_CALIB (*(volatile uint32_t *) 0x0FE081E4UL) /**< ADC temperature for calibration and result */
/**************************************************************************//**
*
* @defgroup EFM32G890F128_Peripheral_Base EFM32G890F128 Peripheral Base Addresses
* @{
*****************************************************************************/
#define MSC_BASE (0x400C0000) /**< MSC base address */
#define EMU_BASE (0x400C6000) /**< EMU base address */
#define RMU_BASE (0x400CA000) /**< RMU base address */
#define CMU_BASE (0x400C8000) /**< CMU base address */
#define AES_BASE (0x400E0000) /**< AES base address */
#define EBI_BASE (0x40008000) /**< EBI base address */
#define GPIO_BASE (0x40006000) /**< GPIO base address */
#define PRS_BASE (0x400CC000) /**< PRS base address */
#define DMA_BASE (0x400C2000) /**< DMA base address */
#define TIMER0_BASE (0x40010000) /**< TIMER0 base address */
#define TIMER1_BASE (0x40010400) /**< TIMER1 base address */
#define TIMER2_BASE (0x40010800) /**< TIMER2 base address */
#define USART0_BASE (0x4000C000) /**< USART0 base address */
#define USART1_BASE (0x4000C400) /**< USART1 base address */
#define USART2_BASE (0x4000C800) /**< USART2 base address */
#define UART0_BASE (0x4000E000) /**< UART0 base address */
#define LEUART0_BASE (0x40084000) /**< LEUART0 base address */
#define LEUART1_BASE (0x40084400) /**< LEUART1 base address */
#define LETIMER0_BASE (0x40082000) /**< LETIMER0 base address */
#define PCNT0_BASE (0x40086000) /**< PCNT0 base address */
#define PCNT1_BASE (0x40086400) /**< PCNT1 base address */
#define PCNT2_BASE (0x40086800) /**< PCNT2 base address */
#define I2C0_BASE (0x4000A000) /**< I2C0 base address */
#define ADC0_BASE (0x40002000) /**< ADC0 base address */
#define DAC0_BASE (0x40004000) /**< DAC0 base address */
#define ACMP0_BASE (0x40001000) /**< ACMP0 base address */
#define ACMP1_BASE (0x40001400) /**< ACMP1 base address */
#define VCMP_BASE (0x40000000) /**< VCMP base address */
#define LCD_BASE (0x4008A000) /**< LCD base address */
#define RTC_BASE (0x40080000) /**< RTC base address */
#define WDOG_BASE (0x40088000) /**< WDOG base address */
#define DEVINFO_BASE (0x0FE081F0UL) /**< DEVINFO base address */
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
/**
* @}
*/
/**************************************************************************//**
*
* @defgroup EFM32G890F128_Peripheral_Declaration EFM32G890F128 Peripheral Declaration
* @{
*****************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
/**
* @}
*/
/**************************************************************************//**
*
* @defgroup EFM32G890F128_BitFields EFM32G890F128 Bit Fields
* @{
*****************************************************************************/
/**************************************************************************//**
*
* @addtogroup EFM32G890F128_PRS
* @{
*****************************************************************************/
#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */
#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
#define PRS_USART2_IRTX ((18 << 16) + 0) /**< PRS USART 2 IRDA out */
#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
#define PRS_UART0_IRTX ((41 << 16) + 0) /**< PRS USART 0 IRDA out */
#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */
#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
/**
* @}
*/
/**************************************************************************//**
*
* @defgroup EFM32G890F128_DMA_Channel_Select EFM32G890F128 DMA Channel Select
* @{
*****************************************************************************/
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
/**
* @}
*/
/**
* @addtogroup EFM32G890F128_TIMER
* @{
*/
/** Bit fields for TIMER CTRL */
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
#define _TIMER_CTRL_MASK 0x0F030FFBUL /**< Mask for TIMER_CTRL */
#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define TIMER_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_MODE_UP (0x00000000UL << 0) /**< Shifted mode UP for TIMER_CTRL */
#define TIMER_CTRL_MODE_DOWN (0x00000001UL << 0) /**< Shifted mode DOWN for TIMER_CTRL */
#define TIMER_CTRL_MODE_UPDOWN (0x00000002UL << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
#define TIMER_CTRL_MODE_QDEC (0x00000003UL << 0) /**< Shifted mode QDEC for TIMER_CTRL */
#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
#define TIMER_CTRL_SYNC (1 << 3) /**< Timer Start/Stop/Reload Synchronization */
#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
#define TIMER_CTRL_SYNC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_OSMEN (1 << 4) /**< One-shot Mode Enable */
#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
#define TIMER_CTRL_OSMEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_QEM (1 << 5) /**< Quadrature Decoder Mode Selection */
#define _TIMER_CTRL_QEM_SHIFT 5 /**< Shift value for TIMER_QEM */
#define _TIMER_CTRL_QEM_MASK 0x20UL /**< Bit mask for TIMER_QEM */
#define TIMER_CTRL_QEM_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_QEM_X2 (0x00000000UL << 5) /**< Shifted mode X2 for TIMER_CTRL */
#define TIMER_CTRL_QEM_X4 (0x00000001UL << 5) /**< Shifted mode X4 for TIMER_CTRL */
#define _TIMER_CTRL_QEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_QEM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
#define _TIMER_CTRL_QEM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
#define TIMER_CTRL_DEBUGRUN (1 << 6) /**< Debug Mode Run Enable */
#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
#define TIMER_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_DMACLRACT (1 << 7) /**< DMA Request Clear on Active */
#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
#define TIMER_CTRL_DMACLRACT_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
#define TIMER_CTRL_RISEA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_RISEA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CTRL */
#define TIMER_CTRL_RISEA_START (0x00000001UL << 8) /**< Shifted mode START for TIMER_CTRL */
#define TIMER_CTRL_RISEA_STOP (0x00000002UL << 8) /**< Shifted mode STOP for TIMER_CTRL */
#define TIMER_CTRL_RISEA_RELOADSTART (0x00000003UL << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
#define TIMER_CTRL_FALLA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_FALLA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CTRL */
#define TIMER_CTRL_FALLA_START (0x00000001UL << 10) /**< Shifted mode START for TIMER_CTRL */
#define TIMER_CTRL_FALLA_STOP (0x00000002UL << 10) /**< Shifted mode STOP for TIMER_CTRL */
#define TIMER_CTRL_FALLA_RELOADSTART (0x00000003UL << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define TIMER_CTRL_CLKSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (0x00000000UL << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_CC1 (0x00000001UL << 16) /**< Shifted mode CC1 for TIMER_CTRL */
#define TIMER_CTRL_CLKSEL_TIMEROUF (0x00000002UL << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
#define TIMER_CTRL_PRESC_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV1 (0x00000000UL << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV2 (0x00000001UL << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV4 (0x00000002UL << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV8 (0x00000003UL << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV16 (0x00000004UL << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV32 (0x00000005UL << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV64 (0x00000006UL << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV128 (0x00000007UL << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV256 (0x00000008UL << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV512 (0x00000009UL << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
#define TIMER_CTRL_PRESC_DIV1024 (0x0000000AUL << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
/** Bit fields for TIMER CMD */
#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
#define TIMER_CMD_START (1 << 0) /**< Start Timer */
#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
#define TIMER_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
#define TIMER_CMD_STOP (1 << 1) /**< Stop Timer */
#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
#define TIMER_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
/** Bit fields for TIMER STATUS */
#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
#define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */
#define TIMER_STATUS_RUNNING (1 << 0) /**< Running */
#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
#define TIMER_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_DIR (1 << 1) /**< Direction */
#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
#define TIMER_STATUS_DIR_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_DIR_UP (0x00000000UL << 1) /**< Shifted mode UP for TIMER_STATUS */
#define TIMER_STATUS_DIR_DOWN (0x00000001UL << 1) /**< Shifted mode DOWN for TIMER_STATUS */
#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
#define TIMER_STATUS_TOPBV (1 << 2) /**< TOPB Valid */
#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
#define TIMER_STATUS_TOPBV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV0 (1 << 8) /**< CC0 CCVB Valid */
#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
#define TIMER_STATUS_CCVBV0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV1 (1 << 9) /**< CC1 CCVB Valid */
#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
#define TIMER_STATUS_CCVBV1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCVBV2 (1 << 10) /**< CC2 CCVB Valid */
#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
#define TIMER_STATUS_CCVBV2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV0 (1 << 16) /**< CC0 Input Capture Valid */
#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
#define TIMER_STATUS_ICV0_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV1 (1 << 17) /**< CC1 Input Capture Valid */
#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
#define TIMER_STATUS_ICV1_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_ICV2 (1 << 18) /**< CC2 Input Capture Valid */
#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
#define TIMER_STATUS_ICV2_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0 (1 << 24) /**< CC0 Polarity */
#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
#define TIMER_STATUS_CCPOL0_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0_LOWRISE (0x00000000UL << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL0_HIGHFALL (0x00000001UL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1 (1 << 25) /**< CC1 Polarity */
#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
#define TIMER_STATUS_CCPOL1_DEFAULT (0x00000000UL << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1_LOWRISE (0x00000000UL << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL1_HIGHFALL (0x00000001UL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2 (1 << 26) /**< CC2 Polarity */
#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
#define TIMER_STATUS_CCPOL2_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2_LOWRISE (0x00000000UL << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
#define TIMER_STATUS_CCPOL2_HIGHFALL (0x00000001UL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
/** Bit fields for TIMER IEN */
#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
#define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */
#define TIMER_IEN_OF (1 << 0) /**< Overflow Interrupt Enable */
#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define TIMER_IEN_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_UF (1 << 1) /**< Underflow Interrupt Enable */
#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define TIMER_IEN_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC0 (1 << 4) /**< CC Channel 0 Interrupt Enable */
#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define TIMER_IEN_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC1 (1 << 5) /**< CC Channel 1 Interrupt Enable */
#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define TIMER_IEN_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_CC2 (1 << 6) /**< CC Channel 2 Interrupt Enable */
#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define TIMER_IEN_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define TIMER_IEN_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define TIMER_IEN_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
#define TIMER_IEN_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define TIMER_IEN_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
/** Bit fields for TIMER IF */
#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
#define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */
#define TIMER_IF_OF (1 << 0) /**< Overflow Interrupt Flag */
#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define TIMER_IF_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_UF (1 << 1) /**< Underflow Interrupt Flag */
#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define TIMER_IF_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag */
#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define TIMER_IF_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag */
#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define TIMER_IF_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag */
#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define TIMER_IF_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define TIMER_IF_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define TIMER_IF_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
#define TIMER_IF_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define TIMER_IF_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IF */
#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
/** Bit fields for TIMER IFS */
#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
#define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */
#define TIMER_IFS_OF (1 << 0) /**< Overflow Interrupt Flag Set */
#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define TIMER_IFS_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_UF (1 << 1) /**< Underflow Interrupt Flag Set */
#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define TIMER_IFS_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Set */
#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define TIMER_IFS_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Set */
#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define TIMER_IFS_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Set */
#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define TIMER_IFS_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define TIMER_IFS_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define TIMER_IFS_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
#define TIMER_IFS_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define TIMER_IFS_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
/** Bit fields for TIMER IFC */
#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
#define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */
#define TIMER_IFC_OF (1 << 0) /**< Overflow Interrupt Flag Clear */
#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
#define TIMER_IFC_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_UF (1 << 1) /**< Underflow Interrupt Flag Clear */
#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
#define TIMER_IFC_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Clear */
#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
#define TIMER_IFC_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Clear */
#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
#define TIMER_IFC_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Clear */
#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
#define TIMER_IFC_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
#define TIMER_IFC_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
#define TIMER_IFC_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
#define TIMER_IFC_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
#define TIMER_IFC_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
/** Bit fields for TIMER TOP */
#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
#define TIMER_TOP_TOP_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
/** Bit fields for TIMER TOPB */
#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
#define TIMER_TOPB_TOPB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
/** Bit fields for TIMER CNT */
#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
#define TIMER_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
/** Bit fields for TIMER ROUTE */
#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */
#define _TIMER_ROUTE_MASK 0x00030707UL /**< Mask for TIMER_ROUTE */
#define _TIMER_ROUTE_CCPEN_SHIFT 0 /**< Shift value for TIMER_CCPEN */
#define _TIMER_ROUTE_CCPEN_MASK 0x7UL /**< Bit mask for TIMER_CCPEN */
#define TIMER_ROUTE_CCPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_CCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_CDTIPEN_SHIFT 8 /**< Shift value for TIMER_CDTIPEN */
#define _TIMER_ROUTE_CDTIPEN_MASK 0x700UL /**< Bit mask for TIMER_CDTIPEN */
#define TIMER_ROUTE_CDTIPEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_CDTIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
#define _TIMER_ROUTE_LOCATION_MASK 0x30000UL /**< Bit mask for TIMER_LOCATION */
#define TIMER_ROUTE_LOCATION_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC0 (0x00000000UL << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC1 (0x00000001UL << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC2 (0x00000002UL << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
#define TIMER_ROUTE_LOCATION_LOC3 (0x00000003UL << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
/** Bit fields for TIMER CC_CTRL */
#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MASK 0x0F373F17UL /**< Mask for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define TIMER_CC_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_OFF (0x00000000UL << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (0x00000001UL << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (0x00000002UL << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_MODE_PWM (0x00000003UL << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_OUTINV (1 << 2) /**< Output Invert */
#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
#define TIMER_CC_CTRL_OUTINV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COIST (1 << 4) /**< Compare Output Initial State */
#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
#define TIMER_CC_CTRL_COIST_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
#define TIMER_CC_CTRL_CMOA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_TOGGLE (0x00000001UL << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_CLEAR (0x00000002UL << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CMOA_SET (0x00000003UL << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
#define TIMER_CC_CTRL_COFOA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_TOGGLE (0x00000001UL << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_CLEAR (0x00000002UL << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_COFOA_SET (0x00000003UL << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
#define TIMER_CC_CTRL_CUFOA_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_NONE (0x00000000UL << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_TOGGLE (0x00000001UL << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_CLEAR (0x00000002UL << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_CUFOA_SET (0x00000003UL << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
#define _TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL /**< Bit mask for TIMER_PRSSEL */
#define TIMER_CC_CTRL_PRSSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (0x00000000UL << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (0x00000001UL << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (0x00000002UL << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (0x00000003UL << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (0x00000004UL << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (0x00000005UL << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (0x00000006UL << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (0x00000007UL << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL (1 << 20) /**< Input Selection */
#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */
#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */
#define TIMER_CC_CTRL_INSEL_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL_PIN (0x00000000UL << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_INSEL_PRS (0x00000001UL << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT (1 << 21) /**< Digital Filter */
#define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */
#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */
#define TIMER_CC_CTRL_FILT_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT_DISABLE (0x00000000UL << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_FILT_ENABLE (0x00000001UL << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
#define TIMER_CC_CTRL_ICEDGE_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_RISING (0x00000000UL << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_FALLING (0x00000001UL << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_BOTH (0x00000002UL << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEDGE_NONE (0x00000003UL << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (0x00000000UL << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (0x00000001UL << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_RISING (0x00000002UL << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
#define TIMER_CC_CTRL_ICEVCTRL_FALLING (0x00000003UL << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
/** Bit fields for TIMER CC_CCV */
#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
#define TIMER_CC_CCV_CCV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
/** Bit fields for TIMER CC_CCVP */
#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
#define TIMER_CC_CCVP_CCVP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
/** Bit fields for TIMER CC_CCVB */
#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
#define TIMER_CC_CCVB_CCVB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
/** Bit fields for TIMER DTCTRL */
#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
#define _TIMER_DTCTRL_MASK 0x0100007FUL /**< Mask for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTEN (1 << 0) /**< DTI Enable */
#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
#define TIMER_DTCTRL_DTEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS (1 << 1) /**< DTI Automatic Start-up Functionality */
#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
#define TIMER_DTCTRL_DTDAS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS_NORESTART (0x00000000UL << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTDAS_RESTART (0x00000001UL << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTIPOL (1 << 2) /**< DTI Inactive Polarity */
#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define TIMER_DTCTRL_DTIPOL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTCINV (1 << 3) /**< DTI Complementary Output Invert. */
#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define TIMER_DTCTRL_DTCINV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
#define _TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL /**< Bit mask for TIMER_DTPRSSEL */
#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTPRSEN (1 << 24) /**< DTI PRS Source Enable */
#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
#define TIMER_DTCTRL_DTPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
/** Bit fields for TIMER DTTIME */
#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
#define TIMER_DTTIME_DTPRESC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV16 (0x00000004UL << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV32 (0x00000005UL << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV64 (0x00000006UL << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV128 (0x00000007UL << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV256 (0x00000008UL << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV512 (0x00000009UL << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
#define TIMER_DTTIME_DTPRESC_DIV1024 (0x0000000AUL << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
#define TIMER_DTTIME_DTRISET_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
#define TIMER_DTTIME_DTFALLT_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
/** Bit fields for TIMER DTFC */
#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
#define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_SHIFT 0 /**< Shift value for TIMER_DTPRSFSEL0 */
#define _TIMER_DTFC_DTPRSFSEL0_MASK 0x7UL /**< Bit mask for TIMER_DTPRSFSEL0 */
#define TIMER_DTFC_DTPRSFSEL0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL0_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_SHIFT 8 /**< Shift value for TIMER_DTPRSFSEL1 */
#define _TIMER_DTFC_DTPRSFSEL1_MASK 0x700UL /**< Bit mask for TIMER_DTPRSFSEL1 */
#define TIMER_DTFC_DTPRSFSEL1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH0 (0x00000000UL << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH1 (0x00000001UL << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH2 (0x00000002UL << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH3 (0x00000003UL << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH4 (0x00000004UL << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH5 (0x00000005UL << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH6 (0x00000006UL << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
#define TIMER_DTFC_DTPRSFSEL1_PRSCH7 (0x00000007UL << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
#define _TIMER_DTFC_DTPRSFSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
#define TIMER_DTFC_DTFA_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTFA_NONE (0x00000000UL << 16) /**< Shifted mode NONE for TIMER_DTFC */
#define TIMER_DTFC_DTFA_INACTIVE (0x00000001UL << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
#define TIMER_DTFC_DTFA_CLEAR (0x00000002UL << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
#define TIMER_DTFC_DTFA_TRISTATE (0x00000003UL << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_SHIFT 24 /**< Shift value for TIMER_DTFSEN */
#define _TIMER_DTFC_DTFSEN_MASK 0xF000000UL /**< Bit mask for TIMER_DTFSEN */
#define TIMER_DTFC_DTFSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
#define TIMER_DTFC_DTFSEN_PRS0 (0x00000001UL << 24) /**< Shifted mode PRS0 for TIMER_DTFC */
#define TIMER_DTFC_DTFSEN_PRS1 (0x00000002UL << 24) /**< Shifted mode PRS1 for TIMER_DTFC */
#define TIMER_DTFC_DTFSEN_DEBUG (0x00000004UL << 24) /**< Shifted mode DEBUG for TIMER_DTFC */
#define TIMER_DTFC_DTFSEN_LOCKUP (0x00000008UL << 24) /**< Shifted mode LOCKUP for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFC */
#define _TIMER_DTFC_DTFSEN_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFC */
/** Bit fields for TIMER DTOGEN */
#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_SHIFT 0 /**< Shift value for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_MASK 0x3FUL /**< Bit mask for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CC0 (0x00000001UL << 0) /**< Shifted mode CC0 for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CC1 (0x00000002UL << 0) /**< Shifted mode CC1 for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CC2 (0x00000004UL << 0) /**< Shifted mode CC2 for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CDTI0 (0x00000008UL << 0) /**< Shifted mode CDTI0 for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CDTI1 (0x00000010UL << 0) /**< Shifted mode CDTI1 for TIMER_DTOGEN */
#define TIMER_DTOGEN_DTOGEN_CDTI2 (0x00000020UL << 0) /**< Shifted mode CDTI2 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CC0 0x00000001UL /**< Mode CC0 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CC1 0x00000002UL /**< Mode CC1 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CC2 0x00000004UL /**< Mode CC2 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CDTI0 0x00000008UL /**< Mode CDTI0 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CDTI1 0x00000010UL /**< Mode CDTI1 for TIMER_DTOGEN */
#define _TIMER_DTOGEN_DTOGEN_CDTI2 0x00000020UL /**< Mode CDTI2 for TIMER_DTOGEN */
/** Bit fields for TIMER DTFAULT */
#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_SHIFT 0 /**< Shift value for TIMER_DTFS */
#define _TIMER_DTFAULT_DTFS_MASK 0xFUL /**< Bit mask for TIMER_DTFS */
#define TIMER_DTFAULT_DTFS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTFS_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTFS_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTFS_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULT */
#define TIMER_DTFAULT_DTFS_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULT */
#define _TIMER_DTFAULT_DTFS_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULT */
/** Bit fields for TIMER DTFAULTC */
#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_SHIFT 0 /**< Shift value for TIMER_DTFSC */
#define _TIMER_DTFAULTC_DTFSC_MASK 0xFUL /**< Bit mask for TIMER_DTFSC */
#define TIMER_DTFAULTC_DTFSC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTFSC_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTFSC_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTFSC_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULTC */
#define TIMER_DTFAULTC_DTFSC_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULTC */
#define _TIMER_DTFAULTC_DTFSC_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULTC */
/** Bit fields for TIMER DTLOCK */
#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (0x0000CE80UL << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
/**
* @}
*/
/**
* @addtogroup EFM32G890F128_USART
* @{
*/
/** Bit fields for USART CTRL */
#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
#define _USART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for USART_CTRL */
#define USART_CTRL_SYNC (1 << 0) /**< USART Synchronous Mode */
#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
#define USART_CTRL_SYNC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_LOOPBK (1 << 1) /**< Loopback Enable */
#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
#define USART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_CCEN (1 << 2) /**< Collision Check Enable */
#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
#define USART_CTRL_CCEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_MPM (1 << 3) /**< Multi-Processor Mode */
#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
#define USART_CTRL_MPM_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_MPAB (1 << 4) /**< Multi-Processor Address-Bit */
#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
#define USART_CTRL_MPAB_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
#define USART_CTRL_OVS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_OVS_X16 (0x00000000UL << 5) /**< Shifted mode X16 for USART_CTRL */
#define USART_CTRL_OVS_X8 (0x00000001UL << 5) /**< Shifted mode X8 for USART_CTRL */
#define USART_CTRL_OVS_X6 (0x00000002UL << 5) /**< Shifted mode X6 for USART_CTRL */
#define USART_CTRL_OVS_X4 (0x00000003UL << 5) /**< Shifted mode X4 for USART_CTRL */
#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
#define USART_CTRL_CLKPOL (1 << 8) /**< Clock Polarity */
#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
#define USART_CTRL_CLKPOL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_CLKPOL_IDLELOW (0x00000000UL << 8) /**< Shifted mode IDLELOW for USART_CTRL */
#define USART_CTRL_CLKPOL_IDLEHIGH (0x00000001UL << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
#define USART_CTRL_CLKPHA (1 << 9) /**< Clock Edge For Setup/Sample */
#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
#define USART_CTRL_CLKPHA_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_CLKPHA_SAMPLELEADING (0x00000000UL << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
#define USART_CTRL_CLKPHA_SAMPLETRAILING (0x00000001UL << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
#define USART_CTRL_MSBF (1 << 10) /**< Most Significant Bit First */
#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
#define USART_CTRL_MSBF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_CSMA (1 << 11) /**< Action On Slave-Select In Master Mode */
#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
#define USART_CTRL_CSMA_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_CSMA_NOACTION (0x00000000UL << 11) /**< Shifted mode NOACTION for USART_CTRL */
#define USART_CTRL_CSMA_GOTOSLAVEMODE (0x00000001UL << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
#define USART_CTRL_TXBIL (1 << 12) /**< TX Buffer Interrupt Level */
#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
#define USART_CTRL_TXBIL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_TXBIL_EMPTY (0x00000000UL << 12) /**< Shifted mode EMPTY for USART_CTRL */
#define USART_CTRL_TXBIL_HALFFULL (0x00000001UL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
#define USART_CTRL_RXINV (1 << 13) /**< Receiver Input Invert */
#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
#define USART_CTRL_RXINV_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_TXINV (1 << 14) /**< Transmitter output Invert */
#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
#define USART_CTRL_TXINV_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_CSINV (1 << 15) /**< Chip Select Invert */
#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
#define USART_CTRL_CSINV_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_AUTOCS (1 << 16) /**< Automatic Chip Select */
#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
#define USART_CTRL_AUTOCS_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_AUTOTRI (1 << 17) /**< Automatic TX Tristate */
#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
#define USART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_SCMODE (1 << 18) /**< SmartCard Mode */
#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
#define USART_CTRL_SCMODE_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_SCRETRANS (1 << 19) /**< SmartCard Retransmit */
#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
#define USART_CTRL_SCRETRANS_DEFAULT (0x00000000UL << 19) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_SKIPPERRF (1 << 20) /**< Skip Parity Error Frames */
#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
#define USART_CTRL_SKIPPERRF_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_BIT8DV (1 << 21) /**< Bit 8 Default Value */
#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
#define USART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_ERRSDMA (1 << 22) /**< Halt DMA On Error */
#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
#define USART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 22) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_ERRSRX (1 << 23) /**< Disable RX On Error */
#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
#define USART_CTRL_ERRSRX_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_ERRSTX (1 << 24) /**< Disable TX On Error */
#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
#define USART_CTRL_ERRSTX_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
#define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
#define USART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_TXDELAY_NONE (0x00000000UL << 26) /**< Shifted mode NONE for USART_CTRL */
#define USART_CTRL_TXDELAY_SINGLE (0x00000001UL << 26) /**< Shifted mode SINGLE for USART_CTRL */
#define USART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 26) /**< Shifted mode DOUBLE for USART_CTRL */
#define USART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 26) /**< Shifted mode TRIPLE for USART_CTRL */
#define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */
#define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */
#define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */
#define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */
#define USART_CTRL_BYTESWAP (1 << 28) /**< Byteswap In Double Accesses */
#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
#define USART_CTRL_BYTESWAP_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for USART_CTRL */
#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
/** Bit fields for USART FRAME */
#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
#define USART_FRAME_DATABITS_FOUR (0x00000001UL << 0) /**< Shifted mode FOUR for USART_FRAME */
#define USART_FRAME_DATABITS_FIVE (0x00000002UL << 0) /**< Shifted mode FIVE for USART_FRAME */
#define USART_FRAME_DATABITS_SIX (0x00000003UL << 0) /**< Shifted mode SIX for USART_FRAME */
#define USART_FRAME_DATABITS_SEVEN (0x00000004UL << 0) /**< Shifted mode SEVEN for USART_FRAME */
#define USART_FRAME_DATABITS_DEFAULT (0x00000005UL << 0) /**< Shifted mode DEFAULT for USART_FRAME */
#define USART_FRAME_DATABITS_EIGHT (0x00000005UL << 0) /**< Shifted mode EIGHT for USART_FRAME */
#define USART_FRAME_DATABITS_NINE (0x00000006UL << 0) /**< Shifted mode NINE for USART_FRAME */
#define USART_FRAME_DATABITS_TEN (0x00000007UL << 0) /**< Shifted mode TEN for USART_FRAME */
#define USART_FRAME_DATABITS_ELEVEN (0x00000008UL << 0) /**< Shifted mode ELEVEN for USART_FRAME */
#define USART_FRAME_DATABITS_TWELVE (0x00000009UL << 0) /**< Shifted mode TWELVE for USART_FRAME */
#define USART_FRAME_DATABITS_THIRTEEN (0x0000000AUL << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
#define USART_FRAME_DATABITS_FOURTEEN (0x0000000BUL << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
#define USART_FRAME_DATABITS_FIFTEEN (0x0000000CUL << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
#define USART_FRAME_DATABITS_SIXTEEN (0x0000000DUL << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
#define USART_FRAME_PARITY_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_FRAME */
#define USART_FRAME_PARITY_NONE (0x00000000UL << 8) /**< Shifted mode NONE for USART_FRAME */
#define USART_FRAME_PARITY_EVEN (0x00000002UL << 8) /**< Shifted mode EVEN for USART_FRAME */
#define USART_FRAME_PARITY_ODD (0x00000003UL << 8) /**< Shifted mode ODD for USART_FRAME */
#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
#define USART_FRAME_STOPBITS_HALF (0x00000000UL << 12) /**< Shifted mode HALF for USART_FRAME */
#define USART_FRAME_STOPBITS_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for USART_FRAME */
#define USART_FRAME_STOPBITS_ONE (0x00000001UL << 12) /**< Shifted mode ONE for USART_FRAME */
#define USART_FRAME_STOPBITS_ONEANDAHALF (0x00000002UL << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
#define USART_FRAME_STOPBITS_TWO (0x00000003UL << 12) /**< Shifted mode TWO for USART_FRAME */
#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
/** Bit fields for USART TRIGCTRL */
#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
#define _USART_TRIGCTRL_MASK 0x00000037UL /**< Mask for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
#define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
#define USART_TRIGCTRL_TSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
#define USART_TRIGCTRL_TSEL_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
#define USART_TRIGCTRL_RXTEN (1 << 4) /**< Receive Trigger Enable */
#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
#define USART_TRIGCTRL_RXTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_TXTEN (1 << 5) /**< Transmit Trigger Enable */
#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
#define USART_TRIGCTRL_TXTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
/** Bit fields for USART CMD */
#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
#define USART_CMD_RXEN (1 << 0) /**< Receiver Enable */
#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
#define USART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_RXDIS (1 << 1) /**< Receiver Disable */
#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
#define USART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_TXEN (1 << 2) /**< Transmitter Enable */
#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
#define USART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */
#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
#define USART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_MASTEREN (1 << 4) /**< Master Enable */
#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
#define USART_CMD_MASTEREN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_MASTERDIS (1 << 5) /**< Master Disable */
#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
#define USART_CMD_MASTERDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_RXBLOCKEN (1 << 6) /**< Receiver Block Enable */
#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
#define USART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_RXBLOCKDIS (1 << 7) /**< Receiver Block Disable */
#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
#define USART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_TXTRIEN (1 << 8) /**< Transmitter Tristate Enable */
#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
#define USART_CMD_TXTRIEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_TXTRIDIS (1 << 9) /**< Transmitter Tristate Disable */
#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
#define USART_CMD_TXTRIDIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_CLEARTX (1 << 10) /**< Clear TX */
#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
#define USART_CMD_CLEARTX_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
#define USART_CMD_CLEARRX (1 << 11) /**< Clear RX */
#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
#define USART_CMD_CLEARRX_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CMD */
#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
/** Bit fields for USART STATUS */
#define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */
#define _USART_STATUS_MASK 0x000001FFUL /**< Mask for USART_STATUS */
#define USART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */
#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
#define USART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */
#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
#define USART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_MASTER (1 << 2) /**< SPI Master Mode */
#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
#define USART_STATUS_MASTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_RXBLOCK (1 << 3) /**< Block Incoming Data */
#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
#define USART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_TXTRI (1 << 4) /**< Transmitter Tristated */
#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
#define USART_STATUS_TXTRI_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_TXC (1 << 5) /**< TX Complete */
#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
#define USART_STATUS_TXC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_TXBL (1 << 6) /**< TX Buffer Level */
#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
#define USART_STATUS_TXBL_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_RXDATAV (1 << 7) /**< RX Data Valid */
#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
#define USART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_RXFULL (1 << 8) /**< RX FIFO Full */
#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
#define USART_STATUS_RXFULL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_STATUS */
#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
/** Bit fields for USART CLKDIV */
#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
#define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */
#define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
#define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
#define USART_CLKDIV_DIV_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */
#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
/** Bit fields for USART RXDATAX */
#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
#define USART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
#define USART_RXDATAX_PERR (1 << 14) /**< Data Parity Error */
#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
#define USART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
#define USART_RXDATAX_FERR (1 << 15) /**< Data Framing Error */
#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
#define USART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
/** Bit fields for USART RXDATA */
#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
#define USART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
/** Bit fields for USART RXDOUBLEX */
#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
#define USART_RXDOUBLEX_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
#define USART_RXDOUBLEX_PERR0 (1 << 14) /**< Data Parity Error 0 */
#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
#define USART_RXDOUBLEX_PERR0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
#define USART_RXDOUBLEX_FERR0 (1 << 15) /**< Data Framing Error 0 */
#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
#define USART_RXDOUBLEX_FERR0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
#define USART_RXDOUBLEX_RXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
#define USART_RXDOUBLEX_PERR1 (1 << 30) /**< Data Parity Error 1 */
#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
#define USART_RXDOUBLEX_PERR1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
#define USART_RXDOUBLEX_FERR1 (1 << 31) /**< Data Framing Error 1 */
#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
#define USART_RXDOUBLEX_FERR1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
/** Bit fields for USART RXDOUBLE */
#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
#define USART_RXDOUBLE_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
#define USART_RXDOUBLE_RXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
/** Bit fields for USART RXDATAXP */
#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
#define USART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
#define USART_RXDATAXP_PERRP (1 << 14) /**< Data Parity Error Peek */
#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
#define USART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
#define USART_RXDATAXP_FERRP (1 << 15) /**< Data Framing Error Peek */