/** | |
* \file | |
* | |
* Copyright (c) 2013 Atmel Corporation. All rights reserved. | |
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* \asf_license_start | |
* | |
* \page License | |
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* Redistribution and use in source and binary forms, with or without | |
* modification, are permitted provided that the following conditions are met: | |
* | |
* 1. Redistributions of source code must retain the above copyright notice, | |
* this list of conditions and the following disclaimer. | |
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* 2. Redistributions in binary form must reproduce the above copyright notice, | |
* this list of conditions and the following disclaimer in the documentation | |
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* 3. The name of Atmel may not be used to endorse or promote products derived | |
* from this software without specific prior written permission. | |
* | |
* 4. This software may only be redistributed and used in connection with an | |
* Atmel microcontroller product. | |
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED | |
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*/ | |
#ifndef _SAM4E_CMCC_INSTANCE_ | |
#define _SAM4E_CMCC_INSTANCE_ | |
/* ========== Register definition for CMCC peripheral ========== */ | |
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) | |
#define REG_CMCC_TYPE (0x400C4000U) /**< \brief (CMCC) Cache Type Register */ | |
#define REG_CMCC_CFG (0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */ | |
#define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */ | |
#define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */ | |
#define REG_CMCC_MAINT0 (0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */ | |
#define REG_CMCC_MAINT1 (0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */ | |
#define REG_CMCC_MCFG (0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */ | |
#define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ | |
#define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ | |
#define REG_CMCC_MSR (0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */ | |
#else | |
#define REG_CMCC_TYPE (*(RoReg*)0x400C4000U) /**< \brief (CMCC) Cache Type Register */ | |
#define REG_CMCC_CFG (*(RwReg*)0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */ | |
#define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */ | |
#define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */ | |
#define REG_CMCC_MAINT0 (*(WoReg*)0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */ | |
#define REG_CMCC_MAINT1 (*(WoReg*)0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */ | |
#define REG_CMCC_MCFG (*(RwReg*)0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */ | |
#define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */ | |
#define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */ | |
#define REG_CMCC_MSR (*(RoReg*)0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */ | |
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ | |
#endif /* _SAM4E_CMCC_INSTANCE_ */ |