############################################################################ | |
## This system.ucf file is generated by Base System Builder based on the | |
## settings in the selected Xilinx Board Definition file. Please add other | |
## user constraints to this file based on customer design specifications. | |
############################################################################ | |
Net sys_clk_pin LOC=AE14; | |
Net sys_clk_pin IOSTANDARD = LVCMOS33; | |
Net sys_rst_pin LOC=D6; | |
Net sys_rst_pin PULLUP; | |
## System level constraints | |
Net sys_clk_pin TNM_NET = sys_clk_pin; | |
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; | |
Net sys_rst_pin TIG; | |
## FPGA pin constraints | |
Net fpga_0_RS232_Uart_RX_pin LOC=W2; | |
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; | |
Net fpga_0_RS232_Uart_TX_pin LOC=W1; | |
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; | |
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; | |
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; |