| setup() | |
| { | |
| __var Reg; | |
| // Enable I Cache | |
| // Disable MMU and enable ICache | |
| Reg = __jtagCP15ReadReg(1, 0, 0, 0); | |
| Reg &= 0xFFFFFFFA; | |
| Reg |= 1<<12; | |
| __jtagCP15WriteReg(1, 0, 0, 0, Reg); | |
| __writeMemory16(0x0000FF41, 0xFCFE721C, "Memory"); // set PIPC7.6 direction controlled by alt.WE0 | |
| __writeMemory16(0x0000FF41, 0xFCFE341C, "Memory"); // set PMC7.6 to be alt.WE0 | |
| __writeMemory16(0x0000FFFF, 0xFCFE7220, "Memory"); // set PIPC8 direction controlled by alt.A8-A23 | |
| __writeMemory16(0x0000FFFF, 0xFCFE3420, "Memory"); // set PMC8 to be alt.A8-A23 | |
| __writeMemory16(0x00000003, 0xFCFE7224, "Memory"); // set PIPC9 direction controlled by alt.A24-A25 | |
| __writeMemory16(0x00000003, 0xFCFE3424, "Memory"); // set PMC9 to be alt.A24-A25 | |
| __writeMemory16(0x00000080, 0xFCFE720C, "Memory"); // set PIPC3 direction controlled by alt.CS1 | |
| __writeMemory16(0x00000080, 0xFCFE340C, "Memory"); // set PMC3 to be alt.CS1 | |
| __writeMemory16(0x00000080, 0xFCFE360C, "Memory"); // set PFCE3 to be alt.CS1 | |
| __writeMemory16(0x00000080, 0xFCFE3A0C, "Memory"); // set PFCAE3 to be alt.CS1 | |
| } | |
| execUserPreload() | |
| { | |
| __message "----- Prepare hardware for debug -----\n"; | |
| __hwReset(0); | |
| setup(); | |
| } |