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/****************************************************************************************************//**
* @file XMC1300.h
*
* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
* XMC1300 from Infineon.
*
* @version V1.0.6 (Reference Manual v1.0)
* @date 26. March 2013
*
* @note Generated with SVDConv V2.78b
* from CMSIS SVD File 'XMC1300_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),
*******************************************************************************************************/
/** @addtogroup Infineon
* @{
*/
/** @addtogroup XMC1300
* @{
*/
#ifndef XMC1300_H
#define XMC1300_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum {
/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* --------------------- XMC1300 Specific Interrupt Numbers --------------------- */
SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */
SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */
SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */
ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */
ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */
ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */
ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */
MATH0_0_IRQn = 7, /*!< MATH0 SR0 Interrupt */
USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */
USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */
USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */
USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */
USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */
USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */
VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */
VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */
VADC0_G0_0_IRQn = 17, /*!< VADC SR2 Interrupt */
VADC0_G0_1_IRQn = 18, /*!< VADC SR3 Interrupt */
VADC0_G1_0_IRQn = 19, /*!< VADC SR4 Interrupt */
VADC0_G1_1_IRQn = 20, /*!< VADC SR5 Interrupt */
CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */
CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */
CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */
CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */
CCU80_0_IRQn = 25, /*!< CCU80 SR0 Interrupt */
CCU80_1_IRQn = 26, /*!< CCU80 SR1 Interrupt */
POSIF0_0_IRQn = 27, /*!< POSIF0 SR0 Interrupt */
POSIF0_1_IRQn = 28, /*!< POSIF1 SR1 Interrupt */
BCCU0_0_IRQn = 31, /*!< BCCU0 SR0 Interrupt */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
#include "system_XMC1300.h" /*!< XMC1300 System */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* Macro to modify desired bitfields of a register */
#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
((uint32_t)mask)) | \
(reg & ((uint32_t)~((uint32_t)mask)))
/* Macro to modify desired bitfields of a register */
#define WR_REG_SIZE(reg, mask, pos, val, size) { \
uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
reg = (uint##size##_t) (VAL2 | VAL4);\
}
/** Macro to read bitfields from a register */
#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
/** Macro to read bitfields from a register */
#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
(uint32_t)mask) >> pos) )
/** Macro to set a bit in register */
#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
/** Macro to clear a bit in register */
#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
/*
* ==========================================================================
* ---------- Interrupt Handler Definition ----------------------------------
* ==========================================================================
*/
#define IRQ_Hdlr_0 SCU_0_IRQHandler
#define IRQ_Hdlr_1 SCU_1_IRQHandler
#define IRQ_Hdlr_2 SCU_2_IRQHandler
#define IRQ_Hdlr_3 ERU0_0_IRQHandler
#define IRQ_Hdlr_4 ERU0_1_IRQHandler
#define IRQ_Hdlr_5 ERU0_2_IRQHandler
#define IRQ_Hdlr_6 ERU0_3_IRQHandler
#define IRQ_Hdlr_7 MATH0_0_IRQHandler
#define IRQ_Hdlr_9 USIC0_0_IRQHandler
#define IRQ_Hdlr_10 USIC0_1_IRQHandler
#define IRQ_Hdlr_11 USIC0_2_IRQHandler
#define IRQ_Hdlr_12 USIC0_3_IRQHandler
#define IRQ_Hdlr_13 USIC0_4_IRQHandler
#define IRQ_Hdlr_14 USIC0_5_IRQHandler
#define IRQ_Hdlr_15 VADC0_C0_0_IRQHandler
#define IRQ_Hdlr_16 VADC0_C0_1_IRQHandler
#define IRQ_Hdlr_17 VADC0_G0_0_IRQHandler
#define IRQ_Hdlr_18 VADC0_G0_1_IRQHandler
#define IRQ_Hdlr_19 VADC0_G1_0_IRQHandler
#define IRQ_Hdlr_20 VADC0_G1_1_IRQHandler
#define IRQ_Hdlr_21 CCU40_0_IRQHandler
#define IRQ_Hdlr_22 CCU40_1_IRQHandler
#define IRQ_Hdlr_23 CCU40_2_IRQHandler
#define IRQ_Hdlr_24 CCU40_3_IRQHandler
#define IRQ_Hdlr_25 CCU80_0_IRQHandler
#define IRQ_Hdlr_26 CCU80_1_IRQHandler
#define IRQ_Hdlr_27 POSIF0_0_IRQHandler
#define IRQ_Hdlr_28 POSIF0_1_IRQHandler
#define IRQ_Hdlr_31 BCCU0_0_IRQHandler
/*
* ==========================================================================
* ---------- Interrupt Handler retrieval macro -----------------------------
* ==========================================================================
*/
#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
/** @addtogroup Device_Peripheral_Registers
* @{
*/
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ PPB ================ */
/* ================================================================================ */
/**
* @brief Cortex-M0 Private Peripheral Block (PPB)
*/
typedef struct { /*!< (@ 0xE000E000) PPB Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
__IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
__IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
__I uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register */
__I uint32_t RESERVED1[56];
__IO uint32_t NVIC_ISER; /*!< (@ 0xE000E100) Interrupt Set-enable Register */
__I uint32_t RESERVED2[31];
__IO uint32_t NVIC_ICER; /*!< (@ 0xE000E180) IInterrupt Clear-enable Register */
__I uint32_t RESERVED3[31];
__IO uint32_t NVIC_ISPR; /*!< (@ 0xE000E200) Interrupt Set-pending Register */
__I uint32_t RESERVED4[31];
__IO uint32_t NVIC_ICPR; /*!< (@ 0xE000E280) Interrupt Clear-pending Register */
__I uint32_t RESERVED5[95];
__IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
__IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
__IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
__IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
__IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
__IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
__IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
__IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
__I uint32_t RESERVED6[568];
__I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
__IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
__I uint32_t RESERVED7;
__IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
__I uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
__I uint32_t RESERVED8;
__IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
__IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
__IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
} PPB_Type;
/* ================================================================================ */
/* ================ ERU [ERU0] ================ */
/* ================================================================================ */
/**
* @brief Event Request Unit 0 (ERU)
*/
typedef struct { /*!< (@ 0x40010600) ERU Structure */
__IO uint32_t EXISEL; /*!< (@ 0x40010600) Event Input Select */
__I uint32_t RESERVED0[3];
__IO uint32_t EXICON[4]; /*!< (@ 0x40010610) Event Input Control */
__IO uint32_t EXOCON[4]; /*!< (@ 0x40010620) Event Output Trigger Control */
} ERU_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ MATH ================ */
/* ================================================================================ */
/**
* @brief MATH Unit (MATH)
*/
typedef struct { /*!< (@ 0x40030000) MATH Structure */
__I uint32_t RESERVED0;
__IO uint32_t GLBCON; /*!< (@ 0x40030004) Global Control Register */
__I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */
__IO uint32_t EVIER; /*!< (@ 0x4003000C) Event Interrupt Enable Register */
__I uint32_t EVFR; /*!< (@ 0x40030010) Event Flag Register */
__O uint32_t EVFSR; /*!< (@ 0x40030014) Event Flag Set Register */
__O uint32_t EVFCR; /*!< (@ 0x40030018) Event Flag Clear Register */
__I uint32_t RESERVED1;
__IO uint32_t DVD; /*!< (@ 0x40030020) Dividend Register */
__IO uint32_t DVS; /*!< (@ 0x40030024) Divisor Register */
__I uint32_t QUOT; /*!< (@ 0x40030028) Quotient Register */
__I uint32_t RMD; /*!< (@ 0x4003002C) Remainder Register */
__I uint32_t DIVST; /*!< (@ 0x40030030) Divider Status Register */
__IO uint32_t DIVCON; /*!< (@ 0x40030034) Divider Control Register */
__I uint32_t RESERVED2[2];
__IO uint32_t STATC; /*!< (@ 0x40030040) CORDIC Status and Data Control Register */
__IO uint32_t CON; /*!< (@ 0x40030044) CORDIC Control Register */
__IO uint32_t CORDX; /*!< (@ 0x40030048) CORDIC X Data Register */
__IO uint32_t CORDY; /*!< (@ 0x4003004C) CORDIC Y Data Register */
__IO uint32_t CORDZ; /*!< (@ 0x40030050) CORDIC Z Data Register */
__I uint32_t CORRX; /*!< (@ 0x40030054) CORDIC X Result Register */
__I uint32_t CORRY; /*!< (@ 0x40030058) CORDIC Y Result Register */
__I uint32_t CORRZ; /*!< (@ 0x4003005C) CORDIC Z Result Register */
} MATH_Type;
/* ================================================================================ */
/* ================ PAU ================ */
/* ================================================================================ */
/**
* @brief PAU Unit (PAU)
*/
typedef struct { /*!< (@ 0x40000000) PAU Structure */
__I uint32_t RESERVED0[16];
__I uint32_t AVAIL0; /*!< (@ 0x40000040) Peripheral Availability Register 0 */
__I uint32_t AVAIL1; /*!< (@ 0x40000044) Peripheral Availability Register 1 */
__I uint32_t AVAIL2; /*!< (@ 0x40000048) Peripheral Availability Register 2 */
__I uint32_t RESERVED1[13];
__IO uint32_t PRIVDIS0; /*!< (@ 0x40000080) Peripheral Privilege Access Register 0 */
__IO uint32_t PRIVDIS1; /*!< (@ 0x40000084) Peripheral Privilege Access Register 1 */
__IO uint32_t PRIVDIS2; /*!< (@ 0x40000088) Peripheral Privilege Access Register 2 */
__I uint32_t RESERVED2[221];
__I uint32_t ROMSIZE; /*!< (@ 0x40000400) ROM Size Register */
__I uint32_t FLSIZE; /*!< (@ 0x40000404) Flash Size Register */
__I uint32_t RESERVED3[2];
__I uint32_t RAM0SIZE; /*!< (@ 0x40000410) RAM0 Size Register */
} PAU_Type;
/* ================================================================================ */
/* ================ NVM ================ */
/* ================================================================================ */
/**
* @brief NVM Unit (NVM)
*/
typedef struct { /*!< (@ 0x40050000) NVM Structure */
__I uint16_t NVMSTATUS; /*!< (@ 0x40050000) NVM Status Register */
__I uint16_t RESERVED0;
__IO uint16_t NVMPROG; /*!< (@ 0x40050004) NVM Programming Control Register */
__I uint16_t RESERVED1;
__IO uint16_t NVMCONF; /*!< (@ 0x40050008) NVM Configuration Register */
} NVM_Type;
/* ================================================================================ */
/* ================ WDT ================ */
/* ================================================================================ */
/**
* @brief Watch Dog Timer (WDT)
*/
typedef struct { /*!< (@ 0x40020000) WDT Structure */
__I uint32_t ID; /*!< (@ 0x40020000) WDT Module ID Register */
__IO uint32_t CTR; /*!< (@ 0x40020004) WDT Control Register */
__O uint32_t SRV; /*!< (@ 0x40020008) WDT Service Register */
__I uint32_t TIM; /*!< (@ 0x4002000C) WDT Timer Register */
__IO uint32_t WLB; /*!< (@ 0x40020010) WDT Window Lower Bound Register */
__IO uint32_t WUB; /*!< (@ 0x40020014) WDT Window Upper Bound Register */
__I uint32_t WDTSTS; /*!< (@ 0x40020018) WDT Status Register */
__O uint32_t WDTCLR; /*!< (@ 0x4002001C) WDT Clear Register */
} WDT_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ RTC ================ */
/* ================================================================================ */
/**
* @brief Real Time Clock (RTC)
*/
typedef struct { /*!< (@ 0x40010A00) RTC Structure */
__I uint32_t ID; /*!< (@ 0x40010A00) RTC Module ID Register */
__IO uint32_t CTR; /*!< (@ 0x40010A04) RTC Control Register */
__I uint32_t RAWSTAT; /*!< (@ 0x40010A08) RTC Raw Service Request Register */
__I uint32_t STSSR; /*!< (@ 0x40010A0C) RTC Service Request Status Register */
__IO uint32_t MSKSR; /*!< (@ 0x40010A10) RTC Service Request Mask Register */
__O uint32_t CLRSR; /*!< (@ 0x40010A14) RTC Clear Service Request Register */
__IO uint32_t ATIM0; /*!< (@ 0x40010A18) RTC Alarm Time Register 0 */
__IO uint32_t ATIM1; /*!< (@ 0x40010A1C) RTC Alarm Time Register 1 */
__IO uint32_t TIM0; /*!< (@ 0x40010A20) RTC Time Register 0 */
__IO uint32_t TIM1; /*!< (@ 0x40010A24) RTC Time Register 1 */
} RTC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ PRNG ================ */
/* ================================================================================ */
/**
* @brief PRNG Unit (PRNG)
*/
typedef struct { /*!< (@ 0x48020000) PRNG Structure */
__IO uint16_t WORD; /*!< (@ 0x48020000) Pseudo RNG Word Register */
__I uint16_t RESERVED0;
__I uint16_t CHK; /*!< (@ 0x48020004) Pseudo RNG Status Check Register */
__I uint16_t RESERVED1[3];
__IO uint16_t CTRL; /*!< (@ 0x4802000C) Pseudo RNG Control Register */
} PRNG_Type;
/* ================================================================================ */
/* ================ USIC [USIC0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Interface Controller 0 (USIC)
*/
typedef struct { /*!< (@ 0x48000008) USIC Structure */
__I uint32_t ID; /*!< (@ 0x48000008) Module Identification Register */
} USIC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ USIC_CH [USIC0_CH0] ================ */
/* ================================================================================ */
/**
* @brief Universal Serial Interface Controller 0 (USIC_CH)
*/
typedef struct { /*!< (@ 0x48000000) USIC_CH Structure */
__I uint32_t RESERVED0;
__I uint32_t CCFG; /*!< (@ 0x48000004) Channel Configuration Register */
__I uint32_t RESERVED1;
__IO uint32_t KSCFG; /*!< (@ 0x4800000C) Kernel State Configuration Register */
__IO uint32_t FDR; /*!< (@ 0x48000010) Fractional Divider Register */
__IO uint32_t BRG; /*!< (@ 0x48000014) Baud Rate Generator Register */
__IO uint32_t INPR; /*!< (@ 0x48000018) Interrupt Node Pointer Register */
__IO uint32_t DX0CR; /*!< (@ 0x4800001C) Input Control Register 0 */
__IO uint32_t DX1CR; /*!< (@ 0x48000020) Input Control Register 1 */
__IO uint32_t DX2CR; /*!< (@ 0x48000024) Input Control Register 2 */
__IO uint32_t DX3CR; /*!< (@ 0x48000028) Input Control Register 3 */
__IO uint32_t DX4CR; /*!< (@ 0x4800002C) Input Control Register 4 */
__IO uint32_t DX5CR; /*!< (@ 0x48000030) Input Control Register 5 */
__IO uint32_t SCTR; /*!< (@ 0x48000034) Shift Control Register */
__IO uint32_t TCSR; /*!< (@ 0x48000038) Transmit Control/Status Register */
union {
__IO uint32_t PCR_IICMode; /*!< (@ 0x4800003C) Protocol Control Register [IIC Mode] */
__IO uint32_t PCR_IISMode; /*!< (@ 0x4800003C) Protocol Control Register [IIS Mode] */
__IO uint32_t PCR_SSCMode; /*!< (@ 0x4800003C) Protocol Control Register [SSC Mode] */
__IO uint32_t PCR; /*!< (@ 0x4800003C) Protocol Control Register */
__IO uint32_t PCR_ASCMode; /*!< (@ 0x4800003C) Protocol Control Register [ASC Mode] */
};
__IO uint32_t CCR; /*!< (@ 0x48000040) Channel Control Register */
__IO uint32_t CMTR; /*!< (@ 0x48000044) Capture Mode Timer Register */
union {
__IO uint32_t PSR_IICMode; /*!< (@ 0x48000048) Protocol Status Register [IIC Mode] */
__IO uint32_t PSR_IISMode; /*!< (@ 0x48000048) Protocol Status Register [IIS Mode] */
__IO uint32_t PSR_SSCMode; /*!< (@ 0x48000048) Protocol Status Register [SSC Mode] */
__IO uint32_t PSR; /*!< (@ 0x48000048) Protocol Status Register */
__IO uint32_t PSR_ASCMode; /*!< (@ 0x48000048) Protocol Status Register [ASC Mode] */
};
__O uint32_t PSCR; /*!< (@ 0x4800004C) Protocol Status Clear Register */
__I uint32_t RBUFSR; /*!< (@ 0x48000050) Receiver Buffer Status Register */
__I uint32_t RBUF; /*!< (@ 0x48000054) Receiver Buffer Register */
__I uint32_t RBUFD; /*!< (@ 0x48000058) Receiver Buffer Register for Debugger */
__I uint32_t RBUF0; /*!< (@ 0x4800005C) Receiver Buffer Register 0 */
__I uint32_t RBUF1; /*!< (@ 0x48000060) Receiver Buffer Register 1 */
__I uint32_t RBUF01SR; /*!< (@ 0x48000064) Receiver Buffer 01 Status Register */
__O uint32_t FMR; /*!< (@ 0x48000068) Flag Modification Register */
__I uint32_t RESERVED2[5];
__IO uint32_t TBUF[32]; /*!< (@ 0x48000080) Transmit Buffer */
__IO uint32_t BYP; /*!< (@ 0x48000100) Bypass Data Register */
__IO uint32_t BYPCR; /*!< (@ 0x48000104) Bypass Control Register */
__IO uint32_t TBCTR; /*!< (@ 0x48000108) Transmitter Buffer Control Register */
__IO uint32_t RBCTR; /*!< (@ 0x4800010C) Receiver Buffer Control Register */
__I uint32_t TRBPTR; /*!< (@ 0x48000110) Transmit/Receive Buffer Pointer Register */
__IO uint32_t TRBSR; /*!< (@ 0x48000114) Transmit/Receive Buffer Status Register */
__O uint32_t TRBSCR; /*!< (@ 0x48000118) Transmit/Receive Buffer Status Clear Register */
__I uint32_t OUTR; /*!< (@ 0x4800011C) Receiver Buffer Output Register */
__I uint32_t OUTDR; /*!< (@ 0x48000120) Receiver Buffer Output Register L for Debugger */
__I uint32_t RESERVED3[23];
__O uint32_t IN[32]; /*!< (@ 0x48000180) Transmit FIFO Buffer */
} USIC_CH_TypeDef;
/* ================================================================================ */
/* ================ SCU_GENERAL ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_GENERAL)
*/
typedef struct { /*!< (@ 0x40010000) SCU_GENERAL Structure */
__I uint32_t DBGROMID; /*!< (@ 0x40010000) Debug System ROM ID Register */
__I uint32_t IDCHIP; /*!< (@ 0x40010004) Chip ID Register */
__I uint32_t ID; /*!< (@ 0x40010008) SCU Module ID Register */
__I uint32_t RESERVED0[2];
__IO uint32_t SSW0; /*!< (@ 0x40010014) SSW Register 0 */
__I uint32_t RESERVED1[3];
__IO uint32_t PASSWD; /*!< (@ 0x40010024) Password Register */
__I uint32_t RESERVED2[2];
__IO uint32_t CCUCON; /*!< (@ 0x40010030) CCU Control Register */
__I uint32_t RESERVED3[5];
__I uint32_t MIRRSTS; /*!< (@ 0x40010048) Mirror Update Status Register */
__I uint32_t RESERVED4[2];
__IO uint32_t PMTSR; /*!< (@ 0x40010054) Parity Memory Test Select Register */
} SCU_GENERAL_Type;
/* ================================================================================ */
/* ================ SCU_INTERRUPT ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_INTERRUPT)
*/
typedef struct { /*!< (@ 0x40010038) SCU_INTERRUPT Structure */
__I uint32_t SRRAW; /*!< (@ 0x40010038) SCU Raw Service Request Status */
__IO uint32_t SRMSK; /*!< (@ 0x4001003C) SCU Service Request Mask */
__O uint32_t SRCLR; /*!< (@ 0x40010040) SCU Service Request Clear */
__O uint32_t SRSET; /*!< (@ 0x40010044) SCU Service Request Set */
} SCU_INTERRUPT_TypeDef;
/* ================================================================================ */
/* ================ SCU_POWER ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_POWER)
*/
typedef struct { /*!< (@ 0x40010200) SCU_POWER Structure */
__I uint32_t VDESR; /*!< (@ 0x40010200) Voltage Detector Status Register */
} SCU_POWER_Type;
/* ================================================================================ */
/* ================ SCU_CLK ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_CLK)
*/
typedef struct { /*!< (@ 0x40010300) SCU_CLK Structure */
__IO uint32_t CLKCR; /*!< (@ 0x40010300) Clock Control Register */
__IO uint32_t PWRSVCR; /*!< (@ 0x40010304) Power Save Control Register */
__I uint32_t CGATSTAT0; /*!< (@ 0x40010308) Peripheral 0 Clock Gating Status */
__O uint32_t CGATSET0; /*!< (@ 0x4001030C) Peripheral 0 Clock Gating Set */
__O uint32_t CGATCLR0; /*!< (@ 0x40010310) Peripheral 0 Clock Gating Clear */
__IO uint32_t OSCCSR; /*!< (@ 0x40010314) Oscillator Control and Status Register */
} SCU_CLK_TypeDef;
/* ================================================================================ */
/* ================ SCU_RESET ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_RESET)
*/
typedef struct { /*!< (@ 0x40010400) SCU_RESET Structure */
__I uint32_t RSTSTAT; /*!< (@ 0x40010400) RCU Reset Status */
__O uint32_t RSTSET; /*!< (@ 0x40010404) RCU Reset Set Register */
__O uint32_t RSTCLR; /*!< (@ 0x40010408) RCU Reset Clear Register */
__IO uint32_t RSTCON; /*!< (@ 0x4001040C) RCU Reset Control Register */
} SCU_RESET_Type;
/* ================================================================================ */
/* ================ COMPARATOR ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (COMPARATOR)
*/
typedef struct { /*!< (@ 0x40010500) COMPARATOR Structure */
__IO uint32_t ORCCTRL; /*!< (@ 0x40010500) Out Of Range Comparator Control Register */
__I uint32_t RESERVED0[726];
__IO uint16_t ANACMP0; /*!< (@ 0x4001105C) Analog Comparator 0 Control Register */
__I uint16_t RESERVED1;
__IO uint16_t ANACMP1; /*!< (@ 0x40011060) Analog Comparator 1 Control Register */
__I uint16_t RESERVED2;
__IO uint16_t ANACMP2; /*!< (@ 0x40011064) Analog Comparator 2 Control Register */
} COMPARATOR_Type;
/* ================================================================================ */
/* ================ SCU_ANALOG ================ */
/* ================================================================================ */
/**
* @brief System Control Unit (SCU_ANALOG)
*/
typedef struct { /*!< (@ 0x40011000) SCU_ANALOG Structure */
__I uint32_t RESERVED0[9];
__IO uint16_t ANATSECTRL; /*!< (@ 0x40011024) Temperature Sensor Control Register */
__I uint16_t RESERVED1[5];
__IO uint16_t ANATSEIH; /*!< (@ 0x40011030) Temperature Sensor High Temperature Interrupt
Register */
__I uint16_t RESERVED2;
__IO uint16_t ANATSEIL; /*!< (@ 0x40011034) Temperature Sensor Low Temperature Interrupt
Register */
__I uint16_t RESERVED3[5];
__I uint16_t ANATSEMON; /*!< (@ 0x40011040) Temperature Sensor Counter2 Monitor Register */
__I uint16_t RESERVED4[7];
__IO uint16_t ANAVDEL; /*!< (@ 0x40011050) Voltage Detector Control Register */
__I uint16_t RESERVED5[13];
__IO uint16_t ANAOFFSET; /*!< (@ 0x4001106C) DCO1 Offset Register */
} SCU_ANALOG_Type;
/* ================================================================================ */
/* ================ CCU4 [CCU40] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 4 - Unit 0 (CCU4)
*/
typedef struct { /*!< (@ 0x48040000) CCU4 Structure */
__IO uint32_t GCTRL; /*!< (@ 0x48040000) Global Control Register */
__I uint32_t GSTAT; /*!< (@ 0x48040004) Global Status Register */
__O uint32_t GIDLS; /*!< (@ 0x48040008) Global Idle Set */
__O uint32_t GIDLC; /*!< (@ 0x4804000C) Global Idle Clear */
__O uint32_t GCSS; /*!< (@ 0x48040010) Global Channel Set */
__O uint32_t GCSC; /*!< (@ 0x48040014) Global Channel Clear */
__I uint32_t GCST; /*!< (@ 0x48040018) Global Channel Status */
__I uint32_t RESERVED0[25];
__I uint32_t MIDR; /*!< (@ 0x48040080) Module Identification */
} CCU4_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CCU4_CC4 [CCU40_CC40] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
*/
typedef struct { /*!< (@ 0x48040100) CCU4_CC4 Structure */
__IO uint32_t INS; /*!< (@ 0x48040100) Input Selector Configuration */
__IO uint32_t CMC; /*!< (@ 0x48040104) Connection Matrix Control */
__I uint32_t TCST; /*!< (@ 0x48040108) Slice Timer Status */
__O uint32_t TCSET; /*!< (@ 0x4804010C) Slice Timer Run Set */
__O uint32_t TCCLR; /*!< (@ 0x48040110) Slice Timer Clear */
__IO uint32_t TC; /*!< (@ 0x48040114) Slice Timer Control */
__IO uint32_t PSL; /*!< (@ 0x48040118) Passive Level Config */
__I uint32_t DIT; /*!< (@ 0x4804011C) Dither Config */
__IO uint32_t DITS; /*!< (@ 0x48040120) Dither Shadow Register */
__IO uint32_t PSC; /*!< (@ 0x48040124) Prescaler Control */
__IO uint32_t FPC; /*!< (@ 0x48040128) Floating Prescaler Control */
__IO uint32_t FPCS; /*!< (@ 0x4804012C) Floating Prescaler Shadow */
__I uint32_t PR; /*!< (@ 0x48040130) Timer Period Value */
__IO uint32_t PRS; /*!< (@ 0x48040134) Timer Shadow Period Value */
__I uint32_t CR; /*!< (@ 0x48040138) Timer Compare Value */
__IO uint32_t CRS; /*!< (@ 0x4804013C) Timer Shadow Compare Value */
__I uint32_t RESERVED0[12];
__IO uint32_t TIMER; /*!< (@ 0x48040170) Timer Value */
__I uint32_t CV[4]; /*!< (@ 0x48040174) Capture Register 0 */
__I uint32_t RESERVED1[7];
__I uint32_t INTS; /*!< (@ 0x480401A0) Interrupt Status */
__IO uint32_t INTE; /*!< (@ 0x480401A4) Interrupt Enable Control */
__IO uint32_t SRS; /*!< (@ 0x480401A8) Service Request Selector */
__O uint32_t SWS; /*!< (@ 0x480401AC) Interrupt Status Set */
__O uint32_t SWR; /*!< (@ 0x480401B0) Interrupt Status Clear */
__I uint32_t RESERVED2;
__I uint32_t ECRD0; /*!< (@ 0x480401B8) Extended Read Back 0 */
__I uint32_t ECRD1; /*!< (@ 0x480401BC) Extended Read Back 1 */
} CCU4_CC4_TypeDef;
/* ================================================================================ */
/* ================ CCU8 [CCU80] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 8 - Unit 0 (CCU8)
*/
typedef struct { /*!< (@ 0x50000000) CCU8 Structure */
__IO uint32_t GCTRL; /*!< (@ 0x50000000) Global Control Register */
__I uint32_t GSTAT; /*!< (@ 0x50000004) Global Status Register */
__O uint32_t GIDLS; /*!< (@ 0x50000008) Global Idle Set */
__O uint32_t GIDLC; /*!< (@ 0x5000000C) Global Idle Clear */
__O uint32_t GCSS; /*!< (@ 0x50000010) Global Channel Set */
__O uint32_t GCSC; /*!< (@ 0x50000014) Global Channel Clear */
__I uint32_t GCST; /*!< (@ 0x50000018) Global Channel status */
__IO uint32_t GPCHK; /*!< (@ 0x5000001C) Parity Checker Configuration */
__I uint32_t RESERVED0[24];
__I uint32_t MIDR; /*!< (@ 0x50000080) Module Identification */
} CCU8_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ CCU8_CC8 [CCU80_CC80] ================ */
/* ================================================================================ */
/**
* @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)
*/
typedef struct { /*!< (@ 0x50000100) CCU8_CC8 Structure */
__IO uint32_t INS; /*!< (@ 0x50000100) Input Selector Configuration */
__IO uint32_t CMC; /*!< (@ 0x50000104) Connection Matrix Control */
__I uint32_t TCST; /*!< (@ 0x50000108) Slice Timer Status */
__O uint32_t TCSET; /*!< (@ 0x5000010C) Slice Timer Run Set */
__O uint32_t TCCLR; /*!< (@ 0x50000110) Slice Timer Clear */
__IO uint32_t TC; /*!< (@ 0x50000114) Slice Timer Control */
__IO uint32_t PSL; /*!< (@ 0x50000118) Passive Level Config */
__I uint32_t DIT; /*!< (@ 0x5000011C) Dither Config */
__IO uint32_t DITS; /*!< (@ 0x50000120) Dither Shadow Register */
__IO uint32_t PSC; /*!< (@ 0x50000124) Prescaler Control */
__IO uint32_t FPC; /*!< (@ 0x50000128) Floating Prescaler Control */
__IO uint32_t FPCS; /*!< (@ 0x5000012C) Floating Prescaler Shadow */
__I uint32_t PR; /*!< (@ 0x50000130) Timer Period Value */
__IO uint32_t PRS; /*!< (@ 0x50000134) Timer Shadow Period Value */
__I uint32_t CR1; /*!< (@ 0x50000138) Channel 1 Compare Value */
__IO uint32_t CR1S; /*!< (@ 0x5000013C) Channel 1 Compare Shadow Value */
__I uint32_t CR2; /*!< (@ 0x50000140) Channel 2 Compare Value */
__IO uint32_t CR2S; /*!< (@ 0x50000144) Channel 2 Compare Shadow Value */
__IO uint32_t CHC; /*!< (@ 0x50000148) Channel Control */
__IO uint32_t DTC; /*!< (@ 0x5000014C) Dead Time Control */
__IO uint32_t DC1R; /*!< (@ 0x50000150) Channel 1 Dead Time Values */
__IO uint32_t DC2R; /*!< (@ 0x50000154) Channel 2 Dead Time Values */
__I uint32_t RESERVED0[6];
__IO uint32_t TIMER; /*!< (@ 0x50000170) Timer Value */
__I uint32_t CV[4]; /*!< (@ 0x50000174) Capture Register 0 */
__I uint32_t RESERVED1[7];
__I uint32_t INTS; /*!< (@ 0x500001A0) Interrupt Status */
__IO uint32_t INTE; /*!< (@ 0x500001A4) Interrupt Enable Control */
__IO uint32_t SRS; /*!< (@ 0x500001A8) Service Request Selector */
__O uint32_t SWS; /*!< (@ 0x500001AC) Interrupt Status Set */
__O uint32_t SWR; /*!< (@ 0x500001B0) Interrupt Status Clear */
__IO uint32_t STC; /*!< (@ 0x500001B4) Shadow transfer control */
__I uint32_t ECRD0; /*!< (@ 0x500001B8) Extended Read Back 0 */
__I uint32_t ECRD1; /*!< (@ 0x500001BC) Extended Read Back 1 */
} CCU8_CC8_TypeDef;
/* ================================================================================ */
/* ================ POSIF [POSIF0] ================ */
/* ================================================================================ */
/**
* @brief Position Interface 0 (POSIF)
*/
typedef struct { /*!< (@ 0x50010000) POSIF Structure */
__IO uint32_t PCONF; /*!< (@ 0x50010000) CORDIC Coprocessor configuration */
__IO uint32_t PSUS; /*!< (@ 0x50010004) CORDIC Coprocessor Suspend Config */
__O uint32_t PRUNS; /*!< (@ 0x50010008) CORDIC Coprocessor Run Bit Set */
__O uint32_t PRUNC; /*!< (@ 0x5001000C) CORDIC Coprocessor Run Bit Clear */
__I uint32_t PRUN; /*!< (@ 0x50010010) CORDIC Coprocessor Run Bit Status */
__I uint32_t RESERVED0[3];
__I uint32_t MIDR; /*!< (@ 0x50010020) Module Identification register */
__I uint32_t RESERVED1[3];
__I uint32_t HALP; /*!< (@ 0x50010030) Hall Sensor Patterns */
__IO uint32_t HALPS; /*!< (@ 0x50010034) Hall Sensor Shadow Patterns */
__I uint32_t RESERVED2[2];
__I uint32_t MCM; /*!< (@ 0x50010040) Multi-Channel Pattern */
__IO uint32_t MCSM; /*!< (@ 0x50010044) Multi-Channel Shadow Pattern */
__O uint32_t MCMS; /*!< (@ 0x50010048) Multi-Channel Pattern Control set */
__O uint32_t MCMC; /*!< (@ 0x5001004C) Multi-Channel Pattern Control clear */
__I uint32_t MCMF; /*!< (@ 0x50010050) Multi-Channel Pattern Control flag */
__I uint32_t RESERVED3[3];
__IO uint32_t QDC; /*!< (@ 0x50010060) Quadrature Decoder Control */
__I uint32_t RESERVED4[3];
__I uint32_t PFLG; /*!< (@ 0x50010070) CORDIC Coprocessor Interrupt Flags */
__IO uint32_t PFLGE; /*!< (@ 0x50010074) CORDIC Coprocessor Interrupt Enable */
__O uint32_t SPFLG; /*!< (@ 0x50010078) CORDIC Coprocessor Interrupt Set */
__O uint32_t RPFLG; /*!< (@ 0x5001007C) CORDIC Coprocessor Interrupt Clear */
__I uint32_t RESERVED5[32];
__I uint32_t PDBG; /*!< (@ 0x50010100) CORDIC Coprocessor Debug register */
} POSIF_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ VADC [VADC] ================ */
/* ================================================================================ */
/**
* @brief Analog to Digital Converter (VADC)
*/
typedef struct { /*!< (@ 0x48030000) VADC Structure */
__IO uint32_t CLC; /*!< (@ 0x48030000) Clock Control Register */
__I uint32_t RESERVED0;
__I uint32_t ID; /*!< (@ 0x48030008) Module Identification Register */
__I uint32_t RESERVED1[7];
__IO uint32_t OCS; /*!< (@ 0x48030028) OCDS Control and Status Register */
__I uint32_t RESERVED2[21];
__IO uint32_t GLOBCFG; /*!< (@ 0x48030080) Global Configuration Register */
__I uint32_t RESERVED3;
__IO uint32_t ACCPROT0; /*!< (@ 0x48030088) Access Protection Register */
__IO uint32_t ACCPROT1; /*!< (@ 0x4803008C) Access Protection Register */
__I uint32_t RESERVED4[4];
__IO uint32_t GLOBICLASS[2]; /*!< (@ 0x480300A0) Input Class Register, Global */
__I uint32_t RESERVED5[4];
__IO uint32_t GLOBBOUND; /*!< (@ 0x480300B8) Global Boundary Select Register */
__I uint32_t RESERVED6[9];
__IO uint32_t GLOBEFLAG; /*!< (@ 0x480300E0) Global Event Flag Register */
__I uint32_t RESERVED7[23];
__IO uint32_t GLOBEVNP; /*!< (@ 0x48030140) Global Event Node Pointer Register */
__I uint32_t RESERVED8[15];
__IO uint32_t BRSSEL[2]; /*!< (@ 0x48030180) Background Request Source Channel Select Register */
__I uint32_t RESERVED9[14];
__IO uint32_t BRSPND[2]; /*!< (@ 0x480301C0) Background Request Source Pending Register */
__I uint32_t RESERVED10[14];
__IO uint32_t BRSCTRL; /*!< (@ 0x48030200) Background Request Source Control Register */
__IO uint32_t BRSMR; /*!< (@ 0x48030204) Background Request Source Mode Register */
__I uint32_t RESERVED11[30];
__IO uint32_t GLOBRCR; /*!< (@ 0x48030280) Global Result Control Register */
__I uint32_t RESERVED12[31];
__IO uint32_t GLOBRES; /*!< (@ 0x48030300) Global Result Register */
__I uint32_t RESERVED13[31];
__IO uint32_t GLOBRESD; /*!< (@ 0x48030380) Global Result Register, Debug */
__I uint32_t RESERVED14[27];
__IO uint32_t EMUXSEL; /*!< (@ 0x480303F0) External Multiplexer Select Register */
} VADC_GLOBAL_TypeDef;
/* ================================================================================ */
/* ================ VADC_G [VADC_G0] ================ */
/* ================================================================================ */
/**
* @brief Analog to Digital Converter (VADC_G)
*/
typedef struct { /*!< (@ 0x48030400) VADC_G Structure */
__I uint32_t RESERVED0[32];
__IO uint32_t ARBCFG; /*!< (@ 0x48030480) Arbitration Configuration Register */
__IO uint32_t ARBPR; /*!< (@ 0x48030484) Arbitration Priority Register */
__IO uint32_t CHASS; /*!< (@ 0x48030488) Channel Assignment Register */
__IO uint32_t RRASS; /*!< (@ 0x4803048C) Result Assignment Register */
__I uint32_t RESERVED1[4];
__IO uint32_t ICLASS[2]; /*!< (@ 0x480304A0) Input Class Register 0 */
__I uint32_t RESERVED2[2];
__IO uint32_t ALIAS; /*!< (@ 0x480304B0) Alias Register */
__I uint32_t RESERVED3;
__IO uint32_t BOUND; /*!< (@ 0x480304B8) Boundary Select Register */
__I uint32_t RESERVED4;
__IO uint32_t SYNCTR; /*!< (@ 0x480304C0) Synchronization Control Register */
__I uint32_t RESERVED5;
__IO uint32_t BFL; /*!< (@ 0x480304C8) Boundary Flag Register */
__O uint32_t BFLS; /*!< (@ 0x480304CC) Boundary Flag Software Register */
__IO uint32_t BFLC; /*!< (@ 0x480304D0) Boundary Flag Control Register */
__IO uint32_t BFLNP; /*!< (@ 0x480304D4) Boundary Flag Node Pointer Register */
__I uint32_t RESERVED6[10];
__IO uint32_t QCTRL0; /*!< (@ 0x48030500) Queue 0 Source Control Register */
__IO uint32_t QMR0; /*!< (@ 0x48030504) Queue 0 Mode Register */
__I uint32_t QSR0; /*!< (@ 0x48030508) Queue 0 Status Register */
__I uint32_t Q0R0; /*!< (@ 0x4803050C) Queue 0 Register 0 */
union {
__I uint32_t QBUR0; /*!< (@ 0x48030510) Queue 0 Backup Register */
__O uint32_t QINR0; /*!< (@ 0x48030510) Queue 0 Input Register */
};
__I uint32_t RESERVED7[3];
__IO uint32_t ASCTRL; /*!< (@ 0x48030520) Autoscan Source Control Register */
__IO uint32_t ASMR; /*!< (@ 0x48030524) Autoscan Source Mode Register */
__IO uint32_t ASSEL; /*!< (@ 0x48030528) Autoscan Source Channel Select Register */
__IO uint32_t ASPND; /*!< (@ 0x4803052C) Autoscan Source Pending Register */
__I uint32_t RESERVED8[20];
__IO uint32_t CEFLAG; /*!< (@ 0x48030580) Channel Event Flag Register */
__IO uint32_t REFLAG; /*!< (@ 0x48030584) Result Event Flag Register */
__IO uint32_t SEFLAG; /*!< (@ 0x48030588) Source Event Flag Register */
__I uint32_t RESERVED9;
__O uint32_t CEFCLR; /*!< (@ 0x48030590) Channel Event Flag Clear Register */
__O uint32_t REFCLR; /*!< (@ 0x48030594) Result Event Flag Clear Register */
__O uint32_t SEFCLR; /*!< (@ 0x48030598) Source Event Flag Clear Register */
__I uint32_t RESERVED10;
__IO uint32_t CEVNP0; /*!< (@ 0x480305A0) Channel Event Node Pointer Register 0 */
__I uint32_t RESERVED11[3];
__IO uint32_t REVNP0; /*!< (@ 0x480305B0) Result Event Node Pointer Register 0 */
__IO uint32_t REVNP1; /*!< (@ 0x480305B4) Result Event Node Pointer Register 1 */
__I uint32_t RESERVED12[2];
__IO uint32_t SEVNP; /*!< (@ 0x480305C0) Source Event Node Pointer Register */
__I uint32_t RESERVED13;
__O uint32_t SRACT; /*!< (@ 0x480305C8) Service Request Software Activation Trigger */
__I uint32_t RESERVED14[9];
__IO uint32_t EMUXCTR; /*!< (@ 0x480305F0) E0ternal Multiplexer Control Register, Group
x */
__I uint32_t RESERVED15;
__IO uint32_t VFR; /*!< (@ 0x480305F8) Valid Flag Register, Group 0 */
__I uint32_t RESERVED16;
__IO uint32_t CHCTR[8]; /*!< (@ 0x48030600) Channel Ctrl. Reg. */
__I uint32_t RESERVED17[24];
__IO uint32_t RCR[16]; /*!< (@ 0x48030680) Result Control Reg. */
__I uint32_t RESERVED18[16];
__IO uint32_t RES[16]; /*!< (@ 0x48030700) Result Register */
__I uint32_t RESERVED19[16];
__I uint32_t RESD[16]; /*!< (@ 0x48030780) Result Register, Debug */
} VADC_G_TypeDef;
/* ================================================================================ */
/* ================ SHS [SHS0] ================ */
/* ================================================================================ */
/**
* @brief Sample and Hold ADC Sequencer (SHS)
*/
typedef struct { /*!< (@ 0x48034000) SHS Structure */
__I uint32_t RESERVED0[2];
__I uint32_t ID; /*!< (@ 0x48034008) Module Identification Register */
__I uint32_t RESERVED1[13];
__IO uint32_t SHSCFG; /*!< (@ 0x48034040) SHS Configuration Register */
__IO uint32_t STEPCFG; /*!< (@ 0x48034044) Stepper Configuration Register */
__I uint32_t RESERVED2[2];
__IO uint32_t LOOP; /*!< (@ 0x48034050) Loop Control Register */
__I uint32_t RESERVED3[11];
__IO uint32_t TIMCFG0; /*!< (@ 0x48034080) Timing Configuration Register 0 */
__IO uint32_t TIMCFG1; /*!< (@ 0x48034084) Timing Configuration Register 1 */
__I uint32_t RESERVED4[13];
__IO uint32_t CALCTR; /*!< (@ 0x480340BC) Calibration Control Register */
__IO uint32_t CALGC0; /*!< (@ 0x480340C0) Gain Calibration Control Register 0 */
__IO uint32_t CALGC1; /*!< (@ 0x480340C4) Gain Calibration Control Register 1 */
__I uint32_t RESERVED5[46];
__IO uint32_t GNCTR00; /*!< (@ 0x48034180) Gain Control Register 00 */
__I uint32_t RESERVED6[3];
__IO uint32_t GNCTR10; /*!< (@ 0x48034190) Gain Control Register 10 */
} SHS_Type;
/* ================================================================================ */
/* ================ BCCU [BCCU0] ================ */
/* ================================================================================ */
/**
* @brief BCCU Unit 0 (BCCU)
*/
typedef struct { /*!< (@ 0x50030000) BCCU Structure */
__IO uint32_t GLOBCON; /*!< (@ 0x50030000) Global Control */
__IO uint32_t GLOBCLK; /*!< (@ 0x50030004) Global Clock */
__I uint32_t ID; /*!< (@ 0x50030008) Module Identification */
__IO uint32_t CHEN; /*!< (@ 0x5003000C) Channel Enable */
__IO uint32_t CHOCON; /*!< (@ 0x50030010) Channel Output Control */
__IO uint32_t CHTRIG; /*!< (@ 0x50030014) Channel Trigger */
__IO uint32_t CHSTRCON; /*!< (@ 0x50030018) Channel Shadow Transfer */
__I uint32_t LTCHOL; /*!< (@ 0x5003001C) Last Trigger Channel Output Level */
__IO uint32_t DEEN; /*!< (@ 0x50030020) Dimming Engine Enable */
__IO uint32_t DESTRCON; /*!< (@ 0x50030024) Dimming Shadow Transfer */
__IO uint32_t GLOBDIM; /*!< (@ 0x50030028) Global Dimming Level */
__IO uint32_t EVIER; /*!< (@ 0x5003002C) Event Interrupt Enable */
__I uint32_t EVFR; /*!< (@ 0x50030030) Event Flag */
__O uint32_t EVFSR; /*!< (@ 0x50030034) Event Flag Set */
__O uint32_t EVFCR; /*!< (@ 0x50030038) Event Flag Clear */
} BCCU_Type;
/* ================================================================================ */
/* ================ BCCU_CH [BCCU0_CH0] ================ */
/* ================================================================================ */
/**
* @brief BCCU Unit 0 (BCCU_CH)
*/
typedef struct { /*!< (@ 0x5003003C) BCCU_CH Structure */
__IO uint32_t INTS; /*!< (@ 0x5003003C) Channel Intensit0 Shadow */
__I uint32_t INT; /*!< (@ 0x50030040) Channel Intensit0 */
__IO uint32_t CHCONFIG; /*!< (@ 0x50030044) Channel Configuration */
__IO uint32_t PKCMP; /*!< (@ 0x50030048) Packer Compare */
__IO uint32_t PKCNTR; /*!< (@ 0x5003004C) Packer Counter */
} BCCU_CH_Type;
/* ================================================================================ */
/* ================ BCCU_DE [BCCU0_DE0] ================ */
/* ================================================================================ */
/**
* @brief BCCU Unit 0 (BCCU_DE)
*/
typedef struct { /*!< (@ 0x5003017C) BCCU_DE Structure */
__IO uint32_t DLS; /*!< (@ 0x5003017C) Dimming Level Shadow */
__I uint32_t DL; /*!< (@ 0x50030180) Dimming Level */
__IO uint32_t DTT; /*!< (@ 0x50030184) Dimming Transition Time */
} BCCU_DE_Type;
/* ================================================================================ */
/* ================ PORT0 ================ */
/* ================================================================================ */
/**
* @brief Port 0 (PORT0)
*/
typedef struct { /*!< (@ 0x40040000) PORT0 Structure */
__IO uint32_t OUT; /*!< (@ 0x40040000) Port 0 Output Register */
__O uint32_t OMR; /*!< (@ 0x40040004) Port 0 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x40040010) Port 0 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x40040014) Port 0 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x40040018) Port 0 Input/Output Control Register 8 */
__IO uint32_t IOCR12; /*!< (@ 0x4004001C) Port 0 Input/Output Control Register 12 */
__I uint32_t RESERVED1;
__I uint32_t IN; /*!< (@ 0x40040024) Port 0 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PHCR0; /*!< (@ 0x40040040) Port 0 Pad Hysteresis Control Register 0 */
__IO uint32_t PHCR1; /*!< (@ 0x40040044) Port 0 Pad Hysteresis Control Register 1 */
__I uint32_t RESERVED3[6];
__I uint32_t PDISC; /*!< (@ 0x40040060) Port 0 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x40040070) Port 0 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x40040074) Port 0 Pin Hardware Select Register */
} PORT0_Type;
/* ================================================================================ */
/* ================ PORT1 ================ */
/* ================================================================================ */
/**
* @brief Port 1 (PORT1)
*/
typedef struct { /*!< (@ 0x40040100) PORT1 Structure */
__IO uint32_t OUT; /*!< (@ 0x40040100) Port 1 Output Register */
__O uint32_t OMR; /*!< (@ 0x40040104) Port 1 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x40040110) Port 1 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x40040114) Port 1 Input/Output Control Register 4 */
__I uint32_t RESERVED1[3];
__I uint32_t IN; /*!< (@ 0x40040124) Port 1 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PHCR0; /*!< (@ 0x40040140) Port 1 Pad Hysteresis Control Register 0 */
__I uint32_t RESERVED3[7];
__I uint32_t PDISC; /*!< (@ 0x40040160) Port 1 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x40040170) Port 1 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x40040174) Port 1 Pin Hardware Select Register */
} PORT1_Type;
/* ================================================================================ */
/* ================ PORT2 ================ */
/* ================================================================================ */
/**
* @brief Port 2 (PORT2)
*/
typedef struct { /*!< (@ 0x40040200) PORT2 Structure */
__IO uint32_t OUT; /*!< (@ 0x40040200) Port 2 Output Register */
__O uint32_t OMR; /*!< (@ 0x40040204) Port 2 Output Modification Register */
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR0; /*!< (@ 0x40040210) Port 2 Input/Output Control Register 0 */
__IO uint32_t IOCR4; /*!< (@ 0x40040214) Port 2 Input/Output Control Register 4 */
__IO uint32_t IOCR8; /*!< (@ 0x40040218) Port 2 Input/Output Control Register 8 */
__I uint32_t RESERVED1[2];
__I uint32_t IN; /*!< (@ 0x40040224) Port 2 Input Register */
__I uint32_t RESERVED2[6];
__IO uint32_t PHCR0; /*!< (@ 0x40040240) Port 2 Pad Hysteresis Control Register 0 */
__IO uint32_t PHCR1; /*!< (@ 0x40040244) Port 2 Pad Hysteresis Control Register 1 */
__I uint32_t RESERVED3[6];
__IO uint32_t PDISC; /*!< (@ 0x40040260) Port 2 Pin Function Decision Control Register */
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /*!< (@ 0x40040270) Port 2 Pin Power Save Register */
__IO uint32_t HWSEL; /*!< (@ 0x40040274) Port 2 Pin Hardware Select Register */
} PORT2_Type;
/* -------------------- End of section using anonymous unions ------------------- */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ struct 'PPB' Position & Mask ================ */
/* ================================================================================ */
/* -------------------------------- PPB_SYST_CSR -------------------------------- */
#define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
#define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
#define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
#define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
#define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
#define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
#define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
#define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
/* -------------------------------- PPB_SYST_RVR -------------------------------- */
#define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
#define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
/* -------------------------------- PPB_SYST_CVR -------------------------------- */
#define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
#define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
/* ------------------------------- PPB_SYST_CALIB ------------------------------- */
#define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
#define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
#define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
#define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
#define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
#define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
/* -------------------------------- PPB_NVIC_ISER ------------------------------- */
#define PPB_NVIC_ISER_SETENA_Pos 0 /*!< PPB NVIC_ISER: SETENA Position */
#define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER_SETENA_Pos) /*!< PPB NVIC_ISER: SETENA Mask */
/* -------------------------------- PPB_NVIC_ICER ------------------------------- */
#define PPB_NVIC_ICER_CLRENA_Pos 0 /*!< PPB NVIC_ICER: CLRENA Position */
#define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER_CLRENA_Pos) /*!< PPB NVIC_ICER: CLRENA Mask */
/* -------------------------------- PPB_NVIC_ISPR ------------------------------- */
#define PPB_NVIC_ISPR_SETPEND_Pos 0 /*!< PPB NVIC_ISPR: SETPEND Position */
#define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR_SETPEND_Pos) /*!< PPB NVIC_ISPR: SETPEND Mask */
/* -------------------------------- PPB_NVIC_ICPR ------------------------------- */
#define PPB_NVIC_ICPR_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR: CLRPEND Position */
#define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR_CLRPEND_Pos) /*!< PPB NVIC_ICPR: CLRPEND Mask */
/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
#define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
#define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
#define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
#define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
#define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
#define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
#define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
#define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
#define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
#define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
#define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
#define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
#define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
#define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
#define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
#define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
#define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
#define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
#define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
#define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
#define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
#define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
#define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
#define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
#define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
#define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
#define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
#define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
#define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
#define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
#define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
#define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
#define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
#define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
#define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
#define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
#define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
#define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
#define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
#define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
#define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
#define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
#define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
#define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
#define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
#define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
#define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
#define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
#define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
#define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
#define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
#define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
#define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
#define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
#define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
#define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
#define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
#define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
#define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
#define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
#define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
#define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
#define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
#define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
/* ---------------------------------- PPB_CPUID --------------------------------- */
#define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */
#define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */
#define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */
#define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */
#define PPB_CPUID_Architecture_Pos 16 /*!< PPB CPUID: Architecture Position */
#define PPB_CPUID_Architecture_Msk (0x0fUL << PPB_CPUID_Architecture_Pos) /*!< PPB CPUID: Architecture Mask */
#define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */
#define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */
#define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */
#define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */
/* ---------------------------------- PPB_ICSR ---------------------------------- */
#define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */
#define PPB_ICSR_VECTACTIVE_Msk (0x3fUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */
#define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */
#define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */
#define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */
#define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */
#define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */
#define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */
#define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */
#define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */
#define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */
#define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */
#define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */
#define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */
/* ---------------------------------- PPB_AIRCR --------------------------------- */
#define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */
#define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */
#define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */
#define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */
#define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */
#define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */
/* ----------------------------------- PPB_SCR ---------------------------------- */
#define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */
#define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */
#define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */
#define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */
#define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */
#define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */
/* ----------------------------------- PPB_CCR ---------------------------------- */
#define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */
#define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */
#define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */
#define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */
/* ---------------------------------- PPB_SHPR2 --------------------------------- */
#define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */
#define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */
/* ---------------------------------- PPB_SHPR3 --------------------------------- */
#define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */
#define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */
#define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */
#define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */
/* ---------------------------------- PPB_SHCSR --------------------------------- */
#define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */
#define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */
/* ================================================================================ */
/* ================ Group 'ERU' Position & Mask ================ */
/* ================================================================================ */
/* --------------------------------- ERU_EXISEL --------------------------------- */
#define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */
#define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */
#define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */
#define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */
#define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */
#define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */
#define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */
#define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */
#define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */
#define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */
#define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */
#define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */
#define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */
#define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */
#define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */
#define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */
/* --------------------------------- ERU_EXICON --------------------------------- */
#define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */
#define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */
#define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */
#define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */
#define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */
#define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */
#define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */
#define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */
#define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */
#define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */
#define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */
#define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */
#define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */
#define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */
#define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */
#define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */
#define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */
#define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */
/* --------------------------------- ERU_EXOCON --------------------------------- */
#define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */
#define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */
#define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */
#define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */
#define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */
#define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */
#define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */
#define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */
#define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */
#define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */
#define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */
#define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */
#define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */
#define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */
#define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */
#define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */
/* ================================================================================ */
/* ================ struct 'MATH' Position & Mask ================ */
/* ================================================================================ */
/* --------------------------------- MATH_GLBCON -------------------------------- */
#define MATH_GLBCON_DVDRC_Pos 0 /*!< MATH GLBCON: DVDRC Position */
#define MATH_GLBCON_DVDRC_Msk (0x07UL << MATH_GLBCON_DVDRC_Pos) /*!< MATH GLBCON: DVDRC Mask */
#define MATH_GLBCON_DVSRC_Pos 3 /*!< MATH GLBCON: DVSRC Position */
#define MATH_GLBCON_DVSRC_Msk (0x07UL << MATH_GLBCON_DVSRC_Pos) /*!< MATH GLBCON: DVSRC Mask */
#define MATH_GLBCON_CORDXRC_Pos 6 /*!< MATH GLBCON: CORDXRC Position */
#define MATH_GLBCON_CORDXRC_Msk (0x03UL << MATH_GLBCON_CORDXRC_Pos) /*!< MATH GLBCON: CORDXRC Mask */
#define MATH_GLBCON_CORDYRC_Pos 9 /*!< MATH GLBCON: CORDYRC Position */
#define MATH_GLBCON_CORDYRC_Msk (0x03UL << MATH_GLBCON_CORDYRC_Pos) /*!< MATH GLBCON: CORDYRC Mask */
#define MATH_GLBCON_CORDZRC_Pos 12 /*!< MATH GLBCON: CORDZRC Position */
#define MATH_GLBCON_CORDZRC_Msk (0x03UL << MATH_GLBCON_CORDZRC_Pos) /*!< MATH GLBCON: CORDZRC Mask */
#define MATH_GLBCON_SUSCFG_Pos 16 /*!< MATH GLBCON: SUSCFG Position */
#define MATH_GLBCON_SUSCFG_Msk (0x03UL << MATH_GLBCON_SUSCFG_Pos) /*!< MATH GLBCON: SUSCFG Mask */
/* ----------------------------------- MATH_ID ---------------------------------- */
#define MATH_ID_MOD_REV_Pos 0 /*!< MATH ID: MOD_REV Position */
#define MATH_ID_MOD_REV_Msk (0x000000ffUL << MATH_ID_MOD_REV_Pos) /*!< MATH ID: MOD_REV Mask */
#define MATH_ID_MOD_TYPE_Pos 8 /*!< MATH ID: MOD_TYPE Position */
#define MATH_ID_MOD_TYPE_Msk (0x000000ffUL << MATH_ID_MOD_TYPE_Pos) /*!< MATH ID: MOD_TYPE Mask */
#define MATH_ID_MOD_NUMBER_Pos 16 /*!< MATH ID: MOD_NUMBER Position */
#define MATH_ID_MOD_NUMBER_Msk (0x0000ffffUL << MATH_ID_MOD_NUMBER_Pos) /*!< MATH ID: MOD_NUMBER Mask */
/* --------------------------------- MATH_EVIER --------------------------------- */
#define MATH_EVIER_DIVEOCIEN_Pos 0 /*!< MATH EVIER: DIVEOCIEN Position */
#define MATH_EVIER_DIVEOCIEN_Msk (0x01UL << MATH_EVIER_DIVEOCIEN_Pos) /*!< MATH EVIER: DIVEOCIEN Mask */
#define MATH_EVIER_DIVERRIEN_Pos 1 /*!< MATH EVIER: DIVERRIEN Position */
#define MATH_EVIER_DIVERRIEN_Msk (0x01UL << MATH_EVIER_DIVERRIEN_Pos) /*!< MATH EVIER: DIVERRIEN Mask */
#define MATH_EVIER_CDEOCIEN_Pos 2 /*!< MATH EVIER: CDEOCIEN Position */
#define MATH_EVIER_CDEOCIEN_Msk (0x01UL << MATH_EVIER_CDEOCIEN_Pos) /*!< MATH EVIER: CDEOCIEN Mask */
#define MATH_EVIER_CDERRIEN_Pos 3 /*!< MATH EVIER: CDERRIEN Position */
#define MATH_EVIER_CDERRIEN_Msk (0x01UL << MATH_EVIER_CDERRIEN_Pos) /*!< MATH EVIER: CDERRIEN Mask */
/* ---------------------------------- MATH_EVFR --------------------------------- */
#define MATH_EVFR_DIVEOC_Pos 0 /*!< MATH EVFR: DIVEOC Position */
#define MATH_EVFR_DIVEOC_Msk (0x01UL << MATH_EVFR_DIVEOC_Pos) /*!< MATH EVFR: DIVEOC Mask */
#define MATH_EVFR_DIVERR_Pos 1 /*!< MATH EVFR: DIVERR Position */
#define MATH_EVFR_DIVERR_Msk (0x01UL << MATH_EVFR_DIVERR_Pos) /*!< MATH EVFR: DIVERR Mask */
#define MATH_EVFR_CDEOC_Pos 2 /*!< MATH EVFR: CDEOC Position */
#define MATH_EVFR_CDEOC_Msk (0x01UL << MATH_EVFR_CDEOC_Pos) /*!< MATH EVFR: CDEOC Mask */
#define MATH_EVFR_CDERR_Pos 3 /*!< MATH EVFR: CDERR Position */
#define MATH_EVFR_CDERR_Msk (0x01UL << MATH_EVFR_CDERR_Pos) /*!< MATH EVFR: CDERR Mask */
/* --------------------------------- MATH_EVFSR --------------------------------- */
#define MATH_EVFSR_DIVEOCS_Pos 0 /*!< MATH EVFSR: DIVEOCS Position */
#define MATH_EVFSR_DIVEOCS_Msk (0x01UL << MATH_EVFSR_DIVEOCS_Pos) /*!< MATH EVFSR: DIVEOCS Mask */
#define MATH_EVFSR_DIVERRS_Pos 1 /*!< MATH EVFSR: DIVERRS Position */
#define MATH_EVFSR_DIVERRS_Msk (0x01UL << MATH_EVFSR_DIVERRS_Pos) /*!< MATH EVFSR: DIVERRS Mask */
#define MATH_EVFSR_CDEOCS_Pos 2 /*!< MATH EVFSR: CDEOCS Position */
#define MATH_EVFSR_CDEOCS_Msk (0x01UL << MATH_EVFSR_CDEOCS_Pos) /*!< MATH EVFSR: CDEOCS Mask */
#define MATH_EVFSR_CDERRS_Pos 3 /*!< MATH EVFSR: CDERRS Position */
#define MATH_EVFSR_CDERRS_Msk (0x01UL << MATH_EVFSR_CDERRS_Pos) /*!< MATH EVFSR: CDERRS Mask */
/* --------------------------------- MATH_EVFCR --------------------------------- */
#define MATH_EVFCR_DIVEOCC_Pos 0 /*!< MATH EVFCR: DIVEOCC Position */
#define MATH_EVFCR_DIVEOCC_Msk (0x01UL << MATH_EVFCR_DIVEOCC_Pos) /*!< MATH EVFCR: DIVEOCC Mask */
#define MATH_EVFCR_DIVERRC_Pos 1 /*!< MATH EVFCR: DIVERRC Position */
#define MATH_EVFCR_DIVERRC_Msk (0x01UL << MATH_EVFCR_DIVERRC_Pos) /*!< MATH EVFCR: DIVERRC Mask */
#define MATH_EVFCR_CDEOCC_Pos 2 /*!< MATH EVFCR: CDEOCC Position */
#define MATH_EVFCR_CDEOCC_Msk (0x01UL << MATH_EVFCR_CDEOCC_Pos) /*!< MATH EVFCR: CDEOCC Mask */
#define MATH_EVFCR_CDERRC_Pos 3 /*!< MATH EVFCR: CDERRC Position */
#define MATH_EVFCR_CDERRC_Msk (0x01UL << MATH_EVFCR_CDERRC_Pos) /*!< MATH EVFCR: CDERRC Mask */
/* ---------------------------------- MATH_DVD ---------------------------------- */
#define MATH_DVD_VAL_Pos 0 /*!< MATH DVD: VAL Position */
#define MATH_DVD_VAL_Msk (0xffffffffUL << MATH_DVD_VAL_Pos) /*!< MATH DVD: VAL Mask */
/* ---------------------------------- MATH_DVS ---------------------------------- */
#define MATH_DVS_VAL_Pos 0 /*!< MATH DVS: VAL Position */
#define MATH_DVS_VAL_Msk (0xffffffffUL << MATH_DVS_VAL_Pos) /*!< MATH DVS: VAL Mask */
/* ---------------------------------- MATH_QUOT --------------------------------- */
#define MATH_QUOT_VAL_Pos 0 /*!< MATH QUOT: VAL Position */
#define MATH_QUOT_VAL_Msk (0xffffffffUL << MATH_QUOT_VAL_Pos) /*!< MATH QUOT: VAL Mask */
/* ---------------------------------- MATH_RMD ---------------------------------- */
#define MATH_RMD_VAL_Pos 0 /*!< MATH RMD: VAL Position */
#define MATH_RMD_VAL_Msk (0xffffffffUL << MATH_RMD_VAL_Pos) /*!< MATH RMD: VAL Mask */
/* --------------------------------- MATH_DIVST --------------------------------- */
#define MATH_DIVST_BSY_Pos 0 /*!< MATH DIVST: BSY Position */
#define MATH_DIVST_BSY_Msk (0x01UL << MATH_DIVST_BSY_Pos) /*!< MATH DIVST: BSY Mask */
/* --------------------------------- MATH_DIVCON -------------------------------- */
#define MATH_DIVCON_ST_Pos 0 /*!< MATH DIVCON: ST Position */
#define MATH_DIVCON_ST_Msk (0x01UL << MATH_DIVCON_ST_Pos) /*!< MATH DIVCON: ST Mask */
#define MATH_DIVCON_STMODE_Pos 1 /*!< MATH DIVCON: STMODE Position */
#define MATH_DIVCON_STMODE_Msk (0x01UL << MATH_DIVCON_STMODE_Pos) /*!< MATH DIVCON: STMODE Mask */
#define MATH_DIVCON_USIGN_Pos 2 /*!< MATH DIVCON: USIGN Position */
#define MATH_DIVCON_USIGN_Msk (0x01UL << MATH_DIVCON_USIGN_Pos) /*!< MATH DIVCON: USIGN Mask */
#define MATH_DIVCON_DIVMODE_Pos 3 /*!< MATH DIVCON: DIVMODE Position */
#define MATH_DIVCON_DIVMODE_Msk (0x03UL << MATH_DIVCON_DIVMODE_Pos) /*!< MATH DIVCON: DIVMODE Mask */
#define MATH_DIVCON_QSCNT_Pos 8 /*!< MATH DIVCON: QSCNT Position */
#define MATH_DIVCON_QSCNT_Msk (0x1fUL << MATH_DIVCON_QSCNT_Pos) /*!< MATH DIVCON: QSCNT Mask */
#define MATH_DIVCON_QSDIR_Pos 15 /*!< MATH DIVCON: QSDIR Position */
#define MATH_DIVCON_QSDIR_Msk (0x01UL << MATH_DIVCON_QSDIR_Pos) /*!< MATH DIVCON: QSDIR Mask */
#define MATH_DIVCON_DVDSLC_Pos 16 /*!< MATH DIVCON: DVDSLC Position */
#define MATH_DIVCON_DVDSLC_Msk (0x1fUL << MATH_DIVCON_DVDSLC_Pos) /*!< MATH DIVCON: DVDSLC Mask */
#define MATH_DIVCON_DVSSRC_Pos 24 /*!< MATH DIVCON: DVSSRC Position */
#define MATH_DIVCON_DVSSRC_Msk (0x1fUL << MATH_DIVCON_DVSSRC_Pos) /*!< MATH DIVCON: DVSSRC Mask */
/* --------------------------------- MATH_STATC --------------------------------- */
#define MATH_STATC_BSY_Pos 0 /*!< MATH STATC: BSY Position */
#define MATH_STATC_BSY_Msk (0x01UL << MATH_STATC_BSY_Pos) /*!< MATH STATC: BSY Mask */
#define MATH_STATC_KEEPX_Pos 5 /*!< MATH STATC: KEEPX Position */
#define MATH_STATC_KEEPX_Msk (0x01UL << MATH_STATC_KEEPX_Pos) /*!< MATH STATC: KEEPX Mask */
#define MATH_STATC_KEEPY_Pos 6 /*!< MATH STATC: KEEPY Position */
#define MATH_STATC_KEEPY_Msk (0x01UL << MATH_STATC_KEEPY_Pos) /*!< MATH STATC: KEEPY Mask */
#define MATH_STATC_KEEPZ_Pos 7 /*!< MATH STATC: KEEPZ Position */
#define MATH_STATC_KEEPZ_Msk (0x01UL << MATH_STATC_KEEPZ_Pos) /*!< MATH STATC: KEEPZ Mask */
/* ---------------------------------- MATH_CON ---------------------------------- */
#define MATH_CON_ST_Pos 0 /*!< MATH CON: ST Position */
#define MATH_CON_ST_Msk (0x01UL << MATH_CON_ST_Pos) /*!< MATH CON: ST Mask */
#define MATH_CON_MODE_Pos 1 /*!< MATH CON: MODE Position */
#define MATH_CON_MODE_Msk (0x03UL << MATH_CON_MODE_Pos) /*!< MATH CON: MODE Mask */
#define MATH_CON_ROTVEC_Pos 3 /*!< MATH CON: ROTVEC Position */
#define MATH_CON_ROTVEC_Msk (0x01UL << MATH_CON_ROTVEC_Pos) /*!< MATH CON: ROTVEC Mask */
#define MATH_CON_ST_MODE_Pos 4 /*!< MATH CON: ST_MODE Position */
#define MATH_CON_ST_MODE_Msk (0x01UL << MATH_CON_ST_MODE_Pos) /*!< MATH CON: ST_MODE Mask */
#define MATH_CON_X_USIGN_Pos 5 /*!< MATH CON: X_USIGN Position */
#define MATH_CON_X_USIGN_Msk (0x01UL << MATH_CON_X_USIGN_Pos) /*!< MATH CON: X_USIGN Mask */
#define MATH_CON_MPS_Pos 6 /*!< MATH CON: MPS Position */
#define MATH_CON_MPS_Msk (0x03UL << MATH_CON_MPS_Pos) /*!< MATH CON: MPS Mask */
/* --------------------------------- MATH_CORDX --------------------------------- */
#define MATH_CORDX_DATA_Pos 8 /*!< MATH CORDX: DATA Position */
#define MATH_CORDX_DATA_Msk (0x00ffffffUL << MATH_CORDX_DATA_Pos) /*!< MATH CORDX: DATA Mask */
/* --------------------------------- MATH_CORDY --------------------------------- */
#define MATH_CORDY_DATA_Pos 8 /*!< MATH CORDY: DATA Position */
#define MATH_CORDY_DATA_Msk (0x00ffffffUL << MATH_CORDY_DATA_Pos) /*!< MATH CORDY: DATA Mask */
/* --------------------------------- MATH_CORDZ --------------------------------- */
#define MATH_CORDZ_DATA_Pos 8 /*!< MATH CORDZ: DATA Position */
#define MATH_CORDZ_DATA_Msk (0x00ffffffUL << MATH_CORDZ_DATA_Pos) /*!< MATH CORDZ: DATA Mask */
/* --------------------------------- MATH_CORRX --------------------------------- */
#define MATH_CORRX_RESULT_Pos 8 /*!< MATH CORRX: RESULT Position */
#define MATH_CORRX_RESULT_Msk (0x00ffffffUL << MATH_CORRX_RESULT_Pos) /*!< MATH CORRX: RESULT Mask */
/* --------------------------------- MATH_CORRY --------------------------------- */
#define MATH_CORRY_RESULT_Pos 8 /*!< MATH CORRY: RESULT Position */
#define MATH_CORRY_RESULT_Msk (0x00ffffffUL << MATH_CORRY_RESULT_Pos) /*!< MATH CORRY: RESULT Mask */
/* --------------------------------- MATH_CORRZ --------------------------------- */
#define MATH_CORRZ_RESULT_Pos 8 /*!< MATH CORRZ: RESULT Position */
#define MATH_CORRZ_RESULT_Msk (0x00ffffffUL << MATH_CORRZ_RESULT_Pos) /*!< MATH CORRZ: RESULT Mask */
/* ================================================================================ */
/* ================ struct 'PAU' Position & Mask ================ */
/* ================================================================================ */
/* --------------------------------- PAU_AVAIL0 --------------------------------- */
#define PAU_AVAIL0_AVAIL20_Pos 20 /*!< PAU AVAIL0: AVAIL20 Position */
#define PAU_AVAIL0_AVAIL20_Msk (0x01UL << PAU_AVAIL0_AVAIL20_Pos) /*!< PAU AVAIL0: AVAIL20 Mask */
#define PAU_AVAIL0_AVAIL21_Pos 21 /*!< PAU AVAIL0: AVAIL21 Position */
#define PAU_AVAIL0_AVAIL21_Msk (0x01UL << PAU_AVAIL0_AVAIL21_Pos) /*!< PAU AVAIL0: AVAIL21 Mask */
#define PAU_AVAIL0_AVAIL22_Pos 22 /*!< PAU AVAIL0: AVAIL22 Position */
#define PAU_AVAIL0_AVAIL22_Msk (0x01UL << PAU_AVAIL0_AVAIL22_Pos) /*!< PAU AVAIL0: AVAIL22 Mask */
#define PAU_AVAIL0_AVAIL23_Pos 23 /*!< PAU AVAIL0: AVAIL23 Position */
#define PAU_AVAIL0_AVAIL23_Msk (0x01UL << PAU_AVAIL0_AVAIL23_Pos) /*!< PAU AVAIL0: AVAIL23 Mask */
#define PAU_AVAIL0_AVAIL24_Pos 24 /*!< PAU AVAIL0: AVAIL24 Position */
#define PAU_AVAIL0_AVAIL24_Msk (0x01UL << PAU_AVAIL0_AVAIL24_Pos) /*!< PAU AVAIL0: AVAIL24 Mask */
/* --------------------------------- PAU_AVAIL1 --------------------------------- */
#define PAU_AVAIL1_AVAIL0_Pos 0 /*!< PAU AVAIL1: AVAIL0 Position */
#define PAU_AVAIL1_AVAIL0_Msk (0x01UL << PAU_AVAIL1_AVAIL0_Pos) /*!< PAU AVAIL1: AVAIL0 Mask */
#define PAU_AVAIL1_AVAIL1_Pos 1 /*!< PAU AVAIL1: AVAIL1 Position */
#define PAU_AVAIL1_AVAIL1_Msk (0x01UL << PAU_AVAIL1_AVAIL1_Pos) /*!< PAU AVAIL1: AVAIL1 Mask */
#define PAU_AVAIL1_AVAIL4_Pos 4 /*!< PAU AVAIL1: AVAIL4 Position */
#define PAU_AVAIL1_AVAIL4_Msk (0x01UL << PAU_AVAIL1_AVAIL4_Pos) /*!< PAU AVAIL1: AVAIL4 Mask */
#define PAU_AVAIL1_AVAIL5_Pos 5 /*!< PAU AVAIL1: AVAIL5 Position */
#define PAU_AVAIL1_AVAIL5_Msk (0x01UL << PAU_AVAIL1_AVAIL5_Pos) /*!< PAU AVAIL1: AVAIL5 Mask */
#define PAU_AVAIL1_AVAIL6_Pos 6 /*!< PAU AVAIL1: AVAIL6 Position */
#define PAU_AVAIL1_AVAIL6_Msk (0x01UL << PAU_AVAIL1_AVAIL6_Pos) /*!< PAU AVAIL1: AVAIL6 Mask */
#define PAU_AVAIL1_AVAIL7_Pos 7 /*!< PAU AVAIL1: AVAIL7 Position */
#define PAU_AVAIL1_AVAIL7_Msk (0x01UL << PAU_AVAIL1_AVAIL7_Pos) /*!< PAU AVAIL1: AVAIL7 Mask */
#define PAU_AVAIL1_AVAIL8_Pos 8 /*!< PAU AVAIL1: AVAIL8 Position */
#define PAU_AVAIL1_AVAIL8_Msk (0x01UL << PAU_AVAIL1_AVAIL8_Pos) /*!< PAU AVAIL1: AVAIL8 Mask */
#define PAU_AVAIL1_AVAIL9_Pos 9 /*!< PAU AVAIL1: AVAIL9 Position */
#define PAU_AVAIL1_AVAIL9_Msk (0x01UL << PAU_AVAIL1_AVAIL9_Pos) /*!< PAU AVAIL1: AVAIL9 Mask */
#define PAU_AVAIL1_AVAIL10_Pos 10 /*!< PAU AVAIL1: AVAIL10 Position */
#define PAU_AVAIL1_AVAIL10_Msk (0x01UL << PAU_AVAIL1_AVAIL10_Pos) /*!< PAU AVAIL1: AVAIL10 Mask */
#define PAU_AVAIL1_AVAIL11_Pos 11 /*!< PAU AVAIL1: AVAIL11 Position */
#define PAU_AVAIL1_AVAIL11_Msk (0x01UL << PAU_AVAIL1_AVAIL11_Pos) /*!< PAU AVAIL1: AVAIL11 Mask */
#define PAU_AVAIL1_AVAIL12_Pos 12 /*!< PAU AVAIL1: AVAIL12 Position */
#define PAU_AVAIL1_AVAIL12_Msk (0x01UL << PAU_AVAIL1_AVAIL12_Pos) /*!< PAU AVAIL1: AVAIL12 Mask */
/* --------------------------------- PAU_AVAIL2 --------------------------------- */
#define PAU_AVAIL2_AVAIL0_Pos 0 /*!< PAU AVAIL2: AVAIL0 Position */
#define PAU_AVAIL2_AVAIL0_Msk (0x01UL << PAU_AVAIL2_AVAIL0_Pos) /*!< PAU AVAIL2: AVAIL0 Mask */
#define PAU_AVAIL2_AVAIL1_Pos 1 /*!< PAU AVAIL2: AVAIL1 Position */
#define PAU_AVAIL2_AVAIL1_Msk (0x01UL << PAU_AVAIL2_AVAIL1_Pos) /*!< PAU AVAIL2: AVAIL1 Mask */
#define PAU_AVAIL2_AVAIL2_Pos 2 /*!< PAU AVAIL2: AVAIL2 Position */
#define PAU_AVAIL2_AVAIL2_Msk (0x01UL << PAU_AVAIL2_AVAIL2_Pos) /*!< PAU AVAIL2: AVAIL2 Mask */
#define PAU_AVAIL2_AVAIL3_Pos 3 /*!< PAU AVAIL2: AVAIL3 Position */
#define PAU_AVAIL2_AVAIL3_Msk (0x01UL << PAU_AVAIL2_AVAIL3_Pos) /*!< PAU AVAIL2: AVAIL3 Mask */
#define PAU_AVAIL2_AVAIL12_Pos 12 /*!< PAU AVAIL2: AVAIL12 Position */
#define PAU_AVAIL2_AVAIL12_Msk (0x01UL << PAU_AVAIL2_AVAIL12_Pos) /*!< PAU AVAIL2: AVAIL12 Mask */
#define PAU_AVAIL2_AVAIL15_Pos 15 /*!< PAU AVAIL2: AVAIL15 Position */
#define PAU_AVAIL2_AVAIL15_Msk (0x01UL << PAU_AVAIL2_AVAIL15_Pos) /*!< PAU AVAIL2: AVAIL15 Mask */
/* -------------------------------- PAU_PRIVDIS0 -------------------------------- */
#define PAU_PRIVDIS0_PDIS2_Pos 2 /*!< PAU PRIVDIS0: PDIS2 Position */
#define PAU_PRIVDIS0_PDIS2_Msk (0x01UL << PAU_PRIVDIS0_PDIS2_Pos) /*!< PAU PRIVDIS0: PDIS2 Mask */
#define PAU_PRIVDIS0_PDIS5_Pos 5 /*!< PAU PRIVDIS0: PDIS5 Position */
#define PAU_PRIVDIS0_PDIS5_Msk (0x01UL << PAU_PRIVDIS0_PDIS5_Pos) /*!< PAU PRIVDIS0: PDIS5 Mask */
#define PAU_PRIVDIS0_PDIS6_Pos 6 /*!< PAU PRIVDIS0: PDIS6 Position */
#define PAU_PRIVDIS0_PDIS6_Msk (0x01UL << PAU_PRIVDIS0_PDIS6_Pos) /*!< PAU PRIVDIS0: PDIS6 Mask */
#define PAU_PRIVDIS0_PDIS7_Pos 7 /*!< PAU PRIVDIS0: PDIS7 Position */
#define PAU_PRIVDIS0_PDIS7_Msk (0x01UL << PAU_PRIVDIS0_PDIS7_Pos) /*!< PAU PRIVDIS0: PDIS7 Mask */
#define PAU_PRIVDIS0_PDIS19_Pos 19 /*!< PAU PRIVDIS0: PDIS19 Position */
#define PAU_PRIVDIS0_PDIS19_Msk (0x01UL << PAU_PRIVDIS0_PDIS19_Pos) /*!< PAU PRIVDIS0: PDIS19 Mask */
#define PAU_PRIVDIS0_PDIS20_Pos 20 /*!< PAU PRIVDIS0: PDIS20 Position */
#define PAU_PRIVDIS0_PDIS20_Msk (0x01UL << PAU_PRIVDIS0_PDIS20_Pos) /*!< PAU PRIVDIS0: PDIS20 Mask */
#define PAU_PRIVDIS0_PDIS21_Pos 21 /*!< PAU PRIVDIS0: PDIS21 Position */
#define PAU_PRIVDIS0_PDIS21_Msk (0x01UL << PAU_PRIVDIS0_PDIS21_Pos) /*!< PAU PRIVDIS0: PDIS21 Mask */
#define PAU_PRIVDIS0_PDIS22_Pos 22 /*!< PAU PRIVDIS0: PDIS22 Position */
#define PAU_PRIVDIS0_PDIS22_Msk (0x01UL << PAU_PRIVDIS0_PDIS22_Pos) /*!< PAU PRIVDIS0: PDIS22 Mask */
#define PAU_PRIVDIS0_PDIS23_Pos 23 /*!< PAU PRIVDIS0: PDIS23 Position */
#define PAU_PRIVDIS0_PDIS23_Msk (0x01UL << PAU_PRIVDIS0_PDIS23_Pos) /*!< PAU PRIVDIS0: PDIS23 Mask */
#define PAU_PRIVDIS0_PDIS24_Pos 24 /*!< PAU PRIVDIS0: PDIS24 Position */
#define PAU_PRIVDIS0_PDIS24_Msk (0x01UL << PAU_PRIVDIS0_PDIS24_Pos) /*!< PAU PRIVDIS0: PDIS24 Mask */
/* -------------------------------- PAU_PRIVDIS1 -------------------------------- */
#define PAU_PRIVDIS1_PDIS0_Pos 0 /*!< PAU PRIVDIS1: PDIS0 Position */
#define PAU_PRIVDIS1_PDIS0_Msk (0x01UL << PAU_PRIVDIS1_PDIS0_Pos) /*!< PAU PRIVDIS1: PDIS0 Mask */
#define PAU_PRIVDIS1_PDIS1_Pos 1 /*!< PAU PRIVDIS1: PDIS1 Position */
#define PAU_PRIVDIS1_PDIS1_Msk (0x01UL << PAU_PRIVDIS1_PDIS1_Pos) /*!< PAU PRIVDIS1: PDIS1 Mask */
#define PAU_PRIVDIS1_PDIS5_Pos 5 /*!< PAU PRIVDIS1: PDIS5 Position */
#define PAU_PRIVDIS1_PDIS5_Msk (0x01UL << PAU_PRIVDIS1_PDIS5_Pos) /*!< PAU PRIVDIS1: PDIS5 Mask */
#define PAU_PRIVDIS1_PDIS6_Pos 6 /*!< PAU PRIVDIS1: PDIS6 Position */
#define PAU_PRIVDIS1_PDIS6_Msk (0x01UL << PAU_PRIVDIS1_PDIS6_Pos) /*!< PAU PRIVDIS1: PDIS6 Mask */
#define PAU_PRIVDIS1_PDIS7_Pos 7 /*!< PAU PRIVDIS1: PDIS7 Position */
#define PAU_PRIVDIS1_PDIS7_Msk (0x01UL << PAU_PRIVDIS1_PDIS7_Pos) /*!< PAU PRIVDIS1: PDIS7 Mask */
#define PAU_PRIVDIS1_PDIS8_Pos 8 /*!< PAU PRIVDIS1: PDIS8 Position */
#define PAU_PRIVDIS1_PDIS8_Msk (0x01UL << PAU_PRIVDIS1_PDIS8_Pos) /*!< PAU PRIVDIS1: PDIS8 Mask */
#define PAU_PRIVDIS1_PDIS9_Pos 9 /*!< PAU PRIVDIS1: PDIS9 Position */
#define PAU_PRIVDIS1_PDIS9_Msk (0x01UL << PAU_PRIVDIS1_PDIS9_Pos) /*!< PAU PRIVDIS1: PDIS9 Mask */
#define PAU_PRIVDIS1_PDIS10_Pos 10 /*!< PAU PRIVDIS1: PDIS10 Position */
#define PAU_PRIVDIS1_PDIS10_Msk (0x01UL << PAU_PRIVDIS1_PDIS10_Pos) /*!< PAU PRIVDIS1: PDIS10 Mask */
#define PAU_PRIVDIS1_PDIS11_Pos 11 /*!< PAU PRIVDIS1: PDIS11 Position */
#define PAU_PRIVDIS1_PDIS11_Msk (0x01UL << PAU_PRIVDIS1_PDIS11_Pos) /*!< PAU PRIVDIS1: PDIS11 Mask */
#define PAU_PRIVDIS1_PDIS12_Pos 12 /*!< PAU PRIVDIS1: PDIS12 Position */
#define PAU_PRIVDIS1_PDIS12_Msk (0x01UL << PAU_PRIVDIS1_PDIS12_Pos) /*!< PAU PRIVDIS1: PDIS12 Mask */
/* -------------------------------- PAU_PRIVDIS2 -------------------------------- */
#define PAU_PRIVDIS2_PDIS0_Pos 0 /*!< PAU PRIVDIS2: PDIS0 Position */
#define PAU_PRIVDIS2_PDIS0_Msk (0x01UL << PAU_PRIVDIS2_PDIS0_Pos) /*!< PAU PRIVDIS2: PDIS0 Mask */
#define PAU_PRIVDIS2_PDIS1_Pos 1 /*!< PAU PRIVDIS2: PDIS1 Position */
#define PAU_PRIVDIS2_PDIS1_Msk (0x01UL << PAU_PRIVDIS2_PDIS1_Pos) /*!< PAU PRIVDIS2: PDIS1 Mask */
#define PAU_PRIVDIS2_PDIS2_Pos 2 /*!< PAU PRIVDIS2: PDIS2 Position */
#define PAU_PRIVDIS2_PDIS2_Msk (0x01UL << PAU_PRIVDIS2_PDIS2_Pos) /*!< PAU PRIVDIS2: PDIS2 Mask */
#define PAU_PRIVDIS2_PDIS3_Pos 3 /*!< PAU PRIVDIS2: PDIS3 Position */
#define PAU_PRIVDIS2_PDIS3_Msk (0x01UL << PAU_PRIVDIS2_PDIS3_Pos) /*!< PAU PRIVDIS2: PDIS3 Mask */
#define PAU_PRIVDIS2_PDIS12_Pos 12 /*!< PAU PRIVDIS2: PDIS12 Position */
#define PAU_PRIVDIS2_PDIS12_Msk (0x01UL << PAU_PRIVDIS2_PDIS12_Pos) /*!< PAU PRIVDIS2: PDIS12 Mask */
#define PAU_PRIVDIS2_PDIS15_Pos 15 /*!< PAU PRIVDIS2: PDIS15 Position */
#define PAU_PRIVDIS2_PDIS15_Msk (0x01UL << PAU_PRIVDIS2_PDIS15_Pos) /*!< PAU PRIVDIS2: PDIS15 Mask */
/* --------------------------------- PAU_ROMSIZE -------------------------------- */
#define PAU_ROMSIZE_ADDR_Pos 8 /*!< PAU ROMSIZE: ADDR Position */
#define PAU_ROMSIZE_ADDR_Msk (0x3fUL << PAU_ROMSIZE_ADDR_Pos) /*!< PAU ROMSIZE: ADDR Mask */
/* --------------------------------- PAU_FLSIZE --------------------------------- */
#define PAU_FLSIZE_ADDR_Pos 12 /*!< PAU FLSIZE: ADDR Position */
#define PAU_FLSIZE_ADDR_Msk (0x3fUL << PAU_FLSIZE_ADDR_Pos) /*!< PAU FLSIZE: ADDR Mask */
/* -------------------------------- PAU_RAM0SIZE -------------------------------- */
#define PAU_RAM0SIZE_ADDR_Pos 8 /*!< PAU RAM0SIZE: ADDR Position */
#define PAU_RAM0SIZE_ADDR_Msk (0x1fUL << PAU_RAM0SIZE_ADDR_Pos) /*!< PAU RAM0SIZE: ADDR Mask */
/* ================================================================================ */
/* ================ struct 'NVM' Position & Mask ================ */
/* ================================================================================ */
/* -------------------------------- NVM_NVMSTATUS ------------------------------- */
#define NVM_NVMSTATUS_BUSY_Pos 0 /*!< NVM NVMSTATUS: BUSY Position */
#define NVM_NVMSTATUS_BUSY_Msk (0x01UL << NVM_NVMSTATUS_BUSY_Pos) /*!< NVM NVMSTATUS: BUSY Mask */
#define NVM_NVMSTATUS_SLEEP_Pos 1 /*!< NVM NVMSTATUS: SLEEP Position */
#define NVM_NVMSTATUS_SLEEP_Msk (0x01UL << NVM_NVMSTATUS_SLEEP_Pos) /*!< NVM NVMSTATUS: SLEEP Mask */
#define NVM_NVMSTATUS_VERR_Pos 2 /*!< NVM NVMSTATUS: VERR Position */
#define NVM_NVMSTATUS_VERR_Msk (0x03UL << NVM_NVMSTATUS_VERR_Pos) /*!< NVM NVMSTATUS: VERR Mask */
#define NVM_NVMSTATUS_ECC1READ_Pos 4 /*!< NVM NVMSTATUS: ECC1READ Position */
#define NVM_NVMSTATUS_ECC1READ_Msk (0x01UL << NVM_NVMSTATUS_ECC1READ_Pos) /*!< NVM NVMSTATUS: ECC1READ Mask */
#define NVM_NVMSTATUS_ECC2READ_Pos 5 /*!< NVM NVMSTATUS: ECC2READ Position */
#define NVM_NVMSTATUS_ECC2READ_Msk (0x01UL << NVM_NVMSTATUS_ECC2READ_Pos) /*!< NVM NVMSTATUS: ECC2READ Mask */
#define NVM_NVMSTATUS_WRPERR_Pos 6 /*!< NVM NVMSTATUS: WRPERR Position */
#define NVM_NVMSTATUS_WRPERR_Msk (0x01UL << NVM_NVMSTATUS_WRPERR_Pos) /*!< NVM NVMSTATUS: WRPERR Mask */
/* --------------------------------- NVM_NVMPROG -------------------------------- */
#define NVM_NVMPROG_ACTION_Pos 0 /*!< NVM NVMPROG: ACTION Position */
#define NVM_NVMPROG_ACTION_Msk (0x000000ffUL << NVM_NVMPROG_ACTION_Pos) /*!< NVM NVMPROG: ACTION Mask */
#define NVM_NVMPROG_RSTVERR_Pos 12 /*!< NVM NVMPROG: RSTVERR Position */
#define NVM_NVMPROG_RSTVERR_Msk (0x01UL << NVM_NVMPROG_RSTVERR_Pos) /*!< NVM NVMPROG: RSTVERR Mask */
#define NVM_NVMPROG_RSTECC_Pos 13 /*!< NVM NVMPROG: RSTECC Position */
#define NVM_NVMPROG_RSTECC_Msk (0x01UL << NVM_NVMPROG_RSTECC_Pos) /*!< NVM NVMPROG: RSTECC Mask */
/* --------------------------------- NVM_NVMCONF -------------------------------- */
#define NVM_NVMCONF_HRLEV_Pos 1 /*!< NVM NVMCONF: HRLEV Position */
#define NVM_NVMCONF_HRLEV_Msk (0x03UL << NVM_NVMCONF_HRLEV_Pos) /*!< NVM NVMCONF: HRLEV Mask */
#define NVM_NVMCONF_SECPROT_Pos 4 /*!< NVM NVMCONF: SECPROT Position */
#define NVM_NVMCONF_SECPROT_Msk (0x000000ffUL << NVM_NVMCONF_SECPROT_Pos) /*!< NVM NVMCONF: SECPROT Mask */
#define NVM_NVMCONF_INT_ON_Pos 14 /*!< NVM NVMCONF: INT_ON Position */
#define NVM_NVMCONF_INT_ON_Msk (0x01UL << NVM_NVMCONF_INT_ON_Pos) /*!< NVM NVMCONF: INT_ON Mask */
#define NVM_NVMCONF_NVM_ON_Pos 15 /*!< NVM NVMCONF: NVM_ON Position */
#define NVM_NVMCONF_NVM_ON_Msk (0x01UL << NVM_NVMCONF_NVM_ON_Pos) /*!< NVM NVMCONF: NVM_ON Mask */
/* ================================================================================ */
/* ================ struct 'WDT' Position & Mask ================ */
/* ================================================================================ */
/* ----------------------------------- WDT_ID ----------------------------------- */
#define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */
#define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */
#define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */
#define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */
#define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */
#define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */
/* ----------------------------------- WDT_CTR ---------------------------------- */
#define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */
#define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */
#define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */
#define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */
#define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */
#define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */
#define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */
#define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */
/* ----------------------------------- WDT_SRV ---------------------------------- */
#define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */
#define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */
/* ----------------------------------- WDT_TIM ---------------------------------- */
#define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */
#define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */
/* ----------------------------------- WDT_WLB ---------------------------------- */
#define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */
#define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */
/* ----------------------------------- WDT_WUB ---------------------------------- */
#define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */
#define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */
/* --------------------------------- WDT_WDTSTS --------------------------------- */
#define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */
#define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */
/* --------------------------------- WDT_WDTCLR --------------------------------- */
#define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */
#define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */
/* ================================================================================ */
/* ================ struct 'RTC' Position & Mask ================ */
/* ================================================================================ */
/* ----------------------------------- RTC_ID ----------------------------------- */
#define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */
#define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */
#define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */
#define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */
#define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */
#define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */
/* ----------------------------------- RTC_CTR ---------------------------------- */
#define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */
#define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */
#define RTC_CTR_SUS_Pos 1 /*!< RTC CTR: SUS Position */
#define RTC_CTR_SUS_Msk (0x01UL << RTC_CTR_SUS_Pos) /*!< RTC CTR: SUS Mask */
#define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */
#define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */
/* --------------------------------- RTC_RAWSTAT -------------------------------- */
#define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */
#define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */
#define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */
#define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */
#define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */
#define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */
#define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */
#define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */
#define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */
#define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */
#define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */
#define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */
#define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */
#define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */
/* ---------------------------------- RTC_STSSR --------------------------------- */
#define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */
#define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */
#define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */
#define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */
#define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */
#define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */
#define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */
#define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */
#define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */
#define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */
#define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */
#define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */
#define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */
#define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */
/* ---------------------------------- RTC_MSKSR --------------------------------- */
#define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */
#define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */
#define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */
#define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */
#define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */
#define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */
#define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */
#define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */
#define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */
#define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */
#define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */
#define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */
#define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */
#define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */
/* ---------------------------------- RTC_CLRSR --------------------------------- */
#define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */
#define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */
#define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */
#define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */
#define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */
#define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */
#define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */
#define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */
#define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */
#define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */
#define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */
#define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */
#define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */
#define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */
/* ---------------------------------- RTC_ATIM0 --------------------------------- */
#define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */
#define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */
#define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */
#define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */
#define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */
#define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */
#define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */
#define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */
/* ---------------------------------- RTC_ATIM1 --------------------------------- */
#define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */
#define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */
#define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */
#define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */
/* ---------------------------------- RTC_TIM0 ---------------------------------- */
#define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */
#define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */
#define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */
#define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */
#define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */
#define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */
#define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */
#define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */
/* ---------------------------------- RTC_TIM1 ---------------------------------- */
#define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */
#define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */
#define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */
#define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */
#define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */
#define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */
/* ================================================================================ */
/* ================ struct 'PRNG' Position & Mask ================ */
/* ================================================================================ */
/* ---------------------------------- PRNG_WORD --------------------------------- */
#define PRNG_WORD_RDATA_Pos 0 /*!< PRNG WORD: RDATA Position */
#define PRNG_WORD_RDATA_Msk (0x0000ffffUL << PRNG_WORD_RDATA_Pos) /*!< PRNG WORD: RDATA Mask */
/* ---------------------------------- PRNG_CHK ---------------------------------- */
#define PRNG_CHK_RDV_Pos 0 /*!< PRNG CHK: RDV Position */
#define PRNG_CHK_RDV_Msk (0x01UL << PRNG_CHK_RDV_Pos) /*!< PRNG CHK: RDV Mask */
/* ---------------------------------- PRNG_CTRL --------------------------------- */
#define PRNG_CTRL_RDBS_Pos 1 /*!< PRNG CTRL: RDBS Position */
#define PRNG_CTRL_RDBS_Msk (0x03UL << PRNG_CTRL_RDBS_Pos) /*!< PRNG CTRL: RDBS Mask */
#define PRNG_CTRL_KLD_Pos 3 /*!< PRNG CTRL: KLD Position */
#define PRNG_CTRL_KLD_Msk (0x01UL << PRNG_CTRL_KLD_Pos) /*!< PRNG CTRL: KLD Mask */
/* ================================================================================ */
/* ================ Group 'USIC' Position & Mask ================ */
/* ================================================================================ */
/* ----------------------------------- USIC_ID ---------------------------------- */
#define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */
#define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */
#define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */
#define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */
#define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */
#define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */
/* ================================================================================ */
/* ================ Group 'USIC_CH' Position & Mask ================ */
/* ================================================================================ */
/* -------------------------------- USIC_CH_CCFG -------------------------------- */
#define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */
#define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */
#define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */
#define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */
#define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */
#define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */
#define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */
#define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */
#define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */
#define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */
#define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */
#define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */
/* -------------------------------- USIC_CH_KSCFG ------------------------------- */
#define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */
#define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */
#define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */
#define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */
#define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */
#define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */
#define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */
#define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */
#define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */
#define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */
#define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */
#define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */
/* --------------------------------- USIC_CH_FDR -------------------------------- */
#define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */
#define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */
#define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */
#define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */
#define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */
#define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */
/* --------------------------------- USIC_CH_BRG -------------------------------- */
#define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */
#define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */
#define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */
#define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */
#define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */
#define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */
#define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */
#define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */
#define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */
#define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */
#define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */
#define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */
#define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */
#define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */
#define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */
#define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */
#define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */
#define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */
#define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */
#define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */
/* -------------------------------- USIC_CH_INPR -------------------------------- */
#define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */
#define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */
#define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */
#define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */
#define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */
#define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */
#define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */
#define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */
#define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */
#define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */
/* -------------------------------- USIC_CH_DX0CR ------------------------------- */
#define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */
#define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */
#define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */
#define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */
#define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */
#define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */
#define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */
#define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */
#define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */
#define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */
#define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */
#define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */
#define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */
#define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */
#define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */
#define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */
/* -------------------------------- USIC_CH_DX1CR ------------------------------- */
#define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */
#define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */
#define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */
#define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */
#define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */
#define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */
#define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */
#define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */
#define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */
#define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */
#define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */
#define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */
#define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */
#define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */
#define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */
#define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */
#define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */
#define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */
/* -------------------------------- USIC_CH_DX2CR ------------------------------- */
#define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */
#define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */
#define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */
#define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */
#define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */
#define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */
#define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */
#define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */
#define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */
#define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */
#define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */
#define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */
#define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */
#define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */
#define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */
#define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */
/* -------------------------------- USIC_CH_DX3CR ------------------------------- */
#define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */
#define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */
#define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */
#define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */
#define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */
#define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */
#define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */
#define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */
#define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */
#define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */
#define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */
#define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */
#define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */
#define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */
#define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */
#define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */
/* -------------------------------- USIC_CH_DX4CR ------------------------------- */
#define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */
#define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */
#define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */
#define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */
#define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */
#define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */
#define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */
#define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */
#define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */
#define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */
#define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */
#define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */
#define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */
#define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */
#define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */
#define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */
/* -------------------------------- USIC_CH_DX5CR ------------------------------- */
#define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */
#define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */
#define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */
#define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */
#define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */
#define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */
#define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */
#define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */
#define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */
#define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */
#define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */
#define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */
#define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */
#define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */
#define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */
#define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */
/* -------------------------------- USIC_CH_SCTR -------------------------------- */
#define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */
#define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */
#define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */
#define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */
#define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */
#define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */
#define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */
#define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */
#define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */
#define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */
#define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */
#define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */
#define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */
#define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */
#define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */
#define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */
/* -------------------------------- USIC_CH_TCSR -------------------------------- */
#define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */
#define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */
#define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */
#define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */
#define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */
#define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */
#define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */
#define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */
#define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */
#define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */
#define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */
#define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */
#define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */
#define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */
#define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */
#define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */
#define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */
#define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */
#define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */
#define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */
#define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */
#define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */
#define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */
#define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */
#define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */
#define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */
#define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */
#define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */
#define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */
#define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */
#define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */
#define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */
/* --------------------------------- USIC_CH_PCR -------------------------------- */
#define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */
#define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */
#define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */
#define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */
#define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */
#define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */
#define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */
#define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */
#define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */
#define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */
#define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */
#define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */
#define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */
#define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */
#define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */
#define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */
#define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */
#define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */
#define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */
#define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */
#define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */
#define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */
#define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */
#define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */
#define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */
#define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */
#define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */
#define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */
#define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */
#define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */
#define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */
#define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */
#define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */
#define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */
#define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */
#define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */
#define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */
#define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */
#define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */
#define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */
#define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */
#define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */
#define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */
#define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */
#define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */
#define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */
#define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */
#define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */
#define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */
#define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */
#define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */
#define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */
#define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */
#define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */
#define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */
#define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */
#define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */
#define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */
#define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */
#define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */
#define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */
#define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */
#define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */
#define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */
/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */
#define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */
#define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */
#define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */
#define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */
#define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */
#define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */
#define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */
#define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */
#define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */
#define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */
#define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */
#define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */
#define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */
#define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */
#define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */
#define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */
#define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */
#define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */
#define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */
#define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */
#define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */
#define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */
#define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */
#define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */
#define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */
#define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */
/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */
#define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */
#define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */
#define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */
#define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */
#define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */
#define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */
#define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */
#define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */
#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */
#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */
#define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */
#define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */
#define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */
#define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */
#define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */
#define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */
#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */
#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */
#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */
#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */
#define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */
#define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */
#define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */
#define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */
#define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */
#define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */
/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */
#define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */
#define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */
#define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */
#define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */
#define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */
#define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */
#define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */
#define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */
#define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */
#define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */
#define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */
#define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */
#define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */
#define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */
#define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */
#define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */
#define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */
#define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */
#define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */
#define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */
#define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */
#define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */
#define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */
#define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */
#define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */
#define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */
#define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */
#define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */
/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */
#define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */
#define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */
#define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */
#define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */
#define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */
#define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */
#define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */
#define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */
#define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */
#define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */
#define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */
#define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */
#define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */
#define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */
#define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */
#define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */
#define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */
#define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */
/* --------------------------------- USIC_CH_CCR -------------------------------- */
#define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */
#define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */
#define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */
#define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */
#define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */
#define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */
#define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */
#define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */
#define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */
#define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */
#define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */
#define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */
#define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */
#define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */
#define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */
#define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */
#define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */
#define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */
#define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */
#define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */
/* -------------------------------- USIC_CH_CMTR -------------------------------- */
#define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */
#define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */
/* --------------------------------- USIC_CH_PSR -------------------------------- */
#define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */
#define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */
#define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */
#define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */
#define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */
#define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */
#define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */
#define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */
#define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */
#define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */
#define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */
#define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */
#define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */
#define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */
#define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */
#define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */
#define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */
#define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */
#define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */
#define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */
#define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */
#define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */
#define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */
#define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */
#define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */
#define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */
#define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */
#define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */
#define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */
#define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */
#define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */
#define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */
#define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */
#define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */
/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */
#define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */
#define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */
#define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */
#define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */
#define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */
#define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */
#define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */
#define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */
#define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */
#define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */
#define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */
#define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */
#define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */
#define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */
#define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */
#define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */
#define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */
#define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */
#define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */
#define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */
#define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */
#define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */
#define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */
#define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */
#define USIC_CH_PSR_ASCMod