/** | |
* \file | |
* | |
* Copyright (c) 2012 Atmel Corporation. All rights reserved. | |
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* \page License | |
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* modification, are permitted provided that the following conditions are met: | |
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* 1. Redistributions of source code must retain the above copyright notice, | |
* this list of conditions and the following disclaimer. | |
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* 2. Redistributions in binary form must reproduce the above copyright notice, | |
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* 3. The name of Atmel may not be used to endorse or promote products derived | |
* from this software without specific prior written permission. | |
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* 4. This software may only be redistributed and used in connection with an | |
* Atmel microcontroller product. | |
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*/ | |
#ifndef _SAM3S8_MATRIX_INSTANCE_ | |
#define _SAM3S8_MATRIX_INSTANCE_ | |
/* ========== Register definition for MATRIX peripheral ========== */ | |
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) | |
#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ | |
#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ | |
#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ | |
#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ | |
#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ | |
#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ | |
#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ | |
#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ | |
#define REG_CCFG_SMCNFCS (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ | |
#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ | |
#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ | |
#else | |
#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ | |
#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ | |
#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ | |
#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ | |
#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ | |
#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ | |
#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ | |
#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ | |
#define REG_CCFG_SMCNFCS (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ | |
#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ | |
#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ | |
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ | |
#endif /* _SAM3S8_MATRIX_INSTANCE_ */ |