/* ---------------------------------------------------------------------------- */ | |
/* Atmel Microcontroller Software Support */ | |
/* SAM Software Package License */ | |
/* ---------------------------------------------------------------------------- */ | |
/* Copyright (c) 2014, Atmel Corporation */ | |
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/* */ | |
/* - Redistributions of source code must retain the above copyright notice, */ | |
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/* */ | |
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/* ---------------------------------------------------------------------------- */ | |
#ifndef _SAMV71_WDT_COMPONENT_ | |
#define _SAMV71_WDT_COMPONENT_ | |
/* ============================================================================= */ | |
/** SOFTWARE API DEFINITION FOR Watchdog Timer */ | |
/* ============================================================================= */ | |
/** \addtogroup SAMV71_WDT Watchdog Timer */ | |
/*@{*/ | |
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) | |
/** \brief Wdt hardware registers */ | |
typedef struct { | |
__O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ | |
__IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ | |
__I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ | |
} Wdt; | |
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ | |
/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ | |
#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ | |
#define WDT_CR_KEY_Pos 24 | |
#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ | |
#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) | |
#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ | |
/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ | |
#define WDT_MR_WDV_Pos 0 | |
#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ | |
#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) | |
#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ | |
#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ | |
#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ | |
#define WDT_MR_WDD_Pos 16 | |
#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ | |
#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) | |
#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ | |
#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ | |
/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ | |
#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ | |
#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ | |
/*@}*/ | |
#endif /* _SAMV71_WDT_COMPONENT_ */ |