| /* ---------------------------------------------------------------------------- */ | |
| /* Atmel Microcontroller Software Support */ | |
| /* SAM Software Package License */ | |
| /* ---------------------------------------------------------------------------- */ | |
| /* Copyright (c) 2014, Atmel Corporation */ | |
| /* */ | |
| /* All rights reserved. */ | |
| /* */ | |
| /* Redistribution and use in source and binary forms, with or without */ | |
| /* modification, are permitted provided that the following condition is met: */ | |
| /* */ | |
| /* - Redistributions of source code must retain the above copyright notice, */ | |
| /* this list of conditions and the disclaimer below. */ | |
| /* */ | |
| /* Atmel's name may not be used to endorse or promote products derived from */ | |
| /* this software without specific prior written permission. */ | |
| /* */ | |
| /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ | |
| /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ | |
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| /* ---------------------------------------------------------------------------- */ | |
| #ifndef _SAMV71_UART0_INSTANCE_ | |
| #define _SAMV71_UART0_INSTANCE_ | |
| /* ========== Register definition for UART0 peripheral ========== */ | |
| #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) | |
| #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */ | |
| #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */ | |
| #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ | |
| #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ | |
| #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ | |
| #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */ | |
| #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */ | |
| #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ | |
| #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ | |
| #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */ | |
| #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ | |
| #else | |
| #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */ | |
| #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */ | |
| #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ | |
| #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ | |
| #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ | |
| #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */ | |
| #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */ | |
| #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ | |
| #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ | |
| #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */ | |
| #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ | |
| #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ | |
| #endif /* _SAMV71_UART0_INSTANCE_ */ |