FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/samv7/component/component_twi.h - nest-detect/1.3/freertos - Git at Google

 /* ---------------------------------------------------------------------------- */
 /*                  Atmel Microcontroller Software Support                      */
 /*                       SAM Software Package License                           */
 /* ---------------------------------------------------------------------------- */
 /* Copyright (c) 2014, Atmel Corporation                                        */
 /*                                                                              */
 /* All rights reserved.                                                         */
 /*                                                                              */
 /* Redistribution and use in source and binary forms, with or without           */
 /* modification, are permitted provided that the following condition is met:    */
 /*                                                                              */
 /* - Redistributions of source code must retain the above copyright notice,     */
 /* this list of conditions and the disclaimer below.                            */
 /*                                                                              */
 /* Atmel's name may not be used to endorse or promote products derived from     */
 /* this software without specific prior written permission.                     */
 /*                                                                              */
 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
 /* ---------------------------------------------------------------------------- */

 #ifndef _SAM_TWI_COMPONENT_
 #define _SAM_TWI_COMPONENT_

 /* ============================================================================= */
 /**  SOFTWARE API DEFINITION FOR Two-wire Interface */
 /* ============================================================================= */
 /** \addtogroup SAM_TWI Two-wire Interface */
 /*@{*/

 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 /** \brief Twi hardware registers */
 typedef struct {
   __O  uint32_t TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
   __IO uint32_t TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
   __IO uint32_t TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
   __IO uint32_t TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
   __IO uint32_t TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
   __I  uint32_t Reserved1[3];
   __I  uint32_t TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
   __O  uint32_t TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
   __O  uint32_t TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
   __I  uint32_t TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
   __I  uint32_t TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
   __O  uint32_t TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
   __I  uint32_t Reserved2[43];
   __IO uint32_t TWI_WPMR;      /**< \brief (Twi Offset: 0xE4) Write Protection Mode Register */
   __I  uint32_t TWI_WPSR;      /**< \brief (Twi Offset: 0xE8) Write Protection Status Register */
 } Twi;
 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
 #define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
 #define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
 #define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
 #define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
 #define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
 #define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
 #define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
 #define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
 /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
 #define TWI_MMR_IADRSZ_Pos 8
 #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
 #define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
 #define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
 #define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
 #define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
 #define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
 #define TWI_MMR_DADR_Pos 16
 #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
 /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
 #define TWI_SMR_SADR_Pos 16
 #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
 /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
 #define TWI_IADR_IADR_Pos 0
 #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
 /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
 #define TWI_CWGR_CLDIV_Pos 0
 #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
 #define TWI_CWGR_CHDIV_Pos 8
 #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
 #define TWI_CWGR_CKDIV_Pos 16
 #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
 #define TWI_CWGR_HOLD_Pos 24
 #define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time versus TWCK falling */
 #define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))
 /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
 #define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
 #define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
 #define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
 #define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
 #define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
 #define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
 #define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
 #define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
 #define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
 #define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
 #define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
 /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
 #define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
 #define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
 #define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
 #define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
 #define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
 #define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
 #define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
 #define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
 #define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
 #define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
 /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
 #define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
 #define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
 #define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
 #define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
 #define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
 #define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
 #define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
 #define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
 #define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
 #define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
 /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
 #define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
 #define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
 #define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
 #define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
 #define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
 #define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
 #define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
 #define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
 #define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
 #define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
 /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
 #define TWI_RHR_RXDATA_Pos 0
 #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
 /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
 #define TWI_THR_TXDATA_Pos 0
 #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
 /* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */
 #define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */
 #define TWI_WPMR_WPKEY_Pos 8
 #define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */
 #define   TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
 /* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */
 #define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protection Violation Status */
 #define TWI_WPSR_WPVSRC_Pos 8
 #define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */

 /*@}*/


 #endif /* _SAM_TWI_COMPONENT_ */
	/* ---------------------------------------------------------------------------- */
	/* Atmel Microcontroller Software Support */
	/* SAM Software Package License */
	/* ---------------------------------------------------------------------------- */
	/* Copyright (c) 2014, Atmel Corporation */
	/* */
	/* All rights reserved. */
	/* */
	/* Redistribution and use in source and binary forms, with or without */
	/* modification, are permitted provided that the following condition is met: */
	/* */
	/* - Redistributions of source code must retain the above copyright notice, */
	/* this list of conditions and the disclaimer below. */
	/* */
	/* Atmel's name may not be used to endorse or promote products derived from */
	/* this software without specific prior written permission. */
	/* */
	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
	/* ---------------------------------------------------------------------------- */

	#ifndef _SAM_TWI_COMPONENT_
	#define _SAM_TWI_COMPONENT_

	/* ============================================================================= */
	/** SOFTWARE API DEFINITION FOR Two-wire Interface */
	/* ============================================================================= */
	/** \addtogroup SAM_TWI Two-wire Interface */
	/@{/

	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
	/** \brief Twi hardware registers */
	typedef struct {
	__O uint32_t TWI_CR; /*< \brief (Twi Offset: 0x00) Control Register /
	__IO uint32_t TWI_MMR; /*< \brief (Twi Offset: 0x04) Master Mode Register /
	__IO uint32_t TWI_SMR; /*< \brief (Twi Offset: 0x08) Slave Mode Register /
	__IO uint32_t TWI_IADR; /*< \brief (Twi Offset: 0x0C) Internal Address Register /
	__IO uint32_t TWI_CWGR; /*< \brief (Twi Offset: 0x10) Clock Waveform Generator Register /
	__I uint32_t Reserved1[3];
	__I uint32_t TWI_SR; /*< \brief (Twi Offset: 0x20) Status Register /
	__O uint32_t TWI_IER; /*< \brief (Twi Offset: 0x24) Interrupt Enable Register /
	__O uint32_t TWI_IDR; /*< \brief (Twi Offset: 0x28) Interrupt Disable Register /
	__I uint32_t TWI_IMR; /*< \brief (Twi Offset: 0x2C) Interrupt Mask Register /
	__I uint32_t TWI_RHR; /*< \brief (Twi Offset: 0x30) Receive Holding Register /
	__O uint32_t TWI_THR; /*< \brief (Twi Offset: 0x34) Transmit Holding Register /
	__I uint32_t Reserved2[43];
	__IO uint32_t TWI_WPMR; /*< \brief (Twi Offset: 0xE4) Write Protection Mode Register /
	__I uint32_t TWI_WPSR; /*< \brief (Twi Offset: 0xE8) Write Protection Status Register /
	} Twi;
	#endif /* !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
	/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
	#define TWI_CR_START (0x1u << 0) /*< \brief (TWI_CR) Send a START Condition /
	#define TWI_CR_STOP (0x1u << 1) /*< \brief (TWI_CR) Send a STOP Condition /
	#define TWI_CR_MSEN (0x1u << 2) /*< \brief (TWI_CR) TWI Master Mode Enabled /
	#define TWI_CR_MSDIS (0x1u << 3) /*< \brief (TWI_CR) TWI Master Mode Disabled /
	#define TWI_CR_SVEN (0x1u << 4) /*< \brief (TWI_CR) TWI Slave Mode Enabled /
	#define TWI_CR_SVDIS (0x1u << 5) /*< \brief (TWI_CR) TWI Slave Mode Disabled /
	#define TWI_CR_QUICK (0x1u << 6) /*< \brief (TWI_CR) SMBUS Quick Command /
	#define TWI_CR_SWRST (0x1u << 7) /*< \brief (TWI_CR) Software Reset /
	/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
	#define TWI_MMR_IADRSZ_Pos 8
	#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /*< \brief (TWI_MMR) Internal Device Address Size /
	#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /*< \brief (TWI_MMR) No internal device address /
	#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /*< \brief (TWI_MMR) One-byte internal device address /
	#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /*< \brief (TWI_MMR) Two-byte internal device address /
	#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /*< \brief (TWI_MMR) Three-byte internal device address /
	#define TWI_MMR_MREAD (0x1u << 12) /*< \brief (TWI_MMR) Master Read Direction /
	#define TWI_MMR_DADR_Pos 16
	#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /*< \brief (TWI_MMR) Device Address /
	#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
	/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
	#define TWI_SMR_SADR_Pos 16
	#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /*< \brief (TWI_SMR) Slave Address /
	#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
	/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
	#define TWI_IADR_IADR_Pos 0
	#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /*< \brief (TWI_IADR) Internal Address /
	#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
	/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
	#define TWI_CWGR_CLDIV_Pos 0
	#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /*< \brief (TWI_CWGR) Clock Low Divider /
	#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
	#define TWI_CWGR_CHDIV_Pos 8
	#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /*< \brief (TWI_CWGR) Clock High Divider /
	#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
	#define TWI_CWGR_CKDIV_Pos 16
	#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /*< \brief (TWI_CWGR) Clock Divider /
	#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
	#define TWI_CWGR_HOLD_Pos 24
	#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /*< \brief (TWI_CWGR) TWD Hold Time versus TWCK falling /
	#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))
	/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
	#define TWI_SR_TXCOMP (0x1u << 0) /*< \brief (TWI_SR) Transmission Completed (automatically set / reset) /
	#define TWI_SR_RXRDY (0x1u << 1) /*< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) /
	#define TWI_SR_TXRDY (0x1u << 2) /*< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) /
	#define TWI_SR_SVREAD (0x1u << 3) /*< \brief (TWI_SR) Slave Read (automatically set / reset) /
	#define TWI_SR_SVACC (0x1u << 4) /*< \brief (TWI_SR) Slave Access (automatically set / reset) /
	#define TWI_SR_GACC (0x1u << 5) /*< \brief (TWI_SR) General Call Access (clear on read) /
	#define TWI_SR_OVRE (0x1u << 6) /*< \brief (TWI_SR) Overrun Error (clear on read) /
	#define TWI_SR_NACK (0x1u << 8) /*< \brief (TWI_SR) Not Acknowledged (clear on read) /
	#define TWI_SR_ARBLST (0x1u << 9) /*< \brief (TWI_SR) Arbitration Lost (clear on read) /
	#define TWI_SR_SCLWS (0x1u << 10) /*< \brief (TWI_SR) Clock Wait State (automatically set / reset) /
	#define TWI_SR_EOSACC (0x1u << 11) /*< \brief (TWI_SR) End Of Slave Access (clear on read) /
	/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
	#define TWI_IER_TXCOMP (0x1u << 0) /*< \brief (TWI_IER) Transmission Completed Interrupt Enable /
	#define TWI_IER_RXRDY (0x1u << 1) /*< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable /
	#define TWI_IER_TXRDY (0x1u << 2) /*< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable /
	#define TWI_IER_SVACC (0x1u << 4) /*< \brief (TWI_IER) Slave Access Interrupt Enable /
	#define TWI_IER_GACC (0x1u << 5) /*< \brief (TWI_IER) General Call Access Interrupt Enable /
	#define TWI_IER_OVRE (0x1u << 6) /*< \brief (TWI_IER) Overrun Error Interrupt Enable /
	#define TWI_IER_NACK (0x1u << 8) /*< \brief (TWI_IER) Not Acknowledge Interrupt Enable /
	#define TWI_IER_ARBLST (0x1u << 9) /*< \brief (TWI_IER) Arbitration Lost Interrupt Enable /
	#define TWI_IER_SCL_WS (0x1u << 10) /*< \brief (TWI_IER) Clock Wait State Interrupt Enable /
	#define TWI_IER_EOSACC (0x1u << 11) /*< \brief (TWI_IER) End Of Slave Access Interrupt Enable /
	/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
	#define TWI_IDR_TXCOMP (0x1u << 0) /*< \brief (TWI_IDR) Transmission Completed Interrupt Disable /
	#define TWI_IDR_RXRDY (0x1u << 1) /*< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable /
	#define TWI_IDR_TXRDY (0x1u << 2) /*< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable /
	#define TWI_IDR_SVACC (0x1u << 4) /*< \brief (TWI_IDR) Slave Access Interrupt Disable /
	#define TWI_IDR_GACC (0x1u << 5) /*< \brief (TWI_IDR) General Call Access Interrupt Disable /
	#define TWI_IDR_OVRE (0x1u << 6) /*< \brief (TWI_IDR) Overrun Error Interrupt Disable /
	#define TWI_IDR_NACK (0x1u << 8) /*< \brief (TWI_IDR) Not Acknowledge Interrupt Disable /
	#define TWI_IDR_ARBLST (0x1u << 9) /*< \brief (TWI_IDR) Arbitration Lost Interrupt Disable /
	#define TWI_IDR_SCL_WS (0x1u << 10) /*< \brief (TWI_IDR) Clock Wait State Interrupt Disable /
	#define TWI_IDR_EOSACC (0x1u << 11) /*< \brief (TWI_IDR) End Of Slave Access Interrupt Disable /
	/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
	#define TWI_IMR_TXCOMP (0x1u << 0) /*< \brief (TWI_IMR) Transmission Completed Interrupt Mask /
	#define TWI_IMR_RXRDY (0x1u << 1) /*< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask /
	#define TWI_IMR_TXRDY (0x1u << 2) /*< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask /
	#define TWI_IMR_SVACC (0x1u << 4) /*< \brief (TWI_IMR) Slave Access Interrupt Mask /
	#define TWI_IMR_GACC (0x1u << 5) /*< \brief (TWI_IMR) General Call Access Interrupt Mask /
	#define TWI_IMR_OVRE (0x1u << 6) /*< \brief (TWI_IMR) Overrun Error Interrupt Mask /
	#define TWI_IMR_NACK (0x1u << 8) /*< \brief (TWI_IMR) Not Acknowledge Interrupt Mask /
	#define TWI_IMR_ARBLST (0x1u << 9) /*< \brief (TWI_IMR) Arbitration Lost Interrupt Mask /
	#define TWI_IMR_SCL_WS (0x1u << 10) /*< \brief (TWI_IMR) Clock Wait State Interrupt Mask /
	#define TWI_IMR_EOSACC (0x1u << 11) /*< \brief (TWI_IMR) End Of Slave Access Interrupt Mask /
	/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
	#define TWI_RHR_RXDATA_Pos 0
	#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /*< \brief (TWI_RHR) Master or Slave Receive Holding Data /
	/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
	#define TWI_THR_TXDATA_Pos 0
	#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /*< \brief (TWI_THR) Master or Slave Transmit Holding Data /
	#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
	/* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */
	#define TWI_WPMR_WPEN (0x1u << 0) /*< \brief (TWI_WPMR) Write Protection Enable /
	#define TWI_WPMR_WPKEY_Pos 8
	#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /*< \brief (TWI_WPMR) Write Protection Key /
	#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /*< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 /
	/* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */
	#define TWI_WPSR_WPVS (0x1u << 0) /*< \brief (TWI_WPSR) Write Protection Violation Status /
	#define TWI_WPSR_WPVSRC_Pos 8
	#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /*< \brief (TWI_WPSR) Write Protection Violation Source /

	/@}/


	#endif /* _SAM_TWI_COMPONENT_ */