FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/source/mpu.c

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 * ----------------------------------------------------------------------------
 * Copyright (c) 2014, Atmel Corporation
 *
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/** \file */

/** 
 * \addtogroup mmu MMU Initialization
 *
 * \section Usage
 *
 * Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or
 * translation table entries. TLBs avoid the requirement for every memory access to perform a translation table
 * lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a
 * similar way to the requirements for caches, the architecture only defines certain principles for TLBs:
 * 
 * The MMU supports memory accesses based on memory sections or pages:
 * Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.
 * -# Sections Consist of 1MB blocks of memory.
 * -# Large pages Consist of 64KB blocks of memory.
 * -# Small pages Consist of 4KB blocks of memory.
 *
 * Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.
 * Memory region attributes
 * Each TLB entry has an associated set of memory region attributes. These control accesses to the caches,
 * how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.
 *
 * Related files:\n
 * \ref mmu.c\n
 * \ref mmu.h \n
 */

/*------------------------------------------------------------------------------ */
/*         Headers                                                               */
/*------------------------------------------------------------------------------ */
#include <chip.h>

/*----------------------------------------------------------------------------
 *        Exported functions

 *----------------------------------------------------------------------------*/
/**
 * \brief Enables the MPU module.
 *
 * \param dwMPUEnable  Enable/Disable the memory region.
 */
void MPU_Enable( uint32_t dwMPUEnable )
{
    MPU->CTRL = dwMPUEnable ;
}

/**
 * \brief Set active memory region.
 *
 * \param dwRegionNum  The memory region to be active.
 */
void MPU_SetRegionNum( uint32_t dwRegionNum )
{
    MPU->RNR = dwRegionNum;
}

/**
 * \brief Disable the current active region.
 */
extern void MPU_DisableRegion( void )
{
    MPU->RASR &= 0xfffffffe;
}

/**
 * \brief Setup a memory region.
 *
 * \param dwRegionBaseAddr  Memory region base address.
 * \param dwRegionAttr  Memory region attributes.  
 */
void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr )
{
    MPU->RBAR = dwRegionBaseAddr;
    MPU->RASR = dwRegionAttr;
}


/**
 * \brief Calculate region size for the RASR.
 */
uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes )
{
    uint32_t dwRegionSize = 32;
    uint32_t dwReturnValue = 4;

    while( dwReturnValue < 31 )
    {
        if( dwActualSizeInBytes <= dwRegionSize )
        {
            break;
        }
        else
        {
            dwReturnValue++;
        }

        dwRegionSize <<= 1;
    }

    return ( dwReturnValue << 1 );
}


/**
 *  \brief Update MPU regions.
 *
 *  \return Unused (ANSI-C compatibility).
 */
void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
        uint32_t dwRegionAttr)
{
    /* Raise privilege, the MPU register could be set only in privilege mode */
    asm volatile(" swi 0x00 ");
    while (!dwRaisePriDone);
    dwRaisePriDone = 0;

    /* Disable interrupt */
    __disable_irq();

    /* Clean up data and instruction buffer */
    __DSB();
    __ISB();

    /* Set active region */
    MPU_SetRegionNum(dwRegionNum);

    /* Disable region */
    MPU_DisableRegion();

    /* Update region attribute */
    MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);

    /* Clean up data and instruction buffer to make the new region taking 
       effect at once */
    __DSB();
    __ISB();

    /* Enable the interrupt */
    __enable_irq();

    /* Reset to thread mode */
    __set_CONTROL(USER_MODE);
}