| /****************************************************************************** |
| * |
| * Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a copy |
| * of this software and associated documentation files (the "Software"), to deal |
| * in the Software without restriction, including without limitation the rights |
| * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| * copies of the Software, and to permit persons to whom the Software is |
| * furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * Use of the Software is limited solely to applications: |
| * (a) running on a Xilinx device, or |
| * (b) that interact with a Xilinx device through a bus or interconnect. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Except as contained in this notice, the name of the Xilinx shall not be used |
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| * this Software without prior written authorization from Xilinx. |
| * |
| ******************************************************************************/ |
| /****************************************************************************** |
| * |
| * microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len) |
| * |
| *Flush a L2 Cache range |
| * |
| *Parameters: |
| * 'cacheaddr' - address in the L2 cache where the flush begins |
| * 'len ' - length (in bytes) worth of L2 cache to be flushed |
| * |
| *******************************************************************************/ |
| |
| #include "xparameters.h" |
| |
| #define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16 |
| |
| .text |
| .globl microblaze_flush_cache_ext_range |
| .ent microblaze_flush_cache_ext_range |
| .align 2 |
| |
| microblaze_flush_cache_ext_range: |
| #if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1)) |
| beqi r6, Loop_done |
| |
| addik r6, r6, -1 |
| add r6, r5, r6 |
| |
| andi r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) |
| andi r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) |
| |
| rsubk r6, r5, r6 |
| Loop_start: |
| wdc.ext.flush r5, r6 |
| bneid r6, Loop_start |
| addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN) |
| |
| Loop_done: |
| #endif |
| rtsd r15, 8 |
| nop |
| |
| .end microblaze_flush_cache_ext_range |