| # ARM V7 events |
| # From Scorpion Processor Family Programmer's Reference Manual (PRM) |
| # |
| include:arm/armv7-common |
| |
| event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates |
| event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses |
| event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses |
| event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 |
| event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 |
| event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed |
| event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort |
| event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ |
| event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ |
| event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts |
| event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined |
| event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC |
| event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC |
| event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort |
| event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check |
| event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check |
| event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU |
| event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU |
| event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate |
| event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU |
| |
| event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles |
| event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles |
| event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles |
| event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles |
| event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT |
| event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) |
| event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) |
| event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks |
| event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle |
| event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks |
| event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle |
| |
| event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR |
| event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates |
| event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses |
| event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses |
| event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses |
| event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates |
| event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates |
| event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses |
| event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses |
| event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses |
| event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses |
| event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID |
| event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA |
| event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all |
| event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail |
| event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold |
| event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op |
| event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op |
| event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier |
| |
| event:0x7e counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_DUAL_CYCLE : Scorpion VIU dual cycle |
| event:0x7f counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VIU_SINGLE_CYCLE : Scorpion VIU single cycle |
| event:0x80 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAR_STALL_CYCLES : Scorpion VX pipe WAR cycles |
| event:0x81 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_WAW_STALL_CYCLES : Scorpion VX pipe WAW cycles |
| event:0x82 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_RAW_STALL_CYCLES : Scorpion VX pipe RAW cycles |
| event:0x83 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VX_PIPE_LOAD_USE_STALL : Scorpion VX pipe load use stall |
| event:0x84 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAR_STALL_CYCLES : Scorpion VS pipe WAR stall cycles |
| event:0x85 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_WAW_STALL_CYCLES : Scorpion VS pipe WAW stall cycles |
| event:0x86 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_VS_PIPE_RAW_STALL_CYCLES : Scorpion VS pipe RAW stall cycles |
| event:0x87 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_INV_OPERATION : Scorpion invalid operation exceptions |
| event:0x88 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DIV_BY_ZERO : Scorpion divide by zero exceptions |
| event:0x89 counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VX_PIPE : Scorpion conditional instruction fail VX pipe |
| event:0x8a counters:1,2,3,4 um:zero minimum:500 name:SCORPION_COND_INST_FAIL_VS_PIPE : Scorpion conditional instruction fail VS pipe |
| event:0x8b counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_OVERFLOW : Scorpion overflow exceptions |
| event:0x8c counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_UNDERFLOW : Scorpion underflow exceptions |
| event:0x8d counters:1,2,3,4 um:zero minimum:500 name:SCORPION_EXCEPTIONS_DENORM : Scorpion denorm exceptions |
| |
| event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits |
| event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses |
| event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits |
| event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses |
| event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits |
| event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses |
| event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits |
| event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses |
| event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits |
| event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses |
| event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits |
| event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses |
| event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus |
| event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus |
| event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes |
| event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus |
| event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) |
| event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus |
| event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) |
