linux-imx/arch/arm/mach-imx/mach-imx6q.c - nest-learning-thermostat/5.1.3/linux - Git at Google

 /*
  * Copyright 2011-2014 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
  * Version 2 or later at the following locations:
  *
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */

 #include <linux/can/platform/flexcan.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/cpu.h>
 #include <linux/export.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 #include <linux/of_platform.h>
 #include <linux/opp.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/of_net.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>

 #include "common.h"
 #include "cpuidle.h"
 #include "hardware.h"

 static struct flexcan_platform_data flexcan_pdata[2];
 static int flexcan_en_gpio;
 static int flexcan_stby_gpio;
 static int flexcan0_en;
 static int flexcan1_en;
 static void mx6q_flexcan_switch(void)
 {
 	if (flexcan0_en || flexcan1_en) {
 		/*
 		 * The transceiver TJA1041A on sabreauto RevE baseboard will
 		 * fail to transit to Normal state if EN/STBY is high by default
 		 * after board power up. So we set the EN/STBY initial state to low
 		 * first then to high to guarantee the state transition successfully.
 		 */
 		gpio_set_value_cansleep(flexcan_en_gpio, 0);
 		gpio_set_value_cansleep(flexcan_stby_gpio, 0);

 		gpio_set_value_cansleep(flexcan_en_gpio, 1);
 		gpio_set_value_cansleep(flexcan_stby_gpio, 1);
 	} else {
 		/*
 		 * avoid to disable CAN xcvr if any of the CAN interfaces
 		 * are down. XCRV will be disabled only if both CAN2
 		 * interfaces are DOWN.
 		*/
 		gpio_set_value_cansleep(flexcan_en_gpio, 0);
 		gpio_set_value_cansleep(flexcan_stby_gpio, 0);
 	}
 }

 static void imx6q_flexcan0_switch_auto(int enable)
 {
 	flexcan0_en = enable;
 	mx6q_flexcan_switch();
 }

 static void imx6q_flexcan1_switch_auto(int enable)
 {
 	flexcan1_en = enable;
 	mx6q_flexcan_switch();
 }

 static int __init imx6q_flexcan_fixup_auto(void)
 {
 	struct device_node *np;

 	np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000");
 	if (!np)
 		return -ENODEV;

 	flexcan_en_gpio = of_get_named_gpio(np, "trx-en-gpio", 0);
 	flexcan_stby_gpio = of_get_named_gpio(np, "trx-stby-gpio", 0);
 	if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) &&
 		!gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") &&
 		!gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) {
 		/* flexcan 0 & 1 are using the same GPIOs for transceiver */
 		flexcan_pdata[0].transceiver_switch = imx6q_flexcan0_switch_auto;
 		flexcan_pdata[1].transceiver_switch = imx6q_flexcan1_switch_auto;
 	}

 	return 0;
 }

 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
 	if (IS_BUILTIN(CONFIG_PHYLIB)) {
 		/* min rx data delay */
 		phy_write(phydev, 0x0b, 0x8105);
 		phy_write(phydev, 0x0c, 0x0000);

 		/* max rx/tx clock delay, min rx/tx control delay */
 		phy_write(phydev, 0x0b, 0x8104);
 		phy_write(phydev, 0x0c, 0xf0f0);
 		phy_write(phydev, 0x0b, 0x104);
 	}

 	return 0;
 }

 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
 {
 	phy_write(dev, 0x0d, device);
 	phy_write(dev, 0x0e, reg);
 	phy_write(dev, 0x0d, (1 << 14) | device);
 	phy_write(dev, 0x0e, val);
 }

 static int ksz9031rn_phy_fixup(struct phy_device *dev)
 {
 	/*
 	 * min rx data delay, max rx/tx clock delay,
 	 * min rx/tx control delay
 	 */
 	mmd_write_reg(dev, 2, 4, 0);
 	mmd_write_reg(dev, 2, 5, 0);
 	mmd_write_reg(dev, 2, 8, 0x003ff);

 	return 0;
 }

 static int ar8031_phy_fixup(struct phy_device *dev)
 {
 	u16 val;

 	/* disable phy AR8031 SmartEEE function. */
 	phy_write(dev, 0xd, 0x3);
 	phy_write(dev, 0xe, 0x805d);
 	phy_write(dev, 0xd, 0x4003);
 	val = phy_read(dev, 0xe);
 	val &= ~(0x1 << 8);
 	phy_write(dev, 0xe, val);

 	/* To enable AR8031 output a 125MHz clk from CLK_25M */
 	phy_write(dev, 0xd, 0x7);
 	phy_write(dev, 0xe, 0x8016);
 	phy_write(dev, 0xd, 0x4007);

 	val = phy_read(dev, 0xe);
 	val &= 0xffe3;
 	val |= 0x18;
 	phy_write(dev, 0xe, val);

 	/* introduce tx clock delay */
 	phy_write(dev, 0x1d, 0x5);
 	val = phy_read(dev, 0x1e);
 	val |= 0x0100;
 	phy_write(dev, 0x1e, val);

 	return 0;
 }

 #define PHY_ID_AR8031	0x004dd074

 static void __init imx6q_enet_phy_init(void)
 {
 	if (IS_BUILTIN(CONFIG_PHYLIB)) {
 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 				ksz9021rn_phy_fixup);
 		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
 				ksz9031rn_phy_fixup);
 		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
 				ar8031_phy_fixup);
 	}
 }

 static void __init imx6q_1588_init(void)
 {
 	struct regmap *gpr;

 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 	if (!IS_ERR(gpr))
 		regmap_update_bits(gpr, IOMUXC_GPR1,
 				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
 				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
 	else
 		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

 }

 static void __init imx6q_csi_mux_init(void)
 {
 	/*
 	 * MX6Q SabreSD board:
 	 * IPU1 CSI0 connects to parallel interface.
 	 * Set GPR1 bit 19 to 0x1.
 	 *
 	 * MX6DL SabreSD board:
 	 * IPU1 CSI0 connects to parallel interface.
 	 * Set GPR13 bit 0-2 to 0x4.
 	 * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
 	 * Set GPR13 bit 3-5 to 0x1.
 	 */
 	struct regmap *gpr;

 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 	if (!IS_ERR(gpr)) {
 		if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
 			of_machine_is_compatible("fsl,imx6q-sabreauto"))
 			regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
 		else if (of_machine_is_compatible("fsl,imx6dl-sabresd") ||
 			 of_machine_is_compatible("fsl,imx6dl-sabreauto"))
 			regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
 	} else {
 		pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
 		       __func__);
 	}
 }

 #define OCOTP_MACn(n)	(0x00000620 + (n) * 0x10)
 void __init imx6_enet_mac_init(const char *compatible)
 {
 	struct device_node *ocotp_np, *enet_np, *from = NULL;
 	void __iomem *base;
 	struct property *newmac;
 	u32 macaddr_low;
 	u32 macaddr_high = 0;
 	u32 macaddr1_high = 0;
 	u8 *macaddr;
 	int i;

 	for (i = 0; i < 2; i++) {
 		enet_np = of_find_compatible_node(from, NULL, compatible);
 		if (!enet_np)
 			return;

 		from = enet_np;

 		if (of_get_mac_address(enet_np))
 			goto put_enet_node;

 		ocotp_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 		if (!ocotp_np) {
 			pr_warn("failed to find ocotp node\n");
 			goto put_enet_node;
 		}

 		base = of_iomap(ocotp_np, 0);
 		if (!base) {
 			pr_warn("failed to map ocotp\n");
 			goto put_ocotp_node;
 		}

 		macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
 		if (i)
 			macaddr1_high = readl_relaxed(base + OCOTP_MACn(2));
 		else
 			macaddr_high = readl_relaxed(base + OCOTP_MACn(0));

 		newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
 		if (!newmac)
 			goto put_ocotp_node;

 		newmac->value = newmac + 1;
 		newmac->length = 6;
 		newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
 		if (!newmac->name) {
 			kfree(newmac);
 			goto put_ocotp_node;
 		}

 		macaddr = newmac->value;
 		if (i) {
 			macaddr[5] = (macaddr_low >> 16) & 0xff;
 			macaddr[4] = (macaddr_low >> 24) & 0xff;
 			macaddr[3] = macaddr1_high & 0xff;
 			macaddr[2] = (macaddr1_high >> 8) & 0xff;
 			macaddr[1] = (macaddr1_high >> 16) & 0xff;
 			macaddr[0] = (macaddr1_high >> 24) & 0xff;
 		} else {
 			macaddr[5] = macaddr_high & 0xff;
 			macaddr[4] = (macaddr_high >> 8) & 0xff;
 			macaddr[3] = (macaddr_high >> 16) & 0xff;
 			macaddr[2] = (macaddr_high >> 24) & 0xff;
 			macaddr[1] = macaddr_low & 0xff;
 			macaddr[0] = (macaddr_low >> 8) & 0xff;
 		}

 		of_update_property(enet_np, newmac);

 put_ocotp_node:
 	of_node_put(ocotp_np);
 put_enet_node:
 	of_node_put(enet_np);
 	}
 }

 static inline void imx6q_enet_init(void)
 {
 	imx6_enet_mac_init("fsl,imx6q-fec");
 	imx6q_enet_phy_init();
 	imx6q_1588_init();
 }

 /* Add auxdata to pass platform data */
 static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]),
 	OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]),
 	{ /* sentinel */ }
 };

 static void __init imx6q_init_machine(void)
 {
 	struct device *parent;

 	mxc_arch_reset_init_dt();
 	parent = imx_soc_device_init();
 	if (parent == NULL)
 		pr_warn("failed to initialize soc device\n");

 	of_platform_populate(NULL, of_default_bus_match_table,
 					imx6q_auxdata_lookup, parent);

 	imx6q_enet_init();
 	imx_anatop_init();
 	imx6_pm_init();
 	imx6q_csi_mux_init();
 }

 #define OCOTP_CFG3			0x440
 #define OCOTP_CFG3_SPEED_SHIFT		16
 #define OCOTP_CFG3_SPEED_1P2GHZ		0x3
 #define OCOTP_CFG3_SPEED_1GHZ		0x2
 #define OCOTP_CFG3_SPEED_850MHZ		0x1
 #define OCOTP_CFG3_SPEED_800MHZ		0x0

 static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
 {
 	struct device_node *np;
 	void __iomem *base;
 	u32 val;

 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 	if (!np) {
 		pr_warn("failed to find ocotp node\n");
 		return;
 	}

 	base = of_iomap(np, 0);
 	if (!base) {
 		pr_warn("failed to map ocotp\n");
 		goto put_node;
 	}

 	/*
 	 * SPEED_GRADING[1:0] defines the max speed of ARM:
 	 * 2b'11: 1200000000Hz; -- i.MX6Q only.
 	 * 2b'10: 1000000000Hz;
 	 * 2b'01: 850000000Hz; -- i.MX6Q Only, exclusive with 1GHz.
 	 * 2b'00: 800000000Hz;
 	 * We need to set the max speed of ARM according to fuse map.
 	 */
 	val = readl_relaxed(base + OCOTP_CFG3);
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	if (cpu_is_imx6q()) {
 		if ((val & 0x3) < OCOTP_CFG3_SPEED_1P2GHZ)
 			if (opp_disable(cpu_dev, 1200000000))
 				pr_warn("failed to disable 1.2 GHz OPP\n");
 	}
 	if ((val & 0x3) < OCOTP_CFG3_SPEED_1GHZ)
 		if (opp_disable(cpu_dev, 996000000))
 			pr_warn("failed to disable 1 GHz OPP\n");
 	if (cpu_is_imx6q()) {
 		if ((val & 0x3) < OCOTP_CFG3_SPEED_850MHZ ||
 			(val & 0x3) == OCOTP_CFG3_SPEED_1GHZ)
 			if (opp_disable(cpu_dev, 852000000))
 				pr_warn("failed to disable 850 MHz OPP\n");
 	}

 	if (IS_ENABLED(CONFIG_MX6_VPU_352M)) {
 		if (opp_disable(cpu_dev, 396000000))
 			pr_warn("failed to disable 396MHz OPP\n");
 		pr_info("remove 396MHz OPP for VPU running at 352MHz!\n");
 	}

 put_node:
 	of_node_put(np);
 }

 static void __init imx6q_opp_init(struct device *cpu_dev)
 {
 	struct device_node *np;

 	np = of_find_node_by_path("/cpus/cpu@0");
 	if (!np) {
 		pr_warn("failed to find cpu0 node\n");
 		return;
 	}

 	cpu_dev->of_node = np;
 	if (of_init_opp_table(cpu_dev)) {
 		pr_warn("failed to init OPP table\n");
 		goto put_node;
 	}

 	imx6q_opp_check_speed_grading(cpu_dev);

 put_node:
 	of_node_put(np);
 }

 #define ESAI_AUDIO_MCLK 24576000

 static void __init imx6q_audio_lvds2_init(void)
 {
 	struct clk *pll4_sel, *lvds2_in, *pll4_audio_div, *esai_extal;

 	pll4_audio_div = clk_get_sys(NULL, "pll4_audio_div");
 	pll4_sel = clk_get_sys(NULL, "pll4_sel");
 	lvds2_in = clk_get_sys(NULL, "lvds2_in");
 	esai_extal = clk_get_sys(NULL, "esai_extal");
 	if (IS_ERR(pll4_audio_div) || IS_ERR(pll4_sel) ||
 	    IS_ERR(lvds2_in) || IS_ERR(esai_extal))
 		return;

 	if (clk_get_rate(lvds2_in) != ESAI_AUDIO_MCLK)
 		return;

 	clk_set_parent(pll4_sel, lvds2_in);
 	clk_set_rate(pll4_audio_div, 786432000);
 	clk_set_rate(esai_extal, ESAI_AUDIO_MCLK);
 }

 static struct platform_device imx6q_cpufreq_pdev = {
 	.name = "imx6-cpufreq",
 };

 static void __init imx6q_init_late(void)
 {
 	struct regmap *gpr;

 	/*
 	 * Need to force IOMUXC irq pending to meet CCM low power mode
 	 * restriction, this is recommended by hardware team.
 	 */
 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 	if (!IS_ERR(gpr))
 		regmap_update_bits(gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_GINT_MASK,
 			IMX6Q_GPR1_GINT_ASSERT);

 	/*
 	 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
 	 * to run cpuidle on them.
 	 */
 	if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
 		|| (cpu_is_imx6dl() && imx_get_soc_revision() >
 		IMX_CHIP_REVISION_1_0))
 		imx6q_cpuidle_init();

 	if (IS_ENABLED(CONFIG_ARM_IMX6_CPUFREQ)) {
 		imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
 		platform_device_register(&imx6q_cpufreq_pdev);
 	}

 	if (of_machine_is_compatible("fsl,imx6q-sabreauto")
 		|| of_machine_is_compatible("fsl,imx6dl-sabreauto")) {
 		imx6q_flexcan_fixup_auto();
 		imx6q_audio_lvds2_init();
 	}
 }

 static void __init imx6q_map_io(void)
 {
 	debug_ll_io_init();
 	imx_scu_map_io();
 	imx6_pm_map_io();
 	imx6_busfreq_map_io();
 }

 static void __init imx6q_init_irq(void)
 {
 	imx_init_revision_from_anatop();
 	imx_init_l2cache();
 	imx_src_init();
 	imx_gpc_init();
 	irqchip_init();
 }

 static void __init imx6q_timer_init(void)
 {
 	of_clk_init(NULL);
 	clocksource_of_init();
 	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
 			      imx_get_soc_revision());
 }

 static const char *imx6q_dt_compat[] __initdata = {
 	"fsl,imx6dl",
 	"fsl,imx6q",
 	NULL,
 };

 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
 	/*
 	 * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
 	 * GPU has a limit on physical address that it accesses, which must
 	 * be below 2GiB.
 	 */
 	.dma_zone_size	= (SZ_2G - SZ_256M),
 	.smp		= smp_ops(imx_smp_ops),
 	.map_io		= imx6q_map_io,
 	.init_irq	= imx6q_init_irq,
 	.init_time	= imx6q_timer_init,
 	.init_machine	= imx6q_init_machine,
 	.init_late      = imx6q_init_late,
 	.dt_compat	= imx6q_dt_compat,
 	.restart	= mxc_restart,
 MACHINE_END
	/*
	* Copyright 2011-2014 Freescale Semiconductor, Inc.
	* Copyright 2011 Linaro Ltd.
	*
	* The code contained herein is licensed under the GNU General Public
	* License. You may obtain a copy of the GNU General Public License
	* Version 2 or later at the following locations:
	*
	* http://www.opensource.org/licenses/gpl-license.html
	* http://www.gnu.org/copyleft/gpl.html
	*/

	#include <linux/can/platform/flexcan.h>
	#include <linux/clk.h>
	#include <linux/clk-provider.h>
	#include <linux/clkdev.h>
	#include <linux/clocksource.h>
	#include <linux/cpu.h>
	#include <linux/export.h>
	#include <linux/gpio.h>
	#include <linux/init.h>
	#include <linux/io.h>
	#include <linux/irq.h>
	#include <linux/irqchip.h>
	#include <linux/of.h>
	#include <linux/of_address.h>
	#include <linux/of_irq.h>
	#include <linux/of_gpio.h>
	#include <linux/of_platform.h>
	#include <linux/opp.h>
	#include <linux/phy.h>
	#include <linux/regmap.h>
	#include <linux/micrel_phy.h>
	#include <linux/mfd/syscon.h>
	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	#include <linux/of_net.h>
	#include <asm/mach/arch.h>
	#include <asm/mach/map.h>
	#include <asm/system_misc.h>

	#include "common.h"
	#include "cpuidle.h"
	#include "hardware.h"

	static struct flexcan_platform_data flexcan_pdata[2];
	static int flexcan_en_gpio;
	static int flexcan_stby_gpio;
	static int flexcan0_en;
	static int flexcan1_en;
	static void mx6q_flexcan_switch(void)
	{
	if (flexcan0_en \|\| flexcan1_en) {
	/*
	* The transceiver TJA1041A on sabreauto RevE baseboard will
	* fail to transit to Normal state if EN/STBY is high by default
	* after board power up. So we set the EN/STBY initial state to low
	* first then to high to guarantee the state transition successfully.
	*/
	gpio_set_value_cansleep(flexcan_en_gpio, 0);
	gpio_set_value_cansleep(flexcan_stby_gpio, 0);

	gpio_set_value_cansleep(flexcan_en_gpio, 1);
	gpio_set_value_cansleep(flexcan_stby_gpio, 1);
	} else {
	/*
	* avoid to disable CAN xcvr if any of the CAN interfaces
	* are down. XCRV will be disabled only if both CAN2
	* interfaces are DOWN.
	*/
	gpio_set_value_cansleep(flexcan_en_gpio, 0);
	gpio_set_value_cansleep(flexcan_stby_gpio, 0);
	}
	}

	static void imx6q_flexcan0_switch_auto(int enable)
	{
	flexcan0_en = enable;
	mx6q_flexcan_switch();
	}

	static void imx6q_flexcan1_switch_auto(int enable)
	{
	flexcan1_en = enable;
	mx6q_flexcan_switch();
	}

	static int __init imx6q_flexcan_fixup_auto(void)
	{
	struct device_node *np;

	np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000");
	if (!np)
	return -ENODEV;

	flexcan_en_gpio = of_get_named_gpio(np, "trx-en-gpio", 0);
	flexcan_stby_gpio = of_get_named_gpio(np, "trx-stby-gpio", 0);
	if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) &&
	!gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") &&
	!gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) {
	/* flexcan 0 & 1 are using the same GPIOs for transceiver */
	flexcan_pdata[0].transceiver_switch = imx6q_flexcan0_switch_auto;
	flexcan_pdata[1].transceiver_switch = imx6q_flexcan1_switch_auto;
	}

	return 0;
	}

	/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
	static int ksz9021rn_phy_fixup(struct phy_device *phydev)
	{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
	/* min rx data delay */
	phy_write(phydev, 0x0b, 0x8105);
	phy_write(phydev, 0x0c, 0x0000);

	/* max rx/tx clock delay, min rx/tx control delay */
	phy_write(phydev, 0x0b, 0x8104);
	phy_write(phydev, 0x0c, 0xf0f0);
	phy_write(phydev, 0x0b, 0x104);
	}

	return 0;
	}

	static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
	{
	phy_write(dev, 0x0d, device);
	phy_write(dev, 0x0e, reg);
	phy_write(dev, 0x0d, (1 << 14) \| device);
	phy_write(dev, 0x0e, val);
	}

	static int ksz9031rn_phy_fixup(struct phy_device *dev)
	{
	/*
	* min rx data delay, max rx/tx clock delay,
	* min rx/tx control delay
	*/
	mmd_write_reg(dev, 2, 4, 0);
	mmd_write_reg(dev, 2, 5, 0);
	mmd_write_reg(dev, 2, 8, 0x003ff);

	return 0;
	}

	static int ar8031_phy_fixup(struct phy_device *dev)
	{
	u16 val;

	/* disable phy AR8031 SmartEEE function. */
	phy_write(dev, 0xd, 0x3);
	phy_write(dev, 0xe, 0x805d);
	phy_write(dev, 0xd, 0x4003);
	val = phy_read(dev, 0xe);
	val &= ~(0x1 << 8);
	phy_write(dev, 0xe, val);

	/* To enable AR8031 output a 125MHz clk from CLK_25M */
	phy_write(dev, 0xd, 0x7);
	phy_write(dev, 0xe, 0x8016);
	phy_write(dev, 0xd, 0x4007);

	val = phy_read(dev, 0xe);
	val &= 0xffe3;
	val \|= 0x18;
	phy_write(dev, 0xe, val);

	/* introduce tx clock delay */
	phy_write(dev, 0x1d, 0x5);
	val = phy_read(dev, 0x1e);
	val \|= 0x0100;
	phy_write(dev, 0x1e, val);

	return 0;
	}

	#define PHY_ID_AR8031 0x004dd074

	static void __init imx6q_enet_phy_init(void)
	{
	if (IS_BUILTIN(CONFIG_PHYLIB)) {
	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
	ksz9021rn_phy_fixup);
	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
	ksz9031rn_phy_fixup);
	phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
	ar8031_phy_fixup);
	}
	}

	static void __init imx6q_1588_init(void)
	{
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
	regmap_update_bits(gpr, IOMUXC_GPR1,
	IMX6Q_GPR1_ENET_CLK_SEL_MASK,
	IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
	else
	pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");

	}

	static void __init imx6q_csi_mux_init(void)
	{
	/*
	* MX6Q SabreSD board:
	* IPU1 CSI0 connects to parallel interface.
	* Set GPR1 bit 19 to 0x1.
	*
	* MX6DL SabreSD board:
	* IPU1 CSI0 connects to parallel interface.
	* Set GPR13 bit 0-2 to 0x4.
	* IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
	* Set GPR13 bit 3-5 to 0x1.
	*/
	struct regmap *gpr;

	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr)) {
	if (of_machine_is_compatible("fsl,imx6q-sabresd") \|\|
	of_machine_is_compatible("fsl,imx6q-sabreauto"))
	regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
	else if (of_machine_is_compatible("fsl,imx6dl-sabresd") \|\|
	of_machine_is_compatible("fsl,imx6dl-sabreauto"))
	regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
	} else {
	pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
	__func__);
	}
	}

	#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
	void __init imx6_enet_mac_init(const char *compatible)
	{
	struct device_node ocotp_np, enet_np, *from = NULL;
	void __iomem *base;
	struct property *newmac;
	u32 macaddr_low;
	u32 macaddr_high = 0;
	u32 macaddr1_high = 0;
	u8 *macaddr;
	int i;

	for (i = 0; i < 2; i++) {
	enet_np = of_find_compatible_node(from, NULL, compatible);
	if (!enet_np)
	return;

	from = enet_np;

	if (of_get_mac_address(enet_np))
	goto put_enet_node;

	ocotp_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!ocotp_np) {
	pr_warn("failed to find ocotp node\n");
	goto put_enet_node;
	}

	base = of_iomap(ocotp_np, 0);
	if (!base) {
	pr_warn("failed to map ocotp\n");
	goto put_ocotp_node;
	}

	macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
	if (i)
	macaddr1_high = readl_relaxed(base + OCOTP_MACn(2));
	else
	macaddr_high = readl_relaxed(base + OCOTP_MACn(0));

	newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
	if (!newmac)
	goto put_ocotp_node;

	newmac->value = newmac + 1;
	newmac->length = 6;
	newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
	if (!newmac->name) {
	kfree(newmac);
	goto put_ocotp_node;
	}

	macaddr = newmac->value;
	if (i) {
	macaddr[5] = (macaddr_low >> 16) & 0xff;
	macaddr[4] = (macaddr_low >> 24) & 0xff;
	macaddr[3] = macaddr1_high & 0xff;
	macaddr[2] = (macaddr1_high >> 8) & 0xff;
	macaddr[1] = (macaddr1_high >> 16) & 0xff;
	macaddr[0] = (macaddr1_high >> 24) & 0xff;
	} else {
	macaddr[5] = macaddr_high & 0xff;
	macaddr[4] = (macaddr_high >> 8) & 0xff;
	macaddr[3] = (macaddr_high >> 16) & 0xff;
	macaddr[2] = (macaddr_high >> 24) & 0xff;
	macaddr[1] = macaddr_low & 0xff;
	macaddr[0] = (macaddr_low >> 8) & 0xff;
	}

	of_update_property(enet_np, newmac);

	put_ocotp_node:
	of_node_put(ocotp_np);
	put_enet_node:
	of_node_put(enet_np);
	}
	}

	static inline void imx6q_enet_init(void)
	{
	imx6_enet_mac_init("fsl,imx6q-fec");
	imx6q_enet_phy_init();
	imx6q_1588_init();
	}

	/* Add auxdata to pass platform data */
	static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
	OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]),
	OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]),
	{ /* sentinel */ }
	};

	static void __init imx6q_init_machine(void)
	{
	struct device *parent;

	mxc_arch_reset_init_dt();
	parent = imx_soc_device_init();
	if (parent == NULL)
	pr_warn("failed to initialize soc device\n");

	of_platform_populate(NULL, of_default_bus_match_table,
	imx6q_auxdata_lookup, parent);

	imx6q_enet_init();
	imx_anatop_init();
	imx6_pm_init();
	imx6q_csi_mux_init();
	}

	#define OCOTP_CFG3 0x440
	#define OCOTP_CFG3_SPEED_SHIFT 16
	#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
	#define OCOTP_CFG3_SPEED_1GHZ 0x2
	#define OCOTP_CFG3_SPEED_850MHZ 0x1
	#define OCOTP_CFG3_SPEED_800MHZ 0x0

	static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
	{
	struct device_node *np;
	void __iomem *base;
	u32 val;

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
	if (!np) {
	pr_warn("failed to find ocotp node\n");
	return;
	}

	base = of_iomap(np, 0);
	if (!base) {
	pr_warn("failed to map ocotp\n");
	goto put_node;
	}

	/*
	* SPEED_GRADING[1:0] defines the max speed of ARM:
	* 2b'11: 1200000000Hz; -- i.MX6Q only.
	* 2b'10: 1000000000Hz;
	* 2b'01: 850000000Hz; -- i.MX6Q Only, exclusive with 1GHz.
	* 2b'00: 800000000Hz;
	* We need to set the max speed of ARM according to fuse map.
	*/
	val = readl_relaxed(base + OCOTP_CFG3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	if (cpu_is_imx6q()) {
	if ((val & 0x3) < OCOTP_CFG3_SPEED_1P2GHZ)
	if (opp_disable(cpu_dev, 1200000000))
	pr_warn("failed to disable 1.2 GHz OPP\n");
	}
	if ((val & 0x3) < OCOTP_CFG3_SPEED_1GHZ)
	if (opp_disable(cpu_dev, 996000000))
	pr_warn("failed to disable 1 GHz OPP\n");
	if (cpu_is_imx6q()) {
	if ((val & 0x3) < OCOTP_CFG3_SPEED_850MHZ \|\|
	(val & 0x3) == OCOTP_CFG3_SPEED_1GHZ)
	if (opp_disable(cpu_dev, 852000000))
	pr_warn("failed to disable 850 MHz OPP\n");
	}

	if (IS_ENABLED(CONFIG_MX6_VPU_352M)) {
	if (opp_disable(cpu_dev, 396000000))
	pr_warn("failed to disable 396MHz OPP\n");
	pr_info("remove 396MHz OPP for VPU running at 352MHz!\n");
	}

	put_node:
	of_node_put(np);
	}

	static void __init imx6q_opp_init(struct device *cpu_dev)
	{
	struct device_node *np;

	np = of_find_node_by_path("/cpus/cpu@0");
	if (!np) {
	pr_warn("failed to find cpu0 node\n");
	return;
	}

	cpu_dev->of_node = np;
	if (of_init_opp_table(cpu_dev)) {
	pr_warn("failed to init OPP table\n");
	goto put_node;
	}

	imx6q_opp_check_speed_grading(cpu_dev);

	put_node:
	of_node_put(np);
	}

	#define ESAI_AUDIO_MCLK 24576000

	static void __init imx6q_audio_lvds2_init(void)
	{
	struct clk pll4_sel, lvds2_in, pll4_audio_div, esai_extal;

	pll4_audio_div = clk_get_sys(NULL, "pll4_audio_div");
	pll4_sel = clk_get_sys(NULL, "pll4_sel");
	lvds2_in = clk_get_sys(NULL, "lvds2_in");
	esai_extal = clk_get_sys(NULL, "esai_extal");
	if (IS_ERR(pll4_audio_div) \|\| IS_ERR(pll4_sel) \|\|
	IS_ERR(lvds2_in) \|\| IS_ERR(esai_extal))
	return;

	if (clk_get_rate(lvds2_in) != ESAI_AUDIO_MCLK)
	return;

	clk_set_parent(pll4_sel, lvds2_in);
	clk_set_rate(pll4_audio_div, 786432000);
	clk_set_rate(esai_extal, ESAI_AUDIO_MCLK);
	}

	static struct platform_device imx6q_cpufreq_pdev = {
	.name = "imx6-cpufreq",
	};

	static void __init imx6q_init_late(void)
	{
	struct regmap *gpr;

	/*
	* Need to force IOMUXC irq pending to meet CCM low power mode
	* restriction, this is recommended by hardware team.
	*/
	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (!IS_ERR(gpr))
	regmap_update_bits(gpr, IOMUXC_GPR1,
	IMX6Q_GPR1_GINT_MASK,
	IMX6Q_GPR1_GINT_ASSERT);

	/*
	* WAIT mode is broken on TO 1.0 and 1.1, so there is no point
	* to run cpuidle on them.
	*/
	if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
	\|\| (cpu_is_imx6dl() && imx_get_soc_revision() >
	IMX_CHIP_REVISION_1_0))
	imx6q_cpuidle_init();

	if (IS_ENABLED(CONFIG_ARM_IMX6_CPUFREQ)) {
	imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
	platform_device_register(&imx6q_cpufreq_pdev);
	}

	if (of_machine_is_compatible("fsl,imx6q-sabreauto")
	\|\| of_machine_is_compatible("fsl,imx6dl-sabreauto")) {
	imx6q_flexcan_fixup_auto();
	imx6q_audio_lvds2_init();
	}
	}

	static void __init imx6q_map_io(void)
	{
	debug_ll_io_init();
	imx_scu_map_io();
	imx6_pm_map_io();
	imx6_busfreq_map_io();
	}

	static void __init imx6q_init_irq(void)
	{
	imx_init_revision_from_anatop();
	imx_init_l2cache();
	imx_src_init();
	imx_gpc_init();
	irqchip_init();
	}

	static void __init imx6q_timer_init(void)
	{
	of_clk_init(NULL);
	clocksource_of_init();
	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
	imx_get_soc_revision());
	}

	static const char *imx6q_dt_compat[] __initdata = {
	"fsl,imx6dl",
	"fsl,imx6q",
	NULL,
	};

	DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
	/*
	* i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
	* GPU has a limit on physical address that it accesses, which must
	* be below 2GiB.
	*/
	.dma_zone_size = (SZ_2G - SZ_256M),
	.smp = smp_ops(imx_smp_ops),
	.map_io = imx6q_map_io,
	.init_irq = imx6q_init_irq,
	.init_time = imx6q_timer_init,
	.init_machine = imx6q_init_machine,
	.init_late = imx6q_init_late,
	.dt_compat = imx6q_dt_compat,
	.restart = mxc_restart,
	MACHINE_END