blob: 63ea70aa37d5f7d78920f8e1913794084d751f7e [file] [log] [blame]
Igor Sarkisovbd995ac2020-10-06 12:45:40 -07001/*
2 * Copyright (C) 2007-2008
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/MigoR/lowlevel_init.S
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <config.h>
14#include <version.h>
15
16#include <asm/processor.h>
17#include <asm/macro.h>
18
19/*
20 * Board specific low level init code, called _very_ early in the
21 * startup sequence. Relocation to SDRAM has not happened yet, no
22 * stack is available, bss section has not been initialised, etc.
23 *
24 * (Note: As no stack is available, no subroutines can be called...).
25 */
26
27 .global lowlevel_init
28
29 .text
30 .align 2
31
32lowlevel_init:
33 write32 CCR_A, CCR_D ! Address of Cache Control Register
34 ! Instruction Cache Invalidate
35
36 write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
37 ! TI == TLB Invalidate bit
38
39 write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
40
41 write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
42
43 write16 PFC_PULCR_A, PFC_PULCR_D
44
45 write16 PFC_DRVCR_A, PFC_DRVCR_D
46
47 write16 SBSCR_A, SBSCR_D
48
49 write16 PSCR_A, PSCR_D
50
51 write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
52 ! 0xA507 -> timer_STOP / WDT_CLK = max
53
54 write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
55 ! 0x5A00 -> Clear
56
57 write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
58 ! 0xA504 -> timer_STOP / CLK = 500ms
59
60 write32 DLLFRQ_A, DLLFRQ_D ! 20080115
61 ! 20080115
62
63 write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
64 ! 20080115
65
66 write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
67 ! ??
68
69bsc_init:
70 write32 CMNCR_A, CMNCR_D
71
72 write32 CS0BCR_A, CS0BCR_D
73
74 write32 CS4BCR_A, CS4BCR_D
75
76 write32 CS5ABCR_A, CS5ABCR_D
77
78 write32 CS5BBCR_A, CS5BBCR_D
79
80 write32 CS6ABCR_A, CS6ABCR_D
81
82 write32 CS0WCR_A, CS0WCR_D
83
84 write32 CS4WCR_A, CS4WCR_D
85
86 write32 CS5AWCR_A, CS5AWCR_D
87
88 write32 CS5BWCR_A, CS5BWCR_D
89
90 write32 CS6AWCR_A, CS6AWCR_D
91
92 ! SDRAM initialization
93 write32 SDCR_A, SDCR_D
94
95 write32 SDWCR_A, SDWCR_D
96
97 write32 SDPCR_A, SDPCR_D
98
99 write32 RTCOR_A, RTCOR_D
100
101 write32 RTCNT_A, RTCNT_D
102
103 write32 RTCSR_A, RTCSR_D
104
105 write32 RFCR_A, RFCR_D
106
107 write8 SDMR3_A, SDMR3_D
108
109 ! BL bit off (init = ON) (?!?)
110
111 stc sr, r0 ! BL bit off(init=ON)
112 mov.l SR_MASK_D, r1
113 and r1, r0
114 ldc r0, sr
115
116 rts
117 mov #0, r0
118
119 .align 4
120
121CCR_A: .long CCR
122MMUCR_A: .long MMUCR
123MSTPCR0_A: .long MSTPCR0
124MSTPCR2_A: .long MSTPCR2
125PFC_PULCR_A: .long PULCR
126PFC_DRVCR_A: .long DRVCR
127SBSCR_A: .long SBSCR
128PSCR_A: .long PSCR
129RWTCSR_A: .long RWTCSR
130RWTCNT_A: .long RWTCNT
131FRQCR_A: .long FRQCR
132PLLCR_A: .long PLLCR
133DLLFRQ_A: .long DLLFRQ
134
135CCR_D: .long 0x00000800
136CCR_D_2: .long 0x00000103
137MMUCR_D: .long 0x00000004
138MSTPCR0_D: .long 0x00001001
139MSTPCR2_D: .long 0xffffffff
140PFC_PULCR_D: .long 0x6000
141PFC_DRVCR_D: .long 0x0464
142FRQCR_D: .long 0x07033639
143PLLCR_D: .long 0x00005000
144DLLFRQ_D: .long 0x000004F6
145
146CMNCR_A: .long CMNCR
147CMNCR_D: .long 0x0000001B
148CS0BCR_A: .long CS0BCR
149CS0BCR_D: .long 0x24920400
150CS4BCR_A: .long CS4BCR
151CS4BCR_D: .long 0x00003400
152CS5ABCR_A: .long CS5ABCR
153CS5ABCR_D: .long 0x24920400
154CS5BBCR_A: .long CS5BBCR
155CS5BBCR_D: .long 0x24920400
156CS6ABCR_A: .long CS6ABCR
157CS6ABCR_D: .long 0x24920400
158
159CS0WCR_A: .long CS0WCR
160CS0WCR_D: .long 0x00000380
161CS4WCR_A: .long CS4WCR
162CS4WCR_D: .long 0x00110080
163CS5AWCR_A: .long CS5AWCR
164CS5AWCR_D: .long 0x00000300
165CS5BWCR_A: .long CS5BWCR
166CS5BWCR_D: .long 0x00000300
167CS6AWCR_A: .long CS6AWCR
168CS6AWCR_D: .long 0x00000300
169
170SDCR_A: .long SBSC_SDCR
171SDCR_D: .long 0x80160809
172SDWCR_A: .long SBSC_SDWCR
173SDWCR_D: .long 0x0014450C
174SDPCR_A: .long SBSC_SDPCR
175SDPCR_D: .long 0x00000087
176RTCOR_A: .long SBSC_RTCOR
177RTCNT_A: .long SBSC_RTCNT
178RTCNT_D: .long 0xA55A0012
179RTCOR_D: .long 0xA55A001C
180RTCSR_A: .long SBSC_RTCSR
181RFCR_A: .long SBSC_RFCR
182RFCR_D: .long 0xA55A0221
183RTCSR_D: .long 0xA55A009a
184SDMR3_A: .long 0xFE581180
185SDMR3_D: .long 0x0
186
187SR_MASK_D: .long 0xEFFFFF0F
188
189 .align 2
190
191SBSCR_D: .word 0x0044
192PSCR_D: .word 0x0000
193RWTCSR_D_1: .word 0xA507
194RWTCSR_D_2: .word 0xA504
195RWTCNT_D: .word 0x5A00