| /* |
| * Synopsys Designware PCIe host controller driver |
| * |
| * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| * http://www.samsung.com |
| * |
| * Author: Jingoo Han <jg1.han@samsung.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #ifndef _PCIE_DESIGNWARE_H |
| #define _PCIE_DESIGNWARE_H |
| |
| /* Synopsis specific PCIE configuration registers */ |
| #define PCIE_PORT_LINK_CONTROL 0x710 |
| #define PORT_LINK_MODE_MASK (0x3f << 16) |
| #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
| #define PORT_LINK_MODE_2_LANES (0x3 << 16) |
| #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
| |
| #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
| #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) |
| #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
| #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) |
| #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |
| |
| #define PCIE_MSI_ADDR_LO 0x820 |
| #define PCIE_MSI_ADDR_HI 0x824 |
| #define PCIE_MSI_INTR0_ENABLE 0x828 |
| #define PCIE_MSI_INTR0_MASK 0x82C |
| #define PCIE_MSI_INTR0_STATUS 0x830 |
| |
| #define PCIE_ATU_VIEWPORT 0x900 |
| #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
| #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
| #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
| #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
| #define PCIE_ATU_CR1 0x904 |
| #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
| #define PCIE_ATU_TYPE_IO (0x2 << 0) |
| #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
| #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
| #define PCIE_ATU_CR2 0x908 |
| #define PCIE_ATU_ENABLE (0x1 << 31) |
| #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
| #define PCIE_ATU_LOWER_BASE 0x90C |
| #define PCIE_ATU_UPPER_BASE 0x910 |
| #define PCIE_ATU_LIMIT 0x914 |
| #define PCIE_ATU_LOWER_TARGET 0x918 |
| #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
| #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
| #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
| #define PCIE_ATU_UPPER_TARGET 0x91C |
| |
| struct pcie_port_info { |
| u32 cfg0_size; |
| u32 cfg1_size; |
| u32 io_size; |
| u32 mem_size; |
| phys_addr_t io_bus_addr; |
| phys_addr_t mem_bus_addr; |
| }; |
| |
| /* |
| * Maximum number of MSI IRQs can be 256 per controller. But keep |
| * it 32 as of now. Probably we will never need more than 32. If needed, |
| * then increment it in multiple of 32. |
| */ |
| #define MAX_MSI_IRQS 32 |
| #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) |
| |
| struct pcie_port { |
| struct device *dev; |
| u8 root_bus_nr; |
| void __iomem *dbi_base; |
| u64 cfg0_base; |
| void __iomem *va_cfg0_base; |
| u64 cfg1_base; |
| void __iomem *va_cfg1_base; |
| u64 io_base; |
| u64 mem_base; |
| spinlock_t conf_lock; |
| struct resource cfg; |
| struct resource io; |
| struct resource mem; |
| struct pcie_port_info config; |
| int irq; |
| u32 lanes; |
| struct pcie_host_ops *ops; |
| u32 quirks; /* Deviations from spec. */ |
| int msi_irq; |
| struct irq_domain *irq_domain; |
| unsigned long msi_data; |
| DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); |
| u32 msi_inten_save[MAX_MSI_CTRLS]; |
| }; |
| |
| struct pcie_host_ops { |
| void (*readl_rc)(struct pcie_port *pp, |
| void __iomem *dbi_base, u32 *val); |
| void (*writel_rc)(struct pcie_port *pp, |
| u32 val, void __iomem *dbi_base); |
| int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); |
| int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); |
| int (*link_up)(struct pcie_port *pp); |
| int (*host_init)(struct pcie_port *pp); |
| void (*msi_set_irq)(struct pcie_port *pp, int irq); |
| void (*msi_clear_irq)(struct pcie_port *pp, int irq); |
| u32 (*get_msi_data)(struct pcie_port *pp); |
| u32 (*get_msi_addr)(struct pcie_port *pp); |
| }; |
| |
| int cfg_read(void __iomem *addr, int where, int size, u32 *val); |
| int cfg_write(void __iomem *addr, int where, int size, u32 val); |
| irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); |
| void dw_pcie_msi_init(struct pcie_port *pp); |
| void dw_pcie_msi_cfg_save(struct pcie_port *pp); |
| void dw_pcie_msi_cfg_restore(struct pcie_port *pp); |
| int dw_pcie_link_up(struct pcie_port *pp); |
| void dw_pcie_setup_rc(struct pcie_port *pp); |
| int dw_pcie_host_init(struct pcie_port *pp); |
| |
| #endif /* _PCIE_DESIGNWARE_H */ |