| # Cell Broadband Engine possible unit masks |
| # |
| # Copyright OProfile authors |
| # |
| #(C) COPYRIGHT International Business Machines Corp. 2006 |
| # Contributed by Maynard Johnson <maynardj@us.ibm.com> |
| # |
| # |
| name:zero type:mandatory default:0x0 |
| 0x000 Count cycles [mandatory] |
| name:PPU_0_cycles type:bitmask default:0x013 |
| 0x001 Count cycles [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [mandatory] |
| name:PPU_0_edges type:bitmask default:0x012 |
| 0x000 Count edges [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [mandatory] |
| name:PPU_2_cycles type:bitmask default:0x043 |
| 0x001 Count cycles [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x040 PPU Bus Word 2 [mandatory] |
| name:PPU_2_edges type:bitmask default:0x042 |
| 0x000 Count edges [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x040 PPU Bus Word 2 [mandatory] |
| name:PPU_01_cycles type:bitmask default:0x023 |
| 0x001 Count cycles [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [optional ] |
| 0x020 PPU Bus Word 1 [default ] |
| name:PPU_01_edges type:bitmask default:0x022 |
| 0x000 Count edges [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [optional ] |
| 0x020 PPU Bus Word 1 [default ] |
| name:PPU_01_cycles_or_edges type:bitmask default:0x023 |
| 0x000 Count edges [optional ] |
| 0x001 Count cycles [default ] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [optional ] |
| 0x020 PPU Bus Word 1 [default ] |
| name:PPU_02_cycles type:bitmask default:0x013 |
| 0x001 Count cycles [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [default ] |
| 0x040 PPU Bus Word 2 [optional ] |
| name:PPU_02_edges type:bitmask default:0x012 |
| 0x000 Count edges [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [default ] |
| 0x040 PPU Bus Word 2 [optional ] |
| name:PPU_02_cycles_or_edges type:bitmask default:0x013 |
| 0x000 Count edges [optional ] |
| 0x001 Count cycles [default ] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x010 PPU Bus Word 0 [default ] |
| 0x040 PPU Bus Word 2 [optional ] |
| name:PPU_0123_cycles type:bitmask default:0x033 |
| 0x001 Count cycles [mandatory] |
| 0x000 Negative polarity [optional ] |
| 0x002 Positive polarity [default ] |
| 0x030 PPU Bus Word 0/1 [default ] |
| 0x0c0 PPU Bus Word 2/3 [optional ] |
| name:SPU_02_cycles type:bitmask default:0x0113 |
| 0x0001 Count cycles [mandatory] |
| 0x0000 Negative polarity [optional ] |
| 0x0002 Positive polarity [default ] |
| 0x0110 SPU Bus Word 0 [default ] |
| 0x0140 SPU Bus Word 2 [optional ] |
| 0x0000 SPU 0 [default ] |
| 0x1000 SPU 1 [optional ] |
| 0x2000 SPU 2 [optional ] |
| 0x3000 SPU 3 [optional ] |
| 0x4000 SPU 4 [optional ] |
| 0x5000 SPU 5 [optional ] |
| 0x6000 SPU 6 [optional ] |
| 0x7000 SPU 7 [optional ] |
| name:SPU_02_cycles_or_edges type:bitmask default:0x0113 |
| 0x0000 Count edges [optional ] |
| 0x0001 Count cycles [default ] |
| 0x0000 Negative polarity [optional ] |
| 0x0002 Positive polarity [default ] |
| 0x0110 SPU Bus Word 0 [default ] |
| 0x0140 SPU Bus Word 2 [optional ] |
| 0x0000 SPU 0 [default ] |
| 0x1000 SPU 1 [optional ] |
| 0x2000 SPU 2 [optional ] |
| 0x3000 SPU 3 [optional ] |
| 0x4000 SPU 4 [optional ] |
| 0x5000 SPU 5 [optional ] |
| 0x6000 SPU 6 [optional ] |
| 0x7000 SPU 7 [optional ] |
| name:SPU_Trigger_cycles_or_edges type:bitmask default:0x0107 |
| 0x0000 Count edges [optional ] |
| 0x0001 Count cycles [default ] |
| 0x0000 Negative polarity [optional ] |
| 0x0002 Positive polarity [default ] |
| 0x0104 SPU Trigger 0 [default ] |
| 0x0114 SPU Trigger 1 [optional ] |
| 0x0124 SPU Trigger 2 [optional ] |
| 0x0134 SPU Trigger 3 [optional ] |
| 0x0000 SPU 0 [default ] |
| 0x1000 SPU 1 [optional ] |
| 0x2000 SPU 2 [optional ] |
| 0x3000 SPU 3 [optional ] |
| 0x4000 SPU 4 [optional ] |
| 0x5000 SPU 5 [optional ] |
| 0x6000 SPU 6 [optional ] |
| 0x7000 SPU 7 [optional ] |
| name:SPU_Event_cycles_or_edges type:bitmask default:0x0147 |
| 0x0000 Count edges [optional ] |
| 0x0001 Count cycles [default ] |
| 0x0000 Negative polarity [optional ] |
| 0x0002 Positive polarity [default ] |
| 0x0144 SPU Event 0 [default ] |
| 0x0154 SPU Event 1 [optional ] |
| 0x0164 SPU Event 2 [optional ] |
| 0x0174 SPU Event 3 [optional ] |
| 0x0000 SPU 0 [default ] |
| 0x1000 SPU 1 [optional ] |
| 0x2000 SPU 2 [optional ] |
| 0x3000 SPU 3 [optional ] |
| 0x4000 SPU 4 [optional ] |
| 0x5000 SPU 5 [optional ] |
| 0x6000 SPU 6 [optional ] |
| 0x7000 SPU 7 [optional ] |