Documentation/devicetree/bindings/interrupt-controller/nxp,imx-intmux.txt

* NXP i.MX8QM/i.MX8QXP INTMUX Interrupt Multiplexing

Required properties:
- compatible: "nxp,imx-intmux".
- reg: should contain IC registers location and length.
- clocks : ipg clock for intmux.
- interrupts: an interrupt to the parent interrupt controller.
- interrupt-controller: identifies the node as an interrupt controller.
- interrupt-parent: gic interrupt controller, link to parent
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
  The first cell is the IRQ number, the second cell is used to specify
  one of the supported IRQ types:
      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.

Optional properties:
- nxp,intmux_chans: specify the interrupt channel number, default is 1.

Examples:

	intmux_cm40: intmux@37400000 {
		compatible = "nxp,imx-intmux";
		reg = <0x0 0x37400000 0x0 0x1000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;
		clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
		clock-names = "ipg";
		power-domains = <&pd_cm40_intmux>;
		status = "disabled";
	};

	i2c0_cm40: i2c@37230000 {
		compatible = "fsl,imx8qm-lpi2c";
		reg = <0x0 0x37230000 0x0 0x1000>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&intmux_cm40>;
		clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
			<&clk IMX8QXP_CM40_I2C_IPG_CLK>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd_cm40_i2c>;
		status = "disabled";
	};