|  | /* | 
|  | * Samsung's Exynos4x12 SoCs device tree source | 
|  | * | 
|  | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | 
|  | *		http://www.samsung.com | 
|  | * | 
|  | * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 | 
|  | * based board files can include this file and provide values for board specfic | 
|  | * bindings. | 
|  | * | 
|  | * Note: This file does not include device nodes for all the controllers in | 
|  | * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional | 
|  | * nodes can be added to this file. | 
|  | * | 
|  | * This program is free software; you can redistribute it and/or modify | 
|  | * it under the terms of the GNU General Public License version 2 as | 
|  | ` * published by the Free Software Foundation. | 
|  | */ | 
|  |  | 
|  | #include "exynos4.dtsi" | 
|  | #include "exynos4x12-pinctrl.dtsi" | 
|  | #include "exynos4x12-pinctrl-uboot.dtsi" | 
|  |  | 
|  | / { | 
|  | aliases { | 
|  | pinctrl0 = &pinctrl_0; | 
|  | pinctrl1 = &pinctrl_1; | 
|  | pinctrl2 = &pinctrl_2; | 
|  | pinctrl3 = &pinctrl_3; | 
|  | mshc0 = &mshc_0; | 
|  | }; | 
|  |  | 
|  | pd_isp: isp-power-domain@10023CA0 { | 
|  | compatible = "samsung,exynos4210-pd"; | 
|  | reg = <0x10023CA0 0x20>; | 
|  | }; | 
|  |  | 
|  | clock: clock-controller@10030000 { | 
|  | compatible = "samsung,exynos4412-clock"; | 
|  | reg = <0x10030000 0x20000>; | 
|  | #clock-cells = <1>; | 
|  | }; | 
|  |  | 
|  | mct@10050000 { | 
|  | compatible = "samsung,exynos4412-mct"; | 
|  | reg = <0x10050000 0x800>; | 
|  | interrupt-parent = <&mct_map>; | 
|  | interrupts = <0>, <1>, <2>, <3>, <4>; | 
|  | clocks = <&clock 3>, <&clock 344>; | 
|  | clock-names = "fin_pll", "mct"; | 
|  |  | 
|  | mct_map: mct-map { | 
|  | #interrupt-cells = <1>; | 
|  | #address-cells = <0>; | 
|  | #size-cells = <0>; | 
|  | interrupt-map = <0 &gic 0 57 0>, | 
|  | <1 &combiner 12 5>, | 
|  | <2 &combiner 12 6>, | 
|  | <3 &combiner 12 7>, | 
|  | <4 &gic 1 12 0>; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | pinctrl_0: pinctrl@11400000 { | 
|  | compatible = "samsung,exynos4x12-pinctrl"; | 
|  | reg = <0x11400000 0x1000>; | 
|  | interrupts = <0 47 0>; | 
|  | }; | 
|  |  | 
|  | pinctrl_1: pinctrl@11000000 { | 
|  | compatible = "samsung,exynos4x12-pinctrl"; | 
|  | reg = <0x11000000 0x1000>; | 
|  | interrupts = <0 46 0>; | 
|  |  | 
|  | wakup_eint: wakeup-interrupt-controller { | 
|  | compatible = "samsung,exynos4210-wakeup-eint"; | 
|  | interrupt-parent = <&gic>; | 
|  | interrupts = <0 32 0>; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | pinctrl_2: pinctrl@03860000 { | 
|  | compatible = "samsung,exynos4x12-pinctrl"; | 
|  | reg = <0x03860000 0x1000>; | 
|  | interrupt-parent = <&combiner>; | 
|  | interrupts = <10 0>; | 
|  | }; | 
|  |  | 
|  | pinctrl_3: pinctrl@106E0000 { | 
|  | compatible = "samsung,exynos4x12-pinctrl"; | 
|  | reg = <0x106E0000 0x1000>; | 
|  | interrupts = <0 72 0>; | 
|  | }; | 
|  |  | 
|  | g2d@10800000 { | 
|  | compatible = "samsung,exynos4212-g2d"; | 
|  | reg = <0x10800000 0x1000>; | 
|  | interrupts = <0 89 0>; | 
|  | clocks = <&clock 177>, <&clock 277>; | 
|  | clock-names = "sclk_fimg2d", "fimg2d"; | 
|  | status = "disabled"; | 
|  | }; | 
|  |  | 
|  | mshc_0: mmc@12550000 { | 
|  | compatible = "samsung,exynos4412-dw-mshc"; | 
|  | reg = <0x12550000 0x1000>; | 
|  | interrupts = <0 77 0>; | 
|  | #address-cells = <1>; | 
|  | #size-cells = <0>; | 
|  | fifo-depth = <0x80>; | 
|  | clocks = <&clock 301>, <&clock 149>; | 
|  | clock-names = "biu", "ciu"; | 
|  | status = "disabled"; | 
|  | }; | 
|  | }; |