| /* |
| * Copyright (C) NXP Semiconductors (PLMA) |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef __TFA98XX_REGS_H__ |
| #define __TFA98XX_REGS_H__ |
| |
| |
| /** StatusReg Register ($00) ************************************************/ |
| |
| #define TFA98XX_STATUSREG 0x00 |
| #define TFA98XX_STATUSREG_VDDS (0x1<<0) |
| #define TFA98XX_STATUSREG_VDDS_POS 0 |
| #define TFA98XX_STATUSREG_VDDS_LEN 1 |
| #define TFA98XX_STATUSREG_VDDS_MAX 1 |
| #define TFA98XX_STATUSREG_VDDS_MSK 0x1 |
| |
| #define TFA98XX_STATUSREG_PLLS (0x1<<1) |
| #define TFA98XX_STATUSREG_PLLS_POS 1 |
| #define TFA98XX_STATUSREG_PLLS_LEN 1 |
| #define TFA98XX_STATUSREG_PLLS_MAX 1 |
| #define TFA98XX_STATUSREG_PLLS_MSK 0x2 |
| |
| #define TFA98XX_STATUSREG_OTDS (0x1<<2) |
| #define TFA98XX_STATUSREG_OTDS_POS 2 |
| #define TFA98XX_STATUSREG_OTDS_LEN 1 |
| #define TFA98XX_STATUSREG_OTDS_MAX 1 |
| #define TFA98XX_STATUSREG_OTDS_MSK 0x4 |
| |
| #define TFA98XX_STATUSREG_OVDS (0x1<<3) |
| #define TFA98XX_STATUSREG_OVDS_POS 3 |
| #define TFA98XX_STATUSREG_OVDS_LEN 1 |
| #define TFA98XX_STATUSREG_OVDS_MAX 1 |
| #define TFA98XX_STATUSREG_OVDS_MSK 0x8 |
| |
| #define TFA98XX_STATUSREG_UVDS (0x1<<4) |
| #define TFA98XX_STATUSREG_UVDS_POS 4 |
| #define TFA98XX_STATUSREG_UVDS_LEN 1 |
| #define TFA98XX_STATUSREG_UVDS_MAX 1 |
| #define TFA98XX_STATUSREG_UVDS_MSK 0x10 |
| |
| #define TFA98XX_STATUSREG_OCDS (0x1<<5) |
| #define TFA98XX_STATUSREG_OCDS_POS 5 |
| #define TFA98XX_STATUSREG_OCDS_LEN 1 |
| #define TFA98XX_STATUSREG_OCDS_MAX 1 |
| #define TFA98XX_STATUSREG_OCDS_MSK 0x20 |
| |
| #define TFA98XX_STATUSREG_CLKS (0x1<<6) |
| #define TFA98XX_STATUSREG_CLKS_POS 6 |
| #define TFA98XX_STATUSREG_CLKS_LEN 1 |
| #define TFA98XX_STATUSREG_CLKS_MAX 1 |
| #define TFA98XX_STATUSREG_CLKS_MSK 0x40 |
| |
| #define TFA98XX_STATUSREG_CLIPS (0x1<<7) |
| #define TFA98XX_STATUSREG_CLIPS_POS 7 |
| #define TFA98XX_STATUSREG_CLIPS_LEN 1 |
| #define TFA98XX_STATUSREG_CLIPS_MAX 1 |
| #define TFA98XX_STATUSREG_CLIPS_MSK 0x80 |
| |
| #define TFA98XX_STATUSREG_MTPB (0x1<<8) |
| #define TFA98XX_STATUSREG_MTPB_POS 8 |
| #define TFA98XX_STATUSREG_MTPB_LEN 1 |
| #define TFA98XX_STATUSREG_MTPB_MAX 1 |
| #define TFA98XX_STATUSREG_MTPB_MSK 0x100 |
| |
| #define TFA98XX_STATUSREG_NOCLK (0x1<<9) |
| #define TFA98XX_STATUSREG_NOCLK_POS 9 |
| #define TFA98XX_STATUSREG_NOCLK_LEN 1 |
| #define TFA98XX_STATUSREG_NOCLK_MAX 1 |
| #define TFA98XX_STATUSREG_NOCLK_MSK 0x200 |
| |
| #define TFA98XX_STATUSREG_SPKS (0x1<<10) |
| #define TFA98XX_STATUSREG_SPKS_POS 10 |
| #define TFA98XX_STATUSREG_SPKS_LEN 1 |
| #define TFA98XX_STATUSREG_SPKS_MAX 1 |
| #define TFA98XX_STATUSREG_SPKS_MSK 0x400 |
| |
| #define TFA98XX_STATUSREG_ACS (0x1<<11) |
| #define TFA98XX_STATUSREG_ACS_POS 11 |
| #define TFA98XX_STATUSREG_ACS_LEN 1 |
| #define TFA98XX_STATUSREG_ACS_MAX 1 |
| #define TFA98XX_STATUSREG_ACS_MSK 0x800 |
| |
| #define TFA98XX_STATUSREG_SWS (0x1<<12) |
| #define TFA98XX_STATUSREG_SWS_POS 12 |
| #define TFA98XX_STATUSREG_SWS_LEN 1 |
| #define TFA98XX_STATUSREG_SWS_MAX 1 |
| #define TFA98XX_STATUSREG_SWS_MSK 0x1000 |
| |
| #define TFA98XX_STATUSREG_WDS (0x1<<13) |
| #define TFA98XX_STATUSREG_WDS_POS 13 |
| #define TFA98XX_STATUSREG_WDS_LEN 1 |
| #define TFA98XX_STATUSREG_WDS_MAX 1 |
| #define TFA98XX_STATUSREG_WDS_MSK 0x2000 |
| |
| #define TFA98XX_STATUSREG_AMPS (0x1<<14) |
| #define TFA98XX_STATUSREG_AMPS_POS 14 |
| #define TFA98XX_STATUSREG_AMPS_LEN 1 |
| #define TFA98XX_STATUSREG_AMPS_MAX 1 |
| #define TFA98XX_STATUSREG_AMPS_MSK 0x4000 |
| |
| #define TFA98XX_STATUSREG_AREFS (0x1<<15) |
| #define TFA98XX_STATUSREG_AREFS_POS 15 |
| #define TFA98XX_STATUSREG_AREFS_LEN 1 |
| #define TFA98XX_STATUSREG_AREFS_MAX 1 |
| #define TFA98XX_STATUSREG_AREFS_MSK 0x8000 |
| |
| /** BatteryVoltage Register ($01) *******************************************/ |
| |
| #define TFA98XX_BATTERYVOLTAGE 0x01 |
| #define TFA98XX_BATTERYVOLTAGE_BATS (0x3ff<<0) |
| #define TFA98XX_BATTERYVOLTAGE_BATS_POS 0 |
| #define TFA98XX_BATTERYVOLTAGE_BATS_LEN 10 |
| #define TFA98XX_BATTERYVOLTAGE_BATS_MAX 1023 |
| #define TFA98XX_BATTERYVOLTAGE_BATS_MSK 0x3ff |
| |
| /** Temperature Register ($02) **********************************************/ |
| |
| #define TFA98XX_TEMPERATURE 0x02 |
| #define TFA98XX_TEMPERATURE_TEMPS (0x1ff<<0) |
| #define TFA98XX_TEMPERATURE_TEMPS_POS 0 |
| #define TFA98XX_TEMPERATURE_TEMPS_LEN 9 |
| #define TFA98XX_TEMPERATURE_TEMPS_MAX 511 |
| #define TFA98XX_TEMPERATURE_TEMPS_MSK 0x1ff |
| |
| /** RevisionNumber Register ($03) *******************************************/ |
| |
| #define TFA98XX_REVISIONNUMBER 0x03 |
| #define TFA98XX_REVISIONNUMBER_REV (0xff<<0) |
| #define TFA98XX_REVISIONNUMBER_REV_POS 0 |
| #define TFA98XX_REVISIONNUMBER_REV_LEN 8 |
| #define TFA98XX_REVISIONNUMBER_REV_MAX 255 |
| #define TFA98XX_REVISIONNUMBER_REV_MSK 0xff |
| |
| /** RevisionNumber Register ($03) *******************************************/ |
| |
| #define TFA9891_REVISIONNUMBER 0x03 |
| #define TFA9891_REVISIONNUMBER_REV (0xff<<0) |
| #define TFA9891_REVISIONNUMBER_REV_POS 0 |
| #define TFA9891_REVISIONNUMBER_REV_LEN 8 |
| #define TFA9891_REVISIONNUMBER_REV_MAX 255 |
| #define TFA9891_REVISIONNUMBER_REV_MSK 0xff |
| |
| /** AudioReg Register ($04) *************************************************/ |
| |
| #define TFA98XX_AUDIOREG 0x04 |
| #define TFA98XX_AUDIOREG_RCV (0x1<<2) |
| #define TFA98XX_AUDIOREG_RCV_POS 2 |
| #define TFA98XX_AUDIOREG_RCV_LEN 1 |
| #define TFA98XX_AUDIOREG_RCV_MAX 1 |
| #define TFA98XX_AUDIOREG_RCV_MSK 0x4 |
| |
| #define TFA98XX_AUDIOREG_CHS12 (0x3<<3) |
| #define TFA98XX_AUDIOREG_CHS12_POS 3 |
| #define TFA98XX_AUDIOREG_CHS12_LEN 2 |
| #define TFA98XX_AUDIOREG_CHS12_MAX 3 |
| #define TFA98XX_AUDIOREG_CHS12_MSK 0x18 |
| |
| #define TFA98XX_AUDIOREG_CHSA (0x3<<6) |
| #define TFA98XX_AUDIOREG_CHSA_POS 6 |
| #define TFA98XX_AUDIOREG_CHSA_LEN 2 |
| #define TFA98XX_AUDIOREG_CHSA_MAX 3 |
| #define TFA98XX_AUDIOREG_CHSA_MSK 0xc0 |
| |
| #define TFA98XX_AUDIOREG_AUDFS (0xf<<12) |
| #define TFA98XX_AUDIOREG_AUDFS_POS 12 |
| #define TFA98XX_AUDIOREG_AUDFS_LEN 4 |
| #define TFA98XX_AUDIOREG_AUDFS_MAX 15 |
| #define TFA98XX_AUDIOREG_AUDFS_MSK 0xf000 |
| |
| /** I2SReg Register ($04) ***************************************************/ |
| |
| #define TFA98XX_I2SREG 0x04 |
| #define TFA98XX_I2SREG_I2SF (0x7<<0) |
| #define TFA98XX_I2SREG_I2SF_POS 0 |
| #define TFA98XX_I2SREG_I2SF_LEN 3 |
| #define TFA98XX_I2SREG_I2SF_MAX 7 |
| #define TFA98XX_I2SREG_I2SF_MSK 0x7 |
| |
| #define TFA98XX_I2SREG_CHS12 (0x3<<3) |
| #define TFA98XX_I2SREG_CHS12_POS 3 |
| #define TFA98XX_I2SREG_CHS12_LEN 2 |
| #define TFA98XX_I2SREG_CHS12_MAX 3 |
| #define TFA98XX_I2SREG_CHS12_MSK 0x18 |
| |
| #define TFA98XX_I2SREG_CHS3 (0x1<<5) |
| #define TFA98XX_I2SREG_CHS3_POS 5 |
| #define TFA98XX_I2SREG_CHS3_LEN 1 |
| #define TFA98XX_I2SREG_CHS3_MAX 1 |
| #define TFA98XX_I2SREG_CHS3_MSK 0x20 |
| |
| #define TFA98XX_I2SREG_CHSA (0x3<<6) |
| #define TFA98XX_I2SREG_CHSA_POS 6 |
| #define TFA98XX_I2SREG_CHSA_LEN 2 |
| #define TFA98XX_I2SREG_CHSA_MAX 3 |
| #define TFA98XX_I2SREG_CHSA_MSK 0xc0 |
| |
| #define TFA98XX_I2SREG_I2SDOC (0x3<<8) |
| #define TFA98XX_I2SREG_I2SDOC_POS 8 |
| #define TFA98XX_I2SREG_I2SDOC_LEN 2 |
| #define TFA98XX_I2SREG_I2SDOC_MAX 3 |
| #define TFA98XX_I2SREG_I2SDOC_MSK 0x300 |
| |
| #define TFA98XX_I2SREG_DISP (0x1<<10) |
| #define TFA98XX_I2SREG_DISP_POS 10 |
| #define TFA98XX_I2SREG_DISP_LEN 1 |
| #define TFA98XX_I2SREG_DISP_MAX 1 |
| #define TFA98XX_I2SREG_DISP_MSK 0x400 |
| |
| #define TFA98XX_I2SREG_I2SDOE (0x1<<11) |
| #define TFA98XX_I2SREG_I2SDOE_POS 11 |
| #define TFA98XX_I2SREG_I2SDOE_LEN 1 |
| #define TFA98XX_I2SREG_I2SDOE_MAX 1 |
| #define TFA98XX_I2SREG_I2SDOE_MSK 0x800 |
| |
| #define TFA98XX_I2SREG_I2SSR (0xf<<12) |
| #define TFA98XX_I2SREG_I2SSR_POS 12 |
| #define TFA98XX_I2SREG_I2SSR_LEN 4 |
| #define TFA98XX_I2SREG_I2SSR_MAX 15 |
| #define TFA98XX_I2SREG_I2SSR_MSK 0xf000 |
| |
| /** bat_prot Register ($05) *************************************************/ |
| |
| #define TFA98XX_BAT_PROT 0x05 |
| #define TFA98XX_BAT_PROT_BSSCR (0x3<<0) |
| #define TFA98XX_BAT_PROT_BSSCR_POS 0 |
| #define TFA98XX_BAT_PROT_BSSCR_LEN 2 |
| #define TFA98XX_BAT_PROT_BSSCR_MAX 3 |
| #define TFA98XX_BAT_PROT_BSSCR_MSK 0x3 |
| |
| #define TFA98XX_BAT_PROT_BSST (0xf<<2) |
| #define TFA98XX_BAT_PROT_BSST_POS 2 |
| #define TFA98XX_BAT_PROT_BSST_LEN 4 |
| #define TFA98XX_BAT_PROT_BSST_MAX 15 |
| #define TFA98XX_BAT_PROT_BSST_MSK 0x3c |
| |
| #define TFA98XX_BAT_PROT_BSSRL (0x3<<6) |
| #define TFA98XX_BAT_PROT_BSSRL_POS 6 |
| #define TFA98XX_BAT_PROT_BSSRL_LEN 2 |
| #define TFA98XX_BAT_PROT_BSSRL_MAX 3 |
| #define TFA98XX_BAT_PROT_BSSRL_MSK 0xc0 |
| |
| #define TFA98XX_BAT_PROT_BSSRR (0x7<<8) |
| #define TFA98XX_BAT_PROT_BSSRR_POS 8 |
| #define TFA98XX_BAT_PROT_BSSRR_LEN 3 |
| #define TFA98XX_BAT_PROT_BSSRR_MAX 7 |
| #define TFA98XX_BAT_PROT_BSSRR_MSK 0x700 |
| |
| #define TFA98XX_BAT_PROT_BSSHY (0x3<<11) |
| #define TFA98XX_BAT_PROT_BSSHY_POS 11 |
| #define TFA98XX_BAT_PROT_BSSHY_LEN 2 |
| #define TFA98XX_BAT_PROT_BSSHY_MAX 3 |
| #define TFA98XX_BAT_PROT_BSSHY_MSK 0x1800 |
| |
| #define TFA98XX_BAT_PROT_BSSR (0x1<<14) |
| #define TFA98XX_BAT_PROT_BSSR_POS 14 |
| #define TFA98XX_BAT_PROT_BSSR_LEN 1 |
| #define TFA98XX_BAT_PROT_BSSR_MAX 1 |
| #define TFA98XX_BAT_PROT_BSSR_MSK 0x4000 |
| |
| #define TFA98XX_BAT_PROT_BSSBY (0x1<<15) |
| #define TFA98XX_BAT_PROT_BSSBY_POS 15 |
| #define TFA98XX_BAT_PROT_BSSBY_LEN 1 |
| #define TFA98XX_BAT_PROT_BSSBY_MAX 1 |
| #define TFA98XX_BAT_PROT_BSSBY_MSK 0x8000 |
| |
| /** bat_prot Register ($05) *************************************************/ |
| |
| #define TFA9887_BAT_PROT 0x05 |
| #define TFA9887_BAT_PROT_BSSBY (0x1<<0) |
| #define TFA9887_BAT_PROT_BSSBY_POS 0 |
| #define TFA9887_BAT_PROT_BSSBY_LEN 1 |
| #define TFA9887_BAT_PROT_BSSBY_MAX 1 |
| #define TFA9887_BAT_PROT_BSSBY_MSK 0x1 |
| |
| #define TFA9887_BAT_PROT_BSSCR (0x3<<1) |
| #define TFA9887_BAT_PROT_BSSCR_POS 1 |
| #define TFA9887_BAT_PROT_BSSCR_LEN 2 |
| #define TFA9887_BAT_PROT_BSSCR_MAX 3 |
| #define TFA9887_BAT_PROT_BSSCR_MSK 0x6 |
| |
| #define TFA9887_BAT_PROT_BSST (0x7<<3) |
| #define TFA9887_BAT_PROT_BSST_POS 3 |
| #define TFA9887_BAT_PROT_BSST_LEN 3 |
| #define TFA9887_BAT_PROT_BSST_MAX 7 |
| #define TFA9887_BAT_PROT_BSST_MSK 0x38 |
| |
| #define TFA9887_BAT_PROT_I2SDOC (0x1<<15) |
| #define TFA9887_BAT_PROT_I2SDOC_POS 15 |
| #define TFA9887_BAT_PROT_I2SDOC_LEN 1 |
| #define TFA9887_BAT_PROT_I2SDOC_MAX 1 |
| #define TFA9887_BAT_PROT_I2SDOC_MSK 0x8000 |
| |
| /** audio_ctr Register ($06) ************************************************/ |
| |
| #define TFA98XX_AUDIO_CTR 0x06 |
| #define TFA98XX_AUDIO_CTR_DPSA (0x1<<0) |
| #define TFA98XX_AUDIO_CTR_DPSA_POS 0 |
| #define TFA98XX_AUDIO_CTR_DPSA_LEN 1 |
| #define TFA98XX_AUDIO_CTR_DPSA_MAX 1 |
| #define TFA98XX_AUDIO_CTR_DPSA_MSK 0x1 |
| |
| #define TFA98XX_AUDIO_CTR_CFSM (0x1<<5) |
| #define TFA98XX_AUDIO_CTR_CFSM_POS 5 |
| #define TFA98XX_AUDIO_CTR_CFSM_LEN 1 |
| #define TFA98XX_AUDIO_CTR_CFSM_MAX 1 |
| #define TFA98XX_AUDIO_CTR_CFSM_MSK 0x20 |
| |
| #define TFA98XX_AUDIO_CTR_BSSS (0x1<<7) |
| #define TFA98XX_AUDIO_CTR_BSSS_POS 7 |
| #define TFA98XX_AUDIO_CTR_BSSS_LEN 1 |
| #define TFA98XX_AUDIO_CTR_BSSS_MAX 1 |
| #define TFA98XX_AUDIO_CTR_BSSS_MSK 0x80 |
| |
| #define TFA98XX_AUDIO_CTR_VOL (0xff<<8) |
| #define TFA98XX_AUDIO_CTR_VOL_POS 8 |
| #define TFA98XX_AUDIO_CTR_VOL_LEN 8 |
| #define TFA98XX_AUDIO_CTR_VOL_MAX 255 |
| #define TFA98XX_AUDIO_CTR_VOL_MSK 0xff00 |
| |
| /** DCDCboost Register ($07) ************************************************/ |
| |
| #define TFA98XX_DCDCBOOST 0x07 |
| #define TFA98XX_DCDCBOOST_DCVO (0x7<<0) |
| #define TFA98XX_DCDCBOOST_DCVO_POS 0 |
| #define TFA98XX_DCDCBOOST_DCVO_LEN 3 |
| #define TFA98XX_DCDCBOOST_DCVO_MAX 7 |
| #define TFA98XX_DCDCBOOST_DCVO_MSK 0x7 |
| |
| #define TFA98XX_DCDCBOOST_DCMCC (0xf<<3) |
| #define TFA98XX_DCDCBOOST_DCMCC_POS 3 |
| #define TFA98XX_DCDCBOOST_DCMCC_LEN 4 |
| #define TFA98XX_DCDCBOOST_DCMCC_MAX 15 |
| #define TFA98XX_DCDCBOOST_DCMCC_MSK 0x78 |
| |
| #define TFA98XX_DCDCBOOST_DCIE (0x1<<10) |
| #define TFA98XX_DCDCBOOST_DCIE_POS 10 |
| #define TFA98XX_DCDCBOOST_DCIE_LEN 1 |
| #define TFA98XX_DCDCBOOST_DCIE_MAX 1 |
| #define TFA98XX_DCDCBOOST_DCIE_MSK 0x400 |
| |
| #define TFA98XX_DCDCBOOST_DCSR (0x1<<11) |
| #define TFA98XX_DCDCBOOST_DCSR_POS 11 |
| #define TFA98XX_DCDCBOOST_DCSR_LEN 1 |
| #define TFA98XX_DCDCBOOST_DCSR_MAX 1 |
| #define TFA98XX_DCDCBOOST_DCSR_MSK 0x800 |
| |
| #define TFA98XX_DCDCBOOST_DCPAVG (0x1<<12) |
| #define TFA98XX_DCDCBOOST_DCPAVG_POS 12 |
| #define TFA98XX_DCDCBOOST_DCPAVG_LEN 1 |
| #define TFA98XX_DCDCBOOST_DCPAVG_MAX 1 |
| #define TFA98XX_DCDCBOOST_DCPAVG_MSK 0x1000 |
| |
| /** spkr_calibration Register ($08) *****************************************/ |
| |
| #define TFA98XX_SPKR_CALIBRATION 0x08 |
| #define TFA98XX_SPKR_CALIBRATION_TROS (0x1<<0) |
| #define TFA98XX_SPKR_CALIBRATION_TROS_POS 0 |
| #define TFA98XX_SPKR_CALIBRATION_TROS_LEN 1 |
| #define TFA98XX_SPKR_CALIBRATION_TROS_MAX 1 |
| #define TFA98XX_SPKR_CALIBRATION_TROS_MSK 0x1 |
| |
| #define TFA98XX_SPKR_CALIBRATION_EXTTS (0x1ff<<1) |
| #define TFA98XX_SPKR_CALIBRATION_EXTTS_POS 1 |
| #define TFA98XX_SPKR_CALIBRATION_EXTTS_LEN 9 |
| #define TFA98XX_SPKR_CALIBRATION_EXTTS_MAX 511 |
| #define TFA98XX_SPKR_CALIBRATION_EXTTS_MSK 0x3fe |
| |
| /** sys_ctrl Register ($09) *************************************************/ |
| |
| #define TFA98XX_SYS_CTRL 0x09 |
| #define TFA98XX_SYS_CTRL_PWDN (0x1<<0) |
| #define TFA98XX_SYS_CTRL_PWDN_POS 0 |
| #define TFA98XX_SYS_CTRL_PWDN_LEN 1 |
| #define TFA98XX_SYS_CTRL_PWDN_MAX 1 |
| #define TFA98XX_SYS_CTRL_PWDN_MSK 0x1 |
| |
| #define TFA98XX_SYS_CTRL_I2CR (0x1<<1) |
| #define TFA98XX_SYS_CTRL_I2CR_POS 1 |
| #define TFA98XX_SYS_CTRL_I2CR_LEN 1 |
| #define TFA98XX_SYS_CTRL_I2CR_MAX 1 |
| #define TFA98XX_SYS_CTRL_I2CR_MSK 0x2 |
| |
| #define TFA98XX_SYS_CTRL_CFE (0x1<<2) |
| #define TFA98XX_SYS_CTRL_CFE_POS 2 |
| #define TFA98XX_SYS_CTRL_CFE_LEN 1 |
| #define TFA98XX_SYS_CTRL_CFE_MAX 1 |
| #define TFA98XX_SYS_CTRL_CFE_MSK 0x4 |
| |
| #define TFA98XX_SYS_CTRL_AMPE (0x1<<3) |
| #define TFA98XX_SYS_CTRL_AMPE_POS 3 |
| #define TFA98XX_SYS_CTRL_AMPE_LEN 1 |
| #define TFA98XX_SYS_CTRL_AMPE_MAX 1 |
| #define TFA98XX_SYS_CTRL_AMPE_MSK 0x8 |
| |
| #define TFA98XX_SYS_CTRL_DCA (0x1<<4) |
| #define TFA98XX_SYS_CTRL_DCA_POS 4 |
| #define TFA98XX_SYS_CTRL_DCA_LEN 1 |
| #define TFA98XX_SYS_CTRL_DCA_MAX 1 |
| #define TFA98XX_SYS_CTRL_DCA_MSK 0x10 |
| |
| #define TFA98XX_SYS_CTRL_SBSL (0x1<<5) |
| #define TFA98XX_SYS_CTRL_SBSL_POS 5 |
| #define TFA98XX_SYS_CTRL_SBSL_LEN 1 |
| #define TFA98XX_SYS_CTRL_SBSL_MAX 1 |
| #define TFA98XX_SYS_CTRL_SBSL_MSK 0x20 |
| |
| #define TFA98XX_SYS_CTRL_AMPC (0x1<<6) |
| #define TFA98XX_SYS_CTRL_AMPC_POS 6 |
| #define TFA98XX_SYS_CTRL_AMPC_LEN 1 |
| #define TFA98XX_SYS_CTRL_AMPC_MAX 1 |
| #define TFA98XX_SYS_CTRL_AMPC_MSK 0x40 |
| |
| #define TFA98XX_SYS_CTRL_DCDIS (0x1<<7) |
| #define TFA98XX_SYS_CTRL_DCDIS_POS 7 |
| #define TFA98XX_SYS_CTRL_DCDIS_LEN 1 |
| #define TFA98XX_SYS_CTRL_DCDIS_MAX 1 |
| #define TFA98XX_SYS_CTRL_DCDIS_MSK 0x80 |
| |
| #define TFA98XX_SYS_CTRL_PSDR (0x1<<8) |
| #define TFA98XX_SYS_CTRL_PSDR_POS 8 |
| #define TFA98XX_SYS_CTRL_PSDR_LEN 1 |
| #define TFA98XX_SYS_CTRL_PSDR_MAX 1 |
| #define TFA98XX_SYS_CTRL_PSDR_MSK 0x100 |
| |
| #define TFA98XX_SYS_CTRL_DCCV (0x3<<9) |
| #define TFA98XX_SYS_CTRL_DCCV_POS 9 |
| #define TFA98XX_SYS_CTRL_DCCV_LEN 2 |
| #define TFA98XX_SYS_CTRL_DCCV_MAX 3 |
| #define TFA98XX_SYS_CTRL_DCCV_MSK 0x600 |
| |
| #define TFA98XX_SYS_CTRL_CCFD (0x1<<11) |
| #define TFA98XX_SYS_CTRL_CCFD_POS 11 |
| #define TFA98XX_SYS_CTRL_CCFD_LEN 1 |
| #define TFA98XX_SYS_CTRL_CCFD_MAX 1 |
| #define TFA98XX_SYS_CTRL_CCFD_MSK 0x800 |
| |
| #define TFA98XX_SYS_CTRL_INTPAD (0x3<<12) |
| #define TFA98XX_SYS_CTRL_INTPAD_POS 12 |
| #define TFA98XX_SYS_CTRL_INTPAD_LEN 2 |
| #define TFA98XX_SYS_CTRL_INTPAD_MAX 3 |
| #define TFA98XX_SYS_CTRL_INTPAD_MSK 0x3000 |
| |
| #define TFA98XX_SYS_CTRL_IPLL (0x1<<14) |
| #define TFA98XX_SYS_CTRL_IPLL_POS 14 |
| #define TFA98XX_SYS_CTRL_IPLL_LEN 1 |
| #define TFA98XX_SYS_CTRL_IPLL_MAX 1 |
| #define TFA98XX_SYS_CTRL_IPLL_MSK 0x4000 |
| |
| /** sys_ctrl Register ($09) *************************************************/ |
| |
| #define TFA98XX_SYS_CTRL 0x09 |
| #define TFA98XX_SYS_CTRL_ISEL (0x1<<13) |
| #define TFA98XX_SYS_CTRL_ISEL_POS 13 |
| #define TFA98XX_SYS_CTRL_ISEL_LEN 1 |
| #define TFA98XX_SYS_CTRL_ISEL_MAX 1 |
| #define TFA98XX_SYS_CTRL_ISEL_MSK 0x2000 |
| |
| /** I2S_sel_reg Register ($0a) **********************************************/ |
| |
| #define TFA98XX_I2S_SEL_REG 0x0a |
| #define TFA98XX_I2S_SEL_REG_DOLS (0x7<<0) |
| #define TFA98XX_I2S_SEL_REG_DOLS_POS 0 |
| #define TFA98XX_I2S_SEL_REG_DOLS_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_DOLS_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_DOLS_MSK 0x7 |
| |
| #define TFA98XX_I2S_SEL_REG_DORS (0x7<<3) |
| #define TFA98XX_I2S_SEL_REG_DORS_POS 3 |
| #define TFA98XX_I2S_SEL_REG_DORS_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_DORS_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_DORS_MSK 0x38 |
| |
| #define TFA98XX_I2S_SEL_REG_SPKL (0x7<<6) |
| #define TFA98XX_I2S_SEL_REG_SPKL_POS 6 |
| #define TFA98XX_I2S_SEL_REG_SPKL_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_SPKL_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_SPKL_MSK 0x1c0 |
| |
| #define TFA98XX_I2S_SEL_REG_SPKR (0x3<<9) |
| #define TFA98XX_I2S_SEL_REG_SPKR_POS 9 |
| #define TFA98XX_I2S_SEL_REG_SPKR_LEN 2 |
| #define TFA98XX_I2S_SEL_REG_SPKR_MAX 3 |
| #define TFA98XX_I2S_SEL_REG_SPKR_MSK 0x600 |
| |
| #define TFA98XX_I2S_SEL_REG_DCFG (0xf<<11) |
| #define TFA98XX_I2S_SEL_REG_DCFG_POS 11 |
| #define TFA98XX_I2S_SEL_REG_DCFG_LEN 4 |
| #define TFA98XX_I2S_SEL_REG_DCFG_MAX 15 |
| #define TFA98XX_I2S_SEL_REG_DCFG_MSK 0x7800 |
| |
| /** I2S_sel_reg Register ($0a) **********************************************/ |
| |
| #define TFA98XX_I2S_SEL_REG 0x0a |
| #define TFA98XX_I2S_SEL_REG_DOLS (0x7<<0) |
| #define TFA98XX_I2S_SEL_REG_DOLS_POS 0 |
| #define TFA98XX_I2S_SEL_REG_DOLS_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_DOLS_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_DOLS_MSK 0x7 |
| |
| #define TFA98XX_I2S_SEL_REG_DORS (0x7<<3) |
| #define TFA98XX_I2S_SEL_REG_DORS_POS 3 |
| #define TFA98XX_I2S_SEL_REG_DORS_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_DORS_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_DORS_MSK 0x38 |
| |
| #define TFA98XX_I2S_SEL_REG_SPKL (0x7<<6) |
| #define TFA98XX_I2S_SEL_REG_SPKL_POS 6 |
| #define TFA98XX_I2S_SEL_REG_SPKL_LEN 3 |
| #define TFA98XX_I2S_SEL_REG_SPKL_MAX 7 |
| #define TFA98XX_I2S_SEL_REG_SPKL_MSK 0x1c0 |
| |
| #define TFA98XX_I2S_SEL_REG_SPKR (0x3<<9) |
| #define TFA98XX_I2S_SEL_REG_SPKR_POS 9 |
| #define TFA98XX_I2S_SEL_REG_SPKR_LEN 2 |
| #define TFA98XX_I2S_SEL_REG_SPKR_MAX 3 |
| #define TFA98XX_I2S_SEL_REG_SPKR_MSK 0x600 |
| |
| #define TFA98XX_I2S_SEL_REG_DCFG (0xf<<11) |
| #define TFA98XX_I2S_SEL_REG_DCFG_POS 11 |
| #define TFA98XX_I2S_SEL_REG_DCFG_LEN 4 |
| #define TFA98XX_I2S_SEL_REG_DCFG_MAX 15 |
| #define TFA98XX_I2S_SEL_REG_DCFG_MSK 0x7800 |
| |
| /** mtpkey2_reg Register ($0b) **********************************************/ |
| |
| #define TFA98XX_MTPKEY2_REG 0x0b |
| #define TFA98XX_MTPKEY2_REG_MTPK (0xff<<0) |
| #define TFA98XX_MTPKEY2_REG_MTPK_POS 0 |
| #define TFA98XX_MTPKEY2_REG_MTPK_LEN 8 |
| #define TFA98XX_MTPKEY2_REG_MTPK_MAX 255 |
| #define TFA98XX_MTPKEY2_REG_MTPK_MSK 0xff |
| |
| /** voltage_sense_config Register ($0c) *************************************/ |
| |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG 0x0c |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY (0x3f<<2) |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_POS 2 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_LEN 6 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_MAX 63 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_MSK 0xfc |
| |
| /** voltage_sense_config Register ($0c) *************************************/ |
| |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG 0x0c |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY (0x3f<<2) |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_POS 2 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_LEN 6 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_MAX 63 |
| #define TFA98XX_VOLTAGE_SENSE_CONFIG_CVFDLY_MSK 0xfc |
| |
| /** interrupt_reg Register ($0f) ********************************************/ |
| |
| #define TFA98XX_INTERRUPT_REG 0x0f |
| #define TFA98XX_INTERRUPT_REG_VDDD (0x1<<0) |
| #define TFA98XX_INTERRUPT_REG_VDDD_POS 0 |
| #define TFA98XX_INTERRUPT_REG_VDDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_VDDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_VDDD_MSK 0x1 |
| |
| #define TFA98XX_INTERRUPT_REG_OTDD (0x1<<1) |
| #define TFA98XX_INTERRUPT_REG_OTDD_POS 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_MSK 0x2 |
| |
| #define TFA98XX_INTERRUPT_REG_OVDD (0x1<<2) |
| #define TFA98XX_INTERRUPT_REG_OVDD_POS 2 |
| #define TFA98XX_INTERRUPT_REG_OVDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OVDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OVDD_MSK 0x4 |
| |
| #define TFA98XX_INTERRUPT_REG_UVDD (0x1<<3) |
| #define TFA98XX_INTERRUPT_REG_UVDD_POS 3 |
| #define TFA98XX_INTERRUPT_REG_UVDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_UVDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_UVDD_MSK 0x8 |
| |
| #define TFA98XX_INTERRUPT_REG_OCDD (0x1<<4) |
| #define TFA98XX_INTERRUPT_REG_OCDD_POS 4 |
| #define TFA98XX_INTERRUPT_REG_OCDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OCDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OCDD_MSK 0x10 |
| |
| #define TFA98XX_INTERRUPT_REG_CLKD (0x1<<5) |
| #define TFA98XX_INTERRUPT_REG_CLKD_POS 5 |
| #define TFA98XX_INTERRUPT_REG_CLKD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_CLKD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_CLKD_MSK 0x20 |
| |
| #define TFA98XX_INTERRUPT_REG_DCCD (0x1<<6) |
| #define TFA98XX_INTERRUPT_REG_DCCD_POS 6 |
| #define TFA98XX_INTERRUPT_REG_DCCD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_DCCD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_DCCD_MSK 0x40 |
| |
| #define TFA98XX_INTERRUPT_REG_SPKD (0x1<<7) |
| #define TFA98XX_INTERRUPT_REG_SPKD_POS 7 |
| #define TFA98XX_INTERRUPT_REG_SPKD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_SPKD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_SPKD_MSK 0x80 |
| |
| #define TFA98XX_INTERRUPT_REG_WDD (0x1<<8) |
| #define TFA98XX_INTERRUPT_REG_WDD_POS 8 |
| #define TFA98XX_INTERRUPT_REG_WDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_WDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_WDD_MSK 0x100 |
| |
| #define TFA98XX_INTERRUPT_REG_INT (0x1<<14) |
| #define TFA98XX_INTERRUPT_REG_INT_POS 14 |
| #define TFA98XX_INTERRUPT_REG_INT_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_INT_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_INT_MSK 0x4000 |
| |
| #define TFA98XX_INTERRUPT_REG_INTP (0x1<<15) |
| #define TFA98XX_INTERRUPT_REG_INTP_POS 15 |
| #define TFA98XX_INTERRUPT_REG_INTP_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_INTP_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_INTP_MSK 0x8000 |
| |
| /** interrupt_reg Register ($0f) ********************************************/ |
| |
| #define TFA98XX_INTERRUPT_REG 0x0f |
| #define TFA98XX_INTERRUPT_REG_VDDD (0x1<<0) |
| #define TFA98XX_INTERRUPT_REG_VDDD_POS 0 |
| #define TFA98XX_INTERRUPT_REG_VDDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_VDDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_VDDD_MSK 0x1 |
| |
| #define TFA98XX_INTERRUPT_REG_OTDD (0x1<<1) |
| #define TFA98XX_INTERRUPT_REG_OTDD_POS 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OTDD_MSK 0x2 |
| |
| #define TFA98XX_INTERRUPT_REG_OVDD (0x1<<2) |
| #define TFA98XX_INTERRUPT_REG_OVDD_POS 2 |
| #define TFA98XX_INTERRUPT_REG_OVDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OVDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OVDD_MSK 0x4 |
| |
| #define TFA98XX_INTERRUPT_REG_UVDD (0x1<<3) |
| #define TFA98XX_INTERRUPT_REG_UVDD_POS 3 |
| #define TFA98XX_INTERRUPT_REG_UVDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_UVDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_UVDD_MSK 0x8 |
| |
| #define TFA98XX_INTERRUPT_REG_OCDD (0x1<<4) |
| #define TFA98XX_INTERRUPT_REG_OCDD_POS 4 |
| #define TFA98XX_INTERRUPT_REG_OCDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_OCDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_OCDD_MSK 0x10 |
| |
| #define TFA98XX_INTERRUPT_REG_CLKD (0x1<<5) |
| #define TFA98XX_INTERRUPT_REG_CLKD_POS 5 |
| #define TFA98XX_INTERRUPT_REG_CLKD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_CLKD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_CLKD_MSK 0x20 |
| |
| #define TFA98XX_INTERRUPT_REG_DCCD (0x1<<6) |
| #define TFA98XX_INTERRUPT_REG_DCCD_POS 6 |
| #define TFA98XX_INTERRUPT_REG_DCCD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_DCCD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_DCCD_MSK 0x40 |
| |
| #define TFA98XX_INTERRUPT_REG_SPKD (0x1<<7) |
| #define TFA98XX_INTERRUPT_REG_SPKD_POS 7 |
| #define TFA98XX_INTERRUPT_REG_SPKD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_SPKD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_SPKD_MSK 0x80 |
| |
| #define TFA98XX_INTERRUPT_REG_WDD (0x1<<8) |
| #define TFA98XX_INTERRUPT_REG_WDD_POS 8 |
| #define TFA98XX_INTERRUPT_REG_WDD_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_WDD_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_WDD_MSK 0x100 |
| |
| #define TFA98XX_INTERRUPT_REG_LCLK (0x1<<9) |
| #define TFA98XX_INTERRUPT_REG_LCLK_POS 9 |
| #define TFA98XX_INTERRUPT_REG_LCLK_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_LCLK_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_LCLK_MSK 0x200 |
| |
| #define TFA98XX_INTERRUPT_REG_INT (0x1<<14) |
| #define TFA98XX_INTERRUPT_REG_INT_POS 14 |
| #define TFA98XX_INTERRUPT_REG_INT_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_INT_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_INT_MSK 0x4000 |
| |
| #define TFA98XX_INTERRUPT_REG_INTP (0x1<<15) |
| #define TFA98XX_INTERRUPT_REG_INTP_POS 15 |
| #define TFA98XX_INTERRUPT_REG_INTP_LEN 1 |
| #define TFA98XX_INTERRUPT_REG_INTP_MAX 1 |
| #define TFA98XX_INTERRUPT_REG_INTP_MSK 0x8000 |
| |
| /** tdm_config_reg0 Register ($10) ******************************************/ |
| |
| #define TFA98XX_TDM_CONFIG_REG0 0x10 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMMODE (0x1<<0) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMMODE_POS 0 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMMODE_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMMODE_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMMODE_MSK 0x1 |
| |
| #define TFA98XX_TDM_CONFIG_REG0_TDMPRF (0x3<<1) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMPRF_POS 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMPRF_LEN 2 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMPRF_MAX 3 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMPRF_MSK 0x6 |
| |
| #define TFA98XX_TDM_CONFIG_REG0_TDMEN (0x1<<3) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMEN_POS 3 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMEN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMEN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMEN_MSK 0x8 |
| |
| #define TFA98XX_TDM_CONFIG_REG0_TDMCKINV (0x1<<4) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMCKINV_POS 4 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMCKINV_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMCKINV_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMCKINV_MSK 0x10 |
| |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSLN (0xf<<5) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSLN_POS 5 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSLN_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSLN_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSLN_MSK 0x1e0 |
| |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSPOL (0x1<<9) |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSPOL_POS 9 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSPOL_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSPOL_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG0_TDMFSPOL_MSK 0x200 |
| |
| /** tdm_config_reg1 Register ($11) ******************************************/ |
| |
| #define TFA98XX_TDM_CONFIG_REG1 0x11 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLOTS (0xf<<0) |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLOTS_POS 0 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLOTS_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLOTS_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLOTS_MSK 0xf |
| |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLLN (0x1f<<4) |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLLN_POS 4 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLLN_LEN 5 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLLN_MAX 31 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMSLLN_MSK 0x1f0 |
| |
| #define TFA98XX_TDM_CONFIG_REG1_TDMBRMG (0x1f<<9) |
| #define TFA98XX_TDM_CONFIG_REG1_TDMBRMG_POS 9 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMBRMG_LEN 5 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMBRMG_MAX 31 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMBRMG_MSK 0x3e00 |
| |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDDEL (0x1<<14) |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDDEL_POS 14 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDDEL_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDDEL_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDDEL_MSK 0x4000 |
| |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDADJ (0x1<<15) |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDADJ_POS 15 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDADJ_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDADJ_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG1_TDMDADJ_MSK 0x8000 |
| |
| /** tdm_config_reg2 Register ($12) ******************************************/ |
| |
| #define TFA98XX_TDM_CONFIG_REG2 0x12 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMCOMP (0x3<<0) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMCOMP_POS 0 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMCOMP_LEN 2 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMCOMP_MAX 3 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMCOMP_MSK 0x3 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMTXFRM (0x3<<2) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMTXFRM_POS 2 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMTXFRM_LEN 2 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMTXFRM_MAX 3 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMTXFRM_MSK 0xc |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0EN (0x1<<7) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0EN_POS 7 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0EN_MSK 0x80 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1EN (0x1<<8) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1EN_POS 8 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1EN_MSK 0x100 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2EN (0x1<<9) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2EN_POS 9 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2EN_MSK 0x200 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO0EN (0x1<<10) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO0EN_POS 10 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO0EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO0EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO0EN_MSK 0x400 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO1EN (0x1<<11) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO1EN_POS 11 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO1EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO1EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO1EN_MSK 0x800 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO2EN (0x1<<12) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO2EN_POS 12 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO2EN_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO2EN_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSO2EN_MSK 0x1000 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0IO (0x1<<13) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0IO_POS 13 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI0IO_MSK 0x2000 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1IO (0x1<<14) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1IO_POS 14 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI1IO_MSK 0x4000 |
| |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2IO (0x1<<15) |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2IO_POS 15 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG2_TDMSI2IO_MSK 0x8000 |
| |
| /** tdm_config_reg3 Register ($13) ******************************************/ |
| |
| #define TFA98XX_TDM_CONFIG_REG3 0x13 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO0IO (0x1<<0) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO0IO_POS 0 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO0IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO0IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO0IO_MSK 0x1 |
| |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO1IO (0x1<<1) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO1IO_POS 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO1IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO1IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO1IO_MSK 0x2 |
| |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO2IO (0x1<<2) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO2IO_POS 2 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO2IO_LEN 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO2IO_MAX 1 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSO2IO_MSK 0x4 |
| |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI0SL (0xf<<3) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI0SL_POS 3 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI0SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI0SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI0SL_MSK 0x78 |
| |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI1SL (0xf<<7) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI1SL_POS 7 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI1SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI1SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI1SL_MSK 0x780 |
| |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI2SL (0xf<<11) |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI2SL_POS 11 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI2SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI2SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG3_TDMSI2SL_MSK 0x7800 |
| |
| /** tdm_config_reg4 Register ($14) ******************************************/ |
| |
| #define TFA98XX_TDM_CONFIG_REG4 0x14 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO0SL (0xf<<0) |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO0SL_POS 0 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO0SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO0SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO0SL_MSK 0xf |
| |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO1SL (0xf<<4) |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO1SL_POS 4 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO1SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO1SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO1SL_MSK 0xf0 |
| |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO2SL (0xf<<8) |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO2SL_POS 8 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO2SL_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO2SL_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG4_TDMSO2SL_MSK 0xf00 |
| |
| #define TFA98XX_TDM_CONFIG_REG4_NBCK (0xf<<12) |
| #define TFA98XX_TDM_CONFIG_REG4_NBCK_POS 12 |
| #define TFA98XX_TDM_CONFIG_REG4_NBCK_LEN 4 |
| #define TFA98XX_TDM_CONFIG_REG4_NBCK_MAX 15 |
| #define TFA98XX_TDM_CONFIG_REG4_NBCK_MSK 0xf000 |
| |
| /** interrupt_out_reg1 Register ($20) ***************************************/ |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1 0x20 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOVDDS (0x1<<0) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOVDDS_POS 0 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOVDDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOVDDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOVDDS_MSK 0x1 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOPLLS (0x1<<1) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOPLLS_POS 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOPLLS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOPLLS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOPLLS_MSK 0x2 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOTDS (0x1<<2) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOTDS_POS 2 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOTDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOTDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOTDS_MSK 0x4 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOVDS (0x1<<3) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOVDS_POS 3 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOVDS_MSK 0x8 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOUVDS (0x1<<4) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOUVDS_POS 4 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOUVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOUVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOUVDS_MSK 0x10 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOCDS (0x1<<5) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOCDS_POS 5 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOCDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOCDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOOCDS_MSK 0x20 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLKS (0x1<<6) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLKS_POS 6 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLKS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLKS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLKS_MSK 0x40 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLIPS (0x1<<7) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLIPS_POS 7 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLIPS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLIPS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOCLIPS_MSK 0x80 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOMTPB (0x1<<8) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOMTPB_POS 8 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOMTPB_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOMTPB_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOMTPB_MSK 0x100 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTONOCLK (0x1<<9) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTONOCLK_POS 9 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTONOCLK_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTONOCLK_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTONOCLK_MSK 0x200 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSPKS (0x1<<10) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSPKS_POS 10 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSPKS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSPKS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSPKS_MSK 0x400 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOACS (0x1<<11) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOACS_POS 11 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOACS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOACS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOACS_MSK 0x800 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSWS (0x1<<12) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSWS_POS 12 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSWS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSWS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOSWS_MSK 0x1000 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOWDS (0x1<<13) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOWDS_POS 13 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOWDS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOWDS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOWDS_MSK 0x2000 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAMPS (0x1<<14) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAMPS_POS 14 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAMPS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAMPS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAMPS_MSK 0x4000 |
| |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAREFS (0x1<<15) |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAREFS_POS 15 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAREFS_LEN 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAREFS_MAX 1 |
| #define TFA98XX_INTERRUPT_OUT_REG1_INTOAREFS_MSK 0x8000 |
| |
| /** interrupt_out_reg3 Register ($22) ***************************************/ |
| |
| #define TFA98XX_INTERRUPT_OUT_REG3 0x22 |
| #define TFA98XX_INTERRUPT_OUT_REG3_INTOACK (0x3<<0) |
| #define TFA98XX_INTERRUPT_OUT_REG3_INTOACK_POS 0 |
| #define TFA98XX_INTERRUPT_OUT_REG3_INTOACK_LEN 2 |
| #define TFA98XX_INTERRUPT_OUT_REG3_INTOACK_MAX 3 |
| #define TFA98XX_INTERRUPT_OUT_REG3_INTOACK_MSK 0x3 |
| |
| /** interrupt_in_reg1 Register ($23) ****************************************/ |
| |
| #define TFA98XX_INTERRUPT_IN_REG1 0x23 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIVDDS (0x1<<0) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIVDDS_POS 0 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIVDDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIVDDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIVDDS_MSK 0x1 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIPLLS (0x1<<1) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIPLLS_POS 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIPLLS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIPLLS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIPLLS_MSK 0x2 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOTDS (0x1<<2) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOTDS_POS 2 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOTDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOTDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOTDS_MSK 0x4 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOVDS (0x1<<3) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOVDS_POS 3 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOVDS_MSK 0x8 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIUVDS (0x1<<4) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIUVDS_POS 4 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIUVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIUVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIUVDS_MSK 0x10 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOCDS (0x1<<5) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOCDS_POS 5 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOCDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOCDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIOCDS_MSK 0x20 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLKS (0x1<<6) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLKS_POS 6 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLKS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLKS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLKS_MSK 0x40 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLIPS (0x1<<7) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLIPS_POS 7 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLIPS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLIPS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTICLIPS_MSK 0x80 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIMTPB (0x1<<8) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIMTPB_POS 8 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIMTPB_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIMTPB_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIMTPB_MSK 0x100 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTINOCLK (0x1<<9) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTINOCLK_POS 9 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTINOCLK_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTINOCLK_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTINOCLK_MSK 0x200 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISPKS (0x1<<10) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISPKS_POS 10 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISPKS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISPKS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISPKS_MSK 0x400 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIACS (0x1<<11) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIACS_POS 11 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIACS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIACS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIACS_MSK 0x800 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISWS (0x1<<12) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISWS_POS 12 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISWS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISWS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTISWS_MSK 0x1000 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIWDS (0x1<<13) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIWDS_POS 13 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIWDS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIWDS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIWDS_MSK 0x2000 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAMPS (0x1<<14) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAMPS_POS 14 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAMPS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAMPS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAMPS_MSK 0x4000 |
| |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAREFS (0x1<<15) |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAREFS_POS 15 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAREFS_LEN 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAREFS_MAX 1 |
| #define TFA98XX_INTERRUPT_IN_REG1_INTIAREFS_MSK 0x8000 |
| |
| /** interrupt_in_reg3 Register ($25) ****************************************/ |
| |
| #define TFA98XX_INTERRUPT_IN_REG3 0x25 |
| #define TFA98XX_INTERRUPT_IN_REG3_INTIACK (0x3<<0) |
| #define TFA98XX_INTERRUPT_IN_REG3_INTIACK_POS 0 |
| #define TFA98XX_INTERRUPT_IN_REG3_INTIACK_LEN 2 |
| #define TFA98XX_INTERRUPT_IN_REG3_INTIACK_MAX 3 |
| #define TFA98XX_INTERRUPT_IN_REG3_INTIACK_MSK 0x3 |
| |
| /** interrupt_enable_reg1 Register ($26) ************************************/ |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1 0x26 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENVDDS (0x1<<0) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENVDDS_POS 0 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENVDDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENVDDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENVDDS_MSK 0x1 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENPLLS (0x1<<1) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENPLLS_POS 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENPLLS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENPLLS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENPLLS_MSK 0x2 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOTDS (0x1<<2) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOTDS_POS 2 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOTDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOTDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOTDS_MSK 0x4 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOVDS (0x1<<3) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOVDS_POS 3 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOVDS_MSK 0x8 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENUVDS (0x1<<4) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENUVDS_POS 4 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENUVDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENUVDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENUVDS_MSK 0x10 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOCDS (0x1<<5) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOCDS_POS 5 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOCDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOCDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENOCDS_MSK 0x20 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLKS (0x1<<6) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLKS_POS 6 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLKS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLKS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLKS_MSK 0x40 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLIPS (0x1<<7) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLIPS_POS 7 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLIPS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLIPS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENCLIPS_MSK 0x80 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENMTPB (0x1<<8) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENMTPB_POS 8 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENMTPB_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENMTPB_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENMTPB_MSK 0x100 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENNOCLK (0x1<<9) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENNOCLK_POS 9 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENNOCLK_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENNOCLK_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENNOCLK_MSK 0x200 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSPKS (0x1<<10) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSPKS_POS 10 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSPKS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSPKS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSPKS_MSK 0x400 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENACS (0x1<<11) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENACS_POS 11 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENACS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENACS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENACS_MSK 0x800 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSWS (0x1<<12) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSWS_POS 12 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSWS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSWS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENSWS_MSK 0x1000 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENWDS (0x1<<13) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENWDS_POS 13 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENWDS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENWDS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENWDS_MSK 0x2000 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAMPS (0x1<<14) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAMPS_POS 14 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAMPS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAMPS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAMPS_MSK 0x4000 |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAREFS (0x1<<15) |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAREFS_POS 15 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAREFS_LEN 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAREFS_MAX 1 |
| #define TFA98XX_INTERRUPT_ENABLE_REG1_INTENAREFS_MSK 0x8000 |
| |
| /** interrupt_enable_reg3 Register ($28) ************************************/ |
| |
| #define TFA98XX_INTERRUPT_ENABLE_REG3 0x28 |
| #define TFA98XX_INTERRUPT_ENABLE_REG3_INTENACK (0x3<<0) |
| #define TFA98XX_INTERRUPT_ENABLE_REG3_INTENACK_POS 0 |
| #define TFA98XX_INTERRUPT_ENABLE_REG3_INTENACK_LEN 2 |
| #define TFA98XX_INTERRUPT_ENABLE_REG3_INTENACK_MAX 3 |
| #define TFA98XX_INTERRUPT_ENABLE_REG3_INTENACK_MSK 0x3 |
| |
| /** status_polarity_reg1 Register ($29) *************************************/ |
| |
| #define TFA98XX_STATUS_POLARITY_REG1 0x29 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLVDDS (0x1<<0) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLVDDS_POS 0 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLVDDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLVDDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLVDDS_MSK 0x1 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLPLLS (0x1<<1) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLPLLS_POS 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLPLLS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLPLLS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLPLLS_MSK 0x2 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOTDS (0x1<<2) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOTDS_POS 2 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOTDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOTDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOTDS_MSK 0x4 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOVDS (0x1<<3) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOVDS_POS 3 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOVDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOVDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOVDS_MSK 0x8 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLUVDS (0x1<<4) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLUVDS_POS 4 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLUVDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLUVDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLUVDS_MSK 0x10 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOCDS (0x1<<5) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOCDS_POS 5 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOCDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOCDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLOCDS_MSK 0x20 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLKS (0x1<<6) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLKS_POS 6 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLKS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLKS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLKS_MSK 0x40 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLIPS (0x1<<7) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLIPS_POS 7 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLIPS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLIPS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLCLIPS_MSK 0x80 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLMTPB (0x1<<8) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLMTPB_POS 8 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLMTPB_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLMTPB_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLMTPB_MSK 0x100 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLNOCLK (0x1<<9) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLNOCLK_POS 9 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLNOCLK_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLNOCLK_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLNOCLK_MSK 0x200 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSPKS (0x1<<10) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSPKS_POS 10 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSPKS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSPKS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSPKS_MSK 0x400 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLACS (0x1<<11) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLACS_POS 11 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLACS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLACS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLACS_MSK 0x800 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSWS (0x1<<12) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSWS_POS 12 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSWS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSWS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLSWS_MSK 0x1000 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLWDS (0x1<<13) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLWDS_POS 13 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLWDS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLWDS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLWDS_MSK 0x2000 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAMPS (0x1<<14) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAMPS_POS 14 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAMPS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAMPS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAMPS_MSK 0x4000 |
| |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAREFS (0x1<<15) |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAREFS_POS 15 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAREFS_LEN 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAREFS_MAX 1 |
| #define TFA98XX_STATUS_POLARITY_REG1_INTPOLAREFS_MSK 0x8000 |
| |
| /** status_polarity_reg3 Register ($2b) *************************************/ |
| |
| #define TFA98XX_STATUS_POLARITY_REG3 0x2b |
| #define TFA98XX_STATUS_POLARITY_REG3_INTPOLACK (0x3<<0) |
| #define TFA98XX_STATUS_POLARITY_REG3_INTPOLACK_POS 0 |
| #define TFA98XX_STATUS_POLARITY_REG3_INTPOLACK_LEN 2 |
| #define TFA98XX_STATUS_POLARITY_REG3_INTPOLACK_MAX 3 |
| #define TFA98XX_STATUS_POLARITY_REG3_INTPOLACK_MSK 0x3 |
| |
| /** pwm_mute_set Register ($41) *********************************************/ |
| |
| #define TFA98XX_PWM_MUTE_SET 0x41 |
| #define TFA98XX_PWM_MUTE_SET_PWMDEL (0x1f<<3) |
| #define TFA98XX_PWM_MUTE_SET_PWMDEL_POS 3 |
| #define TFA98XX_PWM_MUTE_SET_PWMDEL_LEN 5 |
| #define TFA98XX_PWM_MUTE_SET_PWMDEL_MAX 31 |
| #define TFA98XX_PWM_MUTE_SET_PWMDEL_MSK 0xf8 |
| |
| #define TFA98XX_PWM_MUTE_SET_PWMSH (0x1<<8) |
| #define TFA98XX_PWM_MUTE_SET_PWMSH_POS 8 |
| #define TFA98XX_PWM_MUTE_SET_PWMSH_LEN 1 |
| #define TFA98XX_PWM_MUTE_SET_PWMSH_MAX 1 |
| #define TFA98XX_PWM_MUTE_SET_PWMSH_MSK 0x100 |
| |
| #define TFA98XX_PWM_MUTE_SET_PWMRE (0x1<<9) |
| #define TFA98XX_PWM_MUTE_SET_PWMRE_POS 9 |
| #define TFA98XX_PWM_MUTE_SET_PWMRE_LEN 1 |
| #define TFA98XX_PWM_MUTE_SET_PWMRE_MAX 1 |
| #define TFA98XX_PWM_MUTE_SET_PWMRE_MSK 0x200 |
| |
| /** currentsense3 Register ($48) ********************************************/ |
| |
| #define TFA98XX_CURRENTSENSE3 0x48 |
| #define TFA98XX_CURRENTSENSE3_TCC (0x3<<14) |
| #define TFA98XX_CURRENTSENSE3_TCC_POS 14 |
| #define TFA98XX_CURRENTSENSE3_TCC_LEN 2 |
| #define TFA98XX_CURRENTSENSE3_TCC_MAX 3 |
| #define TFA98XX_CURRENTSENSE3_TCC_MSK 0xc000 |
| |
| /** CurrentSense4 Register ($49) ********************************************/ |
| |
| #define TFA98XX_CURRENTSENSE4 0x49 |
| #define TFA98XX_CURRENTSENSE4_CLIP (0x1<<0) |
| #define TFA98XX_CURRENTSENSE4_CLIP_POS 0 |
| #define TFA98XX_CURRENTSENSE4_CLIP_LEN 1 |
| #define TFA98XX_CURRENTSENSE4_CLIP_MAX 1 |
| #define TFA98XX_CURRENTSENSE4_CLIP_MSK 0x1 |
| |
| #define TFA98XX_CURRENTSENSE4_CTRL_CLKGATECFOFF (0x1<<2) |
| |
| /** KEY1_Protected_mtp_ctrl_reg3 Register ($62) *****************************/ |
| |
| #define TFA98XX_KEY1_PROTECTED_MTP_CTRL_REG3 0x62 |
| /** cf_controls Register ($70) **********************************************/ |
| |
| #define TFA98XX_CF_CONTROLS 0x70 |
| #define TFA98XX_CF_CONTROLS_RST (0x1<<0) |
| #define TFA98XX_CF_CONTROLS_RST_POS 0 |
| #define TFA98XX_CF_CONTROLS_RST_LEN 1 |
| #define TFA98XX_CF_CONTROLS_RST_MAX 1 |
| #define TFA98XX_CF_CONTROLS_RST_MSK 0x1 |
| |
| #define TFA98XX_CF_CONTROLS_DMEM (0x3<<1) |
| #define TFA98XX_CF_CONTROLS_DMEM_POS 1 |
| #define TFA98XX_CF_CONTROLS_DMEM_LEN 2 |
| #define TFA98XX_CF_CONTROLS_DMEM_MAX 3 |
| #define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6 |
| |
| #define TFA98XX_CF_CONTROLS_AIF (0x1<<3) |
| #define TFA98XX_CF_CONTROLS_AIF_POS 3 |
| #define TFA98XX_CF_CONTROLS_AIF_LEN 1 |
| #define TFA98XX_CF_CONTROLS_AIF_MAX 1 |
| #define TFA98XX_CF_CONTROLS_AIF_MSK 0x8 |
| |
| #define TFA98XX_CF_CONTROLS_CFINT (0x1<<4) |
| #define TFA98XX_CF_CONTROLS_CFINT_POS 4 |
| #define TFA98XX_CF_CONTROLS_CFINT_LEN 1 |
| #define TFA98XX_CF_CONTROLS_CFINT_MAX 1 |
| #define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10 |
| |
| #define TFA98XX_CF_CONTROLS_REQ (0xff<<8) |
| #define TFA98XX_CF_CONTROLS_REQ_POS 8 |
| #define TFA98XX_CF_CONTROLS_REQ_LEN 8 |
| #define TFA98XX_CF_CONTROLS_REQ_MAX 255 |
| #define TFA98XX_CF_CONTROLS_REQ_MSK 0xff00 |
| |
| /** cf_mad Register ($71) ***************************************************/ |
| |
| #define TFA98XX_CF_MAD 0x71 |
| #define TFA98XX_CF_MAD_MADD (0xffff<<0) |
| #define TFA98XX_CF_MAD_MADD_POS 0 |
| #define TFA98XX_CF_MAD_MADD_LEN 16 |
| #define TFA98XX_CF_MAD_MADD_MAX 65535 |
| #define TFA98XX_CF_MAD_MADD_MSK 0xffff |
| |
| /** cf_mem Register ($72) ***************************************************/ |
| |
| #define TFA98XX_CF_MEM 0x72 |
| #define TFA98XX_CF_MEM_MEMA (0xffff<<0) |
| #define TFA98XX_CF_MEM_MEMA_POS 0 |
| #define TFA98XX_CF_MEM_MEMA_LEN 16 |
| #define TFA98XX_CF_MEM_MEMA_MAX 65535 |
| #define TFA98XX_CF_MEM_MEMA_MSK 0xffff |
| |
| /** cf_status Register ($73) ************************************************/ |
| |
| #define TFA98XX_CF_STATUS 0x73 |
| #define TFA98XX_CF_STATUS_ERR (0xff<<0) |
| #define TFA98XX_CF_STATUS_ERR_POS 0 |
| #define TFA98XX_CF_STATUS_ERR_LEN 8 |
| #define TFA98XX_CF_STATUS_ERR_MAX 255 |
| #define TFA98XX_CF_STATUS_ERR_MSK 0xff |
| |
| #define TFA98XX_CF_STATUS_ACK (0xff<<8) |
| #define TFA98XX_CF_STATUS_ACK_POS 8 |
| #define TFA98XX_CF_STATUS_ACK_LEN 8 |
| #define TFA98XX_CF_STATUS_ACK_MAX 255 |
| #define TFA98XX_CF_STATUS_ACK_MSK 0xff00 |
| |
| /** Key2_Protected_spkr_cal_mtp Register ($80) ******************************/ |
| |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP 0x80 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC (0x1<<0) |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC_POS 0 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC_LEN 1 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC_MAX 1 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC_MSK 0x1 |
| |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX (0x1<<1) |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX_POS 1 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX_LEN 1 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX_MAX 1 |
| #define TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX_MSK 0x2 |
| |
| /** MTPF Register ($8f) *****************************************************/ |
| |
| #define TFA98XX_MTPF 0x8f |
| #define TFA98XX_MTPF_VERSION (0xffff<<0) |
| #define TFA98XX_MTPF_VERSION_POS 0 |
| #define TFA98XX_MTPF_VERSION_LEN 16 |
| #define TFA98XX_MTPF_VERSION_MAX 65535 |
| #define TFA98XX_MTPF_VERSION_MSK 0xffff |
| |
| #define TFA98XX_MAX_REGISTER 0x8f |
| |
| |
| /* some shorthands for readability */ |
| #define TFA98XX_MTP TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP |
| #define TFA98XX_MTP_COPY TFA98XX_MTP_CTRL_REG3 |
| /* MTP bits */ |
| /* one time calibration */ |
| #define TFA98XX_MTP_MTPOTC TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPOTC |
| /* one time calibration done */ |
| #define TFA98XX_MTP_MTPEX TFA98XX_KEY2_PROTECTED_SPKR_CAL_MTP_MTPEX |
| /* sample rates */ |
| /* I2S_CONTROL bits */ |
| #define TFA98XX_I2SCTRL_RATE_08000 (0<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_11025 (1<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_12000 (2<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_16000 (3<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_22050 (4<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_24000 (5<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_32000 (6<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_44100 (7<<TFA98XX_I2SREG_I2SSR_POS) |
| #define TFA98XX_I2SCTRL_RATE_48000 (8<<TFA98XX_I2SREG_I2SSR_POS) |
| |
| |
| struct TfaBfName { |
| u16 bfEnum; |
| char *bfName; |
| }; |
| |
| |
| #define TFA_NAMETABLE static struct TfaBfName TfaBfNames[]= {\ |
| { 0x0, "VDDS"}, /* Power-on-reset flag , */\ |
| { 0x10, "PLLS"}, /* PLL lock , */\ |
| { 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\ |
| { 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\ |
| { 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\ |
| { 0x50, "OCDS"}, /* Over Current Protection alarm , */\ |
| { 0x60, "CLKS"}, /* Clocks stable flag , */\ |
| { 0x70, "CLIPS"}, /* Amplifier clipping , */\ |
| { 0x80, "MTPB"}, /* MTP busy , */\ |
| { 0x90, "NOCLK"}, /* Flag lost clock from clock generation unit , */\ |
| { 0xa0, "SPKS"}, /* Speaker error flag , */\ |
| { 0xb0, "ACS"}, /* Cold Start flag , */\ |
| { 0xc0, "SWS"}, /* Flag Engage , */\ |
| { 0xd0, "WDS"}, /* Flag watchdog reset , */\ |
| { 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\ |
| { 0xf0, "AREFS"}, /* References are enabled by manager , */\ |
| { 0x109, "BATS"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\ |
| { 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor , */\ |
| { 0x307, "REV"}, /* Device type number is 97 , */\ |
| { 0x307, "REV91 "}, /* , */\ |
| { 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\ |
| { 0x461, "CHSA"}, /* Input selection for amplifier , */\ |
| { 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\ |
| { 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\ |
| { 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\ |
| { 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\ |
| { 0x461, "CHSA"}, /* Input selection for amplifier , */\ |
| { 0x481, "I2SDOC"}, /* selection data out , */\ |
| { 0x4a0, "DISP"}, /* idp protection , */\ |
| { 0x4b0, "I2SDOE"}, /* Enable data output , */\ |
| { 0x4c3, "I2SSR"}, /* sample rate setting , */\ |
| { 0x501, "BSSCR"}, /* Protection Attack Time , */\ |
| { 0x523, "BSST"}, /* ProtectionThreshold , */\ |
| { 0x561, "BSSRL"}, /* Protection Maximum Reduction , */\ |
| { 0x582, "BSSRR"}, /* Battery Protection Release Time , */\ |
| { 0x5b1, "BSSHY"}, /* Battery Protection Hysteresis , */\ |
| { 0x5e0, "BSSR"}, /* battery voltage for I2C read out only , */\ |
| { 0x5f0, "BSSBY"}, /* bypass clipper battery protection , */\ |
| { 0x500, "BSSBY87 "}, /* , */\ |
| { 0x511, "BSSCR87 "}, /* 00 = 0.56 dB/Sample , */\ |
| { 0x532, "BSST87 "}, /* 000 = 2.92V , */\ |
| { 0x5f0, "I2SDOC87 "}, /* selection data out , */\ |
| { 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\ |
| { 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\ |
| { 0x670, "BSSS"}, /* BatSenseSteepness , */\ |
| { 0x687, "VOL"}, /* volume control (in CoolFlux) , */\ |
| { 0x702, "DCVO"}, /* Boost Voltage , */\ |
| { 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\ |
| { 0x7a0, "DCIE"}, /* Adaptive boost mode , */\ |
| { 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\ |
| { 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\ |
| { 0x800, "TROS"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\ |
| { 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\ |
| { 0x900, "PWDN"}, /* Device Mode , */\ |
| { 0x910, "I2CR"}, /* I2C Reset , */\ |
| { 0x920, "CFE"}, /* Enable CoolFlux , */\ |
| { 0x930, "AMPE"}, /* Enable Amplifier , */\ |
| { 0x940, "DCA"}, /* EnableBoost , */\ |
| { 0x950, "SBSL"}, /* Coolflux configured , */\ |
| { 0x960, "AMPC"}, /* Selection on how Amplifier is enabled , */\ |
| { 0x970, "DCDIS"}, /* DCDC not connected , */\ |
| { 0x980, "PSDR"}, /* IDDQ test amplifier , */\ |
| { 0x991, "DCCV"}, /* Coil Value , */\ |
| { 0x9b0, "CCFD"}, /* Selection CoolFlux Clock , */\ |
| { 0x9c1, "INTPAD"}, /* INT pad configuration control , */\ |
| { 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\ |
| { 0x9d0, "ISEL90 "}, /* selection input 1 or 2 , */\ |
| { 0xa02, "DOLS"}, /* Output selection dataout left channel , */\ |
| { 0xa32, "DORS"}, /* Output selection dataout right channel , */\ |
| { 0xa62, "SPKL"}, /* Selection speaker induction , */\ |
| { 0xa91, "SPKR"}, /* Selection speaker impedance , */\ |
| { 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\ |
| { 0xa02, "DOLS90 "}, /* Output selection dataout left channel , */\ |
| { 0xa32, "DORS90 "}, /* Output selection dataout right channel , */\ |
| { 0xa62, "SPKL90 "}, /* Selection speaker induction , */\ |
| { 0xa91, "SPKR90 "}, /* Selection speaker impedance , */\ |
| { 0xab3, "DCFG90 "}, /* DCDC speaker current compensation gain , */\ |
| { 0xb07, "MTPK"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\ |
| { 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\ |
| { 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\ |
| { 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\ |
| { 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\ |
| { 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\ |
| { 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\ |
| { 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\ |
| { 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\ |
| { 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\ |
| { 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\ |
| { 0xfe0, "INT"}, /* enabling interrupt , */\ |
| { 0xff0, "INTP"}, /* Setting polarity interupt , */\ |
| { 0xf00, "VDDD90 "}, /* mask flag_por for interupt generation , */\ |
| { 0xf10, "OTDD90 "}, /* mask flag_otpok for interupt generation , */\ |
| { 0xf20, "OVDD90 "}, /* mask flag_ovpok for interupt generation , */\ |
| { 0xf30, "UVDD90 "}, /* mask flag_uvpok for interupt generation , */\ |
| { 0xf40, "OCDD90 "}, /* mask flag_ocp_alarm for interupt generation , */\ |
| { 0xf50, "CLKD90 "}, /* mask flag_clocks_stable for interupt generation , */\ |
| { 0xf60, "DCCD90 "}, /* mask flag_pwrokbst for interupt generation , */\ |
| { 0xf70, "SPKD90 "}, /* mask flag_cf_speakererror for interupt generation , */\ |
| { 0xf80, "WDD90 "}, /* mask flag_watchdog_reset for interupt generation , */\ |
| { 0xf90, "LCLK90 "}, /* mask flag_lost_clk for interupt generation , */\ |
| { 0xfe0, "INT90 "}, /* enabling interrupt , */\ |
| { 0xff0, "INTP90 "}, /* Setting polarity interupt , */\ |
| { 0x1000, "TDMMODE"}, /* TDM Mode , */\ |
| { 0x1011, "TDMPRF"}, /* TDM_usecase , */\ |
| { 0x1030, "TDMEN"}, /* TDM interface control , */\ |
| { 0x1040, "TDMCKINV"}, /* TDM clock inversion , */\ |
| { 0x1053, "TDMFSLN"}, /* TDM FS length , */\ |
| { 0x1090, "TDMFSPOL"}, /* TDM FS polarity , */\ |
| { 0x1103, "TDMSLOTS"}, /* Number of slots , */\ |
| { 0x1144, "TDMSLLN"}, /* Slot length , */\ |
| { 0x1194, "TDMBRMG"}, /* Bits remaining , */\ |
| { 0x11e0, "TDMDDEL"}, /* Data delay , */\ |
| { 0x11f0, "TDMDADJ"}, /* Data adjustment , */\ |
| { 0x1201, "TDMCOMP"}, /* sample_compression , */\ |
| { 0x1221, "TDMTXFRM"}, /* TXDATA format , */\ |
| { 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\ |
| { 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\ |
| { 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\ |
| { 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\ |
| { 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\ |
| { 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\ |
| { 0x12d0, "TDMSI0IO"}, /* tdm_sink0_io , */\ |
| { 0x12e0, "TDMSI1IO"}, /* tdm_sink1_io , */\ |
| { 0x12f0, "TDMSI2IO"}, /* tdm_sink2_io , */\ |
| { 0x1300, "TDMSO0IO"}, /* tdm_source0_io , */\ |
| { 0x1310, "TDMSO1IO"}, /* tdm_source1_io , */\ |
| { 0x1320, "TDMSO2IO"}, /* tdm_source2_io , */\ |
| { 0x1333, "TDMSI0SL"}, /* sink0_slot [GAIN IN] , */\ |
| { 0x1373, "TDMSI1SL"}, /* sink1_slot [CH1 IN] , */\ |
| { 0x13b3, "TDMSI2SL"}, /* sink2_slot [CH2 IN] , */\ |
| { 0x1403, "TDMSO0SL"}, /* source0_slot [GAIN OUT] , */\ |
| { 0x1443, "TDMSO1SL"}, /* source1_slot [Voltage Sense] , */\ |
| { 0x1483, "TDMSO2SL"}, /* source2_slot [Current Sense] , */\ |
| { 0x14c3, "NBCK"}, /* NBCK , */\ |
| { 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\ |
| { 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\ |
| { 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\ |
| { 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\ |
| { 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\ |
| { 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\ |
| { 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\ |
| { 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\ |
| { 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\ |
| { 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\ |
| { 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\ |
| { 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\ |
| { 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\ |
| { 0x20d0, "INTOWDS"}, /* flag_por_int_out , */\ |
| { 0x20e0, "INTOAMPS"}, /* flag_por_int_out , */\ |
| { 0x20f0, "INTOAREFS"}, /* flag_por_int_out , */\ |
| { 0x2201, "INTOACK"}, /* Interrupt status register output - Corresponding flag, */\ |
| { 0x2300, "INTIVDDS"}, /* flag_por_int_out , */\ |
| { 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\ |
| { 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\ |
| { 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\ |
| { 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\ |
| { 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\ |
| { 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\ |
| { 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\ |
| { 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\ |
| { 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\ |
| { 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\ |
| { 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\ |
| { 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\ |
| { 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\ |
| { 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\ |
| { 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\ |
| { 0x2501, "INTIACK"}, /* Interrupt register input , */\ |
| { 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\ |
| { 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\ |
| { 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\ |
| { 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\ |
| { 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\ |
| { 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\ |
| { 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\ |
| { 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\ |
| { 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\ |
| { 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\ |
| { 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\ |
| { 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\ |
| { 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\ |
| { 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\ |
| { 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\ |
| { 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\ |
| { 0x2801, "INTENACK"}, /* Interrupt enable register , */\ |
| { 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\ |
| { 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\ |
| { 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\ |
| { 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\ |
| { 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\ |
| { 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\ |
| { 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\ |
| { 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\ |
| { 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\ |
| { 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\ |
| { 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\ |
| { 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\ |
| { 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\ |
| { 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\ |
| { 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\ |
| { 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\ |
| { 0x2b01, "INTPOLACK"}, /* Interrupt status flags polarity register , */\ |
| { 0x4134, "PWMDEL"}, /* PWM DelayBits to set the delay , */\ |
| { 0x4180, "PWMSH"}, /* PWM Shape , */\ |
| { 0x4190, "PWMRE"}, /* PWM Bitlength in noise shaper , */\ |
| { 0x48e1, "TCC"}, /* sample & hold track time: , */\ |
| { 0x4900, "CLIP"}, /* Bypass clip control , */\ |
| { 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\ |
| { 0x7000, "RST"}, /* Reset CoolFlux DSP , */\ |
| { 0x7011, "DMEM"}, /* Target memory for access , */\ |
| { 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\ |
| { 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\ |
| { 0x7087, "REQ"}, /* request for access (8 channels) , */\ |
| { 0x710f, "MADD"}, /* memory-address to be accessed , */\ |
| { 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\ |
| { 0x7307, "ERR"}, /* Coolflux error flags , */\ |
| { 0x7387, "ACK"}, /* acknowledge of requests (8 channels) , */\ |
| { 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\ |
| { 0x8010, "MTPEX"}, /* (key2 protected) , */\ |
| { 0x8f0f, "VERSION"}, /* (key1 protected) , */\ |
| { 0xffff,"Unknown bitfield enum"}, /* not found */\ |
| }; |
| |
| |
| #endif |
