| /* |
| * Copyright 2012 Freescale Semiconductor, Inc. |
| * Copyright 2011 Linaro Ltd. |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| / { |
| aliases { |
| mxcfb0 = &mxcfb1; |
| mxcfb1 = &mxcfb2; |
| mxcfb2 = &mxcfb3; |
| mxcfb3 = &mxcfb4; |
| }; |
| |
| memory { |
| reg = <0x10000000 0x40000000>; |
| }; |
| |
| battery: max8903@0 { |
| compatible = "fsl,max8903-charger"; |
| pinctrl-names = "default"; |
| dok_input = <&gpio2 24 1>; |
| uok_input = <&gpio1 27 1>; |
| chg_input = <&gpio3 23 1>; |
| flt_input = <&gpio5 2 1>; |
| fsl,dcm_always_high; |
| fsl,dc_valid; |
| fsl,usb_valid; |
| status = "okay"; |
| }; |
| |
| hannstar_cabc { |
| compatible = "hannstar,cabc"; |
| |
| lvds0 { |
| gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| lvds1 { |
| gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| |
| charger-led { |
| gpios = <&gpio1 2 0>; |
| linux,default-trigger = "max8903-charger-charging"; |
| retain-state-suspended; |
| }; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| |
| reg_usb_otg_vbus: usb_otg_vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio3 22 0>; |
| enable-active-high; |
| }; |
| |
| reg_usb_h1_vbus: usb_h1_vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_h1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 29 0>; |
| enable-active-high; |
| }; |
| |
| reg_audio: wm8962_supply { |
| compatible = "regulator-fixed"; |
| regulator-name = "wm8962-supply"; |
| gpio = <&gpio4 10 0>; |
| enable-active-high; |
| }; |
| |
| reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { |
| compatible = "regulator-fixed"; |
| regulator-name = "mipi_dsi_pwr_on"; |
| gpio = <&gpio6 14 0>; |
| enable-active-high; |
| }; |
| |
| reg_sensor: sensor_supply { |
| compatible = "regulator-fixed"; |
| regulator-name = "sensor-supply"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 31 0>; |
| startup-delay-us = <500>; |
| enable-active-high; |
| }; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| power { |
| label = "Power Button"; |
| gpios = <&gpio3 29 1>; |
| linux,code = <116>; /* KEY_POWER */ |
| gpio-key,wakeup; |
| }; |
| |
| volume-up { |
| label = "Volume Up"; |
| gpios = <&gpio1 4 1>; |
| linux,code = <115>; /* KEY_VOLUMEUP */ |
| }; |
| |
| volume-down { |
| label = "Volume Down"; |
| gpios = <&gpio1 5 1>; |
| linux,code = <114>; /* KEY_VOLUMEDOWN */ |
| }; |
| }; |
| |
| sound { |
| compatible = "fsl,imx6q-sabresd-wm8962", |
| "fsl,imx-audio-wm8962"; |
| model = "wm8962-audio"; |
| cpu-dai = <&ssi2>; |
| audio-codec = <&codec>; |
| audio-routing = |
| "Headphone Jack", "HPOUTL", |
| "Headphone Jack", "HPOUTR", |
| "Ext Spk", "SPKOUTL", |
| "Ext Spk", "SPKOUTR", |
| "MICBIAS", "AMIC", |
| "IN3R", "MICBIAS", |
| "DMIC", "MICBIAS", |
| "DMICDAT", "DMIC"; |
| mux-int-port = <2>; |
| mux-ext-port = <3>; |
| hp-det-gpios = <&gpio7 8 1>; |
| mic-det-gpios = <&gpio1 9 1>; |
| }; |
| |
| sound-hdmi { |
| compatible = "fsl,imx6q-audio-hdmi", |
| "fsl,imx-audio-hdmi"; |
| model = "imx-audio-hdmi"; |
| hdmi-controller = <&hdmi_audio>; |
| }; |
| |
| mxcfb1: fb@0 { |
| compatible = "fsl,mxc_sdc_fb"; |
| disp_dev = "ldb"; |
| interface_pix_fmt = "RGB666"; |
| default_bpp = <16>; |
| int_clk = <0>; |
| late_init = <0>; |
| status = "disabled"; |
| }; |
| |
| mxcfb2: fb@1 { |
| compatible = "fsl,mxc_sdc_fb"; |
| disp_dev = "hdmi"; |
| interface_pix_fmt = "RGB24"; |
| mode_str ="1920x1080M@60"; |
| default_bpp = <24>; |
| int_clk = <0>; |
| late_init = <0>; |
| status = "disabled"; |
| }; |
| |
| mxcfb3: fb@2 { |
| compatible = "fsl,mxc_sdc_fb"; |
| disp_dev = "lcd"; |
| interface_pix_fmt = "RGB565"; |
| mode_str ="CLAA-WVGA"; |
| default_bpp = <16>; |
| int_clk = <0>; |
| late_init = <0>; |
| status = "disabled"; |
| }; |
| |
| mxcfb4: fb@3 { |
| compatible = "fsl,mxc_sdc_fb"; |
| disp_dev = "ldb"; |
| interface_pix_fmt = "RGB666"; |
| default_bpp = <16>; |
| int_clk = <0>; |
| late_init = <0>; |
| status = "disabled"; |
| }; |
| |
| lcd@0 { |
| compatible = "fsl,lcd"; |
| ipu_id = <0>; |
| disp_id = <0>; |
| default_ifmt = "RGB565"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ipu1_1>; |
| status = "okay"; |
| }; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <7>; |
| }; |
| |
| v4l2_cap_0 { |
| compatible = "fsl,imx6q-v4l2-capture"; |
| ipu_id = <0>; |
| csi_id = <0>; |
| mclk_source = <0>; |
| status = "okay"; |
| }; |
| |
| v4l2_cap_1 { |
| compatible = "fsl,imx6q-v4l2-capture"; |
| ipu_id = <0>; |
| csi_id = <1>; |
| mclk_source = <0>; |
| status = "okay"; |
| }; |
| |
| v4l2_out { |
| compatible = "fsl,mxc_v4l2_output"; |
| status = "okay"; |
| }; |
| |
| mipi_dsi_reset: mipi-dsi-reset { |
| compatible = "gpio-reset"; |
| reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <50>; |
| #reset-cells = <0>; |
| }; |
| }; |
| |
| &audmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_audmux_2>; |
| status = "okay"; |
| }; |
| |
| &cpu0 { |
| arm-supply = <&sw1a_reg>; |
| soc-supply = <&sw1c_reg>; |
| pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */ |
| }; |
| |
| &ecspi1 { |
| fsl,spi-num-chipselects = <1>; |
| cs-gpios = <&gpio4 9 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi1_2>; |
| status = "okay"; |
| |
| flash: m25p80@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "st,m25p32"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet_1>; |
| phy-mode = "rgmii"; |
| status = "okay"; |
| }; |
| |
| &gpc { |
| fsl,cpu_pupscr_sw2iso = <0xf>; |
| fsl,cpu_pupscr_sw = <0xf>; |
| fsl,cpu_pdnscr_iso2sw = <0x1>; |
| fsl,cpu_pdnscr_iso = <0x1>; |
| fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ |
| fsl,wdog-reset = <2>; /* watchdog select of reset source */ |
| pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ |
| }; |
| |
| &wdog1 { |
| status = "disabled"; |
| }; |
| |
| &wdog2 { |
| status = "okay"; |
| }; |
| |
| &gpu { |
| pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ |
| }; |
| |
| &hdmi_audio { |
| status = "okay"; |
| }; |
| |
| &hdmi_cec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hdmi_cec_2>; |
| status = "okay"; |
| }; |
| |
| &hdmi_core { |
| ipu_id = <0>; |
| disp_id = <0>; |
| status = "okay"; |
| }; |
| |
| &hdmi_video { |
| fsl,phy_reg_vlev = <0x0294>; |
| fsl,phy_reg_cksymtx = <0x800d>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1_2>; |
| status = "okay"; |
| |
| codec: wm8962@1a { |
| compatible = "wlf,wm8962"; |
| reg = <0x1a>; |
| clocks = <&clks 201>; |
| DCVDD-supply = <®_audio>; |
| DBVDD-supply = <®_audio>; |
| AVDD-supply = <®_audio>; |
| CPVDD-supply = <®_audio>; |
| MICVDD-supply = <®_audio>; |
| PLLVDD-supply = <®_audio>; |
| SPKVDD1-supply = <®_audio>; |
| SPKVDD2-supply = <®_audio>; |
| amic-mono; |
| gpio-cfg = < |
| 0x0000 /* 0:Default */ |
| 0x0000 /* 1:Default */ |
| 0x0013 /* 2:FN_DMICCLK */ |
| 0x0000 /* 3:Default */ |
| 0x8014 /* 4:FN_DMICCDAT */ |
| 0x0000 /* 5:Default */ |
| >; |
| }; |
| |
| ov564x: ov564x@3c { |
| compatible = "ovti,ov564x"; |
| reg = <0x3c>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ipu1_2>; |
| clocks = <&clks 201>; |
| clock-names = "csi_mclk"; |
| DOVDD-supply = <&vgen4_reg>; /* 1.8v */ |
| AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, |
| on rev B board is VGEN5 */ |
| DVDD-supply = <&vgen2_reg>; /* 1.5v*/ |
| pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ |
| rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ |
| csi_id = <0>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| }; |
| |
| mma8451@1c { |
| compatible = "fsl,mma8451"; |
| reg = <0x1c>; |
| position = <0>; |
| vdd-supply = <®_sensor>; |
| vddio-supply = <®_sensor>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <18 8>; |
| interrupt-route = <1>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2_2>; |
| status = "okay"; |
| |
| hdmi: edid@50 { |
| compatible = "fsl,imx6-hdmi-i2c"; |
| reg = <0x50>; |
| }; |
| |
| max11801@48 { |
| compatible = "maxim,max11801"; |
| reg = <0x48>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <26 2>; |
| work-mode = <1>;/*DCM mode*/ |
| }; |
| |
| ov5640_mipi: ov5640_mipi@3c { /* i2c2 driver */ |
| compatible = "ovti,ov5640_mipi"; |
| reg = <0x3c>; |
| clocks = <&clks 201>; |
| clock-names = "csi_mclk"; |
| DOVDD-supply = <&vgen4_reg>; /* 1.8v */ |
| AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 |
| rev B board is VGEN5 */ |
| DVDD-supply = <&vgen2_reg>; /* 1.5v*/ |
| pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ |
| rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ |
| csi_id = <1>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| }; |
| |
| egalax_ts@04 { |
| compatible = "eeti,egalax_ts"; |
| reg = <0x04>; |
| interrupt-parent = <&gpio6>; |
| interrupts = <8 2>; |
| wakeup-gpios = <&gpio6 8 0>; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3_2>; |
| status = "okay"; |
| |
| egalax_ts@04 { |
| compatible = "eeti,egalax_ts"; |
| reg = <0x04>; |
| interrupt-parent = <&gpio6>; |
| interrupts = <7 2>; |
| wakeup-gpios = <&gpio6 7 0>; |
| }; |
| |
| mag3110@0e { |
| compatible = "fsl,mag3110"; |
| reg = <0x0e>; |
| position = <2>; |
| vdd-supply = <®_sensor>; |
| vddio-supply = <®_sensor>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <16 1>; |
| }; |
| |
| elan@10 { |
| compatible = "elan,elan-touch"; |
| reg = <0x10>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <28 3>; |
| gpio_elan_cs = <&gpio2 18 0>; |
| gpio_elan_rst = <&gpio3 8 0>; |
| gpio_intr = <&gpio3 28 0>; |
| status = "okay"; |
| }; |
| |
| isl29023@44 { |
| compatible = "fsl,isl29023"; |
| reg = <0x44>; |
| rext = <499>; |
| vdd-supply = <®_sensor>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <9 2>; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| |
| hog { |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 |
| MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 |
| MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 |
| MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 |
| MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 |
| MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 |
| MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 |
| MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 |
| MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 |
| MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 |
| MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 |
| MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 |
| MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 |
| MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 |
| MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 |
| MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 |
| MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 |
| MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 |
| MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 |
| MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 |
| MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 |
| MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 |
| MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 |
| MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 |
| MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 |
| MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 |
| MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 |
| MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 |
| MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 |
| MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 |
| MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 |
| >; |
| }; |
| }; |
| }; |
| |
| &ldb { |
| status = "okay"; |
| |
| lvds-channel@0 { |
| fsl,data-mapping = "spwg"; |
| fsl,data-width = <18>; |
| status = "okay"; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| timing0: hsd100pxn1 { |
| clock-frequency = <65000000>; |
| hactive = <1024>; |
| vactive = <768>; |
| hback-porch = <220>; |
| hfront-porch = <40>; |
| vback-porch = <21>; |
| vfront-porch = <7>; |
| hsync-len = <60>; |
| vsync-len = <10>; |
| }; |
| }; |
| }; |
| |
| lvds-channel@1 { |
| fsl,data-mapping = "spwg"; |
| fsl,data-width = <18>; |
| primary; |
| status = "okay"; |
| |
| display-timings { |
| native-mode = <&timing1>; |
| timing1: hsd100pxn1 { |
| clock-frequency = <65000000>; |
| hactive = <1024>; |
| vactive = <768>; |
| hback-porch = <220>; |
| hfront-porch = <40>; |
| vback-porch = <21>; |
| vfront-porch = <7>; |
| hsync-len = <60>; |
| vsync-len = <10>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mipi_csi { |
| status = "okay"; |
| ipu_id = <0>; |
| csi_id = <1>; |
| v_channel = <0>; |
| lanes = <2>; |
| }; |
| |
| &mipi_dsi { |
| dev_id = <0>; |
| disp_id = <1>; |
| lcd_panel = "TRULY-WVGA"; |
| disp-power-on-supply = <®_mipi_dsi_pwr_on>; |
| resets = <&mipi_dsi_reset>; |
| status = "okay"; |
| }; |
| |
| &dcic1 { |
| dcic_id = <0>; |
| dcic_mux = "dcic-hdmi"; |
| status = "okay"; |
| }; |
| |
| &dcic2 { |
| dcic_id = <1>; |
| dcic_mux = "dcic-lvds1"; |
| status = "okay"; |
| }; |
| |
| &pcie { |
| power-on-gpio = <&gpio3 19 0>; |
| reset-gpio = <&gpio7 12 0>; |
| status = "okay"; |
| }; |
| |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1_1>; |
| status = "okay"; |
| }; |
| |
| &ssi2 { |
| fsl,mode = "i2s-slave"; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1_1>; |
| status = "okay"; |
| }; |
| |
| &usbh1 { |
| vbus-supply = <®_usb_h1_vbus>; |
| status = "okay"; |
| }; |
| |
| &usbotg { |
| vbus-supply = <®_usb_otg_vbus>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg_2>; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2_1>; |
| cd-gpios = <&gpio2 2 0>; |
| wp-gpios = <&gpio2 3 0>; |
| no-1-8-v; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3_1>; |
| cd-gpios = <&gpio2 0 0>; |
| wp-gpios = <&gpio2 1 0>; |
| no-1-8-v; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| status = "okay"; |
| }; |
| |
| &usdhc4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc4_1>; |
| bus-width = <8>; |
| non-removable; |
| no-1-8-v; |
| keep-power-in-suspend; |
| status = "okay"; |
| }; |
| |
| &vpu { |
| pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ |
| }; |
