| /* |
| * Copyright 2011 Freescale Semiconductor, Inc. |
| * Copyright 2011 Linaro Ltd. |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| aliases { |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| gpio5 = &gpio6; |
| gpio6 = &gpio7; |
| ipu0 = &ipu1; |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| mmc3 = &usdhc4; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| usbphy0 = &usbphy1; |
| usbphy1 = &usbphy2; |
| }; |
| |
| intc: interrupt-controller@00a01000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| reg = <0x00a01000 0x1000>, |
| <0x00a00100 0x100>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ckil { |
| compatible = "fsl,imx-ckil", "fixed-clock"; |
| clock-frequency = <32768>; |
| }; |
| |
| ckih1 { |
| compatible = "fsl,imx-ckih1", "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| osc { |
| compatible = "fsl,imx-osc", "fixed-clock"; |
| clock-frequency = <24000000>; |
| }; |
| }; |
| |
| pu_dummy: pudummy_reg { |
| compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */ |
| }; |
| |
| mxs_viim { |
| compatible = "fsl,mxs_viim"; |
| reg = <0x02098000 0x1000>, /* GPT base */ |
| <0x021bc000 0x1000>; /* OCOTP base */ |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&intc>; |
| ranges; |
| |
| caam_sm: caam-sm@00100000 { |
| compatible = "fsl,imx6q-caam-sm"; |
| reg = <0x00100000 0x3fff>; |
| }; |
| |
| dma_apbh: dma-apbh@00110000 { |
| compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| reg = <0x00110000 0x2000>; |
| interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; |
| interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| #dma-cells = <1>; |
| dma-channels = <4>; |
| clocks = <&clks 106>; |
| }; |
| |
| irq_sec_vio: caam_secvio { |
| compatible = "fsl,imx6q-caam-secvio"; |
| interrupts = <0 20 0x04>; |
| secvio_src = <0x8000001d>; |
| }; |
| |
| gpmi: gpmi-nand@00112000 { |
| compatible = "fsl,imx6q-gpmi-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| reg-names = "gpmi-nand", "bch"; |
| interrupts = <0 15 0x04>; |
| interrupt-names = "bch"; |
| clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| <&clks 150>, <&clks 149>; |
| clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| "gpmi_bch_apb", "per1_bch"; |
| dmas = <&dma_apbh 0>; |
| dma-names = "rx-tx"; |
| status = "disabled"; |
| }; |
| |
| timer@00a00600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x00a00600 0x20>; |
| interrupts = <1 13 0xf01>; |
| clocks = <&clks 15>; |
| }; |
| |
| L2: l2-cache@00a02000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a02000 0x1000>; |
| interrupts = <0 92 0x04>; |
| cache-unified; |
| cache-level = <2>; |
| arm,tag-latency = <4 2 3>; |
| arm,data-latency = <4 2 3>; |
| }; |
| |
| pcie: pcie@0x01000000 { |
| compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
| reg = <0x01ffc000 0x4000>; /* DBI */ |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ |
| 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
| 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
| num-lanes = <1>; |
| interrupts = <0 123 0x04>; |
| clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>; |
| clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate"; |
| status = "disabled"; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupts = <0 94 0x04>; |
| }; |
| |
| aips-bus@02000000 { /* AIPS1 */ |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x100000>; |
| ranges; |
| |
| spba-bus@02000000 { |
| compatible = "fsl,spba-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x40000>; |
| ranges; |
| |
| spdif: spdif@02004000 { |
| compatible = "fsl,imx6q-spdif", |
| "fsl,imx35-spdif"; |
| reg = <0x02004000 0x4000>; |
| interrupts = <0 52 0x04>; |
| dmas = <&sdma 14 18 0>, |
| <&sdma 15 18 0>; |
| dma-names = "rx", "tx"; |
| clocks = <&clks 197>, <&clks 3>, |
| <&clks 197>, <&clks 0>, |
| <&clks 0>, <&clks 0>, |
| <&clks 62>, <&clks 0>, |
| <&clks 0>, <&clks 156>; |
| clock-names = "core", "rxtx0", |
| "rxtx1", "rxtx2", |
| "rxtx3", "rxtx4", |
| "rxtx5", "rxtx6", |
| "rxtx7", "dma"; |
| status = "disabled"; |
| }; |
| |
| ecspi1: ecspi@02008000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02008000 0x4000>; |
| interrupts = <0 31 0x04>; |
| clocks = <&clks 112>, <&clks 112>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi2: ecspi@0200c000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x0200c000 0x4000>; |
| interrupts = <0 32 0x04>; |
| clocks = <&clks 113>, <&clks 113>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi3: ecspi@02010000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02010000 0x4000>; |
| interrupts = <0 33 0x04>; |
| clocks = <&clks 114>, <&clks 114>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi4: ecspi@02014000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02014000 0x4000>; |
| interrupts = <0 34 0x04>; |
| clocks = <&clks 115>, <&clks 115>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@02020000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02020000 0x4000>; |
| interrupts = <0 26 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| esai: esai@02024000 { |
| compatible = "fsl,imx35-esai"; |
| reg = <0x02024000 0x4000>; |
| interrupts = <0 51 0x04>; |
| clocks = <&clks 228>, <&clks 229>, <&clks 118>, <&clks 228>, <&clks 156>; |
| clock-names = "core", "mem", "extal", "fsys", "dma"; |
| fsl,esai-dma-events = <24 23>; |
| fsl,flags = <1>; |
| status = "disabled"; |
| }; |
| |
| ssi1: ssi@02028000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x02028000 0x4000>; |
| interrupts = <0 46 0x04>; |
| clocks = <&clks 178>, <&clks 157>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 37 1 0>, |
| <&sdma 38 1 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ssi2: ssi@0202c000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x0202c000 0x4000>; |
| interrupts = <0 47 0x04>; |
| clocks = <&clks 179>, <&clks 158>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 41 1 0>, |
| <&sdma 42 1 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ssi3: ssi@02030000 { |
| compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
| reg = <0x02030000 0x4000>; |
| interrupts = <0 48 0x04>; |
| clocks = <&clks 180>, <&clks 159>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 45 1 0>, |
| <&sdma 46 1 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| asrc: asrc@02034000 { |
| compatible = "fsl,imx53-asrc"; |
| reg = <0x02034000 0x4000>; |
| interrupts = <0 50 0x04>; |
| clocks = <&clks 227>, <&clks 226>, |
| <&clks 225>, <&clks 156>; |
| clock-names = "mem", "ipg", "asrck", "dma"; |
| dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>, |
| <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>; |
| dma-names = "rxa", "rxb", "rxc", |
| "txa", "txb", "txc"; |
| status = "okay"; |
| }; |
| |
| asrc_p2p: asrc_p2p { |
| compatible = "fsl,imx6q-asrc-p2p"; |
| fsl,p2p-rate = <48000>; |
| fsl,p2p-width = <16>; |
| fsl,asrc-dma-rx-events = <17 18 19>; |
| fsl,asrc-dma-tx-events = <20 21 22>; |
| status = "okay"; |
| }; |
| |
| spba@0203c000 { |
| reg = <0x0203c000 0x4000>; |
| }; |
| }; |
| |
| vpu: vpu@02040000 { |
| compatible = "fsl,imx6-vpu"; |
| reg = <0x02040000 0x3c000>; |
| reg-names = "vpu_regs"; |
| interrupts = <0 3 0x01>, <0 12 0x04>; |
| interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; |
| clocks = <&clks 168>, <&clks 140>, <&clks 142>; |
| clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; |
| iramsize = <0x21000>; |
| iram = <&ocram>; |
| resets = <&src 1>; |
| pu-supply = <®_pu>; |
| status = "disabled"; |
| }; |
| |
| aipstz@0207c000 { /* AIPSTZ1 */ |
| reg = <0x0207c000 0x4000>; |
| }; |
| |
| pwm1: pwm@02080000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02080000 0x4000>; |
| interrupts = <0 83 0x04>; |
| clocks = <&clks 62>, <&clks 145>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm2: pwm@02084000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02084000 0x4000>; |
| interrupts = <0 84 0x04>; |
| clocks = <&clks 62>, <&clks 146>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm3: pwm@02088000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x02088000 0x4000>; |
| interrupts = <0 85 0x04>; |
| clocks = <&clks 62>, <&clks 147>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm4: pwm@0208c000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
| reg = <0x0208c000 0x4000>; |
| interrupts = <0 86 0x04>; |
| clocks = <&clks 62>, <&clks 148>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| flexcan1: can@02090000 { |
| compatible = "fsl,imx6q-flexcan"; |
| reg = <0x02090000 0x4000>; |
| interrupts = <0 110 0x04>; |
| clocks = <&clks 108>, <&clks 109>; |
| clock-names = "ipg", "per"; |
| stop-mode = <&gpr 0x34 28 0x10 17>; |
| status = "disabled"; |
| }; |
| |
| flexcan2: can@02094000 { |
| compatible = "fsl,imx6q-flexcan"; |
| reg = <0x02094000 0x4000>; |
| interrupts = <0 111 0x04>; |
| clocks = <&clks 110>, <&clks 111>; |
| clock-names = "ipg", "per"; |
| stop-mode = <&gpr 0x34 29 0x10 18>; |
| status = "disabled"; |
| }; |
| |
| gpt: gpt@02098000 { |
| compatible = "fsl,imx6q-gpt"; |
| reg = <0x02098000 0x4000>; |
| interrupts = <0 55 0x04>; |
| clocks = <&clks 119>, <&clks 120>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| gpio1: gpio@0209c000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x0209c000 0x4000>; |
| interrupts = <0 66 0x04 0 67 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@020a0000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a0000 0x4000>; |
| interrupts = <0 68 0x04 0 69 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@020a4000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a4000 0x4000>; |
| interrupts = <0 70 0x04 0 71 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio4: gpio@020a8000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a8000 0x4000>; |
| interrupts = <0 72 0x04 0 73 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio5: gpio@020ac000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020ac000 0x4000>; |
| interrupts = <0 74 0x04 0 75 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio6: gpio@020b0000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020b0000 0x4000>; |
| interrupts = <0 76 0x04 0 77 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio7: gpio@020b4000 { |
| compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| reg = <0x020b4000 0x4000>; |
| interrupts = <0 78 0x04 0 79 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| kpp: kpp@020b8000 { |
| reg = <0x020b8000 0x4000>; |
| interrupts = <0 82 0x04>; |
| }; |
| |
| wdog1: wdog@020bc000 { |
| compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| reg = <0x020bc000 0x4000>; |
| interrupts = <0 80 0x04>; |
| clocks = <&clks 0>; |
| }; |
| |
| wdog2: wdog@020c0000 { |
| compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| reg = <0x020c0000 0x4000>; |
| interrupts = <0 81 0x04>; |
| clocks = <&clks 0>; |
| status = "disabled"; |
| }; |
| |
| clks: ccm@020c4000 { |
| compatible = "fsl,imx6q-ccm"; |
| reg = <0x020c4000 0x4000>; |
| interrupts = <0 87 0x04 0 88 0x04>; |
| #clock-cells = <1>; |
| }; |
| |
| anatop: anatop@020c8000 { |
| compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
| reg = <0x020c8000 0x1000>; |
| interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
| |
| regulator-1p1@110 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd1p1"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1375000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x110>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <4>; |
| anatop-min-voltage = <800000>; |
| anatop-max-voltage = <1375000>; |
| }; |
| |
| regulator-3p0@120 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd3p0"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <3150000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x120>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2625000>; |
| anatop-max-voltage = <3400000>; |
| }; |
| |
| regulator-2p5@130 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd2p5"; |
| regulator-min-microvolt = <2000000>; |
| regulator-max-microvolt = <2750000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x130>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2000000>; |
| anatop-max-voltage = <2750000>; |
| }; |
| |
| reg_arm: regulator-vddcore@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "cpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <0>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <24>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| reg_pu: regulator-vddpu@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <9>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <26>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| reg_soc: regulator-vddsoc@140 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddsoc"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <18>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <28>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| }; |
| |
| tempmon: tempmon { |
| compatible = "fsl,imx6q-tempmon"; |
| interrupts = <0 49 0x04>; |
| fsl,tempmon = <&anatop>; |
| fsl,tempmon-data = <&ocotp>; |
| clocks = <&clks 172>; |
| }; |
| |
| usbphy1: usbphy@020c9000 { |
| compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020c9000 0x1000>; |
| interrupts = <0 44 0x04>; |
| clocks = <&clks 182>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| usbphy2: usbphy@020ca000 { |
| compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020ca000 0x1000>; |
| interrupts = <0 45 0x04>; |
| clocks = <&clks 183>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| usbphy_nop1: usbphy_nop1 { |
| compatible = "usb-nop-xceiv"; |
| clocks = <&clks 182>; |
| clock-names = "main_clk"; |
| }; |
| |
| usbphy_nop2: usbphy_nop2 { |
| compatible = "usb-nop-xceiv"; |
| clocks = <&clks 182>; |
| clock-names = "main_clk"; |
| }; |
| |
| caam_snvs: caam-snvs@020cc000 { |
| compatible = "fsl,imx6q-caam-snvs"; |
| reg = <0x020cc000 0x4000>; |
| }; |
| |
| snvs@020cc000 { |
| compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x020cc000 0x4000>; |
| |
| snvs-rtc-lp@34 { |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| reg = <0x34 0x58>; |
| interrupts = <0 19 0x04 0 20 0x04>; |
| }; |
| }; |
| |
| epit1: epit@020d0000 { /* EPIT1 */ |
| reg = <0x020d0000 0x4000>; |
| interrupts = <0 56 0x04>; |
| }; |
| |
| epit2: epit@020d4000 { /* EPIT2 */ |
| reg = <0x020d4000 0x4000>; |
| interrupts = <0 57 0x04>; |
| }; |
| |
| src: src@020d8000 { |
| compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| reg = <0x020d8000 0x4000>; |
| interrupts = <0 91 0x04 0 96 0x04>; |
| #reset-cells = <1>; |
| }; |
| |
| gpc: gpc@020dc000 { |
| compatible = "fsl,imx6q-gpc"; |
| reg = <0x020dc000 0x4000>; |
| interrupts = <0 89 0x04 0 90 0x04>; |
| clocks = <&clks 122>, <&clks 74>, <&clks 121>, |
| <&clks 26>, <&clks 143>, <&clks 168>, <&clks 62>; |
| clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core", |
| "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg"; |
| pu-supply = <®_pu>; |
| }; |
| |
| gpr: iomuxc-gpr@020e0000 { |
| compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; |
| reg = <0x020e0000 0x38>; |
| }; |
| |
| iomuxc: iomuxc@020e0000 { |
| reg = <0x020e0000 0x4000>; |
| }; |
| |
| ldb: ldb@020e0008 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| gpr = <&gpr>; |
| status = "disabled"; |
| |
| lvds-channel@0 { |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| lvds-channel@1 { |
| reg = <1>; |
| status = "disabled"; |
| }; |
| }; |
| |
| dcic1: dcic@020e4000 { |
| compatible = "fsl,imx6q-dcic"; |
| reg = <0x020e4000 0x4000>; |
| interrupts = <0 124 0x04>; |
| clocks = <&clks 231>, <&clks 231>; |
| clock-names = "dcic", "disp-axi"; |
| gpr = <&gpr>; |
| status = "disabled"; |
| }; |
| |
| dcic2: dcic@020e8000 { |
| compatible = "fsl,imx6q-dcic"; |
| reg = <0x020e8000 0x4000>; |
| interrupts = <0 125 0x04>; |
| clocks = <&clks 232>, <&clks 232>; |
| clock-names = "dcic", "disp-axi"; |
| gpr = <&gpr>; |
| status = "disabled"; |
| }; |
| |
| sdma: sdma@020ec000 { |
| compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| reg = <0x020ec000 0x4000>; |
| interrupts = <0 2 0x04>; |
| clocks = <&clks 155>, <&clks 155>; |
| clock-names = "ipg", "ahb"; |
| #dma-cells = <3>; |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| }; |
| }; |
| |
| aips-bus@02100000 { /* AIPS2 */ |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02100000 0x100000>; |
| ranges; |
| |
| crypto: caam@2100000 { |
| compatible = "fsl,sec-v4.0"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x2100000 0x40000>; |
| ranges = <0 0x2100000 0x40000>; |
| interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ |
| clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>; |
| clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; |
| |
| sec_jr0: jr0@1000 { |
| compatible = "fsl,sec-v4.0-job-ring"; |
| reg = <0x1000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <0 105 0x4>; |
| }; |
| |
| sec_jr1: jr1@2000 { |
| compatible = "fsl,sec-v4.0-job-ring"; |
| reg = <0x2000 0x1000>; |
| interrupt-parent = <&intc>; |
| interrupts = <0 106 0x4>; |
| }; |
| }; |
| |
| aipstz@0217c000 { /* AIPSTZ2 */ |
| reg = <0x0217c000 0x4000>; |
| }; |
| |
| usbotg: usb@02184000 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184000 0x200>; |
| interrupts = <0 43 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbphy = <&usbphy1>; |
| fsl,usbmisc = <&usbmisc 0>; |
| fsl,anatop = <&anatop>; |
| status = "disabled"; |
| }; |
| |
| usbh1: usb@02184200 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184200 0x200>; |
| interrupts = <0 40 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbphy = <&usbphy2>; |
| fsl,usbmisc = <&usbmisc 1>; |
| status = "disabled"; |
| }; |
| |
| usbh2: usb@02184400 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184400 0x200>; |
| interrupts = <0 41 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbmisc = <&usbmisc 2>; |
| phy_type = "hsic"; |
| fsl,usbphy = <&usbphy_nop1>; |
| fsl,anatop = <&anatop>; |
| status = "disabled"; |
| }; |
| |
| usbh3: usb@02184600 { |
| compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| reg = <0x02184600 0x200>; |
| interrupts = <0 42 0x04>; |
| clocks = <&clks 162>; |
| fsl,usbmisc = <&usbmisc 3>; |
| phy_type = "hsic"; |
| fsl,usbphy = <&usbphy_nop2>; |
| fsl,anatop = <&anatop>; |
| status = "disabled"; |
| }; |
| |
| usbmisc: usbmisc: usbmisc@02184800 { |
| #index-cells = <1>; |
| compatible = "fsl,imx6q-usbmisc"; |
| reg = <0x02184800 0x200>; |
| clocks = <&clks 162>; |
| }; |
| |
| fec: ethernet@02188000 { |
| compatible = "fsl,imx6q-fec"; |
| reg = <0x02188000 0x4000>; |
| interrupts-extended = <&intc 0 118 0x04>, |
| <&intc 0 119 0x04>; |
| clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
| clock-names = "ipg", "ahb", "ptp"; |
| status = "disabled"; |
| }; |
| |
| mlb: mlb@0218c000 { |
| compatible = "fsl,imx6q-mlb150"; |
| reg = <0x0218c000 0x4000>; |
| interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; |
| clocks = <&clks 139>, <&clks 175>; |
| clock-names = "mlb", "pll8_mlb"; |
| iram = <&ocram>; |
| status = "disabled"; |
| }; |
| |
| usdhc1: usdhc@02190000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02190000 0x4000>; |
| interrupts = <0 22 0x04>; |
| clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: usdhc@02194000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02194000 0x4000>; |
| interrupts = <0 23 0x04>; |
| clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: usdhc@02198000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x02198000 0x4000>; |
| interrupts = <0 24 0x04>; |
| clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc4: usdhc@0219c000 { |
| compatible = "fsl,imx6q-usdhc"; |
| reg = <0x0219c000 0x4000>; |
| interrupts = <0 25 0x04>; |
| clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@021a0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a0000 0x4000>; |
| interrupts = <0 36 0x04>; |
| clocks = <&clks 125>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@021a4000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a4000 0x4000>; |
| interrupts = <0 37 0x04>; |
| clocks = <&clks 126>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@021a8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a8000 0x4000>; |
| interrupts = <0 38 0x04>; |
| clocks = <&clks 127>; |
| status = "disabled"; |
| }; |
| |
| romcp@021ac000 { |
| reg = <0x021ac000 0x4000>; |
| }; |
| |
| mmdc0-1@021b0000 { /* MMDC0-1 */ |
| compatible = "fsl,imx6q-mmdc-combine"; |
| reg = <0x021b0000 0x8000>; |
| }; |
| |
| mmdc0: mmdc@021b0000 { /* MMDC0 */ |
| compatible = "fsl,imx6q-mmdc"; |
| reg = <0x021b0000 0x4000>; |
| }; |
| |
| mmdc1: mmdc@021b4000 { /* MMDC1 */ |
| reg = <0x021b4000 0x4000>; |
| }; |
| |
| weim: weim@021b8000 { |
| compatible = "fsl,imx6q-weim"; |
| reg = <0x021b8000 0x4000>; |
| interrupts = <0 14 0x04>; |
| clocks = <&clks 196>; |
| }; |
| |
| ocotp: ocotp-ctrl@021bc000 { |
| compatible = "syscon"; |
| reg = <0x021bc000 0x4000>; |
| clocks = <&clks 128>; |
| }; |
| |
| ocotp-fuse@021bc000 { |
| compatible = "fsl,imx6q-ocotp"; |
| reg = <0x021bc000 0x4000>; |
| clocks = <&clks 128>; |
| }; |
| |
| tzasc@021d0000 { /* TZASC1 */ |
| reg = <0x021d0000 0x4000>; |
| interrupts = <0 108 0x04>; |
| }; |
| |
| tzasc@021d4000 { /* TZASC2 */ |
| reg = <0x021d4000 0x4000>; |
| interrupts = <0 109 0x04>; |
| }; |
| |
| audmux: audmux@021d8000 { |
| compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
| reg = <0x021d8000 0x4000>; |
| status = "disabled"; |
| }; |
| |
| mipi_csi: mipi_csi@021dc000 { |
| compatible = "fsl,imx6q-mipi-csi2"; |
| reg = <0x021dc000 0x4000>; |
| interrupts = <0 100 0x04>, <0 101 0x04>; |
| clocks = <&clks 138>, <&clks 53>, <&clks 204>; |
| /* Note: clks 138 is hsi_tx, however, the dphy_c |
| * hsi_tx and pll_refclk use the same clk gate. |
| * In current clk driver, open/close clk gate do |
| * use hsi_tx for a temporary debug purpose. |
| */ |
| clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; |
| status = "disabled"; |
| }; |
| |
| vdoa@021e4000 { |
| compatible = "fsl,imx6q-vdoa"; |
| reg = <0x021e4000 0x4000>; |
| interrupts = <0 18 0x04>; |
| clocks = <&clks 202>; |
| iram = <&ocram>; |
| }; |
| |
| uart2: serial@021e8000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021e8000 0x4000>; |
| interrupts = <0 27 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@021ec000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021ec000 0x4000>; |
| interrupts = <0 28 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@021f0000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021f0000 0x4000>; |
| interrupts = <0 29 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@021f4000 { |
| compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x021f4000 0x4000>; |
| interrupts = <0 30 0x04>; |
| clocks = <&clks 160>, <&clks 161>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| ipu1: ipu@02400000 { |
| compatible = "fsl,imx6q-ipu"; |
| reg = <0x02400000 0x400000>; |
| interrupts = <0 6 0x4 0 5 0x4>; |
| clocks = <&clks 130>, <&clks 131>, <&clks 132>, |
| <&clks 39>, <&clks 40>, |
| <&clks 135>, <&clks 136>; |
| clock-names = "bus", "di0", "di1", |
| "di0_sel", "di1_sel", |
| "ldb_di0", "ldb_di1"; |
| resets = <&src 2>; |
| bypass_reset = <0>; |
| }; |
| }; |
| }; |
| |
| |
| &iomuxc { |
| audmux { |
| pinctrl_audmux_1: audmux-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 |
| MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 |
| MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 |
| MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 |
| >; |
| }; |
| |
| pinctrl_audmux_2: audmux-2 { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 |
| MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 |
| MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 |
| MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 |
| >; |
| }; |
| |
| pinctrl_audmux_3: audmux-3 { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 |
| MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 |
| MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 |
| >; |
| }; |
| }; |
| |
| ecspi1 { |
| pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 |
| >; |
| }; |
| |
| pinctrl_ecspi1_1: ecspi1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| >; |
| }; |
| |
| pinctrl_ecspi1_2: ecspi1grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 |
| MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 |
| MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 |
| >; |
| }; |
| }; |
| |
| ecspi3 { |
| pinctrl_ecspi3_1: ecspi3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
| MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
| MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
| >; |
| }; |
| }; |
| |
| enet { |
| pinctrl_enet_1: enetgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| >; |
| }; |
| |
| pinctrl_enet_2: enetgrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| >; |
| }; |
| |
| pinctrl_enet_3: enetgrp-3 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_enet_irq: enetirqgrp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 |
| >; |
| }; |
| }; |
| |
| esai { |
| pinctrl_esai_1: esaigrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 |
| MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 |
| MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 |
| MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 |
| MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 |
| MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 |
| MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 |
| MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 |
| MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 |
| >; |
| }; |
| |
| pinctrl_esai_2: esaigrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 |
| MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 |
| MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 |
| MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 |
| MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 |
| MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 |
| MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 |
| MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 |
| MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 |
| MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 |
| >; |
| }; |
| }; |
| |
| flexcan1 { |
| pinctrl_flexcan1_1: flexcan1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 |
| MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 |
| >; |
| }; |
| |
| pinctrl_flexcan1_2: flexcan1grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 |
| MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 |
| >; |
| }; |
| }; |
| |
| flexcan2 { |
| pinctrl_flexcan2_1: flexcan2grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 |
| MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 |
| >; |
| }; |
| }; |
| |
| gpmi-nand { |
| pinctrl_gpmi_nand_1: gpmi-nand-1 { |
| fsl,pins = < |
| MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
| MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
| MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
| MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
| MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
| MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
| MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
| MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
| MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
| MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
| MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 |
| >; |
| }; |
| }; |
| |
| hdmi_hdcp { |
| pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 |
| >; |
| }; |
| }; |
| |
| hdmi_cec { |
| pinctrl_hdmi_cec_1: hdmicecgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 |
| >; |
| }; |
| |
| pinctrl_hdmi_cec_2: hdmicecgrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 |
| >; |
| }; |
| }; |
| |
| i2c1 { |
| pinctrl_i2c1_1: i2c1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c1_2: i2c1grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 |
| MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 |
| >; |
| }; |
| }; |
| |
| i2c2 { |
| pinctrl_i2c2_1: i2c2grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c2_2: i2c2grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c2_3: i2c2grp-3 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| }; |
| |
| i2c3 { |
| pinctrl_i2c3_1: i2c3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c3_2: i2c3grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
| MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c3_3: i2c3grp-3 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 |
| MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c3_4: i2c3grp-4 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| }; |
| |
| ipu1 { |
| pinctrl_ipu1_1: ipu1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 |
| MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 |
| MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 |
| MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 |
| MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 |
| MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 |
| MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 |
| MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 |
| MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 |
| MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 |
| MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 |
| MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 |
| MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 |
| MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 |
| MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 |
| MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 |
| MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 |
| MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 |
| MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 |
| MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 |
| MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 |
| MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 |
| MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 |
| MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 |
| MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 |
| MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 |
| MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 |
| MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 |
| MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 |
| >; |
| }; |
| |
| pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 |
| MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 |
| MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 |
| MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 |
| MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 |
| MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 |
| MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 |
| MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 |
| MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 |
| MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 |
| MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 |
| MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 |
| >; |
| }; |
| |
| pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 |
| MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 |
| MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 |
| MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 |
| MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 |
| MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 |
| MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 |
| MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 |
| MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 |
| MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 |
| MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 |
| MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 |
| MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 |
| MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 |
| MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 |
| MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 |
| MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 |
| MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 |
| MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 |
| >; |
| }; |
| }; |
| |
| mlb { |
| pinctrl_mlb_1: mlbgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 |
| MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 |
| MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 |
| >; |
| }; |
| |
| pinctrl_mlb_2: mlbgrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 |
| MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 |
| MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 |
| >; |
| }; |
| }; |
| |
| pwm1 { |
| pinctrl_pwm1_1: pwm1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| pwm3 { |
| pinctrl_pwm3_1: pwm3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| spdif { |
| pinctrl_spdif_1: spdifgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_spdif_2: spdifgrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 |
| MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 |
| >; |
| }; |
| }; |
| |
| uart1 { |
| pinctrl_uart1_1: uart1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| uart2 { |
| pinctrl_uart2_1: uart2grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 |
| MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| uart3 { |
| pinctrl_uart3_1: uart3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 |
| MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart3dte_1: uart3dtegrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 |
| MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| uart4 { |
| pinctrl_uart4_1: uart4grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| uart5 { |
| pinctrl_uart5_1: uart5grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 |
| MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart5dte_1: uart5dtegrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 |
| MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 |
| >; |
| }; |
| }; |
| |
| usbotg { |
| pinctrl_usbotg_1: usbotggrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
| >; |
| }; |
| |
| pinctrl_usbotg_2: usbotggrp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 |
| >; |
| }; |
| }; |
| |
| usbh2 { |
| pinctrl_usbh2_1: usbh2grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 |
| MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 |
| >; |
| }; |
| |
| pinctrl_usbh2_2: usbh2grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 |
| >; |
| }; |
| }; |
| |
| usbh3 { |
| pinctrl_usbh3_1: usbh3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 |
| MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 |
| >; |
| }; |
| |
| pinctrl_usbh3_2: usbh3grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 |
| >; |
| }; |
| }; |
| |
| usdhc1 { |
| pinctrl_usdhc1_1: usdhc1grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 |
| MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 |
| MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 |
| MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 |
| MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 |
| MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 |
| >; |
| }; |
| }; |
| |
| usdhc2 { |
| pinctrl_usdhc2_1: usdhc2grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 |
| MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 |
| MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 |
| MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_2: usdhc2grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| >; |
| }; |
| }; |
| |
| usdhc3 { |
| pinctrl_usdhc3_1: usdhc3grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9 |
| >; |
| }; |
| |
| pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9 |
| >; |
| }; |
| |
| pinctrl_usdhc3_2: usdhc3grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| >; |
| }; |
| }; |
| |
| usdhc4 { |
| pinctrl_usdhc4_1: usdhc4grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 |
| MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 |
| MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 |
| MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc4_2: usdhc4grp-2 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 |
| MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 |
| MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 |
| MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 |
| MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 |
| MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 |
| >; |
| }; |
| }; |
| |
| weim { |
| pinctrl_weim_cs0_1: weim_cs0grp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 |
| >; |
| }; |
| |
| pinctrl_weim_nor_1: weim_norgrp-1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 |
| MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 |
| MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 |
| /* data */ |
| MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 |
| MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 |
| MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 |
| MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 |
| MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 |
| MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 |
| MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 |
| MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 |
| MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 |
| MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 |
| MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 |
| MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 |
| MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 |
| MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 |
| MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 |
| MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 |
| /* address */ |
| MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 |
| MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 |
| MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 |
| MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 |
| MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 |
| MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 |
| MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 |
| MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 |
| MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 |
| MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 |
| MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 |
| MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 |
| MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 |
| MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 |
| MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 |
| MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 |
| MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 |
| MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 |
| MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 |
| MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 |
| MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 |
| MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 |
| MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 |
| MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 |
| >; |
| }; |
| }; |
| }; |
