| /* |
| * Copyright (C) 2014 Freescale Semiconductor, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx6sx.dtsi" |
| |
| / { |
| model = "Freescale i.MX6 SoloX 19x19 ARM2 Board"; |
| compatible = "fsl,imx6sx-19x19-arm2", "fsl,imx6sx"; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm3 0 5000000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| }; |
| |
| csi1_v4l2_cap { |
| compatible = "fsl,imx6sx-csi-v4l2", "fsl,imx6sl-csi-v4l2"; |
| csi_id = <0>; |
| status = "okay"; |
| }; |
| |
| csi2_v4l2_cap { |
| compatible = "fsl,imx6sx-csi-v4l2", "fsl,imx6sl-csi-v4l2"; |
| csi_id = <1>; |
| status = "okay"; |
| }; |
| |
| hannstar_cabc { |
| compatible = "hannstar,cabc"; |
| |
| lvds0 { |
| gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| clocks { |
| codec_osc: codec_osc { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <12000000>; |
| }; |
| }; |
| |
| max7322_reset: max7322-reset { |
| compatible = "gpio-reset"; |
| reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <1>; |
| #reset-cells = <0>; |
| }; |
| |
| pxp_v4l2_out { |
| compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; |
| status = "okay"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| |
| reg_3p3v: 3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_usb_otg1_vbus: usb_otg1_vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 9 0>; |
| enable-active-high; |
| }; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x40000000>; |
| }; |
| |
| sound-cs42888 { |
| compatible = "fsl,imx6-sabreauto-cs42888", |
| "fsl,imx-audio-cs42888"; |
| model = "imx-cs42888"; |
| esai-controller = <&esai>; |
| asrc-controller = <&asrc_p2p>; |
| audio-codec = <&cs42888>; |
| }; |
| }; |
| |
| &esai { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_esai_1>; |
| status = "okay"; |
| }; |
| |
| &cpu0 { |
| arm-supply = <&sw1a_reg>; |
| soc-supply = <&sw1c_reg>; |
| pu-supply = <&pu_dummy>; |
| }; |
| |
| &csi1 { |
| status = "okay"; |
| }; |
| |
| &csi2 { |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1_1>; |
| phy-mode = "rgmii"; |
| phy-id = <1>; |
| fsl,num_tx_queues=<3>; |
| fsl,num_rx_queues=<3>; |
| pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; |
| fsl,magic-packet; |
| status = "okay"; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2_1>; |
| phy-mode = "rgmii"; |
| phy-id = <0>; |
| fsl,num_tx_queues=<3>; |
| fsl,num_rx_queues=<3>; |
| pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; |
| fsl,magic-packet; |
| status = "okay"; |
| }; |
| |
| &gpc { |
| fsl,cpu_pupscr_sw2iso = <0x2>; |
| fsl,cpu_pupscr_sw = <0x1>; |
| fsl,cpu_pdnscr_iso2sw = <0x1>; |
| fsl,cpu_pdnscr_iso = <0x1>; |
| fsl,wdog-reset = <1>; /* watchdog select of reset source */ |
| fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1_1>; |
| status = "okay"; |
| |
| pmic: pfuze100@08 { |
| compatible = "fsl,pfuze100"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw1c_reg: sw1c { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3a { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3b_reg: sw3b { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw4_reg: sw4 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vgen1 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen2_reg: vgen2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2_1>; |
| status = "okay"; |
| |
| max7322_1: gpio@68 { |
| compatible = "maxim,max7322"; |
| reg = <0x68>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| resets = <&max7322_reset>; |
| }; |
| |
| max7322_2: gpio@69 { |
| compatible = "maxim,max7322"; |
| reg = <0x69>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| resets = <&max7322_reset>; |
| }; |
| |
| ov564x: ov564x@3c { |
| compatible = "ovti,ov564x"; |
| reg = <0x3c>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_csi_1>; |
| clocks = <&clks IMX6SX_CLK_CSI>; |
| clock-names = "csi_mclk"; |
| AVDD-supply = <&vgen3_reg>; /* 2.8v */ |
| DVDD-supply = <&vgen2_reg>; /* 1.5v*/ |
| pwn-gpios = <&gpio3 26 1>; |
| rst-gpios = <&gpio3 25 0>; |
| csi_id = <0>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3_1>; |
| status = "okay"; |
| }; |
| |
| &i2c4 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c4_2>; |
| status = "okay"; |
| |
| sgtl5000: sgtl5000@0a { |
| compatible = "fsl,sgtl5000"; |
| reg = <0x0a>; |
| clocks = <&codec_osc>; |
| VDDA-supply = <&vgen4_reg>; |
| VDDIO-supply = <®_3p3v>; |
| }; |
| |
| cs42888: cs42888@048 { |
| compatible = "cirrus,cs42888"; |
| reg = <0x048>; |
| clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>; |
| clock-names = "mclk"; |
| VA-supply = <®_3p3v>; |
| VD-supply = <®_3p3v>; |
| VLS-supply = <®_3p3v>; |
| VLC-supply = <®_3p3v>; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| |
| hog { |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0 |
| MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0 |
| MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 |
| >; |
| }; |
| }; |
| }; |
| |
| &lcdif1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcdif_dat_0 |
| &pinctrl_lcdif_ctrl_0>; |
| display = <&display0>; |
| status = "disabled"; |
| |
| display0: display { |
| bits-per-pixel = <16>; |
| bus-width = <24>; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| timing0: timing0 { |
| clock-frequency = <33500000>; |
| hactive = <800>; |
| vactive = <480>; |
| hback-porch = <89>; |
| hfront-porch = <164>; |
| vback-porch = <23>; |
| vfront-porch = <10>; |
| hsync-len = <10>; |
| vsync-len = <10>; |
| hsync-active = <0>; |
| vsync-active = <0>; |
| de-active = <1>; |
| pixelclk-active = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &lcdif2 { |
| display = <&display1>; |
| disp-dev = "ldb"; |
| status = "okay"; |
| |
| display1: display { |
| bits-per-pixel = <16>; |
| bus-width = <18>; |
| }; |
| }; |
| |
| &ldb { |
| status = "okay"; |
| |
| lvds-channel@0 { |
| fsl,data-mapping = "spwg"; |
| fsl,data-width = <18>; |
| crtc = "lcdif2"; |
| status = "okay"; |
| |
| display-timings { |
| native-mode = <&timing1>; |
| timing1: hsd100pxn1 { |
| clock-frequency = <65000000>; |
| hactive = <1024>; |
| vactive = <768>; |
| hback-porch = <220>; |
| hfront-porch = <40>; |
| vback-porch = <21>; |
| vfront-porch = <7>; |
| hsync-len = <60>; |
| vsync-len = <10>; |
| }; |
| }; |
| }; |
| }; |
| |
| &dcic1 { |
| dcic_id = <0>; |
| dcic_mux = "dcic-lcdif1"; |
| status = "okay"; |
| }; |
| |
| &dcic2 { |
| dcic_id = <1>; |
| dcic_mux = "dcic-lvds"; |
| status = "okay"; |
| }; |
| |
| &pwm3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm3_0>; |
| status = "okay"; |
| }; |
| |
| &pxp { |
| status = "okay"; |
| }; |
| |
| &sai1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai1_1>; |
| status = "disabled"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1_1>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2_1>; |
| status = "okay"; |
| }; |
| |
| &qspi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi2_1>; |
| status = "okay"; |
| ddrsmp=<2>; |
| |
| flash0: n25q256a@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,n25q256a"; |
| spi-max-frequency = <29000000>; |
| reg = <0>; |
| }; |
| |
| flash1: n25q256a@1 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,n25q256a"; |
| spi-max-frequency = <29000000>; |
| reg = <1>; |
| }; |
| }; |
| |
| &usbh { |
| pinctrl-names = "idle", "active"; |
| pinctrl-0 = <&pinctrl_usbh_1>; |
| pinctrl-1 = <&pinctrl_usbh_2>; |
| osc-clkgate-delay = <0x3>; |
| pad-supply = <&vgen1_reg>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg1_1>; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1_1>; |
| bus-width = <4>; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| no-1-8-v; |
| status = "okay"; |
| }; |
| |
| &weim { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <0 0 0x50000000 0x08000000>; |
| status = "disabled"; /* pin conflict with qspi, nand and lcd1 */ |
| |
| nor@0,0 { |
| compatible = "cfi-flash"; |
| reg = <0 0 0x02000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| bank-width = <2>; |
| fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 |
| 0x0000c000 0x1404a38e 0x00000000>; |
| }; |
| }; |
| |
| &vadc { |
| vadc_in = <0>; |
| csi_id = <1>; |
| status = "okay"; |
| }; |
