| /* |
| * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| * |
| * This software is licensed under the terms of the GNU General Public |
| * License version 2, as published by the Free Software Foundation, and |
| * may be copied, distributed, and modified under those terms. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <linux/kernel.h> |
| #include <linux/bitops.h> |
| #include <linux/err.h> |
| #include <linux/platform_device.h> |
| #include <linux/module.h> |
| #include <linux/of.h> |
| #include <linux/of_device.h> |
| #include <linux/clk-provider.h> |
| #include <linux/regmap.h> |
| #include <linux/reset-controller.h> |
| |
| #include <dt-bindings/clock/qcom,gcc-msm8960.h> |
| #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
| |
| #include "common.h" |
| #include "clk-regmap.h" |
| #include "clk-pll.h" |
| #include "clk-rcg.h" |
| #include "clk-branch.h" |
| #include "reset.h" |
| |
| static struct clk_pll pll3 = { |
| .l_reg = 0x3164, |
| .m_reg = 0x3168, |
| .n_reg = 0x316c, |
| .config_reg = 0x3174, |
| .mode_reg = 0x3160, |
| .status_reg = 0x3178, |
| .status_bit = 16, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pll3", |
| .parent_names = (const char *[]){ "pxo" }, |
| .num_parents = 1, |
| .ops = &clk_pll_ops, |
| }, |
| }; |
| |
| static struct clk_regmap pll4_vote = { |
| .enable_reg = 0x34c0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "pll4_vote", |
| .parent_names = (const char *[]){ "pll4" }, |
| .num_parents = 1, |
| .ops = &clk_pll_vote_ops, |
| }, |
| }; |
| |
| static struct clk_pll pll8 = { |
| .l_reg = 0x3144, |
| .m_reg = 0x3148, |
| .n_reg = 0x314c, |
| .config_reg = 0x3154, |
| .mode_reg = 0x3140, |
| .status_reg = 0x3158, |
| .status_bit = 16, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pll8", |
| .parent_names = (const char *[]){ "pxo" }, |
| .num_parents = 1, |
| .ops = &clk_pll_ops, |
| }, |
| }; |
| |
| static struct clk_regmap pll8_vote = { |
| .enable_reg = 0x34c0, |
| .enable_mask = BIT(8), |
| .hw.init = &(struct clk_init_data){ |
| .name = "pll8_vote", |
| .parent_names = (const char *[]){ "pll8" }, |
| .num_parents = 1, |
| .ops = &clk_pll_vote_ops, |
| }, |
| }; |
| |
| static struct clk_pll pll14 = { |
| .l_reg = 0x31c4, |
| .m_reg = 0x31c8, |
| .n_reg = 0x31cc, |
| .config_reg = 0x31d4, |
| .mode_reg = 0x31c0, |
| .status_reg = 0x31d8, |
| .status_bit = 16, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "pll14", |
| .parent_names = (const char *[]){ "pxo" }, |
| .num_parents = 1, |
| .ops = &clk_pll_ops, |
| }, |
| }; |
| |
| static struct clk_regmap pll14_vote = { |
| .enable_reg = 0x34c0, |
| .enable_mask = BIT(14), |
| .hw.init = &(struct clk_init_data){ |
| .name = "pll14_vote", |
| .parent_names = (const char *[]){ "pll14" }, |
| .num_parents = 1, |
| .ops = &clk_pll_vote_ops, |
| }, |
| }; |
| |
| enum { |
| P_PXO, |
| P_PLL8, |
| P_PLL3, |
| P_CXO, |
| }; |
| |
| static const struct parent_map gcc_pxo_pll8_map[] = { |
| { P_PXO, 0 }, |
| { P_PLL8, 3 } |
| }; |
| |
| static const char *gcc_pxo_pll8[] = { |
| "pxo", |
| "pll8_vote", |
| }; |
| |
| static const struct parent_map gcc_pxo_pll8_cxo_map[] = { |
| { P_PXO, 0 }, |
| { P_PLL8, 3 }, |
| { P_CXO, 5 } |
| }; |
| |
| static const char *gcc_pxo_pll8_cxo[] = { |
| "pxo", |
| "pll8_vote", |
| "cxo", |
| }; |
| |
| static const struct parent_map gcc_pxo_pll8_pll3_map[] = { |
| { P_PXO, 0 }, |
| { P_PLL8, 3 }, |
| { P_PLL3, 6 } |
| }; |
| |
| static const char *gcc_pxo_pll8_pll3[] = { |
| "pxo", |
| "pll8_vote", |
| "pll3", |
| }; |
| |
| static struct freq_tbl clk_tbl_gsbi_uart[] = { |
| { 1843200, P_PLL8, 2, 6, 625 }, |
| { 3686400, P_PLL8, 2, 12, 625 }, |
| { 7372800, P_PLL8, 2, 24, 625 }, |
| { 14745600, P_PLL8, 2, 48, 625 }, |
| { 16000000, P_PLL8, 4, 1, 6 }, |
| { 24000000, P_PLL8, 4, 1, 4 }, |
| { 32000000, P_PLL8, 4, 1, 3 }, |
| { 40000000, P_PLL8, 1, 5, 48 }, |
| { 46400000, P_PLL8, 1, 29, 240 }, |
| { 48000000, P_PLL8, 4, 1, 2 }, |
| { 51200000, P_PLL8, 1, 2, 15 }, |
| { 56000000, P_PLL8, 1, 7, 48 }, |
| { 58982400, P_PLL8, 1, 96, 625 }, |
| { 64000000, P_PLL8, 2, 1, 3 }, |
| { } |
| }; |
| |
| static struct clk_rcg gsbi1_uart_src = { |
| .ns_reg = 0x29d4, |
| .md_reg = 0x29d0, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x29d4, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi1_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi1_uart_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 10, |
| .clkr = { |
| .enable_reg = 0x29d4, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi1_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi1_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi2_uart_src = { |
| .ns_reg = 0x29f4, |
| .md_reg = 0x29f0, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x29f4, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi2_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi2_uart_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 6, |
| .clkr = { |
| .enable_reg = 0x29f4, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi2_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi2_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi3_uart_src = { |
| .ns_reg = 0x2a14, |
| .md_reg = 0x2a10, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2a14, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi3_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi3_uart_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 2, |
| .clkr = { |
| .enable_reg = 0x2a14, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi3_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi3_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi4_uart_src = { |
| .ns_reg = 0x2a34, |
| .md_reg = 0x2a30, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2a34, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi4_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi4_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 26, |
| .clkr = { |
| .enable_reg = 0x2a34, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi4_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi4_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi5_uart_src = { |
| .ns_reg = 0x2a54, |
| .md_reg = 0x2a50, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2a54, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi5_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi5_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 22, |
| .clkr = { |
| .enable_reg = 0x2a54, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi5_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi5_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi6_uart_src = { |
| .ns_reg = 0x2a74, |
| .md_reg = 0x2a70, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2a74, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi6_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi6_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 18, |
| .clkr = { |
| .enable_reg = 0x2a74, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi6_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi6_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi7_uart_src = { |
| .ns_reg = 0x2a94, |
| .md_reg = 0x2a90, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2a94, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi7_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi7_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 14, |
| .clkr = { |
| .enable_reg = 0x2a94, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi7_uart_clk", |
| .parent_names = (const char *[]){ |
| "gsbi7_uart_src", |
| }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi8_uart_src = { |
| .ns_reg = 0x2ab4, |
| .md_reg = 0x2ab0, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2ab4, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi8_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi8_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 10, |
| .clkr = { |
| .enable_reg = 0x2ab4, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi8_uart_clk", |
| .parent_names = (const char *[]){ "gsbi8_uart_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi9_uart_src = { |
| .ns_reg = 0x2ad4, |
| .md_reg = 0x2ad0, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2ad4, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi9_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi9_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 6, |
| .clkr = { |
| .enable_reg = 0x2ad4, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi9_uart_clk", |
| .parent_names = (const char *[]){ "gsbi9_uart_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi10_uart_src = { |
| .ns_reg = 0x2af4, |
| .md_reg = 0x2af0, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2af4, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi10_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi10_uart_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 2, |
| .clkr = { |
| .enable_reg = 0x2af4, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi10_uart_clk", |
| .parent_names = (const char *[]){ "gsbi10_uart_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi11_uart_src = { |
| .ns_reg = 0x2b14, |
| .md_reg = 0x2b10, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2b14, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi11_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi11_uart_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 17, |
| .clkr = { |
| .enable_reg = 0x2b14, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi11_uart_clk", |
| .parent_names = (const char *[]){ "gsbi11_uart_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi12_uart_src = { |
| .ns_reg = 0x2b34, |
| .md_reg = 0x2b30, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_uart, |
| .clkr = { |
| .enable_reg = 0x2b34, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi12_uart_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi12_uart_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 13, |
| .clkr = { |
| .enable_reg = 0x2b34, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi12_uart_clk", |
| .parent_names = (const char *[]){ "gsbi12_uart_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct freq_tbl clk_tbl_gsbi_qup[] = { |
| { 1100000, P_PXO, 1, 2, 49 }, |
| { 5400000, P_PXO, 1, 1, 5 }, |
| { 10800000, P_PXO, 1, 2, 5 }, |
| { 15060000, P_PLL8, 1, 2, 51 }, |
| { 24000000, P_PLL8, 4, 1, 4 }, |
| { 25600000, P_PLL8, 1, 1, 15 }, |
| { 27000000, P_PXO, 1, 0, 0 }, |
| { 48000000, P_PLL8, 4, 1, 2 }, |
| { 51200000, P_PLL8, 1, 2, 15 }, |
| { } |
| }; |
| |
| static struct clk_rcg gsbi1_qup_src = { |
| .ns_reg = 0x29cc, |
| .md_reg = 0x29c8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x29cc, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi1_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi1_qup_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 9, |
| .clkr = { |
| .enable_reg = 0x29cc, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi1_qup_clk", |
| .parent_names = (const char *[]){ "gsbi1_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi2_qup_src = { |
| .ns_reg = 0x29ec, |
| .md_reg = 0x29e8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x29ec, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi2_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi2_qup_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 4, |
| .clkr = { |
| .enable_reg = 0x29ec, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi2_qup_clk", |
| .parent_names = (const char *[]){ "gsbi2_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi3_qup_src = { |
| .ns_reg = 0x2a0c, |
| .md_reg = 0x2a08, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2a0c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi3_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi3_qup_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 0, |
| .clkr = { |
| .enable_reg = 0x2a0c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi3_qup_clk", |
| .parent_names = (const char *[]){ "gsbi3_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi4_qup_src = { |
| .ns_reg = 0x2a2c, |
| .md_reg = 0x2a28, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2a2c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi4_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi4_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 24, |
| .clkr = { |
| .enable_reg = 0x2a2c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi4_qup_clk", |
| .parent_names = (const char *[]){ "gsbi4_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi5_qup_src = { |
| .ns_reg = 0x2a4c, |
| .md_reg = 0x2a48, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2a4c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi5_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi5_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 20, |
| .clkr = { |
| .enable_reg = 0x2a4c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi5_qup_clk", |
| .parent_names = (const char *[]){ "gsbi5_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi6_qup_src = { |
| .ns_reg = 0x2a6c, |
| .md_reg = 0x2a68, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2a6c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi6_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi6_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 16, |
| .clkr = { |
| .enable_reg = 0x2a6c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi6_qup_clk", |
| .parent_names = (const char *[]){ "gsbi6_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi7_qup_src = { |
| .ns_reg = 0x2a8c, |
| .md_reg = 0x2a88, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2a8c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi7_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi7_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 12, |
| .clkr = { |
| .enable_reg = 0x2a8c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi7_qup_clk", |
| .parent_names = (const char *[]){ "gsbi7_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi8_qup_src = { |
| .ns_reg = 0x2aac, |
| .md_reg = 0x2aa8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2aac, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi8_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi8_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 8, |
| .clkr = { |
| .enable_reg = 0x2aac, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi8_qup_clk", |
| .parent_names = (const char *[]){ "gsbi8_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi9_qup_src = { |
| .ns_reg = 0x2acc, |
| .md_reg = 0x2ac8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2acc, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi9_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi9_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 4, |
| .clkr = { |
| .enable_reg = 0x2acc, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi9_qup_clk", |
| .parent_names = (const char *[]){ "gsbi9_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi10_qup_src = { |
| .ns_reg = 0x2aec, |
| .md_reg = 0x2ae8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2aec, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi10_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi10_qup_clk = { |
| .halt_reg = 0x2fd0, |
| .halt_bit = 0, |
| .clkr = { |
| .enable_reg = 0x2aec, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi10_qup_clk", |
| .parent_names = (const char *[]){ "gsbi10_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi11_qup_src = { |
| .ns_reg = 0x2b0c, |
| .md_reg = 0x2b08, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2b0c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi11_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi11_qup_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 15, |
| .clkr = { |
| .enable_reg = 0x2b0c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi11_qup_clk", |
| .parent_names = (const char *[]){ "gsbi11_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gsbi12_qup_src = { |
| .ns_reg = 0x2b2c, |
| .md_reg = 0x2b28, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_gsbi_qup, |
| .clkr = { |
| .enable_reg = 0x2b2c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi12_qup_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi12_qup_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 11, |
| .clkr = { |
| .enable_reg = 0x2b2c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi12_qup_clk", |
| .parent_names = (const char *[]){ "gsbi12_qup_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl clk_tbl_gp[] = { |
| { 9600000, P_CXO, 2, 0, 0 }, |
| { 13500000, P_PXO, 2, 0, 0 }, |
| { 19200000, P_CXO, 1, 0, 0 }, |
| { 27000000, P_PXO, 1, 0, 0 }, |
| { 64000000, P_PLL8, 2, 1, 3 }, |
| { 76800000, P_PLL8, 1, 1, 5 }, |
| { 96000000, P_PLL8, 4, 0, 0 }, |
| { 128000000, P_PLL8, 3, 0, 0 }, |
| { 192000000, P_PLL8, 2, 0, 0 }, |
| { } |
| }; |
| |
| static struct clk_rcg gp0_src = { |
| .ns_reg = 0x2d24, |
| .md_reg = 0x2d00, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_cxo_map, |
| }, |
| .freq_tbl = clk_tbl_gp, |
| .clkr = { |
| .enable_reg = 0x2d24, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp0_src", |
| .parent_names = gcc_pxo_pll8_cxo, |
| .num_parents = 3, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_PARENT_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch gp0_clk = { |
| .halt_reg = 0x2fd8, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x2d24, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp0_clk", |
| .parent_names = (const char *[]){ "gp0_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gp1_src = { |
| .ns_reg = 0x2d44, |
| .md_reg = 0x2d40, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_cxo_map, |
| }, |
| .freq_tbl = clk_tbl_gp, |
| .clkr = { |
| .enable_reg = 0x2d44, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp1_src", |
| .parent_names = gcc_pxo_pll8_cxo, |
| .num_parents = 3, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch gp1_clk = { |
| .halt_reg = 0x2fd8, |
| .halt_bit = 6, |
| .clkr = { |
| .enable_reg = 0x2d44, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp1_clk", |
| .parent_names = (const char *[]){ "gp1_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg gp2_src = { |
| .ns_reg = 0x2d64, |
| .md_reg = 0x2d60, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_cxo_map, |
| }, |
| .freq_tbl = clk_tbl_gp, |
| .clkr = { |
| .enable_reg = 0x2d64, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp2_src", |
| .parent_names = gcc_pxo_pll8_cxo, |
| .num_parents = 3, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch gp2_clk = { |
| .halt_reg = 0x2fd8, |
| .halt_bit = 5, |
| .clkr = { |
| .enable_reg = 0x2d64, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp2_clk", |
| .parent_names = (const char *[]){ "gp2_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch pmem_clk = { |
| .hwcg_reg = 0x25a0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 20, |
| .clkr = { |
| .enable_reg = 0x25a0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "pmem_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg prng_src = { |
| .ns_reg = 0x2e80, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 4, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "prng_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch prng_clk = { |
| .halt_reg = 0x2fd8, |
| .halt_check = BRANCH_HALT_VOTED, |
| .halt_bit = 10, |
| .clkr = { |
| .enable_reg = 0x3080, |
| .enable_mask = BIT(10), |
| .hw.init = &(struct clk_init_data){ |
| .name = "prng_clk", |
| .parent_names = (const char *[]){ "prng_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl clk_tbl_sdc[] = { |
| { 144000, P_PXO, 3, 2, 125 }, |
| { 400000, P_PLL8, 4, 1, 240 }, |
| { 16000000, P_PLL8, 4, 1, 6 }, |
| { 17070000, P_PLL8, 1, 2, 45 }, |
| { 20210000, P_PLL8, 1, 1, 19 }, |
| { 24000000, P_PLL8, 4, 1, 4 }, |
| { 48000000, P_PLL8, 4, 1, 2 }, |
| { 64000000, P_PLL8, 3, 1, 2 }, |
| { 96000000, P_PLL8, 4, 0, 0 }, |
| { 192000000, P_PLL8, 2, 0, 0 }, |
| { } |
| }; |
| |
| static struct clk_rcg sdc1_src = { |
| .ns_reg = 0x282c, |
| .md_reg = 0x2828, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_sdc, |
| .clkr = { |
| .enable_reg = 0x282c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc1_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch sdc1_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 6, |
| .clkr = { |
| .enable_reg = 0x282c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc1_clk", |
| .parent_names = (const char *[]){ "sdc1_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg sdc2_src = { |
| .ns_reg = 0x284c, |
| .md_reg = 0x2848, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_sdc, |
| .clkr = { |
| .enable_reg = 0x284c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc2_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch sdc2_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 5, |
| .clkr = { |
| .enable_reg = 0x284c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc2_clk", |
| .parent_names = (const char *[]){ "sdc2_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg sdc3_src = { |
| .ns_reg = 0x286c, |
| .md_reg = 0x2868, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_sdc, |
| .clkr = { |
| .enable_reg = 0x286c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc3_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch sdc3_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 4, |
| .clkr = { |
| .enable_reg = 0x286c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc3_clk", |
| .parent_names = (const char *[]){ "sdc3_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg sdc4_src = { |
| .ns_reg = 0x288c, |
| .md_reg = 0x2888, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_sdc, |
| .clkr = { |
| .enable_reg = 0x288c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc4_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch sdc4_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 3, |
| .clkr = { |
| .enable_reg = 0x288c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc4_clk", |
| .parent_names = (const char *[]){ "sdc4_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg sdc5_src = { |
| .ns_reg = 0x28ac, |
| .md_reg = 0x28a8, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_sdc, |
| .clkr = { |
| .enable_reg = 0x28ac, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc5_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch sdc5_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 2, |
| .clkr = { |
| .enable_reg = 0x28ac, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc5_clk", |
| .parent_names = (const char *[]){ "sdc5_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl clk_tbl_tsif_ref[] = { |
| { 105000, P_PXO, 1, 1, 256 }, |
| { } |
| }; |
| |
| static struct clk_rcg tsif_ref_src = { |
| .ns_reg = 0x2710, |
| .md_reg = 0x270c, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 16, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_tsif_ref, |
| .clkr = { |
| .enable_reg = 0x2710, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "tsif_ref_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch tsif_ref_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 5, |
| .clkr = { |
| .enable_reg = 0x2710, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "tsif_ref_clk", |
| .parent_names = (const char *[]){ "tsif_ref_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl clk_tbl_usb[] = { |
| { 60000000, P_PLL8, 1, 5, 32 }, |
| { } |
| }; |
| |
| static struct clk_rcg usb_hs1_xcvr_src = { |
| .ns_reg = 0x290c, |
| .md_reg = 0x2908, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x290c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs1_xcvr_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch usb_hs1_xcvr_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 0, |
| .clkr = { |
| .enable_reg = 0x290c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs1_xcvr_clk", |
| .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg usb_hs3_xcvr_src = { |
| .ns_reg = 0x370c, |
| .md_reg = 0x3708, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x370c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs3_xcvr_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch usb_hs3_xcvr_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 30, |
| .clkr = { |
| .enable_reg = 0x370c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs3_xcvr_clk", |
| .parent_names = (const char *[]){ "usb_hs3_xcvr_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg usb_hs4_xcvr_src = { |
| .ns_reg = 0x372c, |
| .md_reg = 0x3728, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x372c, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs4_xcvr_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static struct clk_branch usb_hs4_xcvr_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 2, |
| .clkr = { |
| .enable_reg = 0x372c, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs4_xcvr_clk", |
| .parent_names = (const char *[]){ "usb_hs4_xcvr_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg usb_hsic_xcvr_fs_src = { |
| .ns_reg = 0x2928, |
| .md_reg = 0x2924, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x2928, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hsic_xcvr_fs_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; |
| |
| static struct clk_branch usb_hsic_xcvr_fs_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 2, |
| .clkr = { |
| .enable_reg = 0x2928, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hsic_xcvr_fs_clk", |
| .parent_names = usb_hsic_xcvr_fs_src_p, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hsic_system_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 24, |
| .clkr = { |
| .enable_reg = 0x292c, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .parent_names = usb_hsic_xcvr_fs_src_p, |
| .num_parents = 1, |
| .name = "usb_hsic_system_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hsic_hsic_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 19, |
| .clkr = { |
| .enable_reg = 0x2b44, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .parent_names = (const char *[]){ "pll14_vote" }, |
| .num_parents = 1, |
| .name = "usb_hsic_hsic_clk", |
| .ops = &clk_branch_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hsic_hsio_cal_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 23, |
| .clkr = { |
| .enable_reg = 0x2b48, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hsic_hsio_cal_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg usb_fs1_xcvr_fs_src = { |
| .ns_reg = 0x2968, |
| .md_reg = 0x2964, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x2968, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs1_xcvr_fs_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; |
| |
| static struct clk_branch usb_fs1_xcvr_fs_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 15, |
| .clkr = { |
| .enable_reg = 0x2968, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs1_xcvr_fs_clk", |
| .parent_names = usb_fs1_xcvr_fs_src_p, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_fs1_system_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 16, |
| .clkr = { |
| .enable_reg = 0x296c, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .parent_names = usb_fs1_xcvr_fs_src_p, |
| .num_parents = 1, |
| .name = "usb_fs1_system_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_rcg usb_fs2_xcvr_fs_src = { |
| .ns_reg = 0x2988, |
| .md_reg = 0x2984, |
| .mn = { |
| .mnctr_en_bit = 8, |
| .mnctr_reset_bit = 7, |
| .mnctr_mode_shift = 5, |
| .n_val_shift = 16, |
| .m_val_shift = 16, |
| .width = 8, |
| }, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 2, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_map, |
| }, |
| .freq_tbl = clk_tbl_usb, |
| .clkr = { |
| .enable_reg = 0x2988, |
| .enable_mask = BIT(11), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs2_xcvr_fs_src", |
| .parent_names = gcc_pxo_pll8, |
| .num_parents = 2, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| } |
| }; |
| |
| static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; |
| |
| static struct clk_branch usb_fs2_xcvr_fs_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 12, |
| .clkr = { |
| .enable_reg = 0x2988, |
| .enable_mask = BIT(9), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs2_xcvr_fs_clk", |
| .parent_names = usb_fs2_xcvr_fs_src_p, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_fs2_system_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 13, |
| .clkr = { |
| .enable_reg = 0x298c, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs2_system_clk", |
| .parent_names = usb_fs2_xcvr_fs_src_p, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch ce1_core_clk = { |
| .hwcg_reg = 0x2724, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd4, |
| .halt_bit = 27, |
| .clkr = { |
| .enable_reg = 0x2724, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ce1_core_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch ce1_h_clk = { |
| .halt_reg = 0x2fd4, |
| .halt_bit = 1, |
| .clkr = { |
| .enable_reg = 0x2720, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ce1_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch dma_bam_h_clk = { |
| .hwcg_reg = 0x25c0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 12, |
| .clkr = { |
| .enable_reg = 0x25c0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "dma_bam_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi1_h_clk = { |
| .hwcg_reg = 0x29c0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fcc, |
| .halt_bit = 11, |
| .clkr = { |
| .enable_reg = 0x29c0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi1_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi2_h_clk = { |
| .hwcg_reg = 0x29e0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fcc, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x29e0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi2_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi3_h_clk = { |
| .hwcg_reg = 0x2a00, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fcc, |
| .halt_bit = 3, |
| .clkr = { |
| .enable_reg = 0x2a00, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi3_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi4_h_clk = { |
| .hwcg_reg = 0x2a20, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 27, |
| .clkr = { |
| .enable_reg = 0x2a20, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi4_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi5_h_clk = { |
| .hwcg_reg = 0x2a40, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 23, |
| .clkr = { |
| .enable_reg = 0x2a40, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi5_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi6_h_clk = { |
| .hwcg_reg = 0x2a60, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 19, |
| .clkr = { |
| .enable_reg = 0x2a60, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi6_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi7_h_clk = { |
| .hwcg_reg = 0x2a80, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 15, |
| .clkr = { |
| .enable_reg = 0x2a80, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi7_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi8_h_clk = { |
| .hwcg_reg = 0x2aa0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 11, |
| .clkr = { |
| .enable_reg = 0x2aa0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi8_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi9_h_clk = { |
| .hwcg_reg = 0x2ac0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x2ac0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi9_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi10_h_clk = { |
| .hwcg_reg = 0x2ae0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd0, |
| .halt_bit = 3, |
| .clkr = { |
| .enable_reg = 0x2ae0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi10_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi11_h_clk = { |
| .hwcg_reg = 0x2b00, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd4, |
| .halt_bit = 18, |
| .clkr = { |
| .enable_reg = 0x2b00, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi11_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gsbi12_h_clk = { |
| .hwcg_reg = 0x2b20, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd4, |
| .halt_bit = 14, |
| .clkr = { |
| .enable_reg = 0x2b20, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "gsbi12_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch tsif_h_clk = { |
| .hwcg_reg = 0x2700, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fd4, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x2700, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "tsif_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_fs1_h_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 17, |
| .clkr = { |
| .enable_reg = 0x2960, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs1_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_fs2_h_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 14, |
| .clkr = { |
| .enable_reg = 0x2980, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_fs2_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hs1_h_clk = { |
| .hwcg_reg = 0x2900, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 1, |
| .clkr = { |
| .enable_reg = 0x2900, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs1_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hs3_h_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 31, |
| .clkr = { |
| .enable_reg = 0x3700, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs3_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hs4_h_clk = { |
| .halt_reg = 0x2fc8, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x3720, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hs4_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch usb_hsic_h_clk = { |
| .halt_reg = 0x2fcc, |
| .halt_bit = 28, |
| .clkr = { |
| .enable_reg = 0x2920, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "usb_hsic_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sdc1_h_clk = { |
| .hwcg_reg = 0x2820, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 11, |
| .clkr = { |
| .enable_reg = 0x2820, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc1_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sdc2_h_clk = { |
| .hwcg_reg = 0x2840, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 10, |
| .clkr = { |
| .enable_reg = 0x2840, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc2_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sdc3_h_clk = { |
| .hwcg_reg = 0x2860, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 9, |
| .clkr = { |
| .enable_reg = 0x2860, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc3_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sdc4_h_clk = { |
| .hwcg_reg = 0x2880, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 8, |
| .clkr = { |
| .enable_reg = 0x2880, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc4_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sdc5_h_clk = { |
| .hwcg_reg = 0x28a0, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fc8, |
| .halt_bit = 7, |
| .clkr = { |
| .enable_reg = 0x28a0, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sdc5_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch adm0_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_check = BRANCH_HALT_VOTED, |
| .halt_bit = 14, |
| .clkr = { |
| .enable_reg = 0x3080, |
| .enable_mask = BIT(2), |
| .hw.init = &(struct clk_init_data){ |
| .name = "adm0_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch adm0_pbus_clk = { |
| .hwcg_reg = 0x2208, |
| .hwcg_bit = 6, |
| .halt_reg = 0x2fdc, |
| .halt_check = BRANCH_HALT_VOTED, |
| .halt_bit = 13, |
| .clkr = { |
| .enable_reg = 0x3080, |
| .enable_mask = BIT(3), |
| .hw.init = &(struct clk_init_data){ |
| .name = "adm0_pbus_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct freq_tbl clk_tbl_ce3[] = { |
| { 48000000, P_PLL8, 8 }, |
| { 100000000, P_PLL3, 12 }, |
| { 120000000, P_PLL3, 10 }, |
| { } |
| }; |
| |
| static struct clk_rcg ce3_src = { |
| .ns_reg = 0x36c0, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 4, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_pll3_map, |
| }, |
| .freq_tbl = clk_tbl_ce3, |
| .clkr = { |
| .enable_reg = 0x2c08, |
| .enable_mask = BIT(7), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ce3_src", |
| .parent_names = gcc_pxo_pll8_pll3, |
| .num_parents = 3, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch ce3_core_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_bit = 5, |
| .clkr = { |
| .enable_reg = 0x36c4, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ce3_core_clk", |
| .parent_names = (const char *[]){ "ce3_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch ce3_h_clk = { |
| .halt_reg = 0x2fc4, |
| .halt_bit = 16, |
| .clkr = { |
| .enable_reg = 0x36c4, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "ce3_h_clk", |
| .parent_names = (const char *[]){ "ce3_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static const struct freq_tbl clk_tbl_sata_ref[] = { |
| { 48000000, P_PLL8, 8, 0, 0 }, |
| { 100000000, P_PLL3, 12, 0, 0 }, |
| { } |
| }; |
| |
| static struct clk_rcg sata_clk_src = { |
| .ns_reg = 0x2c08, |
| .p = { |
| .pre_div_shift = 3, |
| .pre_div_width = 4, |
| }, |
| .s = { |
| .src_sel_shift = 0, |
| .parent_map = gcc_pxo_pll8_pll3_map, |
| }, |
| .freq_tbl = clk_tbl_sata_ref, |
| .clkr = { |
| .enable_reg = 0x2c08, |
| .enable_mask = BIT(7), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_clk_src", |
| .parent_names = gcc_pxo_pll8_pll3, |
| .num_parents = 3, |
| .ops = &clk_rcg_ops, |
| .flags = CLK_SET_RATE_GATE, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sata_rxoob_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_bit = 26, |
| .clkr = { |
| .enable_reg = 0x2c0c, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_rxoob_clk", |
| .parent_names = (const char *[]){ "sata_clk_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sata_pmalive_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_bit = 25, |
| .clkr = { |
| .enable_reg = 0x2c10, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_pmalive_clk", |
| .parent_names = (const char *[]){ "sata_clk_src" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sata_phy_ref_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_bit = 24, |
| .clkr = { |
| .enable_reg = 0x2c14, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_phy_ref_clk", |
| .parent_names = (const char *[]){ "pxo" }, |
| .num_parents = 1, |
| .ops = &clk_branch_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sata_a_clk = { |
| .halt_reg = 0x2fc0, |
| .halt_bit = 12, |
| .clkr = { |
| .enable_reg = 0x2c20, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_a_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sata_h_clk = { |
| .halt_reg = 0x2fdc, |
| .halt_bit = 27, |
| .clkr = { |
| .enable_reg = 0x2c00, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sata_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch sfab_sata_s_h_clk = { |
| .halt_reg = 0x2fc4, |
| .halt_bit = 14, |
| .clkr = { |
| .enable_reg = 0x2480, |
| .enable_mask = BIT(4), |
| .hw.init = &(struct clk_init_data){ |
| .name = "sfab_sata_s_h_clk", |
| .ops = &clk_branch_ops, |
| .flags = CLK_IS_ROOT, |
| |