u-boot-imx/board/nest/onyx/imximage_onyx.cfg

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */

#define __ASSEMBLY__
#include <config.h>

/* image version */

IMAGE_VERSION 2

/*
 * Boot Device : one of
 * spi/sd/nand/onenand, qspi/nor
 */

#ifdef CONFIG_SYS_BOOT_QSPI
BOOT_FROM	qspi
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
BOOT_FROM	nor
#else
BOOT_FROM	sd
#endif

#ifdef CONFIG_USE_PLUGIN
/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
PLUGIN	board/nest/onyx/plugin.bin 0x00907000
#else

#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

/* Set Boot-Time ARM and DDR Clocks */
DATA 4 0x020c4010 0x00000007
DATA 4 0x020C4014 0x00018908
CHECK_BITS_CLR 4 0x020c4048 0xffffffff

/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff

/*=============================================================================	*/
/* IOMUX	*/
/*=============================================================================	*/
/*DDR IO TYPE:	*/
DATA 4 0x020E04B4 0x00080000	/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE*/
DATA 4 0x020E04AC 0x00000000	/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE*/
	
/*CLOCK:	*/
DATA 4 0x020E027C 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P*/
	
/*Control and Address:	*/
DATA 4 0x020E0250 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS*/
DATA 4 0x020E024C 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS*/
DATA 4 0x020E0490 0x00000020	/* IOMUXC_SW_PAD_CTL_GRP_ADDDS*/
DATA 4 0x020E0288 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET*/
DATA 4 0x020E0270 0x00000000	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
DATA 4 0x020E0260 0x00000000	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0*/
DATA 4 0x020E0264 0x00000000	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1*/
DATA 4 0x020E04A0 0x00000020	/* IOMUXC_SW_PAD_CTL_GRP_CTLDS*/
	
/*Data Strobes:	*/
DATA 4 0x020E0494 0x00020000	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/
DATA 4 0x020E0280 0x00003020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P*/
DATA 4 0x020E0284 0x00003020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P*/
	
/*Data:	*/
DATA 4 0x020E04B0 0x00020000	/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/
DATA 4 0x020E0498 0x00000020	/* IOMUXC_SW_PAD_CTL_GRP_B0DS*/
DATA 4 0x020E04A4 0x00000020	/* IOMUXC_SW_PAD_CTL_GRP_B1DS*/
DATA 4 0x020E0244 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/
DATA 4 0x020E0248 0x00000020	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/
	
/*=============================================================================	*/
/* DDR Controller Registers	*/
/*=============================================================================	*/
/* Manufacturer:	ISSI*/
/* Device Part Number:	IS43LD16640A-25BLI */
/* Clock Freq.: 	400MHz*/
/* Density per CS in Gb: 	1*/
/* Chip Selects used:	1*/
/* Total DRAM density (Gb)	2*/
/* Number of Banks:	8*/
/* Row address:    	14*/
/* Column address: 	10*/
/* Data bus width	16*/
/*=============================================================================	*/
DATA 4 0x021B001C 0x00008000	/* [MMDC_MDSCR] Set the Configuration request bit during MMDC set up*/
DATA 4 0x021B085C 0x1B4700C7	/* [MMDC_MPZQLP2CTL] LPDDR2 ZQ params, values based on JEDEC standard */
	
/*======================================================	*/
/*Calibrations:	*/
/*======================================================	*/
DATA 4 0x021B0800 0xA1390003	/* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.*/
	
DATA 4 0x021B0890 0x00470000 	/* [MMDC_MPPDCMPR2] MMDC PHY CA delay-line Configuration*/
	
DATA 4 0x021B08B8 0x00000800	/* [MMDC_MPMUR0] MMDC PHY Measure Unit Register*/
	
DATA 4 0x021b0848 0x4040484F	/* [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register*/
DATA 4 0x021b0850 0x40405247	/* [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register*/
	
DATA 4 0x021B081C 0x33333333	/* [MMDC_MPRDDQBY0DL] MMDC PHY Read DQ Byte0 Delay Register*/
DATA 4 0x021B0820 0x33333333	/* [MMDC_MPRDDQBY1DL] MMDC PHY Read DQ Byte1 Delay Register*/
	
DATA 4 0x021B082C 0xf3333333	/* [MMDC_MPWRDQBY0DL] MMDC PHY Write DQ Byte0 Delay Register*/
DATA 4 0x021B0830 0xf3333333 	/* [MMDC_MPWRDQBY1DL] MMDC PHY Write DQ Byte1 Delay Register*/
	
DATA 4 0x021B08C0 0x00922012	/* [MMDC_MPDCCR] MMDC Duty Cycle Control Register*/
	
/* Complete calibration by forced measurement:	*/
DATA 4 0x021B08b8 0x00000800	/* [MMDC_MPMUR0] MMDC PHY Measure Unit Register*/
	
/*======================================================	*/
/*MMDC init:	*/
/*======================================================	*/
DATA 4 0x021B0004 0x00020012	/* MMDC0_MDPDC */
DATA 4 0x021B0008 0x00000000	/* MMDC0_MDOTC*/
DATA 4 0x021B000C 0x33374133	/* MMDC0_MDCFG0*/
DATA 4 0x021B0010 0x00100A82	/* MMDC0_MDCFG1*/
DATA 4 0x021B0014 0x00000093	/* MMDC0_MDCFG2*/
DATA 4 0x021B0018 0x00201748	/* MMDC0_MDMISC*/
DATA 4 0x021B002C 0x0F9F26D2	/* MMDC0_MDRWD; recommend to maintain the default values*/
DATA 4 0x021B0030 0x009F0E10	/* MMDC0_MDOR*/
DATA 4 0x021B0038 0x00190778	/* MMDC0_MDCFG3LP*/
DATA 4 0x021B0040 0x00000047	/* CS0_END */
DATA 4 0x021B0000 0x83100000	/* MMDC0_MDCTL*/
	
/*======================================================	*/
/*Optional Precharge all command per JEDEC:*/
/*The memory controller may optionally issue a Precharge-All command (for LPDDR2-SX) or Preactive (for LPDDR2-N) prior to the MRW Reset command.*/
/*======================================================	*/

DATA 4 0x021b001c 0x00008010	/* precharge all command */

/* Mode register writes for CS0	*/
DATA 4 0x021b001c 0x003F8030	/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)*/
DATA 4 0x021b001c 0xFF0A8030	/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)*/
DATA 4 0x021B001C 0x82018030	/* MMDC0_MDSCR, MR3 write, CS0*/
DATA 4 0x021B001C 0x04028030	/* MMDC0_MDSCR, MR1 write, CS0*/
DATA 4 0x021B001C 0x04038030	/* MMDC0_MDSCR, MR0 write, CS0*/
DATA 4 0x021b083C 0xA0000000	/* Reset read fifo pointer in the MMDC and disable DQS gate for LPDDR2*/
DATA 4 0x021b083C 0xA0000000	/* twice to fully reset the read FIFO pointer*/
	
/* Mode register writes for CS, commented out automatically if only one chip select used	*/
/*DATA 4 0x021b001c 0x003F8038	# MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset)*/
/*DATA 4 0x021b001c 0xFF0A8038	# MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code)*/
/*DATA 4 0x021B001C 0x82018038	# MMDC0_MDSCR, MR3 write, CS0*/
/*DATA 4 0x021B001C 0x04028038	# MMDC0_MDSCR, MR1 write, CS0*/
/*DATA 4 0x021B001C 0x01038038	# MMDC0_MDSCR, MR0 write, CS0*/
	
/*final DDR setup, before operation start:	*/
DATA 4 0x021B0020 0x00001800	/* MMDC0_MDREF*/
DATA 4 0x021B0818 0x00000000	/* MMDC_MPODTCTRL, ensure PHY ODT control register is cleared*/
DATA 4 0x021B0800 0xA1310003	/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration*/
DATA 4 0x021B0004 0x00025552	/* MMDC0_MDPDC now SDCTL power down enabled*/
DATA 4 0x021B0404 0x00011006	/* MMDC0_MAPSR ADOPT power down enabled*/
DATA 4 0x021B001C 0x00000000	/* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)*/
#endif