blob: 841f9c39f060041c378977c784a92b429f6889bd [file] [log] [blame]
/*
* Copyright (C) 2017 Nest labs, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/* Mirrored by reset-decoder */
/*
* LPGPR register field descriptions
*
* bits - description
* 31..16 - U-Boot Magic Value (0xB001)
* A signature used to guard against parsing invalid data
* 15 - Reset Cause Written
* Since this function causes a cold reset upon detecting a warm reset,
* this bit is needed to signal that we've already written state to
* SNVS, and thus should continue booting.
* 14 - Watchdog State
* Enumerated in wdog_state, this value is undefined if the reset
* cause in SRC_SRSR is not WDOG (0x10).
* 13..12 - PMIC state
* Enumerated in struct pmic_state
* 11..3 - SRC_SRSR
* The lowest 9 bits of the SRC_SRSR register, with warm_boot (bit 16)
* moved to bit 1
* 2..0 - Bootcount
*/
#define LPGPR_BOOTCOUNT_SHIFT 0
#define LPGPR_BOOTCOUNT_MASK (0x7 << LPGPR_BOOTCOUNT_SHIFT)
#define LPGPR_SRSR_SHIFT 3
#define LPGPR_SRSR_MASK (0x1FF << LPGPR_SRSR_SHIFT)
#define LPGPR_PMIC_STATE_SHIFT 12
#define LPGPR_PMIC_STATE_MASK (0x3UL << LPGPR_PMIC_STATE_SHIFT)
#define LPGPR_WRSR_SHIFT 14
#define LPGPR_WRSR_MASK (0x1UL << LPGPR_WRSR_SHIFT)
/* The warm_boot bit is at bit 16 in SRC_SRSR. Shift it down
* to bit 1, which is always set to zero, to save space */
#define LPGPR_SRSR_WARM_BOOT_ADJ 15
#define LPGPR_SRSR_WARM_BOOT_MASK 2
#define LPGPR_RESET_CAUSE_WRITTEN (1UL << 15)
#define PMIC_DEFAULT_STBYDLY_VALUE 0x1
#define PMIC_NON_DEFAULT_STBYDLY_VALUE 0x2
#define PMIC_DEFAULT_MEMA_VALUE 0x00
#define PMIC_NON_DEFAULT_MEMA_VALUE 0xDE
#define LPGPR_UBOOT_MAGIC_SHIFT 16
#define LPGPR_UBOOT_MAGIC_MASK (0xFFFFUL << LPGPR_UBOOT_MAGIC_SHIFT)
#define LPGPR_UBOOT_MAGIC_VALUE 0xB001
enum pmic_state {
resurrected, /* was without power for >20 s */
reset,
still_on,
unknown
};
enum wdog_state {
sftw, /* Software Reset (SRS) */
tout /* Timeout */
};