|  | Qualcomm adreno/snapdragon GPU | 
|  |  | 
|  | Required properties: | 
|  | - compatible: "qcom,adreno-3xx" | 
|  | - reg: Physical base address and length of the controller's registers. | 
|  | - interrupts: The interrupt signal from the gpu. | 
|  | - clocks: device clocks | 
|  | See ../clocks/clock-bindings.txt for details. | 
|  | - clock-names: the following clocks are required: | 
|  | * "core_clk" | 
|  | * "iface_clk" | 
|  | * "mem_iface_clk" | 
|  | - qcom,chipid: gpu chip-id.  Note this may become optional for future | 
|  | devices if we can reliably read the chipid from hw | 
|  | - qcom,gpu-pwrlevels: list of operating points | 
|  | - compatible: "qcom,gpu-pwrlevels" | 
|  | - for each qcom,gpu-pwrlevel: | 
|  | - qcom,gpu-freq: requested gpu clock speed | 
|  | - NOTE: downstream android driver defines additional parameters to | 
|  | configure memory bandwidth scaling per OPP. | 
|  |  | 
|  | Example: | 
|  |  | 
|  | / { | 
|  | ... | 
|  |  | 
|  | gpu: qcom,kgsl-3d0@4300000 { | 
|  | compatible = "qcom,adreno-3xx"; | 
|  | reg = <0x04300000 0x20000>; | 
|  | reg-names = "kgsl_3d0_reg_memory"; | 
|  | interrupts = <GIC_SPI 80 0>; | 
|  | interrupt-names = "kgsl_3d0_irq"; | 
|  | clock-names = | 
|  | "core_clk", | 
|  | "iface_clk", | 
|  | "mem_iface_clk"; | 
|  | clocks = | 
|  | <&mmcc GFX3D_CLK>, | 
|  | <&mmcc GFX3D_AHB_CLK>, | 
|  | <&mmcc MMSS_IMEM_AHB_CLK>; | 
|  | qcom,chipid = <0x03020100>; | 
|  | qcom,gpu-pwrlevels { | 
|  | compatible = "qcom,gpu-pwrlevels"; | 
|  | qcom,gpu-pwrlevel@0 { | 
|  | qcom,gpu-freq = <450000000>; | 
|  | }; | 
|  | qcom,gpu-pwrlevel@1 { | 
|  | qcom,gpu-freq = <27000000>; | 
|  | }; | 
|  | }; | 
|  | }; | 
|  | }; |