| /* |
| * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/input/input.h> |
| #include "imx7d.dtsi" |
| |
| / { |
| model = "Freescale i.MX7 DDR3 12x12 ARM2 Board"; |
| compatible = "fsl,imx7d-12x12-ddr3-arm2", "fsl,imx7d"; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| status = "okay"; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_keys>; |
| |
| volume-up { |
| label = "Volume Up"; |
| gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEUP>; |
| }; |
| |
| volume-down { |
| label = "Volume Down"; |
| gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEDOWN>; |
| }; |
| }; |
| |
| pxp_v4l2_out { |
| compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; |
| status = "okay"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_sd3_vmmc: sd3_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "VCC_SD3"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usb_otg1_vbus: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usb_otg2_vbus: regulator@1 { |
| compatible = "regulator-fixed"; |
| reg = <1>; |
| regulator-name = "usb_otg2_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_vref_1v8: regulator@2 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vref-1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| reg_can1_3v3: can1-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can1-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_can2_3v3: can2-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can2-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x80000000>; |
| }; |
| }; |
| |
| &adc1 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &cpu0 { |
| arm-supply = <&sw1a_reg>; |
| }; |
| |
| &ecspi4 { |
| fsl,spi-num-chipselects = <4>; |
| cs-gpios = <&gpio5 3 0>, <&gpio5 4 0>, <&gpio5 5 0>, <&gpio5 6 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; |
| status = "disabled"; |
| |
| flash: m25p80@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "st,m25p32"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| }; |
| }; |
| |
| &epxp { |
| status = "okay"; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_can1_3v3>; |
| status = "disabled"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can2_3v3>; |
| status = "disabled"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1_1>; |
| status = "okay"; |
| |
| pmic: pfuze3000@08 { |
| compatible = "fsl,pfuze3000"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1a { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| /* use sw1c_reg to align with pfuze100/pfuze200 */ |
| sw1c_reg: sw1b { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3 { |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1650000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vldo1 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen2_reg: vldo2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vccsd { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: v33 { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vldo3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vldo4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3_1>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| |
| imx7d-12x12-ddr3-arm2 { |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 |
| MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 |
| MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 |
| >; |
| }; |
| |
| pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { |
| fsl,pins = < |
| MX7D_PAD_SD1_CLK__GPIO5_IO3 0x2 |
| MX7D_PAD_SD1_CMD__GPIO5_IO4 0x2 |
| MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x2 |
| MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x2 |
| >; |
| }; |
| |
| pinctrl_ecspi4_1: ecspi4grp-1 { |
| fsl,pins = < |
| MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x2 |
| MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x2 |
| MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x2 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x59 |
| MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x59 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x59 |
| MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x59 |
| >; |
| }; |
| |
| pinctrl_gpio_keys: gpio_keysgrp { |
| fsl,pins = < |
| MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x32 |
| MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x32 |
| >; |
| }; |
| |
| pinctrl_i2c3_1: i2c3grp-1 { |
| fsl,pins = < |
| MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f |
| MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c4_1: i2c4grp-1 { |
| fsl,pins = < |
| MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f |
| MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_lcdif_dat: lcdifdatgrp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x4001b0b0 |
| MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x4001b0b0 |
| MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x4001b0b0 |
| MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x4001b0b0 |
| MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x4001b0b0 |
| MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x4001b0b0 |
| MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x4001b0b0 |
| MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x4001b0b0 |
| MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x4001b0b0 |
| MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x4001b0b0 |
| >; |
| }; |
| |
| pinctrl_lcdif_ctrl: lcdifctrlgrp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x4001b0b0 |
| MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x4001b0b0 |
| MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x4001b0b0 |
| MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x4001b0b0 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 |
| >; |
| }; |
| |
| pinctrl_uart1_1: uart1grp-1 { |
| fsl,pins = < |
| MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 |
| MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_usdhc2_1: usdhc2grp-1 { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x59 |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x19 |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 |
| MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x59 |
| MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x59 |
| MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x59 |
| MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x59 |
| >; |
| }; |
| |
| pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5a |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1a |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a |
| MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5a |
| MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5a |
| MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5a |
| MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5a |
| >; |
| }; |
| |
| pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5b |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1b |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b |
| MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5b |
| MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5b |
| MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5b |
| MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5b |
| >; |
| }; |
| |
| pinctrl_usdhc3_1: usdhc3grp-1 { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x19 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
| >; |
| }; |
| }; |
| }; |
| |
| &iomuxc_lpsr { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_2>; |
| |
| imx7d-12x12-ddr3-arm2 { |
| pinctrl_hog_2: hoggrp-2 { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */ |
| MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */ |
| MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x80000000 |
| >; |
| }; |
| |
| pinctrl_i2c1_1: i2c1grp-1 { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f |
| MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2_1: i2c2grp-1 { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x4000007f |
| MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x4000007f |
| >; |
| }; |
| }; |
| }; |
| |
| &lcdif { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcdif_dat |
| &pinctrl_lcdif_ctrl>; |
| display = <&display0>; |
| status = "okay"; |
| |
| display0: display { |
| bits-per-pixel = <16>; |
| bus-width = <24>; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| timing0: timing0 { |
| clock-frequency = <33500000>; |
| hactive = <800>; |
| vactive = <480>; |
| hback-porch = <89>; |
| hfront-porch = <164>; |
| vback-porch = <23>; |
| vfront-porch = <10>; |
| hsync-len = <10>; |
| vsync-len = <10>; |
| hsync-active = <0>; |
| vsync-active = <0>; |
| de-active = <1>; |
| pixelclk-active = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &sdma { |
| status = "okay"; |
| }; |
| |
| &pcie { |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1>; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1_1>; |
| status = "okay"; |
| }; |
| |
| &usbh { |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| vbus-supply = <®_usb_otg2_vbus>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2_1>; |
| pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; |
| assigned-clocks = <&clks IMX7D_USDHC2_ROOT_CLK>; |
| assigned-clocks-rates = <400000000>; |
| bus-width = <8>; |
| tuning-step = <2>; |
| non-removable; |
| keep-power-in-suspend; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3_1>; |
| vmmc-supply = <®_sd3_vmmc>; |
| cd-gpios = <&gpio1 14>; |
| wp-gpios = <&gpio1 15>; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| no-1-8-v; |
| status = "okay"; |
| }; |
