| /** |
| * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer |
| * |
| * Copyright (C) 2014 Chen-Zhi (Roger Chen) |
| * |
| * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <linux/stmmac.h> |
| #include <linux/bitops.h> |
| #include <linux/clk.h> |
| #include <linux/phy.h> |
| #include <linux/of_net.h> |
| #include <linux/gpio.h> |
| #include <linux/module.h> |
| #include <linux/of_gpio.h> |
| #include <linux/of_device.h> |
| #include <linux/platform_device.h> |
| #include <linux/regulator/consumer.h> |
| #include <linux/delay.h> |
| #include <linux/mfd/syscon.h> |
| #include <linux/regmap.h> |
| #include <linux/pm_runtime.h> |
| |
| #include "stmmac_platform.h" |
| |
| struct rk_priv_data; |
| struct rk_gmac_ops { |
| void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay); |
| void (*set_to_rmii)(struct rk_priv_data *bsp_priv); |
| void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); |
| void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); |
| }; |
| |
| struct rk_priv_data { |
| struct platform_device *pdev; |
| int phy_iface; |
| struct regulator *regulator; |
| bool suspended; |
| const struct rk_gmac_ops *ops; |
| |
| bool clk_enabled; |
| bool clock_input; |
| |
| struct clk *clk_mac; |
| struct clk *gmac_clkin; |
| struct clk *mac_clk_rx; |
| struct clk *mac_clk_tx; |
| struct clk *clk_mac_ref; |
| struct clk *clk_mac_refout; |
| struct clk *aclk_mac; |
| struct clk *pclk_mac; |
| |
| int tx_delay; |
| int rx_delay; |
| |
| struct regmap *grf; |
| }; |
| |
| #define HIWORD_UPDATE(val, mask, shift) \ |
| ((val) << (shift) | (mask) << ((shift) + 16)) |
| |
| #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) |
| #define GRF_CLR_BIT(nr) (BIT(nr+16)) |
| |
| #define RK3228_GRF_MAC_CON0 0x0900 |
| #define RK3228_GRF_MAC_CON1 0x0904 |
| |
| /* RK3228_GRF_MAC_CON0 */ |
| #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
| #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
| |
| /* RK3228_GRF_MAC_CON1 */ |
| #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ |
| (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) |
| #define RK3228_GMAC_PHY_INTF_SEL_RMII \ |
| (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) |
| #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) |
| #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
| #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) |
| #define RK3228_GMAC_SPEED_100M GRF_BIT(2) |
| #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) |
| #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) |
| #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) |
| #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) |
| #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) |
| #define RK3228_GMAC_RMII_MODE GRF_BIT(10) |
| #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) |
| #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) |
| #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
| #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) |
| #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) |
| |
| static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_PHY_INTF_SEL_RGMII | |
| RK3228_GMAC_RMII_MODE_CLR | |
| RK3228_GMAC_RXCLK_DLY_ENABLE | |
| RK3228_GMAC_TXCLK_DLY_ENABLE); |
| |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, |
| RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | |
| RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); |
| } |
| |
| static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_PHY_INTF_SEL_RMII | |
| RK3228_GMAC_RMII_MODE); |
| |
| /* set MAC to RMII mode */ |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); |
| } |
| |
| static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_CLK_2_5M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_CLK_25M); |
| else if (speed == 1000) |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_CLK_125M); |
| else |
| dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); |
| } |
| |
| static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_RMII_CLK_2_5M | |
| RK3228_GMAC_SPEED_10M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, |
| RK3228_GMAC_RMII_CLK_25M | |
| RK3228_GMAC_SPEED_100M); |
| else |
| dev_err(dev, "unknown speed value for RMII! speed=%d", speed); |
| } |
| |
| static const struct rk_gmac_ops rk3228_ops = { |
| .set_to_rgmii = rk3228_set_to_rgmii, |
| .set_to_rmii = rk3228_set_to_rmii, |
| .set_rgmii_speed = rk3228_set_rgmii_speed, |
| .set_rmii_speed = rk3228_set_rmii_speed, |
| }; |
| |
| #define RK3288_GRF_SOC_CON1 0x0248 |
| #define RK3288_GRF_SOC_CON3 0x0250 |
| |
| /*RK3288_GRF_SOC_CON1*/ |
| #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ |
| GRF_CLR_BIT(8)) |
| #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ |
| GRF_BIT(8)) |
| #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) |
| #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) |
| #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) |
| #define RK3288_GMAC_SPEED_100M GRF_BIT(10) |
| #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) |
| #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) |
| #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) |
| #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) |
| #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) |
| #define RK3288_GMAC_RMII_MODE GRF_BIT(14) |
| #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) |
| |
| /*RK3288_GRF_SOC_CON3*/ |
| #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) |
| #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) |
| #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
| #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
| #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
| #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
| |
| static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_PHY_INTF_SEL_RGMII | |
| RK3288_GMAC_RMII_MODE_CLR); |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, |
| RK3288_GMAC_RXCLK_DLY_ENABLE | |
| RK3288_GMAC_TXCLK_DLY_ENABLE | |
| RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | |
| RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); |
| } |
| |
| static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); |
| } |
| |
| static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_CLK_2_5M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_CLK_25M); |
| else if (speed == 1000) |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_CLK_125M); |
| else |
| dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); |
| } |
| |
| static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "Missing rockchip,grf property\n"); |
| return; |
| } |
| |
| if (speed == 10) { |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_RMII_CLK_2_5M | |
| RK3288_GMAC_SPEED_10M); |
| } else if (speed == 100) { |
| regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
| RK3288_GMAC_RMII_CLK_25M | |
| RK3288_GMAC_SPEED_100M); |
| } else { |
| dev_err(dev, "unknown speed value for RMII! speed=%d", speed); |
| } |
| } |
| |
| static const struct rk_gmac_ops rk3288_ops = { |
| .set_to_rgmii = rk3288_set_to_rgmii, |
| .set_to_rmii = rk3288_set_to_rmii, |
| .set_rgmii_speed = rk3288_set_rgmii_speed, |
| .set_rmii_speed = rk3288_set_rmii_speed, |
| }; |
| |
| #define RK3366_GRF_SOC_CON6 0x0418 |
| #define RK3366_GRF_SOC_CON7 0x041c |
| |
| /* RK3366_GRF_SOC_CON6 */ |
| #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_CLR_BIT(11)) |
| #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_BIT(11)) |
| #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) |
| #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
| #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) |
| #define RK3366_GMAC_SPEED_100M GRF_BIT(7) |
| #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) |
| #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
| #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
| #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
| #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
| #define RK3366_GMAC_RMII_MODE GRF_BIT(6) |
| #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
| |
| /* RK3366_GRF_SOC_CON7 */ |
| #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
| #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
| #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
| #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
| #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
| #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
| |
| static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_PHY_INTF_SEL_RGMII | |
| RK3366_GMAC_RMII_MODE_CLR); |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, |
| RK3366_GMAC_RXCLK_DLY_ENABLE | |
| RK3366_GMAC_TXCLK_DLY_ENABLE | |
| RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | |
| RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); |
| } |
| |
| static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); |
| } |
| |
| static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_CLK_2_5M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_CLK_25M); |
| else if (speed == 1000) |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_CLK_125M); |
| else |
| dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); |
| } |
| |
| static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) { |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_RMII_CLK_2_5M | |
| RK3366_GMAC_SPEED_10M); |
| } else if (speed == 100) { |
| regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, |
| RK3366_GMAC_RMII_CLK_25M | |
| RK3366_GMAC_SPEED_100M); |
| } else { |
| dev_err(dev, "unknown speed value for RMII! speed=%d", speed); |
| } |
| } |
| |
| static const struct rk_gmac_ops rk3366_ops = { |
| .set_to_rgmii = rk3366_set_to_rgmii, |
| .set_to_rmii = rk3366_set_to_rmii, |
| .set_rgmii_speed = rk3366_set_rgmii_speed, |
| .set_rmii_speed = rk3366_set_rmii_speed, |
| }; |
| |
| #define RK3368_GRF_SOC_CON15 0x043c |
| #define RK3368_GRF_SOC_CON16 0x0440 |
| |
| /* RK3368_GRF_SOC_CON15 */ |
| #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_CLR_BIT(11)) |
| #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_BIT(11)) |
| #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) |
| #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
| #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) |
| #define RK3368_GMAC_SPEED_100M GRF_BIT(7) |
| #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) |
| #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
| #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
| #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
| #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
| #define RK3368_GMAC_RMII_MODE GRF_BIT(6) |
| #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
| |
| /* RK3368_GRF_SOC_CON16 */ |
| #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
| #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
| #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
| #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
| #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
| #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
| |
| static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_PHY_INTF_SEL_RGMII | |
| RK3368_GMAC_RMII_MODE_CLR); |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, |
| RK3368_GMAC_RXCLK_DLY_ENABLE | |
| RK3368_GMAC_TXCLK_DLY_ENABLE | |
| RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | |
| RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); |
| } |
| |
| static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); |
| } |
| |
| static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_CLK_2_5M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_CLK_25M); |
| else if (speed == 1000) |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_CLK_125M); |
| else |
| dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); |
| } |
| |
| static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) { |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_RMII_CLK_2_5M | |
| RK3368_GMAC_SPEED_10M); |
| } else if (speed == 100) { |
| regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, |
| RK3368_GMAC_RMII_CLK_25M | |
| RK3368_GMAC_SPEED_100M); |
| } else { |
| dev_err(dev, "unknown speed value for RMII! speed=%d", speed); |
| } |
| } |
| |
| static const struct rk_gmac_ops rk3368_ops = { |
| .set_to_rgmii = rk3368_set_to_rgmii, |
| .set_to_rmii = rk3368_set_to_rmii, |
| .set_rgmii_speed = rk3368_set_rgmii_speed, |
| .set_rmii_speed = rk3368_set_rmii_speed, |
| }; |
| |
| #define RK3399_GRF_SOC_CON5 0xc214 |
| #define RK3399_GRF_SOC_CON6 0xc218 |
| |
| /* RK3399_GRF_SOC_CON5 */ |
| #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_CLR_BIT(11)) |
| #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
| GRF_BIT(11)) |
| #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) |
| #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
| #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) |
| #define RK3399_GMAC_SPEED_100M GRF_BIT(7) |
| #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) |
| #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
| #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
| #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
| #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
| #define RK3399_GMAC_RMII_MODE GRF_BIT(6) |
| #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
| |
| /* RK3399_GRF_SOC_CON6 */ |
| #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
| #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
| #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
| #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
| #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
| #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
| |
| static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, |
| int tx_delay, int rx_delay) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_PHY_INTF_SEL_RGMII | |
| RK3399_GMAC_RMII_MODE_CLR); |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, |
| RK3399_GMAC_RXCLK_DLY_ENABLE | |
| RK3399_GMAC_TXCLK_DLY_ENABLE | |
| RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | |
| RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); |
| } |
| |
| static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); |
| } |
| |
| static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_CLK_2_5M); |
| else if (speed == 100) |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_CLK_25M); |
| else if (speed == 1000) |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_CLK_125M); |
| else |
| dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); |
| } |
| |
| static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (IS_ERR(bsp_priv->grf)) { |
| dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); |
| return; |
| } |
| |
| if (speed == 10) { |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_RMII_CLK_2_5M | |
| RK3399_GMAC_SPEED_10M); |
| } else if (speed == 100) { |
| regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, |
| RK3399_GMAC_RMII_CLK_25M | |
| RK3399_GMAC_SPEED_100M); |
| } else { |
| dev_err(dev, "unknown speed value for RMII! speed=%d", speed); |
| } |
| } |
| |
| static const struct rk_gmac_ops rk3399_ops = { |
| .set_to_rgmii = rk3399_set_to_rgmii, |
| .set_to_rmii = rk3399_set_to_rmii, |
| .set_rgmii_speed = rk3399_set_rgmii_speed, |
| .set_rmii_speed = rk3399_set_rmii_speed, |
| }; |
| |
| static int gmac_clk_init(struct rk_priv_data *bsp_priv) |
| { |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| bsp_priv->clk_enabled = false; |
| |
| bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); |
| if (IS_ERR(bsp_priv->mac_clk_rx)) |
| dev_err(dev, "cannot get clock %s\n", |
| "mac_clk_rx"); |
| |
| bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); |
| if (IS_ERR(bsp_priv->mac_clk_tx)) |
| dev_err(dev, "cannot get clock %s\n", |
| "mac_clk_tx"); |
| |
| bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); |
| if (IS_ERR(bsp_priv->aclk_mac)) |
| dev_err(dev, "cannot get clock %s\n", |
| "aclk_mac"); |
| |
| bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); |
| if (IS_ERR(bsp_priv->pclk_mac)) |
| dev_err(dev, "cannot get clock %s\n", |
| "pclk_mac"); |
| |
| bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); |
| if (IS_ERR(bsp_priv->clk_mac)) |
| dev_err(dev, "cannot get clock %s\n", |
| "stmmaceth"); |
| |
| if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { |
| bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); |
| if (IS_ERR(bsp_priv->clk_mac_ref)) |
| dev_err(dev, "cannot get clock %s\n", |
| "clk_mac_ref"); |
| |
| if (!bsp_priv->clock_input) { |
| bsp_priv->clk_mac_refout = |
| devm_clk_get(dev, "clk_mac_refout"); |
| if (IS_ERR(bsp_priv->clk_mac_refout)) |
| dev_err(dev, "cannot get clock %s\n", |
| "clk_mac_refout"); |
| } |
| } |
| |
| if (bsp_priv->clock_input) { |
| dev_info(dev, "clock input from PHY\n"); |
| } else { |
| if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) |
| clk_set_rate(bsp_priv->clk_mac, 50000000); |
| } |
| |
| return 0; |
| } |
| |
| static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) |
| { |
| int phy_iface = bsp_priv->phy_iface; |
| |
| if (enable) { |
| if (!bsp_priv->clk_enabled) { |
| if (phy_iface == PHY_INTERFACE_MODE_RMII) { |
| if (!IS_ERR(bsp_priv->mac_clk_rx)) |
| clk_prepare_enable( |
| bsp_priv->mac_clk_rx); |
| |
| if (!IS_ERR(bsp_priv->clk_mac_ref)) |
| clk_prepare_enable( |
| bsp_priv->clk_mac_ref); |
| |
| if (!IS_ERR(bsp_priv->clk_mac_refout)) |
| clk_prepare_enable( |
| bsp_priv->clk_mac_refout); |
| } |
| |
| if (!IS_ERR(bsp_priv->aclk_mac)) |
| clk_prepare_enable(bsp_priv->aclk_mac); |
| |
| if (!IS_ERR(bsp_priv->pclk_mac)) |
| clk_prepare_enable(bsp_priv->pclk_mac); |
| |
| if (!IS_ERR(bsp_priv->mac_clk_tx)) |
| clk_prepare_enable(bsp_priv->mac_clk_tx); |
| |
| /** |
| * if (!IS_ERR(bsp_priv->clk_mac)) |
| * clk_prepare_enable(bsp_priv->clk_mac); |
| */ |
| mdelay(5); |
| bsp_priv->clk_enabled = true; |
| } |
| } else { |
| if (bsp_priv->clk_enabled) { |
| if (phy_iface == PHY_INTERFACE_MODE_RMII) { |
| if (!IS_ERR(bsp_priv->mac_clk_rx)) |
| clk_disable_unprepare( |
| bsp_priv->mac_clk_rx); |
| |
| if (!IS_ERR(bsp_priv->clk_mac_ref)) |
| clk_disable_unprepare( |
| bsp_priv->clk_mac_ref); |
| |
| if (!IS_ERR(bsp_priv->clk_mac_refout)) |
| clk_disable_unprepare( |
| bsp_priv->clk_mac_refout); |
| } |
| |
| if (!IS_ERR(bsp_priv->aclk_mac)) |
| clk_disable_unprepare(bsp_priv->aclk_mac); |
| |
| if (!IS_ERR(bsp_priv->pclk_mac)) |
| clk_disable_unprepare(bsp_priv->pclk_mac); |
| |
| if (!IS_ERR(bsp_priv->mac_clk_tx)) |
| clk_disable_unprepare(bsp_priv->mac_clk_tx); |
| /** |
| * if (!IS_ERR(bsp_priv->clk_mac)) |
| * clk_disable_unprepare(bsp_priv->clk_mac); |
| */ |
| bsp_priv->clk_enabled = false; |
| } |
| } |
| |
| return 0; |
| } |
| |
| static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) |
| { |
| struct regulator *ldo = bsp_priv->regulator; |
| int ret; |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (!ldo) { |
| dev_err(dev, "no regulator found\n"); |
| return -1; |
| } |
| |
| if (enable) { |
| ret = regulator_enable(ldo); |
| if (ret) |
| dev_err(dev, "fail to enable phy-supply\n"); |
| } else { |
| ret = regulator_disable(ldo); |
| if (ret) |
| dev_err(dev, "fail to disable phy-supply\n"); |
| } |
| |
| return 0; |
| } |
| |
| static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, |
| const struct rk_gmac_ops *ops) |
| { |
| struct rk_priv_data *bsp_priv; |
| struct device *dev = &pdev->dev; |
| int ret; |
| const char *strings = NULL; |
| int value; |
| |
| bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); |
| if (!bsp_priv) |
| return ERR_PTR(-ENOMEM); |
| |
| bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); |
| bsp_priv->ops = ops; |
| |
| bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); |
| if (IS_ERR(bsp_priv->regulator)) { |
| if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { |
| dev_err(dev, "phy regulator is not available yet, deferred probing\n"); |
| return ERR_PTR(-EPROBE_DEFER); |
| } |
| dev_err(dev, "no regulator found\n"); |
| bsp_priv->regulator = NULL; |
| } |
| |
| ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); |
| if (ret) { |
| dev_err(dev, "Can not read property: clock_in_out.\n"); |
| bsp_priv->clock_input = true; |
| } else { |
| dev_info(dev, "clock input or output? (%s).\n", |
| strings); |
| if (!strcmp(strings, "input")) |
| bsp_priv->clock_input = true; |
| else |
| bsp_priv->clock_input = false; |
| } |
| |
| ret = of_property_read_u32(dev->of_node, "tx_delay", &value); |
| if (ret) { |
| bsp_priv->tx_delay = 0x30; |
| dev_err(dev, "Can not read property: tx_delay."); |
| dev_err(dev, "set tx_delay to 0x%x\n", |
| bsp_priv->tx_delay); |
| } else { |
| dev_info(dev, "TX delay(0x%x).\n", value); |
| bsp_priv->tx_delay = value; |
| } |
| |
| ret = of_property_read_u32(dev->of_node, "rx_delay", &value); |
| if (ret) { |
| bsp_priv->rx_delay = 0x10; |
| dev_err(dev, "Can not read property: rx_delay."); |
| dev_err(dev, "set rx_delay to 0x%x\n", |
| bsp_priv->rx_delay); |
| } else { |
| dev_info(dev, "RX delay(0x%x).\n", value); |
| bsp_priv->rx_delay = value; |
| } |
| |
| bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, |
| "rockchip,grf"); |
| bsp_priv->pdev = pdev; |
| |
| gmac_clk_init(bsp_priv); |
| |
| return bsp_priv; |
| } |
| |
| static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) |
| { |
| int ret; |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| /*rmii or rgmii*/ |
| if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) { |
| dev_info(dev, "init for RGMII\n"); |
| bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, |
| bsp_priv->rx_delay); |
| } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { |
| dev_info(dev, "init for RMII\n"); |
| bsp_priv->ops->set_to_rmii(bsp_priv); |
| } else { |
| dev_err(dev, "NO interface defined!\n"); |
| } |
| |
| ret = phy_power_on(bsp_priv, true); |
| if (ret) |
| return ret; |
| |
| ret = gmac_clk_enable(bsp_priv, true); |
| if (ret) |
| return ret; |
| |
| pm_runtime_enable(dev); |
| pm_runtime_get_sync(dev); |
| |
| return 0; |
| } |
| |
| static void rk_gmac_powerdown(struct rk_priv_data *gmac) |
| { |
| struct device *dev = &gmac->pdev->dev; |
| |
| pm_runtime_put_sync(dev); |
| pm_runtime_disable(dev); |
| |
| phy_power_on(gmac, false); |
| gmac_clk_enable(gmac, false); |
| } |
| |
| static int rk_gmac_init(struct platform_device *pdev, void *priv) |
| { |
| struct rk_priv_data *bsp_priv = priv; |
| |
| return rk_gmac_powerup(bsp_priv); |
| } |
| |
| static void rk_gmac_exit(struct platform_device *pdev, void *priv) |
| { |
| struct rk_priv_data *bsp_priv = priv; |
| |
| rk_gmac_powerdown(bsp_priv); |
| } |
| |
| static void rk_gmac_suspend(struct platform_device *pdev, void *priv) |
| { |
| struct rk_priv_data *bsp_priv = priv; |
| |
| /* Keep the PHY up if we use Wake-on-Lan. */ |
| if (device_may_wakeup(&pdev->dev)) |
| return; |
| |
| rk_gmac_powerdown(bsp_priv); |
| bsp_priv->suspended = true; |
| } |
| |
| static void rk_gmac_resume(struct platform_device *pdev, void *priv) |
| { |
| struct rk_priv_data *bsp_priv = priv; |
| |
| /* The PHY was up for Wake-on-Lan. */ |
| if (!bsp_priv->suspended) |
| return; |
| |
| rk_gmac_powerup(bsp_priv); |
| bsp_priv->suspended = false; |
| } |
| |
| static void rk_fix_speed(void *priv, unsigned int speed) |
| { |
| struct rk_priv_data *bsp_priv = priv; |
| struct device *dev = &bsp_priv->pdev->dev; |
| |
| if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) |
| bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); |
| else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) |
| bsp_priv->ops->set_rmii_speed(bsp_priv, speed); |
| else |
| dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); |
| } |
| |
| static int rk_gmac_probe(struct platform_device *pdev) |
| { |
| struct plat_stmmacenet_data *plat_dat; |
| struct stmmac_resources stmmac_res; |
| const struct rk_gmac_ops *data; |
| int ret; |
| |
| data = of_device_get_match_data(&pdev->dev); |
| if (!data) { |
| dev_err(&pdev->dev, "no of match data provided\n"); |
| return -EINVAL; |
| } |
| |
| ret = stmmac_get_platform_resources(pdev, &stmmac_res); |
| if (ret) |
| return ret; |
| |
| plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); |
| if (IS_ERR(plat_dat)) |
| return PTR_ERR(plat_dat); |
| |
| plat_dat->has_gmac = true; |
| plat_dat->init = rk_gmac_init; |
| plat_dat->exit = rk_gmac_exit; |
| plat_dat->fix_mac_speed = rk_fix_speed; |
| plat_dat->suspend = rk_gmac_suspend; |
| plat_dat->resume = rk_gmac_resume; |
| |
| plat_dat->bsp_priv = rk_gmac_setup(pdev, data); |
| if (IS_ERR(plat_dat->bsp_priv)) { |
| ret = PTR_ERR(plat_dat->bsp_priv); |
| goto err_remove_config_dt; |
| } |
| |
| ret = rk_gmac_init(pdev, plat_dat->bsp_priv); |
| if (ret) |
| goto err_remove_config_dt; |
| |
| ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); |
| if (ret) |
| goto err_gmac_exit; |
| |
| return 0; |
| |
| err_gmac_exit: |
| rk_gmac_exit(pdev, plat_dat->bsp_priv); |
| err_remove_config_dt: |
| stmmac_remove_config_dt(pdev, plat_dat); |
| |
| return ret; |
| } |
| |
| static const struct of_device_id rk_gmac_dwmac_match[] = { |
| { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, |
| { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, |
| { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, |
| { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, |
| { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, |
| { } |
| }; |
| MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); |
| |
| static struct platform_driver rk_gmac_dwmac_driver = { |
| .probe = rk_gmac_probe, |
| .remove = stmmac_pltfr_remove, |
| .driver = { |
| .name = "rk_gmac-dwmac", |
| .pm = &stmmac_pltfr_pm_ops, |
| .of_match_table = rk_gmac_dwmac_match, |
| }, |
| }; |
| module_platform_driver(rk_gmac_dwmac_driver); |
| |
| MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); |
| MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); |
| MODULE_LICENSE("GPL"); |
