| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2021 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __AW933XX_REG_H__ |
| #define __AW933XX_REG_H__ |
| |
| #define AFE_BASE_ADDR (0x0000) |
| #define DSP_BASE_ADDR (0x0000) |
| #define DSPEX_BASE_ADDR (0x0000) |
| #define STAT_BASE_ADDR (0x0000) |
| #define DATA_BASE_ADDR (0x0000) |
| #define CAP_BASE_ADDR (0x1628) |
| #define SFR_BASE_ADDR (0x0000) |
| /* registers list */ |
| //AW933XX_AFE MAP |
| #define REG_SCANCTRL0 ((0x0000) + AFE_BASE_ADDR) |
| #define REG_SCANCTRL1 ((0x0004) + AFE_BASE_ADDR) |
| #define REG_SCANCTRL2 ((0x0008) + AFE_BASE_ADDR) |
| #define REG_SCANCTRL3 ((0x000C) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH0 ((0x0168) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH0 ((0x0170) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH0 ((0x0174) + AFE_BASE_ADDR) |
| #define REG_AFECFG2_CH0 ((0x0178) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH0 ((0x017C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH0 ((0x0180) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH0 ((0x0184) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH0 ((0x0188) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH1 ((0x0318) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH1 ((0x0320) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH1 ((0x0324) + AFE_BASE_ADDR) |
| #define REG_AFECFG2_CH1 ((0x0328) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH1 ((0x032C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH1 ((0x0330) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH1 ((0x0334) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH1 ((0x0338) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH2 ((0x04C8) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH2 ((0x04D0) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH2 ((0x04D4) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH2 ((0x04DC) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH2 ((0x04E0) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH2 ((0x04E4) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH2 ((0x04E8) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH3 ((0x0678) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH3 ((0x0680) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH3 ((0x0684) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH3 ((0x068C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH3 ((0x0690) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH3 ((0x0694) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH3 ((0x0698) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH4 ((0x0828) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH4 ((0x0830) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH4 ((0x0834) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH4 ((0x083C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH4 ((0x0840) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH4 ((0x0844) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH4 ((0x0848) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH5 ((0x09D8) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH5 ((0x09E0) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH5 ((0x09E4) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH5 ((0x09EC) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH5 ((0x09F0) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH5 ((0x09F4) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH5 ((0x09F8) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH6 ((0x0B88) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH6 ((0x0B90) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH6 ((0x0B94) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH6 ((0x0B9C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH6 ((0x0BA0) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH6 ((0x0BA4) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH6 ((0x0BA8) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH7 ((0x0D38) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH7 ((0x0D40) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH7 ((0x0D44) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH7 ((0x0D4C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH7 ((0x0D50) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH7 ((0x0D54) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH7 ((0x0D58) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH8 ((0x0EE8) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH8 ((0x0EF0) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH8 ((0x0EF4) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH8 ((0x0EFC) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH8 ((0x0F00) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH8 ((0x0F04) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH8 ((0x0F08) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH9 ((0x1098) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH9 ((0x10A0) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH9 ((0x10A4) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH9 ((0x10AC) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH9 ((0x10B0) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH9 ((0x10B4) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH9 ((0x10B8) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH10 ((0x1248) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH10 ((0x1250) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH10 ((0x1254) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH10 ((0x125C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH10 ((0x1260) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH10 ((0x1264) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH10 ((0x1268) + AFE_BASE_ADDR) |
| #define REG_AFESOFTCFG0_CH11 ((0x13F8) + AFE_BASE_ADDR) |
| #define REG_AFECFG0_CH11 ((0x1400) + AFE_BASE_ADDR) |
| #define REG_AFECFG1_CH11 ((0x1404) + AFE_BASE_ADDR) |
| #define REG_AFECFG3_CH11 ((0x140C) + AFE_BASE_ADDR) |
| #define REG_AFECFG4_CH11 ((0x1410) + AFE_BASE_ADDR) |
| #define REG_CHLSEL0_CH11 ((0x1414) + AFE_BASE_ADDR) |
| #define REG_CHLSEL1_CH11 ((0x1418) + AFE_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_DSP MAP |
| #define REG_FILTCTRL0_CH0 ((0x018C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH0 ((0x0190) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH0 ((0x0198) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH0 ((0x019C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH0 ((0x01A4) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH0 ((0x01A8) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH0 ((0x01C0) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH0 ((0x01C4) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH1 ((0x033C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH1 ((0x0340) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH1 ((0x0348) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH1 ((0x034C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH1 ((0x0354) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH1 ((0x0358) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH1 ((0x0370) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH1 ((0x0374) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH2 ((0x04EC) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH2 ((0x04F0) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH2 ((0x04F8) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH2 ((0x04FC) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH2 ((0x0504) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH2 ((0x0508) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH2 ((0x0520) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH2 ((0x0524) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH3 ((0x069C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH3 ((0x06A0) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH3 ((0x06A8) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH3 ((0x06AC) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH3 ((0x06B4) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH3 ((0x06B8) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH3 ((0x06D0) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH3 ((0x06D4) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH4 ((0x084C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH4 ((0x0850) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH4 ((0x0858) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH4 ((0x085C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH4 ((0x0864) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH4 ((0x0868) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH4 ((0x0880) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH4 ((0x0884) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH5 ((0x09FC) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH5 ((0x0A00) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH5 ((0x0A08) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH5 ((0x0A0C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH5 ((0x0A14) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH5 ((0x0A18) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH5 ((0x0A30) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH5 ((0x0A34) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH6 ((0x0BAC) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH6 ((0x0BB0) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH6 ((0x0BB8) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH6 ((0x0BBC) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH6 ((0x0BC4) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH6 ((0x0BC8) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH6 ((0x0BE0) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH6 ((0x0BE4) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH7 ((0x0D5C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH7 ((0x0D60) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH7 ((0x0D68) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH7 ((0x0D6C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH7 ((0x0D74) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH7 ((0x0D78) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH7 ((0x0D90) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH7 ((0x0D94) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH8 ((0x0F0C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH8 ((0x0F10) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH8 ((0x0F18) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH8 ((0x0F1C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH8 ((0x0F24) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH8 ((0x0F28) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH8 ((0x0F40) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH8 ((0x0F44) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH9 ((0x10BC) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH9 ((0x10C0) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH9 ((0x10C8) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH9 ((0x10CC) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH9 ((0x10D4) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH9 ((0x10D8) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH9 ((0x10F0) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH9 ((0x10F4) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH10 ((0x126C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH10 ((0x1270) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH10 ((0x1278) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH10 ((0x127C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH10 ((0x1284) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH10 ((0x1288) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH10 ((0x12A0) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH10 ((0x12A4) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL0_CH11 ((0x141C) + DSP_BASE_ADDR) |
| #define REG_REFACOEF_CH11 ((0x1420) + DSP_BASE_ADDR) |
| #define REG_FILTCTRL1_CH11 ((0x1428) + DSP_BASE_ADDR) |
| #define REG_BLFILTA_CH11 ((0x142C) + DSP_BASE_ADDR) |
| #define REG_PROXCTRL_CH11 ((0x1434) + DSP_BASE_ADDR) |
| #define REG_PROXTH0_CH11 ((0x1438) + DSP_BASE_ADDR) |
| #define REG_INITPROX0_CH11 ((0x1450) + DSP_BASE_ADDR) |
| #define REG_INITPROX1_CH11 ((0x1454) + DSP_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_DSPEX MAP |
| #define REG_BLUPTH_CH0 ((0x01D0) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH0 ((0x01D4) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH0 ((0x01F8) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH0 ((0x01FC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH0 ((0x0200) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH0 ((0x0204) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH0 ((0x0208) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH0 ((0x020C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH0 ((0x0210) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH0 ((0x0214) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH0 ((0x0218) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH0 ((0x021C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH1 ((0x0380) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH1 ((0x0384) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH1 ((0x03A8) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH1 ((0x03AC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH1 ((0x03B0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH1 ((0x03B4) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH1 ((0x03B8) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH1 ((0x03BC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH1 ((0x03C0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH1 ((0x03C4) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH1 ((0x03C8) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH1 ((0x03CC) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH2 ((0x0530) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH2 ((0x0534) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH2 ((0x0558) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH2 ((0x055C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH2 ((0x0560) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH2 ((0x0564) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH2 ((0x0568) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH2 ((0x056C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH2 ((0x0570) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH2 ((0x0574) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH2 ((0x0578) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH2 ((0x057C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH3 ((0x06E0) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH3 ((0x06E4) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH3 ((0x0708) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH3 ((0x070C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH3 ((0x0710) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH3 ((0x0714) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH3 ((0x0718) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH3 ((0x071C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH3 ((0x0720) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH3 ((0x0724) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH3 ((0x0728) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH3 ((0x072C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH4 ((0x0890) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH4 ((0x0894) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH4 ((0x08B8) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH4 ((0x08BC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH4 ((0x08C0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH4 ((0x08C4) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH4 ((0x08C8) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH4 ((0x08CC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH4 ((0x08D0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH4 ((0x08D4) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH4 ((0x08D8) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH4 ((0x08DC) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH5 ((0x0A40) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH5 ((0x0A44) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH5 ((0x0A68) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH5 ((0x0A6C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH5 ((0x0A70) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH5 ((0x0A74) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH5 ((0x0A78) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH5 ((0x0A7C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH5 ((0x0A80) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH5 ((0x0A84) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH5 ((0x0A88) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH5 ((0x0A8C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH6 ((0x0BF0) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH6 ((0x0BF4) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH6 ((0x0C18) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH6 ((0x0C1C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH6 ((0x0C20) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH6 ((0x0C24) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH6 ((0x0C28) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH6 ((0x0C2C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH6 ((0x0C30) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH6 ((0x0C34) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH6 ((0x0C38) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH6 ((0x0C3C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH7 ((0x0DA0) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH7 ((0x0DA4) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH7 ((0x0DC8) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH7 ((0x0DCC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH7 ((0x0DD0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH7 ((0x0DD4) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH7 ((0x0DD8) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH7 ((0x0DDC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH7 ((0x0DE0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH7 ((0x0DE4) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH7 ((0x0DE8) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH7 ((0x0DEC) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH8 ((0x0F50) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH8 ((0x0F54) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH8 ((0x0F78) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH8 ((0x0F7C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH8 ((0x0F80) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH8 ((0x0F84) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH8 ((0x0F88) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH8 ((0x0F8C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH8 ((0x0F90) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH8 ((0x0F94) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH8 ((0x0F98) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH8 ((0x0F9C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH9 ((0x1100) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH9 ((0x1104) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH9 ((0x1128) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH9 ((0x112C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH9 ((0x1130) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH9 ((0x1134) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH9 ((0x1138) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH9 ((0x113C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH9 ((0x1140) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH9 ((0x1144) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH9 ((0x1148) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH9 ((0x114C) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH10 ((0x12B0) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH10 ((0x12B4) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH10 ((0x12D8) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH10 ((0x12DC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH10 ((0x12E0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH10 ((0x12E4) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH10 ((0x12E8) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH10 ((0x12EC) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH10 ((0x12F0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH10 ((0x12F4) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH10 ((0x12F8) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH10 ((0x12FC) + DSPEX_BASE_ADDR) |
| #define REG_BLUPTH_CH11 ((0x1460) + DSPEX_BASE_ADDR) |
| #define REG_BLDOWNTH_CH11 ((0x1464) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWTH_CH11 ((0x1488) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMAX_CH11 ((0x148C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFMIN_CH11 ((0x1490) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFINIT_CH11 ((0x1494) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLAST_CH11 ((0x1498) + DSPEX_BASE_ADDR) |
| #define REG_REFKP_CH11 ((0x149C) + DSPEX_BASE_ADDR) |
| #define REG_REFCOEFLIMIT_CH11 ((0x14A0) + DSPEX_BASE_ADDR) |
| #define REG_REFCOMP_CH11 ((0x14A4) + DSPEX_BASE_ADDR) |
| #define REG_REFVALIDTAR_CH11 ((0x14A8) + DSPEX_BASE_ADDR) |
| #define REG_REFRAWLAST_CH11 ((0x14AC) + DSPEX_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_STAT MAP |
| #define REG_WST ((0x001C) + STAT_BASE_ADDR) |
| #define REG_STAT0 ((0x0020) + STAT_BASE_ADDR) |
| #define REG_STAT7 ((0x003C) + STAT_BASE_ADDR) |
| #define REG_STAT9 ((0x0044) + STAT_BASE_ADDR) |
| #define REG_STAT10 ((0x0048) + STAT_BASE_ADDR) |
| #define REG_CLOSEINTEN ((0x004C) + STAT_BASE_ADDR) |
| #define REG_FARINTEN ((0x0050) + STAT_BASE_ADDR) |
| #define REG_FWVER ((0x005C) + STAT_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_DATA MAP |
| #define REG_BASELINE_CH0 ((0x0230) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH0 ((0x0234) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH1 ((0x03E0) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH1 ((0x03E4) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH2 ((0x0590) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH2 ((0x0594) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH3 ((0x0740) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH3 ((0x0744) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH4 ((0x08F0) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH4 ((0x08F4) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH5 ((0x0AA0) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH5 ((0x0AA4) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH6 ((0x0C50) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH6 ((0x0C54) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH7 ((0x0E00) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH7 ((0x0E04) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH8 ((0x0FB0) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH8 ((0x0FB4) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH9 ((0x1160) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH9 ((0x1164) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH10 ((0x1310) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH10 ((0x1314) + DATA_BASE_ADDR) |
| #define REG_BASELINE_CH11 ((0x14C0) + DATA_BASE_ADDR) |
| #define REG_DIFF_CH11 ((0x14C4) + DATA_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_CAP MAP |
| #define REG_TOUCH_TH_X_SLD0 ((0x0000) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD0 ((0x0004) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD0 ((0x0008) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD0 ((0x000C) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD0 ((0x0010) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD0 ((0x0014) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD0 ((0x0018) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD0 ((0x001C) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD0 ((0x0030) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD0 ((0x0034) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD0 ((0x0038) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD0 ((0x0040) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD0 ((0x0044) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD0 ((0x0048) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD0 ((0x004C) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD0 ((0x0050) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD0 ((0x0054) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD1 ((0x005C) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD1 ((0x0060) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD1 ((0x0064) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD1 ((0x0068) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD1 ((0x006C) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD1 ((0x0070) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD1 ((0x0074) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD1 ((0x0078) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD1 ((0x008C) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD1 ((0x0090) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD1 ((0x0094) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD1 ((0x009C) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD1 ((0x00A0) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD1 ((0x00A4) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD1 ((0x00A8) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD1 ((0x00AC) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD1 ((0x00B0) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD2 ((0x00B8) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD2 ((0x00BC) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD2 ((0x00C0) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD2 ((0x00C4) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD2 ((0x00C8) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD2 ((0x00CC) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD2 ((0x00D0) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD2 ((0x00D4) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD2 ((0x00E8) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD2 ((0x00EC) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD2 ((0x00F0) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD2 ((0x00F8) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD2 ((0x00FC) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD2 ((0x0100) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD2 ((0x0104) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD2 ((0x0108) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD2 ((0x010C) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD3 ((0x0114) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD3 ((0x0118) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD3 ((0x011C) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD3 ((0x0120) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD3 ((0x0124) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD3 ((0x0128) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD3 ((0x012C) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD3 ((0x0130) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD3 ((0x0144) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD3 ((0x0148) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD3 ((0x014C) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD3 ((0x0154) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD3 ((0x0158) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD3 ((0x015C) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD3 ((0x0160) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD3 ((0x0164) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD3 ((0x0168) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD4 ((0x0170) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD4 ((0x0174) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD4 ((0x0178) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD4 ((0x017C) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD4 ((0x0180) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD4 ((0x0184) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD4 ((0x0188) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD4 ((0x018C) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD4 ((0x01A0) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD4 ((0x01A4) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD4 ((0x01A8) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD4 ((0x01B0) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD4 ((0x01B4) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD4 ((0x01B8) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD4 ((0x01BC) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD4 ((0x01C0) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD4 ((0x01C4) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD5 ((0x01CC) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD5 ((0x01D0) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD5 ((0x01D4) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD5 ((0x01D8) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD5 ((0x01DC) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD5 ((0x01E0) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD5 ((0x01E4) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD5 ((0x01E8) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD5 ((0x01FC) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD5 ((0x0200) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD5 ((0x0204) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD5 ((0x020C) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD5 ((0x0210) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD5 ((0x0214) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD5 ((0x0218) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD5 ((0x021C) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD5 ((0x0220) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD6 ((0x0228) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD6 ((0x022C) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD6 ((0x0230) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD6 ((0x0234) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD6 ((0x0238) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD6 ((0x023C) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD6 ((0x0240) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD6 ((0x0244) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD6 ((0x0258) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD6 ((0x025C) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD6 ((0x0260) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD6 ((0x0268) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD6 ((0x026C) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD6 ((0x0270) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD6 ((0x0274) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD6 ((0x0278) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD6 ((0x027C) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD7 ((0x0284) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD7 ((0x0288) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD7 ((0x028C) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD7 ((0x0290) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD7 ((0x0294) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD7 ((0x0298) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD7 ((0x029C) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD7 ((0x02A0) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD7 ((0x02B4) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD7 ((0x02B8) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD7 ((0x02BC) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD7 ((0x02C4) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD7 ((0x02C8) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD7 ((0x02CC) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD7 ((0x02D0) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD7 ((0x02D4) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD7 ((0x02D8) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD8 ((0x02E0) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD8 ((0x02E4) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD8 ((0x02E8) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD8 ((0x02EC) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD8 ((0x02F0) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD8 ((0x02F4) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD8 ((0x02F8) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD8 ((0x02FC) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD8 ((0x0310) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD8 ((0x0314) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD8 ((0x0318) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD8 ((0x0320) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD8 ((0x0324) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD8 ((0x0328) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD8 ((0x032C) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD8 ((0x0330) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD8 ((0x0334) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD9 ((0x033C) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD9 ((0x0340) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD9 ((0x0344) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD9 ((0x0348) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD9 ((0x034C) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD9 ((0x0350) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD9 ((0x0354) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD9 ((0x0358) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD9 ((0x036C) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD9 ((0x0370) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD9 ((0x0374) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD9 ((0x037C) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD9 ((0x0380) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD9 ((0x0384) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD9 ((0x0388) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD9 ((0x038C) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD9 ((0x0390) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD10 ((0x0398) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD10 ((0x039C) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD10 ((0x03A0) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD10 ((0x03A4) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD10 ((0x03A8) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD10 ((0x03AC) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD10 ((0x03B0) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD10 ((0x03B4) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD10 ((0x03C8) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD10 ((0x03CC) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD10 ((0x03D0) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD10 ((0x03D8) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD10 ((0x03DC) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD10 ((0x03E0) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD10 ((0x03E4) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD10 ((0x03E8) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD10 ((0x03EC) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_X_SLD11 ((0x03F4) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_X_SLD11 ((0x03F8) + CAP_BASE_ADDR) |
| #define REG_TOUCH_TH_Y_SLD11 ((0x03FC) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_Y_SLD11 ((0x0400) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG0_SLD11 ((0x0404) + CAP_BASE_ADDR) |
| #define REG_BUTTON_CFG1_SLD11 ((0x0408) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG0_SLD11 ((0x040C) + CAP_BASE_ADDR) |
| #define REG_LONGPRESS_CFG1_SLD11 ((0x0410) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_X_SLD11 ((0x0424) + CAP_BASE_ADDR) |
| #define REG_POS_CALCULATE_TH_Y_SLD11 ((0x0428) + CAP_BASE_ADDR) |
| #define REG_SLD_CFG_SLD11 ((0x042C) + CAP_BASE_ADDR) |
| #define REG_SLD_LIMIT_TH_SLD11 ((0x0434) + CAP_BASE_ADDR) |
| #define REG_FIRST_POS_SLD11 ((0x0438) + CAP_BASE_ADDR) |
| #define REG_NOW_POS_SLD11 ((0x043C) + CAP_BASE_ADDR) |
| #define REG_PER_POS_SLD11 ((0x0440) + CAP_BASE_ADDR) |
| #define REG_MOVE_DISTANCE_SLD11 ((0x0444) + CAP_BASE_ADDR) |
| #define REG_BAR_REPORT_SLD11 ((0x0448) + CAP_BASE_ADDR) |
| #define REG_WEAR_CFG ((0x0450) + CAP_BASE_ADDR) |
| #define REG_WEAR_STATE ((0x0454) + CAP_BASE_ADDR) |
| #define REG_PROX_TH_WEAR0 ((0x0458) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_WEAR0 ((0x045C) + CAP_BASE_ADDR) |
| #define REG_DELTA_UP_TH_WEAR0 ((0x0460) + CAP_BASE_ADDR) |
| #define REG_DELTA_DOWN_TH_WEAR0 ((0x0464) + CAP_BASE_ADDR) |
| #define REG_STD_ERR_TH_WEAR0 ((0x0468) + CAP_BASE_ADDR) |
| #define REG_PROX_TH_WEAR1 ((0x04C4) + CAP_BASE_ADDR) |
| #define REG_LEAVE_TH_WEAR1 ((0x04C8) + CAP_BASE_ADDR) |
| #define REG_DELTA_UP_TH_WEAR1 ((0x04CC) + CAP_BASE_ADDR) |
| #define REG_DELTA_DOWN_TH_WEAR1 ((0x04D0) + CAP_BASE_ADDR) |
| #define REG_STD_ERR_TH_WEAR1 ((0x04D4) + CAP_BASE_ADDR) |
| #define REG_CONTROL_NUM ((0x0534) + CAP_BASE_ADDR) |
| |
| /* registers list */ |
| //AW933XX_SFR MAP |
| #define REG_IRQSRC ((0xF080) + SFR_BASE_ADDR) |
| #define REG_IRQEN ((0xF084) + SFR_BASE_ADDR) |
| #define REG_I2CTIMEOUTEN ((0xF0E4) + SFR_BASE_ADDR) |
| #define REG_ANACFG ((0xF804) + SFR_BASE_ADDR) |
| #define REG_CHIPSTAT ((0xFF00) + SFR_BASE_ADDR) |
| #define REG_CHIP_ID0 ((0xFF10) + SFR_BASE_ADDR) |
| #define REG_I3C_OSC_EN ((0xFF40) + SFR_BASE_ADDR) |
| |
| #define REG_SA_RSTNALL (0xFF0C) |
| #define AW933XX_SOFT_RST_EN (0) |
| #define AW963XX_CHIP_INIT_MAX_TIME_MS (30) |
| #define REG_CMD ((0xF008) + SFR_BASE_ADDR) |
| |
| /******************************************** |
| * Register Access |
| *******************************************/ |
| |
| struct reg_data { |
| unsigned char rw; |
| unsigned short reg; |
| }; |
| |
| #define REG_NONE_ACCESS (0) |
| #define REG_RD_ACCESS BIT(0) |
| #define REG_WR_ACCESS BIT(1) |
| |
| static const struct reg_data g_aw933xx_reg_access[] = { |
| //AFE MAP |
| { .reg = REG_SCANCTRL0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SCANCTRL1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SCANCTRL2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SCANCTRL3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFESOFTCFG0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG1_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG3_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_AFECFG4_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHLSEL1_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| |
| //DSP MAP |
| { .reg = REG_FILTCTRL0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFACOEF_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FILTCTRL1_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLFILTA_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXCTRL_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROXTH0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX0_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_INITPROX1_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| |
| //DSPEX MAP |
| { .reg = REG_BLUPTH_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BLUPTH_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BLDOWNTH_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFRAWTH_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMAX_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFMIN_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFINIT_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLAST_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFKP_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOEFLIMIT_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFCOMP_CH11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_REFVALIDTAR_CH11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_REFRAWLAST_CH11, .rw = REG_RD_ACCESS, }, |
| |
| //STAT MAP |
| { .reg = REG_WST, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_STAT0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_STAT7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_STAT9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_STAT10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_CLOSEINTEN, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FARINTEN, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FWVER, .rw = REG_RD_ACCESS, }, |
| |
| //DATA MAP |
| { .reg = REG_BASELINE_CH0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BASELINE_CH11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_DIFF_CH11, .rw = REG_RD_ACCESS, }, |
| |
| //CAP MAP |
| { .reg = REG_TOUCH_TH_X_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD1, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD2, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD2, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD3, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD3, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD4, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD4, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD5, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD5, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD6, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD6, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD7, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD7, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD8, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD8, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD9, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD9, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD10, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD10, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_TOUCH_TH_X_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_X_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_TOUCH_TH_Y_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_Y_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG0_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_BUTTON_CFG1_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG0_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LONGPRESS_CFG1_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_X_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_POS_CALCULATE_TH_Y_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_CFG_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_SLD_LIMIT_TH_SLD11, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_FIRST_POS_SLD11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_NOW_POS_SLD11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PER_POS_SLD11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_MOVE_DISTANCE_SLD11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_BAR_REPORT_SLD11, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_WEAR_CFG, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_WEAR_STATE, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_PROX_TH_WEAR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_WEAR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_DELTA_UP_TH_WEAR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_DELTA_DOWN_TH_WEAR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_STD_ERR_TH_WEAR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_PROX_TH_WEAR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_LEAVE_TH_WEAR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_DELTA_UP_TH_WEAR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_DELTA_DOWN_TH_WEAR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_STD_ERR_TH_WEAR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CONTROL_NUM, .rw = REG_RD_ACCESS, }, |
| |
| //SFR MAP |
| { .reg = REG_IRQSRC, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_IRQEN, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_I2CTIMEOUTEN, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_ANACFG, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| { .reg = REG_CHIPSTAT, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_CHIP_ID0, .rw = REG_RD_ACCESS, }, |
| { .reg = REG_I3C_OSC_EN, .rw = REG_RD_ACCESS | REG_WR_ACCESS, }, |
| |
| }; |
| |
| //reg config |
| const unsigned int aw933xx_default_reg[] = { |
| 0x0000, 0x00000007, |
| 0x0004, 0x00000007, |
| 0x0008, 0x00000FFF, |
| 0x000C, 0x00000014, |
| 0x0010, 0x0000705F, |
| 0x0014, 0x80000000, |
| 0x0168, 0x00000000, |
| 0x016C, 0x003F0000, |
| 0x0170, 0x00093000, |
| 0x0174, 0x00000000, |
| 0x0178, 0x341C9207, |
| 0x017C, 0x00008000, |
| 0x0180, 0x00000909, |
| 0x0184, 0x000000D9, |
| 0x0318, 0x00000000, |
| 0x031C, 0x003F0000, |
| 0x0320, 0x00093000, |
| 0x0324, 0x00000000, |
| 0x0328, 0x341C9207, |
| 0x032C, 0x00008000, |
| 0x0330, 0x00000909, |
| 0x0334, 0x000000CB, |
| 0x04C8, 0x00000000, |
| 0x04CC, 0x003F0000, |
| 0x04D0, 0x00093000, |
| 0x04D4, 0x00000000, |
| 0x04D8, 0x341C9207, |
| 0x04DC, 0x00008000, |
| 0x04E0, 0x00000909, |
| 0x04E4, 0x0000005B, |
| 0x1628, 0x0000C350, |
| 0x162C, 0x00000000, |
| 0x1638, 0x00010000, |
| 0x163C, 0x001401F4, |
| 0x1640, 0x0BB807D0, |
| 0x1644, 0x00000FA0, |
| 0x1658, 0x0000C350, |
| 0x1660, 0x00000300, |
| 0x1668, 0x00000000, |
| 0x1684, 0x0000C350, |
| 0x1688, 0x00000000, |
| 0x1694, 0x00010000, |
| 0x1698, 0x001401F4, |
| 0x169C, 0x0BB807D0, |
| 0x16A0, 0x00000FA0, |
| 0x16B4, 0x0000C350, |
| 0x16BC, 0x00000300, |
| 0x16C4, 0x00000000, |
| 0x16E0, 0x0000C350, |
| 0x16E4, 0x00000000, |
| 0x16F0, 0x00010000, |
| 0x16F4, 0x001401F4, |
| 0x16F8, 0x0BB807D0, |
| 0x16FC, 0x00000FA0, |
| 0x1710, 0x0000C350, |
| 0x1718, 0x00000300, |
| 0x1720, 0x00000000, |
| 0x1A78, 0x00000040, |
| 0x1A80, 0x0000C350, |
| 0x1A84, 0x0000C350, |
| 0x1A88, 0x0000C350, |
| 0x1A8C, 0x0000C350, |
| 0x1A90, 0x0000C350, |
| 0x1AEC, 0x0000C350, |
| 0x1AF0, 0x0000C350, |
| 0x1AF4, 0x0000C350, |
| 0x1AF8, 0x0000C350, |
| 0x1AFC, 0x0000C350, |
| 0x018C, 0x00400000, |
| 0x0190, 0x00000000, |
| 0x0198, 0x00000000, |
| 0x019C, 0x000008D0, |
| 0x01A0, 0x00000000, |
| 0x01A4, 0x00000000, |
| 0x01A8, 0x00004E20, |
| 0x01C0, 0x00000000, |
| 0x01C4, 0x00000000, |
| 0x01CC, 0x00000000, |
| 0x033C, 0x00400000, |
| 0x0340, 0x00000000, |
| 0x0348, 0x00000000, |
| 0x034C, 0x000008D0, |
| 0x0350, 0x00000000, |
| 0x0354, 0x00000000, |
| 0x0358, 0x00004E20, |
| 0x0370, 0x00000000, |
| 0x0374, 0x00000000, |
| 0x037C, 0x00000000, |
| 0x04EC, 0x00400000, |
| 0x04F0, 0x00000000, |
| 0x04F8, 0x00000000, |
| 0x04FC, 0x000008D0, |
| 0x0500, 0x00000000, |
| 0x0504, 0x00000000, |
| 0x0508, 0x00004E20, |
| 0x0520, 0x00000000, |
| 0x0524, 0x00000000, |
| 0x052C, 0x00000000, |
| 0x01D0, 0x00000000, |
| 0x01D4, 0x00000000, |
| 0x01D8, 0x00000000, |
| 0x01E0, 0x00000000, |
| 0x01E4, 0xFFFFFFFF, |
| 0x01F8, 0x070004B0, |
| 0x01FC, 0x0E000000, |
| 0x0200, 0xF2000000, |
| 0x0204, 0x02000000, |
| 0x0208, 0x02000000, |
| 0x020C, 0x00002000, |
| 0x0210, 0x00010000, |
| 0x0214, 0x80007530, |
| 0x0380, 0x00000000, |
| 0x0384, 0x00000000, |
| 0x0388, 0x00000000, |
| 0x0390, 0x00000000, |
| 0x0394, 0xFFFFFFFF, |
| 0x03A8, 0x070004B0, |
| 0x03AC, 0x0E000000, |
| 0x03B0, 0xF2000000, |
| 0x03B4, 0x02000000, |
| 0x03B8, 0x02000000, |
| 0x03BC, 0x00002000, |
| 0x03C0, 0x00010000, |
| 0x03C4, 0x80007530, |
| 0x0530, 0x00000000, |
| 0x0534, 0x00000000, |
| 0x0538, 0x00000000, |
| 0x0540, 0x00000000, |
| 0x0544, 0xFFFFFFFF, |
| 0x0558, 0x070004B0, |
| 0x055C, 0x0E000000, |
| 0x0560, 0xF2000000, |
| 0x0564, 0x02000000, |
| 0x0568, 0x02000000, |
| 0x056C, 0x00002000, |
| 0x0570, 0x00010000, |
| 0x0574, 0x80007530, |
| 0xF084, 0x000E0FFF, |
| 0x004C, 0xFFFFFFFF, |
| 0x0050, 0xFFFFFFFF, |
| }; |
| |
| #endif |
