include/linux/input/aw933xx.h - manifest_repos/amlogic-driver - Git at Google

 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
 /*
  * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
  */

 #ifndef __AW933XX_H__
 #define __AW933XX_H__
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/i2c.h>
 #include <linux/of_gpio.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/firmware.h>
 #include <linux/slab.h>
 #include <linux/version.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/debugfs.h>
 #include <linux/uaccess.h>
 #include <linux/syscalls.h>
 #include <linux/string.h>
 #include <linux/jiffies.h>
 #include <linux/sched.h>
 #include <linux/types.h>
 #include <linux/kern_levels.h>
 #include <linux/regulator/consumer.h>
 #include <linux/power_supply.h>
 #include <linux/decompress/mm.h>

 /* It is determined by the specific number of channels of the chip. */
 /* eg: 12/7/5/3 */
 #define AW933XX_CH_NUM_MAX			(3)

 #ifndef AW_TRUE
 #define AW_TRUE					(1)
 #endif

 #ifndef AW_FALSE
 #define AW_FALSE				(0)
 #endif

 #ifndef OFFSET_BIT_0
 #define OFFSET_BIT_0				(0)
 #endif

 #ifndef OFFSET_BIT_8
 #define OFFSET_BIT_8				(8)
 #endif

 #ifndef OFFSET_BIT_16
 #define OFFSET_BIT_16				(16)
 #endif

 #ifndef OFFSET_BIT_24
 #define OFFSET_BIT_24				(24)
 #endif

 #ifndef WORD_LEN
 #define WORD_LEN				(4)
 #endif

 #ifndef GET_BITS_7_0
 #define GET_BITS_7_0				(0x00FF)
 #endif

 #ifndef GET_BITS_15_8
 #define GET_BITS_15_8				(0xFF00)
 #endif

 #ifndef GET_BITS_24_16
 #define GET_BITS_24_16				(0x00FF0000)
 #endif

 #ifndef GET_BITS_31_25
 #define GET_BITS_31_25				(0xFF000000)
 #endif

 #define HALF_WORD				(0xf)
 #define ONE_WORD				(0xff)

 #define AWLOGD(dev, format, arg...) \
 		 dev_dbg(dev, \
 			"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

 #define AWLOGI(dev, format, arg...) \
 		dev_info(dev, \
 			"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

 #define AWLOGE(dev, format, arg...) \
 		 dev_err(dev, \
 			"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

 #define AW933XX_VCC_MIN_UV					(1700000)
 #define AW933XX_VCC_MAX_UV					(3600000)
 #define AW933XX_SRAM_UPDATE_ONE_PACK_SIZE	(1024)
 #define AW933XX_SRAM_UPDATE_ONE_UINT_SIZE	(4)
 #define AW933XX_SRAM_START_ADDR				(0x2000)
 #define AW933XX_SRAM_END_ADDR				(0x4ff4 + 4)
 #define AW933XX_SRAM_SIZE					(AW933XX_SRAM_END_ADDR - \
 	AW933XX_SRAM_START_ADDR)
 #define AW933XX_SRAM_DEFAULT_VAL			(0xffffffff)

 #define AW933XX_I2C_RETRIES			(3)
 #define AW933XX_REG_DATA_LEN		(4)
 #define AW933XX_REG_ADDR_LEN		(2)
 #define AW933XX_CPU_OSC_CTRL_MASK	(1)
 #define AW933XX_OFFSET_LEN			(15)

 #define AW933XX_DATA_OffSET_2		(2)
 #define AW933XX_DATA_OffSET_3		(3)
 #define AW933XX_AWRW_OffSET			(20)
 #define AW933XX_AWRW_DATA_WIDTH		(5)
 #define AW933XX_RST_DELAY_MS		(30)

 #define AW933XX_DATA_PROCESS_FACTOR						(1024)
 #define AW933XX_STEP_LEN_UNSIGNED_CAP_ROUGH_ADJ			(9900)
 #define AW933XX_STEP_LEN_UNSIGNED_CAP_FINE_ADJ			(152)
 #define AW933XX_STEP_LEN_UNSIGNED_CAP_ENLARGE			(10000)
 #define AW933XX_SRAM_UPDATE_ONE_UINT_SIZE				(4)
 #define AW933XX_POWER_ON_SYSFS_DELAY_MS					(5000)

 #define AW93303_NAME	("aw93303")
 #define AW93305_NAME	("aw93305")
 #define AW93308_NAME	("aw93308")
 #define AW93312_NAME	("aw93312")

 #define AW_CAP_FLIP_U16(value) ({ typeof(value) value_ = (value); \
 	(((value_) & (0x00FF)) << (8)) | (((value_) & (0xFF00)) >> (8)); })
 #define AW_CAP_FLIP_U32(value) ({ typeof(value) value_ = (value); \
 	(((value_) & (0x000000FF)) << (24)) | \
 	((((value_) & (0x0000FF00))) << (8)) | \
 	(((value_) & (0x00FF0000)) >> (8)) | \
 	(((value_) & (0xFF000000)) >> (24)); })

 enum aw933xx_state {
 	AW_OK,
 	AW_ERR,
 	AW_PARA_ERR,
 	AW_VERS_ERR,
 	AW_ERR_CHIPID,
 	AW_ERR_IRQ_INIT_OVER,
 	AW_PROT_UPDATE_ERR,
 	AW_REG_LOAD_ERR,
 	AW_INVALID_PARA,
 	AW_BIN_PARA_INVALID,
 	AW_FW_CHECK_ERR,
 	AW_BT_CHECK_ERR,
 	AW_OTEHR_CHECK_ERR,
 	AW_BIN_NAME_CHECK_ERR,
 };

 enum aw933xx_host_irq_state {
 	IRQ_ENABLE,
 	IRQ_DISABLE,
 };

 enum aw933xx_health_check {
 	AW933XX_HEALTHY = 0,
 	AW933XX_UNHEALTHY = 1,
 };

 enum aw933xx_i2c_flag {
 	AW933XX_I2C_WR,
 	AW933XX_I2C_RD,
 	AW933XX_PACKAGE_RD,
 };

 enum aw933xx_chip_id {
 	AW93303_CHIP_ID = 0xA9630340,
 	AW93305_CHIP_ID = 0xA9630520,
 	AW93308_CHIP_ID = 0xA9630808,
 	AW93312_CHIP_ID = 0xA9331210,
 };

 // aw933xx operation mode
 enum aw933xx_op_mode {
 	AW933XX_ACTIVE_MODE = 0x01,
 	AW933XX_SLEEP_MODE = 0x02,
 	AW933XX_DEEPSLEEP_MODE = 0x03,
 };

 enum aw933xx_cap_mode {
 	AW933XX_UNSIGNED_CAP = 0,
 	AW933XX_SIGNED_CAP = 4,
 	AW933XX_MUTUAL_CAP = 5,
 };

 enum aw933xx_bit {
 	AW_BIT0,
 	AW_BIT1,
 	AW_BIT2,
 	AW_BIT3,
 	AW_BIT7 = 7,
 	AW_BIT8 = 8,
 	AW_BIT16 = 16,
 	AW_BIT24 = 24,
 	AW_BIT28 = 28,
 	AW_BIT32 = 32,
 };

 struct aw933xx_dts_info {
 	u32 cap_num;
 	s32 irq_gpio;
 	u32 channel_use_flag;
 	bool use_regulator_flag;
 	bool use_inter_pull_up;
 	bool use_pm;
 };

 struct aw933xx_pm_info {
 	enum aw933xx_op_mode suspend_set_mode;
 	enum aw933xx_op_mode resume_set_mode;
 	enum aw933xx_op_mode shutdown_set_mode;
 };

 struct aw933xx_reg_data {
 	unsigned char rw;
 	unsigned short reg;
 };

 struct aw933xx_diff {
 	u16 diff0_reg;
 	u16 diff_step;
 	//Data format:S21.10, Floating point types generally need to be removed
 	u32 rm_float;
 };

 struct aw933xx_chip_mode_info {
 	u32 init_mode;		// chip init over set mode
 	u32 active;		// chip active mode
 	u32 pre_init_mode; // chip mode when power on
 };

 struct aw933xx_bin_info {
 	const u8 *bin_name;
 	u32 bin_data_ver;
 };

 struct aw933xx_reg_list {
 	u8 reg_none_access;
 	u8 reg_rd_access;
 	u8 reg_wd_access;
 	const struct aw933xx_reg_data *reg_perm;
 	u32 reg_num;
 };

 struct aw933xx_pinctrl {
 	struct pinctrl *pinctrl;
 	struct pinctrl_state *default_sta;
 	struct pinctrl_state *int_out_high;
 	struct pinctrl_state *int_out_low;
 };

 struct aw933xx_awrw_info {
 	u8 rw_flag;
 	u8 addr_len;
 	u8 data_len;
 	u8 reg_num;
 	u32 i2c_tranfar_data_len;
 	u8 *p_i2c_tranfar_data;
 };

 struct aw933xx_irq_init {
 	s32 to_irq;
 	u8 host_irq_stat;
 	void *data;
 	u8 label[30];
 	u8 dev_id[30];
 };

 struct aw933xx_para_info {
 	const u32 *reg_arr;
 	u32 reg_arr_len;
 };

 struct aw933xx_channels_info {
 	u16 used;
 	u32 last_channel_info;
 	struct input_dev *input;
 	u8 name[20];
 };

 struct aw933xx_irq_cfg {
 	unsigned long flags;
 	unsigned long irq_flags;
 	irq_handler_t handler;
 	irq_handler_t thread_fn;

 };

 #define AW933XX_SLDX_STEP					(0x5C)

 #define AW933XX_PRESS_STAT_IDX					(0)
 #define AW933XX_PRESS_VALID_DAT					(0x0f)
 #define AW933XX_CLICK_STAT_IDX					(4)
 #define AW933XX_CLICK_VALID_DAT					(0x3f)
 #define AW933XX_SLIDE_STAT_IDX					(10)
 #define AW933XX_SLIDE_VALID_DAT					(0x3f)
 #define AW933XX_SLIDE_WEAR_STATE_MASK				(0x3)

 #define AW933XX_EVENT_SLIDE_DIR_UP				(1)
 #define AW933XX_EVENT_SLIDE_DIR_DOWN				(2)
 #define AW933XX_EVENT_SLIDE_DIR_LEFT				(4)
 #define AW933XX_EVENT_SLIDE_DIR_RIGHT				(8)

 #define AW933XX_EVENT_PRESS					(1)
 #define AW933XX_EVENT_PRESS_LONG				(3)
 #define AW933XX_EVENT_PRESS_SUPER_LONG				(7)

 struct aw933xx_event {
 	u8 click;
 	u8 press;
 	u8 long_press;
 	u8 super_long_press;
 	u8 wear;
 	u8 irq_trigger;
 	u8 long_press_leave;
 	u8 super_perss;
 	u8 long_perss;
 	u8 triple_click;
 	u8 double_click;
 	u8 single_click;
 	u8 right_wareds;
 	u8 left_wareds;
 	u8 up_wareds;
 	u8 down_wareds;
 	u8 in_ear;
 	u8 prox_stat_th_0;
 	u8 prox_stat_th_1;
 	s32 slide_distance;
 };

 struct aw933xx_cap {
 	u32 chip_id;
 	u8 chip_name[20];
 	u8 reg_name[50];
 	u8 fault_flag;
 	bool driver_code_init_over_flag;
 	bool reg_bin_load_flag;
 	bool code_ram_bin_load_flag;
 	bool power_enable;
 	enum aw933xx_op_mode last_mode;

 	struct i2c_client *i2c;
 	struct device *dev;
 	struct regulator *vcc;
 	struct aw933xx_dts_info dts_info;
 	struct aw933xx_irq_init irq_init;
 	struct aw933xx_pinctrl pinctrl;
 	const struct aw933xx_pm_info *pm_info;
 	const struct aw933xx_chip_mode_info *chip_mode_info;
 	const struct aw933xx_reg_list *p_reg_list;
 	const struct aw933xx_diff *p_diff;
 	struct aw933xx_bin_info *code_ram_info;
 	struct aw933xx_bin_info *reg_bin_info;
 	struct aw933xx_irq_cfg *irq_cfg;
 	// struct aw933xx_irq_init irq_init;
 	struct aw933xx_channels_info *channels_arr;
 	// struct aw_channels_info slider;
 	const struct aw933xx_para_info *para_info;
 	struct delayed_work update_work;
 	struct aw933xx_awrw_info awrw_info;

 	struct aw933xx_event event;
 };

 #endif
	/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
	/*
	* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
	*/

	#ifndef __AW933XX_H__
	#define __AW933XX_H__
	#include <linux/module.h>
	#include <linux/kernel.h>
	#include <linux/i2c.h>
	#include <linux/of_gpio.h>
	#include <linux/delay.h>
	#include <linux/device.h>
	#include <linux/firmware.h>
	#include <linux/slab.h>
	#include <linux/version.h>
	#include <linux/input.h>
	#include <linux/interrupt.h>
	#include <linux/debugfs.h>
	#include <linux/uaccess.h>
	#include <linux/syscalls.h>
	#include <linux/string.h>
	#include <linux/jiffies.h>
	#include <linux/sched.h>
	#include <linux/types.h>
	#include <linux/kern_levels.h>
	#include <linux/regulator/consumer.h>
	#include <linux/power_supply.h>
	#include <linux/decompress/mm.h>

	/* It is determined by the specific number of channels of the chip. */
	/* eg: 12/7/5/3 */
	#define AW933XX_CH_NUM_MAX (3)

	#ifndef AW_TRUE
	#define AW_TRUE (1)
	#endif

	#ifndef AW_FALSE
	#define AW_FALSE (0)
	#endif

	#ifndef OFFSET_BIT_0
	#define OFFSET_BIT_0 (0)
	#endif

	#ifndef OFFSET_BIT_8
	#define OFFSET_BIT_8 (8)
	#endif

	#ifndef OFFSET_BIT_16
	#define OFFSET_BIT_16 (16)
	#endif

	#ifndef OFFSET_BIT_24
	#define OFFSET_BIT_24 (24)
	#endif

	#ifndef WORD_LEN
	#define WORD_LEN (4)
	#endif

	#ifndef GET_BITS_7_0
	#define GET_BITS_7_0 (0x00FF)
	#endif

	#ifndef GET_BITS_15_8
	#define GET_BITS_15_8 (0xFF00)
	#endif

	#ifndef GET_BITS_24_16
	#define GET_BITS_24_16 (0x00FF0000)
	#endif

	#ifndef GET_BITS_31_25
	#define GET_BITS_31_25 (0xFF000000)
	#endif

	#define HALF_WORD (0xf)
	#define ONE_WORD (0xff)

	#define AWLOGD(dev, format, arg...) \
	dev_dbg(dev, \
	"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

	#define AWLOGI(dev, format, arg...) \
	dev_info(dev, \
	"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

	#define AWLOGE(dev, format, arg...) \
	dev_err(dev, \
	"[%s:%d] " format "\n", __func__, __LINE__, ##arg)

	#define AW933XX_VCC_MIN_UV (1700000)
	#define AW933XX_VCC_MAX_UV (3600000)
	#define AW933XX_SRAM_UPDATE_ONE_PACK_SIZE (1024)
	#define AW933XX_SRAM_UPDATE_ONE_UINT_SIZE (4)
	#define AW933XX_SRAM_START_ADDR (0x2000)
	#define AW933XX_SRAM_END_ADDR (0x4ff4 + 4)
	#define AW933XX_SRAM_SIZE (AW933XX_SRAM_END_ADDR - \
	AW933XX_SRAM_START_ADDR)
	#define AW933XX_SRAM_DEFAULT_VAL (0xffffffff)

	#define AW933XX_I2C_RETRIES (3)
	#define AW933XX_REG_DATA_LEN (4)
	#define AW933XX_REG_ADDR_LEN (2)
	#define AW933XX_CPU_OSC_CTRL_MASK (1)
	#define AW933XX_OFFSET_LEN (15)

	#define AW933XX_DATA_OffSET_2 (2)
	#define AW933XX_DATA_OffSET_3 (3)
	#define AW933XX_AWRW_OffSET (20)
	#define AW933XX_AWRW_DATA_WIDTH (5)
	#define AW933XX_RST_DELAY_MS (30)

	#define AW933XX_DATA_PROCESS_FACTOR (1024)
	#define AW933XX_STEP_LEN_UNSIGNED_CAP_ROUGH_ADJ (9900)
	#define AW933XX_STEP_LEN_UNSIGNED_CAP_FINE_ADJ (152)
	#define AW933XX_STEP_LEN_UNSIGNED_CAP_ENLARGE (10000)
	#define AW933XX_SRAM_UPDATE_ONE_UINT_SIZE (4)
	#define AW933XX_POWER_ON_SYSFS_DELAY_MS (5000)

	#define AW93303_NAME ("aw93303")
	#define AW93305_NAME ("aw93305")
	#define AW93308_NAME ("aw93308")
	#define AW93312_NAME ("aw93312")

	#define AW_CAP_FLIP_U16(value) ({ typeof(value) value_ = (value); \
	(((value_) & (0x00FF)) << (8)) \| (((value_) & (0xFF00)) >> (8)); })
	#define AW_CAP_FLIP_U32(value) ({ typeof(value) value_ = (value); \
	(((value_) & (0x000000FF)) << (24)) \| \
	((((value_) & (0x0000FF00))) << (8)) \| \
	(((value_) & (0x00FF0000)) >> (8)) \| \
	(((value_) & (0xFF000000)) >> (24)); })

	enum aw933xx_state {
	AW_OK,
	AW_ERR,
	AW_PARA_ERR,
	AW_VERS_ERR,
	AW_ERR_CHIPID,
	AW_ERR_IRQ_INIT_OVER,
	AW_PROT_UPDATE_ERR,
	AW_REG_LOAD_ERR,
	AW_INVALID_PARA,
	AW_BIN_PARA_INVALID,
	AW_FW_CHECK_ERR,
	AW_BT_CHECK_ERR,
	AW_OTEHR_CHECK_ERR,
	AW_BIN_NAME_CHECK_ERR,
	};

	enum aw933xx_host_irq_state {
	IRQ_ENABLE,
	IRQ_DISABLE,
	};

	enum aw933xx_health_check {
	AW933XX_HEALTHY = 0,
	AW933XX_UNHEALTHY = 1,
	};

	enum aw933xx_i2c_flag {
	AW933XX_I2C_WR,
	AW933XX_I2C_RD,
	AW933XX_PACKAGE_RD,
	};

	enum aw933xx_chip_id {
	AW93303_CHIP_ID = 0xA9630340,
	AW93305_CHIP_ID = 0xA9630520,
	AW93308_CHIP_ID = 0xA9630808,
	AW93312_CHIP_ID = 0xA9331210,
	};

	// aw933xx operation mode
	enum aw933xx_op_mode {
	AW933XX_ACTIVE_MODE = 0x01,
	AW933XX_SLEEP_MODE = 0x02,
	AW933XX_DEEPSLEEP_MODE = 0x03,
	};

	enum aw933xx_cap_mode {
	AW933XX_UNSIGNED_CAP = 0,
	AW933XX_SIGNED_CAP = 4,
	AW933XX_MUTUAL_CAP = 5,
	};

	enum aw933xx_bit {
	AW_BIT0,
	AW_BIT1,
	AW_BIT2,
	AW_BIT3,
	AW_BIT7 = 7,
	AW_BIT8 = 8,
	AW_BIT16 = 16,
	AW_BIT24 = 24,
	AW_BIT28 = 28,
	AW_BIT32 = 32,
	};

	struct aw933xx_dts_info {
	u32 cap_num;
	s32 irq_gpio;
	u32 channel_use_flag;
	bool use_regulator_flag;
	bool use_inter_pull_up;
	bool use_pm;
	};

	struct aw933xx_pm_info {
	enum aw933xx_op_mode suspend_set_mode;
	enum aw933xx_op_mode resume_set_mode;
	enum aw933xx_op_mode shutdown_set_mode;
	};

	struct aw933xx_reg_data {
	unsigned char rw;
	unsigned short reg;
	};

	struct aw933xx_diff {
	u16 diff0_reg;
	u16 diff_step;
	//Data format:S21.10, Floating point types generally need to be removed
	u32 rm_float;
	};

	struct aw933xx_chip_mode_info {
	u32 init_mode; // chip init over set mode
	u32 active; // chip active mode
	u32 pre_init_mode; // chip mode when power on
	};

	struct aw933xx_bin_info {
	const u8 *bin_name;
	u32 bin_data_ver;
	};

	struct aw933xx_reg_list {
	u8 reg_none_access;
	u8 reg_rd_access;
	u8 reg_wd_access;
	const struct aw933xx_reg_data *reg_perm;
	u32 reg_num;
	};

	struct aw933xx_pinctrl {
	struct pinctrl *pinctrl;
	struct pinctrl_state *default_sta;
	struct pinctrl_state *int_out_high;
	struct pinctrl_state *int_out_low;
	};

	struct aw933xx_awrw_info {
	u8 rw_flag;
	u8 addr_len;
	u8 data_len;
	u8 reg_num;
	u32 i2c_tranfar_data_len;
	u8 *p_i2c_tranfar_data;
	};

	struct aw933xx_irq_init {
	s32 to_irq;
	u8 host_irq_stat;
	void *data;
	u8 label[30];
	u8 dev_id[30];
	};

	struct aw933xx_para_info {
	const u32 *reg_arr;
	u32 reg_arr_len;
	};

	struct aw933xx_channels_info {
	u16 used;
	u32 last_channel_info;
	struct input_dev *input;
	u8 name[20];
	};

	struct aw933xx_irq_cfg {
	unsigned long flags;
	unsigned long irq_flags;
	irq_handler_t handler;
	irq_handler_t thread_fn;

	};

	#define AW933XX_SLDX_STEP (0x5C)

	#define AW933XX_PRESS_STAT_IDX (0)
	#define AW933XX_PRESS_VALID_DAT (0x0f)
	#define AW933XX_CLICK_STAT_IDX (4)
	#define AW933XX_CLICK_VALID_DAT (0x3f)
	#define AW933XX_SLIDE_STAT_IDX (10)
	#define AW933XX_SLIDE_VALID_DAT (0x3f)
	#define AW933XX_SLIDE_WEAR_STATE_MASK (0x3)

	#define AW933XX_EVENT_SLIDE_DIR_UP (1)
	#define AW933XX_EVENT_SLIDE_DIR_DOWN (2)
	#define AW933XX_EVENT_SLIDE_DIR_LEFT (4)
	#define AW933XX_EVENT_SLIDE_DIR_RIGHT (8)

	#define AW933XX_EVENT_PRESS (1)
	#define AW933XX_EVENT_PRESS_LONG (3)
	#define AW933XX_EVENT_PRESS_SUPER_LONG (7)

	struct aw933xx_event {
	u8 click;
	u8 press;
	u8 long_press;
	u8 super_long_press;
	u8 wear;
	u8 irq_trigger;
	u8 long_press_leave;
	u8 super_perss;
	u8 long_perss;
	u8 triple_click;
	u8 double_click;
	u8 single_click;
	u8 right_wareds;
	u8 left_wareds;
	u8 up_wareds;
	u8 down_wareds;
	u8 in_ear;
	u8 prox_stat_th_0;
	u8 prox_stat_th_1;
	s32 slide_distance;
	};

	struct aw933xx_cap {
	u32 chip_id;
	u8 chip_name[20];
	u8 reg_name[50];
	u8 fault_flag;
	bool driver_code_init_over_flag;
	bool reg_bin_load_flag;
	bool code_ram_bin_load_flag;
	bool power_enable;
	enum aw933xx_op_mode last_mode;

	struct i2c_client *i2c;
	struct device *dev;
	struct regulator *vcc;
	struct aw933xx_dts_info dts_info;
	struct aw933xx_irq_init irq_init;
	struct aw933xx_pinctrl pinctrl;
	const struct aw933xx_pm_info *pm_info;
	const struct aw933xx_chip_mode_info *chip_mode_info;
	const struct aw933xx_reg_list *p_reg_list;
	const struct aw933xx_diff *p_diff;
	struct aw933xx_bin_info *code_ram_info;
	struct aw933xx_bin_info *reg_bin_info;
	struct aw933xx_irq_cfg *irq_cfg;
	// struct aw933xx_irq_init irq_init;
	struct aw933xx_channels_info *channels_arr;
	// struct aw_channels_info slider;
	const struct aw933xx_para_info *para_info;
	struct delayed_work update_work;
	struct aw933xx_awrw_info awrw_info;

	struct aw933xx_event event;
	};

	#endif