arch/arm/boot/dts/amlogic/mesontxhd2_drm.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */
#include <dt-bindings/display/meson-drm-ids.h>
#include "mesontxhd2.dtsi"

/ {
	drm_vpu: drm-vpu@0xff900000  {
		status = "disabled";
		compatible = "amlogic, meson-txhd2-vpu";
		osd_ver = /bits/ 8 <OSD_V4>;
		reg = <0xff900000 0x40000>,
			  <0xff63c000 0x2000>,
			  <0xff638000 0x2000>;
		reg-names = "base", "hhi", "dmc";
		interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "viu-vsync", "viu2-vsync";
		dma-coherent;
		connectors_dev: port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			drm_to_lcd0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <0>;
			};
		};
	};

	drm_subsystem: drm-subsystem {
		status = "okay";
		compatible = "amlogic, drm-subsystem";
		ports = <&connectors_dev>;
		postblend_path_mask = <1>;
		fbdev_sizes = <1280 720 1280 1440 32>;
		osd_ver = /bits/ 8 <OSD_V4>;
		vfm_mode = <1>; /** 0:drm mode 1:composer mode */
		memory-region = <&logo_reserved>;
		primary_plane_index = <0>; /* primary plane index for crtcs */
		crtc_masks = <0 1 0>; /*for encoder: 0:hdmi 1:lcd 2:cvbs*/

		vpu_topology: vpu_topology {
			vpu_blocks {
				osd1_block: block@0 {
					id = /bits/ 8 <OSD1_BLOCK>;
					index = /bits/ 8  <0>;
					type = /bits/ 8  <0>;
					block_name = "osd1_block";
					num_in_links = /bits/ 8  <0x0>;
					num_out_links = /bits/ 8  <0x1>;
					out_links = <0 &scaler1_block>;
				};
				osd2_block: block@1 {
					id = /bits/ 8  <OSD2_BLOCK>;
					index = /bits/ 8  <1>;
					type = /bits/ 8  <0>;
					block_name = "osd2_block";
					num_in_links = /bits/ 8  <0x0>;
					num_out_links = /bits/ 8  <0x1>;
					out_links = <1 &scaler2_block>;
				};
				scaler1_block: block@4 {
					id = /bits/ 8  <SCALER1_BLOCK>;
					index = /bits/ 8  <0>;
					type = /bits/ 8  <2>;
					block_name = "scaler1_block";
					num_in_links = /bits/ 8  <0x1>;
					in_links = <0 &osd1_block>;
					num_out_links = /bits/ 8  <0x1>;
					out_links = <0 &osd_blend_block>;
				};
				scaler2_block: block@5 {
					id = /bits/ 8  <SCALER2_BLOCK>;
					index = /bits/ 8  <1>;
					type = /bits/ 8  <2>;
					block_name = "scaler2_block";
					num_in_links = /bits/ 8  <0x1>;
					in_links = <1 &osd2_block>;
					num_out_links = /bits/ 8  <0x1>;
					out_links = <1 &osd_blend_block>;
				};
				osd_blend_block: block@7 {
					id = /bits/ 8  <OSD_BLEND_BLOCK>;
					block_name = "osd_blend_block";
					type = /bits/ 8  <3>;
					num_in_links = /bits/ 8  <0x2>;
					in_links = <0 &scaler1_block>,
						<0 &scaler2_block>;
					num_out_links = /bits/ 8  <0x1>;
					out_links = <0 &vpp1_postblend_block>;
				};
				vpp1_postblend_block: block@9 {
					id = /bits/ 8  <VPP1_POSTBLEND_BLOCK>;
					index = /bits/ 8  <0>;
					block_name = "vpp1_postblend_block";
					type = /bits/ 8  <6>;
					num_in_links = /bits/ 8  <0x1>;
					in_links = <0 &osd_blend_block>;
					num_out_links = <0x0>;
				};
				video1_block: block@10 {
					id = /bits/ 8 <VIDEO1_BLOCK>;
					index = /bits/ 8  <0>;
					type = /bits/ 8  <7>;
					block_name = "video1_block";
					num_in_links = /bits/ 8  <0x0>;
					num_out_links = /bits/ 8  <0x0>;
				};
				video2_block: block@11 {
					id = /bits/ 8 <VIDEO2_BLOCK>;
					index = /bits/ 8  <1>;
					type = /bits/ 8  <7>;
					block_name = "video2_block";
					num_in_links = /bits/ 8  <0x0>;
					num_out_links = /bits/ 8  <0x0>;
				};
			};
		};

		vpu_hw_para: vpu_hw_para@0 {
			osd_ver = /bits/ 8 <OSD_V4>;
			afbc_type = /bits/ 8 <0x2>;
			has_deband = /bits/ 8 <0x1>;
			has_lut = /bits/ 8 <0x1>;
			has_rdma = /bits/ 8 <0x1>;
			osd_fifo_len = /bits/ 8 <64>;
			vpp_fifo_len = /bits/ 32 <0xfff>;
		};
	};
};