| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| #include "Galois_memmap.h" |
| #include "global.h" |
| /* |
| #include "io.h" |
| #include "SysMgr.h" |
| #include "apb_perf_base.h" |
| #include "pin_settings.h" |
| #include "gpio.h" |
| */ |
| |
| #if 0 |
| // cdp pinmux registers: |
| |
| #define RA_Gbl_pinMuxCntlBus 0x8000 |
| #define RA_Gbl_pinMuxCntlBus1 0x8004 |
| #define RA_Gbl_pinMuxCntlBus2 0x8008 |
| #define RA_Gbl_pinMuxCntlBus3 0x800C |
| #endif |
| |
| #define SOC_GROUP0 G0_MODE1_IO_GPIO17_18 |
| #define SOC_GROUP1 G1_MODE1_IO_SD0_CLK_CMD |
| #define SOC_GROUP2 G2_MODE1_IO_SD0_DAT0_1 |
| #define SOC_GROUP3 G3_MODE1_IO_SD0_DAT2_3 |
| #define SOC_GROUP4 G4_MODE0_IO_GPIO4 |
| #define SOC_GROUP5 G5_MODE0_IO_GPIO6 |
| #define SOC_GROUP6 G6_MODE0_I_URT0_RXD_TXD |
| #define SOC_GROUP7 G7_MODE1_IO_TW1_SCL_SDA |
| #define SOC_GROUP8 G8_MODE0_O_SPI1_SS0n |
| #define SOC_GROUP9 G9_MODE3_IO_TW0_SCL_SDA |
| #define SOC_GROUP10 G10_MODE0_O_SPI1_SCLK |
| #define SOC_GROUP11 G11_MODE0_IO_SPI1_SDI_SDO |
| #define SOC_GROUP12 G12_MODE1_IO_GPO_22 |
| #define SOC_GROUP13 G13_MODE0_IO_NAND_IO0_7 |
| #define SOC_GROUP14 G14_MODE0_O_NAND_WPn |
| #define SOC_GROUP15 G15_MODE0_O_TDO |
| |
| // BG2_cdp_pins_120413: |
| #define G0_BASE_ADDR (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_pinMuxCntlBus) |
| #define G0_0_URT0_RXD (0 << LSb32Gbl_pinMuxCntlBus_URT0_RXD) |
| #define G0_1_URT0_TXD (0 << LSb32Gbl_pinMuxCntlBus_URT0_TXD) |
| #define G0_2_SPI1_SS0n (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SS0n) |
| #define G0_3_SPI1_SS1n (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_4_SPI1_SS2n (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| #define G0_5_SPI1_SCLK (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SCLK) |
| #define G0_6_SPI1_SDO (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SDO) |
| #define G0_7_SPI1_SDI (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SDI) |
| #define G0_8_USB1_DRV_VBUS (0 << LSb32Gbl_pinMuxCntlBus_USB1_DRV_VBUS) |
| #define G0_9_TW1_SCL (1 << LSb32Gbl_pinMuxCntlBus_TW1_SCL) |
| |
| #define G1_BASE_ADDR (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_pinMuxCntlBus1) |
| #define G1_0_TW1_SDA (1 << LSb32Gbl_pinMuxCntlBus_TW1_SDA) |
| #define G1_1_HDMI_CEC (0 << LSb32Gbl_pinMuxCntlBus_HDMI_CEC) |
| #define G1_2_HDMI_HPD (0 << LSb32Gbl_pinMuxCntlBus_HDMI_HPD) |
| #define G1_3_NAND_IO0 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO0) |
| #define G1_4_NAND_IO1 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO1) |
| #define G1_5_NAND_IO2 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO2) |
| #define G1_6_NAND_IO3 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO3) |
| #define G1_7_NAND_IO4 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO4) |
| #define G1_8_NAND_IO5 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO5) |
| #define G1_9_NAND_IO6 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO6) |
| |
| #define G2_BASE_ADDR (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_pinMuxCntlBus2) |
| #define G2_0_NAND_IO7 (0 << LSb32Gbl_pinMuxCntlBus_NAND_IO7) |
| #define G2_1_NAND_ALE (0 << LSb32Gbl_pinMuxCntlBus_NAND_ALE) |
| #define G2_2_NAND_CLE (0 << LSb32Gbl_pinMuxCntlBus_NAND_CLE) |
| #define G2_3_NAND_WEn (0 << LSb32Gbl_pinMuxCntlBus_NAND_WEn) |
| #define G2_4_NAND_REn (0 << LSb32Gbl_pinMuxCntlBus_NAND_REn) |
| #define G2_5_NAND_WPn (0 << LSb32Gbl_pinMuxCntlBus_NAND_WPn) |
| #define G2_6_NAND_CEn (0 << LSb32Gbl_pinMuxCntlBus_NAND_CEn) |
| #define G2_7_NAND_RDY (0 << LSb32Gbl_pinMuxCntlBus_NAND_RDY) |
| #define G2_8_SD0_CLK (1 << LSb32Gbl_pinMuxCntlBus_SD0_CLK) |
| #define G2_9_SD0_DAT0 (1 << LSb32Gbl_pinMuxCntlBus_SD0_DAT0) |
| |
| #define G3_BASE_ADDR (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_pinMuxCntlBus3) |
| #define G3_0_SD0_DAT1 (1 << LSb32Gbl_pinMuxCntlBus_SD0_DAT1) |
| #define G3_1_SD0_DAT2 (1 << LSb32Gbl_pinMuxCntlBus_SD0_DAT2) |
| #define G3_2_SD0_DAT3 (1 << LSb32Gbl_pinMuxCntlBus_SD0_DAT3) |
| #define G3_3_SD0_CDn (1 << LSb32Gbl_pinMuxCntlBus_SD0_CDn) |
| #define G3_4_SD0_CMD (1 << LSb32Gbl_pinMuxCntlBus_SD0_CMD) |
| #define G3_5_SD0_WP (1 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| #define G3_6_STS0_CLK (0 << LSb32Gbl_pinMuxCntlBus_STS0_CLK) |
| #define G3_7_STS0_SOP (0 << LSb32Gbl_pinMuxCntlBus_STS0_SOP) |
| #define G3_8_STS0_VALD (0 << LSb32Gbl_pinMuxCntlBus_STS0_VALD) |
| #define G3_9_STS0_SD (0 << LSb32Gbl_pinMuxCntlBus_STS0_SD) |
| |
| |
| #define G0_0_GPIO3 (1 << LSb32Gbl_pinMuxCntlBus_URT0_RXD) |
| #define G0_1_GPIO4 (1 << LSb32Gbl_pinMuxCntlBus_URT0_TXD) |
| #define G0_2_GPIO5 (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SS0n) |
| #define G0_3_GPIO6 (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_4_GPIO7 (0 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| #define G0_5_GPIO8 (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| #define G0_6_GPIO9 (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SDO) |
| #define G0_7_GPIO10 (1 << LSb32Gbl_pinMuxCntlBus_SPI1_SDI) |
| #define G0_8_GPIO11 (1 << LSb32Gbl_pinMuxCntlBus_USB1_DRV_VBUS) |
| |
| #define G2_1_GPIO24 (3 << LSb32Gbl_pinMuxCntlBus_NAND_ALE) |
| #define G2_2_GPIO25 (3 << LSb32Gbl_pinMuxCntlBus_NAND_CLE) |
| #define G2_3_GPIO26 (3 << LSb32Gbl_pinMuxCntlBus_NAND_WEn) |
| #define G2_4_GPIO27 (3 << LSb32Gbl_pinMuxCntlBus_NAND_REn) |
| #define G2_5_GPIO28 (3 << LSb32Gbl_pinMuxCntlBus_NAND_WPn) |
| #define G2_6_GPIO29 (3 << LSb32Gbl_pinMuxCntlBus_NAND_CEn) |
| #define G2_7_GPIO30 (3 << LSb32Gbl_pinMuxCntlBus_NAND_RDY) |
| #define G2_8_GPIO31 (0 << LSb32Gbl_pinMuxCntlBus_SD0_CLK) |
| #define G2_9_GPIO32 (0 << LSb32Gbl_pinMuxCntlBus_SD0_DAT0) |
| #define G2_9_GPIO33 (0 << LSb32Gbl_pinMuxCntlBus_SD0_DAT1) |
| #define G2_9_GPIO34 (0 << LSb32Gbl_pinMuxCntlBus_SD0_DAT2) |
| #define G2_9_GPIO35 (0 << LSb32Gbl_pinMuxCntlBus_SD0_DAT3) |
| #define G3_3_GPIO36 (0 << LSb32Gbl_pinMuxCntlBus_SD0_CDn) |
| #define G3_4_GPIO37 (0 << LSb32Gbl_pinMuxCntlBus_SD0_CMD) |
| #define G3_5_GPIO38 (0 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| |
| #define G0_3_AVS_PMIC_0 (3 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_3_TW0_SCL (4 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_3_PWM0 (5 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_4_AVS_PMIC_1 (3 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| #define G0_4_TW0_SDA (4 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| #define G0_4_PWM1 (5 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| |
| #define G2_5_EMMC_CLK (1 << LSb32Gbl_pinMuxCntlBus_NAND_WPn) |
| #define G2_6_EMMC_RSTn (1 << LSb32Gbl_pinMuxCntlBus_NAND_CEn) |
| #define G2_7_EMMC_CMD (1 << LSb32Gbl_pinMuxCntlBus_NAND_RDY) |
| |
| #define G3_3_PDM_DI0 (2 << LSb32Gbl_pinMuxCntlBus_SD0_CDn) |
| #define G3_5_PDM_DI1 (2 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| #define G3_3_PwM0 (4 << LSb32Gbl_pinMuxCntlBus_SD0_CDn) |
| #define G3_5_PwM1 (4 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| #define G3_3_I2S2_DI0 (5 << LSb32Gbl_pinMuxCntlBus_SD0_CDn) |
| #define G3_5_I2S2_DI1 (5 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| |
| #define G3_5_I2S1_DO (6 << LSb32Gbl_pinMuxCntlBus_SD0_WP) |
| #define G0_3_I2S1_BCLKO (6 << LSb32Gbl_pinMuxCntlBus_SPI1_SS1n) |
| #define G0_4_I2S1_LRCKO (6 << LSb32Gbl_pinMuxCntlBus_SPI1_SS2n) |
| |
| void pin_init() |
| { |
| } |
| |
