| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| #include "Galois_memmap.h"
|
| #include "global.h"
|
| #include "cpu_ca7.h"
|
| #include "MctrlSS.h"
|
| #include "util.h"
|
| #include "lgpl_printf.h" |
|
|
| #define SYSPLL_CTRL_BASE (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_sysPll)
|
| #define CPUPLL_CTRL_BASE (MEMMAP_CA7_REG_BASE + RA_CA7PllReg_PllReg)
|
| #define MEMPLL_CTRL_BASE (MEMMAP_MCTRLSS_REG_BASE + RA_MctrlSS_memPll)
|
|
|
| #define dbg_printf lgpl_printf
|
| #define LIST_ALL_SPEEDS 2
|
|
|
| #define PRT_ALL 4
|
|
|
| /*const unsigned int memPLL_config[]=
|
| {
|
|
|
| MEMPLL_800_CTL_VAL, MEMPLL_800_CTL1_VAL, MEMPLL_800_CTL2_VAL, 800,
|
| MEMPLL_1200_CTL_VAL, MEMPLL_1200_CTL1_VAL, MEMPLL_1200_CTL2_VAL, 1200,
|
| MEMPLL_1600_CTL_VAL, MEMPLL_1600_CTL1_VAL, MEMPLL_1600_CTL2_VAL, 1600,
|
| MEMPLL_1800_CTL_VAL, MEMPLL_1800_CTL1_VAL, MEMPLL_1800_CTL2_VAL, 1862,
|
|
|
| 0xFFFFFFFF
|
|
|
| };*/
|
|
|
| const float VcoDiv[8] =
|
| {
|
| 1, /// * 000: 1
|
| 2, /// * 001: 2
|
| 4, /// * 010: 4
|
| 8, /// * 011: 8
|
| 16, /// * 100: 16
|
| 32, /// * 101: 32
|
| 64, /// * 110: 64
|
| 128 /// * 111:128
|
|
|
| };
|
| #ifdef PRT_ALL
|
| enum Clocks
|
| {
|
| CPUFASTREFCLK,
|
| MEMFASTREFCLK,
|
| CFGCLK,
|
| SYSCLK,
|
| V2GCLK,
|
| V2GM3CLK,
|
| G1CORECLK,
|
| GFX3DCORECLK,
|
| GFX3DSYSCLK,
|
| AVIOSYSCLK,
|
| APPCLK,
|
| VPPSYSCLK,
|
| ARCREFCLK,
|
| HDMIRXCLK,
|
| PERIFCLK,
|
| ZSPCLK,
|
| TSPCLK,
|
| TSPREFCLK,
|
| ATBCLK,
|
| BCMCLK,
|
| NFCECCCLK,
|
| SD0CLK,
|
| USB2TESTCLK,
|
| SDIO3DLLMSTREFCLK,
|
| NONCLK,
|
| };
|
|
|
| static const char* g_aClocks[] =
|
| {
|
| "cpufastRefClk",
|
| "memfastRefClk",
|
| "cfgClk",
|
| "sysClk",
|
| "v2gClk",
|
| "v2gM3Clk",
|
| "g1CoreClk",
|
| "gfx3DCoreClk",
|
| "gfx3DSysClk",
|
| "avioSysClk",
|
| "appClk",
|
| "vppSysClk",
|
| "arcRefClk",
|
| "hdmirxMClk",
|
| "perifClk",
|
| "zspClk",
|
| "tspClk",
|
| "tspRefClk",
|
| "atbClk",
|
| "bcmClk",
|
| "nfcEccClk",
|
| "sd0Clk",
|
| "usb2TestClk",
|
| "sdio3DllMstRefClk"
|
| };
|
|
|
| static const unsigned int g_aClkOffset[]=
|
| {
|
| RA_Gbl_cpufastRefClk,
|
| RA_Gbl_memfastRefClk,
|
| RA_Gbl_cfgClk,
|
| RA_Gbl_sysClk,
|
| RA_Gbl_v2gClk,
|
| RA_Gbl_v2gM3Clk,
|
| RA_Gbl_g1CoreClk,
|
| RA_Gbl_gfx3DCoreClk,
|
| RA_Gbl_gfx3DSysClk,
|
| RA_Gbl_avioSysClk,
|
| RA_Gbl_appClk,
|
| RA_Gbl_vppSysClk,
|
| RA_Gbl_arcRefClk,
|
| RA_Gbl_hdmirxMClk,
|
| RA_Gbl_perifClk,
|
| RA_Gbl_zspClk,
|
| RA_Gbl_tspClk,
|
| RA_Gbl_tspRefClk,
|
| RA_Gbl_atbClk,
|
| RA_Gbl_bcmClk,
|
| RA_Gbl_nfcEccClk,
|
| RA_Gbl_sd0Clk,
|
| RA_Gbl_usb2TestClk,
|
| RA_Gbl_sdio3DllMstRefClk
|
| };
|
|
|
| const unsigned int clock_divider[] =
|
| {
|
| 1,
|
| 2,
|
| 4,
|
| 6,
|
| 8,
|
| 12,
|
| 1,
|
| 1
|
| };
|
|
|
| const char *AVPLL[] =
|
| {
|
| "AVPllB4",
|
| "AVPllB5",
|
| "AVPllB6",
|
| "AVPllB7",
|
| };
|
| #endif
|
| int speed_cpu = 400;
|
| int mempll_speed;
|
| unsigned int RefClkIn = 25;
|
| unsigned int RefDiv = 2;
|
| float current_freq[2][8];
|
|
|
| #ifdef PRT_ALL
|
| unsigned int get_divider(unsigned int D3Switch, unsigned int Switch, unsigned int Select)
|
| {
|
| unsigned int divider;
|
| if (D3Switch)
|
| divider = 3;
|
| else
|
| {
|
| if (!Switch)
|
| divider = 1;
|
| else
|
| divider = clock_divider[Select];
|
| }
|
| return divider;
|
| }
|
| #endif
|
|
|
| void list_speed(int level)
|
| {
|
| //YH: this needs to be updated for new PLL IP
|
| unsigned int FbDiv;
|
| unsigned int vcoDiv_sel_setting;
|
| Tpll_ctrl pllCtl;
|
| unsigned int memPll;
|
| unsigned int sysPll;
|
| unsigned int cpuPll;
|
| #ifdef PRT_ALL
|
| unsigned int sysPll_diff_p;
|
| unsigned int divider;
|
| unsigned int D3Switch, Switch, Select;
|
| unsigned int PllSel;
|
| TclkD1_ctrl clkDx; |
| #endif
|
|
|
| // memPll
|
| BFM_HOST_Bus_Read32((MEMPLL_CTRL_BASE + RA_pll_ctrl), &pllCtl.u32[0]);
|
| BFM_HOST_Bus_Read32((MEMPLL_CTRL_BASE + RA_pll_ctrl1), &pllCtl.u32[1]);
|
| FbDiv = pllCtl.uctrl_FBDIV;
|
| RefDiv = pllCtl.uctrl_REFDIV;
|
| vcoDiv_sel_setting = pllCtl.uctrl_CLKOUT_DIFF_DIV_SEL;
|
| memPll = FbDiv * 4 * RefClkIn / RefDiv;
|
| memPll = (float)memPll / VcoDiv[vcoDiv_sel_setting];
|
| mempll_speed=memPll;
|
| dbg_printf("%20s%20s\t%d\n", "memPll", "frequency", memPll);
|
|
|
| // sysPll
|
| BFM_HOST_Bus_Read32((SYSPLL_CTRL_BASE + RA_pll_ctrl), &pllCtl.u32[0]);
|
| BFM_HOST_Bus_Read32((SYSPLL_CTRL_BASE + RA_pll_ctrl1), &pllCtl.u32[1]);
|
| FbDiv = pllCtl.uctrl_FBDIV;
|
| RefDiv = pllCtl.uctrl_REFDIV;
|
| vcoDiv_sel_setting = pllCtl.uctrl_CLKOUT_SE_DIV_SEL;
|
| sysPll = FbDiv * 4 * RefClkIn / RefDiv;
|
| sysPll = (float)sysPll / VcoDiv[vcoDiv_sel_setting];
|
| dbg_printf("%20s%20s\t%d\n", "sysPll", "frequency", sysPll);
|
|
|
| // cpuPll
|
| BFM_HOST_Bus_Read32((CPUPLL_CTRL_BASE + RA_pll_ctrl), &pllCtl.u32[0]);
|
| BFM_HOST_Bus_Read32((CPUPLL_CTRL_BASE + RA_pll_ctrl1), &pllCtl.u32[1]);
|
| FbDiv = pllCtl.uctrl_FBDIV;
|
| RefDiv = pllCtl.uctrl_REFDIV;
|
| vcoDiv_sel_setting = pllCtl.uctrl_CLKOUT_SE_DIV_SEL;
|
| cpuPll = FbDiv * 4 * RefClkIn / RefDiv;
|
| cpuPll = (float)cpuPll / VcoDiv[vcoDiv_sel_setting];
|
| dbg_printf("%20s%20s\t%d\n", "cpuPll", "frequency", cpuPll);
|
|
|
| #ifdef PRT_ALL
|
| // DDR
|
| BFM_HOST_Bus_Read32((MEMMAP_MCTRLSS_REG_BASE + RA_MctrlSS_MC5_4TO1), &cpuPll);
|
| if (cpuPll & 1) // 4 to 1
|
| dbg_printf("%20s%20s\t%d\n", "dClk", "frequency", memPll / 4);
|
| else // 2 to 1
|
| dbg_printf("%20s%20s\t%d\n", "dClk", "frequency", memPll / 2);
|
|
|
| // CPU
|
| speed_cpu = cpuPll ;
|
|
|
| if (level >= LIST_ALL_SPEEDS)
|
| {
|
| int i;
|
| for (i = 0; i < NONCLK; i++)
|
| {
|
| BFM_HOST_Bus_Read32((MEMMAP_CHIP_CTRL_REG_BASE + g_aClkOffset[i]), &clkDx.u32[0]);
|
| D3Switch = clkDx.uctrl_ClkD3Switch;
|
| Switch = clkDx.uctrl_ClkSwitch;
|
| Select = clkDx.uctrl_ClkSel;
|
| divider = get_divider(D3Switch, Switch, Select);
|
| PllSel = clkDx.uctrl_ClkPllSel;
|
|
|
| if (clkDx.uctrl_ClkPllSwitch)
|
| if (PllSel < 4) // AVPLL
|
| dbg_printf("%20s%20s\t%20.0f [%s]\n",
|
| g_aClocks[i], "frequency", current_freq[1][PllSel + 4] / divider, AVPLL[PllSel]);
|
| else // sysPll P (differential output)
|
| dbg_printf("%20s%20s\t%d\n", g_aClocks[i], "frequency", sysPll_diff_p / divider);
|
| else // sysPll (single ended output)
|
| dbg_printf("%20s%20s\t%d\n", g_aClocks[i], "frequency", sysPll / divider);
|
| }
|
| }
|
| #endif
|
| }
|
