berlin_tools/bootloader/board/bg2cdp_z1/power_tuning.c

/********************************************************************************
 * Marvell GPL License Option
 *
 * If you received this File from Marvell, you may opt to use, redistribute and/or
 * modify this File in accordance with the terms and conditions of the General
 * Public License Version 2, June 1991 (the "GPL License"), a copy of which is
 * available along with the File in the license.txt file or by writing to the Free
 * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
 * on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
 * DISCLAIMED.  The GPL License provides additional details about this warranty
 * disclaimer.
 ******************************************************************************/

//#include "galois_io.h"
#include "lgpl_printf.h"
#include "io.h"
#include "berlin_bootinfo.h"

#define WRITE_L_LOCAL(a,b) writel((b), (a))

void power_tuning( void )
{
	lgpl_printf(" \n------ Entered Power_measurement_script() -------\n");
#if !CDP_A0
	//*******************************************************************
	//Power down unused IPs.
	//********* V2G ¨C fully power gated *********

	// turn on isolation
	WRITE_L_LOCAL(0xF7EA0628, 0xE);
	// assert reset
	WRITE_L_LOCAL(0xF7EA0628, 0x6);
	// turn off clock
	WRITE_L_LOCAL(0xF7EA0648, 0x0);
	WRITE_L_LOCAL(0xF7EA064C, 0x0);
	// powr off
	WRITE_L_LOCAL(0xF7EA0628,0x0 );

	// ******** ZSP ¨C fully clock gated **********
	WRITE_L_LOCAL(0xF7EA0674,0x0 );

#if 0   //Commented out as ETHERNET is needed in linux boot. If turned OFF after bootup current drops by 50mA
	// ******** Ethernet controller ¨C fully clock gated **********
	WRITE_L_LOCAL(0xF7EA0630, 0x3E);
	// ******** FE PHY ¨C fully powered down **********
	WRITE_L_LOCAL(0xF7FE1404, 0x4000001);
	WRITE_L_LOCAL(0xF7FCD008, 0x7);
#endif

	// ********	Audio DAC ¨C fully powered down **********
	WRITE_L_LOCAL(0xF7D30020, 0x0);

	//********* SPDIF out ¨C fully clock gated if gating granularity allows *********
	// SPDIF uses Audio3 clock, which is shared with Mic and Primary audio channels. Shouldn't be turned off

	//********* eMMC ¨C fully clock gated if gating granularity allows *********
	// can't turn off. eMMC shares the same clock as NAND

	//********* SD encoder/VOP ¨C fully clock gated if gating granularity allows *********
	//********* Qdeo blocks (including de-int) and CMU ¨C fully clock gated if gating granularity allows *********

	//********* AUX scaler ¨C clock-gate *********;
	WRITE_L_LOCAL(0xF7F72CF0,0xCF9F );

	//********* CPCB2 ¨C fully clock gated if gating granularity allows *********
	// power down AVPLLA C[4]
	WRITE_L_LOCAL(0xF7E20060,0x200000 );

	//********* AVPLL-B - Power-down *********
	WRITE_L_LOCAL(0xF7EA0300, 0x1483814C);

	//commented out since APP is still in use
	//********* APP ¨C clock-gate *********
	WRITE_L_LOCAL(0xF7EA0660 ,0x0 );

#if 0//Song, Fix JIRA 3593. TSP needs 200MHz clock
	//********* slow down TSP clock. can't turn off for VG1 registers work in this domain *********
	WRITE_L_LOCAL(0xF7EA0678,0x2A9 );
	WRITE_L_LOCAL(0xF7EA067C, 0x2A9);
#endif

	//;;; TSI pads
	//sendln 'WD F7EA4014 0'

	//********* power off VDAC *********
	WRITE_L_LOCAL(0xF7F70058,0x0 );


	//set SDIO IDRV to 4 ZP[7:4] and ZN[11:8]
	WRITE_L_LOCAL(0xF7EA400C,0x00400443 );

	//inside loop
//	WRITE_L_LOCAL(0xF7F70068, 0x49242002);
//	WRITE_L_LOCAL(0xF7F70068,0x49242000 );
#else
        //set SDIO IDRV to 4 ZP[7:4] and ZN[11:8]
        WRITE_L_LOCAL(0xF7EA400C,0x00400447 );
#endif
	lgpl_printf(" \n------ End Power_measurement_script() ------\n");

}