| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| ////// |
| /// don't edit! auto-generated by docc: pcube_spec.h |
| //////////////////////////////////////////////////////////// |
| #ifndef pcube_spec_h |
| #define pcube_spec_h (){} |
| |
| |
| #include "ctypes.h" |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| |
| |
| |
| ////// |
| /// |
| /// $INTERFACE SemaINTR (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 mask (W-) |
| /// %unsigned 1 empty 0x0 |
| /// ### |
| /// * Enable interrupt on 'empty' condition |
| /// ### |
| /// %unsigned 1 full 0x0 |
| /// ### |
| /// * Enable interrupt on 'full' condition |
| /// ### |
| /// %unsigned 1 almostEmpty 0x0 |
| /// ### |
| /// * Enable interrupt on 'almostEmpty' condition |
| /// ### |
| /// %unsigned 1 almostFull 0x0 |
| /// ### |
| /// * Enable interrupt on 'almostFull' condition |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 4b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_SemaINTR |
| #define h_SemaINTR (){} |
| |
| #define RA_SemaINTR_mask 0x0000 |
| |
| #define BA_SemaINTR_mask_empty 0x0000 |
| #define B16SemaINTR_mask_empty 0x0000 |
| #define LSb32SemaINTR_mask_empty 0 |
| #define LSb16SemaINTR_mask_empty 0 |
| #define bSemaINTR_mask_empty 1 |
| #define MSK32SemaINTR_mask_empty 0x00000001 |
| |
| #define BA_SemaINTR_mask_full 0x0000 |
| #define B16SemaINTR_mask_full 0x0000 |
| #define LSb32SemaINTR_mask_full 1 |
| #define LSb16SemaINTR_mask_full 1 |
| #define bSemaINTR_mask_full 1 |
| #define MSK32SemaINTR_mask_full 0x00000002 |
| |
| #define BA_SemaINTR_mask_almostEmpty 0x0000 |
| #define B16SemaINTR_mask_almostEmpty 0x0000 |
| #define LSb32SemaINTR_mask_almostEmpty 2 |
| #define LSb16SemaINTR_mask_almostEmpty 2 |
| #define bSemaINTR_mask_almostEmpty 1 |
| #define MSK32SemaINTR_mask_almostEmpty 0x00000004 |
| |
| #define BA_SemaINTR_mask_almostFull 0x0000 |
| #define B16SemaINTR_mask_almostFull 0x0000 |
| #define LSb32SemaINTR_mask_almostFull 3 |
| #define LSb16SemaINTR_mask_almostFull 3 |
| #define bSemaINTR_mask_almostFull 1 |
| #define MSK32SemaINTR_mask_almostFull 0x00000008 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_SemaINTR { |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaINTR_mask_empty(r32) _BFGET_(r32, 0, 0) |
| #define SET32SemaINTR_mask_empty(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16SemaINTR_mask_empty(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaINTR_mask_empty(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaINTR_mask_full(r32) _BFGET_(r32, 1, 1) |
| #define SET32SemaINTR_mask_full(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16SemaINTR_mask_full(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaINTR_mask_full(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaINTR_mask_almostEmpty(r32) _BFGET_(r32, 2, 2) |
| #define SET32SemaINTR_mask_almostEmpty(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16SemaINTR_mask_almostEmpty(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaINTR_mask_almostEmpty(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaINTR_mask_almostFull(r32) _BFGET_(r32, 3, 3) |
| #define SET32SemaINTR_mask_almostFull(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16SemaINTR_mask_almostFull(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaINTR_mask_almostFull(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32SemaINTR_mask {\ |
| UNSG32 umask_empty : 1;\ |
| UNSG32 umask_full : 1;\ |
| UNSG32 umask_almostEmpty : 1;\ |
| UNSG32 umask_almostFull : 1;\ |
| UNSG32 RSVDx0_b4 : 28;\ |
| } |
| union { UNSG32 u32SemaINTR_mask; |
| struct w32SemaINTR_mask; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_SemaINTR; |
| |
| typedef union T32SemaINTR_mask |
| { UNSG32 u32; |
| struct w32SemaINTR_mask; |
| } T32SemaINTR_mask; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TSemaINTR_mask |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaINTR_mask; |
| }; |
| } TSemaINTR_mask; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 SemaINTR_drvrd(SIE_SemaINTR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 SemaINTR_drvwr(SIE_SemaINTR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void SemaINTR_reset(SIE_SemaINTR *p); |
| SIGN32 SemaINTR_cmp (SIE_SemaINTR *p, SIE_SemaINTR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define SemaINTR_check(p,pie,pfx,hLOG) SemaINTR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define SemaINTR_print(p, pfx,hLOG) SemaINTR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: SemaINTR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE Semaphore biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CFG (W-) |
| /// %unsigned 16 DEPTH 0xF |
| /// ### |
| /// * Max level of semaphore |
| /// * Note: write this register will trigger counter reset |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// # 0x00004 INTR |
| /// $SemaINTR INTR REG [3] |
| /// ### |
| /// * Interrupt mask for 3 CPUs |
| /// ### |
| /// @ 0x00010 mask (W-) |
| /// %unsigned 1 full 0x0 |
| /// %unsigned 1 emp 0x0 |
| /// ### |
| /// * When full bit is set to one, to the producer, the semaphore will never be full, so that the producer will never be blocked. |
| /// * When emp bit is set to one, to the consumer, the semaphore will never be empty, so that the consumer will never be blocked. |
| /// * When the emp/full bit is set, the semaphore/FIFO pointer will be maintained, but the counter will be not correct anymore. |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 20B, bits: 30b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_Semaphore |
| #define h_Semaphore (){} |
| |
| #define RA_Semaphore_CFG 0x0000 |
| |
| #define BA_Semaphore_CFG_DEPTH 0x0000 |
| #define B16Semaphore_CFG_DEPTH 0x0000 |
| #define LSb32Semaphore_CFG_DEPTH 0 |
| #define LSb16Semaphore_CFG_DEPTH 0 |
| #define bSemaphore_CFG_DEPTH 16 |
| #define MSK32Semaphore_CFG_DEPTH 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_Semaphore_INTR 0x0004 |
| /////////////////////////////////////////////////////////// |
| #define RA_Semaphore_mask 0x0010 |
| |
| #define BA_Semaphore_mask_full 0x0010 |
| #define B16Semaphore_mask_full 0x0010 |
| #define LSb32Semaphore_mask_full 0 |
| #define LSb16Semaphore_mask_full 0 |
| #define bSemaphore_mask_full 1 |
| #define MSK32Semaphore_mask_full 0x00000001 |
| |
| #define BA_Semaphore_mask_emp 0x0010 |
| #define B16Semaphore_mask_emp 0x0010 |
| #define LSb32Semaphore_mask_emp 1 |
| #define LSb16Semaphore_mask_emp 1 |
| #define bSemaphore_mask_emp 1 |
| #define MSK32Semaphore_mask_emp 0x00000002 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_Semaphore { |
| /////////////////////////////////////////////////////////// |
| #define GET32Semaphore_CFG_DEPTH(r32) _BFGET_(r32,15, 0) |
| #define SET32Semaphore_CFG_DEPTH(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16Semaphore_CFG_DEPTH(r16) _BFGET_(r16,15, 0) |
| #define SET16Semaphore_CFG_DEPTH(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32Semaphore_CFG {\ |
| UNSG32 uCFG_DEPTH : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32Semaphore_CFG; |
| struct w32Semaphore_CFG; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_SemaINTR ie_INTR[3]; |
| /////////////////////////////////////////////////////////// |
| #define GET32Semaphore_mask_full(r32) _BFGET_(r32, 0, 0) |
| #define SET32Semaphore_mask_full(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16Semaphore_mask_full(r16) _BFGET_(r16, 0, 0) |
| #define SET16Semaphore_mask_full(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32Semaphore_mask_emp(r32) _BFGET_(r32, 1, 1) |
| #define SET32Semaphore_mask_emp(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16Semaphore_mask_emp(r16) _BFGET_(r16, 1, 1) |
| #define SET16Semaphore_mask_emp(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32Semaphore_mask {\ |
| UNSG32 umask_full : 1;\ |
| UNSG32 umask_emp : 1;\ |
| UNSG32 RSVDx10_b2 : 30;\ |
| } |
| union { UNSG32 u32Semaphore_mask; |
| struct w32Semaphore_mask; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_Semaphore; |
| |
| typedef union T32Semaphore_CFG |
| { UNSG32 u32; |
| struct w32Semaphore_CFG; |
| } T32Semaphore_CFG; |
| typedef union T32Semaphore_mask |
| { UNSG32 u32; |
| struct w32Semaphore_mask; |
| } T32Semaphore_mask; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TSemaphore_CFG |
| { UNSG32 u32[1]; |
| struct { |
| struct w32Semaphore_CFG; |
| }; |
| } TSemaphore_CFG; |
| typedef union TSemaphore_mask |
| { UNSG32 u32[1]; |
| struct { |
| struct w32Semaphore_mask; |
| }; |
| } TSemaphore_mask; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 Semaphore_drvrd(SIE_Semaphore *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 Semaphore_drvwr(SIE_Semaphore *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void Semaphore_reset(SIE_Semaphore *p); |
| SIGN32 Semaphore_cmp (SIE_Semaphore *p, SIE_Semaphore *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define Semaphore_check(p,pie,pfx,hLOG) Semaphore_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define Semaphore_print(p, pfx,hLOG) Semaphore_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: Semaphore |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE SemaQuery (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 RESP (R-) |
| /// %unsigned 16 CNT |
| /// ### |
| /// * Semaphore counter level |
| /// ### |
| /// %unsigned 16 PTR |
| /// ### |
| /// * Semaphore pointer: |
| /// * producer-wptr or consumer-rptr |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_SemaQuery |
| #define h_SemaQuery (){} |
| |
| #define RA_SemaQuery_RESP 0x0000 |
| |
| #define BA_SemaQuery_RESP_CNT 0x0000 |
| #define B16SemaQuery_RESP_CNT 0x0000 |
| #define LSb32SemaQuery_RESP_CNT 0 |
| #define LSb16SemaQuery_RESP_CNT 0 |
| #define bSemaQuery_RESP_CNT 16 |
| #define MSK32SemaQuery_RESP_CNT 0x0000FFFF |
| |
| #define BA_SemaQuery_RESP_PTR 0x0002 |
| #define B16SemaQuery_RESP_PTR 0x0002 |
| #define LSb32SemaQuery_RESP_PTR 16 |
| #define LSb16SemaQuery_RESP_PTR 0 |
| #define bSemaQuery_RESP_PTR 16 |
| #define MSK32SemaQuery_RESP_PTR 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_SemaQuery { |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaQuery_RESP_CNT(r32) _BFGET_(r32,15, 0) |
| #define SET32SemaQuery_RESP_CNT(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16SemaQuery_RESP_CNT(r16) _BFGET_(r16,15, 0) |
| #define SET16SemaQuery_RESP_CNT(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32SemaQuery_RESP_PTR(r32) _BFGET_(r32,31,16) |
| #define SET32SemaQuery_RESP_PTR(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16SemaQuery_RESP_PTR(r16) _BFGET_(r16,15, 0) |
| #define SET16SemaQuery_RESP_PTR(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32SemaQuery_RESP {\ |
| UNSG32 uRESP_CNT : 16;\ |
| UNSG32 uRESP_PTR : 16;\ |
| } |
| union { UNSG32 u32SemaQuery_RESP; |
| struct w32SemaQuery_RESP; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_SemaQuery; |
| |
| typedef union T32SemaQuery_RESP |
| { UNSG32 u32; |
| struct w32SemaQuery_RESP; |
| } T32SemaQuery_RESP; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TSemaQuery_RESP |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaQuery_RESP; |
| }; |
| } TSemaQuery_RESP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 SemaQuery_drvrd(SIE_SemaQuery *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 SemaQuery_drvwr(SIE_SemaQuery *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void SemaQuery_reset(SIE_SemaQuery *p); |
| SIGN32 SemaQuery_cmp (SIE_SemaQuery *p, SIE_SemaQuery *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define SemaQuery_check(p,pie,pfx,hLOG) SemaQuery_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define SemaQuery_print(p, pfx,hLOG) SemaQuery_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: SemaQuery |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE SemaQueryMap (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ADDR (P) |
| /// %unsigned 2 byte |
| /// %unsigned 5 ID |
| /// ### |
| /// * Semaphore cell index |
| /// ### |
| /// %unsigned 1 master |
| /// : producer 0x0 |
| /// : consumer 0x1 |
| /// ### |
| /// * Select which counter to read |
| /// ### |
| /// %% 24 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 8b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_SemaQueryMap |
| #define h_SemaQueryMap (){} |
| |
| #define RA_SemaQueryMap_ADDR 0x0000 |
| |
| #define BA_SemaQueryMap_ADDR_byte 0x0000 |
| #define B16SemaQueryMap_ADDR_byte 0x0000 |
| #define LSb32SemaQueryMap_ADDR_byte 0 |
| #define LSb16SemaQueryMap_ADDR_byte 0 |
| #define bSemaQueryMap_ADDR_byte 2 |
| #define MSK32SemaQueryMap_ADDR_byte 0x00000003 |
| |
| #define BA_SemaQueryMap_ADDR_ID 0x0000 |
| #define B16SemaQueryMap_ADDR_ID 0x0000 |
| #define LSb32SemaQueryMap_ADDR_ID 2 |
| #define LSb16SemaQueryMap_ADDR_ID 2 |
| #define bSemaQueryMap_ADDR_ID 5 |
| #define MSK32SemaQueryMap_ADDR_ID 0x0000007C |
| |
| #define BA_SemaQueryMap_ADDR_master 0x0000 |
| #define B16SemaQueryMap_ADDR_master 0x0000 |
| #define LSb32SemaQueryMap_ADDR_master 7 |
| #define LSb16SemaQueryMap_ADDR_master 7 |
| #define bSemaQueryMap_ADDR_master 1 |
| #define MSK32SemaQueryMap_ADDR_master 0x00000080 |
| #define SemaQueryMap_ADDR_master_producer 0x0 |
| #define SemaQueryMap_ADDR_master_consumer 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_SemaQueryMap { |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaQueryMap_ADDR_byte(r32) _BFGET_(r32, 1, 0) |
| #define SET32SemaQueryMap_ADDR_byte(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16SemaQueryMap_ADDR_byte(r16) _BFGET_(r16, 1, 0) |
| #define SET16SemaQueryMap_ADDR_byte(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32SemaQueryMap_ADDR_ID(r32) _BFGET_(r32, 6, 2) |
| #define SET32SemaQueryMap_ADDR_ID(r32,v) _BFSET_(r32, 6, 2,v) |
| #define GET16SemaQueryMap_ADDR_ID(r16) _BFGET_(r16, 6, 2) |
| #define SET16SemaQueryMap_ADDR_ID(r16,v) _BFSET_(r16, 6, 2,v) |
| |
| #define GET32SemaQueryMap_ADDR_master(r32) _BFGET_(r32, 7, 7) |
| #define SET32SemaQueryMap_ADDR_master(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16SemaQueryMap_ADDR_master(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaQueryMap_ADDR_master(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define w32SemaQueryMap_ADDR {\ |
| UNSG32 uADDR_byte : 2;\ |
| UNSG32 uADDR_ID : 5;\ |
| UNSG32 uADDR_master : 1;\ |
| UNSG32 RSVDx0_b8 : 24;\ |
| } |
| union { UNSG32 u32SemaQueryMap_ADDR; |
| struct w32SemaQueryMap_ADDR; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_SemaQueryMap; |
| |
| typedef union T32SemaQueryMap_ADDR |
| { UNSG32 u32; |
| struct w32SemaQueryMap_ADDR; |
| } T32SemaQueryMap_ADDR; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TSemaQueryMap_ADDR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaQueryMap_ADDR; |
| }; |
| } TSemaQueryMap_ADDR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 SemaQueryMap_drvrd(SIE_SemaQueryMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 SemaQueryMap_drvwr(SIE_SemaQueryMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void SemaQueryMap_reset(SIE_SemaQueryMap *p); |
| SIGN32 SemaQueryMap_cmp (SIE_SemaQueryMap *p, SIE_SemaQueryMap *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define SemaQueryMap_check(p,pie,pfx,hLOG) SemaQueryMap_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define SemaQueryMap_print(p, pfx,hLOG) SemaQueryMap_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: SemaQueryMap |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE SemaHub biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 Query (R-) |
| /// # 0x00000 counter |
| /// $SemaQuery counter MEM [64] |
| /// ### |
| /// * Access address as defined above |
| /// ### |
| /// @ 0x00100 ARR (P) |
| /// # 0x00100 cell |
| /// $Semaphore cell REG [32] |
| /// ### |
| /// * Up-to 32 semaphore cells |
| /// ### |
| /// @ 0x00380 PUSH (W-) |
| /// %unsigned 8 ID |
| /// %unsigned 8 delta |
| /// ### |
| /// * CPU increases PCounter by delta (range from 0 to 255) |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00384 POP (W-) |
| /// %unsigned 8 ID |
| /// %unsigned 8 delta |
| /// ### |
| /// * CPU decreases CCounter by delta (range from 0 to 255) |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00388 empty (WOC-) |
| /// %unsigned 1 ST_0i 0x0 |
| /// %unsigned 1 ST_1i 0x0 |
| /// %unsigned 1 ST_2i 0x0 |
| /// %unsigned 1 ST_3i 0x0 |
| /// %unsigned 1 ST_4i 0x0 |
| /// %unsigned 1 ST_5i 0x0 |
| /// %unsigned 1 ST_6i 0x0 |
| /// %unsigned 1 ST_7i 0x0 |
| /// %unsigned 1 ST_8i 0x0 |
| /// %unsigned 1 ST_9i 0x0 |
| /// %unsigned 1 ST_10i 0x0 |
| /// %unsigned 1 ST_11i 0x0 |
| /// %unsigned 1 ST_12i 0x0 |
| /// %unsigned 1 ST_13i 0x0 |
| /// %unsigned 1 ST_14i 0x0 |
| /// %unsigned 1 ST_15i 0x0 |
| /// %unsigned 1 ST_16i 0x0 |
| /// %unsigned 1 ST_17i 0x0 |
| /// %unsigned 1 ST_18i 0x0 |
| /// %unsigned 1 ST_19i 0x0 |
| /// %unsigned 1 ST_20i 0x0 |
| /// %unsigned 1 ST_21i 0x0 |
| /// %unsigned 1 ST_22i 0x0 |
| /// %unsigned 1 ST_23i 0x0 |
| /// %unsigned 1 ST_24i 0x0 |
| /// %unsigned 1 ST_25i 0x0 |
| /// %unsigned 1 ST_26i 0x0 |
| /// %unsigned 1 ST_27i 0x0 |
| /// %unsigned 1 ST_28i 0x0 |
| /// %unsigned 1 ST_29i 0x0 |
| /// %unsigned 1 ST_30i 0x0 |
| /// %unsigned 1 ST_31i 0x0 |
| /// ### |
| /// * All cell 'empty' status |
| /// ### |
| /// @ 0x0038C full (WOC-) |
| /// %unsigned 1 ST_0i 0x0 |
| /// %unsigned 1 ST_1i 0x0 |
| /// %unsigned 1 ST_2i 0x0 |
| /// %unsigned 1 ST_3i 0x0 |
| /// %unsigned 1 ST_4i 0x0 |
| /// %unsigned 1 ST_5i 0x0 |
| /// %unsigned 1 ST_6i 0x0 |
| /// %unsigned 1 ST_7i 0x0 |
| /// %unsigned 1 ST_8i 0x0 |
| /// %unsigned 1 ST_9i 0x0 |
| /// %unsigned 1 ST_10i 0x0 |
| /// %unsigned 1 ST_11i 0x0 |
| /// %unsigned 1 ST_12i 0x0 |
| /// %unsigned 1 ST_13i 0x0 |
| /// %unsigned 1 ST_14i 0x0 |
| /// %unsigned 1 ST_15i 0x0 |
| /// %unsigned 1 ST_16i 0x0 |
| /// %unsigned 1 ST_17i 0x0 |
| /// %unsigned 1 ST_18i 0x0 |
| /// %unsigned 1 ST_19i 0x0 |
| /// %unsigned 1 ST_20i 0x0 |
| /// %unsigned 1 ST_21i 0x0 |
| /// %unsigned 1 ST_22i 0x0 |
| /// %unsigned 1 ST_23i 0x0 |
| /// %unsigned 1 ST_24i 0x0 |
| /// %unsigned 1 ST_25i 0x0 |
| /// %unsigned 1 ST_26i 0x0 |
| /// %unsigned 1 ST_27i 0x0 |
| /// %unsigned 1 ST_28i 0x0 |
| /// %unsigned 1 ST_29i 0x0 |
| /// %unsigned 1 ST_30i 0x0 |
| /// %unsigned 1 ST_31i 0x0 |
| /// ### |
| /// * All cell 'full' status |
| /// ### |
| /// @ 0x00390 almostEmpty (WOC-) |
| /// %unsigned 1 ST_0i 0x0 |
| /// %unsigned 1 ST_1i 0x0 |
| /// %unsigned 1 ST_2i 0x0 |
| /// %unsigned 1 ST_3i 0x0 |
| /// %unsigned 1 ST_4i 0x0 |
| /// %unsigned 1 ST_5i 0x0 |
| /// %unsigned 1 ST_6i 0x0 |
| /// %unsigned 1 ST_7i 0x0 |
| /// %unsigned 1 ST_8i 0x0 |
| /// %unsigned 1 ST_9i 0x0 |
| /// %unsigned 1 ST_10i 0x0 |
| /// %unsigned 1 ST_11i 0x0 |
| /// %unsigned 1 ST_12i 0x0 |
| /// %unsigned 1 ST_13i 0x0 |
| /// %unsigned 1 ST_14i 0x0 |
| /// %unsigned 1 ST_15i 0x0 |
| /// %unsigned 1 ST_16i 0x0 |
| /// %unsigned 1 ST_17i 0x0 |
| /// %unsigned 1 ST_18i 0x0 |
| /// %unsigned 1 ST_19i 0x0 |
| /// %unsigned 1 ST_20i 0x0 |
| /// %unsigned 1 ST_21i 0x0 |
| /// %unsigned 1 ST_22i 0x0 |
| /// %unsigned 1 ST_23i 0x0 |
| /// %unsigned 1 ST_24i 0x0 |
| /// %unsigned 1 ST_25i 0x0 |
| /// %unsigned 1 ST_26i 0x0 |
| /// %unsigned 1 ST_27i 0x0 |
| /// %unsigned 1 ST_28i 0x0 |
| /// %unsigned 1 ST_29i 0x0 |
| /// %unsigned 1 ST_30i 0x0 |
| /// %unsigned 1 ST_31i 0x0 |
| /// ### |
| /// * All cell 'almostEmpty' status |
| /// ### |
| /// @ 0x00394 almostFull (WOC-) |
| /// %unsigned 1 ST_0i 0x0 |
| /// %unsigned 1 ST_1i 0x0 |
| /// %unsigned 1 ST_2i 0x0 |
| /// %unsigned 1 ST_3i 0x0 |
| /// %unsigned 1 ST_4i 0x0 |
| /// %unsigned 1 ST_5i 0x0 |
| /// %unsigned 1 ST_6i 0x0 |
| /// %unsigned 1 ST_7i 0x0 |
| /// %unsigned 1 ST_8i 0x0 |
| /// %unsigned 1 ST_9i 0x0 |
| /// %unsigned 1 ST_10i 0x0 |
| /// %unsigned 1 ST_11i 0x0 |
| /// %unsigned 1 ST_12i 0x0 |
| /// %unsigned 1 ST_13i 0x0 |
| /// %unsigned 1 ST_14i 0x0 |
| /// %unsigned 1 ST_15i 0x0 |
| /// %unsigned 1 ST_16i 0x0 |
| /// %unsigned 1 ST_17i 0x0 |
| /// %unsigned 1 ST_18i 0x0 |
| /// %unsigned 1 ST_19i 0x0 |
| /// %unsigned 1 ST_20i 0x0 |
| /// %unsigned 1 ST_21i 0x0 |
| /// %unsigned 1 ST_22i 0x0 |
| /// %unsigned 1 ST_23i 0x0 |
| /// %unsigned 1 ST_24i 0x0 |
| /// %unsigned 1 ST_25i 0x0 |
| /// %unsigned 1 ST_26i 0x0 |
| /// %unsigned 1 ST_27i 0x0 |
| /// %unsigned 1 ST_28i 0x0 |
| /// %unsigned 1 ST_29i 0x0 |
| /// %unsigned 1 ST_30i 0x0 |
| /// %unsigned 1 ST_31i 0x0 |
| /// ### |
| /// * All cell 'almostFull' status |
| /// ### |
| /// @ 0x00398 (W-) |
| /// # # Stuffing bytes... |
| /// %% 832 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 1024B, bits: 1152b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_SemaHub |
| #define h_SemaHub (){} |
| |
| #define RA_SemaHub_Query 0x0000 |
| #define RA_SemaHub_counter 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_ARR 0x0100 |
| #define RA_SemaHub_cell 0x0100 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_PUSH 0x0380 |
| |
| #define BA_SemaHub_PUSH_ID 0x0380 |
| #define B16SemaHub_PUSH_ID 0x0380 |
| #define LSb32SemaHub_PUSH_ID 0 |
| #define LSb16SemaHub_PUSH_ID 0 |
| #define bSemaHub_PUSH_ID 8 |
| #define MSK32SemaHub_PUSH_ID 0x000000FF |
| |
| #define BA_SemaHub_PUSH_delta 0x0381 |
| #define B16SemaHub_PUSH_delta 0x0380 |
| #define LSb32SemaHub_PUSH_delta 8 |
| #define LSb16SemaHub_PUSH_delta 8 |
| #define bSemaHub_PUSH_delta 8 |
| #define MSK32SemaHub_PUSH_delta 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_POP 0x0384 |
| |
| #define BA_SemaHub_POP_ID 0x0384 |
| #define B16SemaHub_POP_ID 0x0384 |
| #define LSb32SemaHub_POP_ID 0 |
| #define LSb16SemaHub_POP_ID 0 |
| #define bSemaHub_POP_ID 8 |
| #define MSK32SemaHub_POP_ID 0x000000FF |
| |
| #define BA_SemaHub_POP_delta 0x0385 |
| #define B16SemaHub_POP_delta 0x0384 |
| #define LSb32SemaHub_POP_delta 8 |
| #define LSb16SemaHub_POP_delta 8 |
| #define bSemaHub_POP_delta 8 |
| #define MSK32SemaHub_POP_delta 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_empty 0x0388 |
| |
| #define BA_SemaHub_empty_ST_0i 0x0388 |
| #define B16SemaHub_empty_ST_0i 0x0388 |
| #define LSb32SemaHub_empty_ST_0i 0 |
| #define LSb16SemaHub_empty_ST_0i 0 |
| #define bSemaHub_empty_ST_0i 1 |
| #define MSK32SemaHub_empty_ST_0i 0x00000001 |
| |
| #define BA_SemaHub_empty_ST_1i 0x0388 |
| #define B16SemaHub_empty_ST_1i 0x0388 |
| #define LSb32SemaHub_empty_ST_1i 1 |
| #define LSb16SemaHub_empty_ST_1i 1 |
| #define bSemaHub_empty_ST_1i 1 |
| #define MSK32SemaHub_empty_ST_1i 0x00000002 |
| |
| #define BA_SemaHub_empty_ST_2i 0x0388 |
| #define B16SemaHub_empty_ST_2i 0x0388 |
| #define LSb32SemaHub_empty_ST_2i 2 |
| #define LSb16SemaHub_empty_ST_2i 2 |
| #define bSemaHub_empty_ST_2i 1 |
| #define MSK32SemaHub_empty_ST_2i 0x00000004 |
| |
| #define BA_SemaHub_empty_ST_3i 0x0388 |
| #define B16SemaHub_empty_ST_3i 0x0388 |
| #define LSb32SemaHub_empty_ST_3i 3 |
| #define LSb16SemaHub_empty_ST_3i 3 |
| #define bSemaHub_empty_ST_3i 1 |
| #define MSK32SemaHub_empty_ST_3i 0x00000008 |
| |
| #define BA_SemaHub_empty_ST_4i 0x0388 |
| #define B16SemaHub_empty_ST_4i 0x0388 |
| #define LSb32SemaHub_empty_ST_4i 4 |
| #define LSb16SemaHub_empty_ST_4i 4 |
| #define bSemaHub_empty_ST_4i 1 |
| #define MSK32SemaHub_empty_ST_4i 0x00000010 |
| |
| #define BA_SemaHub_empty_ST_5i 0x0388 |
| #define B16SemaHub_empty_ST_5i 0x0388 |
| #define LSb32SemaHub_empty_ST_5i 5 |
| #define LSb16SemaHub_empty_ST_5i 5 |
| #define bSemaHub_empty_ST_5i 1 |
| #define MSK32SemaHub_empty_ST_5i 0x00000020 |
| |
| #define BA_SemaHub_empty_ST_6i 0x0388 |
| #define B16SemaHub_empty_ST_6i 0x0388 |
| #define LSb32SemaHub_empty_ST_6i 6 |
| #define LSb16SemaHub_empty_ST_6i 6 |
| #define bSemaHub_empty_ST_6i 1 |
| #define MSK32SemaHub_empty_ST_6i 0x00000040 |
| |
| #define BA_SemaHub_empty_ST_7i 0x0388 |
| #define B16SemaHub_empty_ST_7i 0x0388 |
| #define LSb32SemaHub_empty_ST_7i 7 |
| #define LSb16SemaHub_empty_ST_7i 7 |
| #define bSemaHub_empty_ST_7i 1 |
| #define MSK32SemaHub_empty_ST_7i 0x00000080 |
| |
| #define BA_SemaHub_empty_ST_8i 0x0389 |
| #define B16SemaHub_empty_ST_8i 0x0388 |
| #define LSb32SemaHub_empty_ST_8i 8 |
| #define LSb16SemaHub_empty_ST_8i 8 |
| #define bSemaHub_empty_ST_8i 1 |
| #define MSK32SemaHub_empty_ST_8i 0x00000100 |
| |
| #define BA_SemaHub_empty_ST_9i 0x0389 |
| #define B16SemaHub_empty_ST_9i 0x0388 |
| #define LSb32SemaHub_empty_ST_9i 9 |
| #define LSb16SemaHub_empty_ST_9i 9 |
| #define bSemaHub_empty_ST_9i 1 |
| #define MSK32SemaHub_empty_ST_9i 0x00000200 |
| |
| #define BA_SemaHub_empty_ST_10i 0x0389 |
| #define B16SemaHub_empty_ST_10i 0x0388 |
| #define LSb32SemaHub_empty_ST_10i 10 |
| #define LSb16SemaHub_empty_ST_10i 10 |
| #define bSemaHub_empty_ST_10i 1 |
| #define MSK32SemaHub_empty_ST_10i 0x00000400 |
| |
| #define BA_SemaHub_empty_ST_11i 0x0389 |
| #define B16SemaHub_empty_ST_11i 0x0388 |
| #define LSb32SemaHub_empty_ST_11i 11 |
| #define LSb16SemaHub_empty_ST_11i 11 |
| #define bSemaHub_empty_ST_11i 1 |
| #define MSK32SemaHub_empty_ST_11i 0x00000800 |
| |
| #define BA_SemaHub_empty_ST_12i 0x0389 |
| #define B16SemaHub_empty_ST_12i 0x0388 |
| #define LSb32SemaHub_empty_ST_12i 12 |
| #define LSb16SemaHub_empty_ST_12i 12 |
| #define bSemaHub_empty_ST_12i 1 |
| #define MSK32SemaHub_empty_ST_12i 0x00001000 |
| |
| #define BA_SemaHub_empty_ST_13i 0x0389 |
| #define B16SemaHub_empty_ST_13i 0x0388 |
| #define LSb32SemaHub_empty_ST_13i 13 |
| #define LSb16SemaHub_empty_ST_13i 13 |
| #define bSemaHub_empty_ST_13i 1 |
| #define MSK32SemaHub_empty_ST_13i 0x00002000 |
| |
| #define BA_SemaHub_empty_ST_14i 0x0389 |
| #define B16SemaHub_empty_ST_14i 0x0388 |
| #define LSb32SemaHub_empty_ST_14i 14 |
| #define LSb16SemaHub_empty_ST_14i 14 |
| #define bSemaHub_empty_ST_14i 1 |
| #define MSK32SemaHub_empty_ST_14i 0x00004000 |
| |
| #define BA_SemaHub_empty_ST_15i 0x0389 |
| #define B16SemaHub_empty_ST_15i 0x0388 |
| #define LSb32SemaHub_empty_ST_15i 15 |
| #define LSb16SemaHub_empty_ST_15i 15 |
| #define bSemaHub_empty_ST_15i 1 |
| #define MSK32SemaHub_empty_ST_15i 0x00008000 |
| |
| #define BA_SemaHub_empty_ST_16i 0x038A |
| #define B16SemaHub_empty_ST_16i 0x038A |
| #define LSb32SemaHub_empty_ST_16i 16 |
| #define LSb16SemaHub_empty_ST_16i 0 |
| #define bSemaHub_empty_ST_16i 1 |
| #define MSK32SemaHub_empty_ST_16i 0x00010000 |
| |
| #define BA_SemaHub_empty_ST_17i 0x038A |
| #define B16SemaHub_empty_ST_17i 0x038A |
| #define LSb32SemaHub_empty_ST_17i 17 |
| #define LSb16SemaHub_empty_ST_17i 1 |
| #define bSemaHub_empty_ST_17i 1 |
| #define MSK32SemaHub_empty_ST_17i 0x00020000 |
| |
| #define BA_SemaHub_empty_ST_18i 0x038A |
| #define B16SemaHub_empty_ST_18i 0x038A |
| #define LSb32SemaHub_empty_ST_18i 18 |
| #define LSb16SemaHub_empty_ST_18i 2 |
| #define bSemaHub_empty_ST_18i 1 |
| #define MSK32SemaHub_empty_ST_18i 0x00040000 |
| |
| #define BA_SemaHub_empty_ST_19i 0x038A |
| #define B16SemaHub_empty_ST_19i 0x038A |
| #define LSb32SemaHub_empty_ST_19i 19 |
| #define LSb16SemaHub_empty_ST_19i 3 |
| #define bSemaHub_empty_ST_19i 1 |
| #define MSK32SemaHub_empty_ST_19i 0x00080000 |
| |
| #define BA_SemaHub_empty_ST_20i 0x038A |
| #define B16SemaHub_empty_ST_20i 0x038A |
| #define LSb32SemaHub_empty_ST_20i 20 |
| #define LSb16SemaHub_empty_ST_20i 4 |
| #define bSemaHub_empty_ST_20i 1 |
| #define MSK32SemaHub_empty_ST_20i 0x00100000 |
| |
| #define BA_SemaHub_empty_ST_21i 0x038A |
| #define B16SemaHub_empty_ST_21i 0x038A |
| #define LSb32SemaHub_empty_ST_21i 21 |
| #define LSb16SemaHub_empty_ST_21i 5 |
| #define bSemaHub_empty_ST_21i 1 |
| #define MSK32SemaHub_empty_ST_21i 0x00200000 |
| |
| #define BA_SemaHub_empty_ST_22i 0x038A |
| #define B16SemaHub_empty_ST_22i 0x038A |
| #define LSb32SemaHub_empty_ST_22i 22 |
| #define LSb16SemaHub_empty_ST_22i 6 |
| #define bSemaHub_empty_ST_22i 1 |
| #define MSK32SemaHub_empty_ST_22i 0x00400000 |
| |
| #define BA_SemaHub_empty_ST_23i 0x038A |
| #define B16SemaHub_empty_ST_23i 0x038A |
| #define LSb32SemaHub_empty_ST_23i 23 |
| #define LSb16SemaHub_empty_ST_23i 7 |
| #define bSemaHub_empty_ST_23i 1 |
| #define MSK32SemaHub_empty_ST_23i 0x00800000 |
| |
| #define BA_SemaHub_empty_ST_24i 0x038B |
| #define B16SemaHub_empty_ST_24i 0x038A |
| #define LSb32SemaHub_empty_ST_24i 24 |
| #define LSb16SemaHub_empty_ST_24i 8 |
| #define bSemaHub_empty_ST_24i 1 |
| #define MSK32SemaHub_empty_ST_24i 0x01000000 |
| |
| #define BA_SemaHub_empty_ST_25i 0x038B |
| #define B16SemaHub_empty_ST_25i 0x038A |
| #define LSb32SemaHub_empty_ST_25i 25 |
| #define LSb16SemaHub_empty_ST_25i 9 |
| #define bSemaHub_empty_ST_25i 1 |
| #define MSK32SemaHub_empty_ST_25i 0x02000000 |
| |
| #define BA_SemaHub_empty_ST_26i 0x038B |
| #define B16SemaHub_empty_ST_26i 0x038A |
| #define LSb32SemaHub_empty_ST_26i 26 |
| #define LSb16SemaHub_empty_ST_26i 10 |
| #define bSemaHub_empty_ST_26i 1 |
| #define MSK32SemaHub_empty_ST_26i 0x04000000 |
| |
| #define BA_SemaHub_empty_ST_27i 0x038B |
| #define B16SemaHub_empty_ST_27i 0x038A |
| #define LSb32SemaHub_empty_ST_27i 27 |
| #define LSb16SemaHub_empty_ST_27i 11 |
| #define bSemaHub_empty_ST_27i 1 |
| #define MSK32SemaHub_empty_ST_27i 0x08000000 |
| |
| #define BA_SemaHub_empty_ST_28i 0x038B |
| #define B16SemaHub_empty_ST_28i 0x038A |
| #define LSb32SemaHub_empty_ST_28i 28 |
| #define LSb16SemaHub_empty_ST_28i 12 |
| #define bSemaHub_empty_ST_28i 1 |
| #define MSK32SemaHub_empty_ST_28i 0x10000000 |
| |
| #define BA_SemaHub_empty_ST_29i 0x038B |
| #define B16SemaHub_empty_ST_29i 0x038A |
| #define LSb32SemaHub_empty_ST_29i 29 |
| #define LSb16SemaHub_empty_ST_29i 13 |
| #define bSemaHub_empty_ST_29i 1 |
| #define MSK32SemaHub_empty_ST_29i 0x20000000 |
| |
| #define BA_SemaHub_empty_ST_30i 0x038B |
| #define B16SemaHub_empty_ST_30i 0x038A |
| #define LSb32SemaHub_empty_ST_30i 30 |
| #define LSb16SemaHub_empty_ST_30i 14 |
| #define bSemaHub_empty_ST_30i 1 |
| #define MSK32SemaHub_empty_ST_30i 0x40000000 |
| |
| #define BA_SemaHub_empty_ST_31i 0x038B |
| #define B16SemaHub_empty_ST_31i 0x038A |
| #define LSb32SemaHub_empty_ST_31i 31 |
| #define LSb16SemaHub_empty_ST_31i 15 |
| #define bSemaHub_empty_ST_31i 1 |
| #define MSK32SemaHub_empty_ST_31i 0x80000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_full 0x038C |
| |
| #define BA_SemaHub_full_ST_0i 0x038C |
| #define B16SemaHub_full_ST_0i 0x038C |
| #define LSb32SemaHub_full_ST_0i 0 |
| #define LSb16SemaHub_full_ST_0i 0 |
| #define bSemaHub_full_ST_0i 1 |
| #define MSK32SemaHub_full_ST_0i 0x00000001 |
| |
| #define BA_SemaHub_full_ST_1i 0x038C |
| #define B16SemaHub_full_ST_1i 0x038C |
| #define LSb32SemaHub_full_ST_1i 1 |
| #define LSb16SemaHub_full_ST_1i 1 |
| #define bSemaHub_full_ST_1i 1 |
| #define MSK32SemaHub_full_ST_1i 0x00000002 |
| |
| #define BA_SemaHub_full_ST_2i 0x038C |
| #define B16SemaHub_full_ST_2i 0x038C |
| #define LSb32SemaHub_full_ST_2i 2 |
| #define LSb16SemaHub_full_ST_2i 2 |
| #define bSemaHub_full_ST_2i 1 |
| #define MSK32SemaHub_full_ST_2i 0x00000004 |
| |
| #define BA_SemaHub_full_ST_3i 0x038C |
| #define B16SemaHub_full_ST_3i 0x038C |
| #define LSb32SemaHub_full_ST_3i 3 |
| #define LSb16SemaHub_full_ST_3i 3 |
| #define bSemaHub_full_ST_3i 1 |
| #define MSK32SemaHub_full_ST_3i 0x00000008 |
| |
| #define BA_SemaHub_full_ST_4i 0x038C |
| #define B16SemaHub_full_ST_4i 0x038C |
| #define LSb32SemaHub_full_ST_4i 4 |
| #define LSb16SemaHub_full_ST_4i 4 |
| #define bSemaHub_full_ST_4i 1 |
| #define MSK32SemaHub_full_ST_4i 0x00000010 |
| |
| #define BA_SemaHub_full_ST_5i 0x038C |
| #define B16SemaHub_full_ST_5i 0x038C |
| #define LSb32SemaHub_full_ST_5i 5 |
| #define LSb16SemaHub_full_ST_5i 5 |
| #define bSemaHub_full_ST_5i 1 |
| #define MSK32SemaHub_full_ST_5i 0x00000020 |
| |
| #define BA_SemaHub_full_ST_6i 0x038C |
| #define B16SemaHub_full_ST_6i 0x038C |
| #define LSb32SemaHub_full_ST_6i 6 |
| #define LSb16SemaHub_full_ST_6i 6 |
| #define bSemaHub_full_ST_6i 1 |
| #define MSK32SemaHub_full_ST_6i 0x00000040 |
| |
| #define BA_SemaHub_full_ST_7i 0x038C |
| #define B16SemaHub_full_ST_7i 0x038C |
| #define LSb32SemaHub_full_ST_7i 7 |
| #define LSb16SemaHub_full_ST_7i 7 |
| #define bSemaHub_full_ST_7i 1 |
| #define MSK32SemaHub_full_ST_7i 0x00000080 |
| |
| #define BA_SemaHub_full_ST_8i 0x038D |
| #define B16SemaHub_full_ST_8i 0x038C |
| #define LSb32SemaHub_full_ST_8i 8 |
| #define LSb16SemaHub_full_ST_8i 8 |
| #define bSemaHub_full_ST_8i 1 |
| #define MSK32SemaHub_full_ST_8i 0x00000100 |
| |
| #define BA_SemaHub_full_ST_9i 0x038D |
| #define B16SemaHub_full_ST_9i 0x038C |
| #define LSb32SemaHub_full_ST_9i 9 |
| #define LSb16SemaHub_full_ST_9i 9 |
| #define bSemaHub_full_ST_9i 1 |
| #define MSK32SemaHub_full_ST_9i 0x00000200 |
| |
| #define BA_SemaHub_full_ST_10i 0x038D |
| #define B16SemaHub_full_ST_10i 0x038C |
| #define LSb32SemaHub_full_ST_10i 10 |
| #define LSb16SemaHub_full_ST_10i 10 |
| #define bSemaHub_full_ST_10i 1 |
| #define MSK32SemaHub_full_ST_10i 0x00000400 |
| |
| #define BA_SemaHub_full_ST_11i 0x038D |
| #define B16SemaHub_full_ST_11i 0x038C |
| #define LSb32SemaHub_full_ST_11i 11 |
| #define LSb16SemaHub_full_ST_11i 11 |
| #define bSemaHub_full_ST_11i 1 |
| #define MSK32SemaHub_full_ST_11i 0x00000800 |
| |
| #define BA_SemaHub_full_ST_12i 0x038D |
| #define B16SemaHub_full_ST_12i 0x038C |
| #define LSb32SemaHub_full_ST_12i 12 |
| #define LSb16SemaHub_full_ST_12i 12 |
| #define bSemaHub_full_ST_12i 1 |
| #define MSK32SemaHub_full_ST_12i 0x00001000 |
| |
| #define BA_SemaHub_full_ST_13i 0x038D |
| #define B16SemaHub_full_ST_13i 0x038C |
| #define LSb32SemaHub_full_ST_13i 13 |
| #define LSb16SemaHub_full_ST_13i 13 |
| #define bSemaHub_full_ST_13i 1 |
| #define MSK32SemaHub_full_ST_13i 0x00002000 |
| |
| #define BA_SemaHub_full_ST_14i 0x038D |
| #define B16SemaHub_full_ST_14i 0x038C |
| #define LSb32SemaHub_full_ST_14i 14 |
| #define LSb16SemaHub_full_ST_14i 14 |
| #define bSemaHub_full_ST_14i 1 |
| #define MSK32SemaHub_full_ST_14i 0x00004000 |
| |
| #define BA_SemaHub_full_ST_15i 0x038D |
| #define B16SemaHub_full_ST_15i 0x038C |
| #define LSb32SemaHub_full_ST_15i 15 |
| #define LSb16SemaHub_full_ST_15i 15 |
| #define bSemaHub_full_ST_15i 1 |
| #define MSK32SemaHub_full_ST_15i 0x00008000 |
| |
| #define BA_SemaHub_full_ST_16i 0x038E |
| #define B16SemaHub_full_ST_16i 0x038E |
| #define LSb32SemaHub_full_ST_16i 16 |
| #define LSb16SemaHub_full_ST_16i 0 |
| #define bSemaHub_full_ST_16i 1 |
| #define MSK32SemaHub_full_ST_16i 0x00010000 |
| |
| #define BA_SemaHub_full_ST_17i 0x038E |
| #define B16SemaHub_full_ST_17i 0x038E |
| #define LSb32SemaHub_full_ST_17i 17 |
| #define LSb16SemaHub_full_ST_17i 1 |
| #define bSemaHub_full_ST_17i 1 |
| #define MSK32SemaHub_full_ST_17i 0x00020000 |
| |
| #define BA_SemaHub_full_ST_18i 0x038E |
| #define B16SemaHub_full_ST_18i 0x038E |
| #define LSb32SemaHub_full_ST_18i 18 |
| #define LSb16SemaHub_full_ST_18i 2 |
| #define bSemaHub_full_ST_18i 1 |
| #define MSK32SemaHub_full_ST_18i 0x00040000 |
| |
| #define BA_SemaHub_full_ST_19i 0x038E |
| #define B16SemaHub_full_ST_19i 0x038E |
| #define LSb32SemaHub_full_ST_19i 19 |
| #define LSb16SemaHub_full_ST_19i 3 |
| #define bSemaHub_full_ST_19i 1 |
| #define MSK32SemaHub_full_ST_19i 0x00080000 |
| |
| #define BA_SemaHub_full_ST_20i 0x038E |
| #define B16SemaHub_full_ST_20i 0x038E |
| #define LSb32SemaHub_full_ST_20i 20 |
| #define LSb16SemaHub_full_ST_20i 4 |
| #define bSemaHub_full_ST_20i 1 |
| #define MSK32SemaHub_full_ST_20i 0x00100000 |
| |
| #define BA_SemaHub_full_ST_21i 0x038E |
| #define B16SemaHub_full_ST_21i 0x038E |
| #define LSb32SemaHub_full_ST_21i 21 |
| #define LSb16SemaHub_full_ST_21i 5 |
| #define bSemaHub_full_ST_21i 1 |
| #define MSK32SemaHub_full_ST_21i 0x00200000 |
| |
| #define BA_SemaHub_full_ST_22i 0x038E |
| #define B16SemaHub_full_ST_22i 0x038E |
| #define LSb32SemaHub_full_ST_22i 22 |
| #define LSb16SemaHub_full_ST_22i 6 |
| #define bSemaHub_full_ST_22i 1 |
| #define MSK32SemaHub_full_ST_22i 0x00400000 |
| |
| #define BA_SemaHub_full_ST_23i 0x038E |
| #define B16SemaHub_full_ST_23i 0x038E |
| #define LSb32SemaHub_full_ST_23i 23 |
| #define LSb16SemaHub_full_ST_23i 7 |
| #define bSemaHub_full_ST_23i 1 |
| #define MSK32SemaHub_full_ST_23i 0x00800000 |
| |
| #define BA_SemaHub_full_ST_24i 0x038F |
| #define B16SemaHub_full_ST_24i 0x038E |
| #define LSb32SemaHub_full_ST_24i 24 |
| #define LSb16SemaHub_full_ST_24i 8 |
| #define bSemaHub_full_ST_24i 1 |
| #define MSK32SemaHub_full_ST_24i 0x01000000 |
| |
| #define BA_SemaHub_full_ST_25i 0x038F |
| #define B16SemaHub_full_ST_25i 0x038E |
| #define LSb32SemaHub_full_ST_25i 25 |
| #define LSb16SemaHub_full_ST_25i 9 |
| #define bSemaHub_full_ST_25i 1 |
| #define MSK32SemaHub_full_ST_25i 0x02000000 |
| |
| #define BA_SemaHub_full_ST_26i 0x038F |
| #define B16SemaHub_full_ST_26i 0x038E |
| #define LSb32SemaHub_full_ST_26i 26 |
| #define LSb16SemaHub_full_ST_26i 10 |
| #define bSemaHub_full_ST_26i 1 |
| #define MSK32SemaHub_full_ST_26i 0x04000000 |
| |
| #define BA_SemaHub_full_ST_27i 0x038F |
| #define B16SemaHub_full_ST_27i 0x038E |
| #define LSb32SemaHub_full_ST_27i 27 |
| #define LSb16SemaHub_full_ST_27i 11 |
| #define bSemaHub_full_ST_27i 1 |
| #define MSK32SemaHub_full_ST_27i 0x08000000 |
| |
| #define BA_SemaHub_full_ST_28i 0x038F |
| #define B16SemaHub_full_ST_28i 0x038E |
| #define LSb32SemaHub_full_ST_28i 28 |
| #define LSb16SemaHub_full_ST_28i 12 |
| #define bSemaHub_full_ST_28i 1 |
| #define MSK32SemaHub_full_ST_28i 0x10000000 |
| |
| #define BA_SemaHub_full_ST_29i 0x038F |
| #define B16SemaHub_full_ST_29i 0x038E |
| #define LSb32SemaHub_full_ST_29i 29 |
| #define LSb16SemaHub_full_ST_29i 13 |
| #define bSemaHub_full_ST_29i 1 |
| #define MSK32SemaHub_full_ST_29i 0x20000000 |
| |
| #define BA_SemaHub_full_ST_30i 0x038F |
| #define B16SemaHub_full_ST_30i 0x038E |
| #define LSb32SemaHub_full_ST_30i 30 |
| #define LSb16SemaHub_full_ST_30i 14 |
| #define bSemaHub_full_ST_30i 1 |
| #define MSK32SemaHub_full_ST_30i 0x40000000 |
| |
| #define BA_SemaHub_full_ST_31i 0x038F |
| #define B16SemaHub_full_ST_31i 0x038E |
| #define LSb32SemaHub_full_ST_31i 31 |
| #define LSb16SemaHub_full_ST_31i 15 |
| #define bSemaHub_full_ST_31i 1 |
| #define MSK32SemaHub_full_ST_31i 0x80000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_almostEmpty 0x0390 |
| |
| #define BA_SemaHub_almostEmpty_ST_0i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_0i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_0i 0 |
| #define LSb16SemaHub_almostEmpty_ST_0i 0 |
| #define bSemaHub_almostEmpty_ST_0i 1 |
| #define MSK32SemaHub_almostEmpty_ST_0i 0x00000001 |
| |
| #define BA_SemaHub_almostEmpty_ST_1i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_1i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_1i 1 |
| #define LSb16SemaHub_almostEmpty_ST_1i 1 |
| #define bSemaHub_almostEmpty_ST_1i 1 |
| #define MSK32SemaHub_almostEmpty_ST_1i 0x00000002 |
| |
| #define BA_SemaHub_almostEmpty_ST_2i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_2i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_2i 2 |
| #define LSb16SemaHub_almostEmpty_ST_2i 2 |
| #define bSemaHub_almostEmpty_ST_2i 1 |
| #define MSK32SemaHub_almostEmpty_ST_2i 0x00000004 |
| |
| #define BA_SemaHub_almostEmpty_ST_3i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_3i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_3i 3 |
| #define LSb16SemaHub_almostEmpty_ST_3i 3 |
| #define bSemaHub_almostEmpty_ST_3i 1 |
| #define MSK32SemaHub_almostEmpty_ST_3i 0x00000008 |
| |
| #define BA_SemaHub_almostEmpty_ST_4i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_4i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_4i 4 |
| #define LSb16SemaHub_almostEmpty_ST_4i 4 |
| #define bSemaHub_almostEmpty_ST_4i 1 |
| #define MSK32SemaHub_almostEmpty_ST_4i 0x00000010 |
| |
| #define BA_SemaHub_almostEmpty_ST_5i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_5i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_5i 5 |
| #define LSb16SemaHub_almostEmpty_ST_5i 5 |
| #define bSemaHub_almostEmpty_ST_5i 1 |
| #define MSK32SemaHub_almostEmpty_ST_5i 0x00000020 |
| |
| #define BA_SemaHub_almostEmpty_ST_6i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_6i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_6i 6 |
| #define LSb16SemaHub_almostEmpty_ST_6i 6 |
| #define bSemaHub_almostEmpty_ST_6i 1 |
| #define MSK32SemaHub_almostEmpty_ST_6i 0x00000040 |
| |
| #define BA_SemaHub_almostEmpty_ST_7i 0x0390 |
| #define B16SemaHub_almostEmpty_ST_7i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_7i 7 |
| #define LSb16SemaHub_almostEmpty_ST_7i 7 |
| #define bSemaHub_almostEmpty_ST_7i 1 |
| #define MSK32SemaHub_almostEmpty_ST_7i 0x00000080 |
| |
| #define BA_SemaHub_almostEmpty_ST_8i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_8i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_8i 8 |
| #define LSb16SemaHub_almostEmpty_ST_8i 8 |
| #define bSemaHub_almostEmpty_ST_8i 1 |
| #define MSK32SemaHub_almostEmpty_ST_8i 0x00000100 |
| |
| #define BA_SemaHub_almostEmpty_ST_9i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_9i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_9i 9 |
| #define LSb16SemaHub_almostEmpty_ST_9i 9 |
| #define bSemaHub_almostEmpty_ST_9i 1 |
| #define MSK32SemaHub_almostEmpty_ST_9i 0x00000200 |
| |
| #define BA_SemaHub_almostEmpty_ST_10i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_10i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_10i 10 |
| #define LSb16SemaHub_almostEmpty_ST_10i 10 |
| #define bSemaHub_almostEmpty_ST_10i 1 |
| #define MSK32SemaHub_almostEmpty_ST_10i 0x00000400 |
| |
| #define BA_SemaHub_almostEmpty_ST_11i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_11i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_11i 11 |
| #define LSb16SemaHub_almostEmpty_ST_11i 11 |
| #define bSemaHub_almostEmpty_ST_11i 1 |
| #define MSK32SemaHub_almostEmpty_ST_11i 0x00000800 |
| |
| #define BA_SemaHub_almostEmpty_ST_12i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_12i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_12i 12 |
| #define LSb16SemaHub_almostEmpty_ST_12i 12 |
| #define bSemaHub_almostEmpty_ST_12i 1 |
| #define MSK32SemaHub_almostEmpty_ST_12i 0x00001000 |
| |
| #define BA_SemaHub_almostEmpty_ST_13i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_13i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_13i 13 |
| #define LSb16SemaHub_almostEmpty_ST_13i 13 |
| #define bSemaHub_almostEmpty_ST_13i 1 |
| #define MSK32SemaHub_almostEmpty_ST_13i 0x00002000 |
| |
| #define BA_SemaHub_almostEmpty_ST_14i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_14i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_14i 14 |
| #define LSb16SemaHub_almostEmpty_ST_14i 14 |
| #define bSemaHub_almostEmpty_ST_14i 1 |
| #define MSK32SemaHub_almostEmpty_ST_14i 0x00004000 |
| |
| #define BA_SemaHub_almostEmpty_ST_15i 0x0391 |
| #define B16SemaHub_almostEmpty_ST_15i 0x0390 |
| #define LSb32SemaHub_almostEmpty_ST_15i 15 |
| #define LSb16SemaHub_almostEmpty_ST_15i 15 |
| #define bSemaHub_almostEmpty_ST_15i 1 |
| #define MSK32SemaHub_almostEmpty_ST_15i 0x00008000 |
| |
| #define BA_SemaHub_almostEmpty_ST_16i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_16i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_16i 16 |
| #define LSb16SemaHub_almostEmpty_ST_16i 0 |
| #define bSemaHub_almostEmpty_ST_16i 1 |
| #define MSK32SemaHub_almostEmpty_ST_16i 0x00010000 |
| |
| #define BA_SemaHub_almostEmpty_ST_17i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_17i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_17i 17 |
| #define LSb16SemaHub_almostEmpty_ST_17i 1 |
| #define bSemaHub_almostEmpty_ST_17i 1 |
| #define MSK32SemaHub_almostEmpty_ST_17i 0x00020000 |
| |
| #define BA_SemaHub_almostEmpty_ST_18i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_18i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_18i 18 |
| #define LSb16SemaHub_almostEmpty_ST_18i 2 |
| #define bSemaHub_almostEmpty_ST_18i 1 |
| #define MSK32SemaHub_almostEmpty_ST_18i 0x00040000 |
| |
| #define BA_SemaHub_almostEmpty_ST_19i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_19i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_19i 19 |
| #define LSb16SemaHub_almostEmpty_ST_19i 3 |
| #define bSemaHub_almostEmpty_ST_19i 1 |
| #define MSK32SemaHub_almostEmpty_ST_19i 0x00080000 |
| |
| #define BA_SemaHub_almostEmpty_ST_20i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_20i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_20i 20 |
| #define LSb16SemaHub_almostEmpty_ST_20i 4 |
| #define bSemaHub_almostEmpty_ST_20i 1 |
| #define MSK32SemaHub_almostEmpty_ST_20i 0x00100000 |
| |
| #define BA_SemaHub_almostEmpty_ST_21i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_21i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_21i 21 |
| #define LSb16SemaHub_almostEmpty_ST_21i 5 |
| #define bSemaHub_almostEmpty_ST_21i 1 |
| #define MSK32SemaHub_almostEmpty_ST_21i 0x00200000 |
| |
| #define BA_SemaHub_almostEmpty_ST_22i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_22i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_22i 22 |
| #define LSb16SemaHub_almostEmpty_ST_22i 6 |
| #define bSemaHub_almostEmpty_ST_22i 1 |
| #define MSK32SemaHub_almostEmpty_ST_22i 0x00400000 |
| |
| #define BA_SemaHub_almostEmpty_ST_23i 0x0392 |
| #define B16SemaHub_almostEmpty_ST_23i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_23i 23 |
| #define LSb16SemaHub_almostEmpty_ST_23i 7 |
| #define bSemaHub_almostEmpty_ST_23i 1 |
| #define MSK32SemaHub_almostEmpty_ST_23i 0x00800000 |
| |
| #define BA_SemaHub_almostEmpty_ST_24i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_24i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_24i 24 |
| #define LSb16SemaHub_almostEmpty_ST_24i 8 |
| #define bSemaHub_almostEmpty_ST_24i 1 |
| #define MSK32SemaHub_almostEmpty_ST_24i 0x01000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_25i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_25i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_25i 25 |
| #define LSb16SemaHub_almostEmpty_ST_25i 9 |
| #define bSemaHub_almostEmpty_ST_25i 1 |
| #define MSK32SemaHub_almostEmpty_ST_25i 0x02000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_26i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_26i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_26i 26 |
| #define LSb16SemaHub_almostEmpty_ST_26i 10 |
| #define bSemaHub_almostEmpty_ST_26i 1 |
| #define MSK32SemaHub_almostEmpty_ST_26i 0x04000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_27i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_27i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_27i 27 |
| #define LSb16SemaHub_almostEmpty_ST_27i 11 |
| #define bSemaHub_almostEmpty_ST_27i 1 |
| #define MSK32SemaHub_almostEmpty_ST_27i 0x08000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_28i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_28i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_28i 28 |
| #define LSb16SemaHub_almostEmpty_ST_28i 12 |
| #define bSemaHub_almostEmpty_ST_28i 1 |
| #define MSK32SemaHub_almostEmpty_ST_28i 0x10000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_29i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_29i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_29i 29 |
| #define LSb16SemaHub_almostEmpty_ST_29i 13 |
| #define bSemaHub_almostEmpty_ST_29i 1 |
| #define MSK32SemaHub_almostEmpty_ST_29i 0x20000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_30i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_30i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_30i 30 |
| #define LSb16SemaHub_almostEmpty_ST_30i 14 |
| #define bSemaHub_almostEmpty_ST_30i 1 |
| #define MSK32SemaHub_almostEmpty_ST_30i 0x40000000 |
| |
| #define BA_SemaHub_almostEmpty_ST_31i 0x0393 |
| #define B16SemaHub_almostEmpty_ST_31i 0x0392 |
| #define LSb32SemaHub_almostEmpty_ST_31i 31 |
| #define LSb16SemaHub_almostEmpty_ST_31i 15 |
| #define bSemaHub_almostEmpty_ST_31i 1 |
| #define MSK32SemaHub_almostEmpty_ST_31i 0x80000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_SemaHub_almostFull 0x0394 |
| |
| #define BA_SemaHub_almostFull_ST_0i 0x0394 |
| #define B16SemaHub_almostFull_ST_0i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_0i 0 |
| #define LSb16SemaHub_almostFull_ST_0i 0 |
| #define bSemaHub_almostFull_ST_0i 1 |
| #define MSK32SemaHub_almostFull_ST_0i 0x00000001 |
| |
| #define BA_SemaHub_almostFull_ST_1i 0x0394 |
| #define B16SemaHub_almostFull_ST_1i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_1i 1 |
| #define LSb16SemaHub_almostFull_ST_1i 1 |
| #define bSemaHub_almostFull_ST_1i 1 |
| #define MSK32SemaHub_almostFull_ST_1i 0x00000002 |
| |
| #define BA_SemaHub_almostFull_ST_2i 0x0394 |
| #define B16SemaHub_almostFull_ST_2i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_2i 2 |
| #define LSb16SemaHub_almostFull_ST_2i 2 |
| #define bSemaHub_almostFull_ST_2i 1 |
| #define MSK32SemaHub_almostFull_ST_2i 0x00000004 |
| |
| #define BA_SemaHub_almostFull_ST_3i 0x0394 |
| #define B16SemaHub_almostFull_ST_3i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_3i 3 |
| #define LSb16SemaHub_almostFull_ST_3i 3 |
| #define bSemaHub_almostFull_ST_3i 1 |
| #define MSK32SemaHub_almostFull_ST_3i 0x00000008 |
| |
| #define BA_SemaHub_almostFull_ST_4i 0x0394 |
| #define B16SemaHub_almostFull_ST_4i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_4i 4 |
| #define LSb16SemaHub_almostFull_ST_4i 4 |
| #define bSemaHub_almostFull_ST_4i 1 |
| #define MSK32SemaHub_almostFull_ST_4i 0x00000010 |
| |
| #define BA_SemaHub_almostFull_ST_5i 0x0394 |
| #define B16SemaHub_almostFull_ST_5i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_5i 5 |
| #define LSb16SemaHub_almostFull_ST_5i 5 |
| #define bSemaHub_almostFull_ST_5i 1 |
| #define MSK32SemaHub_almostFull_ST_5i 0x00000020 |
| |
| #define BA_SemaHub_almostFull_ST_6i 0x0394 |
| #define B16SemaHub_almostFull_ST_6i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_6i 6 |
| #define LSb16SemaHub_almostFull_ST_6i 6 |
| #define bSemaHub_almostFull_ST_6i 1 |
| #define MSK32SemaHub_almostFull_ST_6i 0x00000040 |
| |
| #define BA_SemaHub_almostFull_ST_7i 0x0394 |
| #define B16SemaHub_almostFull_ST_7i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_7i 7 |
| #define LSb16SemaHub_almostFull_ST_7i 7 |
| #define bSemaHub_almostFull_ST_7i 1 |
| #define MSK32SemaHub_almostFull_ST_7i 0x00000080 |
| |
| #define BA_SemaHub_almostFull_ST_8i 0x0395 |
| #define B16SemaHub_almostFull_ST_8i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_8i 8 |
| #define LSb16SemaHub_almostFull_ST_8i 8 |
| #define bSemaHub_almostFull_ST_8i 1 |
| #define MSK32SemaHub_almostFull_ST_8i 0x00000100 |
| |
| #define BA_SemaHub_almostFull_ST_9i 0x0395 |
| #define B16SemaHub_almostFull_ST_9i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_9i 9 |
| #define LSb16SemaHub_almostFull_ST_9i 9 |
| #define bSemaHub_almostFull_ST_9i 1 |
| #define MSK32SemaHub_almostFull_ST_9i 0x00000200 |
| |
| #define BA_SemaHub_almostFull_ST_10i 0x0395 |
| #define B16SemaHub_almostFull_ST_10i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_10i 10 |
| #define LSb16SemaHub_almostFull_ST_10i 10 |
| #define bSemaHub_almostFull_ST_10i 1 |
| #define MSK32SemaHub_almostFull_ST_10i 0x00000400 |
| |
| #define BA_SemaHub_almostFull_ST_11i 0x0395 |
| #define B16SemaHub_almostFull_ST_11i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_11i 11 |
| #define LSb16SemaHub_almostFull_ST_11i 11 |
| #define bSemaHub_almostFull_ST_11i 1 |
| #define MSK32SemaHub_almostFull_ST_11i 0x00000800 |
| |
| #define BA_SemaHub_almostFull_ST_12i 0x0395 |
| #define B16SemaHub_almostFull_ST_12i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_12i 12 |
| #define LSb16SemaHub_almostFull_ST_12i 12 |
| #define bSemaHub_almostFull_ST_12i 1 |
| #define MSK32SemaHub_almostFull_ST_12i 0x00001000 |
| |
| #define BA_SemaHub_almostFull_ST_13i 0x0395 |
| #define B16SemaHub_almostFull_ST_13i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_13i 13 |
| #define LSb16SemaHub_almostFull_ST_13i 13 |
| #define bSemaHub_almostFull_ST_13i 1 |
| #define MSK32SemaHub_almostFull_ST_13i 0x00002000 |
| |
| #define BA_SemaHub_almostFull_ST_14i 0x0395 |
| #define B16SemaHub_almostFull_ST_14i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_14i 14 |
| #define LSb16SemaHub_almostFull_ST_14i 14 |
| #define bSemaHub_almostFull_ST_14i 1 |
| #define MSK32SemaHub_almostFull_ST_14i 0x00004000 |
| |
| #define BA_SemaHub_almostFull_ST_15i 0x0395 |
| #define B16SemaHub_almostFull_ST_15i 0x0394 |
| #define LSb32SemaHub_almostFull_ST_15i 15 |
| #define LSb16SemaHub_almostFull_ST_15i 15 |
| #define bSemaHub_almostFull_ST_15i 1 |
| #define MSK32SemaHub_almostFull_ST_15i 0x00008000 |
| |
| #define BA_SemaHub_almostFull_ST_16i 0x0396 |
| #define B16SemaHub_almostFull_ST_16i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_16i 16 |
| #define LSb16SemaHub_almostFull_ST_16i 0 |
| #define bSemaHub_almostFull_ST_16i 1 |
| #define MSK32SemaHub_almostFull_ST_16i 0x00010000 |
| |
| #define BA_SemaHub_almostFull_ST_17i 0x0396 |
| #define B16SemaHub_almostFull_ST_17i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_17i 17 |
| #define LSb16SemaHub_almostFull_ST_17i 1 |
| #define bSemaHub_almostFull_ST_17i 1 |
| #define MSK32SemaHub_almostFull_ST_17i 0x00020000 |
| |
| #define BA_SemaHub_almostFull_ST_18i 0x0396 |
| #define B16SemaHub_almostFull_ST_18i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_18i 18 |
| #define LSb16SemaHub_almostFull_ST_18i 2 |
| #define bSemaHub_almostFull_ST_18i 1 |
| #define MSK32SemaHub_almostFull_ST_18i 0x00040000 |
| |
| #define BA_SemaHub_almostFull_ST_19i 0x0396 |
| #define B16SemaHub_almostFull_ST_19i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_19i 19 |
| #define LSb16SemaHub_almostFull_ST_19i 3 |
| #define bSemaHub_almostFull_ST_19i 1 |
| #define MSK32SemaHub_almostFull_ST_19i 0x00080000 |
| |
| #define BA_SemaHub_almostFull_ST_20i 0x0396 |
| #define B16SemaHub_almostFull_ST_20i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_20i 20 |
| #define LSb16SemaHub_almostFull_ST_20i 4 |
| #define bSemaHub_almostFull_ST_20i 1 |
| #define MSK32SemaHub_almostFull_ST_20i 0x00100000 |
| |
| #define BA_SemaHub_almostFull_ST_21i 0x0396 |
| #define B16SemaHub_almostFull_ST_21i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_21i 21 |
| #define LSb16SemaHub_almostFull_ST_21i 5 |
| #define bSemaHub_almostFull_ST_21i 1 |
| #define MSK32SemaHub_almostFull_ST_21i 0x00200000 |
| |
| #define BA_SemaHub_almostFull_ST_22i 0x0396 |
| #define B16SemaHub_almostFull_ST_22i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_22i 22 |
| #define LSb16SemaHub_almostFull_ST_22i 6 |
| #define bSemaHub_almostFull_ST_22i 1 |
| #define MSK32SemaHub_almostFull_ST_22i 0x00400000 |
| |
| #define BA_SemaHub_almostFull_ST_23i 0x0396 |
| #define B16SemaHub_almostFull_ST_23i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_23i 23 |
| #define LSb16SemaHub_almostFull_ST_23i 7 |
| #define bSemaHub_almostFull_ST_23i 1 |
| #define MSK32SemaHub_almostFull_ST_23i 0x00800000 |
| |
| #define BA_SemaHub_almostFull_ST_24i 0x0397 |
| #define B16SemaHub_almostFull_ST_24i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_24i 24 |
| #define LSb16SemaHub_almostFull_ST_24i 8 |
| #define bSemaHub_almostFull_ST_24i 1 |
| #define MSK32SemaHub_almostFull_ST_24i 0x01000000 |
| |
| #define BA_SemaHub_almostFull_ST_25i 0x0397 |
| #define B16SemaHub_almostFull_ST_25i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_25i 25 |
| #define LSb16SemaHub_almostFull_ST_25i 9 |
| #define bSemaHub_almostFull_ST_25i 1 |
| #define MSK32SemaHub_almostFull_ST_25i 0x02000000 |
| |
| #define BA_SemaHub_almostFull_ST_26i 0x0397 |
| #define B16SemaHub_almostFull_ST_26i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_26i 26 |
| #define LSb16SemaHub_almostFull_ST_26i 10 |
| #define bSemaHub_almostFull_ST_26i 1 |
| #define MSK32SemaHub_almostFull_ST_26i 0x04000000 |
| |
| #define BA_SemaHub_almostFull_ST_27i 0x0397 |
| #define B16SemaHub_almostFull_ST_27i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_27i 27 |
| #define LSb16SemaHub_almostFull_ST_27i 11 |
| #define bSemaHub_almostFull_ST_27i 1 |
| #define MSK32SemaHub_almostFull_ST_27i 0x08000000 |
| |
| #define BA_SemaHub_almostFull_ST_28i 0x0397 |
| #define B16SemaHub_almostFull_ST_28i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_28i 28 |
| #define LSb16SemaHub_almostFull_ST_28i 12 |
| #define bSemaHub_almostFull_ST_28i 1 |
| #define MSK32SemaHub_almostFull_ST_28i 0x10000000 |
| |
| #define BA_SemaHub_almostFull_ST_29i 0x0397 |
| #define B16SemaHub_almostFull_ST_29i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_29i 29 |
| #define LSb16SemaHub_almostFull_ST_29i 13 |
| #define bSemaHub_almostFull_ST_29i 1 |
| #define MSK32SemaHub_almostFull_ST_29i 0x20000000 |
| |
| #define BA_SemaHub_almostFull_ST_30i 0x0397 |
| #define B16SemaHub_almostFull_ST_30i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_30i 30 |
| #define LSb16SemaHub_almostFull_ST_30i 14 |
| #define bSemaHub_almostFull_ST_30i 1 |
| #define MSK32SemaHub_almostFull_ST_30i 0x40000000 |
| |
| #define BA_SemaHub_almostFull_ST_31i 0x0397 |
| #define B16SemaHub_almostFull_ST_31i 0x0396 |
| #define LSb32SemaHub_almostFull_ST_31i 31 |
| #define LSb16SemaHub_almostFull_ST_31i 15 |
| #define bSemaHub_almostFull_ST_31i 1 |
| #define MSK32SemaHub_almostFull_ST_31i 0x80000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_SemaHub { |
| /////////////////////////////////////////////////////////// |
| SIE_SemaQuery ie_counter[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_Semaphore ie_cell[32]; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_PUSH_ID(r32) _BFGET_(r32, 7, 0) |
| #define SET32SemaHub_PUSH_ID(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16SemaHub_PUSH_ID(r16) _BFGET_(r16, 7, 0) |
| #define SET16SemaHub_PUSH_ID(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32SemaHub_PUSH_delta(r32) _BFGET_(r32,15, 8) |
| #define SET32SemaHub_PUSH_delta(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16SemaHub_PUSH_delta(r16) _BFGET_(r16,15, 8) |
| #define SET16SemaHub_PUSH_delta(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32SemaHub_PUSH {\ |
| UNSG32 uPUSH_ID : 8;\ |
| UNSG32 uPUSH_delta : 8;\ |
| UNSG32 RSVDx380_b16 : 16;\ |
| } |
| union { UNSG32 u32SemaHub_PUSH; |
| struct w32SemaHub_PUSH; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_POP_ID(r32) _BFGET_(r32, 7, 0) |
| #define SET32SemaHub_POP_ID(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16SemaHub_POP_ID(r16) _BFGET_(r16, 7, 0) |
| #define SET16SemaHub_POP_ID(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32SemaHub_POP_delta(r32) _BFGET_(r32,15, 8) |
| #define SET32SemaHub_POP_delta(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16SemaHub_POP_delta(r16) _BFGET_(r16,15, 8) |
| #define SET16SemaHub_POP_delta(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32SemaHub_POP {\ |
| UNSG32 uPOP_ID : 8;\ |
| UNSG32 uPOP_delta : 8;\ |
| UNSG32 RSVDx384_b16 : 16;\ |
| } |
| union { UNSG32 u32SemaHub_POP; |
| struct w32SemaHub_POP; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_empty_ST_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32SemaHub_empty_ST_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16SemaHub_empty_ST_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_empty_ST_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_empty_ST_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32SemaHub_empty_ST_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16SemaHub_empty_ST_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_empty_ST_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_empty_ST_2i(r32) _BFGET_(r32, 2, 2) |
| #define SET32SemaHub_empty_ST_2i(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16SemaHub_empty_ST_2i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_empty_ST_2i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_empty_ST_3i(r32) _BFGET_(r32, 3, 3) |
| #define SET32SemaHub_empty_ST_3i(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16SemaHub_empty_ST_3i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_empty_ST_3i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_empty_ST_4i(r32) _BFGET_(r32, 4, 4) |
| #define SET32SemaHub_empty_ST_4i(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16SemaHub_empty_ST_4i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_empty_ST_4i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_empty_ST_5i(r32) _BFGET_(r32, 5, 5) |
| #define SET32SemaHub_empty_ST_5i(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16SemaHub_empty_ST_5i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_empty_ST_5i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_empty_ST_6i(r32) _BFGET_(r32, 6, 6) |
| #define SET32SemaHub_empty_ST_6i(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16SemaHub_empty_ST_6i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_empty_ST_6i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_empty_ST_7i(r32) _BFGET_(r32, 7, 7) |
| #define SET32SemaHub_empty_ST_7i(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16SemaHub_empty_ST_7i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_empty_ST_7i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_empty_ST_8i(r32) _BFGET_(r32, 8, 8) |
| #define SET32SemaHub_empty_ST_8i(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16SemaHub_empty_ST_8i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_empty_ST_8i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_empty_ST_9i(r32) _BFGET_(r32, 9, 9) |
| #define SET32SemaHub_empty_ST_9i(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16SemaHub_empty_ST_9i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_empty_ST_9i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_empty_ST_10i(r32) _BFGET_(r32,10,10) |
| #define SET32SemaHub_empty_ST_10i(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16SemaHub_empty_ST_10i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_empty_ST_10i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_empty_ST_11i(r32) _BFGET_(r32,11,11) |
| #define SET32SemaHub_empty_ST_11i(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16SemaHub_empty_ST_11i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_empty_ST_11i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_empty_ST_12i(r32) _BFGET_(r32,12,12) |
| #define SET32SemaHub_empty_ST_12i(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16SemaHub_empty_ST_12i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_empty_ST_12i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_empty_ST_13i(r32) _BFGET_(r32,13,13) |
| #define SET32SemaHub_empty_ST_13i(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16SemaHub_empty_ST_13i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_empty_ST_13i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_empty_ST_14i(r32) _BFGET_(r32,14,14) |
| #define SET32SemaHub_empty_ST_14i(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16SemaHub_empty_ST_14i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_empty_ST_14i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_empty_ST_15i(r32) _BFGET_(r32,15,15) |
| #define SET32SemaHub_empty_ST_15i(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16SemaHub_empty_ST_15i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_empty_ST_15i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32SemaHub_empty_ST_16i(r32) _BFGET_(r32,16,16) |
| #define SET32SemaHub_empty_ST_16i(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16SemaHub_empty_ST_16i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_empty_ST_16i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_empty_ST_17i(r32) _BFGET_(r32,17,17) |
| #define SET32SemaHub_empty_ST_17i(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16SemaHub_empty_ST_17i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_empty_ST_17i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_empty_ST_18i(r32) _BFGET_(r32,18,18) |
| #define SET32SemaHub_empty_ST_18i(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16SemaHub_empty_ST_18i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_empty_ST_18i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_empty_ST_19i(r32) _BFGET_(r32,19,19) |
| #define SET32SemaHub_empty_ST_19i(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16SemaHub_empty_ST_19i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_empty_ST_19i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_empty_ST_20i(r32) _BFGET_(r32,20,20) |
| #define SET32SemaHub_empty_ST_20i(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16SemaHub_empty_ST_20i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_empty_ST_20i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_empty_ST_21i(r32) _BFGET_(r32,21,21) |
| #define SET32SemaHub_empty_ST_21i(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16SemaHub_empty_ST_21i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_empty_ST_21i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_empty_ST_22i(r32) _BFGET_(r32,22,22) |
| #define SET32SemaHub_empty_ST_22i(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16SemaHub_empty_ST_22i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_empty_ST_22i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_empty_ST_23i(r32) _BFGET_(r32,23,23) |
| #define SET32SemaHub_empty_ST_23i(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16SemaHub_empty_ST_23i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_empty_ST_23i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_empty_ST_24i(r32) _BFGET_(r32,24,24) |
| #define SET32SemaHub_empty_ST_24i(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16SemaHub_empty_ST_24i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_empty_ST_24i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_empty_ST_25i(r32) _BFGET_(r32,25,25) |
| #define SET32SemaHub_empty_ST_25i(r32,v) _BFSET_(r32,25,25,v) |
| #define GET16SemaHub_empty_ST_25i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_empty_ST_25i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_empty_ST_26i(r32) _BFGET_(r32,26,26) |
| #define SET32SemaHub_empty_ST_26i(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16SemaHub_empty_ST_26i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_empty_ST_26i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_empty_ST_27i(r32) _BFGET_(r32,27,27) |
| #define SET32SemaHub_empty_ST_27i(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16SemaHub_empty_ST_27i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_empty_ST_27i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_empty_ST_28i(r32) _BFGET_(r32,28,28) |
| #define SET32SemaHub_empty_ST_28i(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16SemaHub_empty_ST_28i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_empty_ST_28i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_empty_ST_29i(r32) _BFGET_(r32,29,29) |
| #define SET32SemaHub_empty_ST_29i(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16SemaHub_empty_ST_29i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_empty_ST_29i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_empty_ST_30i(r32) _BFGET_(r32,30,30) |
| #define SET32SemaHub_empty_ST_30i(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16SemaHub_empty_ST_30i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_empty_ST_30i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_empty_ST_31i(r32) _BFGET_(r32,31,31) |
| #define SET32SemaHub_empty_ST_31i(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16SemaHub_empty_ST_31i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_empty_ST_31i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32SemaHub_empty {\ |
| UNSG32 uempty_ST_0i : 1;\ |
| UNSG32 uempty_ST_1i : 1;\ |
| UNSG32 uempty_ST_2i : 1;\ |
| UNSG32 uempty_ST_3i : 1;\ |
| UNSG32 uempty_ST_4i : 1;\ |
| UNSG32 uempty_ST_5i : 1;\ |
| UNSG32 uempty_ST_6i : 1;\ |
| UNSG32 uempty_ST_7i : 1;\ |
| UNSG32 uempty_ST_8i : 1;\ |
| UNSG32 uempty_ST_9i : 1;\ |
| UNSG32 uempty_ST_10i : 1;\ |
| UNSG32 uempty_ST_11i : 1;\ |
| UNSG32 uempty_ST_12i : 1;\ |
| UNSG32 uempty_ST_13i : 1;\ |
| UNSG32 uempty_ST_14i : 1;\ |
| UNSG32 uempty_ST_15i : 1;\ |
| UNSG32 uempty_ST_16i : 1;\ |
| UNSG32 uempty_ST_17i : 1;\ |
| UNSG32 uempty_ST_18i : 1;\ |
| UNSG32 uempty_ST_19i : 1;\ |
| UNSG32 uempty_ST_20i : 1;\ |
| UNSG32 uempty_ST_21i : 1;\ |
| UNSG32 uempty_ST_22i : 1;\ |
| UNSG32 uempty_ST_23i : 1;\ |
| UNSG32 uempty_ST_24i : 1;\ |
| UNSG32 uempty_ST_25i : 1;\ |
| UNSG32 uempty_ST_26i : 1;\ |
| UNSG32 uempty_ST_27i : 1;\ |
| UNSG32 uempty_ST_28i : 1;\ |
| UNSG32 uempty_ST_29i : 1;\ |
| UNSG32 uempty_ST_30i : 1;\ |
| UNSG32 uempty_ST_31i : 1;\ |
| } |
| union { UNSG32 u32SemaHub_empty; |
| struct w32SemaHub_empty; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_full_ST_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32SemaHub_full_ST_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16SemaHub_full_ST_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_full_ST_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_full_ST_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32SemaHub_full_ST_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16SemaHub_full_ST_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_full_ST_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_full_ST_2i(r32) _BFGET_(r32, 2, 2) |
| #define SET32SemaHub_full_ST_2i(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16SemaHub_full_ST_2i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_full_ST_2i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_full_ST_3i(r32) _BFGET_(r32, 3, 3) |
| #define SET32SemaHub_full_ST_3i(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16SemaHub_full_ST_3i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_full_ST_3i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_full_ST_4i(r32) _BFGET_(r32, 4, 4) |
| #define SET32SemaHub_full_ST_4i(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16SemaHub_full_ST_4i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_full_ST_4i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_full_ST_5i(r32) _BFGET_(r32, 5, 5) |
| #define SET32SemaHub_full_ST_5i(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16SemaHub_full_ST_5i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_full_ST_5i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_full_ST_6i(r32) _BFGET_(r32, 6, 6) |
| #define SET32SemaHub_full_ST_6i(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16SemaHub_full_ST_6i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_full_ST_6i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_full_ST_7i(r32) _BFGET_(r32, 7, 7) |
| #define SET32SemaHub_full_ST_7i(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16SemaHub_full_ST_7i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_full_ST_7i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_full_ST_8i(r32) _BFGET_(r32, 8, 8) |
| #define SET32SemaHub_full_ST_8i(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16SemaHub_full_ST_8i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_full_ST_8i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_full_ST_9i(r32) _BFGET_(r32, 9, 9) |
| #define SET32SemaHub_full_ST_9i(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16SemaHub_full_ST_9i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_full_ST_9i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_full_ST_10i(r32) _BFGET_(r32,10,10) |
| #define SET32SemaHub_full_ST_10i(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16SemaHub_full_ST_10i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_full_ST_10i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_full_ST_11i(r32) _BFGET_(r32,11,11) |
| #define SET32SemaHub_full_ST_11i(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16SemaHub_full_ST_11i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_full_ST_11i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_full_ST_12i(r32) _BFGET_(r32,12,12) |
| #define SET32SemaHub_full_ST_12i(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16SemaHub_full_ST_12i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_full_ST_12i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_full_ST_13i(r32) _BFGET_(r32,13,13) |
| #define SET32SemaHub_full_ST_13i(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16SemaHub_full_ST_13i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_full_ST_13i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_full_ST_14i(r32) _BFGET_(r32,14,14) |
| #define SET32SemaHub_full_ST_14i(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16SemaHub_full_ST_14i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_full_ST_14i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_full_ST_15i(r32) _BFGET_(r32,15,15) |
| #define SET32SemaHub_full_ST_15i(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16SemaHub_full_ST_15i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_full_ST_15i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32SemaHub_full_ST_16i(r32) _BFGET_(r32,16,16) |
| #define SET32SemaHub_full_ST_16i(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16SemaHub_full_ST_16i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_full_ST_16i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_full_ST_17i(r32) _BFGET_(r32,17,17) |
| #define SET32SemaHub_full_ST_17i(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16SemaHub_full_ST_17i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_full_ST_17i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_full_ST_18i(r32) _BFGET_(r32,18,18) |
| #define SET32SemaHub_full_ST_18i(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16SemaHub_full_ST_18i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_full_ST_18i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_full_ST_19i(r32) _BFGET_(r32,19,19) |
| #define SET32SemaHub_full_ST_19i(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16SemaHub_full_ST_19i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_full_ST_19i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_full_ST_20i(r32) _BFGET_(r32,20,20) |
| #define SET32SemaHub_full_ST_20i(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16SemaHub_full_ST_20i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_full_ST_20i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_full_ST_21i(r32) _BFGET_(r32,21,21) |
| #define SET32SemaHub_full_ST_21i(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16SemaHub_full_ST_21i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_full_ST_21i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_full_ST_22i(r32) _BFGET_(r32,22,22) |
| #define SET32SemaHub_full_ST_22i(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16SemaHub_full_ST_22i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_full_ST_22i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_full_ST_23i(r32) _BFGET_(r32,23,23) |
| #define SET32SemaHub_full_ST_23i(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16SemaHub_full_ST_23i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_full_ST_23i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_full_ST_24i(r32) _BFGET_(r32,24,24) |
| #define SET32SemaHub_full_ST_24i(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16SemaHub_full_ST_24i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_full_ST_24i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_full_ST_25i(r32) _BFGET_(r32,25,25) |
| #define SET32SemaHub_full_ST_25i(r32,v) _BFSET_(r32,25,25,v) |
| #define GET16SemaHub_full_ST_25i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_full_ST_25i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_full_ST_26i(r32) _BFGET_(r32,26,26) |
| #define SET32SemaHub_full_ST_26i(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16SemaHub_full_ST_26i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_full_ST_26i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_full_ST_27i(r32) _BFGET_(r32,27,27) |
| #define SET32SemaHub_full_ST_27i(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16SemaHub_full_ST_27i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_full_ST_27i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_full_ST_28i(r32) _BFGET_(r32,28,28) |
| #define SET32SemaHub_full_ST_28i(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16SemaHub_full_ST_28i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_full_ST_28i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_full_ST_29i(r32) _BFGET_(r32,29,29) |
| #define SET32SemaHub_full_ST_29i(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16SemaHub_full_ST_29i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_full_ST_29i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_full_ST_30i(r32) _BFGET_(r32,30,30) |
| #define SET32SemaHub_full_ST_30i(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16SemaHub_full_ST_30i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_full_ST_30i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_full_ST_31i(r32) _BFGET_(r32,31,31) |
| #define SET32SemaHub_full_ST_31i(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16SemaHub_full_ST_31i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_full_ST_31i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32SemaHub_full {\ |
| UNSG32 ufull_ST_0i : 1;\ |
| UNSG32 ufull_ST_1i : 1;\ |
| UNSG32 ufull_ST_2i : 1;\ |
| UNSG32 ufull_ST_3i : 1;\ |
| UNSG32 ufull_ST_4i : 1;\ |
| UNSG32 ufull_ST_5i : 1;\ |
| UNSG32 ufull_ST_6i : 1;\ |
| UNSG32 ufull_ST_7i : 1;\ |
| UNSG32 ufull_ST_8i : 1;\ |
| UNSG32 ufull_ST_9i : 1;\ |
| UNSG32 ufull_ST_10i : 1;\ |
| UNSG32 ufull_ST_11i : 1;\ |
| UNSG32 ufull_ST_12i : 1;\ |
| UNSG32 ufull_ST_13i : 1;\ |
| UNSG32 ufull_ST_14i : 1;\ |
| UNSG32 ufull_ST_15i : 1;\ |
| UNSG32 ufull_ST_16i : 1;\ |
| UNSG32 ufull_ST_17i : 1;\ |
| UNSG32 ufull_ST_18i : 1;\ |
| UNSG32 ufull_ST_19i : 1;\ |
| UNSG32 ufull_ST_20i : 1;\ |
| UNSG32 ufull_ST_21i : 1;\ |
| UNSG32 ufull_ST_22i : 1;\ |
| UNSG32 ufull_ST_23i : 1;\ |
| UNSG32 ufull_ST_24i : 1;\ |
| UNSG32 ufull_ST_25i : 1;\ |
| UNSG32 ufull_ST_26i : 1;\ |
| UNSG32 ufull_ST_27i : 1;\ |
| UNSG32 ufull_ST_28i : 1;\ |
| UNSG32 ufull_ST_29i : 1;\ |
| UNSG32 ufull_ST_30i : 1;\ |
| UNSG32 ufull_ST_31i : 1;\ |
| } |
| union { UNSG32 u32SemaHub_full; |
| struct w32SemaHub_full; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_almostEmpty_ST_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32SemaHub_almostEmpty_ST_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16SemaHub_almostEmpty_ST_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_almostEmpty_ST_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32SemaHub_almostEmpty_ST_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16SemaHub_almostEmpty_ST_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_almostEmpty_ST_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_2i(r32) _BFGET_(r32, 2, 2) |
| #define SET32SemaHub_almostEmpty_ST_2i(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16SemaHub_almostEmpty_ST_2i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_almostEmpty_ST_2i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_3i(r32) _BFGET_(r32, 3, 3) |
| #define SET32SemaHub_almostEmpty_ST_3i(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16SemaHub_almostEmpty_ST_3i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_almostEmpty_ST_3i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_4i(r32) _BFGET_(r32, 4, 4) |
| #define SET32SemaHub_almostEmpty_ST_4i(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16SemaHub_almostEmpty_ST_4i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_almostEmpty_ST_4i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_5i(r32) _BFGET_(r32, 5, 5) |
| #define SET32SemaHub_almostEmpty_ST_5i(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16SemaHub_almostEmpty_ST_5i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_almostEmpty_ST_5i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_6i(r32) _BFGET_(r32, 6, 6) |
| #define SET32SemaHub_almostEmpty_ST_6i(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16SemaHub_almostEmpty_ST_6i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_almostEmpty_ST_6i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_7i(r32) _BFGET_(r32, 7, 7) |
| #define SET32SemaHub_almostEmpty_ST_7i(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16SemaHub_almostEmpty_ST_7i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_almostEmpty_ST_7i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_8i(r32) _BFGET_(r32, 8, 8) |
| #define SET32SemaHub_almostEmpty_ST_8i(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16SemaHub_almostEmpty_ST_8i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_almostEmpty_ST_8i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_9i(r32) _BFGET_(r32, 9, 9) |
| #define SET32SemaHub_almostEmpty_ST_9i(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16SemaHub_almostEmpty_ST_9i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_almostEmpty_ST_9i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_10i(r32) _BFGET_(r32,10,10) |
| #define SET32SemaHub_almostEmpty_ST_10i(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16SemaHub_almostEmpty_ST_10i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_almostEmpty_ST_10i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_11i(r32) _BFGET_(r32,11,11) |
| #define SET32SemaHub_almostEmpty_ST_11i(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16SemaHub_almostEmpty_ST_11i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_almostEmpty_ST_11i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_12i(r32) _BFGET_(r32,12,12) |
| #define SET32SemaHub_almostEmpty_ST_12i(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16SemaHub_almostEmpty_ST_12i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_almostEmpty_ST_12i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_13i(r32) _BFGET_(r32,13,13) |
| #define SET32SemaHub_almostEmpty_ST_13i(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16SemaHub_almostEmpty_ST_13i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_almostEmpty_ST_13i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_14i(r32) _BFGET_(r32,14,14) |
| #define SET32SemaHub_almostEmpty_ST_14i(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16SemaHub_almostEmpty_ST_14i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_almostEmpty_ST_14i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_15i(r32) _BFGET_(r32,15,15) |
| #define SET32SemaHub_almostEmpty_ST_15i(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16SemaHub_almostEmpty_ST_15i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_almostEmpty_ST_15i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_16i(r32) _BFGET_(r32,16,16) |
| #define SET32SemaHub_almostEmpty_ST_16i(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16SemaHub_almostEmpty_ST_16i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_almostEmpty_ST_16i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_17i(r32) _BFGET_(r32,17,17) |
| #define SET32SemaHub_almostEmpty_ST_17i(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16SemaHub_almostEmpty_ST_17i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_almostEmpty_ST_17i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_18i(r32) _BFGET_(r32,18,18) |
| #define SET32SemaHub_almostEmpty_ST_18i(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16SemaHub_almostEmpty_ST_18i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_almostEmpty_ST_18i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_19i(r32) _BFGET_(r32,19,19) |
| #define SET32SemaHub_almostEmpty_ST_19i(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16SemaHub_almostEmpty_ST_19i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_almostEmpty_ST_19i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_20i(r32) _BFGET_(r32,20,20) |
| #define SET32SemaHub_almostEmpty_ST_20i(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16SemaHub_almostEmpty_ST_20i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_almostEmpty_ST_20i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_21i(r32) _BFGET_(r32,21,21) |
| #define SET32SemaHub_almostEmpty_ST_21i(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16SemaHub_almostEmpty_ST_21i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_almostEmpty_ST_21i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_22i(r32) _BFGET_(r32,22,22) |
| #define SET32SemaHub_almostEmpty_ST_22i(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16SemaHub_almostEmpty_ST_22i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_almostEmpty_ST_22i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_23i(r32) _BFGET_(r32,23,23) |
| #define SET32SemaHub_almostEmpty_ST_23i(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16SemaHub_almostEmpty_ST_23i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_almostEmpty_ST_23i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_24i(r32) _BFGET_(r32,24,24) |
| #define SET32SemaHub_almostEmpty_ST_24i(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16SemaHub_almostEmpty_ST_24i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_almostEmpty_ST_24i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_25i(r32) _BFGET_(r32,25,25) |
| #define SET32SemaHub_almostEmpty_ST_25i(r32,v) _BFSET_(r32,25,25,v) |
| #define GET16SemaHub_almostEmpty_ST_25i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_almostEmpty_ST_25i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_26i(r32) _BFGET_(r32,26,26) |
| #define SET32SemaHub_almostEmpty_ST_26i(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16SemaHub_almostEmpty_ST_26i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_almostEmpty_ST_26i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_27i(r32) _BFGET_(r32,27,27) |
| #define SET32SemaHub_almostEmpty_ST_27i(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16SemaHub_almostEmpty_ST_27i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_almostEmpty_ST_27i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_28i(r32) _BFGET_(r32,28,28) |
| #define SET32SemaHub_almostEmpty_ST_28i(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16SemaHub_almostEmpty_ST_28i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_almostEmpty_ST_28i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_29i(r32) _BFGET_(r32,29,29) |
| #define SET32SemaHub_almostEmpty_ST_29i(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16SemaHub_almostEmpty_ST_29i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_almostEmpty_ST_29i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_30i(r32) _BFGET_(r32,30,30) |
| #define SET32SemaHub_almostEmpty_ST_30i(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16SemaHub_almostEmpty_ST_30i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_almostEmpty_ST_30i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_almostEmpty_ST_31i(r32) _BFGET_(r32,31,31) |
| #define SET32SemaHub_almostEmpty_ST_31i(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16SemaHub_almostEmpty_ST_31i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_almostEmpty_ST_31i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32SemaHub_almostEmpty {\ |
| UNSG32 ualmostEmpty_ST_0i : 1;\ |
| UNSG32 ualmostEmpty_ST_1i : 1;\ |
| UNSG32 ualmostEmpty_ST_2i : 1;\ |
| UNSG32 ualmostEmpty_ST_3i : 1;\ |
| UNSG32 ualmostEmpty_ST_4i : 1;\ |
| UNSG32 ualmostEmpty_ST_5i : 1;\ |
| UNSG32 ualmostEmpty_ST_6i : 1;\ |
| UNSG32 ualmostEmpty_ST_7i : 1;\ |
| UNSG32 ualmostEmpty_ST_8i : 1;\ |
| UNSG32 ualmostEmpty_ST_9i : 1;\ |
| UNSG32 ualmostEmpty_ST_10i : 1;\ |
| UNSG32 ualmostEmpty_ST_11i : 1;\ |
| UNSG32 ualmostEmpty_ST_12i : 1;\ |
| UNSG32 ualmostEmpty_ST_13i : 1;\ |
| UNSG32 ualmostEmpty_ST_14i : 1;\ |
| UNSG32 ualmostEmpty_ST_15i : 1;\ |
| UNSG32 ualmostEmpty_ST_16i : 1;\ |
| UNSG32 ualmostEmpty_ST_17i : 1;\ |
| UNSG32 ualmostEmpty_ST_18i : 1;\ |
| UNSG32 ualmostEmpty_ST_19i : 1;\ |
| UNSG32 ualmostEmpty_ST_20i : 1;\ |
| UNSG32 ualmostEmpty_ST_21i : 1;\ |
| UNSG32 ualmostEmpty_ST_22i : 1;\ |
| UNSG32 ualmostEmpty_ST_23i : 1;\ |
| UNSG32 ualmostEmpty_ST_24i : 1;\ |
| UNSG32 ualmostEmpty_ST_25i : 1;\ |
| UNSG32 ualmostEmpty_ST_26i : 1;\ |
| UNSG32 ualmostEmpty_ST_27i : 1;\ |
| UNSG32 ualmostEmpty_ST_28i : 1;\ |
| UNSG32 ualmostEmpty_ST_29i : 1;\ |
| UNSG32 ualmostEmpty_ST_30i : 1;\ |
| UNSG32 ualmostEmpty_ST_31i : 1;\ |
| } |
| union { UNSG32 u32SemaHub_almostEmpty; |
| struct w32SemaHub_almostEmpty; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32SemaHub_almostFull_ST_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32SemaHub_almostFull_ST_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16SemaHub_almostFull_ST_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_almostFull_ST_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_almostFull_ST_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32SemaHub_almostFull_ST_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16SemaHub_almostFull_ST_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_almostFull_ST_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_almostFull_ST_2i(r32) _BFGET_(r32, 2, 2) |
| #define SET32SemaHub_almostFull_ST_2i(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16SemaHub_almostFull_ST_2i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_almostFull_ST_2i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_almostFull_ST_3i(r32) _BFGET_(r32, 3, 3) |
| #define SET32SemaHub_almostFull_ST_3i(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16SemaHub_almostFull_ST_3i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_almostFull_ST_3i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_almostFull_ST_4i(r32) _BFGET_(r32, 4, 4) |
| #define SET32SemaHub_almostFull_ST_4i(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16SemaHub_almostFull_ST_4i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_almostFull_ST_4i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_almostFull_ST_5i(r32) _BFGET_(r32, 5, 5) |
| #define SET32SemaHub_almostFull_ST_5i(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16SemaHub_almostFull_ST_5i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_almostFull_ST_5i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_almostFull_ST_6i(r32) _BFGET_(r32, 6, 6) |
| #define SET32SemaHub_almostFull_ST_6i(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16SemaHub_almostFull_ST_6i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_almostFull_ST_6i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_almostFull_ST_7i(r32) _BFGET_(r32, 7, 7) |
| #define SET32SemaHub_almostFull_ST_7i(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16SemaHub_almostFull_ST_7i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_almostFull_ST_7i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_almostFull_ST_8i(r32) _BFGET_(r32, 8, 8) |
| #define SET32SemaHub_almostFull_ST_8i(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16SemaHub_almostFull_ST_8i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_almostFull_ST_8i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_almostFull_ST_9i(r32) _BFGET_(r32, 9, 9) |
| #define SET32SemaHub_almostFull_ST_9i(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16SemaHub_almostFull_ST_9i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_almostFull_ST_9i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_almostFull_ST_10i(r32) _BFGET_(r32,10,10) |
| #define SET32SemaHub_almostFull_ST_10i(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16SemaHub_almostFull_ST_10i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_almostFull_ST_10i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_almostFull_ST_11i(r32) _BFGET_(r32,11,11) |
| #define SET32SemaHub_almostFull_ST_11i(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16SemaHub_almostFull_ST_11i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_almostFull_ST_11i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_almostFull_ST_12i(r32) _BFGET_(r32,12,12) |
| #define SET32SemaHub_almostFull_ST_12i(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16SemaHub_almostFull_ST_12i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_almostFull_ST_12i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_almostFull_ST_13i(r32) _BFGET_(r32,13,13) |
| #define SET32SemaHub_almostFull_ST_13i(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16SemaHub_almostFull_ST_13i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_almostFull_ST_13i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_almostFull_ST_14i(r32) _BFGET_(r32,14,14) |
| #define SET32SemaHub_almostFull_ST_14i(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16SemaHub_almostFull_ST_14i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_almostFull_ST_14i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_almostFull_ST_15i(r32) _BFGET_(r32,15,15) |
| #define SET32SemaHub_almostFull_ST_15i(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16SemaHub_almostFull_ST_15i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_almostFull_ST_15i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32SemaHub_almostFull_ST_16i(r32) _BFGET_(r32,16,16) |
| #define SET32SemaHub_almostFull_ST_16i(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16SemaHub_almostFull_ST_16i(r16) _BFGET_(r16, 0, 0) |
| #define SET16SemaHub_almostFull_ST_16i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32SemaHub_almostFull_ST_17i(r32) _BFGET_(r32,17,17) |
| #define SET32SemaHub_almostFull_ST_17i(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16SemaHub_almostFull_ST_17i(r16) _BFGET_(r16, 1, 1) |
| #define SET16SemaHub_almostFull_ST_17i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32SemaHub_almostFull_ST_18i(r32) _BFGET_(r32,18,18) |
| #define SET32SemaHub_almostFull_ST_18i(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16SemaHub_almostFull_ST_18i(r16) _BFGET_(r16, 2, 2) |
| #define SET16SemaHub_almostFull_ST_18i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32SemaHub_almostFull_ST_19i(r32) _BFGET_(r32,19,19) |
| #define SET32SemaHub_almostFull_ST_19i(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16SemaHub_almostFull_ST_19i(r16) _BFGET_(r16, 3, 3) |
| #define SET16SemaHub_almostFull_ST_19i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32SemaHub_almostFull_ST_20i(r32) _BFGET_(r32,20,20) |
| #define SET32SemaHub_almostFull_ST_20i(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16SemaHub_almostFull_ST_20i(r16) _BFGET_(r16, 4, 4) |
| #define SET16SemaHub_almostFull_ST_20i(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32SemaHub_almostFull_ST_21i(r32) _BFGET_(r32,21,21) |
| #define SET32SemaHub_almostFull_ST_21i(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16SemaHub_almostFull_ST_21i(r16) _BFGET_(r16, 5, 5) |
| #define SET16SemaHub_almostFull_ST_21i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32SemaHub_almostFull_ST_22i(r32) _BFGET_(r32,22,22) |
| #define SET32SemaHub_almostFull_ST_22i(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16SemaHub_almostFull_ST_22i(r16) _BFGET_(r16, 6, 6) |
| #define SET16SemaHub_almostFull_ST_22i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32SemaHub_almostFull_ST_23i(r32) _BFGET_(r32,23,23) |
| #define SET32SemaHub_almostFull_ST_23i(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16SemaHub_almostFull_ST_23i(r16) _BFGET_(r16, 7, 7) |
| #define SET16SemaHub_almostFull_ST_23i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32SemaHub_almostFull_ST_24i(r32) _BFGET_(r32,24,24) |
| #define SET32SemaHub_almostFull_ST_24i(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16SemaHub_almostFull_ST_24i(r16) _BFGET_(r16, 8, 8) |
| #define SET16SemaHub_almostFull_ST_24i(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32SemaHub_almostFull_ST_25i(r32) _BFGET_(r32,25,25) |
| #define SET32SemaHub_almostFull_ST_25i(r32,v) _BFSET_(r32,25,25,v) |
| #define GET16SemaHub_almostFull_ST_25i(r16) _BFGET_(r16, 9, 9) |
| #define SET16SemaHub_almostFull_ST_25i(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32SemaHub_almostFull_ST_26i(r32) _BFGET_(r32,26,26) |
| #define SET32SemaHub_almostFull_ST_26i(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16SemaHub_almostFull_ST_26i(r16) _BFGET_(r16,10,10) |
| #define SET16SemaHub_almostFull_ST_26i(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32SemaHub_almostFull_ST_27i(r32) _BFGET_(r32,27,27) |
| #define SET32SemaHub_almostFull_ST_27i(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16SemaHub_almostFull_ST_27i(r16) _BFGET_(r16,11,11) |
| #define SET16SemaHub_almostFull_ST_27i(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32SemaHub_almostFull_ST_28i(r32) _BFGET_(r32,28,28) |
| #define SET32SemaHub_almostFull_ST_28i(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16SemaHub_almostFull_ST_28i(r16) _BFGET_(r16,12,12) |
| #define SET16SemaHub_almostFull_ST_28i(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32SemaHub_almostFull_ST_29i(r32) _BFGET_(r32,29,29) |
| #define SET32SemaHub_almostFull_ST_29i(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16SemaHub_almostFull_ST_29i(r16) _BFGET_(r16,13,13) |
| #define SET16SemaHub_almostFull_ST_29i(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32SemaHub_almostFull_ST_30i(r32) _BFGET_(r32,30,30) |
| #define SET32SemaHub_almostFull_ST_30i(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16SemaHub_almostFull_ST_30i(r16) _BFGET_(r16,14,14) |
| #define SET16SemaHub_almostFull_ST_30i(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32SemaHub_almostFull_ST_31i(r32) _BFGET_(r32,31,31) |
| #define SET32SemaHub_almostFull_ST_31i(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16SemaHub_almostFull_ST_31i(r16) _BFGET_(r16,15,15) |
| #define SET16SemaHub_almostFull_ST_31i(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32SemaHub_almostFull {\ |
| UNSG32 ualmostFull_ST_0i : 1;\ |
| UNSG32 ualmostFull_ST_1i : 1;\ |
| UNSG32 ualmostFull_ST_2i : 1;\ |
| UNSG32 ualmostFull_ST_3i : 1;\ |
| UNSG32 ualmostFull_ST_4i : 1;\ |
| UNSG32 ualmostFull_ST_5i : 1;\ |
| UNSG32 ualmostFull_ST_6i : 1;\ |
| UNSG32 ualmostFull_ST_7i : 1;\ |
| UNSG32 ualmostFull_ST_8i : 1;\ |
| UNSG32 ualmostFull_ST_9i : 1;\ |
| UNSG32 ualmostFull_ST_10i : 1;\ |
| UNSG32 ualmostFull_ST_11i : 1;\ |
| UNSG32 ualmostFull_ST_12i : 1;\ |
| UNSG32 ualmostFull_ST_13i : 1;\ |
| UNSG32 ualmostFull_ST_14i : 1;\ |
| UNSG32 ualmostFull_ST_15i : 1;\ |
| UNSG32 ualmostFull_ST_16i : 1;\ |
| UNSG32 ualmostFull_ST_17i : 1;\ |
| UNSG32 ualmostFull_ST_18i : 1;\ |
| UNSG32 ualmostFull_ST_19i : 1;\ |
| UNSG32 ualmostFull_ST_20i : 1;\ |
| UNSG32 ualmostFull_ST_21i : 1;\ |
| UNSG32 ualmostFull_ST_22i : 1;\ |
| UNSG32 ualmostFull_ST_23i : 1;\ |
| UNSG32 ualmostFull_ST_24i : 1;\ |
| UNSG32 ualmostFull_ST_25i : 1;\ |
| UNSG32 ualmostFull_ST_26i : 1;\ |
| UNSG32 ualmostFull_ST_27i : 1;\ |
| UNSG32 ualmostFull_ST_28i : 1;\ |
| UNSG32 ualmostFull_ST_29i : 1;\ |
| UNSG32 ualmostFull_ST_30i : 1;\ |
| UNSG32 ualmostFull_ST_31i : 1;\ |
| } |
| union { UNSG32 u32SemaHub_almostFull; |
| struct w32SemaHub_almostFull; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx398 [104]; |
| /////////////////////////////////////////////////////////// |
| } SIE_SemaHub; |
| |
| typedef union T32SemaHub_PUSH |
| { UNSG32 u32; |
| struct w32SemaHub_PUSH; |
| } T32SemaHub_PUSH; |
| typedef union T32SemaHub_POP |
| { UNSG32 u32; |
| struct w32SemaHub_POP; |
| } T32SemaHub_POP; |
| typedef union T32SemaHub_empty |
| { UNSG32 u32; |
| struct w32SemaHub_empty; |
| } T32SemaHub_empty; |
| typedef union T32SemaHub_full |
| { UNSG32 u32; |
| struct w32SemaHub_full; |
| } T32SemaHub_full; |
| typedef union T32SemaHub_almostEmpty |
| { UNSG32 u32; |
| struct w32SemaHub_almostEmpty; |
| } T32SemaHub_almostEmpty; |
| typedef union T32SemaHub_almostFull |
| { UNSG32 u32; |
| struct w32SemaHub_almostFull; |
| } T32SemaHub_almostFull; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TSemaHub_PUSH |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_PUSH; |
| }; |
| } TSemaHub_PUSH; |
| typedef union TSemaHub_POP |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_POP; |
| }; |
| } TSemaHub_POP; |
| typedef union TSemaHub_empty |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_empty; |
| }; |
| } TSemaHub_empty; |
| typedef union TSemaHub_full |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_full; |
| }; |
| } TSemaHub_full; |
| typedef union TSemaHub_almostEmpty |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_almostEmpty; |
| }; |
| } TSemaHub_almostEmpty; |
| typedef union TSemaHub_almostFull |
| { UNSG32 u32[1]; |
| struct { |
| struct w32SemaHub_almostFull; |
| }; |
| } TSemaHub_almostFull; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 SemaHub_drvrd(SIE_SemaHub *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 SemaHub_drvwr(SIE_SemaHub *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void SemaHub_reset(SIE_SemaHub *p); |
| SIGN32 SemaHub_cmp (SIE_SemaHub *p, SIE_SemaHub *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define SemaHub_check(p,pie,pfx,hLOG) SemaHub_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define SemaHub_print(p, pfx,hLOG) SemaHub_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: SemaHub |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FiFo biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CFG (W-) |
| /// %unsigned 20 BASE |
| /// ### |
| /// * Base address (byte-address) of a FIFO in the shared SRAM. A channel's read/write pointers will be added to this “BASE” to get exact location of shared SRAM. |
| /// * Note: aligned with base SRAM data bus. |
| /// * For example, if SRAM data is 64-bit, then base[2:0] should be 3'b0; |
| /// ### |
| /// %% 12 # Stuffing bits... |
| /// @ 0x00004 START (W-) |
| /// %unsigned 1 EN 0x0 |
| /// ### |
| /// * Write 1 to this register will enable this channel, or 0 to this register will disable this channel. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00008 CLEAR (W-) |
| /// %unsigned 1 EN |
| /// ### |
| /// * Write anything to clear FIFO pointers to 0. |
| /// * Note : |
| /// * CPU should make sure to disabled the channel (write 0 to START_EN register) before issue clear command, otherwise the clear request will be ignored. |
| /// * Do not restart the channel when clear operation is in process. |
| /// * HW will make sure there is no pending transactions before execute the clear operation. |
| /// * Associated semaphore cell needs reset separately by re-write “CFG_DEPTH” |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0000C FLUSH (W-) |
| /// %unsigned 1 EN |
| /// ### |
| /// * No support for now |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 23b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FiFo |
| #define h_FiFo (){} |
| |
| #define RA_FiFo_CFG 0x0000 |
| |
| #define BA_FiFo_CFG_BASE 0x0000 |
| #define B16FiFo_CFG_BASE 0x0000 |
| #define LSb32FiFo_CFG_BASE 0 |
| #define LSb16FiFo_CFG_BASE 0 |
| #define bFiFo_CFG_BASE 20 |
| #define MSK32FiFo_CFG_BASE 0x000FFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FiFo_START 0x0004 |
| |
| #define BA_FiFo_START_EN 0x0004 |
| #define B16FiFo_START_EN 0x0004 |
| #define LSb32FiFo_START_EN 0 |
| #define LSb16FiFo_START_EN 0 |
| #define bFiFo_START_EN 1 |
| #define MSK32FiFo_START_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FiFo_CLEAR 0x0008 |
| |
| #define BA_FiFo_CLEAR_EN 0x0008 |
| #define B16FiFo_CLEAR_EN 0x0008 |
| #define LSb32FiFo_CLEAR_EN 0 |
| #define LSb16FiFo_CLEAR_EN 0 |
| #define bFiFo_CLEAR_EN 1 |
| #define MSK32FiFo_CLEAR_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FiFo_FLUSH 0x000C |
| |
| #define BA_FiFo_FLUSH_EN 0x000C |
| #define B16FiFo_FLUSH_EN 0x000C |
| #define LSb32FiFo_FLUSH_EN 0 |
| #define LSb16FiFo_FLUSH_EN 0 |
| #define bFiFo_FLUSH_EN 1 |
| #define MSK32FiFo_FLUSH_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FiFo { |
| /////////////////////////////////////////////////////////// |
| #define GET32FiFo_CFG_BASE(r32) _BFGET_(r32,19, 0) |
| #define SET32FiFo_CFG_BASE(r32,v) _BFSET_(r32,19, 0,v) |
| |
| #define w32FiFo_CFG {\ |
| UNSG32 uCFG_BASE : 20;\ |
| UNSG32 RSVDx0_b20 : 12;\ |
| } |
| union { UNSG32 u32FiFo_CFG; |
| struct w32FiFo_CFG; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FiFo_START_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32FiFo_START_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FiFo_START_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16FiFo_START_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FiFo_START {\ |
| UNSG32 uSTART_EN : 1;\ |
| UNSG32 RSVDx4_b1 : 31;\ |
| } |
| union { UNSG32 u32FiFo_START; |
| struct w32FiFo_START; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FiFo_CLEAR_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32FiFo_CLEAR_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FiFo_CLEAR_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16FiFo_CLEAR_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FiFo_CLEAR {\ |
| UNSG32 uCLEAR_EN : 1;\ |
| UNSG32 RSVDx8_b1 : 31;\ |
| } |
| union { UNSG32 u32FiFo_CLEAR; |
| struct w32FiFo_CLEAR; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FiFo_FLUSH_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32FiFo_FLUSH_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FiFo_FLUSH_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16FiFo_FLUSH_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FiFo_FLUSH {\ |
| UNSG32 uFLUSH_EN : 1;\ |
| UNSG32 RSVDxC_b1 : 31;\ |
| } |
| union { UNSG32 u32FiFo_FLUSH; |
| struct w32FiFo_FLUSH; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FiFo; |
| |
| typedef union T32FiFo_CFG |
| { UNSG32 u32; |
| struct w32FiFo_CFG; |
| } T32FiFo_CFG; |
| typedef union T32FiFo_START |
| { UNSG32 u32; |
| struct w32FiFo_START; |
| } T32FiFo_START; |
| typedef union T32FiFo_CLEAR |
| { UNSG32 u32; |
| struct w32FiFo_CLEAR; |
| } T32FiFo_CLEAR; |
| typedef union T32FiFo_FLUSH |
| { UNSG32 u32; |
| struct w32FiFo_FLUSH; |
| } T32FiFo_FLUSH; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFiFo_CFG |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FiFo_CFG; |
| }; |
| } TFiFo_CFG; |
| typedef union TFiFo_START |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FiFo_START; |
| }; |
| } TFiFo_START; |
| typedef union TFiFo_CLEAR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FiFo_CLEAR; |
| }; |
| } TFiFo_CLEAR; |
| typedef union TFiFo_FLUSH |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FiFo_FLUSH; |
| }; |
| } TFiFo_FLUSH; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FiFo_drvrd(SIE_FiFo *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FiFo_drvwr(SIE_FiFo *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FiFo_reset(SIE_FiFo *p); |
| SIGN32 FiFo_cmp (SIE_FiFo *p, SIE_FiFo *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FiFo_check(p,pie,pfx,hLOG) FiFo_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FiFo_print(p, pfx,hLOG) FiFo_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FiFo |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE HBO biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 FiFoCtl |
| /// $SemaHub FiFoCtl REG |
| /// @ 0x00400 ARR (P) |
| /// # 0x00400 FiFo |
| /// $FiFo FiFo REG [32] |
| /// ### |
| /// * Up-to 32 FIFO channels |
| /// * FiFo[N] is controlled by HBO.FiFoCtl.Channel[N] |
| /// ### |
| /// @ 0x00600 BUSY (R-) |
| /// %unsigned 32 ST |
| /// ### |
| /// * Per channel status |
| /// * Indicate the clear operation status. |
| /// * 1: clear is in process. |
| /// * 0 : clear is done. |
| /// ### |
| /// @ 0x00604 (W-) |
| /// # # Stuffing bytes... |
| /// %% 2016 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 1792B, bits: 1920b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_HBO |
| #define h_HBO (){} |
| |
| #define RA_HBO_FiFoCtl 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_HBO_ARR 0x0400 |
| #define RA_HBO_FiFo 0x0400 |
| /////////////////////////////////////////////////////////// |
| #define RA_HBO_BUSY 0x0600 |
| |
| #define BA_HBO_BUSY_ST 0x0600 |
| #define B16HBO_BUSY_ST 0x0600 |
| #define LSb32HBO_BUSY_ST 0 |
| #define LSb16HBO_BUSY_ST 0 |
| #define bHBO_BUSY_ST 32 |
| #define MSK32HBO_BUSY_ST 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_HBO { |
| /////////////////////////////////////////////////////////// |
| SIE_SemaHub ie_FiFoCtl; |
| /////////////////////////////////////////////////////////// |
| SIE_FiFo ie_FiFo[32]; |
| /////////////////////////////////////////////////////////// |
| #define GET32HBO_BUSY_ST(r32) _BFGET_(r32,31, 0) |
| #define SET32HBO_BUSY_ST(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32HBO_BUSY {\ |
| UNSG32 uBUSY_ST : 32;\ |
| } |
| union { UNSG32 u32HBO_BUSY; |
| struct w32HBO_BUSY; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx604 [252]; |
| /////////////////////////////////////////////////////////// |
| } SIE_HBO; |
| |
| typedef union T32HBO_BUSY |
| { UNSG32 u32; |
| struct w32HBO_BUSY; |
| } T32HBO_BUSY; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union THBO_BUSY |
| { UNSG32 u32[1]; |
| struct { |
| struct w32HBO_BUSY; |
| }; |
| } THBO_BUSY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 HBO_drvrd(SIE_HBO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 HBO_drvwr(SIE_HBO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void HBO_reset(SIE_HBO *p); |
| SIGN32 HBO_cmp (SIE_HBO *p, SIE_HBO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define HBO_check(p,pie,pfx,hLOG) HBO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define HBO_print(p, pfx,hLOG) HBO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: HBO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE LLDesFmt biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 mem (P) |
| /// %unsigned 16 size |
| /// ### |
| /// * The size of one piece of scattered memory. |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_LLDesFmt |
| #define h_LLDesFmt (){} |
| |
| #define RA_LLDesFmt_mem 0x0000 |
| |
| #define BA_LLDesFmt_mem_size 0x0000 |
| #define B16LLDesFmt_mem_size 0x0000 |
| #define LSb32LLDesFmt_mem_size 0 |
| #define LSb16LLDesFmt_mem_size 0 |
| #define bLLDesFmt_mem_size 16 |
| #define MSK32LLDesFmt_mem_size 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_LLDesFmt { |
| /////////////////////////////////////////////////////////// |
| #define GET32LLDesFmt_mem_size(r32) _BFGET_(r32,15, 0) |
| #define SET32LLDesFmt_mem_size(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16LLDesFmt_mem_size(r16) _BFGET_(r16,15, 0) |
| #define SET16LLDesFmt_mem_size(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32LLDesFmt_mem {\ |
| UNSG32 umem_size : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32LLDesFmt_mem; |
| struct w32LLDesFmt_mem; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_LLDesFmt; |
| |
| typedef union T32LLDesFmt_mem |
| { UNSG32 u32; |
| struct w32LLDesFmt_mem; |
| } T32LLDesFmt_mem; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TLLDesFmt_mem |
| { UNSG32 u32[1]; |
| struct { |
| struct w32LLDesFmt_mem; |
| }; |
| } TLLDesFmt_mem; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 LLDesFmt_drvrd(SIE_LLDesFmt *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 LLDesFmt_drvwr(SIE_LLDesFmt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void LLDesFmt_reset(SIE_LLDesFmt *p); |
| SIGN32 LLDesFmt_cmp (SIE_LLDesFmt *p, SIE_LLDesFmt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define LLDesFmt_check(p,pie,pfx,hLOG) LLDesFmt_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define LLDesFmt_print(p, pfx,hLOG) LLDesFmt_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: LLDesFmt |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubCmdHDR (4,4) |
| /// ### |
| /// * 32-bit dHub command header |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 DESC (W-) |
| /// %unsigned 16 size |
| /// ### |
| /// * amount of data to be transferred, in bytes or MTU. |
| /// * Size of 0 is forbidden. |
| /// ### |
| /// %unsigned 1 sizeMTU |
| /// ### |
| /// * 0: size given in bytes; |
| /// * 1: size given in MTU (see dHubChCtl.CFG.MTU for MTU size definition) |
| /// ### |
| /// %unsigned 1 semOpMTU |
| /// ### |
| /// * 0: semaphore operations applied on dHubCmd level |
| /// * 1: semaphore operations applied on MTU level |
| /// ### |
| /// %unsigned 5 chkSemId |
| /// ### |
| /// * ID of semaphore to check before cmd / MTU; |
| /// * 0 indicates semaphore check is disabled |
| /// ### |
| /// %unsigned 5 updSemId |
| /// ### |
| /// * ID of semaphore to update after cmd / MTU; |
| /// * 0 indicates semaphore update is disabled |
| /// ### |
| /// %unsigned 1 interrupt |
| /// ### |
| /// * 1: raise interrupt upon command finish |
| /// * end dHubCmdHDR |
| /// ### |
| /// %% 3 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 29b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubCmdHDR |
| #define h_dHubCmdHDR (){} |
| |
| #define RA_dHubCmdHDR_DESC 0x0000 |
| |
| #define BA_dHubCmdHDR_DESC_size 0x0000 |
| #define B16dHubCmdHDR_DESC_size 0x0000 |
| #define LSb32dHubCmdHDR_DESC_size 0 |
| #define LSb16dHubCmdHDR_DESC_size 0 |
| #define bdHubCmdHDR_DESC_size 16 |
| #define MSK32dHubCmdHDR_DESC_size 0x0000FFFF |
| |
| #define BA_dHubCmdHDR_DESC_sizeMTU 0x0002 |
| #define B16dHubCmdHDR_DESC_sizeMTU 0x0002 |
| #define LSb32dHubCmdHDR_DESC_sizeMTU 16 |
| #define LSb16dHubCmdHDR_DESC_sizeMTU 0 |
| #define bdHubCmdHDR_DESC_sizeMTU 1 |
| #define MSK32dHubCmdHDR_DESC_sizeMTU 0x00010000 |
| |
| #define BA_dHubCmdHDR_DESC_semOpMTU 0x0002 |
| #define B16dHubCmdHDR_DESC_semOpMTU 0x0002 |
| #define LSb32dHubCmdHDR_DESC_semOpMTU 17 |
| #define LSb16dHubCmdHDR_DESC_semOpMTU 1 |
| #define bdHubCmdHDR_DESC_semOpMTU 1 |
| #define MSK32dHubCmdHDR_DESC_semOpMTU 0x00020000 |
| |
| #define BA_dHubCmdHDR_DESC_chkSemId 0x0002 |
| #define B16dHubCmdHDR_DESC_chkSemId 0x0002 |
| #define LSb32dHubCmdHDR_DESC_chkSemId 18 |
| #define LSb16dHubCmdHDR_DESC_chkSemId 2 |
| #define bdHubCmdHDR_DESC_chkSemId 5 |
| #define MSK32dHubCmdHDR_DESC_chkSemId 0x007C0000 |
| |
| #define BA_dHubCmdHDR_DESC_updSemId 0x0002 |
| #define B16dHubCmdHDR_DESC_updSemId 0x0002 |
| #define LSb32dHubCmdHDR_DESC_updSemId 23 |
| #define LSb16dHubCmdHDR_DESC_updSemId 7 |
| #define bdHubCmdHDR_DESC_updSemId 5 |
| #define MSK32dHubCmdHDR_DESC_updSemId 0x0F800000 |
| |
| #define BA_dHubCmdHDR_DESC_interrupt 0x0003 |
| #define B16dHubCmdHDR_DESC_interrupt 0x0002 |
| #define LSb32dHubCmdHDR_DESC_interrupt 28 |
| #define LSb16dHubCmdHDR_DESC_interrupt 12 |
| #define bdHubCmdHDR_DESC_interrupt 1 |
| #define MSK32dHubCmdHDR_DESC_interrupt 0x10000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubCmdHDR { |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmdHDR_DESC_size(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubCmdHDR_DESC_size(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubCmdHDR_DESC_size(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubCmdHDR_DESC_size(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32dHubCmdHDR_DESC_sizeMTU(r32) _BFGET_(r32,16,16) |
| #define SET32dHubCmdHDR_DESC_sizeMTU(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16dHubCmdHDR_DESC_sizeMTU(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubCmdHDR_DESC_sizeMTU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32dHubCmdHDR_DESC_semOpMTU(r32) _BFGET_(r32,17,17) |
| #define SET32dHubCmdHDR_DESC_semOpMTU(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16dHubCmdHDR_DESC_semOpMTU(r16) _BFGET_(r16, 1, 1) |
| #define SET16dHubCmdHDR_DESC_semOpMTU(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32dHubCmdHDR_DESC_chkSemId(r32) _BFGET_(r32,22,18) |
| #define SET32dHubCmdHDR_DESC_chkSemId(r32,v) _BFSET_(r32,22,18,v) |
| #define GET16dHubCmdHDR_DESC_chkSemId(r16) _BFGET_(r16, 6, 2) |
| #define SET16dHubCmdHDR_DESC_chkSemId(r16,v) _BFSET_(r16, 6, 2,v) |
| |
| #define GET32dHubCmdHDR_DESC_updSemId(r32) _BFGET_(r32,27,23) |
| #define SET32dHubCmdHDR_DESC_updSemId(r32,v) _BFSET_(r32,27,23,v) |
| #define GET16dHubCmdHDR_DESC_updSemId(r16) _BFGET_(r16,11, 7) |
| #define SET16dHubCmdHDR_DESC_updSemId(r16,v) _BFSET_(r16,11, 7,v) |
| |
| #define GET32dHubCmdHDR_DESC_interrupt(r32) _BFGET_(r32,28,28) |
| #define SET32dHubCmdHDR_DESC_interrupt(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16dHubCmdHDR_DESC_interrupt(r16) _BFGET_(r16,12,12) |
| #define SET16dHubCmdHDR_DESC_interrupt(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define w32dHubCmdHDR_DESC {\ |
| UNSG32 uDESC_size : 16;\ |
| UNSG32 uDESC_sizeMTU : 1;\ |
| UNSG32 uDESC_semOpMTU : 1;\ |
| UNSG32 uDESC_chkSemId : 5;\ |
| UNSG32 uDESC_updSemId : 5;\ |
| UNSG32 uDESC_interrupt : 1;\ |
| UNSG32 RSVDx0_b29 : 3;\ |
| } |
| union { UNSG32 u32dHubCmdHDR_DESC; |
| struct w32dHubCmdHDR_DESC; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubCmdHDR; |
| |
| typedef union T32dHubCmdHDR_DESC |
| { UNSG32 u32; |
| struct w32dHubCmdHDR_DESC; |
| } T32dHubCmdHDR_DESC; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubCmdHDR_DESC |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmdHDR_DESC; |
| }; |
| } TdHubCmdHDR_DESC; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubCmdHDR_drvrd(SIE_dHubCmdHDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubCmdHDR_drvwr(SIE_dHubCmdHDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubCmdHDR_reset(SIE_dHubCmdHDR *p); |
| SIGN32 dHubCmdHDR_cmp (SIE_dHubCmdHDR *p, SIE_dHubCmdHDR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubCmdHDR_check(p,pie,pfx,hLOG) dHubCmdHDR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubCmdHDR_print(p, pfx,hLOG) dHubCmdHDR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubCmdHDR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubCmd biu (4,4) |
| /// ### |
| /// * 64-bit dHub command issued by read/write masters |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 MEM (W-) |
| /// %unsigned 32 addr |
| /// ### |
| /// * DRAM data address, in bytes; not necessarily MTU aligned. |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 HDR |
| /// $dHubCmdHDR HDR REG |
| /// ### |
| /// * end dHubCmd |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 61b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubCmd |
| #define h_dHubCmd (){} |
| |
| #define RA_dHubCmd_MEM 0x0000 |
| |
| #define BA_dHubCmd_MEM_addr 0x0000 |
| #define B16dHubCmd_MEM_addr 0x0000 |
| #define LSb32dHubCmd_MEM_addr 0 |
| #define LSb16dHubCmd_MEM_addr 0 |
| #define bdHubCmd_MEM_addr 32 |
| #define MSK32dHubCmd_MEM_addr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubCmd_HDR 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubCmd { |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmd_MEM_addr(r32) _BFGET_(r32,31, 0) |
| #define SET32dHubCmd_MEM_addr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32dHubCmd_MEM {\ |
| UNSG32 uMEM_addr : 32;\ |
| } |
| union { UNSG32 u32dHubCmd_MEM; |
| struct w32dHubCmd_MEM; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_dHubCmdHDR ie_HDR; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubCmd; |
| |
| typedef union T32dHubCmd_MEM |
| { UNSG32 u32; |
| struct w32dHubCmd_MEM; |
| } T32dHubCmd_MEM; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubCmd_MEM |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmd_MEM; |
| }; |
| } TdHubCmd_MEM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubCmd_drvrd(SIE_dHubCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubCmd_drvwr(SIE_dHubCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubCmd_reset(SIE_dHubCmd *p); |
| SIGN32 dHubCmd_cmp (SIE_dHubCmd *p, SIE_dHubCmd *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubCmd_check(p,pie,pfx,hLOG) dHubCmd_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubCmd_print(p, pfx,hLOG) dHubCmd_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubCmd |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubChannel biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CFG (W-) |
| /// %unsigned 2 MTU |
| /// : 8byte 0x0 |
| /// : 32byte 0x1 |
| /// : 128byte 0x2 |
| /// : 1024byte 0x3 |
| /// ### |
| /// * Minimum transfer unit of the channel |
| /// ### |
| /// %unsigned 1 QoS |
| /// ### |
| /// * Write 1 to turn on QoS detection |
| /// ### |
| /// %unsigned 1 selfLoop |
| /// ### |
| /// * Write 1 to enable cmd looping support; 0 to turn off |
| /// ### |
| /// %unsigned 1 intrCtl 0x0 |
| /// : cmdDone 0x0 |
| /// : chIdle 0x1 |
| /// ### |
| /// * 0 : default vlaue, the interrupt is triggered by the finish of the dHub command if the interrupt bit is defined in the dHub command. |
| /// * 1 : The interrupt is triggered if the dHub channel is idle ( no busy and no pending and the corresponding dHub command Q is empty). |
| /// ### |
| /// %% 27 # Stuffing bits... |
| /// @ 0x00004 START (W-) |
| /// %unsigned 1 EN 0x0 |
| /// ### |
| /// * Write 1 to enable the channel; 0 to pause the channel |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00008 CLEAR (W-) |
| /// %unsigned 1 EN |
| /// ### |
| /// * Write anything to reset the channel controller state |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0000C FLUSH (W-) |
| /// %unsigned 1 EN |
| /// ### |
| /// * Write anything to start the data flushing process. Invalid for read (M2H) channels |
| /// * end dHubChannel |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 8b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubChannel |
| #define h_dHubChannel (){} |
| |
| #define RA_dHubChannel_CFG 0x0000 |
| |
| #define BA_dHubChannel_CFG_MTU 0x0000 |
| #define B16dHubChannel_CFG_MTU 0x0000 |
| #define LSb32dHubChannel_CFG_MTU 0 |
| #define LSb16dHubChannel_CFG_MTU 0 |
| #define bdHubChannel_CFG_MTU 2 |
| #define MSK32dHubChannel_CFG_MTU 0x00000003 |
| #define dHubChannel_CFG_MTU_8byte 0x0 |
| #define dHubChannel_CFG_MTU_32byte 0x1 |
| #define dHubChannel_CFG_MTU_128byte 0x2 |
| #define dHubChannel_CFG_MTU_1024byte 0x3 |
| |
| #define BA_dHubChannel_CFG_QoS 0x0000 |
| #define B16dHubChannel_CFG_QoS 0x0000 |
| #define LSb32dHubChannel_CFG_QoS 2 |
| #define LSb16dHubChannel_CFG_QoS 2 |
| #define bdHubChannel_CFG_QoS 1 |
| #define MSK32dHubChannel_CFG_QoS 0x00000004 |
| |
| #define BA_dHubChannel_CFG_selfLoop 0x0000 |
| #define B16dHubChannel_CFG_selfLoop 0x0000 |
| #define LSb32dHubChannel_CFG_selfLoop 3 |
| #define LSb16dHubChannel_CFG_selfLoop 3 |
| #define bdHubChannel_CFG_selfLoop 1 |
| #define MSK32dHubChannel_CFG_selfLoop 0x00000008 |
| |
| #define BA_dHubChannel_CFG_intrCtl 0x0000 |
| #define B16dHubChannel_CFG_intrCtl 0x0000 |
| #define LSb32dHubChannel_CFG_intrCtl 4 |
| #define LSb16dHubChannel_CFG_intrCtl 4 |
| #define bdHubChannel_CFG_intrCtl 1 |
| #define MSK32dHubChannel_CFG_intrCtl 0x00000010 |
| #define dHubChannel_CFG_intrCtl_cmdDone 0x0 |
| #define dHubChannel_CFG_intrCtl_chIdle 0x1 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubChannel_START 0x0004 |
| |
| #define BA_dHubChannel_START_EN 0x0004 |
| #define B16dHubChannel_START_EN 0x0004 |
| #define LSb32dHubChannel_START_EN 0 |
| #define LSb16dHubChannel_START_EN 0 |
| #define bdHubChannel_START_EN 1 |
| #define MSK32dHubChannel_START_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubChannel_CLEAR 0x0008 |
| |
| #define BA_dHubChannel_CLEAR_EN 0x0008 |
| #define B16dHubChannel_CLEAR_EN 0x0008 |
| #define LSb32dHubChannel_CLEAR_EN 0 |
| #define LSb16dHubChannel_CLEAR_EN 0 |
| #define bdHubChannel_CLEAR_EN 1 |
| #define MSK32dHubChannel_CLEAR_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubChannel_FLUSH 0x000C |
| |
| #define BA_dHubChannel_FLUSH_EN 0x000C |
| #define B16dHubChannel_FLUSH_EN 0x000C |
| #define LSb32dHubChannel_FLUSH_EN 0 |
| #define LSb16dHubChannel_FLUSH_EN 0 |
| #define bdHubChannel_FLUSH_EN 1 |
| #define MSK32dHubChannel_FLUSH_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubChannel { |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubChannel_CFG_MTU(r32) _BFGET_(r32, 1, 0) |
| #define SET32dHubChannel_CFG_MTU(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16dHubChannel_CFG_MTU(r16) _BFGET_(r16, 1, 0) |
| #define SET16dHubChannel_CFG_MTU(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32dHubChannel_CFG_QoS(r32) _BFGET_(r32, 2, 2) |
| #define SET32dHubChannel_CFG_QoS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16dHubChannel_CFG_QoS(r16) _BFGET_(r16, 2, 2) |
| #define SET16dHubChannel_CFG_QoS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32dHubChannel_CFG_selfLoop(r32) _BFGET_(r32, 3, 3) |
| #define SET32dHubChannel_CFG_selfLoop(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16dHubChannel_CFG_selfLoop(r16) _BFGET_(r16, 3, 3) |
| #define SET16dHubChannel_CFG_selfLoop(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32dHubChannel_CFG_intrCtl(r32) _BFGET_(r32, 4, 4) |
| #define SET32dHubChannel_CFG_intrCtl(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16dHubChannel_CFG_intrCtl(r16) _BFGET_(r16, 4, 4) |
| #define SET16dHubChannel_CFG_intrCtl(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32dHubChannel_CFG {\ |
| UNSG32 uCFG_MTU : 2;\ |
| UNSG32 uCFG_QoS : 1;\ |
| UNSG32 uCFG_selfLoop : 1;\ |
| UNSG32 uCFG_intrCtl : 1;\ |
| UNSG32 RSVDx0_b5 : 27;\ |
| } |
| union { UNSG32 u32dHubChannel_CFG; |
| struct w32dHubChannel_CFG; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubChannel_START_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubChannel_START_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubChannel_START_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubChannel_START_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubChannel_START {\ |
| UNSG32 uSTART_EN : 1;\ |
| UNSG32 RSVDx4_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubChannel_START; |
| struct w32dHubChannel_START; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubChannel_CLEAR_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubChannel_CLEAR_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubChannel_CLEAR_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubChannel_CLEAR_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubChannel_CLEAR {\ |
| UNSG32 uCLEAR_EN : 1;\ |
| UNSG32 RSVDx8_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubChannel_CLEAR; |
| struct w32dHubChannel_CLEAR; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubChannel_FLUSH_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubChannel_FLUSH_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubChannel_FLUSH_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubChannel_FLUSH_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubChannel_FLUSH {\ |
| UNSG32 uFLUSH_EN : 1;\ |
| UNSG32 RSVDxC_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubChannel_FLUSH; |
| struct w32dHubChannel_FLUSH; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubChannel; |
| |
| typedef union T32dHubChannel_CFG |
| { UNSG32 u32; |
| struct w32dHubChannel_CFG; |
| } T32dHubChannel_CFG; |
| typedef union T32dHubChannel_START |
| { UNSG32 u32; |
| struct w32dHubChannel_START; |
| } T32dHubChannel_START; |
| typedef union T32dHubChannel_CLEAR |
| { UNSG32 u32; |
| struct w32dHubChannel_CLEAR; |
| } T32dHubChannel_CLEAR; |
| typedef union T32dHubChannel_FLUSH |
| { UNSG32 u32; |
| struct w32dHubChannel_FLUSH; |
| } T32dHubChannel_FLUSH; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubChannel_CFG |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubChannel_CFG; |
| }; |
| } TdHubChannel_CFG; |
| typedef union TdHubChannel_START |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubChannel_START; |
| }; |
| } TdHubChannel_START; |
| typedef union TdHubChannel_CLEAR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubChannel_CLEAR; |
| }; |
| } TdHubChannel_CLEAR; |
| typedef union TdHubChannel_FLUSH |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubChannel_FLUSH; |
| }; |
| } TdHubChannel_FLUSH; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubChannel_drvrd(SIE_dHubChannel *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubChannel_drvwr(SIE_dHubChannel *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubChannel_reset(SIE_dHubChannel *p); |
| SIGN32 dHubChannel_cmp (SIE_dHubChannel *p, SIE_dHubChannel *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubChannel_check(p,pie,pfx,hLOG) dHubChannel_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubChannel_print(p, pfx,hLOG) dHubChannel_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubChannel |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubReg biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 SemaHub |
| /// $SemaHub SemaHub REG |
| /// ### |
| /// * For dHub internal interrupts, also provide semaphore service for external (all channels will be opened to external to access). |
| /// * Channel 0 is used for dHub.HBO interrupt. |
| /// * Channel N+1 is used for dHub.Channel[N] interrupt. |
| /// ### |
| /// @ 0x00400 (P) |
| /// # 0x00400 HBO |
| /// $HBO HBO REG |
| /// ### |
| /// * For dHub channels (command/data queues), also provide (unused) FIFO service for external. |
| /// * Channel 2N is used for dHub.Channel[N] command. |
| /// * Channel 2N+1 is used for dHub.Channel[N] data. |
| /// ### |
| /// @ 0x00B00 ARR (P) |
| /// # 0x00B00 channelCtl |
| /// $dHubChannel channelCtl REG [16] |
| /// ### |
| /// * Up-to 16 channels |
| /// ### |
| /// @ 0x00C00 BUSY (R-) |
| /// %unsigned 16 ST |
| /// ### |
| /// * Per channel status |
| /// * 0: no ongoing command is being processed, and no flushing is taking place |
| /// * 1: channel controller is busy |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00C04 PENDING (R-) |
| /// %unsigned 16 ST |
| /// ### |
| /// * Per channel status |
| /// * 0: Response queue is empty, meaning no outstanding AXI transactions |
| /// * 1: there exist some outstanding AXI transactions |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00C08 busRstEn (RW-) |
| /// %unsigned 1 reg 0x0 |
| /// ### |
| /// * Write one to this register will trigger gate-keeper to take over the AXI bus. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00C0C busRstDone (R-) |
| /// %unsigned 1 reg 0x1 |
| /// ### |
| /// * After gate-keeper take over the AXI bus, it will assert this bit once there is no outstanding transactions on AXI bus. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00C10 flowCtl (P) |
| /// %unsigned 8 rAlpha 0x0 |
| /// %unsigned 8 wAlpha 0x0 |
| /// ### |
| /// * Flow control parameter for read and write axi master. |
| /// * clkCnt=(alpha*bstLen)>>4. |
| /// * This # of clock cycles will be blocked for the axi master after an axi command with the burst length of “bstLen”. |
| /// * When set alpha to be 0, the master will never be blocked. |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00C14 axiCmdCol (P) |
| /// %unsigned 16 rCnt 0x0 |
| /// %unsigned 16 wCnt 0x0 |
| /// ### |
| /// * Axi command collection. The counter value indicate read/write do the command collection for # of clock cycles, start from the first command pushed to an empty command Q. Here are the conditions that will trigger the Axi master to send out command. |
| /// * Cmd Q full or the counter count down to “0” from the programmed value. |
| /// * Set the counter to 0 will disable the command collection. |
| /// * end dHubReg |
| /// ### |
| /// @ 0x00C18 (W-) |
| /// # # Stuffing bytes... |
| /// %% 1856 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 3328B, bits: 3282b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubReg |
| #define h_dHubReg (){} |
| |
| #define RA_dHubReg_SemaHub 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_HBO 0x0400 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_ARR 0x0B00 |
| #define RA_dHubReg_channelCtl 0x0B00 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_BUSY 0x0C00 |
| |
| #define BA_dHubReg_BUSY_ST 0x0C00 |
| #define B16dHubReg_BUSY_ST 0x0C00 |
| #define LSb32dHubReg_BUSY_ST 0 |
| #define LSb16dHubReg_BUSY_ST 0 |
| #define bdHubReg_BUSY_ST 16 |
| #define MSK32dHubReg_BUSY_ST 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_PENDING 0x0C04 |
| |
| #define BA_dHubReg_PENDING_ST 0x0C04 |
| #define B16dHubReg_PENDING_ST 0x0C04 |
| #define LSb32dHubReg_PENDING_ST 0 |
| #define LSb16dHubReg_PENDING_ST 0 |
| #define bdHubReg_PENDING_ST 16 |
| #define MSK32dHubReg_PENDING_ST 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_busRstEn 0x0C08 |
| |
| #define BA_dHubReg_busRstEn_reg 0x0C08 |
| #define B16dHubReg_busRstEn_reg 0x0C08 |
| #define LSb32dHubReg_busRstEn_reg 0 |
| #define LSb16dHubReg_busRstEn_reg 0 |
| #define bdHubReg_busRstEn_reg 1 |
| #define MSK32dHubReg_busRstEn_reg 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_busRstDone 0x0C0C |
| |
| #define BA_dHubReg_busRstDone_reg 0x0C0C |
| #define B16dHubReg_busRstDone_reg 0x0C0C |
| #define LSb32dHubReg_busRstDone_reg 0 |
| #define LSb16dHubReg_busRstDone_reg 0 |
| #define bdHubReg_busRstDone_reg 1 |
| #define MSK32dHubReg_busRstDone_reg 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_flowCtl 0x0C10 |
| |
| #define BA_dHubReg_flowCtl_rAlpha 0x0C10 |
| #define B16dHubReg_flowCtl_rAlpha 0x0C10 |
| #define LSb32dHubReg_flowCtl_rAlpha 0 |
| #define LSb16dHubReg_flowCtl_rAlpha 0 |
| #define bdHubReg_flowCtl_rAlpha 8 |
| #define MSK32dHubReg_flowCtl_rAlpha 0x000000FF |
| |
| #define BA_dHubReg_flowCtl_wAlpha 0x0C11 |
| #define B16dHubReg_flowCtl_wAlpha 0x0C10 |
| #define LSb32dHubReg_flowCtl_wAlpha 8 |
| #define LSb16dHubReg_flowCtl_wAlpha 8 |
| #define bdHubReg_flowCtl_wAlpha 8 |
| #define MSK32dHubReg_flowCtl_wAlpha 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg_axiCmdCol 0x0C14 |
| |
| #define BA_dHubReg_axiCmdCol_rCnt 0x0C14 |
| #define B16dHubReg_axiCmdCol_rCnt 0x0C14 |
| #define LSb32dHubReg_axiCmdCol_rCnt 0 |
| #define LSb16dHubReg_axiCmdCol_rCnt 0 |
| #define bdHubReg_axiCmdCol_rCnt 16 |
| #define MSK32dHubReg_axiCmdCol_rCnt 0x0000FFFF |
| |
| #define BA_dHubReg_axiCmdCol_wCnt 0x0C16 |
| #define B16dHubReg_axiCmdCol_wCnt 0x0C16 |
| #define LSb32dHubReg_axiCmdCol_wCnt 16 |
| #define LSb16dHubReg_axiCmdCol_wCnt 0 |
| #define bdHubReg_axiCmdCol_wCnt 16 |
| #define MSK32dHubReg_axiCmdCol_wCnt 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubReg { |
| /////////////////////////////////////////////////////////// |
| SIE_SemaHub ie_SemaHub; |
| /////////////////////////////////////////////////////////// |
| SIE_HBO ie_HBO; |
| /////////////////////////////////////////////////////////// |
| SIE_dHubChannel ie_channelCtl[16]; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_BUSY_ST(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubReg_BUSY_ST(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubReg_BUSY_ST(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubReg_BUSY_ST(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dHubReg_BUSY {\ |
| UNSG32 uBUSY_ST : 16;\ |
| UNSG32 RSVDxC00_b16 : 16;\ |
| } |
| union { UNSG32 u32dHubReg_BUSY; |
| struct w32dHubReg_BUSY; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_PENDING_ST(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubReg_PENDING_ST(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubReg_PENDING_ST(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubReg_PENDING_ST(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dHubReg_PENDING {\ |
| UNSG32 uPENDING_ST : 16;\ |
| UNSG32 RSVDxC04_b16 : 16;\ |
| } |
| union { UNSG32 u32dHubReg_PENDING; |
| struct w32dHubReg_PENDING; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_busRstEn_reg(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubReg_busRstEn_reg(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubReg_busRstEn_reg(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubReg_busRstEn_reg(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubReg_busRstEn {\ |
| UNSG32 ubusRstEn_reg : 1;\ |
| UNSG32 RSVDxC08_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubReg_busRstEn; |
| struct w32dHubReg_busRstEn; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_busRstDone_reg(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubReg_busRstDone_reg(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubReg_busRstDone_reg(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubReg_busRstDone_reg(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubReg_busRstDone {\ |
| UNSG32 ubusRstDone_reg : 1;\ |
| UNSG32 RSVDxC0C_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubReg_busRstDone; |
| struct w32dHubReg_busRstDone; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_flowCtl_rAlpha(r32) _BFGET_(r32, 7, 0) |
| #define SET32dHubReg_flowCtl_rAlpha(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16dHubReg_flowCtl_rAlpha(r16) _BFGET_(r16, 7, 0) |
| #define SET16dHubReg_flowCtl_rAlpha(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32dHubReg_flowCtl_wAlpha(r32) _BFGET_(r32,15, 8) |
| #define SET32dHubReg_flowCtl_wAlpha(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16dHubReg_flowCtl_wAlpha(r16) _BFGET_(r16,15, 8) |
| #define SET16dHubReg_flowCtl_wAlpha(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32dHubReg_flowCtl {\ |
| UNSG32 uflowCtl_rAlpha : 8;\ |
| UNSG32 uflowCtl_wAlpha : 8;\ |
| UNSG32 RSVDxC10_b16 : 16;\ |
| } |
| union { UNSG32 u32dHubReg_flowCtl; |
| struct w32dHubReg_flowCtl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg_axiCmdCol_rCnt(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubReg_axiCmdCol_rCnt(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubReg_axiCmdCol_rCnt(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubReg_axiCmdCol_rCnt(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32dHubReg_axiCmdCol_wCnt(r32) _BFGET_(r32,31,16) |
| #define SET32dHubReg_axiCmdCol_wCnt(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16dHubReg_axiCmdCol_wCnt(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubReg_axiCmdCol_wCnt(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dHubReg_axiCmdCol {\ |
| UNSG32 uaxiCmdCol_rCnt : 16;\ |
| UNSG32 uaxiCmdCol_wCnt : 16;\ |
| } |
| union { UNSG32 u32dHubReg_axiCmdCol; |
| struct w32dHubReg_axiCmdCol; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxC18 [232]; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubReg; |
| |
| typedef union T32dHubReg_BUSY |
| { UNSG32 u32; |
| struct w32dHubReg_BUSY; |
| } T32dHubReg_BUSY; |
| typedef union T32dHubReg_PENDING |
| { UNSG32 u32; |
| struct w32dHubReg_PENDING; |
| } T32dHubReg_PENDING; |
| typedef union T32dHubReg_busRstEn |
| { UNSG32 u32; |
| struct w32dHubReg_busRstEn; |
| } T32dHubReg_busRstEn; |
| typedef union T32dHubReg_busRstDone |
| { UNSG32 u32; |
| struct w32dHubReg_busRstDone; |
| } T32dHubReg_busRstDone; |
| typedef union T32dHubReg_flowCtl |
| { UNSG32 u32; |
| struct w32dHubReg_flowCtl; |
| } T32dHubReg_flowCtl; |
| typedef union T32dHubReg_axiCmdCol |
| { UNSG32 u32; |
| struct w32dHubReg_axiCmdCol; |
| } T32dHubReg_axiCmdCol; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubReg_BUSY |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_BUSY; |
| }; |
| } TdHubReg_BUSY; |
| typedef union TdHubReg_PENDING |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_PENDING; |
| }; |
| } TdHubReg_PENDING; |
| typedef union TdHubReg_busRstEn |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_busRstEn; |
| }; |
| } TdHubReg_busRstEn; |
| typedef union TdHubReg_busRstDone |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_busRstDone; |
| }; |
| } TdHubReg_busRstDone; |
| typedef union TdHubReg_flowCtl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_flowCtl; |
| }; |
| } TdHubReg_flowCtl; |
| typedef union TdHubReg_axiCmdCol |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg_axiCmdCol; |
| }; |
| } TdHubReg_axiCmdCol; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubReg_drvrd(SIE_dHubReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubReg_drvwr(SIE_dHubReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubReg_reset(SIE_dHubReg *p); |
| SIGN32 dHubReg_cmp (SIE_dHubReg *p, SIE_dHubReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubReg_check(p,pie,pfx,hLOG) dHubReg_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubReg_print(p, pfx,hLOG) dHubReg_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubReg |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubCmd2D biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 MEM (W-) |
| /// %unsigned 32 addr |
| /// ### |
| /// * DRAM data address of the 2D buffer, in bytes. |
| /// ### |
| /// @ 0x00004 DESC (W-) |
| /// %unsigned 16 stride |
| /// ### |
| /// * Line stride size in bytes |
| /// ### |
| /// %unsigned 13 numLine |
| /// ### |
| /// * Number of lines in buffer. Size of 0 is forbidden. |
| /// ### |
| /// %unsigned 2 hdrLoop |
| /// ### |
| /// * Size of line-loop for choosing dHubCmdHDR |
| /// * 0 is treated as 4 |
| /// ### |
| /// %unsigned 1 interrupt |
| /// ### |
| /// * 1: raise interrupt upon whole 2D command finish. |
| /// * 1: set the last 1D command interrupt bit. |
| /// * 0 : use the default 1D command interrupt bit. |
| /// ### |
| /// @ 0x00008 START (W-) |
| /// %unsigned 1 EN 0x0 |
| /// ### |
| /// * Write 1 to enable the channel; 0 to pause the channel |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0000C CLEAR (W-) |
| /// %unsigned 1 EN |
| /// ### |
| /// * Write anything to reset the 2D engine. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00010 (P) |
| /// # 0x00010 HDR |
| /// $dHubCmdHDR HDR REG [4] |
| /// ### |
| /// * Headers used in generating dHubCmd for each line in looping order, loop size (1,2,3,4) specified by DESC_hdrLoop |
| /// * end dHubCmd2D |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 32B, bits: 182b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubCmd2D |
| #define h_dHubCmd2D (){} |
| |
| #define RA_dHubCmd2D_MEM 0x0000 |
| |
| #define BA_dHubCmd2D_MEM_addr 0x0000 |
| #define B16dHubCmd2D_MEM_addr 0x0000 |
| #define LSb32dHubCmd2D_MEM_addr 0 |
| #define LSb16dHubCmd2D_MEM_addr 0 |
| #define bdHubCmd2D_MEM_addr 32 |
| #define MSK32dHubCmd2D_MEM_addr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubCmd2D_DESC 0x0004 |
| |
| #define BA_dHubCmd2D_DESC_stride 0x0004 |
| #define B16dHubCmd2D_DESC_stride 0x0004 |
| #define LSb32dHubCmd2D_DESC_stride 0 |
| #define LSb16dHubCmd2D_DESC_stride 0 |
| #define bdHubCmd2D_DESC_stride 16 |
| #define MSK32dHubCmd2D_DESC_stride 0x0000FFFF |
| |
| #define BA_dHubCmd2D_DESC_numLine 0x0006 |
| #define B16dHubCmd2D_DESC_numLine 0x0006 |
| #define LSb32dHubCmd2D_DESC_numLine 16 |
| #define LSb16dHubCmd2D_DESC_numLine 0 |
| #define bdHubCmd2D_DESC_numLine 13 |
| #define MSK32dHubCmd2D_DESC_numLine 0x1FFF0000 |
| |
| #define BA_dHubCmd2D_DESC_hdrLoop 0x0007 |
| #define B16dHubCmd2D_DESC_hdrLoop 0x0006 |
| #define LSb32dHubCmd2D_DESC_hdrLoop 29 |
| #define LSb16dHubCmd2D_DESC_hdrLoop 13 |
| #define bdHubCmd2D_DESC_hdrLoop 2 |
| #define MSK32dHubCmd2D_DESC_hdrLoop 0x60000000 |
| |
| #define BA_dHubCmd2D_DESC_interrupt 0x0007 |
| #define B16dHubCmd2D_DESC_interrupt 0x0006 |
| #define LSb32dHubCmd2D_DESC_interrupt 31 |
| #define LSb16dHubCmd2D_DESC_interrupt 15 |
| #define bdHubCmd2D_DESC_interrupt 1 |
| #define MSK32dHubCmd2D_DESC_interrupt 0x80000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubCmd2D_START 0x0008 |
| |
| #define BA_dHubCmd2D_START_EN 0x0008 |
| #define B16dHubCmd2D_START_EN 0x0008 |
| #define LSb32dHubCmd2D_START_EN 0 |
| #define LSb16dHubCmd2D_START_EN 0 |
| #define bdHubCmd2D_START_EN 1 |
| #define MSK32dHubCmd2D_START_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubCmd2D_CLEAR 0x000C |
| |
| #define BA_dHubCmd2D_CLEAR_EN 0x000C |
| #define B16dHubCmd2D_CLEAR_EN 0x000C |
| #define LSb32dHubCmd2D_CLEAR_EN 0 |
| #define LSb16dHubCmd2D_CLEAR_EN 0 |
| #define bdHubCmd2D_CLEAR_EN 1 |
| #define MSK32dHubCmd2D_CLEAR_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubCmd2D_HDR 0x0010 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubCmd2D { |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmd2D_MEM_addr(r32) _BFGET_(r32,31, 0) |
| #define SET32dHubCmd2D_MEM_addr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32dHubCmd2D_MEM {\ |
| UNSG32 uMEM_addr : 32;\ |
| } |
| union { UNSG32 u32dHubCmd2D_MEM; |
| struct w32dHubCmd2D_MEM; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmd2D_DESC_stride(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubCmd2D_DESC_stride(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubCmd2D_DESC_stride(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubCmd2D_DESC_stride(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32dHubCmd2D_DESC_numLine(r32) _BFGET_(r32,28,16) |
| #define SET32dHubCmd2D_DESC_numLine(r32,v) _BFSET_(r32,28,16,v) |
| #define GET16dHubCmd2D_DESC_numLine(r16) _BFGET_(r16,12, 0) |
| #define SET16dHubCmd2D_DESC_numLine(r16,v) _BFSET_(r16,12, 0,v) |
| |
| #define GET32dHubCmd2D_DESC_hdrLoop(r32) _BFGET_(r32,30,29) |
| #define SET32dHubCmd2D_DESC_hdrLoop(r32,v) _BFSET_(r32,30,29,v) |
| #define GET16dHubCmd2D_DESC_hdrLoop(r16) _BFGET_(r16,14,13) |
| #define SET16dHubCmd2D_DESC_hdrLoop(r16,v) _BFSET_(r16,14,13,v) |
| |
| #define GET32dHubCmd2D_DESC_interrupt(r32) _BFGET_(r32,31,31) |
| #define SET32dHubCmd2D_DESC_interrupt(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16dHubCmd2D_DESC_interrupt(r16) _BFGET_(r16,15,15) |
| #define SET16dHubCmd2D_DESC_interrupt(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32dHubCmd2D_DESC {\ |
| UNSG32 uDESC_stride : 16;\ |
| UNSG32 uDESC_numLine : 13;\ |
| UNSG32 uDESC_hdrLoop : 2;\ |
| UNSG32 uDESC_interrupt : 1;\ |
| } |
| union { UNSG32 u32dHubCmd2D_DESC; |
| struct w32dHubCmd2D_DESC; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmd2D_START_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubCmd2D_START_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubCmd2D_START_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubCmd2D_START_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubCmd2D_START {\ |
| UNSG32 uSTART_EN : 1;\ |
| UNSG32 RSVDx8_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubCmd2D_START; |
| struct w32dHubCmd2D_START; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubCmd2D_CLEAR_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32dHubCmd2D_CLEAR_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16dHubCmd2D_CLEAR_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16dHubCmd2D_CLEAR_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32dHubCmd2D_CLEAR {\ |
| UNSG32 uCLEAR_EN : 1;\ |
| UNSG32 RSVDxC_b1 : 31;\ |
| } |
| union { UNSG32 u32dHubCmd2D_CLEAR; |
| struct w32dHubCmd2D_CLEAR; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_dHubCmdHDR ie_HDR[4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubCmd2D; |
| |
| typedef union T32dHubCmd2D_MEM |
| { UNSG32 u32; |
| struct w32dHubCmd2D_MEM; |
| } T32dHubCmd2D_MEM; |
| typedef union T32dHubCmd2D_DESC |
| { UNSG32 u32; |
| struct w32dHubCmd2D_DESC; |
| } T32dHubCmd2D_DESC; |
| typedef union T32dHubCmd2D_START |
| { UNSG32 u32; |
| struct w32dHubCmd2D_START; |
| } T32dHubCmd2D_START; |
| typedef union T32dHubCmd2D_CLEAR |
| { UNSG32 u32; |
| struct w32dHubCmd2D_CLEAR; |
| } T32dHubCmd2D_CLEAR; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubCmd2D_MEM |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmd2D_MEM; |
| }; |
| } TdHubCmd2D_MEM; |
| typedef union TdHubCmd2D_DESC |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmd2D_DESC; |
| }; |
| } TdHubCmd2D_DESC; |
| typedef union TdHubCmd2D_START |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmd2D_START; |
| }; |
| } TdHubCmd2D_START; |
| typedef union TdHubCmd2D_CLEAR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubCmd2D_CLEAR; |
| }; |
| } TdHubCmd2D_CLEAR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubCmd2D_drvrd(SIE_dHubCmd2D *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubCmd2D_drvwr(SIE_dHubCmd2D *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubCmd2D_reset(SIE_dHubCmd2D *p); |
| SIGN32 dHubCmd2D_cmp (SIE_dHubCmd2D *p, SIE_dHubCmd2D *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubCmd2D_check(p,pie,pfx,hLOG) dHubCmd2D_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubCmd2D_print(p, pfx,hLOG) dHubCmd2D_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubCmd2D |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubQuery (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 RESP (R-) |
| /// %unsigned 16 ST |
| /// ### |
| /// * Dhub channel state machine status. |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubQuery |
| #define h_dHubQuery (){} |
| |
| #define RA_dHubQuery_RESP 0x0000 |
| |
| #define BA_dHubQuery_RESP_ST 0x0000 |
| #define B16dHubQuery_RESP_ST 0x0000 |
| #define LSb32dHubQuery_RESP_ST 0 |
| #define LSb16dHubQuery_RESP_ST 0 |
| #define bdHubQuery_RESP_ST 16 |
| #define MSK32dHubQuery_RESP_ST 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubQuery { |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubQuery_RESP_ST(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubQuery_RESP_ST(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubQuery_RESP_ST(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubQuery_RESP_ST(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dHubQuery_RESP {\ |
| UNSG32 uRESP_ST : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32dHubQuery_RESP; |
| struct w32dHubQuery_RESP; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubQuery; |
| |
| typedef union T32dHubQuery_RESP |
| { UNSG32 u32; |
| struct w32dHubQuery_RESP; |
| } T32dHubQuery_RESP; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubQuery_RESP |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubQuery_RESP; |
| }; |
| } TdHubQuery_RESP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubQuery_drvrd(SIE_dHubQuery *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubQuery_drvwr(SIE_dHubQuery *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubQuery_reset(SIE_dHubQuery *p); |
| SIGN32 dHubQuery_cmp (SIE_dHubQuery *p, SIE_dHubQuery *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubQuery_check(p,pie,pfx,hLOG) dHubQuery_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubQuery_print(p, pfx,hLOG) dHubQuery_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubQuery |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dHubReg2D biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 dHub |
| /// $dHubReg dHub REG |
| /// @ 0x00D00 ARR (P) |
| /// # 0x00D00 Cmd2D |
| /// $dHubCmd2D Cmd2D REG [16] |
| /// ### |
| /// * Up-to 16 2D channels. |
| /// * 2D Channel[N] is connected to dHub.Channel[N] command queue, that is, dHub.HBO.Channel[2N] |
| /// * Note: Number of 2D channels could be less than dHub channels (rest of are 1D only) |
| /// ### |
| /// @ 0x00F00 BUSY (R-) |
| /// %unsigned 16 ST |
| /// ### |
| /// * Per channel status |
| /// * 0: no ongoing command is being processed |
| /// * 1: channel controller is busy |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00F04 (W-) |
| /// # # Stuffing bytes... |
| /// %% 480 |
| /// @ 0x00F40 (P) |
| /// # 0x00F40 CH_ST |
| /// $dHubQuery CH_ST MEM [16] |
| /// ### |
| /// * end dHubReg2D |
| /// ### |
| /// @ 0x00F80 (W-) |
| /// # # Stuffing bytes... |
| /// %% 1024 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4096B, bits: 6242b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dHubReg2D |
| #define h_dHubReg2D (){} |
| |
| #define RA_dHubReg2D_dHub 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg2D_ARR 0x0D00 |
| #define RA_dHubReg2D_Cmd2D 0x0D00 |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg2D_BUSY 0x0F00 |
| |
| #define BA_dHubReg2D_BUSY_ST 0x0F00 |
| #define B16dHubReg2D_BUSY_ST 0x0F00 |
| #define LSb32dHubReg2D_BUSY_ST 0 |
| #define LSb16dHubReg2D_BUSY_ST 0 |
| #define bdHubReg2D_BUSY_ST 16 |
| #define MSK32dHubReg2D_BUSY_ST 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dHubReg2D_CH_ST 0x0F40 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dHubReg2D { |
| /////////////////////////////////////////////////////////// |
| SIE_dHubReg ie_dHub; |
| /////////////////////////////////////////////////////////// |
| SIE_dHubCmd2D ie_Cmd2D[16]; |
| /////////////////////////////////////////////////////////// |
| #define GET32dHubReg2D_BUSY_ST(r32) _BFGET_(r32,15, 0) |
| #define SET32dHubReg2D_BUSY_ST(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dHubReg2D_BUSY_ST(r16) _BFGET_(r16,15, 0) |
| #define SET16dHubReg2D_BUSY_ST(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dHubReg2D_BUSY {\ |
| UNSG32 uBUSY_ST : 16;\ |
| UNSG32 RSVDxF00_b16 : 16;\ |
| } |
| union { UNSG32 u32dHubReg2D_BUSY; |
| struct w32dHubReg2D_BUSY; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxF04 [60]; |
| /////////////////////////////////////////////////////////// |
| SIE_dHubQuery ie_CH_ST[16]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxF80 [128]; |
| /////////////////////////////////////////////////////////// |
| } SIE_dHubReg2D; |
| |
| typedef union T32dHubReg2D_BUSY |
| { UNSG32 u32; |
| struct w32dHubReg2D_BUSY; |
| } T32dHubReg2D_BUSY; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdHubReg2D_BUSY |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dHubReg2D_BUSY; |
| }; |
| } TdHubReg2D_BUSY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dHubReg2D_drvrd(SIE_dHubReg2D *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dHubReg2D_drvwr(SIE_dHubReg2D *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dHubReg2D_reset(SIE_dHubReg2D *p); |
| SIGN32 dHubReg2D_cmp (SIE_dHubReg2D *p, SIE_dHubReg2D *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dHubReg2D_check(p,pie,pfx,hLOG) dHubReg2D_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dHubReg2D_print(p, pfx,hLOG) dHubReg2D_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dHubReg2D |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE DSmsg biu (4,4) |
| /// ### |
| /// * Data Streamer message format |
| /// * [00:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 13 count |
| /// ### |
| /// * number of bytes to transfer, the starting address is byte aligned. |
| /// ### |
| /// %unsigned 1 NOS |
| /// ### |
| /// * No outstanding |
| /// * 1: this command will not be executed until the completion of all the previous command. |
| /// * 0: This command can be executed without checking the previous command completion status. |
| /// ### |
| /// %unsigned 1 dir |
| /// : m2h 0x0 |
| /// ### |
| /// * Data transfer from external memory to HBO |
| /// ### |
| /// : h2m 0x1 |
| /// ### |
| /// * Data transfer from HBO to external memory |
| /// ### |
| /// %unsigned 1 intr |
| /// ### |
| /// * Setting to 1 forces Data Streamer to raise interrupt after command completion |
| /// ### |
| /// %unsigned 16 hboAdr |
| /// ### |
| /// * HBO byte address for data transfer |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 32 memAdr |
| /// ### |
| /// * Memory address equivalent to DDR addr [31:0]; |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_DSmsg |
| #define h_DSmsg (){} |
| |
| #define BA_DSmsg_count 0x0000 |
| #define B16DSmsg_count 0x0000 |
| #define LSb32DSmsg_count 0 |
| #define LSb16DSmsg_count 0 |
| #define bDSmsg_count 13 |
| #define MSK32DSmsg_count 0x00001FFF |
| |
| #define BA_DSmsg_NOS 0x0001 |
| #define B16DSmsg_NOS 0x0000 |
| #define LSb32DSmsg_NOS 13 |
| #define LSb16DSmsg_NOS 13 |
| #define bDSmsg_NOS 1 |
| #define MSK32DSmsg_NOS 0x00002000 |
| |
| #define BA_DSmsg_dir 0x0001 |
| #define B16DSmsg_dir 0x0000 |
| #define LSb32DSmsg_dir 14 |
| #define LSb16DSmsg_dir 14 |
| #define bDSmsg_dir 1 |
| #define MSK32DSmsg_dir 0x00004000 |
| #define DSmsg_dir_m2h 0x0 |
| #define DSmsg_dir_h2m 0x1 |
| |
| #define BA_DSmsg_intr 0x0001 |
| #define B16DSmsg_intr 0x0000 |
| #define LSb32DSmsg_intr 15 |
| #define LSb16DSmsg_intr 15 |
| #define bDSmsg_intr 1 |
| #define MSK32DSmsg_intr 0x00008000 |
| |
| #define BA_DSmsg_hboAdr 0x0002 |
| #define B16DSmsg_hboAdr 0x0002 |
| #define LSb32DSmsg_hboAdr 16 |
| #define LSb16DSmsg_hboAdr 0 |
| #define bDSmsg_hboAdr 16 |
| #define MSK32DSmsg_hboAdr 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_DSmsg_memAdr 0x0004 |
| #define B16DSmsg_memAdr 0x0004 |
| #define LSb32DSmsg_memAdr 0 |
| #define LSb16DSmsg_memAdr 0 |
| #define bDSmsg_memAdr 32 |
| #define MSK32DSmsg_memAdr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_DSmsg { |
| /////////////////////////////////////////////////////////// |
| #define GET32DSmsg_count(r32) _BFGET_(r32,12, 0) |
| #define SET32DSmsg_count(r32,v) _BFSET_(r32,12, 0,v) |
| #define GET16DSmsg_count(r16) _BFGET_(r16,12, 0) |
| #define SET16DSmsg_count(r16,v) _BFSET_(r16,12, 0,v) |
| |
| #define GET32DSmsg_NOS(r32) _BFGET_(r32,13,13) |
| #define SET32DSmsg_NOS(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16DSmsg_NOS(r16) _BFGET_(r16,13,13) |
| #define SET16DSmsg_NOS(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32DSmsg_dir(r32) _BFGET_(r32,14,14) |
| #define SET32DSmsg_dir(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16DSmsg_dir(r16) _BFGET_(r16,14,14) |
| #define SET16DSmsg_dir(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32DSmsg_intr(r32) _BFGET_(r32,15,15) |
| #define SET32DSmsg_intr(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16DSmsg_intr(r16) _BFGET_(r16,15,15) |
| #define SET16DSmsg_intr(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32DSmsg_hboAdr(r32) _BFGET_(r32,31,16) |
| #define SET32DSmsg_hboAdr(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16DSmsg_hboAdr(r16) _BFGET_(r16,15, 0) |
| #define SET16DSmsg_hboAdr(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_count : 13; |
| UNSG32 u_NOS : 1; |
| UNSG32 u_dir : 1; |
| UNSG32 u_intr : 1; |
| UNSG32 u_hboAdr : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32DSmsg_memAdr(r32) _BFGET_(r32,31, 0) |
| #define SET32DSmsg_memAdr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_memAdr : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_DSmsg; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 DSmsg_drvrd(SIE_DSmsg *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 DSmsg_drvwr(SIE_DSmsg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void DSmsg_reset(SIE_DSmsg *p); |
| SIGN32 DSmsg_cmp (SIE_DSmsg *p, SIE_DSmsg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define DSmsg_check(p,pie,pfx,hLOG) DSmsg_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define DSmsg_print(p, pfx,hLOG) DSmsg_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: DSmsg |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dsCh biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 retID (P) |
| /// %unsigned 16 addr 0x0 |
| /// ### |
| /// * The HBO address of the memory location at which the retired command ID is stored |
| /// * Note : the addr should be 64-bit aligned. Nor the RTL implementation will always put the 16-bit ID to lower 16-bit of the DTCM entry. |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00004 initID (P) |
| /// %unsigned 16 Val 0x0 |
| /// ### |
| /// * Initial retire id value |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dsCh |
| #define h_dsCh (){} |
| |
| #define RA_dsCh_retID 0x0000 |
| |
| #define BA_dsCh_retID_addr 0x0000 |
| #define B16dsCh_retID_addr 0x0000 |
| #define LSb32dsCh_retID_addr 0 |
| #define LSb16dsCh_retID_addr 0 |
| #define bdsCh_retID_addr 16 |
| #define MSK32dsCh_retID_addr 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_dsCh_initID 0x0004 |
| |
| #define BA_dsCh_initID_Val 0x0004 |
| #define B16dsCh_initID_Val 0x0004 |
| #define LSb32dsCh_initID_Val 0 |
| #define LSb16dsCh_initID_Val 0 |
| #define bdsCh_initID_Val 16 |
| #define MSK32dsCh_initID_Val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dsCh { |
| /////////////////////////////////////////////////////////// |
| #define GET32dsCh_retID_addr(r32) _BFGET_(r32,15, 0) |
| #define SET32dsCh_retID_addr(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dsCh_retID_addr(r16) _BFGET_(r16,15, 0) |
| #define SET16dsCh_retID_addr(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dsCh_retID {\ |
| UNSG32 uretID_addr : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32dsCh_retID; |
| struct w32dsCh_retID; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32dsCh_initID_Val(r32) _BFGET_(r32,15, 0) |
| #define SET32dsCh_initID_Val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16dsCh_initID_Val(r16) _BFGET_(r16,15, 0) |
| #define SET16dsCh_initID_Val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32dsCh_initID {\ |
| UNSG32 uinitID_Val : 16;\ |
| UNSG32 RSVDx4_b16 : 16;\ |
| } |
| union { UNSG32 u32dsCh_initID; |
| struct w32dsCh_initID; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_dsCh; |
| |
| typedef union T32dsCh_retID |
| { UNSG32 u32; |
| struct w32dsCh_retID; |
| } T32dsCh_retID; |
| typedef union T32dsCh_initID |
| { UNSG32 u32; |
| struct w32dsCh_initID; |
| } T32dsCh_initID; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TdsCh_retID |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dsCh_retID; |
| }; |
| } TdsCh_retID; |
| typedef union TdsCh_initID |
| { UNSG32 u32[1]; |
| struct { |
| struct w32dsCh_initID; |
| }; |
| } TdsCh_initID; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dsCh_drvrd(SIE_dsCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dsCh_drvwr(SIE_dsCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dsCh_reset(SIE_dsCh *p); |
| SIGN32 dsCh_cmp (SIE_dsCh *p, SIE_dsCh *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dsCh_check(p,pie,pfx,hLOG) dsCh_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dsCh_print(p, pfx,hLOG) dsCh_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dsCh |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE DataStreamer biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 dsCh (P) |
| /// # 0x00000 dsCh |
| /// $dsCh dsCh REG [4] |
| /// ### |
| /// * The command that was just finished by Data Streamer generated interrupt; write 1 to clear |
| /// ### |
| /// @ 0x00020 intr (WOC-) |
| /// %unsigned 1 st_0i |
| /// %unsigned 1 st_1i |
| /// %unsigned 1 st_2i |
| /// %unsigned 1 st_3i |
| /// ### |
| /// * Interrupt status |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 36B, bits: 132b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_DataStreamer |
| #define h_DataStreamer (){} |
| |
| #define RA_DataStreamer_dsCh 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_DataStreamer_intr 0x0020 |
| |
| #define BA_DataStreamer_intr_st_0i 0x0020 |
| #define B16DataStreamer_intr_st_0i 0x0020 |
| #define LSb32DataStreamer_intr_st_0i 0 |
| #define LSb16DataStreamer_intr_st_0i 0 |
| #define bDataStreamer_intr_st_0i 1 |
| #define MSK32DataStreamer_intr_st_0i 0x00000001 |
| |
| #define BA_DataStreamer_intr_st_1i 0x0020 |
| #define B16DataStreamer_intr_st_1i 0x0020 |
| #define LSb32DataStreamer_intr_st_1i 1 |
| #define LSb16DataStreamer_intr_st_1i 1 |
| #define bDataStreamer_intr_st_1i 1 |
| #define MSK32DataStreamer_intr_st_1i 0x00000002 |
| |
| #define BA_DataStreamer_intr_st_2i 0x0020 |
| #define B16DataStreamer_intr_st_2i 0x0020 |
| #define LSb32DataStreamer_intr_st_2i 2 |
| #define LSb16DataStreamer_intr_st_2i 2 |
| #define bDataStreamer_intr_st_2i 1 |
| #define MSK32DataStreamer_intr_st_2i 0x00000004 |
| |
| #define BA_DataStreamer_intr_st_3i 0x0020 |
| #define B16DataStreamer_intr_st_3i 0x0020 |
| #define LSb32DataStreamer_intr_st_3i 3 |
| #define LSb16DataStreamer_intr_st_3i 3 |
| #define bDataStreamer_intr_st_3i 1 |
| #define MSK32DataStreamer_intr_st_3i 0x00000008 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_DataStreamer { |
| /////////////////////////////////////////////////////////// |
| SIE_dsCh ie_dsCh[4]; |
| /////////////////////////////////////////////////////////// |
| #define GET32DataStreamer_intr_st_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32DataStreamer_intr_st_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16DataStreamer_intr_st_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16DataStreamer_intr_st_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32DataStreamer_intr_st_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32DataStreamer_intr_st_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16DataStreamer_intr_st_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16DataStreamer_intr_st_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32DataStreamer_intr_st_2i(r32) _BFGET_(r32, 2, 2) |
| #define SET32DataStreamer_intr_st_2i(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16DataStreamer_intr_st_2i(r16) _BFGET_(r16, 2, 2) |
| #define SET16DataStreamer_intr_st_2i(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32DataStreamer_intr_st_3i(r32) _BFGET_(r32, 3, 3) |
| #define SET32DataStreamer_intr_st_3i(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16DataStreamer_intr_st_3i(r16) _BFGET_(r16, 3, 3) |
| #define SET16DataStreamer_intr_st_3i(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32DataStreamer_intr {\ |
| UNSG32 uintr_st_0i : 1;\ |
| UNSG32 uintr_st_1i : 1;\ |
| UNSG32 uintr_st_2i : 1;\ |
| UNSG32 uintr_st_3i : 1;\ |
| UNSG32 RSVDx20_b4 : 28;\ |
| } |
| union { UNSG32 u32DataStreamer_intr; |
| struct w32DataStreamer_intr; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_DataStreamer; |
| |
| typedef union T32DataStreamer_intr |
| { UNSG32 u32; |
| struct w32DataStreamer_intr; |
| } T32DataStreamer_intr; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TDataStreamer_intr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32DataStreamer_intr; |
| }; |
| } TDataStreamer_intr; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 DataStreamer_drvrd(SIE_DataStreamer *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 DataStreamer_drvwr(SIE_DataStreamer *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void DataStreamer_reset(SIE_DataStreamer *p); |
| SIGN32 DataStreamer_cmp (SIE_DataStreamer *p, SIE_DataStreamer *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define DataStreamer_check(p,pie,pfx,hLOG) DataStreamer_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define DataStreamer_print(p, pfx,hLOG) DataStreamer_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: DataStreamer |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ALU64CMD (4,4) |
| /// ### |
| /// * 16-bit + 6-bit parameters for A64CMD |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 par (W-) |
| /// %unsigned 16 rS |
| /// ### |
| /// * rS register for A64CMD |
| /// ### |
| /// %unsigned 6 q6 |
| /// ### |
| /// * q6 parameter for A64CMD |
| /// * end ALU64CMD |
| /// ### |
| /// %% 10 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 22b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ALU64CMD |
| #define h_ALU64CMD (){} |
| |
| #define RA_ALU64CMD_par 0x0000 |
| |
| #define BA_ALU64CMD_par_rS 0x0000 |
| #define B16ALU64CMD_par_rS 0x0000 |
| #define LSb32ALU64CMD_par_rS 0 |
| #define LSb16ALU64CMD_par_rS 0 |
| #define bALU64CMD_par_rS 16 |
| #define MSK32ALU64CMD_par_rS 0x0000FFFF |
| |
| #define BA_ALU64CMD_par_q6 0x0002 |
| #define B16ALU64CMD_par_q6 0x0002 |
| #define LSb32ALU64CMD_par_q6 16 |
| #define LSb16ALU64CMD_par_q6 0 |
| #define bALU64CMD_par_q6 6 |
| #define MSK32ALU64CMD_par_q6 0x003F0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ALU64CMD { |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64CMD_par_rS(r32) _BFGET_(r32,15, 0) |
| #define SET32ALU64CMD_par_rS(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16ALU64CMD_par_rS(r16) _BFGET_(r16,15, 0) |
| #define SET16ALU64CMD_par_rS(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32ALU64CMD_par_q6(r32) _BFGET_(r32,21,16) |
| #define SET32ALU64CMD_par_q6(r32,v) _BFSET_(r32,21,16,v) |
| #define GET16ALU64CMD_par_q6(r16) _BFGET_(r16, 5, 0) |
| #define SET16ALU64CMD_par_q6(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define w32ALU64CMD_par {\ |
| UNSG32 upar_rS : 16;\ |
| UNSG32 upar_q6 : 6;\ |
| UNSG32 RSVDx0_b22 : 10;\ |
| } |
| union { UNSG32 u32ALU64CMD_par; |
| struct w32ALU64CMD_par; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_ALU64CMD; |
| |
| typedef union T32ALU64CMD_par |
| { UNSG32 u32; |
| struct w32ALU64CMD_par; |
| } T32ALU64CMD_par; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TALU64CMD_par |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64CMD_par; |
| }; |
| } TALU64CMD_par; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ALU64CMD_drvrd(SIE_ALU64CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ALU64CMD_drvwr(SIE_ALU64CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ALU64CMD_reset(SIE_ALU64CMD *p); |
| SIGN32 ALU64CMD_cmp (SIE_ALU64CMD *p, SIE_ALU64CMD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ALU64CMD_check(p,pie,pfx,hLOG) ALU64CMD_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ALU64CMD_print(p, pfx,hLOG) ALU64CMD_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ALU64CMD |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64CmdAll (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ext (P) |
| /// # 0x00000 ext |
| /// $ALU64CMD ext REG [256] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 1024B, bits: 5632b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64CmdAll |
| #define h_A64CmdAll (){} |
| |
| #define RA_A64CmdAll_ext 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64CmdAll { |
| /////////////////////////////////////////////////////////// |
| SIE_ALU64CMD ie_ext[256]; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64CmdAll; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64CmdAll_drvrd(SIE_A64CmdAll *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64CmdAll_drvwr(SIE_A64CmdAll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64CmdAll_reset(SIE_A64CmdAll *p); |
| SIGN32 A64CmdAll_cmp (SIE_A64CmdAll *p, SIE_A64CmdAll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64CmdAll_check(p,pie,pfx,hLOG) A64CmdAll_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64CmdAll_print(p, pfx,hLOG) A64CmdAll_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64CmdAll |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ALU64DAT (4,4) |
| /// ### |
| /// * 64-bit return data from ALU64 extensions |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 low (R-) |
| /// %unsigned 32 val |
| /// ### |
| /// * Lower 32-bit of the ALU64 return value; read triggers ALU64 extension pop |
| /// ### |
| /// @ 0x00004 high (R-) |
| /// %unsigned 32 val |
| /// ### |
| /// * Higher 32-bit of the ALU64 return value |
| /// * end ALU64DAT |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ALU64DAT |
| #define h_ALU64DAT (){} |
| |
| #define RA_ALU64DAT_low 0x0000 |
| |
| #define BA_ALU64DAT_low_val 0x0000 |
| #define B16ALU64DAT_low_val 0x0000 |
| #define LSb32ALU64DAT_low_val 0 |
| #define LSb16ALU64DAT_low_val 0 |
| #define bALU64DAT_low_val 32 |
| #define MSK32ALU64DAT_low_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64DAT_high 0x0004 |
| |
| #define BA_ALU64DAT_high_val 0x0004 |
| #define B16ALU64DAT_high_val 0x0004 |
| #define LSb32ALU64DAT_high_val 0 |
| #define LSb16ALU64DAT_high_val 0 |
| #define bALU64DAT_high_val 32 |
| #define MSK32ALU64DAT_high_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ALU64DAT { |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64DAT_low_val(r32) _BFGET_(r32,31, 0) |
| #define SET32ALU64DAT_low_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32ALU64DAT_low {\ |
| UNSG32 ulow_val : 32;\ |
| } |
| union { UNSG32 u32ALU64DAT_low; |
| struct w32ALU64DAT_low; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64DAT_high_val(r32) _BFGET_(r32,31, 0) |
| #define SET32ALU64DAT_high_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32ALU64DAT_high {\ |
| UNSG32 uhigh_val : 32;\ |
| } |
| union { UNSG32 u32ALU64DAT_high; |
| struct w32ALU64DAT_high; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_ALU64DAT; |
| |
| typedef union T32ALU64DAT_low |
| { UNSG32 u32; |
| struct w32ALU64DAT_low; |
| } T32ALU64DAT_low; |
| typedef union T32ALU64DAT_high |
| { UNSG32 u32; |
| struct w32ALU64DAT_high; |
| } T32ALU64DAT_high; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TALU64DAT_low |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64DAT_low; |
| }; |
| } TALU64DAT_low; |
| typedef union TALU64DAT_high |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64DAT_high; |
| }; |
| } TALU64DAT_high; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ALU64DAT_drvrd(SIE_ALU64DAT *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ALU64DAT_drvwr(SIE_ALU64DAT *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ALU64DAT_reset(SIE_ALU64DAT *p); |
| SIGN32 ALU64DAT_cmp (SIE_ALU64DAT *p, SIE_ALU64DAT *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ALU64DAT_check(p,pie,pfx,hLOG) ALU64DAT_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ALU64DAT_print(p, pfx,hLOG) ALU64DAT_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ALU64DAT |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64DatAll (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ext (P) |
| /// # 0x00000 ext |
| /// $ALU64DAT ext REG [256] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 2048B, bits: 16384b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64DatAll |
| #define h_A64DatAll (){} |
| |
| #define RA_A64DatAll_ext 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64DatAll { |
| /////////////////////////////////////////////////////////// |
| SIE_ALU64DAT ie_ext[256]; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64DatAll; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64DatAll_drvrd(SIE_A64DatAll *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64DatAll_drvwr(SIE_A64DatAll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64DatAll_reset(SIE_A64DatAll *p); |
| SIGN32 A64DatAll_cmp (SIE_A64DatAll *p, SIE_A64DatAll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64DatAll_check(p,pie,pfx,hLOG) A64DatAll_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64DatAll_print(p, pfx,hLOG) A64DatAll_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64DatAll |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ALU64 biu (4,4) |
| /// ### |
| /// * Registers ports for CPU to access FIGO ALU64 extensions |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 xT_l (P) |
| /// %unsigned 32 val |
| /// ### |
| /// * Higher 32-bit of the FIGO xT register |
| /// ### |
| /// @ 0x00004 xT_h (P) |
| /// %unsigned 32 val |
| /// ### |
| /// * Lower 32-bit of the FIGO xT register |
| /// ### |
| /// @ 0x00008 X2Q (RW-) |
| /// %unsigned 6 adr |
| /// ### |
| /// * Write triggers a transfer from {xt_H, xt_L} to RF64 selected by the address |
| /// ### |
| /// %% 26 # Stuffing bits... |
| /// @ 0x0000C PopParam (P) |
| /// %unsigned 16 rS |
| /// ### |
| /// * rS register for A64LD |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00010 (W-) |
| /// # # Stuffing bytes... |
| /// %% 8064 |
| /// @ 0x00400 Push (P) |
| /// # 0x00400 a64CmdAll |
| /// $A64CmdAll a64CmdAll MEM |
| /// ### |
| /// * Write triggers A64CMD |
| /// ### |
| /// @ 0x00800 Pop (P) |
| /// # 0x00800 a64DatAll |
| /// $A64DatAll a64DatAll MEM |
| /// ### |
| /// * Read triggers A64LD |
| /// * ALU64 interface |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4096B, bits: 150b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ALU64 |
| #define h_ALU64 (){} |
| |
| #define RA_ALU64_xT_l 0x0000 |
| |
| #define BA_ALU64_xT_l_val 0x0000 |
| #define B16ALU64_xT_l_val 0x0000 |
| #define LSb32ALU64_xT_l_val 0 |
| #define LSb16ALU64_xT_l_val 0 |
| #define bALU64_xT_l_val 32 |
| #define MSK32ALU64_xT_l_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64_xT_h 0x0004 |
| |
| #define BA_ALU64_xT_h_val 0x0004 |
| #define B16ALU64_xT_h_val 0x0004 |
| #define LSb32ALU64_xT_h_val 0 |
| #define LSb16ALU64_xT_h_val 0 |
| #define bALU64_xT_h_val 32 |
| #define MSK32ALU64_xT_h_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64_X2Q 0x0008 |
| |
| #define BA_ALU64_X2Q_adr 0x0008 |
| #define B16ALU64_X2Q_adr 0x0008 |
| #define LSb32ALU64_X2Q_adr 0 |
| #define LSb16ALU64_X2Q_adr 0 |
| #define bALU64_X2Q_adr 6 |
| #define MSK32ALU64_X2Q_adr 0x0000003F |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64_PopParam 0x000C |
| |
| #define BA_ALU64_PopParam_rS 0x000C |
| #define B16ALU64_PopParam_rS 0x000C |
| #define LSb32ALU64_PopParam_rS 0 |
| #define LSb16ALU64_PopParam_rS 0 |
| #define bALU64_PopParam_rS 16 |
| #define MSK32ALU64_PopParam_rS 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64_Push 0x0400 |
| #define RA_ALU64_a64CmdAll 0x0400 |
| /////////////////////////////////////////////////////////// |
| #define RA_ALU64_Pop 0x0800 |
| #define RA_ALU64_a64DatAll 0x0800 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ALU64 { |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64_xT_l_val(r32) _BFGET_(r32,31, 0) |
| #define SET32ALU64_xT_l_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32ALU64_xT_l {\ |
| UNSG32 uxT_l_val : 32;\ |
| } |
| union { UNSG32 u32ALU64_xT_l; |
| struct w32ALU64_xT_l; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64_xT_h_val(r32) _BFGET_(r32,31, 0) |
| #define SET32ALU64_xT_h_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32ALU64_xT_h {\ |
| UNSG32 uxT_h_val : 32;\ |
| } |
| union { UNSG32 u32ALU64_xT_h; |
| struct w32ALU64_xT_h; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64_X2Q_adr(r32) _BFGET_(r32, 5, 0) |
| #define SET32ALU64_X2Q_adr(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16ALU64_X2Q_adr(r16) _BFGET_(r16, 5, 0) |
| #define SET16ALU64_X2Q_adr(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define w32ALU64_X2Q {\ |
| UNSG32 uX2Q_adr : 6;\ |
| UNSG32 RSVDx8_b6 : 26;\ |
| } |
| union { UNSG32 u32ALU64_X2Q; |
| struct w32ALU64_X2Q; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32ALU64_PopParam_rS(r32) _BFGET_(r32,15, 0) |
| #define SET32ALU64_PopParam_rS(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16ALU64_PopParam_rS(r16) _BFGET_(r16,15, 0) |
| #define SET16ALU64_PopParam_rS(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32ALU64_PopParam {\ |
| UNSG32 uPopParam_rS : 16;\ |
| UNSG32 RSVDxC_b16 : 16;\ |
| } |
| union { UNSG32 u32ALU64_PopParam; |
| struct w32ALU64_PopParam; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx10 [1008]; |
| /////////////////////////////////////////////////////////// |
| SIE_A64CmdAll ie_a64CmdAll; |
| /////////////////////////////////////////////////////////// |
| SIE_A64DatAll ie_a64DatAll; |
| /////////////////////////////////////////////////////////// |
| } SIE_ALU64; |
| |
| typedef union T32ALU64_xT_l |
| { UNSG32 u32; |
| struct w32ALU64_xT_l; |
| } T32ALU64_xT_l; |
| typedef union T32ALU64_xT_h |
| { UNSG32 u32; |
| struct w32ALU64_xT_h; |
| } T32ALU64_xT_h; |
| typedef union T32ALU64_X2Q |
| { UNSG32 u32; |
| struct w32ALU64_X2Q; |
| } T32ALU64_X2Q; |
| typedef union T32ALU64_PopParam |
| { UNSG32 u32; |
| struct w32ALU64_PopParam; |
| } T32ALU64_PopParam; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TALU64_xT_l |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64_xT_l; |
| }; |
| } TALU64_xT_l; |
| typedef union TALU64_xT_h |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64_xT_h; |
| }; |
| } TALU64_xT_h; |
| typedef union TALU64_X2Q |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64_X2Q; |
| }; |
| } TALU64_X2Q; |
| typedef union TALU64_PopParam |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ALU64_PopParam; |
| }; |
| } TALU64_PopParam; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ALU64_drvrd(SIE_ALU64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ALU64_drvwr(SIE_ALU64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ALU64_reset(SIE_ALU64 *p); |
| SIGN32 ALU64_cmp (SIE_ALU64 *p, SIE_ALU64 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ALU64_check(p,pie,pfx,hLOG) ALU64_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ALU64_print(p, pfx,hLOG) ALU64_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ALU64 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoTraceBuf biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 entry (P) |
| /// %unsigned 32 val |
| /// ### |
| /// * Register window for the trace buffer |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoTraceBuf |
| #define h_FigoTraceBuf (){} |
| |
| #define RA_FigoTraceBuf_entry 0x0000 |
| |
| #define BA_FigoTraceBuf_entry_val 0x0000 |
| #define B16FigoTraceBuf_entry_val 0x0000 |
| #define LSb32FigoTraceBuf_entry_val 0 |
| #define LSb16FigoTraceBuf_entry_val 0 |
| #define bFigoTraceBuf_entry_val 32 |
| #define MSK32FigoTraceBuf_entry_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoTraceBuf { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoTraceBuf_entry_val(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoTraceBuf_entry_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32FigoTraceBuf_entry {\ |
| UNSG32 uentry_val : 32;\ |
| } |
| union { UNSG32 u32FigoTraceBuf_entry; |
| struct w32FigoTraceBuf_entry; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoTraceBuf; |
| |
| typedef union T32FigoTraceBuf_entry |
| { UNSG32 u32; |
| struct w32FigoTraceBuf_entry; |
| } T32FigoTraceBuf_entry; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoTraceBuf_entry |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoTraceBuf_entry; |
| }; |
| } TFigoTraceBuf_entry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoTraceBuf_drvrd(SIE_FigoTraceBuf *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoTraceBuf_drvwr(SIE_FigoTraceBuf *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoTraceBuf_reset(SIE_FigoTraceBuf *p); |
| SIGN32 FigoTraceBuf_cmp (SIE_FigoTraceBuf *p, SIE_FigoTraceBuf *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoTraceBuf_check(p,pie,pfx,hLOG) FigoTraceBuf_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoTraceBuf_print(p, pfx,hLOG) FigoTraceBuf_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoTraceBuf |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoReg16 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 entry (P) |
| /// %unsigned 16 val |
| /// ### |
| /// * Register window for the trace buffer |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoReg16 |
| #define h_FigoReg16 (){} |
| |
| #define RA_FigoReg16_entry 0x0000 |
| |
| #define BA_FigoReg16_entry_val 0x0000 |
| #define B16FigoReg16_entry_val 0x0000 |
| #define LSb32FigoReg16_entry_val 0 |
| #define LSb16FigoReg16_entry_val 0 |
| #define bFigoReg16_entry_val 16 |
| #define MSK32FigoReg16_entry_val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoReg16 { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg16_entry_val(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoReg16_entry_val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoReg16_entry_val(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg16_entry_val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoReg16_entry {\ |
| UNSG32 uentry_val : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoReg16_entry; |
| struct w32FigoReg16_entry; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoReg16; |
| |
| typedef union T32FigoReg16_entry |
| { UNSG32 u32; |
| struct w32FigoReg16_entry; |
| } T32FigoReg16_entry; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoReg16_entry |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg16_entry; |
| }; |
| } TFigoReg16_entry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoReg16_drvrd(SIE_FigoReg16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoReg16_drvwr(SIE_FigoReg16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoReg16_reset(SIE_FigoReg16 *p); |
| SIGN32 FigoReg16_cmp (SIE_FigoReg16 *p, SIE_FigoReg16 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoReg16_check(p,pie,pfx,hLOG) FigoReg16_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoReg16_print(p, pfx,hLOG) FigoReg16_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoReg16 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoRF16Reg biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 entry (RW) |
| /// %unsigned 16 val 0x0 |
| /// ### |
| /// * Register window for the RF16 access in debug mode |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoRF16Reg |
| #define h_FigoRF16Reg (){} |
| |
| #define RA_FigoRF16Reg_entry 0x0000 |
| |
| #define BA_FigoRF16Reg_entry_val 0x0000 |
| #define B16FigoRF16Reg_entry_val 0x0000 |
| #define LSb32FigoRF16Reg_entry_val 0 |
| #define LSb16FigoRF16Reg_entry_val 0 |
| #define bFigoRF16Reg_entry_val 16 |
| #define MSK32FigoRF16Reg_entry_val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoRF16Reg { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoRF16Reg_entry_val(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoRF16Reg_entry_val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoRF16Reg_entry_val(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoRF16Reg_entry_val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoRF16Reg_entry {\ |
| UNSG32 uentry_val : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoRF16Reg_entry; |
| struct w32FigoRF16Reg_entry; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoRF16Reg; |
| |
| typedef union T32FigoRF16Reg_entry |
| { UNSG32 u32; |
| struct w32FigoRF16Reg_entry; |
| } T32FigoRF16Reg_entry; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoRF16Reg_entry |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoRF16Reg_entry; |
| }; |
| } TFigoRF16Reg_entry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoRF16Reg_drvrd(SIE_FigoRF16Reg *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoRF16Reg_drvwr(SIE_FigoRF16Reg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoRF16Reg_reset(SIE_FigoRF16Reg *p); |
| SIGN32 FigoRF16Reg_cmp (SIE_FigoRF16Reg *p, SIE_FigoRF16Reg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoRF16Reg_check(p,pie,pfx,hLOG) FigoRF16Reg_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoRF16Reg_print(p, pfx,hLOG) FigoRF16Reg_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoRF16Reg |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoMem16 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 entry (RW-) |
| /// %unsigned 16 val |
| /// ### |
| /// * Register window for the Jump Stack access in debug mode |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoMem16 |
| #define h_FigoMem16 (){} |
| |
| #define RA_FigoMem16_entry 0x0000 |
| |
| #define BA_FigoMem16_entry_val 0x0000 |
| #define B16FigoMem16_entry_val 0x0000 |
| #define LSb32FigoMem16_entry_val 0 |
| #define LSb16FigoMem16_entry_val 0 |
| #define bFigoMem16_entry_val 16 |
| #define MSK32FigoMem16_entry_val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoMem16 { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoMem16_entry_val(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoMem16_entry_val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoMem16_entry_val(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoMem16_entry_val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoMem16_entry {\ |
| UNSG32 uentry_val : 16;\ |
| UNSG32 RSVDx0_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoMem16_entry; |
| struct w32FigoMem16_entry; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoMem16; |
| |
| typedef union T32FigoMem16_entry |
| { UNSG32 u32; |
| struct w32FigoMem16_entry; |
| } T32FigoMem16_entry; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoMem16_entry |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoMem16_entry; |
| }; |
| } TFigoMem16_entry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoMem16_drvrd(SIE_FigoMem16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoMem16_drvwr(SIE_FigoMem16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoMem16_reset(SIE_FigoMem16 *p); |
| SIGN32 FigoMem16_cmp (SIE_FigoMem16 *p, SIE_FigoMem16 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoMem16_check(p,pie,pfx,hLOG) FigoMem16_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoMem16_print(p, pfx,hLOG) FigoMem16_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoMem16 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoMem32 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 entry (RW-) |
| /// %unsigned 32 val |
| /// ### |
| /// * Register window for the Jump Stack access in debug mode |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoMem32 |
| #define h_FigoMem32 (){} |
| |
| #define RA_FigoMem32_entry 0x0000 |
| |
| #define BA_FigoMem32_entry_val 0x0000 |
| #define B16FigoMem32_entry_val 0x0000 |
| #define LSb32FigoMem32_entry_val 0 |
| #define LSb16FigoMem32_entry_val 0 |
| #define bFigoMem32_entry_val 32 |
| #define MSK32FigoMem32_entry_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoMem32 { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoMem32_entry_val(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoMem32_entry_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32FigoMem32_entry {\ |
| UNSG32 uentry_val : 32;\ |
| } |
| union { UNSG32 u32FigoMem32_entry; |
| struct w32FigoMem32_entry; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoMem32; |
| |
| typedef union T32FigoMem32_entry |
| { UNSG32 u32; |
| struct w32FigoMem32_entry; |
| } T32FigoMem32_entry; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoMem32_entry |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoMem32_entry; |
| }; |
| } TFigoMem32_entry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoMem32_drvrd(SIE_FigoMem32 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoMem32_drvwr(SIE_FigoMem32 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoMem32_reset(SIE_FigoMem32 *p); |
| SIGN32 FigoMem32_cmp (SIE_FigoMem32 *p, SIE_FigoMem32 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoMem32_check(p,pie,pfx,hLOG) FigoMem32_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoMem32_print(p, pfx,hLOG) FigoMem32_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoMem32 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoDebug biu (4,4) |
| /// ### |
| /// * FIGO debug mode related registers and signals |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 figoDbg (RW-) |
| /// ### |
| /// * Puts FIGO in debug mode |
| /// ### |
| /// %unsigned 1 on 0x0 |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00004 figoDbgMode (P) |
| /// ### |
| /// * Determines FIGO's behavior in debug mode |
| /// ### |
| /// %unsigned 2 mode 0x0 |
| /// : stop 0x0 |
| /// ### |
| /// * FIGO flushes and stalls its pipeline |
| /// ### |
| /// : step 0x1 |
| /// ### |
| /// * FIGO executes one instruction at a time. Repeat to execute the next instruction. |
| /// ### |
| /// : slow_run 0x2 |
| /// ### |
| /// * FIGO inserts sufficient bubbles between each instruction to bypass all forwarding logic |
| /// ### |
| /// : fast_run 0x3 |
| /// ### |
| /// * FIGO resumes full-speed operation. Feature has been disabled due to timing impact. |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// @ 0x00008 figoDbgModeStatus (R-) |
| /// ### |
| /// * Similar to figoDbgMode, but read-only. Shows the actual status of FIGO, as it may be different from what is set in figoDbgMode. |
| /// ### |
| /// %unsigned 2 mode 0x0 |
| /// : stop 0x0 |
| /// : step 0x1 |
| /// : slow_run 0x2 |
| /// : fast_run 0x3 |
| /// ### |
| /// * Same enumerations |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// @ 0x0000C figoDbgTrigInMask (P) |
| /// ### |
| /// * 4 mask bits for trigger-in signals from up to 4 other FIGOs hitting breakpoints. |
| /// ### |
| /// %unsigned 4 on 0xF |
| /// ### |
| /// * On by default, all trigger-ins are blocked. |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x00010 (W-) |
| /// # # Stuffing bytes... |
| /// %% 384 |
| /// @ 0x00040 figoDbgRF16 (RW-) |
| /// ### |
| /// * BIU access to RF16 |
| /// ### |
| /// # 0x00040 rf16 |
| /// $FigoMem16 rf16 MEM [16] |
| /// ### |
| /// * Register mapping |
| /// * x0 = {d0,c0,b0,a0} = MEM[3:0] |
| /// * x1 = {d1,c1,b1,a1} = MEM[7:4] |
| /// * x2 = {d2,c2,b2,a2} = MEM[11:8] |
| /// * x3 = {d3,c3,b3,a3} = MEM[15:12] |
| /// ### |
| /// @ 0x00080 figoDbgRB (RW-) |
| /// ### |
| /// * BIU access to RB register |
| /// ### |
| /// %unsigned 16 rb 0x0 |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00084 figoDbgPCAtFetch (R-) |
| /// ### |
| /// * BIU access to PC register at Fetch stage |
| /// ### |
| /// %unsigned 16 pc 0x0 |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00088 (W-) |
| /// # # Stuffing bytes... |
| /// %% 64 |
| /// @ 0x00090 figoDbgJumpStack (RW-) |
| /// ### |
| /// * BIU access to jump stack |
| /// ### |
| /// # 0x00090 stack |
| /// $FigoMem32 stack MEM [4] |
| /// ### |
| /// * Register mapping |
| /// * MEM[0] = {branchPos[0],jumpDest[0]} |
| /// * MEM[1] = {branchPos[1],jumpDest[1]} |
| /// * MEM[2] = {branchPos[2],jumpDest[2]} |
| /// * MEM[3] = {branchPos[3],jumpDest[3]} |
| /// ### |
| /// @ 0x000A0 figoDbgStackDepth (R-) |
| /// ### |
| /// * BIU access to number of current jump stack entries |
| /// ### |
| /// %unsigned 5 depth 0x0 |
| /// ### |
| /// * Values are one-hot. Following actual stack pointer implementation inside FIGO so that no additional logic is required. |
| /// * 00001 = 0 valid entries (stack empty) |
| /// * 00010 = 1 valid entry |
| /// * 00100 = 2 valid entries |
| /// * 01000 = 3 valid entries |
| /// * 10000 = 4 valid entries (stack full) |
| /// ### |
| /// %% 27 # Stuffing bits... |
| /// @ 0x000A4 figoDbgFlags (R-) |
| /// ### |
| /// * BIU access to flags register |
| /// ### |
| /// %unsigned 16 flags 0x0 |
| /// ### |
| /// * flags[15:0] = {LSj, Lj, GSj, Gj, LS, L, GS, G, 1, 0, Cj, Zj, V, N, C, Z} |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x000A8 figoDbgBreak (WOC-) |
| /// ### |
| /// * Bit that indicates FIGO entered debug mode due to breakpoint |
| /// ### |
| /// %unsigned 1 up 0x0 |
| /// ### |
| /// * Write one to clear |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x000AC figoDbgBkBitWen (P) |
| /// ### |
| /// * Enable bit to allow breakpoint bits to be written into ITCM by BIU. |
| /// ### |
| /// %unsigned 1 en 0x0 |
| /// ### |
| /// * Additional enable bit to safeguard against accidentally writing ones into the breakpoint fields of the ITCM. |
| /// * Register window for the trace buffer |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x000B0 (W-) |
| /// # # Stuffing bytes... |
| /// %% 128 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 192B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoDebug |
| #define h_FigoDebug (){} |
| |
| #define RA_FigoDebug_figoDbg 0x0000 |
| |
| #define BA_FigoDebug_figoDbg_on 0x0000 |
| #define B16FigoDebug_figoDbg_on 0x0000 |
| #define LSb32FigoDebug_figoDbg_on 0 |
| #define LSb16FigoDebug_figoDbg_on 0 |
| #define bFigoDebug_figoDbg_on 1 |
| #define MSK32FigoDebug_figoDbg_on 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgMode 0x0004 |
| |
| #define BA_FigoDebug_figoDbgMode_mode 0x0004 |
| #define B16FigoDebug_figoDbgMode_mode 0x0004 |
| #define LSb32FigoDebug_figoDbgMode_mode 0 |
| #define LSb16FigoDebug_figoDbgMode_mode 0 |
| #define bFigoDebug_figoDbgMode_mode 2 |
| #define MSK32FigoDebug_figoDbgMode_mode 0x00000003 |
| #define FigoDebug_figoDbgMode_mode_stop 0x0 |
| #define FigoDebug_figoDbgMode_mode_step 0x1 |
| #define FigoDebug_figoDbgMode_mode_slow_run 0x2 |
| #define FigoDebug_figoDbgMode_mode_fast_run 0x3 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgModeStatus 0x0008 |
| |
| #define BA_FigoDebug_figoDbgModeStatus_mode 0x0008 |
| #define B16FigoDebug_figoDbgModeStatus_mode 0x0008 |
| #define LSb32FigoDebug_figoDbgModeStatus_mode 0 |
| #define LSb16FigoDebug_figoDbgModeStatus_mode 0 |
| #define bFigoDebug_figoDbgModeStatus_mode 2 |
| #define MSK32FigoDebug_figoDbgModeStatus_mode 0x00000003 |
| #define FigoDebug_figoDbgModeStatus_mode_stop 0x0 |
| #define FigoDebug_figoDbgModeStatus_mode_step 0x1 |
| #define FigoDebug_figoDbgModeStatus_mode_slow_run 0x2 |
| #define FigoDebug_figoDbgModeStatus_mode_fast_run 0x3 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgTrigInMask 0x000C |
| |
| #define BA_FigoDebug_figoDbgTrigInMask_on 0x000C |
| #define B16FigoDebug_figoDbgTrigInMask_on 0x000C |
| #define LSb32FigoDebug_figoDbgTrigInMask_on 0 |
| #define LSb16FigoDebug_figoDbgTrigInMask_on 0 |
| #define bFigoDebug_figoDbgTrigInMask_on 4 |
| #define MSK32FigoDebug_figoDbgTrigInMask_on 0x0000000F |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgRF16 0x0040 |
| #define RA_FigoDebug_rf16 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgRB 0x0080 |
| |
| #define BA_FigoDebug_figoDbgRB_rb 0x0080 |
| #define B16FigoDebug_figoDbgRB_rb 0x0080 |
| #define LSb32FigoDebug_figoDbgRB_rb 0 |
| #define LSb16FigoDebug_figoDbgRB_rb 0 |
| #define bFigoDebug_figoDbgRB_rb 16 |
| #define MSK32FigoDebug_figoDbgRB_rb 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgPCAtFetch 0x0084 |
| |
| #define BA_FigoDebug_figoDbgPCAtFetch_pc 0x0084 |
| #define B16FigoDebug_figoDbgPCAtFetch_pc 0x0084 |
| #define LSb32FigoDebug_figoDbgPCAtFetch_pc 0 |
| #define LSb16FigoDebug_figoDbgPCAtFetch_pc 0 |
| #define bFigoDebug_figoDbgPCAtFetch_pc 16 |
| #define MSK32FigoDebug_figoDbgPCAtFetch_pc 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgJumpStack 0x0090 |
| #define RA_FigoDebug_stack 0x0090 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgStackDepth 0x00A0 |
| |
| #define BA_FigoDebug_figoDbgStackDepth_depth 0x00A0 |
| #define B16FigoDebug_figoDbgStackDepth_depth 0x00A0 |
| #define LSb32FigoDebug_figoDbgStackDepth_depth 0 |
| #define LSb16FigoDebug_figoDbgStackDepth_depth 0 |
| #define bFigoDebug_figoDbgStackDepth_depth 5 |
| #define MSK32FigoDebug_figoDbgStackDepth_depth 0x0000001F |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgFlags 0x00A4 |
| |
| #define BA_FigoDebug_figoDbgFlags_flags 0x00A4 |
| #define B16FigoDebug_figoDbgFlags_flags 0x00A4 |
| #define LSb32FigoDebug_figoDbgFlags_flags 0 |
| #define LSb16FigoDebug_figoDbgFlags_flags 0 |
| #define bFigoDebug_figoDbgFlags_flags 16 |
| #define MSK32FigoDebug_figoDbgFlags_flags 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgBreak 0x00A8 |
| |
| #define BA_FigoDebug_figoDbgBreak_up 0x00A8 |
| #define B16FigoDebug_figoDbgBreak_up 0x00A8 |
| #define LSb32FigoDebug_figoDbgBreak_up 0 |
| #define LSb16FigoDebug_figoDbgBreak_up 0 |
| #define bFigoDebug_figoDbgBreak_up 1 |
| #define MSK32FigoDebug_figoDbgBreak_up 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoDebug_figoDbgBkBitWen 0x00AC |
| |
| #define BA_FigoDebug_figoDbgBkBitWen_en 0x00AC |
| #define B16FigoDebug_figoDbgBkBitWen_en 0x00AC |
| #define LSb32FigoDebug_figoDbgBkBitWen_en 0 |
| #define LSb16FigoDebug_figoDbgBkBitWen_en 0 |
| #define bFigoDebug_figoDbgBkBitWen_en 1 |
| #define MSK32FigoDebug_figoDbgBkBitWen_en 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoDebug { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbg_on(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoDebug_figoDbg_on(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoDebug_figoDbg_on(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoDebug_figoDbg_on(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoDebug_figoDbg {\ |
| UNSG32 ufigoDbg_on : 1;\ |
| UNSG32 RSVDx0_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbg; |
| struct w32FigoDebug_figoDbg; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgMode_mode(r32) _BFGET_(r32, 1, 0) |
| #define SET32FigoDebug_figoDbgMode_mode(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16FigoDebug_figoDbgMode_mode(r16) _BFGET_(r16, 1, 0) |
| #define SET16FigoDebug_figoDbgMode_mode(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define w32FigoDebug_figoDbgMode {\ |
| UNSG32 ufigoDbgMode_mode : 2;\ |
| UNSG32 RSVDx4_b2 : 30;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgMode; |
| struct w32FigoDebug_figoDbgMode; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgModeStatus_mode(r32) _BFGET_(r32, 1, 0) |
| #define SET32FigoDebug_figoDbgModeStatus_mode(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16FigoDebug_figoDbgModeStatus_mode(r16) _BFGET_(r16, 1, 0) |
| #define SET16FigoDebug_figoDbgModeStatus_mode(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define w32FigoDebug_figoDbgModeStatus {\ |
| UNSG32 ufigoDbgModeStatus_mode : 2;\ |
| UNSG32 RSVDx8_b2 : 30;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgModeStatus; |
| struct w32FigoDebug_figoDbgModeStatus; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgTrigInMask_on(r32) _BFGET_(r32, 3, 0) |
| #define SET32FigoDebug_figoDbgTrigInMask_on(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16FigoDebug_figoDbgTrigInMask_on(r16) _BFGET_(r16, 3, 0) |
| #define SET16FigoDebug_figoDbgTrigInMask_on(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define w32FigoDebug_figoDbgTrigInMask {\ |
| UNSG32 ufigoDbgTrigInMask_on : 4;\ |
| UNSG32 RSVDxC_b4 : 28;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgTrigInMask; |
| struct w32FigoDebug_figoDbgTrigInMask; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx10 [48]; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoMem16 ie_rf16[16]; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgRB_rb(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoDebug_figoDbgRB_rb(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoDebug_figoDbgRB_rb(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoDebug_figoDbgRB_rb(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoDebug_figoDbgRB {\ |
| UNSG32 ufigoDbgRB_rb : 16;\ |
| UNSG32 RSVDx80_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgRB; |
| struct w32FigoDebug_figoDbgRB; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgPCAtFetch_pc(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoDebug_figoDbgPCAtFetch_pc(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoDebug_figoDbgPCAtFetch_pc(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoDebug_figoDbgPCAtFetch_pc(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoDebug_figoDbgPCAtFetch {\ |
| UNSG32 ufigoDbgPCAtFetch_pc : 16;\ |
| UNSG32 RSVDx84_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgPCAtFetch; |
| struct w32FigoDebug_figoDbgPCAtFetch; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx88 [8]; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoMem32 ie_stack[4]; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgStackDepth_depth(r32) _BFGET_(r32, 4, 0) |
| #define SET32FigoDebug_figoDbgStackDepth_depth(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16FigoDebug_figoDbgStackDepth_depth(r16) _BFGET_(r16, 4, 0) |
| #define SET16FigoDebug_figoDbgStackDepth_depth(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define w32FigoDebug_figoDbgStackDepth {\ |
| UNSG32 ufigoDbgStackDepth_depth : 5;\ |
| UNSG32 RSVDxA0_b5 : 27;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgStackDepth; |
| struct w32FigoDebug_figoDbgStackDepth; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgFlags_flags(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoDebug_figoDbgFlags_flags(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoDebug_figoDbgFlags_flags(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoDebug_figoDbgFlags_flags(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoDebug_figoDbgFlags {\ |
| UNSG32 ufigoDbgFlags_flags : 16;\ |
| UNSG32 RSVDxA4_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgFlags; |
| struct w32FigoDebug_figoDbgFlags; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgBreak_up(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoDebug_figoDbgBreak_up(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoDebug_figoDbgBreak_up(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoDebug_figoDbgBreak_up(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoDebug_figoDbgBreak {\ |
| UNSG32 ufigoDbgBreak_up : 1;\ |
| UNSG32 RSVDxA8_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgBreak; |
| struct w32FigoDebug_figoDbgBreak; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoDebug_figoDbgBkBitWen_en(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoDebug_figoDbgBkBitWen_en(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoDebug_figoDbgBkBitWen_en(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoDebug_figoDbgBkBitWen_en(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoDebug_figoDbgBkBitWen {\ |
| UNSG32 ufigoDbgBkBitWen_en : 1;\ |
| UNSG32 RSVDxAC_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoDebug_figoDbgBkBitWen; |
| struct w32FigoDebug_figoDbgBkBitWen; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxB0 [16]; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoDebug; |
| |
| typedef union T32FigoDebug_figoDbg |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbg; |
| } T32FigoDebug_figoDbg; |
| typedef union T32FigoDebug_figoDbgMode |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgMode; |
| } T32FigoDebug_figoDbgMode; |
| typedef union T32FigoDebug_figoDbgModeStatus |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgModeStatus; |
| } T32FigoDebug_figoDbgModeStatus; |
| typedef union T32FigoDebug_figoDbgTrigInMask |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgTrigInMask; |
| } T32FigoDebug_figoDbgTrigInMask; |
| typedef union T32FigoDebug_figoDbgRB |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgRB; |
| } T32FigoDebug_figoDbgRB; |
| typedef union T32FigoDebug_figoDbgPCAtFetch |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgPCAtFetch; |
| } T32FigoDebug_figoDbgPCAtFetch; |
| typedef union T32FigoDebug_figoDbgStackDepth |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgStackDepth; |
| } T32FigoDebug_figoDbgStackDepth; |
| typedef union T32FigoDebug_figoDbgFlags |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgFlags; |
| } T32FigoDebug_figoDbgFlags; |
| typedef union T32FigoDebug_figoDbgBreak |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgBreak; |
| } T32FigoDebug_figoDbgBreak; |
| typedef union T32FigoDebug_figoDbgBkBitWen |
| { UNSG32 u32; |
| struct w32FigoDebug_figoDbgBkBitWen; |
| } T32FigoDebug_figoDbgBkBitWen; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoDebug_figoDbg |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbg; |
| }; |
| } TFigoDebug_figoDbg; |
| typedef union TFigoDebug_figoDbgMode |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgMode; |
| }; |
| } TFigoDebug_figoDbgMode; |
| typedef union TFigoDebug_figoDbgModeStatus |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgModeStatus; |
| }; |
| } TFigoDebug_figoDbgModeStatus; |
| typedef union TFigoDebug_figoDbgTrigInMask |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgTrigInMask; |
| }; |
| } TFigoDebug_figoDbgTrigInMask; |
| typedef union TFigoDebug_figoDbgRB |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgRB; |
| }; |
| } TFigoDebug_figoDbgRB; |
| typedef union TFigoDebug_figoDbgPCAtFetch |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgPCAtFetch; |
| }; |
| } TFigoDebug_figoDbgPCAtFetch; |
| typedef union TFigoDebug_figoDbgStackDepth |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgStackDepth; |
| }; |
| } TFigoDebug_figoDbgStackDepth; |
| typedef union TFigoDebug_figoDbgFlags |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgFlags; |
| }; |
| } TFigoDebug_figoDbgFlags; |
| typedef union TFigoDebug_figoDbgBreak |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgBreak; |
| }; |
| } TFigoDebug_figoDbgBreak; |
| typedef union TFigoDebug_figoDbgBkBitWen |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoDebug_figoDbgBkBitWen; |
| }; |
| } TFigoDebug_figoDbgBkBitWen; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoDebug_drvrd(SIE_FigoDebug *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoDebug_drvwr(SIE_FigoDebug *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoDebug_reset(SIE_FigoDebug *p); |
| SIGN32 FigoDebug_cmp (SIE_FigoDebug *p, SIE_FigoDebug *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoDebug_check(p,pie,pfx,hLOG) FigoDebug_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoDebug_print(p, pfx,hLOG) FigoDebug_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoDebug |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoReg biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 figoCtrl (P) |
| /// %unsigned 16 pcStartLoc 0x0 |
| /// %unsigned 1 tBufMode 0x0 |
| /// : freeRun 0x0 |
| /// ### |
| /// * Trace buffer operating as ring buffer |
| /// ### |
| /// : fifoMode 0x1 |
| /// ### |
| /// * Trace buffer operating as FIFO; FIGO stalls when full |
| /// ### |
| /// %% 15 # Stuffing bits... |
| /// @ 0x00004 figoID (R-) |
| /// ### |
| /// * Processor ID, unique for each FIGO |
| /// ### |
| /// %unsigned 16 ID 0x0 |
| /// ### |
| /// * Processor ID. Specified in FIGO baseline subsystem configuration file. |
| /// ### |
| /// %unsigned 16 REV 0x0 |
| /// ### |
| /// * Revision ID. Hard-coded in FIGO core RTL. |
| /// ### |
| /// @ 0x00008 figoMaxAdr (P) |
| /// ### |
| /// * Max address for ITCM and DTCM, used to detect addr out-of-bound |
| /// ### |
| /// %unsigned 16 itcm 0xFFFF |
| /// %unsigned 16 dtcm 0xFFFF |
| /// @ 0x0000C figoFlags (WOC-) |
| /// ### |
| /// * Exception flags; FIGO halts when unmasked exception happens; write one to clear |
| /// ### |
| /// %unsigned 1 itcmAdrOOB 0x0 |
| /// ### |
| /// * ITCM address > figoMaxAdr.itcm |
| /// ### |
| /// %unsigned 1 dtcmAdrOOB 0x0 |
| /// ### |
| /// * DTCM address > figoMaxAdr.dtcm |
| /// ### |
| /// %unsigned 1 divideBy0 0x0 |
| /// ### |
| /// * MDU divide by 0 detected |
| /// ### |
| /// %unsigned 1 traceBufFull 0x0 |
| /// ### |
| /// * Trace buffer is full. Only valid when figoCtrl.tBufMode = fifoMode |
| /// ### |
| /// %unsigned 1 illegalIns 0x0 |
| /// ### |
| /// * Illegal instruction detected at ID stage |
| /// ### |
| /// %unsigned 1 ALU64Overflow 0x0 |
| /// ### |
| /// * One of the ALU64 extensions asserted a command push overflow. |
| /// ### |
| /// %unsigned 1 JTInvdPush 0x0 |
| /// ### |
| /// * Detected a jump table push when it's already full. |
| /// ### |
| /// %% 25 # Stuffing bits... |
| /// @ 0x00010 figoFlagsMask (P) |
| /// ### |
| /// * Mask bits for FIGO exception flags. Does not block exception flags from asserting, instead, it prevents FIGO from halting when the masked exception occurs. |
| /// ### |
| /// %unsigned 1 itcmAdrOOBMask 0x0 |
| /// %unsigned 1 dtcmAdrOOBMask 0x0 |
| /// %unsigned 1 divideBy0Mask 0x0 |
| /// %unsigned 1 traceBufFullMask 0x0 |
| /// %unsigned 1 illegalInsMask 0x0 |
| /// %unsigned 1 ALU64OverflowMask 0x0 |
| /// %unsigned 1 JTInvdPushMask 0x0 |
| /// %% 25 # Stuffing bits... |
| /// @ 0x00014 figoLastPC (R-) |
| /// ### |
| /// * Last PC value before exception occurred |
| /// ### |
| /// %unsigned 16 val 0x0 |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00018 figoCurrPC (R-) |
| /// # 0x00018 pc |
| /// $FigoReg16 pc MEM |
| /// ### |
| /// * Current PC value @ ID stage |
| /// ### |
| /// @ 0x0001C figoTraceBuf (RW-) |
| /// # 0x0001C tbuf |
| /// $FigoTraceBuf tbuf MEM |
| /// ### |
| /// * Register window for the trace buffer |
| /// ### |
| /// @ 0x00020 figoIntr (W-) |
| /// ### |
| /// * Special register for FIGO to raise interrupt to CPU via vPro semaphore; write to raise interrupt; no status |
| /// ### |
| /// %unsigned 1 up 0x0 |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00024 figoIntrLvl (WOC-) |
| /// ### |
| /// * Special register to record that interrupt has occurred; to be used as level interrupt; cleared by writing 1 |
| /// ### |
| /// %unsigned 1 st 0x0 |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00028 figoRstn (RW-) |
| /// ### |
| /// * Special register to stop / reset FIGO execution; write 1 to release FIGO, write 0 to reset FIGO (sticky) |
| /// ### |
| /// %unsigned 1 up 0x0 |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0002C figoCnt (RW-) |
| /// ### |
| /// * Controls the FIGO counter behavior |
| /// ### |
| /// %unsigned 1 en 0x0 |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00030 figoCntClr (W-) |
| /// ### |
| /// * Clear FIGO counters; write 1 to clear specific counters |
| /// ### |
| /// %unsigned 1 run |
| /// %unsigned 1 stall |
| /// %% 30 # Stuffing bits... |
| /// @ 0x00034 figoRun (R-) |
| /// %unsigned 32 Cnt 0x0 |
| /// @ 0x00038 figoStall (R-) |
| /// %unsigned 32 Cnt 0x0 |
| /// @ 0x0003C (W-) |
| /// # # Stuffing bytes... |
| /// %% 15904 |
| /// @ 0x00800 ALU64 (P) |
| /// # 0x00800 alu64 |
| /// $ALU64 alu64 REG |
| /// ### |
| /// * ALU64 extensions access via AHB |
| /// ### |
| /// @ 0x01800 FIGODBG (P) |
| /// # 0x01800 debug |
| /// $FigoDebug debug REG |
| /// @ 0x018C0 wdCnt (P) |
| /// %unsigned 32 threshold 0xFFFF |
| /// ### |
| /// * When set to “0”, the watch dot timer will be disabled, it will not count and also won't trigger the overflow status. |
| /// ### |
| /// @ 0x018C4 wdClr (W-) |
| /// %unsigned 1 en |
| /// ### |
| /// * Write “1” to this register will clear the watchdog timer value to “0”. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x018C8 wdSt (WOC-) |
| /// %unsigned 1 overflow 0x0 |
| /// ### |
| /// * Overflow will be set when the watchdog timer value >= wdCnt.threshold. |
| /// * Write “1” to this register will clear the status to 0. |
| /// * Debug mode related registers |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x018CC (W-) |
| /// # # Stuffing bytes... |
| /// %% 14752 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8192B, bits: 557b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoReg |
| #define h_FigoReg (){} |
| |
| #define RA_FigoReg_figoCtrl 0x0000 |
| |
| #define BA_FigoReg_figoCtrl_pcStartLoc 0x0000 |
| #define B16FigoReg_figoCtrl_pcStartLoc 0x0000 |
| #define LSb32FigoReg_figoCtrl_pcStartLoc 0 |
| #define LSb16FigoReg_figoCtrl_pcStartLoc 0 |
| #define bFigoReg_figoCtrl_pcStartLoc 16 |
| #define MSK32FigoReg_figoCtrl_pcStartLoc 0x0000FFFF |
| |
| #define BA_FigoReg_figoCtrl_tBufMode 0x0002 |
| #define B16FigoReg_figoCtrl_tBufMode 0x0002 |
| #define LSb32FigoReg_figoCtrl_tBufMode 16 |
| #define LSb16FigoReg_figoCtrl_tBufMode 0 |
| #define bFigoReg_figoCtrl_tBufMode 1 |
| #define MSK32FigoReg_figoCtrl_tBufMode 0x00010000 |
| #define FigoReg_figoCtrl_tBufMode_freeRun 0x0 |
| #define FigoReg_figoCtrl_tBufMode_fifoMode 0x1 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoID 0x0004 |
| |
| #define BA_FigoReg_figoID_ID 0x0004 |
| #define B16FigoReg_figoID_ID 0x0004 |
| #define LSb32FigoReg_figoID_ID 0 |
| #define LSb16FigoReg_figoID_ID 0 |
| #define bFigoReg_figoID_ID 16 |
| #define MSK32FigoReg_figoID_ID 0x0000FFFF |
| |
| #define BA_FigoReg_figoID_REV 0x0006 |
| #define B16FigoReg_figoID_REV 0x0006 |
| #define LSb32FigoReg_figoID_REV 16 |
| #define LSb16FigoReg_figoID_REV 0 |
| #define bFigoReg_figoID_REV 16 |
| #define MSK32FigoReg_figoID_REV 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoMaxAdr 0x0008 |
| |
| #define BA_FigoReg_figoMaxAdr_itcm 0x0008 |
| #define B16FigoReg_figoMaxAdr_itcm 0x0008 |
| #define LSb32FigoReg_figoMaxAdr_itcm 0 |
| #define LSb16FigoReg_figoMaxAdr_itcm 0 |
| #define bFigoReg_figoMaxAdr_itcm 16 |
| #define MSK32FigoReg_figoMaxAdr_itcm 0x0000FFFF |
| |
| #define BA_FigoReg_figoMaxAdr_dtcm 0x000A |
| #define B16FigoReg_figoMaxAdr_dtcm 0x000A |
| #define LSb32FigoReg_figoMaxAdr_dtcm 16 |
| #define LSb16FigoReg_figoMaxAdr_dtcm 0 |
| #define bFigoReg_figoMaxAdr_dtcm 16 |
| #define MSK32FigoReg_figoMaxAdr_dtcm 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoFlags 0x000C |
| |
| #define BA_FigoReg_figoFlags_itcmAdrOOB 0x000C |
| #define B16FigoReg_figoFlags_itcmAdrOOB 0x000C |
| #define LSb32FigoReg_figoFlags_itcmAdrOOB 0 |
| #define LSb16FigoReg_figoFlags_itcmAdrOOB 0 |
| #define bFigoReg_figoFlags_itcmAdrOOB 1 |
| #define MSK32FigoReg_figoFlags_itcmAdrOOB 0x00000001 |
| |
| #define BA_FigoReg_figoFlags_dtcmAdrOOB 0x000C |
| #define B16FigoReg_figoFlags_dtcmAdrOOB 0x000C |
| #define LSb32FigoReg_figoFlags_dtcmAdrOOB 1 |
| #define LSb16FigoReg_figoFlags_dtcmAdrOOB 1 |
| #define bFigoReg_figoFlags_dtcmAdrOOB 1 |
| #define MSK32FigoReg_figoFlags_dtcmAdrOOB 0x00000002 |
| |
| #define BA_FigoReg_figoFlags_divideBy0 0x000C |
| #define B16FigoReg_figoFlags_divideBy0 0x000C |
| #define LSb32FigoReg_figoFlags_divideBy0 2 |
| #define LSb16FigoReg_figoFlags_divideBy0 2 |
| #define bFigoReg_figoFlags_divideBy0 1 |
| #define MSK32FigoReg_figoFlags_divideBy0 0x00000004 |
| |
| #define BA_FigoReg_figoFlags_traceBufFull 0x000C |
| #define B16FigoReg_figoFlags_traceBufFull 0x000C |
| #define LSb32FigoReg_figoFlags_traceBufFull 3 |
| #define LSb16FigoReg_figoFlags_traceBufFull 3 |
| #define bFigoReg_figoFlags_traceBufFull 1 |
| #define MSK32FigoReg_figoFlags_traceBufFull 0x00000008 |
| |
| #define BA_FigoReg_figoFlags_illegalIns 0x000C |
| #define B16FigoReg_figoFlags_illegalIns 0x000C |
| #define LSb32FigoReg_figoFlags_illegalIns 4 |
| #define LSb16FigoReg_figoFlags_illegalIns 4 |
| #define bFigoReg_figoFlags_illegalIns 1 |
| #define MSK32FigoReg_figoFlags_illegalIns 0x00000010 |
| |
| #define BA_FigoReg_figoFlags_ALU64Overflow 0x000C |
| #define B16FigoReg_figoFlags_ALU64Overflow 0x000C |
| #define LSb32FigoReg_figoFlags_ALU64Overflow 5 |
| #define LSb16FigoReg_figoFlags_ALU64Overflow 5 |
| #define bFigoReg_figoFlags_ALU64Overflow 1 |
| #define MSK32FigoReg_figoFlags_ALU64Overflow 0x00000020 |
| |
| #define BA_FigoReg_figoFlags_JTInvdPush 0x000C |
| #define B16FigoReg_figoFlags_JTInvdPush 0x000C |
| #define LSb32FigoReg_figoFlags_JTInvdPush 6 |
| #define LSb16FigoReg_figoFlags_JTInvdPush 6 |
| #define bFigoReg_figoFlags_JTInvdPush 1 |
| #define MSK32FigoReg_figoFlags_JTInvdPush 0x00000040 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoFlagsMask 0x0010 |
| |
| #define BA_FigoReg_figoFlagsMask_itcmAdrOOBMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_itcmAdrOOBMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_itcmAdrOOBMask 0 |
| #define LSb16FigoReg_figoFlagsMask_itcmAdrOOBMask 0 |
| #define bFigoReg_figoFlagsMask_itcmAdrOOBMask 1 |
| #define MSK32FigoReg_figoFlagsMask_itcmAdrOOBMask 0x00000001 |
| |
| #define BA_FigoReg_figoFlagsMask_dtcmAdrOOBMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_dtcmAdrOOBMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_dtcmAdrOOBMask 1 |
| #define LSb16FigoReg_figoFlagsMask_dtcmAdrOOBMask 1 |
| #define bFigoReg_figoFlagsMask_dtcmAdrOOBMask 1 |
| #define MSK32FigoReg_figoFlagsMask_dtcmAdrOOBMask 0x00000002 |
| |
| #define BA_FigoReg_figoFlagsMask_divideBy0Mask 0x0010 |
| #define B16FigoReg_figoFlagsMask_divideBy0Mask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_divideBy0Mask 2 |
| #define LSb16FigoReg_figoFlagsMask_divideBy0Mask 2 |
| #define bFigoReg_figoFlagsMask_divideBy0Mask 1 |
| #define MSK32FigoReg_figoFlagsMask_divideBy0Mask 0x00000004 |
| |
| #define BA_FigoReg_figoFlagsMask_traceBufFullMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_traceBufFullMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_traceBufFullMask 3 |
| #define LSb16FigoReg_figoFlagsMask_traceBufFullMask 3 |
| #define bFigoReg_figoFlagsMask_traceBufFullMask 1 |
| #define MSK32FigoReg_figoFlagsMask_traceBufFullMask 0x00000008 |
| |
| #define BA_FigoReg_figoFlagsMask_illegalInsMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_illegalInsMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_illegalInsMask 4 |
| #define LSb16FigoReg_figoFlagsMask_illegalInsMask 4 |
| #define bFigoReg_figoFlagsMask_illegalInsMask 1 |
| #define MSK32FigoReg_figoFlagsMask_illegalInsMask 0x00000010 |
| |
| #define BA_FigoReg_figoFlagsMask_ALU64OverflowMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_ALU64OverflowMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_ALU64OverflowMask 5 |
| #define LSb16FigoReg_figoFlagsMask_ALU64OverflowMask 5 |
| #define bFigoReg_figoFlagsMask_ALU64OverflowMask 1 |
| #define MSK32FigoReg_figoFlagsMask_ALU64OverflowMask 0x00000020 |
| |
| #define BA_FigoReg_figoFlagsMask_JTInvdPushMask 0x0010 |
| #define B16FigoReg_figoFlagsMask_JTInvdPushMask 0x0010 |
| #define LSb32FigoReg_figoFlagsMask_JTInvdPushMask 6 |
| #define LSb16FigoReg_figoFlagsMask_JTInvdPushMask 6 |
| #define bFigoReg_figoFlagsMask_JTInvdPushMask 1 |
| #define MSK32FigoReg_figoFlagsMask_JTInvdPushMask 0x00000040 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoLastPC 0x0014 |
| |
| #define BA_FigoReg_figoLastPC_val 0x0014 |
| #define B16FigoReg_figoLastPC_val 0x0014 |
| #define LSb32FigoReg_figoLastPC_val 0 |
| #define LSb16FigoReg_figoLastPC_val 0 |
| #define bFigoReg_figoLastPC_val 16 |
| #define MSK32FigoReg_figoLastPC_val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoCurrPC 0x0018 |
| #define RA_FigoReg_pc 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoTraceBuf 0x001C |
| #define RA_FigoReg_tbuf 0x001C |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoIntr 0x0020 |
| |
| #define BA_FigoReg_figoIntr_up 0x0020 |
| #define B16FigoReg_figoIntr_up 0x0020 |
| #define LSb32FigoReg_figoIntr_up 0 |
| #define LSb16FigoReg_figoIntr_up 0 |
| #define bFigoReg_figoIntr_up 1 |
| #define MSK32FigoReg_figoIntr_up 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoIntrLvl 0x0024 |
| |
| #define BA_FigoReg_figoIntrLvl_st 0x0024 |
| #define B16FigoReg_figoIntrLvl_st 0x0024 |
| #define LSb32FigoReg_figoIntrLvl_st 0 |
| #define LSb16FigoReg_figoIntrLvl_st 0 |
| #define bFigoReg_figoIntrLvl_st 1 |
| #define MSK32FigoReg_figoIntrLvl_st 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoRstn 0x0028 |
| |
| #define BA_FigoReg_figoRstn_up 0x0028 |
| #define B16FigoReg_figoRstn_up 0x0028 |
| #define LSb32FigoReg_figoRstn_up 0 |
| #define LSb16FigoReg_figoRstn_up 0 |
| #define bFigoReg_figoRstn_up 1 |
| #define MSK32FigoReg_figoRstn_up 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoCnt 0x002C |
| |
| #define BA_FigoReg_figoCnt_en 0x002C |
| #define B16FigoReg_figoCnt_en 0x002C |
| #define LSb32FigoReg_figoCnt_en 0 |
| #define LSb16FigoReg_figoCnt_en 0 |
| #define bFigoReg_figoCnt_en 1 |
| #define MSK32FigoReg_figoCnt_en 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoCntClr 0x0030 |
| |
| #define BA_FigoReg_figoCntClr_run 0x0030 |
| #define B16FigoReg_figoCntClr_run 0x0030 |
| #define LSb32FigoReg_figoCntClr_run 0 |
| #define LSb16FigoReg_figoCntClr_run 0 |
| #define bFigoReg_figoCntClr_run 1 |
| #define MSK32FigoReg_figoCntClr_run 0x00000001 |
| |
| #define BA_FigoReg_figoCntClr_stall 0x0030 |
| #define B16FigoReg_figoCntClr_stall 0x0030 |
| #define LSb32FigoReg_figoCntClr_stall 1 |
| #define LSb16FigoReg_figoCntClr_stall 1 |
| #define bFigoReg_figoCntClr_stall 1 |
| #define MSK32FigoReg_figoCntClr_stall 0x00000002 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoRun 0x0034 |
| |
| #define BA_FigoReg_figoRun_Cnt 0x0034 |
| #define B16FigoReg_figoRun_Cnt 0x0034 |
| #define LSb32FigoReg_figoRun_Cnt 0 |
| #define LSb16FigoReg_figoRun_Cnt 0 |
| #define bFigoReg_figoRun_Cnt 32 |
| #define MSK32FigoReg_figoRun_Cnt 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_figoStall 0x0038 |
| |
| #define BA_FigoReg_figoStall_Cnt 0x0038 |
| #define B16FigoReg_figoStall_Cnt 0x0038 |
| #define LSb32FigoReg_figoStall_Cnt 0 |
| #define LSb16FigoReg_figoStall_Cnt 0 |
| #define bFigoReg_figoStall_Cnt 32 |
| #define MSK32FigoReg_figoStall_Cnt 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_ALU64 0x0800 |
| #define RA_FigoReg_alu64 0x0800 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_FIGODBG 0x1800 |
| #define RA_FigoReg_debug 0x1800 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_wdCnt 0x18C0 |
| |
| #define BA_FigoReg_wdCnt_threshold 0x18C0 |
| #define B16FigoReg_wdCnt_threshold 0x18C0 |
| #define LSb32FigoReg_wdCnt_threshold 0 |
| #define LSb16FigoReg_wdCnt_threshold 0 |
| #define bFigoReg_wdCnt_threshold 32 |
| #define MSK32FigoReg_wdCnt_threshold 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_wdClr 0x18C4 |
| |
| #define BA_FigoReg_wdClr_en 0x18C4 |
| #define B16FigoReg_wdClr_en 0x18C4 |
| #define LSb32FigoReg_wdClr_en 0 |
| #define LSb16FigoReg_wdClr_en 0 |
| #define bFigoReg_wdClr_en 1 |
| #define MSK32FigoReg_wdClr_en 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoReg_wdSt 0x18C8 |
| |
| #define BA_FigoReg_wdSt_overflow 0x18C8 |
| #define B16FigoReg_wdSt_overflow 0x18C8 |
| #define LSb32FigoReg_wdSt_overflow 0 |
| #define LSb16FigoReg_wdSt_overflow 0 |
| #define bFigoReg_wdSt_overflow 1 |
| #define MSK32FigoReg_wdSt_overflow 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoReg { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoCtrl_pcStartLoc(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoReg_figoCtrl_pcStartLoc(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoReg_figoCtrl_pcStartLoc(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoCtrl_pcStartLoc(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32FigoReg_figoCtrl_tBufMode(r32) _BFGET_(r32,16,16) |
| #define SET32FigoReg_figoCtrl_tBufMode(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16FigoReg_figoCtrl_tBufMode(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoCtrl_tBufMode(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_figoCtrl {\ |
| UNSG32 ufigoCtrl_pcStartLoc : 16;\ |
| UNSG32 ufigoCtrl_tBufMode : 1;\ |
| UNSG32 RSVDx0_b17 : 15;\ |
| } |
| union { UNSG32 u32FigoReg_figoCtrl; |
| struct w32FigoReg_figoCtrl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoID_ID(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoReg_figoID_ID(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoReg_figoID_ID(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoID_ID(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32FigoReg_figoID_REV(r32) _BFGET_(r32,31,16) |
| #define SET32FigoReg_figoID_REV(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16FigoReg_figoID_REV(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoID_REV(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoReg_figoID {\ |
| UNSG32 ufigoID_ID : 16;\ |
| UNSG32 ufigoID_REV : 16;\ |
| } |
| union { UNSG32 u32FigoReg_figoID; |
| struct w32FigoReg_figoID; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoMaxAdr_itcm(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoReg_figoMaxAdr_itcm(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoReg_figoMaxAdr_itcm(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoMaxAdr_itcm(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32FigoReg_figoMaxAdr_dtcm(r32) _BFGET_(r32,31,16) |
| #define SET32FigoReg_figoMaxAdr_dtcm(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16FigoReg_figoMaxAdr_dtcm(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoMaxAdr_dtcm(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoReg_figoMaxAdr {\ |
| UNSG32 ufigoMaxAdr_itcm : 16;\ |
| UNSG32 ufigoMaxAdr_dtcm : 16;\ |
| } |
| union { UNSG32 u32FigoReg_figoMaxAdr; |
| struct w32FigoReg_figoMaxAdr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoFlags_itcmAdrOOB(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoFlags_itcmAdrOOB(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoFlags_itcmAdrOOB(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoFlags_itcmAdrOOB(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32FigoReg_figoFlags_dtcmAdrOOB(r32) _BFGET_(r32, 1, 1) |
| #define SET32FigoReg_figoFlags_dtcmAdrOOB(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16FigoReg_figoFlags_dtcmAdrOOB(r16) _BFGET_(r16, 1, 1) |
| #define SET16FigoReg_figoFlags_dtcmAdrOOB(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32FigoReg_figoFlags_divideBy0(r32) _BFGET_(r32, 2, 2) |
| #define SET32FigoReg_figoFlags_divideBy0(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16FigoReg_figoFlags_divideBy0(r16) _BFGET_(r16, 2, 2) |
| #define SET16FigoReg_figoFlags_divideBy0(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32FigoReg_figoFlags_traceBufFull(r32) _BFGET_(r32, 3, 3) |
| #define SET32FigoReg_figoFlags_traceBufFull(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16FigoReg_figoFlags_traceBufFull(r16) _BFGET_(r16, 3, 3) |
| #define SET16FigoReg_figoFlags_traceBufFull(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32FigoReg_figoFlags_illegalIns(r32) _BFGET_(r32, 4, 4) |
| #define SET32FigoReg_figoFlags_illegalIns(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16FigoReg_figoFlags_illegalIns(r16) _BFGET_(r16, 4, 4) |
| #define SET16FigoReg_figoFlags_illegalIns(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32FigoReg_figoFlags_ALU64Overflow(r32) _BFGET_(r32, 5, 5) |
| #define SET32FigoReg_figoFlags_ALU64Overflow(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16FigoReg_figoFlags_ALU64Overflow(r16) _BFGET_(r16, 5, 5) |
| #define SET16FigoReg_figoFlags_ALU64Overflow(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32FigoReg_figoFlags_JTInvdPush(r32) _BFGET_(r32, 6, 6) |
| #define SET32FigoReg_figoFlags_JTInvdPush(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16FigoReg_figoFlags_JTInvdPush(r16) _BFGET_(r16, 6, 6) |
| #define SET16FigoReg_figoFlags_JTInvdPush(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define w32FigoReg_figoFlags {\ |
| UNSG32 ufigoFlags_itcmAdrOOB : 1;\ |
| UNSG32 ufigoFlags_dtcmAdrOOB : 1;\ |
| UNSG32 ufigoFlags_divideBy0 : 1;\ |
| UNSG32 ufigoFlags_traceBufFull : 1;\ |
| UNSG32 ufigoFlags_illegalIns : 1;\ |
| UNSG32 ufigoFlags_ALU64Overflow : 1;\ |
| UNSG32 ufigoFlags_JTInvdPush : 1;\ |
| UNSG32 RSVDxC_b7 : 25;\ |
| } |
| union { UNSG32 u32FigoReg_figoFlags; |
| struct w32FigoReg_figoFlags; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoFlagsMask_itcmAdrOOBMask(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoFlagsMask_itcmAdrOOBMask(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoFlagsMask_itcmAdrOOBMask(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoFlagsMask_itcmAdrOOBMask(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32FigoReg_figoFlagsMask_dtcmAdrOOBMask(r32) _BFGET_(r32, 1, 1) |
| #define SET32FigoReg_figoFlagsMask_dtcmAdrOOBMask(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16FigoReg_figoFlagsMask_dtcmAdrOOBMask(r16) _BFGET_(r16, 1, 1) |
| #define SET16FigoReg_figoFlagsMask_dtcmAdrOOBMask(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32FigoReg_figoFlagsMask_divideBy0Mask(r32) _BFGET_(r32, 2, 2) |
| #define SET32FigoReg_figoFlagsMask_divideBy0Mask(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16FigoReg_figoFlagsMask_divideBy0Mask(r16) _BFGET_(r16, 2, 2) |
| #define SET16FigoReg_figoFlagsMask_divideBy0Mask(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32FigoReg_figoFlagsMask_traceBufFullMask(r32) _BFGET_(r32, 3, 3) |
| #define SET32FigoReg_figoFlagsMask_traceBufFullMask(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16FigoReg_figoFlagsMask_traceBufFullMask(r16) _BFGET_(r16, 3, 3) |
| #define SET16FigoReg_figoFlagsMask_traceBufFullMask(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32FigoReg_figoFlagsMask_illegalInsMask(r32) _BFGET_(r32, 4, 4) |
| #define SET32FigoReg_figoFlagsMask_illegalInsMask(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16FigoReg_figoFlagsMask_illegalInsMask(r16) _BFGET_(r16, 4, 4) |
| #define SET16FigoReg_figoFlagsMask_illegalInsMask(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32FigoReg_figoFlagsMask_ALU64OverflowMask(r32) _BFGET_(r32, 5, 5) |
| #define SET32FigoReg_figoFlagsMask_ALU64OverflowMask(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16FigoReg_figoFlagsMask_ALU64OverflowMask(r16) _BFGET_(r16, 5, 5) |
| #define SET16FigoReg_figoFlagsMask_ALU64OverflowMask(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32FigoReg_figoFlagsMask_JTInvdPushMask(r32) _BFGET_(r32, 6, 6) |
| #define SET32FigoReg_figoFlagsMask_JTInvdPushMask(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16FigoReg_figoFlagsMask_JTInvdPushMask(r16) _BFGET_(r16, 6, 6) |
| #define SET16FigoReg_figoFlagsMask_JTInvdPushMask(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define w32FigoReg_figoFlagsMask {\ |
| UNSG32 ufigoFlagsMask_itcmAdrOOBMask : 1;\ |
| UNSG32 ufigoFlagsMask_dtcmAdrOOBMask : 1;\ |
| UNSG32 ufigoFlagsMask_divideBy0Mask : 1;\ |
| UNSG32 ufigoFlagsMask_traceBufFullMask : 1;\ |
| UNSG32 ufigoFlagsMask_illegalInsMask : 1;\ |
| UNSG32 ufigoFlagsMask_ALU64OverflowMask : 1;\ |
| UNSG32 ufigoFlagsMask_JTInvdPushMask : 1;\ |
| UNSG32 RSVDx10_b7 : 25;\ |
| } |
| union { UNSG32 u32FigoReg_figoFlagsMask; |
| struct w32FigoReg_figoFlagsMask; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoLastPC_val(r32) _BFGET_(r32,15, 0) |
| #define SET32FigoReg_figoLastPC_val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16FigoReg_figoLastPC_val(r16) _BFGET_(r16,15, 0) |
| #define SET16FigoReg_figoLastPC_val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32FigoReg_figoLastPC {\ |
| UNSG32 ufigoLastPC_val : 16;\ |
| UNSG32 RSVDx14_b16 : 16;\ |
| } |
| union { UNSG32 u32FigoReg_figoLastPC; |
| struct w32FigoReg_figoLastPC; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg16 ie_pc; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoTraceBuf ie_tbuf; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoIntr_up(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoIntr_up(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoIntr_up(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoIntr_up(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_figoIntr {\ |
| UNSG32 ufigoIntr_up : 1;\ |
| UNSG32 RSVDx20_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_figoIntr; |
| struct w32FigoReg_figoIntr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoIntrLvl_st(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoIntrLvl_st(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoIntrLvl_st(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoIntrLvl_st(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_figoIntrLvl {\ |
| UNSG32 ufigoIntrLvl_st : 1;\ |
| UNSG32 RSVDx24_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_figoIntrLvl; |
| struct w32FigoReg_figoIntrLvl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoRstn_up(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoRstn_up(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoRstn_up(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoRstn_up(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_figoRstn {\ |
| UNSG32 ufigoRstn_up : 1;\ |
| UNSG32 RSVDx28_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_figoRstn; |
| struct w32FigoReg_figoRstn; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoCnt_en(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoCnt_en(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoCnt_en(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoCnt_en(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_figoCnt {\ |
| UNSG32 ufigoCnt_en : 1;\ |
| UNSG32 RSVDx2C_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_figoCnt; |
| struct w32FigoReg_figoCnt; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoCntClr_run(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_figoCntClr_run(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_figoCntClr_run(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_figoCntClr_run(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32FigoReg_figoCntClr_stall(r32) _BFGET_(r32, 1, 1) |
| #define SET32FigoReg_figoCntClr_stall(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16FigoReg_figoCntClr_stall(r16) _BFGET_(r16, 1, 1) |
| #define SET16FigoReg_figoCntClr_stall(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32FigoReg_figoCntClr {\ |
| UNSG32 ufigoCntClr_run : 1;\ |
| UNSG32 ufigoCntClr_stall : 1;\ |
| UNSG32 RSVDx30_b2 : 30;\ |
| } |
| union { UNSG32 u32FigoReg_figoCntClr; |
| struct w32FigoReg_figoCntClr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoRun_Cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoReg_figoRun_Cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32FigoReg_figoRun {\ |
| UNSG32 ufigoRun_Cnt : 32;\ |
| } |
| union { UNSG32 u32FigoReg_figoRun; |
| struct w32FigoReg_figoRun; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_figoStall_Cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoReg_figoStall_Cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32FigoReg_figoStall {\ |
| UNSG32 ufigoStall_Cnt : 32;\ |
| } |
| union { UNSG32 u32FigoReg_figoStall; |
| struct w32FigoReg_figoStall; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx3C [1988]; |
| /////////////////////////////////////////////////////////// |
| SIE_ALU64 ie_alu64; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoDebug ie_debug; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_wdCnt_threshold(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoReg_wdCnt_threshold(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32FigoReg_wdCnt {\ |
| UNSG32 uwdCnt_threshold : 32;\ |
| } |
| union { UNSG32 u32FigoReg_wdCnt; |
| struct w32FigoReg_wdCnt; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_wdClr_en(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_wdClr_en(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_wdClr_en(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_wdClr_en(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_wdClr {\ |
| UNSG32 uwdClr_en : 1;\ |
| UNSG32 RSVDx18C4_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_wdClr; |
| struct w32FigoReg_wdClr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoReg_wdSt_overflow(r32) _BFGET_(r32, 0, 0) |
| #define SET32FigoReg_wdSt_overflow(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16FigoReg_wdSt_overflow(r16) _BFGET_(r16, 0, 0) |
| #define SET16FigoReg_wdSt_overflow(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32FigoReg_wdSt {\ |
| UNSG32 uwdSt_overflow : 1;\ |
| UNSG32 RSVDx18C8_b1 : 31;\ |
| } |
| union { UNSG32 u32FigoReg_wdSt; |
| struct w32FigoReg_wdSt; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx18CC [1844]; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoReg; |
| |
| typedef union T32FigoReg_figoCtrl |
| { UNSG32 u32; |
| struct w32FigoReg_figoCtrl; |
| } T32FigoReg_figoCtrl; |
| typedef union T32FigoReg_figoID |
| { UNSG32 u32; |
| struct w32FigoReg_figoID; |
| } T32FigoReg_figoID; |
| typedef union T32FigoReg_figoMaxAdr |
| { UNSG32 u32; |
| struct w32FigoReg_figoMaxAdr; |
| } T32FigoReg_figoMaxAdr; |
| typedef union T32FigoReg_figoFlags |
| { UNSG32 u32; |
| struct w32FigoReg_figoFlags; |
| } T32FigoReg_figoFlags; |
| typedef union T32FigoReg_figoFlagsMask |
| { UNSG32 u32; |
| struct w32FigoReg_figoFlagsMask; |
| } T32FigoReg_figoFlagsMask; |
| typedef union T32FigoReg_figoLastPC |
| { UNSG32 u32; |
| struct w32FigoReg_figoLastPC; |
| } T32FigoReg_figoLastPC; |
| typedef union T32FigoReg_figoIntr |
| { UNSG32 u32; |
| struct w32FigoReg_figoIntr; |
| } T32FigoReg_figoIntr; |
| typedef union T32FigoReg_figoIntrLvl |
| { UNSG32 u32; |
| struct w32FigoReg_figoIntrLvl; |
| } T32FigoReg_figoIntrLvl; |
| typedef union T32FigoReg_figoRstn |
| { UNSG32 u32; |
| struct w32FigoReg_figoRstn; |
| } T32FigoReg_figoRstn; |
| typedef union T32FigoReg_figoCnt |
| { UNSG32 u32; |
| struct w32FigoReg_figoCnt; |
| } T32FigoReg_figoCnt; |
| typedef union T32FigoReg_figoCntClr |
| { UNSG32 u32; |
| struct w32FigoReg_figoCntClr; |
| } T32FigoReg_figoCntClr; |
| typedef union T32FigoReg_figoRun |
| { UNSG32 u32; |
| struct w32FigoReg_figoRun; |
| } T32FigoReg_figoRun; |
| typedef union T32FigoReg_figoStall |
| { UNSG32 u32; |
| struct w32FigoReg_figoStall; |
| } T32FigoReg_figoStall; |
| typedef union T32FigoReg_wdCnt |
| { UNSG32 u32; |
| struct w32FigoReg_wdCnt; |
| } T32FigoReg_wdCnt; |
| typedef union T32FigoReg_wdClr |
| { UNSG32 u32; |
| struct w32FigoReg_wdClr; |
| } T32FigoReg_wdClr; |
| typedef union T32FigoReg_wdSt |
| { UNSG32 u32; |
| struct w32FigoReg_wdSt; |
| } T32FigoReg_wdSt; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TFigoReg_figoCtrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoCtrl; |
| }; |
| } TFigoReg_figoCtrl; |
| typedef union TFigoReg_figoID |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoID; |
| }; |
| } TFigoReg_figoID; |
| typedef union TFigoReg_figoMaxAdr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoMaxAdr; |
| }; |
| } TFigoReg_figoMaxAdr; |
| typedef union TFigoReg_figoFlags |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoFlags; |
| }; |
| } TFigoReg_figoFlags; |
| typedef union TFigoReg_figoFlagsMask |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoFlagsMask; |
| }; |
| } TFigoReg_figoFlagsMask; |
| typedef union TFigoReg_figoLastPC |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoLastPC; |
| }; |
| } TFigoReg_figoLastPC; |
| typedef union TFigoReg_figoIntr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoIntr; |
| }; |
| } TFigoReg_figoIntr; |
| typedef union TFigoReg_figoIntrLvl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoIntrLvl; |
| }; |
| } TFigoReg_figoIntrLvl; |
| typedef union TFigoReg_figoRstn |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoRstn; |
| }; |
| } TFigoReg_figoRstn; |
| typedef union TFigoReg_figoCnt |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoCnt; |
| }; |
| } TFigoReg_figoCnt; |
| typedef union TFigoReg_figoCntClr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoCntClr; |
| }; |
| } TFigoReg_figoCntClr; |
| typedef union TFigoReg_figoRun |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoRun; |
| }; |
| } TFigoReg_figoRun; |
| typedef union TFigoReg_figoStall |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_figoStall; |
| }; |
| } TFigoReg_figoStall; |
| typedef union TFigoReg_wdCnt |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_wdCnt; |
| }; |
| } TFigoReg_wdCnt; |
| typedef union TFigoReg_wdClr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_wdClr; |
| }; |
| } TFigoReg_wdClr; |
| typedef union TFigoReg_wdSt |
| { UNSG32 u32[1]; |
| struct { |
| struct w32FigoReg_wdSt; |
| }; |
| } TFigoReg_wdSt; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoReg_drvrd(SIE_FigoReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoReg_drvwr(SIE_FigoReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoReg_reset(SIE_FigoReg *p); |
| SIGN32 FigoReg_cmp (SIE_FigoReg *p, SIE_FigoReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoReg_check(p,pie,pfx,hLOG) FigoReg_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoReg_print(p, pfx,hLOG) FigoReg_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoReg |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoInst (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (RW) |
| /// ### |
| /// * Instruction opcode, 24-bit word |
| /// ### |
| /// %unsigned 24 opcode 0x0 |
| /// %% 8 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 24b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoInst |
| #define h_FigoInst (){} |
| |
| #define BA_FigoInst_opcode 0x0000 |
| #define B16FigoInst_opcode 0x0000 |
| #define LSb32FigoInst_opcode 0 |
| #define LSb16FigoInst_opcode 0 |
| #define bFigoInst_opcode 24 |
| #define MSK32FigoInst_opcode 0x00FFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoInst { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoInst_opcode(r32) _BFGET_(r32,23, 0) |
| #define SET32FigoInst_opcode(r32,v) _BFSET_(r32,23, 0,v) |
| |
| UNSG32 u_opcode : 24; |
| UNSG32 RSVDx0_b24 : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoInst; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoInst_drvrd(SIE_FigoInst *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoInst_drvwr(SIE_FigoInst *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoInst_reset(SIE_FigoInst *p); |
| SIGN32 FigoInst_cmp (SIE_FigoInst *p, SIE_FigoInst *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoInst_check(p,pie,pfx,hLOG) FigoInst_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoInst_print(p, pfx,hLOG) FigoInst_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoInst |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ITCM (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 figoItcm (P) |
| /// # 0x00000 inst |
| /// $FigoInst inst REG [2048] |
| /// ### |
| /// * Instruction memory, 8K word each maximum |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8192B, bits: 49152b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ITCM |
| #define h_ITCM (){} |
| |
| #define RA_ITCM_figoItcm 0x0000 |
| #define RA_ITCM_inst 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ITCM { |
| /////////////////////////////////////////////////////////// |
| SIE_FigoInst ie_inst[2048]; |
| /////////////////////////////////////////////////////////// |
| } SIE_ITCM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ITCM_drvrd(SIE_ITCM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ITCM_drvwr(SIE_ITCM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ITCM_reset(SIE_ITCM *p); |
| SIGN32 ITCM_cmp (SIE_ITCM *p, SIE_ITCM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ITCM_check(p,pie,pfx,hLOG) ITCM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ITCM_print(p, pfx,hLOG) ITCM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ITCM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoData (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (RW) |
| /// ### |
| /// * 32-bit data |
| /// ### |
| /// %unsigned 32 data_0i |
| /// %unsigned 32 data_1i |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoData |
| #define h_FigoData (){} |
| |
| #define BA_FigoData_data_0i 0x0000 |
| #define B16FigoData_data_0i 0x0000 |
| #define LSb32FigoData_data_0i 0 |
| #define LSb16FigoData_data_0i 0 |
| #define bFigoData_data_0i 32 |
| #define MSK32FigoData_data_0i 0xFFFFFFFF |
| |
| #define BA_FigoData_data_1i 0x0004 |
| #define B16FigoData_data_1i 0x0004 |
| #define LSb32FigoData_data_1i 0 |
| #define LSb16FigoData_data_1i 0 |
| #define bFigoData_data_1i 32 |
| #define MSK32FigoData_data_1i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoData { |
| /////////////////////////////////////////////////////////// |
| #define GET32FigoData_data_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoData_data_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32FigoData_data_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32FigoData_data_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_1i : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoData; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoData_drvrd(SIE_FigoData *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoData_drvwr(SIE_FigoData *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoData_reset(SIE_FigoData *p); |
| SIGN32 FigoData_cmp (SIE_FigoData *p, SIE_FigoData *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoData_check(p,pie,pfx,hLOG) FigoData_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoData_print(p, pfx,hLOG) FigoData_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoData |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoSys biu (4,4) |
| /// ### |
| /// * FigoSys registers |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 HBO0 (P) |
| /// # 0x00000 hbo0 |
| /// $HBO hbo0 REG |
| /// @ 0x00700 HBO1 (P) |
| /// # 0x00700 hbo1 |
| /// $HBO hbo1 REG |
| /// @ 0x00E00 (W-) |
| /// # # Stuffing bytes... |
| /// %% 4096 |
| /// @ 0x01000 FIGO0 (P) |
| /// # 0x01000 figo0 |
| /// $FigoReg figo0 REG |
| /// @ 0x03000 FIGO1 (P) |
| /// # 0x03000 figo1 |
| /// $FigoReg figo1 REG |
| /// @ 0x05000 DS (P) |
| /// # 0x05000 ds |
| /// $DataStreamer ds REG |
| /// @ 0x05024 (W-) |
| /// # # Stuffing bytes... |
| /// %% 16096 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 22528B, bits: 5086b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoSys |
| #define h_FigoSys (){} |
| |
| #define RA_FigoSys_HBO0 0x0000 |
| #define RA_FigoSys_hbo0 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSys_HBO1 0x0700 |
| #define RA_FigoSys_hbo1 0x0700 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSys_FIGO0 0x1000 |
| #define RA_FigoSys_figo0 0x1000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSys_FIGO1 0x3000 |
| #define RA_FigoSys_figo1 0x3000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSys_DS 0x5000 |
| #define RA_FigoSys_ds 0x5000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoSys { |
| /////////////////////////////////////////////////////////// |
| SIE_HBO ie_hbo0; |
| /////////////////////////////////////////////////////////// |
| SIE_HBO ie_hbo1; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxE00 [512]; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg ie_figo0; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg ie_figo1; |
| /////////////////////////////////////////////////////////// |
| SIE_DataStreamer ie_ds; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx5024 [2012]; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoSys; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoSys_drvrd(SIE_FigoSys *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoSys_drvwr(SIE_FigoSys *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoSys_reset(SIE_FigoSys *p); |
| SIGN32 FigoSys_cmp (SIE_FigoSys *p, SIE_FigoSys *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoSys_check(p,pie,pfx,hLOG) FigoSys_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoSys_print(p, pfx,hLOG) FigoSys_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoSys |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FigoSysBasic biu (4,4) |
| /// ### |
| /// * FigoSys registers |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 HBO0 (P) |
| /// # 0x00000 hbo0 |
| /// $HBO hbo0 REG |
| /// @ 0x00700 (W-) |
| /// # # Stuffing bytes... |
| /// %% 2048 |
| /// @ 0x00800 FIGO0 (P) |
| /// # 0x00800 figo0 |
| /// $FigoReg figo0 REG |
| /// @ 0x02800 DS (P) |
| /// # 0x02800 ds |
| /// $DataStreamer ds REG |
| /// @ 0x02824 (W-) |
| /// # # Stuffing bytes... |
| /// %% 16096 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 12288B, bits: 2609b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FigoSysBasic |
| #define h_FigoSysBasic (){} |
| |
| #define RA_FigoSysBasic_HBO0 0x0000 |
| #define RA_FigoSysBasic_hbo0 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSysBasic_FIGO0 0x0800 |
| #define RA_FigoSysBasic_figo0 0x0800 |
| /////////////////////////////////////////////////////////// |
| #define RA_FigoSysBasic_DS 0x2800 |
| #define RA_FigoSysBasic_ds 0x2800 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FigoSysBasic { |
| /////////////////////////////////////////////////////////// |
| SIE_HBO ie_hbo0; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx700 [256]; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg ie_figo0; |
| /////////////////////////////////////////////////////////// |
| SIE_DataStreamer ie_ds; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx2824 [2012]; |
| /////////////////////////////////////////////////////////// |
| } SIE_FigoSysBasic; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FigoSysBasic_drvrd(SIE_FigoSysBasic *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FigoSysBasic_drvwr(SIE_FigoSysBasic *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FigoSysBasic_reset(SIE_FigoSysBasic *p); |
| SIGN32 FigoSysBasic_cmp (SIE_FigoSysBasic *p, SIE_FigoSysBasic *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FigoSysBasic_check(p,pie,pfx,hLOG) FigoSysBasic_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FigoSysBasic_print(p, pfx,hLOG) FigoSysBasic_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FigoSysBasic |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQCmd (4,4) |
| /// ### |
| /// * QdeQ Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 Category |
| /// : Y16x16I 0x0 |
| /// ### |
| /// * Luma_16x16_Intra (H.264) mode |
| /// ### |
| /// : Y8x8I 0x1 |
| /// ### |
| /// * Luma_8x8_intra |
| /// ### |
| /// : Y4x4I 0x2 |
| /// ### |
| /// * Luma_4x4_intra |
| /// ### |
| /// : Y8x8P 0x3 |
| /// ### |
| /// * Luma_8x8_singlepredicted |
| /// ### |
| /// : Y4x4P 0x4 |
| /// ### |
| /// * Luma_4x4_singlepredicted |
| /// ### |
| /// : Y8x8B 0x5 |
| /// ### |
| /// * Luma_8x8_Bipredicted |
| /// ### |
| /// : Y4x4B 0x6 |
| /// ### |
| /// * Luma_4x4bipredicted |
| /// ### |
| /// : C8x8I 0x7 |
| /// ### |
| /// * Cb_8x8_Intra |
| /// ### |
| /// : C8x8PB 0x8 |
| /// ### |
| /// * Cb_8x8_inter (single and bi predicted) |
| /// ### |
| /// : C4x4I 0x9 |
| /// ### |
| /// * Cb_4x4_intra |
| /// ### |
| /// : C4x4PB 0xA |
| /// ### |
| /// * Cb_4x4_inter (single and bi predicted) |
| /// ### |
| /// : Reset 0x10 |
| /// ### |
| /// * QdeQ reset. Command not valid. Software should never issue command 0x10. |
| /// ### |
| /// : Coeff 0x11 |
| /// ### |
| /// * VLC statistics for coefficients and trailing ones |
| /// ### |
| /// : Stat 0x12 |
| /// ### |
| /// * No. of bits (Exp Golomb code ) and luma distortion SSD |
| /// ### |
| /// : CBP 0x13 |
| /// ### |
| /// * CBP, CBPDC, CBF, etc. |
| /// ### |
| /// %unsigned 4 DzEnable |
| /// ### |
| /// * One per 8x8 block |
| /// * DzEnable[1:0] – for luma and chroma (blk1 blk0) |
| /// * DzEnabke[3:2] – for luma only. (blk3 blk2) |
| /// ### |
| /// %% 23 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 9b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQCmd |
| #define h_QdeQCmd (){} |
| |
| #define BA_QdeQCmd_Category 0x0000 |
| #define B16QdeQCmd_Category 0x0000 |
| #define LSb32QdeQCmd_Category 0 |
| #define LSb16QdeQCmd_Category 0 |
| #define bQdeQCmd_Category 5 |
| #define MSK32QdeQCmd_Category 0x0000001F |
| #define QdeQCmd_Category_Y16x16I 0x0 |
| #define QdeQCmd_Category_Y8x8I 0x1 |
| #define QdeQCmd_Category_Y4x4I 0x2 |
| #define QdeQCmd_Category_Y8x8P 0x3 |
| #define QdeQCmd_Category_Y4x4P 0x4 |
| #define QdeQCmd_Category_Y8x8B 0x5 |
| #define QdeQCmd_Category_Y4x4B 0x6 |
| #define QdeQCmd_Category_C8x8I 0x7 |
| #define QdeQCmd_Category_C8x8PB 0x8 |
| #define QdeQCmd_Category_C4x4I 0x9 |
| #define QdeQCmd_Category_C4x4PB 0xA |
| #define QdeQCmd_Category_Reset 0x10 |
| #define QdeQCmd_Category_Coeff 0x11 |
| #define QdeQCmd_Category_Stat 0x12 |
| #define QdeQCmd_Category_CBP 0x13 |
| |
| #define BA_QdeQCmd_DzEnable 0x0000 |
| #define B16QdeQCmd_DzEnable 0x0000 |
| #define LSb32QdeQCmd_DzEnable 5 |
| #define LSb16QdeQCmd_DzEnable 5 |
| #define bQdeQCmd_DzEnable 4 |
| #define MSK32QdeQCmd_DzEnable 0x000001E0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQCmd { |
| /////////////////////////////////////////////////////////// |
| #define GET32QdeQCmd_Category(r32) _BFGET_(r32, 4, 0) |
| #define SET32QdeQCmd_Category(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16QdeQCmd_Category(r16) _BFGET_(r16, 4, 0) |
| #define SET16QdeQCmd_Category(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32QdeQCmd_DzEnable(r32) _BFGET_(r32, 8, 5) |
| #define SET32QdeQCmd_DzEnable(r32,v) _BFSET_(r32, 8, 5,v) |
| #define GET16QdeQCmd_DzEnable(r16) _BFGET_(r16, 8, 5) |
| #define SET16QdeQCmd_DzEnable(r16,v) _BFSET_(r16, 8, 5,v) |
| |
| UNSG32 u_Category : 5; |
| UNSG32 u_DzEnable : 4; |
| UNSG32 RSVDx0_b9 : 23; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQCmd; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQCmd_drvrd(SIE_QdeQCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQCmd_drvwr(SIE_QdeQCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQCmd_reset(SIE_QdeQCmd *p); |
| SIGN32 QdeQCmd_cmp (SIE_QdeQCmd *p, SIE_QdeQCmd *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQCmd_check(p,pie,pfx,hLOG) QdeQCmd_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQCmd_print(p, pfx,hLOG) QdeQCmd_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQCmd |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQMatrixEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 QuantEntry_0i |
| /// %unsigned 16 QuantEntry_1i |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQMatrixEntry |
| #define h_QdeQMatrixEntry (){} |
| |
| #define BA_QdeQMatrixEntry_QuantEntry_0i 0x0000 |
| #define B16QdeQMatrixEntry_QuantEntry_0i 0x0000 |
| #define LSb32QdeQMatrixEntry_QuantEntry_0i 0 |
| #define LSb16QdeQMatrixEntry_QuantEntry_0i 0 |
| #define bQdeQMatrixEntry_QuantEntry_0i 16 |
| #define MSK32QdeQMatrixEntry_QuantEntry_0i 0x0000FFFF |
| |
| #define BA_QdeQMatrixEntry_QuantEntry_1i 0x0002 |
| #define B16QdeQMatrixEntry_QuantEntry_1i 0x0002 |
| #define LSb32QdeQMatrixEntry_QuantEntry_1i 16 |
| #define LSb16QdeQMatrixEntry_QuantEntry_1i 0 |
| #define bQdeQMatrixEntry_QuantEntry_1i 16 |
| #define MSK32QdeQMatrixEntry_QuantEntry_1i 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQMatrixEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32QdeQMatrixEntry_QuantEntry_0i(r32) _BFGET_(r32,15, 0) |
| #define SET32QdeQMatrixEntry_QuantEntry_0i(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16QdeQMatrixEntry_QuantEntry_0i(r16) _BFGET_(r16,15, 0) |
| #define SET16QdeQMatrixEntry_QuantEntry_0i(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32QdeQMatrixEntry_QuantEntry_1i(r32) _BFGET_(r32,31,16) |
| #define SET32QdeQMatrixEntry_QuantEntry_1i(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16QdeQMatrixEntry_QuantEntry_1i(r16) _BFGET_(r16,15, 0) |
| #define SET16QdeQMatrixEntry_QuantEntry_1i(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_QuantEntry_0i : 16; |
| UNSG32 u_QuantEntry_1i : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQMatrixEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQMatrixEntry_drvrd(SIE_QdeQMatrixEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQMatrixEntry_drvwr(SIE_QdeQMatrixEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQMatrixEntry_reset(SIE_QdeQMatrixEntry *p); |
| SIGN32 QdeQMatrixEntry_cmp (SIE_QdeQMatrixEntry *p, SIE_QdeQMatrixEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQMatrixEntry_check(p,pie,pfx,hLOG) QdeQMatrixEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQMatrixEntry_print(p, pfx,hLOG) QdeQMatrixEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQMatrixEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QMatrix (4,4) |
| /// ### |
| /// * Quantization matrix, ordered based on frequency index |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $QdeQMatrixEntry Y8x8Intra MEM [32] |
| /// ### |
| /// * For H.264: Intra Y 8x8 block Q matrix |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 Y8x8Inter |
| /// $QdeQMatrixEntry Y8x8Inter MEM [32] |
| /// ### |
| /// * For H.264: Inter Y 8x8 block Q matrix |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 Y4x4Intra |
| /// $QdeQMatrixEntry Y4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: Intra Y 4x4 block Q matrix |
| /// ### |
| /// @ 0x00120 (P) |
| /// # 0x00120 U4x4Intra |
| /// $QdeQMatrixEntry U4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: Intra U 4x4 block Q matrix |
| /// ### |
| /// @ 0x00140 (P) |
| /// # 0x00140 V4x4Intra |
| /// $QdeQMatrixEntry V4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: Intra V 4x4 block Q matrix |
| /// ### |
| /// @ 0x00160 (P) |
| /// # 0x00160 Y4x4Inter |
| /// $QdeQMatrixEntry Y4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter Y 4x4 block Q matrix |
| /// ### |
| /// @ 0x00180 (P) |
| /// # 0x00180 U4x4Inter |
| /// $QdeQMatrixEntry U4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter U 4x4 block Q matrix |
| /// ### |
| /// @ 0x001A0 (P) |
| /// # 0x001A0 V4x4Inter |
| /// $QdeQMatrixEntry V4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter V 4x4 block Q matrix |
| /// ### |
| /// @ 0x001C0 (W-) |
| /// # # Stuffing bytes... |
| /// %% 512 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 256b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QMatrix |
| #define h_QMatrix (){} |
| |
| #define RA_QMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_Y8x8Inter 0x0080 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_Y4x4Intra 0x0100 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_U4x4Intra 0x0120 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_V4x4Intra 0x0140 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_Y4x4Inter 0x0160 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_U4x4Inter 0x0180 |
| /////////////////////////////////////////////////////////// |
| #define RA_QMatrix_V4x4Inter 0x01A0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y8x8Intra[32]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y8x8Inter[32]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_U4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_V4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_U4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_V4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx1C0 [64]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QMatrix_drvrd(SIE_QMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QMatrix_drvwr(SIE_QMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QMatrix_reset(SIE_QMatrix *p); |
| SIGN32 QMatrix_cmp (SIE_QMatrix *p, SIE_QMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QMatrix_check(p,pie,pfx,hLOG) QMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QMatrix_print(p, pfx,hLOG) QMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE deQMatrix (4,4) |
| /// ### |
| /// * Dequantized matrix; ordered based on frequency index |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $QdeQMatrixEntry Y8x8Intra MEM [32] |
| /// ### |
| /// * For H.264: Intra Y 8x8 block deQ matrix |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 Y8x8Inter |
| /// $QdeQMatrixEntry Y8x8Inter MEM [32] |
| /// ### |
| /// * For H.264: Inter Y 8x8 block deQ matrix |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 Y4x4Intra |
| /// $QdeQMatrixEntry Y4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: Intra Y 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00120 (P) |
| /// # 0x00120 U4x4Intra |
| /// $QdeQMatrixEntry U4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: Intra U 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00140 (P) |
| /// # 0x00140 V4x4Intra |
| /// $QdeQMatrixEntry V4x4Intra MEM [8] |
| /// ### |
| /// * For H.264: 4 Intra V 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00160 (P) |
| /// # 0x00160 Y4x4Inter |
| /// $QdeQMatrixEntry Y4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter Y 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00180 (P) |
| /// # 0x00180 U4x4Inter |
| /// $QdeQMatrixEntry U4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter U 4x4 block deQ matrix |
| /// ### |
| /// @ 0x001A0 (P) |
| /// # 0x001A0 V4x4Inter |
| /// $QdeQMatrixEntry V4x4Inter MEM [8] |
| /// ### |
| /// * For H.264: Inter V 4x4 block deQ matrix |
| /// ### |
| /// @ 0x001C0 (W-) |
| /// # # Stuffing bytes... |
| /// %% 512 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 256b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_deQMatrix |
| #define h_deQMatrix (){} |
| |
| #define RA_deQMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_Y8x8Inter 0x0080 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_Y4x4Intra 0x0100 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_U4x4Intra 0x0120 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_V4x4Intra 0x0140 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_Y4x4Inter 0x0160 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_U4x4Inter 0x0180 |
| /////////////////////////////////////////////////////////// |
| #define RA_deQMatrix_V4x4Inter 0x01A0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_deQMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y8x8Intra[32]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y8x8Inter[32]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_U4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_V4x4Intra[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_Y4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_U4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_V4x4Inter[8]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx1C0 [64]; |
| /////////////////////////////////////////////////////////// |
| } SIE_deQMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 deQMatrix_drvrd(SIE_deQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 deQMatrix_drvwr(SIE_deQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void deQMatrix_reset(SIE_deQMatrix *p); |
| SIGN32 deQMatrix_cmp (SIE_deQMatrix *p, SIE_deQMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define deQMatrix_check(p,pie,pfx,hLOG) deQMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define deQMatrix_print(p, pfx,hLOG) deQMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: deQMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RoundInfo flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 32 RoundErrorSum |
| /// ### |
| /// * The Sum of round error |
| /// ### |
| /// %unsigned 17 RoundErrorNum |
| /// ### |
| /// * The num of samples for round error |
| /// ### |
| /// %unsigned 8 RoundOffsetN8 |
| /// ### |
| /// * 8 bit Norm Round Offset for each position |
| /// ### |
| /// %% 7 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RoundInfo |
| #define h_RoundInfo (){} |
| |
| #define BA_RoundInfo_RoundErrorSum 0x0000 |
| #define B16RoundInfo_RoundErrorSum 0x0000 |
| #define LSb32RoundInfo_RoundErrorSum 0 |
| #define LSb16RoundInfo_RoundErrorSum 0 |
| #define bRoundInfo_RoundErrorSum 32 |
| #define MSK32RoundInfo_RoundErrorSum 0xFFFFFFFF |
| |
| #define BA_RoundInfo_RoundErrorNum 0x0004 |
| #define B16RoundInfo_RoundErrorNum 0x0004 |
| #define LSb32RoundInfo_RoundErrorNum 0 |
| #define LSb16RoundInfo_RoundErrorNum 0 |
| #define bRoundInfo_RoundErrorNum 17 |
| #define MSK32RoundInfo_RoundErrorNum 0x0001FFFF |
| |
| #define BA_RoundInfo_RoundOffsetN8 0x0006 |
| #define B16RoundInfo_RoundOffsetN8 0x0006 |
| #define LSb32RoundInfo_RoundOffsetN8 17 |
| #define LSb16RoundInfo_RoundOffsetN8 1 |
| #define bRoundInfo_RoundOffsetN8 8 |
| #define MSK32RoundInfo_RoundOffsetN8 0x01FE0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RoundInfo { |
| /////////////////////////////////////////////////////////// |
| #define GET32RoundInfo_RoundErrorSum(r32) _BFGET_(r32,31, 0) |
| #define SET32RoundInfo_RoundErrorSum(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 s_RoundErrorSum : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RoundInfo_RoundErrorNum(r32) _BFGET_(r32,16, 0) |
| #define SET32RoundInfo_RoundErrorNum(r32,v) _BFSET_(r32,16, 0,v) |
| |
| #define GET32RoundInfo_RoundOffsetN8(r32) _BFGET_(r32,24,17) |
| #define SET32RoundInfo_RoundOffsetN8(r32,v) _BFSET_(r32,24,17,v) |
| #define GET16RoundInfo_RoundOffsetN8(r16) _BFGET_(r16, 8, 1) |
| #define SET16RoundInfo_RoundOffsetN8(r16,v) _BFSET_(r16, 8, 1,v) |
| |
| UNSG32 u_RoundErrorNum : 17; |
| UNSG32 u_RoundOffsetN8 : 8; |
| UNSG32 RSVDx4_b25 : 7; |
| /////////////////////////////////////////////////////////// |
| } SIE_RoundInfo; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RoundInfo_drvrd(SIE_RoundInfo *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RoundInfo_drvwr(SIE_RoundInfo *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RoundInfo_reset(SIE_RoundInfo *p); |
| SIGN32 RoundInfo_cmp (SIE_RoundInfo *p, SIE_RoundInfo *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RoundInfo_check(p,pie,pfx,hLOG) RoundInfo_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RoundInfo_print(p, pfx,hLOG) RoundInfo_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RoundInfo |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RoundMatrix (4,4) |
| /// ### |
| /// * Rounding offset matrix; ordered based on the frequency index |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $RoundInfo Y8x8Intra MEM [64] |
| /// ### |
| /// * Luma16x16 Intra Round Info Matrix |
| /// ### |
| /// @ 0x00200 (P) |
| /// # 0x00200 Y8x8Inter |
| /// $RoundInfo Y8x8Inter MEM [64] |
| /// ### |
| /// * Luma4x4 Intra Round Info Matrix |
| /// ### |
| /// @ 0x00400 (P) |
| /// # 0x00400 Y8x8Bi |
| /// $RoundInfo Y8x8Bi MEM [64] |
| /// ### |
| /// * Luma4x4 single-pred Inter Round Info Matrix |
| /// ### |
| /// @ 0x00600 (P) |
| /// # 0x00600 Y16x16Intra |
| /// $RoundInfo Y16x16Intra MEM [16] |
| /// ### |
| /// * Luma16x16 Intra Round Info Matrix |
| /// * Y16x16Intra[0] is used for the luma DC block. |
| /// * Y16x16Intra[15:1] is used for each of the 15 AC coefficients |
| /// ### |
| /// @ 0x00680 (P) |
| /// # 0x00680 Y4x4Intra |
| /// $RoundInfo Y4x4Intra MEM [16] |
| /// ### |
| /// * Luma4x4 Intra Round Info Matrix |
| /// ### |
| /// @ 0x00700 (P) |
| /// # 0x00700 Y4x4Inter |
| /// $RoundInfo Y4x4Inter MEM [16] |
| /// ### |
| /// * Luma4x4 single-pred Inter Round Info Matrix |
| /// ### |
| /// @ 0x00780 (P) |
| /// # 0x00780 Y4x4Bi |
| /// $RoundInfo Y4x4Bi MEM [16] |
| /// ### |
| /// * Luma4x4 Bi-pred inter Round Info Matrix |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 2048B, bits: 224b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RoundMatrix |
| #define h_RoundMatrix (){} |
| |
| #define RA_RoundMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y8x8Inter 0x0200 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y8x8Bi 0x0400 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y16x16Intra 0x0600 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y4x4Intra 0x0680 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y4x4Inter 0x0700 |
| /////////////////////////////////////////////////////////// |
| #define RA_RoundMatrix_Y4x4Bi 0x0780 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RoundMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y8x8Intra[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y8x8Inter[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y8x8Bi[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y16x16Intra[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y4x4Intra[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y4x4Inter[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundInfo ie_Y4x4Bi[16]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RoundMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RoundMatrix_drvrd(SIE_RoundMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RoundMatrix_drvwr(SIE_RoundMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RoundMatrix_reset(SIE_RoundMatrix *p); |
| SIGN32 RoundMatrix_cmp (SIE_RoundMatrix *p, SIE_RoundMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RoundMatrix_check(p,pie,pfx,hLOG) RoundMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RoundMatrix_print(p, pfx,hLOG) RoundMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RoundMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ScaleInfo (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 14 Forward |
| /// ### |
| /// * Forward scaling factor |
| /// ### |
| /// %unsigned 14 Inverse |
| /// ### |
| /// * Inverse scaling factor |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 28b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ScaleInfo |
| #define h_ScaleInfo (){} |
| |
| #define BA_ScaleInfo_Forward 0x0000 |
| #define B16ScaleInfo_Forward 0x0000 |
| #define LSb32ScaleInfo_Forward 0 |
| #define LSb16ScaleInfo_Forward 0 |
| #define bScaleInfo_Forward 14 |
| #define MSK32ScaleInfo_Forward 0x00003FFF |
| |
| #define BA_ScaleInfo_Inverse 0x0001 |
| #define B16ScaleInfo_Inverse 0x0000 |
| #define LSb32ScaleInfo_Inverse 14 |
| #define LSb16ScaleInfo_Inverse 14 |
| #define bScaleInfo_Inverse 14 |
| #define MSK32ScaleInfo_Inverse 0x0FFFC000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ScaleInfo { |
| /////////////////////////////////////////////////////////// |
| #define GET32ScaleInfo_Forward(r32) _BFGET_(r32,13, 0) |
| #define SET32ScaleInfo_Forward(r32,v) _BFSET_(r32,13, 0,v) |
| #define GET16ScaleInfo_Forward(r16) _BFGET_(r16,13, 0) |
| #define SET16ScaleInfo_Forward(r16,v) _BFSET_(r16,13, 0,v) |
| |
| #define GET32ScaleInfo_Inverse(r32) _BFGET_(r32,27,14) |
| #define SET32ScaleInfo_Inverse(r32,v) _BFSET_(r32,27,14,v) |
| |
| UNSG32 u_Forward : 14; |
| UNSG32 u_Inverse : 14; |
| UNSG32 RSVDx0_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| } SIE_ScaleInfo; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ScaleInfo_drvrd(SIE_ScaleInfo *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ScaleInfo_drvwr(SIE_ScaleInfo *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ScaleInfo_reset(SIE_ScaleInfo *p); |
| SIGN32 ScaleInfo_cmp (SIE_ScaleInfo *p, SIE_ScaleInfo *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ScaleInfo_check(p,pie,pfx,hLOG) ScaleInfo_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ScaleInfo_print(p, pfx,hLOG) ScaleInfo_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ScaleInfo |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ScaleMatrix (4,4) |
| /// ### |
| /// * SSD Scaling matrix; ordered based on frequency index |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $ScaleInfo Y8x8Intra MEM [64] |
| /// ### |
| /// * Luma8x8 Intra scaling matrix for SSD |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 Y8x8Inter |
| /// $ScaleInfo Y8x8Inter MEM [64] |
| /// ### |
| /// * Luma8x8 Inter scaling matrix for SSD |
| /// ### |
| /// @ 0x00200 (P) |
| /// # 0x00200 Y4x4Intra |
| /// $ScaleInfo Y4x4Intra MEM [16] |
| /// ### |
| /// * Luma4x4 Intra scaling matrix for SSD |
| /// ### |
| /// @ 0x00240 (P) |
| /// # 0x00240 Y4x4Inter |
| /// $ScaleInfo Y4x4Inter MEM [16] |
| /// ### |
| /// * Luma4x4 Inter scaling matrix for SSD |
| /// ### |
| /// @ 0x00280 (W-) |
| /// # # Stuffing bytes... |
| /// %% 1024 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 768B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ScaleMatrix |
| #define h_ScaleMatrix (){} |
| |
| #define RA_ScaleMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_ScaleMatrix_Y8x8Inter 0x0100 |
| /////////////////////////////////////////////////////////// |
| #define RA_ScaleMatrix_Y4x4Intra 0x0200 |
| /////////////////////////////////////////////////////////// |
| #define RA_ScaleMatrix_Y4x4Inter 0x0240 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ScaleMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_ScaleInfo ie_Y8x8Intra[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_ScaleInfo ie_Y8x8Inter[64]; |
| /////////////////////////////////////////////////////////// |
| SIE_ScaleInfo ie_Y4x4Intra[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_ScaleInfo ie_Y4x4Inter[16]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx280 [128]; |
| /////////////////////////////////////////////////////////// |
| } SIE_ScaleMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ScaleMatrix_drvrd(SIE_ScaleMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ScaleMatrix_drvwr(SIE_ScaleMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ScaleMatrix_reset(SIE_ScaleMatrix *p); |
| SIGN32 ScaleMatrix_cmp (SIE_ScaleMatrix *p, SIE_ScaleMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ScaleMatrix_check(p,pie,pfx,hLOG) ScaleMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ScaleMatrix_print(p, pfx,hLOG) ScaleMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ScaleMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64QdeQ flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 Cost8x8 (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x00004 Cost8x81 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// # 0x00008 Cost8x82 |
| /// %unsigned 4 v_16i |
| /// %unsigned 4 v_17i |
| /// %unsigned 4 v_18i |
| /// %unsigned 4 v_19i |
| /// %unsigned 4 v_20i |
| /// %unsigned 4 v_21i |
| /// %unsigned 4 v_22i |
| /// %unsigned 4 v_23i |
| /// # 0x0000C Cost8x83 |
| /// %unsigned 4 v_24i |
| /// %unsigned 4 v_25i |
| /// %unsigned 4 v_26i |
| /// %unsigned 4 v_27i |
| /// %unsigned 4 v_28i |
| /// %unsigned 4 v_29i |
| /// %unsigned 4 v_30i |
| /// %unsigned 4 v_31i |
| /// # 0x00010 Cost8x84 |
| /// %unsigned 4 v_32i |
| /// %unsigned 4 v_33i |
| /// %unsigned 4 v_34i |
| /// %unsigned 4 v_35i |
| /// %unsigned 4 v_36i |
| /// %unsigned 4 v_37i |
| /// %unsigned 4 v_38i |
| /// %unsigned 4 v_39i |
| /// # 0x00014 Cost8x85 |
| /// %unsigned 4 v_40i |
| /// %unsigned 4 v_41i |
| /// %unsigned 4 v_42i |
| /// %unsigned 4 v_43i |
| /// %unsigned 4 v_44i |
| /// %unsigned 4 v_45i |
| /// %unsigned 4 v_46i |
| /// %unsigned 4 v_47i |
| /// # 0x00018 Cost8x86 |
| /// %unsigned 4 v_48i |
| /// %unsigned 4 v_49i |
| /// %unsigned 4 v_50i |
| /// %unsigned 4 v_51i |
| /// %unsigned 4 v_52i |
| /// %unsigned 4 v_53i |
| /// %unsigned 4 v_54i |
| /// %unsigned 4 v_55i |
| /// # 0x0001C Cost8x87 |
| /// %unsigned 4 v_56i |
| /// %unsigned 4 v_57i |
| /// %unsigned 4 v_58i |
| /// %unsigned 4 v_59i |
| /// %unsigned 4 v_60i |
| /// %unsigned 4 v_61i |
| /// %unsigned 4 v_62i |
| /// %unsigned 4 v_63i |
| /// ### |
| /// * 8x8 Cost Matrix , ordered in frequency index |
| /// ### |
| /// @ 0x00020 DZ8x8Intra (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x00024 DZ8x8Intra1 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// # 0x00028 DZ8x8Intra2 |
| /// %unsigned 4 v_16i |
| /// %unsigned 4 v_17i |
| /// %unsigned 4 v_18i |
| /// %unsigned 4 v_19i |
| /// %unsigned 4 v_20i |
| /// %unsigned 4 v_21i |
| /// %unsigned 4 v_22i |
| /// %unsigned 4 v_23i |
| /// # 0x0002C DZ8x8Intra3 |
| /// %unsigned 4 v_24i |
| /// %unsigned 4 v_25i |
| /// %unsigned 4 v_26i |
| /// %unsigned 4 v_27i |
| /// %unsigned 4 v_28i |
| /// %unsigned 4 v_29i |
| /// %unsigned 4 v_30i |
| /// %unsigned 4 v_31i |
| /// # 0x00030 DZ8x8Intra4 |
| /// %unsigned 4 v_32i |
| /// %unsigned 4 v_33i |
| /// %unsigned 4 v_34i |
| /// %unsigned 4 v_35i |
| /// %unsigned 4 v_36i |
| /// %unsigned 4 v_37i |
| /// %unsigned 4 v_38i |
| /// %unsigned 4 v_39i |
| /// # 0x00034 DZ8x8Intra5 |
| /// %unsigned 4 v_40i |
| /// %unsigned 4 v_41i |
| /// %unsigned 4 v_42i |
| /// %unsigned 4 v_43i |
| /// %unsigned 4 v_44i |
| /// %unsigned 4 v_45i |
| /// %unsigned 4 v_46i |
| /// %unsigned 4 v_47i |
| /// # 0x00038 DZ8x8Intra6 |
| /// %unsigned 4 v_48i |
| /// %unsigned 4 v_49i |
| /// %unsigned 4 v_50i |
| /// %unsigned 4 v_51i |
| /// %unsigned 4 v_52i |
| /// %unsigned 4 v_53i |
| /// %unsigned 4 v_54i |
| /// %unsigned 4 v_55i |
| /// # 0x0003C DZ8x8Intra7 |
| /// %unsigned 4 v_56i |
| /// %unsigned 4 v_57i |
| /// %unsigned 4 v_58i |
| /// %unsigned 4 v_59i |
| /// %unsigned 4 v_60i |
| /// %unsigned 4 v_61i |
| /// %unsigned 4 v_62i |
| /// %unsigned 4 v_63i |
| /// ### |
| /// * 8x8 Intra DeadZone map Matrix ordered in frequency index |
| /// ### |
| /// @ 0x00040 DZ8x8Inter (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x00044 DZ8x8Inter1 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// # 0x00048 DZ8x8Inter2 |
| /// %unsigned 4 v_16i |
| /// %unsigned 4 v_17i |
| /// %unsigned 4 v_18i |
| /// %unsigned 4 v_19i |
| /// %unsigned 4 v_20i |
| /// %unsigned 4 v_21i |
| /// %unsigned 4 v_22i |
| /// %unsigned 4 v_23i |
| /// # 0x0004C DZ8x8Inter3 |
| /// %unsigned 4 v_24i |
| /// %unsigned 4 v_25i |
| /// %unsigned 4 v_26i |
| /// %unsigned 4 v_27i |
| /// %unsigned 4 v_28i |
| /// %unsigned 4 v_29i |
| /// %unsigned 4 v_30i |
| /// %unsigned 4 v_31i |
| /// # 0x00050 DZ8x8Inter4 |
| /// %unsigned 4 v_32i |
| /// %unsigned 4 v_33i |
| /// %unsigned 4 v_34i |
| /// %unsigned 4 v_35i |
| /// %unsigned 4 v_36i |
| /// %unsigned 4 v_37i |
| /// %unsigned 4 v_38i |
| /// %unsigned 4 v_39i |
| /// # 0x00054 DZ8x8Inter5 |
| /// %unsigned 4 v_40i |
| /// %unsigned 4 v_41i |
| /// %unsigned 4 v_42i |
| /// %unsigned 4 v_43i |
| /// %unsigned 4 v_44i |
| /// %unsigned 4 v_45i |
| /// %unsigned 4 v_46i |
| /// %unsigned 4 v_47i |
| /// # 0x00058 DZ8x8Inter6 |
| /// %unsigned 4 v_48i |
| /// %unsigned 4 v_49i |
| /// %unsigned 4 v_50i |
| /// %unsigned 4 v_51i |
| /// %unsigned 4 v_52i |
| /// %unsigned 4 v_53i |
| /// %unsigned 4 v_54i |
| /// %unsigned 4 v_55i |
| /// # 0x0005C DZ8x8Inter7 |
| /// %unsigned 4 v_56i |
| /// %unsigned 4 v_57i |
| /// %unsigned 4 v_58i |
| /// %unsigned 4 v_59i |
| /// %unsigned 4 v_60i |
| /// %unsigned 4 v_61i |
| /// %unsigned 4 v_62i |
| /// %unsigned 4 v_63i |
| /// ### |
| /// * 8x8 Inter DeadZone map Matrix ordered in frequency index |
| /// ### |
| /// @ 0x00060 Cost4x4 (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x00064 Cost4x41 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// ### |
| /// * 4x4 Cost Matrix ordered in frequency index |
| /// ### |
| /// @ 0x00068 DZ4x4Intra (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x0006C DZ4x4Intra1 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// ### |
| /// * 4x4 Intra DeadZone map Matrix ordered in frequency index |
| /// ### |
| /// @ 0x00070 DZ4x4Inter (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x00074 DZ4x4Inter1 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// ### |
| /// * 4x4 Inter DeadZone map Matrix ordered in frequency index |
| /// ### |
| /// @ 0x00078 PostQThr (P) |
| /// %unsigned 4 TailYIntra8x8 |
| /// ### |
| /// * Luma Intra 8x8 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailUVIntra8x8 |
| /// ### |
| /// * Chroma Intra 8x8 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailYInter8x8 |
| /// ### |
| /// * Luma Inter 8x8 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailUVInter8x8 |
| /// ### |
| /// * Chroma Inter 8x8 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailYIntra4x4 |
| /// ### |
| /// * Luma Intra 4x4 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailUVIntra4x4 |
| /// ### |
| /// * Chroma Intra 4x4 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailYInter4x4 |
| /// ### |
| /// * Luma Inter 4x4 Tail Cut Threshold |
| /// ### |
| /// %unsigned 4 TailUVInter4x4 |
| /// ### |
| /// * Chroma Inter 4x4 Tail Cut Threshold |
| /// ### |
| /// # 0x0007C PostQThr1 |
| /// %unsigned 8 ZeroYInter8x8 |
| /// ### |
| /// * Luma inter 8x8 Zero Out Threshold |
| /// ### |
| /// %unsigned 8 ZeroUVInter8x8 |
| /// ### |
| /// * Chroma inter 8x8 Zero Out Threshold |
| /// ### |
| /// %unsigned 8 ZeroYInter4x4 |
| /// ### |
| /// * Luma inter 4x4 Zero Out Threshold |
| /// ### |
| /// %unsigned 8 ZeroUVInter4x4 |
| /// ### |
| /// * Chroma inter 4x4 Zero Out Threshold |
| /// ### |
| /// @ 0x00080 Scan8x8 (P) |
| /// %unsigned 8 v_0i |
| /// %unsigned 8 v_1i |
| /// %unsigned 8 v_2i |
| /// %unsigned 8 v_3i |
| /// # 0x00084 Scan8x81 |
| /// %unsigned 8 v_4i |
| /// %unsigned 8 v_5i |
| /// %unsigned 8 v_6i |
| /// %unsigned 8 v_7i |
| /// # 0x00088 Scan8x82 |
| /// %unsigned 8 v_8i |
| /// %unsigned 8 v_9i |
| /// %unsigned 8 v_10i |
| /// %unsigned 8 v_11i |
| /// # 0x0008C Scan8x83 |
| /// %unsigned 8 v_12i |
| /// %unsigned 8 v_13i |
| /// %unsigned 8 v_14i |
| /// %unsigned 8 v_15i |
| /// # 0x00090 Scan8x84 |
| /// %unsigned 8 v_16i |
| /// %unsigned 8 v_17i |
| /// %unsigned 8 v_18i |
| /// %unsigned 8 v_19i |
| /// # 0x00094 Scan8x85 |
| /// %unsigned 8 v_20i |
| /// %unsigned 8 v_21i |
| /// %unsigned 8 v_22i |
| /// %unsigned 8 v_23i |
| /// # 0x00098 Scan8x86 |
| /// %unsigned 8 v_24i |
| /// %unsigned 8 v_25i |
| /// %unsigned 8 v_26i |
| /// %unsigned 8 v_27i |
| /// # 0x0009C Scan8x87 |
| /// %unsigned 8 v_28i |
| /// %unsigned 8 v_29i |
| /// %unsigned 8 v_30i |
| /// %unsigned 8 v_31i |
| /// # 0x000A0 Scan8x88 |
| /// %unsigned 8 v_32i |
| /// %unsigned 8 v_33i |
| /// %unsigned 8 v_34i |
| /// %unsigned 8 v_35i |
| /// # 0x000A4 Scan8x89 |
| /// %unsigned 8 v_36i |
| /// %unsigned 8 v_37i |
| /// %unsigned 8 v_38i |
| /// %unsigned 8 v_39i |
| /// # 0x000A8 Scan8x810 |
| /// %unsigned 8 v_40i |
| /// %unsigned 8 v_41i |
| /// %unsigned 8 v_42i |
| /// %unsigned 8 v_43i |
| /// # 0x000AC Scan8x811 |
| /// %unsigned 8 v_44i |
| /// %unsigned 8 v_45i |
| /// %unsigned 8 v_46i |
| /// %unsigned 8 v_47i |
| /// # 0x000B0 Scan8x812 |
| /// %unsigned 8 v_48i |
| /// %unsigned 8 v_49i |
| /// %unsigned 8 v_50i |
| /// %unsigned 8 v_51i |
| /// # 0x000B4 Scan8x813 |
| /// %unsigned 8 v_52i |
| /// %unsigned 8 v_53i |
| /// %unsigned 8 v_54i |
| /// %unsigned 8 v_55i |
| /// # 0x000B8 Scan8x814 |
| /// %unsigned 8 v_56i |
| /// %unsigned 8 v_57i |
| /// %unsigned 8 v_58i |
| /// %unsigned 8 v_59i |
| /// # 0x000BC Scan8x815 |
| /// %unsigned 8 v_60i |
| /// %unsigned 8 v_61i |
| /// %unsigned 8 v_62i |
| /// %unsigned 8 v_63i |
| /// ### |
| /// * 8x8 transform Scan order matrix |
| /// ### |
| /// @ 0x000C0 Scan4x4 (P) |
| /// %unsigned 4 v_0i |
| /// %unsigned 4 v_1i |
| /// %unsigned 4 v_2i |
| /// %unsigned 4 v_3i |
| /// %unsigned 4 v_4i |
| /// %unsigned 4 v_5i |
| /// %unsigned 4 v_6i |
| /// %unsigned 4 v_7i |
| /// # 0x000C4 Scan4x41 |
| /// %unsigned 4 v_8i |
| /// %unsigned 4 v_9i |
| /// %unsigned 4 v_10i |
| /// %unsigned 4 v_11i |
| /// %unsigned 4 v_12i |
| /// %unsigned 4 v_13i |
| /// %unsigned 4 v_14i |
| /// %unsigned 4 v_15i |
| /// ### |
| /// * 4x4 transform Scan order matrix |
| /// ### |
| /// @ 0x000C8 Param1 (P) |
| /// %unsigned 8 IntraDC |
| /// ### |
| /// * Intra DC Chroma Quant Round Offset |
| /// ### |
| /// %unsigned 8 IntraAC |
| /// ### |
| /// * Intra AC Chroma Quant Round Offset |
| /// ### |
| /// %unsigned 8 InterDC |
| /// ### |
| /// * Inter DC Chroma Quant Round Offset. |
| /// * Only used in H264 mode for C4x4PB. |
| /// ### |
| /// %unsigned 8 InterAC |
| /// # 0x000CC Param11 |
| /// %unsigned 4 Type |
| /// : mpeg2 0x0 |
| /// : h263 0x1 |
| /// : mpeg3 0x2 |
| /// ### |
| /// * MPEG4 H.263 type quant |
| /// ### |
| /// : mpeg4 0x3 |
| /// : vc1ap 0x5 |
| /// : wmv 0x6 |
| /// : h264vlc 0x7 |
| /// : h264cabac 0x8 |
| /// %unsigned 4 EOB4x4 |
| /// %unsigned 8 QPY |
| /// %unsigned 8 QPU |
| /// %unsigned 8 QPV |
| /// @ 0x000D0 Param2 (P) |
| /// %signed 16 QDcLimitL |
| /// %signed 16 QDcLimitH |
| /// # 0x000D4 Param21 |
| /// %signed 16 QAcLimitL |
| /// %signed 16 QAcLimitH |
| /// @ 0x000D8 Param3 (P) |
| /// %unsigned 16 istepY |
| /// %unsigned 16 istepC |
| /// # 0x000DC Param31 |
| /// %unsigned 16 AC_dqofs |
| /// %unsigned 16 dQ_offset |
| /// @ 0x000E0 Param4 (P) |
| /// %unsigned 6 EOB8x8 |
| /// %unsigned 6 istepb |
| /// %unsigned 2 MismatchCtrl |
| /// : disable 0x0 |
| /// : mpeg1 0x1 |
| /// : mpeg2 0x2 |
| /// %% 18 # Stuffing bits... |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 232B, bits: 1856b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64QdeQ |
| #define h_RF64QdeQ (){} |
| |
| #define RA_RF64QdeQ_Cost8x8 0x0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_0i 0x0000 |
| #define B16RF64QdeQ_Cost8x8_v_0i 0x0000 |
| #define LSb32RF64QdeQ_Cost8x8_v_0i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_0i 0 |
| #define bRF64QdeQ_Cost8x8_v_0i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_1i 0x0000 |
| #define B16RF64QdeQ_Cost8x8_v_1i 0x0000 |
| #define LSb32RF64QdeQ_Cost8x8_v_1i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_1i 4 |
| #define bRF64QdeQ_Cost8x8_v_1i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_2i 0x0001 |
| #define B16RF64QdeQ_Cost8x8_v_2i 0x0000 |
| #define LSb32RF64QdeQ_Cost8x8_v_2i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_2i 8 |
| #define bRF64QdeQ_Cost8x8_v_2i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_3i 0x0001 |
| #define B16RF64QdeQ_Cost8x8_v_3i 0x0000 |
| #define LSb32RF64QdeQ_Cost8x8_v_3i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_3i 12 |
| #define bRF64QdeQ_Cost8x8_v_3i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_4i 0x0002 |
| #define B16RF64QdeQ_Cost8x8_v_4i 0x0002 |
| #define LSb32RF64QdeQ_Cost8x8_v_4i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_4i 0 |
| #define bRF64QdeQ_Cost8x8_v_4i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_5i 0x0002 |
| #define B16RF64QdeQ_Cost8x8_v_5i 0x0002 |
| #define LSb32RF64QdeQ_Cost8x8_v_5i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_5i 4 |
| #define bRF64QdeQ_Cost8x8_v_5i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_6i 0x0003 |
| #define B16RF64QdeQ_Cost8x8_v_6i 0x0002 |
| #define LSb32RF64QdeQ_Cost8x8_v_6i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_6i 8 |
| #define bRF64QdeQ_Cost8x8_v_6i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_7i 0x0003 |
| #define B16RF64QdeQ_Cost8x8_v_7i 0x0002 |
| #define LSb32RF64QdeQ_Cost8x8_v_7i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_7i 12 |
| #define bRF64QdeQ_Cost8x8_v_7i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x81 0x0004 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_8i 0x0004 |
| #define B16RF64QdeQ_Cost8x8_v_8i 0x0004 |
| #define LSb32RF64QdeQ_Cost8x8_v_8i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_8i 0 |
| #define bRF64QdeQ_Cost8x8_v_8i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_9i 0x0004 |
| #define B16RF64QdeQ_Cost8x8_v_9i 0x0004 |
| #define LSb32RF64QdeQ_Cost8x8_v_9i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_9i 4 |
| #define bRF64QdeQ_Cost8x8_v_9i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_10i 0x0005 |
| #define B16RF64QdeQ_Cost8x8_v_10i 0x0004 |
| #define LSb32RF64QdeQ_Cost8x8_v_10i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_10i 8 |
| #define bRF64QdeQ_Cost8x8_v_10i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_11i 0x0005 |
| #define B16RF64QdeQ_Cost8x8_v_11i 0x0004 |
| #define LSb32RF64QdeQ_Cost8x8_v_11i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_11i 12 |
| #define bRF64QdeQ_Cost8x8_v_11i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_12i 0x0006 |
| #define B16RF64QdeQ_Cost8x8_v_12i 0x0006 |
| #define LSb32RF64QdeQ_Cost8x8_v_12i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_12i 0 |
| #define bRF64QdeQ_Cost8x8_v_12i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_13i 0x0006 |
| #define B16RF64QdeQ_Cost8x8_v_13i 0x0006 |
| #define LSb32RF64QdeQ_Cost8x8_v_13i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_13i 4 |
| #define bRF64QdeQ_Cost8x8_v_13i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_14i 0x0007 |
| #define B16RF64QdeQ_Cost8x8_v_14i 0x0006 |
| #define LSb32RF64QdeQ_Cost8x8_v_14i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_14i 8 |
| #define bRF64QdeQ_Cost8x8_v_14i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_15i 0x0007 |
| #define B16RF64QdeQ_Cost8x8_v_15i 0x0006 |
| #define LSb32RF64QdeQ_Cost8x8_v_15i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_15i 12 |
| #define bRF64QdeQ_Cost8x8_v_15i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_15i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x82 0x0008 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_16i 0x0008 |
| #define B16RF64QdeQ_Cost8x8_v_16i 0x0008 |
| #define LSb32RF64QdeQ_Cost8x8_v_16i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_16i 0 |
| #define bRF64QdeQ_Cost8x8_v_16i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_16i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_17i 0x0008 |
| #define B16RF64QdeQ_Cost8x8_v_17i 0x0008 |
| #define LSb32RF64QdeQ_Cost8x8_v_17i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_17i 4 |
| #define bRF64QdeQ_Cost8x8_v_17i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_17i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_18i 0x0009 |
| #define B16RF64QdeQ_Cost8x8_v_18i 0x0008 |
| #define LSb32RF64QdeQ_Cost8x8_v_18i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_18i 8 |
| #define bRF64QdeQ_Cost8x8_v_18i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_18i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_19i 0x0009 |
| #define B16RF64QdeQ_Cost8x8_v_19i 0x0008 |
| #define LSb32RF64QdeQ_Cost8x8_v_19i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_19i 12 |
| #define bRF64QdeQ_Cost8x8_v_19i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_19i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_20i 0x000A |
| #define B16RF64QdeQ_Cost8x8_v_20i 0x000A |
| #define LSb32RF64QdeQ_Cost8x8_v_20i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_20i 0 |
| #define bRF64QdeQ_Cost8x8_v_20i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_20i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_21i 0x000A |
| #define B16RF64QdeQ_Cost8x8_v_21i 0x000A |
| #define LSb32RF64QdeQ_Cost8x8_v_21i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_21i 4 |
| #define bRF64QdeQ_Cost8x8_v_21i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_21i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_22i 0x000B |
| #define B16RF64QdeQ_Cost8x8_v_22i 0x000A |
| #define LSb32RF64QdeQ_Cost8x8_v_22i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_22i 8 |
| #define bRF64QdeQ_Cost8x8_v_22i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_22i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_23i 0x000B |
| #define B16RF64QdeQ_Cost8x8_v_23i 0x000A |
| #define LSb32RF64QdeQ_Cost8x8_v_23i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_23i 12 |
| #define bRF64QdeQ_Cost8x8_v_23i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_23i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x83 0x000C |
| |
| #define BA_RF64QdeQ_Cost8x8_v_24i 0x000C |
| #define B16RF64QdeQ_Cost8x8_v_24i 0x000C |
| #define LSb32RF64QdeQ_Cost8x8_v_24i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_24i 0 |
| #define bRF64QdeQ_Cost8x8_v_24i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_24i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_25i 0x000C |
| #define B16RF64QdeQ_Cost8x8_v_25i 0x000C |
| #define LSb32RF64QdeQ_Cost8x8_v_25i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_25i 4 |
| #define bRF64QdeQ_Cost8x8_v_25i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_25i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_26i 0x000D |
| #define B16RF64QdeQ_Cost8x8_v_26i 0x000C |
| #define LSb32RF64QdeQ_Cost8x8_v_26i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_26i 8 |
| #define bRF64QdeQ_Cost8x8_v_26i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_26i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_27i 0x000D |
| #define B16RF64QdeQ_Cost8x8_v_27i 0x000C |
| #define LSb32RF64QdeQ_Cost8x8_v_27i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_27i 12 |
| #define bRF64QdeQ_Cost8x8_v_27i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_27i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_28i 0x000E |
| #define B16RF64QdeQ_Cost8x8_v_28i 0x000E |
| #define LSb32RF64QdeQ_Cost8x8_v_28i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_28i 0 |
| #define bRF64QdeQ_Cost8x8_v_28i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_28i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_29i 0x000E |
| #define B16RF64QdeQ_Cost8x8_v_29i 0x000E |
| #define LSb32RF64QdeQ_Cost8x8_v_29i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_29i 4 |
| #define bRF64QdeQ_Cost8x8_v_29i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_29i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_30i 0x000F |
| #define B16RF64QdeQ_Cost8x8_v_30i 0x000E |
| #define LSb32RF64QdeQ_Cost8x8_v_30i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_30i 8 |
| #define bRF64QdeQ_Cost8x8_v_30i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_30i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_31i 0x000F |
| #define B16RF64QdeQ_Cost8x8_v_31i 0x000E |
| #define LSb32RF64QdeQ_Cost8x8_v_31i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_31i 12 |
| #define bRF64QdeQ_Cost8x8_v_31i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_31i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x84 0x0010 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_32i 0x0010 |
| #define B16RF64QdeQ_Cost8x8_v_32i 0x0010 |
| #define LSb32RF64QdeQ_Cost8x8_v_32i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_32i 0 |
| #define bRF64QdeQ_Cost8x8_v_32i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_32i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_33i 0x0010 |
| #define B16RF64QdeQ_Cost8x8_v_33i 0x0010 |
| #define LSb32RF64QdeQ_Cost8x8_v_33i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_33i 4 |
| #define bRF64QdeQ_Cost8x8_v_33i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_33i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_34i 0x0011 |
| #define B16RF64QdeQ_Cost8x8_v_34i 0x0010 |
| #define LSb32RF64QdeQ_Cost8x8_v_34i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_34i 8 |
| #define bRF64QdeQ_Cost8x8_v_34i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_34i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_35i 0x0011 |
| #define B16RF64QdeQ_Cost8x8_v_35i 0x0010 |
| #define LSb32RF64QdeQ_Cost8x8_v_35i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_35i 12 |
| #define bRF64QdeQ_Cost8x8_v_35i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_35i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_36i 0x0012 |
| #define B16RF64QdeQ_Cost8x8_v_36i 0x0012 |
| #define LSb32RF64QdeQ_Cost8x8_v_36i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_36i 0 |
| #define bRF64QdeQ_Cost8x8_v_36i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_36i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_37i 0x0012 |
| #define B16RF64QdeQ_Cost8x8_v_37i 0x0012 |
| #define LSb32RF64QdeQ_Cost8x8_v_37i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_37i 4 |
| #define bRF64QdeQ_Cost8x8_v_37i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_37i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_38i 0x0013 |
| #define B16RF64QdeQ_Cost8x8_v_38i 0x0012 |
| #define LSb32RF64QdeQ_Cost8x8_v_38i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_38i 8 |
| #define bRF64QdeQ_Cost8x8_v_38i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_38i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_39i 0x0013 |
| #define B16RF64QdeQ_Cost8x8_v_39i 0x0012 |
| #define LSb32RF64QdeQ_Cost8x8_v_39i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_39i 12 |
| #define bRF64QdeQ_Cost8x8_v_39i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_39i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x85 0x0014 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_40i 0x0014 |
| #define B16RF64QdeQ_Cost8x8_v_40i 0x0014 |
| #define LSb32RF64QdeQ_Cost8x8_v_40i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_40i 0 |
| #define bRF64QdeQ_Cost8x8_v_40i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_40i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_41i 0x0014 |
| #define B16RF64QdeQ_Cost8x8_v_41i 0x0014 |
| #define LSb32RF64QdeQ_Cost8x8_v_41i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_41i 4 |
| #define bRF64QdeQ_Cost8x8_v_41i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_41i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_42i 0x0015 |
| #define B16RF64QdeQ_Cost8x8_v_42i 0x0014 |
| #define LSb32RF64QdeQ_Cost8x8_v_42i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_42i 8 |
| #define bRF64QdeQ_Cost8x8_v_42i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_42i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_43i 0x0015 |
| #define B16RF64QdeQ_Cost8x8_v_43i 0x0014 |
| #define LSb32RF64QdeQ_Cost8x8_v_43i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_43i 12 |
| #define bRF64QdeQ_Cost8x8_v_43i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_43i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_44i 0x0016 |
| #define B16RF64QdeQ_Cost8x8_v_44i 0x0016 |
| #define LSb32RF64QdeQ_Cost8x8_v_44i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_44i 0 |
| #define bRF64QdeQ_Cost8x8_v_44i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_44i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_45i 0x0016 |
| #define B16RF64QdeQ_Cost8x8_v_45i 0x0016 |
| #define LSb32RF64QdeQ_Cost8x8_v_45i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_45i 4 |
| #define bRF64QdeQ_Cost8x8_v_45i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_45i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_46i 0x0017 |
| #define B16RF64QdeQ_Cost8x8_v_46i 0x0016 |
| #define LSb32RF64QdeQ_Cost8x8_v_46i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_46i 8 |
| #define bRF64QdeQ_Cost8x8_v_46i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_46i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_47i 0x0017 |
| #define B16RF64QdeQ_Cost8x8_v_47i 0x0016 |
| #define LSb32RF64QdeQ_Cost8x8_v_47i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_47i 12 |
| #define bRF64QdeQ_Cost8x8_v_47i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_47i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x86 0x0018 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_48i 0x0018 |
| #define B16RF64QdeQ_Cost8x8_v_48i 0x0018 |
| #define LSb32RF64QdeQ_Cost8x8_v_48i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_48i 0 |
| #define bRF64QdeQ_Cost8x8_v_48i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_48i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_49i 0x0018 |
| #define B16RF64QdeQ_Cost8x8_v_49i 0x0018 |
| #define LSb32RF64QdeQ_Cost8x8_v_49i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_49i 4 |
| #define bRF64QdeQ_Cost8x8_v_49i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_49i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_50i 0x0019 |
| #define B16RF64QdeQ_Cost8x8_v_50i 0x0018 |
| #define LSb32RF64QdeQ_Cost8x8_v_50i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_50i 8 |
| #define bRF64QdeQ_Cost8x8_v_50i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_50i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_51i 0x0019 |
| #define B16RF64QdeQ_Cost8x8_v_51i 0x0018 |
| #define LSb32RF64QdeQ_Cost8x8_v_51i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_51i 12 |
| #define bRF64QdeQ_Cost8x8_v_51i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_51i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_52i 0x001A |
| #define B16RF64QdeQ_Cost8x8_v_52i 0x001A |
| #define LSb32RF64QdeQ_Cost8x8_v_52i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_52i 0 |
| #define bRF64QdeQ_Cost8x8_v_52i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_52i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_53i 0x001A |
| #define B16RF64QdeQ_Cost8x8_v_53i 0x001A |
| #define LSb32RF64QdeQ_Cost8x8_v_53i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_53i 4 |
| #define bRF64QdeQ_Cost8x8_v_53i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_53i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_54i 0x001B |
| #define B16RF64QdeQ_Cost8x8_v_54i 0x001A |
| #define LSb32RF64QdeQ_Cost8x8_v_54i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_54i 8 |
| #define bRF64QdeQ_Cost8x8_v_54i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_54i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_55i 0x001B |
| #define B16RF64QdeQ_Cost8x8_v_55i 0x001A |
| #define LSb32RF64QdeQ_Cost8x8_v_55i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_55i 12 |
| #define bRF64QdeQ_Cost8x8_v_55i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_55i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost8x87 0x001C |
| |
| #define BA_RF64QdeQ_Cost8x8_v_56i 0x001C |
| #define B16RF64QdeQ_Cost8x8_v_56i 0x001C |
| #define LSb32RF64QdeQ_Cost8x8_v_56i 0 |
| #define LSb16RF64QdeQ_Cost8x8_v_56i 0 |
| #define bRF64QdeQ_Cost8x8_v_56i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_56i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost8x8_v_57i 0x001C |
| #define B16RF64QdeQ_Cost8x8_v_57i 0x001C |
| #define LSb32RF64QdeQ_Cost8x8_v_57i 4 |
| #define LSb16RF64QdeQ_Cost8x8_v_57i 4 |
| #define bRF64QdeQ_Cost8x8_v_57i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_57i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_58i 0x001D |
| #define B16RF64QdeQ_Cost8x8_v_58i 0x001C |
| #define LSb32RF64QdeQ_Cost8x8_v_58i 8 |
| #define LSb16RF64QdeQ_Cost8x8_v_58i 8 |
| #define bRF64QdeQ_Cost8x8_v_58i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_58i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_59i 0x001D |
| #define B16RF64QdeQ_Cost8x8_v_59i 0x001C |
| #define LSb32RF64QdeQ_Cost8x8_v_59i 12 |
| #define LSb16RF64QdeQ_Cost8x8_v_59i 12 |
| #define bRF64QdeQ_Cost8x8_v_59i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_59i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_60i 0x001E |
| #define B16RF64QdeQ_Cost8x8_v_60i 0x001E |
| #define LSb32RF64QdeQ_Cost8x8_v_60i 16 |
| #define LSb16RF64QdeQ_Cost8x8_v_60i 0 |
| #define bRF64QdeQ_Cost8x8_v_60i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_60i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_61i 0x001E |
| #define B16RF64QdeQ_Cost8x8_v_61i 0x001E |
| #define LSb32RF64QdeQ_Cost8x8_v_61i 20 |
| #define LSb16RF64QdeQ_Cost8x8_v_61i 4 |
| #define bRF64QdeQ_Cost8x8_v_61i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_61i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_62i 0x001F |
| #define B16RF64QdeQ_Cost8x8_v_62i 0x001E |
| #define LSb32RF64QdeQ_Cost8x8_v_62i 24 |
| #define LSb16RF64QdeQ_Cost8x8_v_62i 8 |
| #define bRF64QdeQ_Cost8x8_v_62i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_62i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost8x8_v_63i 0x001F |
| #define B16RF64QdeQ_Cost8x8_v_63i 0x001E |
| #define LSb32RF64QdeQ_Cost8x8_v_63i 28 |
| #define LSb16RF64QdeQ_Cost8x8_v_63i 12 |
| #define bRF64QdeQ_Cost8x8_v_63i 4 |
| #define MSK32RF64QdeQ_Cost8x8_v_63i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_DZ8x8Intra 0x0020 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_0i 0x0020 |
| #define B16RF64QdeQ_DZ8x8Intra_v_0i 0x0020 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_0i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_0i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_0i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_1i 0x0020 |
| #define B16RF64QdeQ_DZ8x8Intra_v_1i 0x0020 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_1i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_1i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_1i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_2i 0x0021 |
| #define B16RF64QdeQ_DZ8x8Intra_v_2i 0x0020 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_2i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_2i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_2i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_3i 0x0021 |
| #define B16RF64QdeQ_DZ8x8Intra_v_3i 0x0020 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_3i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_3i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_3i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_4i 0x0022 |
| #define B16RF64QdeQ_DZ8x8Intra_v_4i 0x0022 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_4i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_4i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_4i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_5i 0x0022 |
| #define B16RF64QdeQ_DZ8x8Intra_v_5i 0x0022 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_5i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_5i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_5i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_6i 0x0023 |
| #define B16RF64QdeQ_DZ8x8Intra_v_6i 0x0022 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_6i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_6i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_6i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_7i 0x0023 |
| #define B16RF64QdeQ_DZ8x8Intra_v_7i 0x0022 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_7i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_7i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_7i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra1 0x0024 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_8i 0x0024 |
| #define B16RF64QdeQ_DZ8x8Intra_v_8i 0x0024 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_8i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_8i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_8i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_9i 0x0024 |
| #define B16RF64QdeQ_DZ8x8Intra_v_9i 0x0024 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_9i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_9i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_9i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_10i 0x0025 |
| #define B16RF64QdeQ_DZ8x8Intra_v_10i 0x0024 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_10i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_10i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_10i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_11i 0x0025 |
| #define B16RF64QdeQ_DZ8x8Intra_v_11i 0x0024 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_11i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_11i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_11i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_12i 0x0026 |
| #define B16RF64QdeQ_DZ8x8Intra_v_12i 0x0026 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_12i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_12i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_12i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_13i 0x0026 |
| #define B16RF64QdeQ_DZ8x8Intra_v_13i 0x0026 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_13i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_13i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_13i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_14i 0x0027 |
| #define B16RF64QdeQ_DZ8x8Intra_v_14i 0x0026 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_14i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_14i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_14i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_15i 0x0027 |
| #define B16RF64QdeQ_DZ8x8Intra_v_15i 0x0026 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_15i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_15i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_15i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_15i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra2 0x0028 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_16i 0x0028 |
| #define B16RF64QdeQ_DZ8x8Intra_v_16i 0x0028 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_16i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_16i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_16i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_16i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_17i 0x0028 |
| #define B16RF64QdeQ_DZ8x8Intra_v_17i 0x0028 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_17i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_17i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_17i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_17i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_18i 0x0029 |
| #define B16RF64QdeQ_DZ8x8Intra_v_18i 0x0028 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_18i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_18i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_18i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_18i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_19i 0x0029 |
| #define B16RF64QdeQ_DZ8x8Intra_v_19i 0x0028 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_19i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_19i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_19i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_19i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_20i 0x002A |
| #define B16RF64QdeQ_DZ8x8Intra_v_20i 0x002A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_20i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_20i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_20i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_20i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_21i 0x002A |
| #define B16RF64QdeQ_DZ8x8Intra_v_21i 0x002A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_21i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_21i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_21i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_21i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_22i 0x002B |
| #define B16RF64QdeQ_DZ8x8Intra_v_22i 0x002A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_22i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_22i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_22i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_22i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_23i 0x002B |
| #define B16RF64QdeQ_DZ8x8Intra_v_23i 0x002A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_23i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_23i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_23i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_23i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra3 0x002C |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_24i 0x002C |
| #define B16RF64QdeQ_DZ8x8Intra_v_24i 0x002C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_24i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_24i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_24i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_24i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_25i 0x002C |
| #define B16RF64QdeQ_DZ8x8Intra_v_25i 0x002C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_25i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_25i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_25i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_25i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_26i 0x002D |
| #define B16RF64QdeQ_DZ8x8Intra_v_26i 0x002C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_26i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_26i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_26i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_26i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_27i 0x002D |
| #define B16RF64QdeQ_DZ8x8Intra_v_27i 0x002C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_27i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_27i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_27i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_27i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_28i 0x002E |
| #define B16RF64QdeQ_DZ8x8Intra_v_28i 0x002E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_28i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_28i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_28i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_28i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_29i 0x002E |
| #define B16RF64QdeQ_DZ8x8Intra_v_29i 0x002E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_29i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_29i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_29i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_29i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_30i 0x002F |
| #define B16RF64QdeQ_DZ8x8Intra_v_30i 0x002E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_30i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_30i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_30i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_30i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_31i 0x002F |
| #define B16RF64QdeQ_DZ8x8Intra_v_31i 0x002E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_31i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_31i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_31i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_31i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra4 0x0030 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_32i 0x0030 |
| #define B16RF64QdeQ_DZ8x8Intra_v_32i 0x0030 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_32i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_32i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_32i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_32i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_33i 0x0030 |
| #define B16RF64QdeQ_DZ8x8Intra_v_33i 0x0030 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_33i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_33i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_33i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_33i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_34i 0x0031 |
| #define B16RF64QdeQ_DZ8x8Intra_v_34i 0x0030 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_34i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_34i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_34i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_34i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_35i 0x0031 |
| #define B16RF64QdeQ_DZ8x8Intra_v_35i 0x0030 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_35i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_35i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_35i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_35i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_36i 0x0032 |
| #define B16RF64QdeQ_DZ8x8Intra_v_36i 0x0032 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_36i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_36i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_36i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_36i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_37i 0x0032 |
| #define B16RF64QdeQ_DZ8x8Intra_v_37i 0x0032 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_37i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_37i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_37i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_37i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_38i 0x0033 |
| #define B16RF64QdeQ_DZ8x8Intra_v_38i 0x0032 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_38i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_38i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_38i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_38i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_39i 0x0033 |
| #define B16RF64QdeQ_DZ8x8Intra_v_39i 0x0032 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_39i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_39i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_39i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_39i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra5 0x0034 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_40i 0x0034 |
| #define B16RF64QdeQ_DZ8x8Intra_v_40i 0x0034 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_40i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_40i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_40i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_40i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_41i 0x0034 |
| #define B16RF64QdeQ_DZ8x8Intra_v_41i 0x0034 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_41i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_41i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_41i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_41i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_42i 0x0035 |
| #define B16RF64QdeQ_DZ8x8Intra_v_42i 0x0034 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_42i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_42i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_42i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_42i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_43i 0x0035 |
| #define B16RF64QdeQ_DZ8x8Intra_v_43i 0x0034 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_43i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_43i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_43i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_43i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_44i 0x0036 |
| #define B16RF64QdeQ_DZ8x8Intra_v_44i 0x0036 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_44i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_44i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_44i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_44i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_45i 0x0036 |
| #define B16RF64QdeQ_DZ8x8Intra_v_45i 0x0036 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_45i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_45i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_45i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_45i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_46i 0x0037 |
| #define B16RF64QdeQ_DZ8x8Intra_v_46i 0x0036 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_46i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_46i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_46i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_46i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_47i 0x0037 |
| #define B16RF64QdeQ_DZ8x8Intra_v_47i 0x0036 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_47i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_47i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_47i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_47i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra6 0x0038 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_48i 0x0038 |
| #define B16RF64QdeQ_DZ8x8Intra_v_48i 0x0038 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_48i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_48i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_48i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_48i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_49i 0x0038 |
| #define B16RF64QdeQ_DZ8x8Intra_v_49i 0x0038 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_49i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_49i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_49i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_49i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_50i 0x0039 |
| #define B16RF64QdeQ_DZ8x8Intra_v_50i 0x0038 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_50i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_50i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_50i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_50i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_51i 0x0039 |
| #define B16RF64QdeQ_DZ8x8Intra_v_51i 0x0038 |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_51i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_51i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_51i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_51i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_52i 0x003A |
| #define B16RF64QdeQ_DZ8x8Intra_v_52i 0x003A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_52i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_52i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_52i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_52i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_53i 0x003A |
| #define B16RF64QdeQ_DZ8x8Intra_v_53i 0x003A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_53i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_53i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_53i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_53i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_54i 0x003B |
| #define B16RF64QdeQ_DZ8x8Intra_v_54i 0x003A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_54i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_54i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_54i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_54i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_55i 0x003B |
| #define B16RF64QdeQ_DZ8x8Intra_v_55i 0x003A |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_55i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_55i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_55i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_55i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Intra7 0x003C |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_56i 0x003C |
| #define B16RF64QdeQ_DZ8x8Intra_v_56i 0x003C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_56i 0 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_56i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_56i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_56i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_57i 0x003C |
| #define B16RF64QdeQ_DZ8x8Intra_v_57i 0x003C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_57i 4 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_57i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_57i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_57i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_58i 0x003D |
| #define B16RF64QdeQ_DZ8x8Intra_v_58i 0x003C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_58i 8 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_58i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_58i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_58i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_59i 0x003D |
| #define B16RF64QdeQ_DZ8x8Intra_v_59i 0x003C |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_59i 12 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_59i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_59i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_59i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_60i 0x003E |
| #define B16RF64QdeQ_DZ8x8Intra_v_60i 0x003E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_60i 16 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_60i 0 |
| #define bRF64QdeQ_DZ8x8Intra_v_60i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_60i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_61i 0x003E |
| #define B16RF64QdeQ_DZ8x8Intra_v_61i 0x003E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_61i 20 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_61i 4 |
| #define bRF64QdeQ_DZ8x8Intra_v_61i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_61i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_62i 0x003F |
| #define B16RF64QdeQ_DZ8x8Intra_v_62i 0x003E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_62i 24 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_62i 8 |
| #define bRF64QdeQ_DZ8x8Intra_v_62i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_62i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Intra_v_63i 0x003F |
| #define B16RF64QdeQ_DZ8x8Intra_v_63i 0x003E |
| #define LSb32RF64QdeQ_DZ8x8Intra_v_63i 28 |
| #define LSb16RF64QdeQ_DZ8x8Intra_v_63i 12 |
| #define bRF64QdeQ_DZ8x8Intra_v_63i 4 |
| #define MSK32RF64QdeQ_DZ8x8Intra_v_63i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_DZ8x8Inter 0x0040 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_0i 0x0040 |
| #define B16RF64QdeQ_DZ8x8Inter_v_0i 0x0040 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_0i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_0i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_0i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_1i 0x0040 |
| #define B16RF64QdeQ_DZ8x8Inter_v_1i 0x0040 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_1i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_1i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_1i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_2i 0x0041 |
| #define B16RF64QdeQ_DZ8x8Inter_v_2i 0x0040 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_2i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_2i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_2i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_3i 0x0041 |
| #define B16RF64QdeQ_DZ8x8Inter_v_3i 0x0040 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_3i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_3i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_3i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_4i 0x0042 |
| #define B16RF64QdeQ_DZ8x8Inter_v_4i 0x0042 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_4i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_4i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_4i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_5i 0x0042 |
| #define B16RF64QdeQ_DZ8x8Inter_v_5i 0x0042 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_5i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_5i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_5i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_6i 0x0043 |
| #define B16RF64QdeQ_DZ8x8Inter_v_6i 0x0042 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_6i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_6i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_6i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_7i 0x0043 |
| #define B16RF64QdeQ_DZ8x8Inter_v_7i 0x0042 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_7i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_7i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_7i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter1 0x0044 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_8i 0x0044 |
| #define B16RF64QdeQ_DZ8x8Inter_v_8i 0x0044 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_8i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_8i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_8i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_9i 0x0044 |
| #define B16RF64QdeQ_DZ8x8Inter_v_9i 0x0044 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_9i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_9i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_9i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_10i 0x0045 |
| #define B16RF64QdeQ_DZ8x8Inter_v_10i 0x0044 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_10i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_10i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_10i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_11i 0x0045 |
| #define B16RF64QdeQ_DZ8x8Inter_v_11i 0x0044 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_11i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_11i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_11i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_12i 0x0046 |
| #define B16RF64QdeQ_DZ8x8Inter_v_12i 0x0046 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_12i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_12i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_12i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_13i 0x0046 |
| #define B16RF64QdeQ_DZ8x8Inter_v_13i 0x0046 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_13i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_13i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_13i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_14i 0x0047 |
| #define B16RF64QdeQ_DZ8x8Inter_v_14i 0x0046 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_14i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_14i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_14i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_15i 0x0047 |
| #define B16RF64QdeQ_DZ8x8Inter_v_15i 0x0046 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_15i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_15i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_15i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_15i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter2 0x0048 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_16i 0x0048 |
| #define B16RF64QdeQ_DZ8x8Inter_v_16i 0x0048 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_16i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_16i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_16i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_16i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_17i 0x0048 |
| #define B16RF64QdeQ_DZ8x8Inter_v_17i 0x0048 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_17i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_17i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_17i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_17i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_18i 0x0049 |
| #define B16RF64QdeQ_DZ8x8Inter_v_18i 0x0048 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_18i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_18i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_18i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_18i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_19i 0x0049 |
| #define B16RF64QdeQ_DZ8x8Inter_v_19i 0x0048 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_19i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_19i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_19i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_19i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_20i 0x004A |
| #define B16RF64QdeQ_DZ8x8Inter_v_20i 0x004A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_20i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_20i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_20i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_20i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_21i 0x004A |
| #define B16RF64QdeQ_DZ8x8Inter_v_21i 0x004A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_21i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_21i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_21i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_21i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_22i 0x004B |
| #define B16RF64QdeQ_DZ8x8Inter_v_22i 0x004A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_22i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_22i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_22i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_22i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_23i 0x004B |
| #define B16RF64QdeQ_DZ8x8Inter_v_23i 0x004A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_23i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_23i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_23i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_23i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter3 0x004C |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_24i 0x004C |
| #define B16RF64QdeQ_DZ8x8Inter_v_24i 0x004C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_24i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_24i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_24i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_24i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_25i 0x004C |
| #define B16RF64QdeQ_DZ8x8Inter_v_25i 0x004C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_25i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_25i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_25i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_25i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_26i 0x004D |
| #define B16RF64QdeQ_DZ8x8Inter_v_26i 0x004C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_26i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_26i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_26i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_26i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_27i 0x004D |
| #define B16RF64QdeQ_DZ8x8Inter_v_27i 0x004C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_27i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_27i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_27i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_27i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_28i 0x004E |
| #define B16RF64QdeQ_DZ8x8Inter_v_28i 0x004E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_28i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_28i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_28i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_28i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_29i 0x004E |
| #define B16RF64QdeQ_DZ8x8Inter_v_29i 0x004E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_29i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_29i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_29i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_29i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_30i 0x004F |
| #define B16RF64QdeQ_DZ8x8Inter_v_30i 0x004E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_30i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_30i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_30i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_30i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_31i 0x004F |
| #define B16RF64QdeQ_DZ8x8Inter_v_31i 0x004E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_31i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_31i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_31i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_31i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter4 0x0050 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_32i 0x0050 |
| #define B16RF64QdeQ_DZ8x8Inter_v_32i 0x0050 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_32i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_32i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_32i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_32i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_33i 0x0050 |
| #define B16RF64QdeQ_DZ8x8Inter_v_33i 0x0050 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_33i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_33i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_33i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_33i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_34i 0x0051 |
| #define B16RF64QdeQ_DZ8x8Inter_v_34i 0x0050 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_34i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_34i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_34i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_34i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_35i 0x0051 |
| #define B16RF64QdeQ_DZ8x8Inter_v_35i 0x0050 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_35i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_35i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_35i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_35i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_36i 0x0052 |
| #define B16RF64QdeQ_DZ8x8Inter_v_36i 0x0052 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_36i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_36i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_36i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_36i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_37i 0x0052 |
| #define B16RF64QdeQ_DZ8x8Inter_v_37i 0x0052 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_37i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_37i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_37i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_37i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_38i 0x0053 |
| #define B16RF64QdeQ_DZ8x8Inter_v_38i 0x0052 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_38i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_38i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_38i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_38i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_39i 0x0053 |
| #define B16RF64QdeQ_DZ8x8Inter_v_39i 0x0052 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_39i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_39i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_39i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_39i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter5 0x0054 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_40i 0x0054 |
| #define B16RF64QdeQ_DZ8x8Inter_v_40i 0x0054 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_40i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_40i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_40i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_40i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_41i 0x0054 |
| #define B16RF64QdeQ_DZ8x8Inter_v_41i 0x0054 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_41i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_41i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_41i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_41i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_42i 0x0055 |
| #define B16RF64QdeQ_DZ8x8Inter_v_42i 0x0054 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_42i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_42i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_42i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_42i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_43i 0x0055 |
| #define B16RF64QdeQ_DZ8x8Inter_v_43i 0x0054 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_43i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_43i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_43i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_43i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_44i 0x0056 |
| #define B16RF64QdeQ_DZ8x8Inter_v_44i 0x0056 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_44i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_44i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_44i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_44i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_45i 0x0056 |
| #define B16RF64QdeQ_DZ8x8Inter_v_45i 0x0056 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_45i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_45i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_45i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_45i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_46i 0x0057 |
| #define B16RF64QdeQ_DZ8x8Inter_v_46i 0x0056 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_46i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_46i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_46i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_46i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_47i 0x0057 |
| #define B16RF64QdeQ_DZ8x8Inter_v_47i 0x0056 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_47i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_47i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_47i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_47i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter6 0x0058 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_48i 0x0058 |
| #define B16RF64QdeQ_DZ8x8Inter_v_48i 0x0058 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_48i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_48i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_48i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_48i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_49i 0x0058 |
| #define B16RF64QdeQ_DZ8x8Inter_v_49i 0x0058 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_49i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_49i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_49i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_49i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_50i 0x0059 |
| #define B16RF64QdeQ_DZ8x8Inter_v_50i 0x0058 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_50i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_50i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_50i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_50i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_51i 0x0059 |
| #define B16RF64QdeQ_DZ8x8Inter_v_51i 0x0058 |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_51i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_51i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_51i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_51i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_52i 0x005A |
| #define B16RF64QdeQ_DZ8x8Inter_v_52i 0x005A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_52i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_52i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_52i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_52i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_53i 0x005A |
| #define B16RF64QdeQ_DZ8x8Inter_v_53i 0x005A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_53i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_53i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_53i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_53i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_54i 0x005B |
| #define B16RF64QdeQ_DZ8x8Inter_v_54i 0x005A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_54i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_54i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_54i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_54i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_55i 0x005B |
| #define B16RF64QdeQ_DZ8x8Inter_v_55i 0x005A |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_55i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_55i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_55i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_55i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ8x8Inter7 0x005C |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_56i 0x005C |
| #define B16RF64QdeQ_DZ8x8Inter_v_56i 0x005C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_56i 0 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_56i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_56i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_56i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_57i 0x005C |
| #define B16RF64QdeQ_DZ8x8Inter_v_57i 0x005C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_57i 4 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_57i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_57i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_57i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_58i 0x005D |
| #define B16RF64QdeQ_DZ8x8Inter_v_58i 0x005C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_58i 8 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_58i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_58i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_58i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_59i 0x005D |
| #define B16RF64QdeQ_DZ8x8Inter_v_59i 0x005C |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_59i 12 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_59i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_59i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_59i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_60i 0x005E |
| #define B16RF64QdeQ_DZ8x8Inter_v_60i 0x005E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_60i 16 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_60i 0 |
| #define bRF64QdeQ_DZ8x8Inter_v_60i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_60i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_61i 0x005E |
| #define B16RF64QdeQ_DZ8x8Inter_v_61i 0x005E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_61i 20 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_61i 4 |
| #define bRF64QdeQ_DZ8x8Inter_v_61i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_61i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_62i 0x005F |
| #define B16RF64QdeQ_DZ8x8Inter_v_62i 0x005E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_62i 24 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_62i 8 |
| #define bRF64QdeQ_DZ8x8Inter_v_62i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_62i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ8x8Inter_v_63i 0x005F |
| #define B16RF64QdeQ_DZ8x8Inter_v_63i 0x005E |
| #define LSb32RF64QdeQ_DZ8x8Inter_v_63i 28 |
| #define LSb16RF64QdeQ_DZ8x8Inter_v_63i 12 |
| #define bRF64QdeQ_DZ8x8Inter_v_63i 4 |
| #define MSK32RF64QdeQ_DZ8x8Inter_v_63i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Cost4x4 0x0060 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_0i 0x0060 |
| #define B16RF64QdeQ_Cost4x4_v_0i 0x0060 |
| #define LSb32RF64QdeQ_Cost4x4_v_0i 0 |
| #define LSb16RF64QdeQ_Cost4x4_v_0i 0 |
| #define bRF64QdeQ_Cost4x4_v_0i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost4x4_v_1i 0x0060 |
| #define B16RF64QdeQ_Cost4x4_v_1i 0x0060 |
| #define LSb32RF64QdeQ_Cost4x4_v_1i 4 |
| #define LSb16RF64QdeQ_Cost4x4_v_1i 4 |
| #define bRF64QdeQ_Cost4x4_v_1i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_2i 0x0061 |
| #define B16RF64QdeQ_Cost4x4_v_2i 0x0060 |
| #define LSb32RF64QdeQ_Cost4x4_v_2i 8 |
| #define LSb16RF64QdeQ_Cost4x4_v_2i 8 |
| #define bRF64QdeQ_Cost4x4_v_2i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_3i 0x0061 |
| #define B16RF64QdeQ_Cost4x4_v_3i 0x0060 |
| #define LSb32RF64QdeQ_Cost4x4_v_3i 12 |
| #define LSb16RF64QdeQ_Cost4x4_v_3i 12 |
| #define bRF64QdeQ_Cost4x4_v_3i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_4i 0x0062 |
| #define B16RF64QdeQ_Cost4x4_v_4i 0x0062 |
| #define LSb32RF64QdeQ_Cost4x4_v_4i 16 |
| #define LSb16RF64QdeQ_Cost4x4_v_4i 0 |
| #define bRF64QdeQ_Cost4x4_v_4i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_5i 0x0062 |
| #define B16RF64QdeQ_Cost4x4_v_5i 0x0062 |
| #define LSb32RF64QdeQ_Cost4x4_v_5i 20 |
| #define LSb16RF64QdeQ_Cost4x4_v_5i 4 |
| #define bRF64QdeQ_Cost4x4_v_5i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_6i 0x0063 |
| #define B16RF64QdeQ_Cost4x4_v_6i 0x0062 |
| #define LSb32RF64QdeQ_Cost4x4_v_6i 24 |
| #define LSb16RF64QdeQ_Cost4x4_v_6i 8 |
| #define bRF64QdeQ_Cost4x4_v_6i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_7i 0x0063 |
| #define B16RF64QdeQ_Cost4x4_v_7i 0x0062 |
| #define LSb32RF64QdeQ_Cost4x4_v_7i 28 |
| #define LSb16RF64QdeQ_Cost4x4_v_7i 12 |
| #define bRF64QdeQ_Cost4x4_v_7i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Cost4x41 0x0064 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_8i 0x0064 |
| #define B16RF64QdeQ_Cost4x4_v_8i 0x0064 |
| #define LSb32RF64QdeQ_Cost4x4_v_8i 0 |
| #define LSb16RF64QdeQ_Cost4x4_v_8i 0 |
| #define bRF64QdeQ_Cost4x4_v_8i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_Cost4x4_v_9i 0x0064 |
| #define B16RF64QdeQ_Cost4x4_v_9i 0x0064 |
| #define LSb32RF64QdeQ_Cost4x4_v_9i 4 |
| #define LSb16RF64QdeQ_Cost4x4_v_9i 4 |
| #define bRF64QdeQ_Cost4x4_v_9i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_10i 0x0065 |
| #define B16RF64QdeQ_Cost4x4_v_10i 0x0064 |
| #define LSb32RF64QdeQ_Cost4x4_v_10i 8 |
| #define LSb16RF64QdeQ_Cost4x4_v_10i 8 |
| #define bRF64QdeQ_Cost4x4_v_10i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_11i 0x0065 |
| #define B16RF64QdeQ_Cost4x4_v_11i 0x0064 |
| #define LSb32RF64QdeQ_Cost4x4_v_11i 12 |
| #define LSb16RF64QdeQ_Cost4x4_v_11i 12 |
| #define bRF64QdeQ_Cost4x4_v_11i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_12i 0x0066 |
| #define B16RF64QdeQ_Cost4x4_v_12i 0x0066 |
| #define LSb32RF64QdeQ_Cost4x4_v_12i 16 |
| #define LSb16RF64QdeQ_Cost4x4_v_12i 0 |
| #define bRF64QdeQ_Cost4x4_v_12i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_13i 0x0066 |
| #define B16RF64QdeQ_Cost4x4_v_13i 0x0066 |
| #define LSb32RF64QdeQ_Cost4x4_v_13i 20 |
| #define LSb16RF64QdeQ_Cost4x4_v_13i 4 |
| #define bRF64QdeQ_Cost4x4_v_13i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_14i 0x0067 |
| #define B16RF64QdeQ_Cost4x4_v_14i 0x0066 |
| #define LSb32RF64QdeQ_Cost4x4_v_14i 24 |
| #define LSb16RF64QdeQ_Cost4x4_v_14i 8 |
| #define bRF64QdeQ_Cost4x4_v_14i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Cost4x4_v_15i 0x0067 |
| #define B16RF64QdeQ_Cost4x4_v_15i 0x0066 |
| #define LSb32RF64QdeQ_Cost4x4_v_15i 28 |
| #define LSb16RF64QdeQ_Cost4x4_v_15i 12 |
| #define bRF64QdeQ_Cost4x4_v_15i 4 |
| #define MSK32RF64QdeQ_Cost4x4_v_15i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_DZ4x4Intra 0x0068 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_0i 0x0068 |
| #define B16RF64QdeQ_DZ4x4Intra_v_0i 0x0068 |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_0i 0 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_0i 0 |
| #define bRF64QdeQ_DZ4x4Intra_v_0i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_1i 0x0068 |
| #define B16RF64QdeQ_DZ4x4Intra_v_1i 0x0068 |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_1i 4 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_1i 4 |
| #define bRF64QdeQ_DZ4x4Intra_v_1i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_2i 0x0069 |
| #define B16RF64QdeQ_DZ4x4Intra_v_2i 0x0068 |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_2i 8 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_2i 8 |
| #define bRF64QdeQ_DZ4x4Intra_v_2i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_3i 0x0069 |
| #define B16RF64QdeQ_DZ4x4Intra_v_3i 0x0068 |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_3i 12 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_3i 12 |
| #define bRF64QdeQ_DZ4x4Intra_v_3i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_4i 0x006A |
| #define B16RF64QdeQ_DZ4x4Intra_v_4i 0x006A |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_4i 16 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_4i 0 |
| #define bRF64QdeQ_DZ4x4Intra_v_4i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_5i 0x006A |
| #define B16RF64QdeQ_DZ4x4Intra_v_5i 0x006A |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_5i 20 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_5i 4 |
| #define bRF64QdeQ_DZ4x4Intra_v_5i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_6i 0x006B |
| #define B16RF64QdeQ_DZ4x4Intra_v_6i 0x006A |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_6i 24 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_6i 8 |
| #define bRF64QdeQ_DZ4x4Intra_v_6i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_7i 0x006B |
| #define B16RF64QdeQ_DZ4x4Intra_v_7i 0x006A |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_7i 28 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_7i 12 |
| #define bRF64QdeQ_DZ4x4Intra_v_7i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ4x4Intra1 0x006C |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_8i 0x006C |
| #define B16RF64QdeQ_DZ4x4Intra_v_8i 0x006C |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_8i 0 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_8i 0 |
| #define bRF64QdeQ_DZ4x4Intra_v_8i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_9i 0x006C |
| #define B16RF64QdeQ_DZ4x4Intra_v_9i 0x006C |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_9i 4 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_9i 4 |
| #define bRF64QdeQ_DZ4x4Intra_v_9i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_10i 0x006D |
| #define B16RF64QdeQ_DZ4x4Intra_v_10i 0x006C |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_10i 8 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_10i 8 |
| #define bRF64QdeQ_DZ4x4Intra_v_10i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_11i 0x006D |
| #define B16RF64QdeQ_DZ4x4Intra_v_11i 0x006C |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_11i 12 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_11i 12 |
| #define bRF64QdeQ_DZ4x4Intra_v_11i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_12i 0x006E |
| #define B16RF64QdeQ_DZ4x4Intra_v_12i 0x006E |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_12i 16 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_12i 0 |
| #define bRF64QdeQ_DZ4x4Intra_v_12i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_13i 0x006E |
| #define B16RF64QdeQ_DZ4x4Intra_v_13i 0x006E |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_13i 20 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_13i 4 |
| #define bRF64QdeQ_DZ4x4Intra_v_13i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_14i 0x006F |
| #define B16RF64QdeQ_DZ4x4Intra_v_14i 0x006E |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_14i 24 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_14i 8 |
| #define bRF64QdeQ_DZ4x4Intra_v_14i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ4x4Intra_v_15i 0x006F |
| #define B16RF64QdeQ_DZ4x4Intra_v_15i 0x006E |
| #define LSb32RF64QdeQ_DZ4x4Intra_v_15i 28 |
| #define LSb16RF64QdeQ_DZ4x4Intra_v_15i 12 |
| #define bRF64QdeQ_DZ4x4Intra_v_15i 4 |
| #define MSK32RF64QdeQ_DZ4x4Intra_v_15i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_DZ4x4Inter 0x0070 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_0i 0x0070 |
| #define B16RF64QdeQ_DZ4x4Inter_v_0i 0x0070 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_0i 0 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_0i 0 |
| #define bRF64QdeQ_DZ4x4Inter_v_0i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_1i 0x0070 |
| #define B16RF64QdeQ_DZ4x4Inter_v_1i 0x0070 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_1i 4 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_1i 4 |
| #define bRF64QdeQ_DZ4x4Inter_v_1i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_2i 0x0071 |
| #define B16RF64QdeQ_DZ4x4Inter_v_2i 0x0070 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_2i 8 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_2i 8 |
| #define bRF64QdeQ_DZ4x4Inter_v_2i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_3i 0x0071 |
| #define B16RF64QdeQ_DZ4x4Inter_v_3i 0x0070 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_3i 12 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_3i 12 |
| #define bRF64QdeQ_DZ4x4Inter_v_3i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_4i 0x0072 |
| #define B16RF64QdeQ_DZ4x4Inter_v_4i 0x0072 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_4i 16 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_4i 0 |
| #define bRF64QdeQ_DZ4x4Inter_v_4i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_5i 0x0072 |
| #define B16RF64QdeQ_DZ4x4Inter_v_5i 0x0072 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_5i 20 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_5i 4 |
| #define bRF64QdeQ_DZ4x4Inter_v_5i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_6i 0x0073 |
| #define B16RF64QdeQ_DZ4x4Inter_v_6i 0x0072 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_6i 24 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_6i 8 |
| #define bRF64QdeQ_DZ4x4Inter_v_6i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_7i 0x0073 |
| #define B16RF64QdeQ_DZ4x4Inter_v_7i 0x0072 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_7i 28 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_7i 12 |
| #define bRF64QdeQ_DZ4x4Inter_v_7i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_DZ4x4Inter1 0x0074 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_8i 0x0074 |
| #define B16RF64QdeQ_DZ4x4Inter_v_8i 0x0074 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_8i 0 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_8i 0 |
| #define bRF64QdeQ_DZ4x4Inter_v_8i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_9i 0x0074 |
| #define B16RF64QdeQ_DZ4x4Inter_v_9i 0x0074 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_9i 4 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_9i 4 |
| #define bRF64QdeQ_DZ4x4Inter_v_9i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_10i 0x0075 |
| #define B16RF64QdeQ_DZ4x4Inter_v_10i 0x0074 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_10i 8 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_10i 8 |
| #define bRF64QdeQ_DZ4x4Inter_v_10i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_11i 0x0075 |
| #define B16RF64QdeQ_DZ4x4Inter_v_11i 0x0074 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_11i 12 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_11i 12 |
| #define bRF64QdeQ_DZ4x4Inter_v_11i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_12i 0x0076 |
| #define B16RF64QdeQ_DZ4x4Inter_v_12i 0x0076 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_12i 16 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_12i 0 |
| #define bRF64QdeQ_DZ4x4Inter_v_12i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_13i 0x0076 |
| #define B16RF64QdeQ_DZ4x4Inter_v_13i 0x0076 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_13i 20 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_13i 4 |
| #define bRF64QdeQ_DZ4x4Inter_v_13i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_14i 0x0077 |
| #define B16RF64QdeQ_DZ4x4Inter_v_14i 0x0076 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_14i 24 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_14i 8 |
| #define bRF64QdeQ_DZ4x4Inter_v_14i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_DZ4x4Inter_v_15i 0x0077 |
| #define B16RF64QdeQ_DZ4x4Inter_v_15i 0x0076 |
| #define LSb32RF64QdeQ_DZ4x4Inter_v_15i 28 |
| #define LSb16RF64QdeQ_DZ4x4Inter_v_15i 12 |
| #define bRF64QdeQ_DZ4x4Inter_v_15i 4 |
| #define MSK32RF64QdeQ_DZ4x4Inter_v_15i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_PostQThr 0x0078 |
| |
| #define BA_RF64QdeQ_PostQThr_TailYIntra8x8 0x0078 |
| #define B16RF64QdeQ_PostQThr_TailYIntra8x8 0x0078 |
| #define LSb32RF64QdeQ_PostQThr_TailYIntra8x8 0 |
| #define LSb16RF64QdeQ_PostQThr_TailYIntra8x8 0 |
| #define bRF64QdeQ_PostQThr_TailYIntra8x8 4 |
| #define MSK32RF64QdeQ_PostQThr_TailYIntra8x8 0x0000000F |
| |
| #define BA_RF64QdeQ_PostQThr_TailUVIntra8x8 0x0078 |
| #define B16RF64QdeQ_PostQThr_TailUVIntra8x8 0x0078 |
| #define LSb32RF64QdeQ_PostQThr_TailUVIntra8x8 4 |
| #define LSb16RF64QdeQ_PostQThr_TailUVIntra8x8 4 |
| #define bRF64QdeQ_PostQThr_TailUVIntra8x8 4 |
| #define MSK32RF64QdeQ_PostQThr_TailUVIntra8x8 0x000000F0 |
| |
| #define BA_RF64QdeQ_PostQThr_TailYInter8x8 0x0079 |
| #define B16RF64QdeQ_PostQThr_TailYInter8x8 0x0078 |
| #define LSb32RF64QdeQ_PostQThr_TailYInter8x8 8 |
| #define LSb16RF64QdeQ_PostQThr_TailYInter8x8 8 |
| #define bRF64QdeQ_PostQThr_TailYInter8x8 4 |
| #define MSK32RF64QdeQ_PostQThr_TailYInter8x8 0x00000F00 |
| |
| #define BA_RF64QdeQ_PostQThr_TailUVInter8x8 0x0079 |
| #define B16RF64QdeQ_PostQThr_TailUVInter8x8 0x0078 |
| #define LSb32RF64QdeQ_PostQThr_TailUVInter8x8 12 |
| #define LSb16RF64QdeQ_PostQThr_TailUVInter8x8 12 |
| #define bRF64QdeQ_PostQThr_TailUVInter8x8 4 |
| #define MSK32RF64QdeQ_PostQThr_TailUVInter8x8 0x0000F000 |
| |
| #define BA_RF64QdeQ_PostQThr_TailYIntra4x4 0x007A |
| #define B16RF64QdeQ_PostQThr_TailYIntra4x4 0x007A |
| #define LSb32RF64QdeQ_PostQThr_TailYIntra4x4 16 |
| #define LSb16RF64QdeQ_PostQThr_TailYIntra4x4 0 |
| #define bRF64QdeQ_PostQThr_TailYIntra4x4 4 |
| #define MSK32RF64QdeQ_PostQThr_TailYIntra4x4 0x000F0000 |
| |
| #define BA_RF64QdeQ_PostQThr_TailUVIntra4x4 0x007A |
| #define B16RF64QdeQ_PostQThr_TailUVIntra4x4 0x007A |
| #define LSb32RF64QdeQ_PostQThr_TailUVIntra4x4 20 |
| #define LSb16RF64QdeQ_PostQThr_TailUVIntra4x4 4 |
| #define bRF64QdeQ_PostQThr_TailUVIntra4x4 4 |
| #define MSK32RF64QdeQ_PostQThr_TailUVIntra4x4 0x00F00000 |
| |
| #define BA_RF64QdeQ_PostQThr_TailYInter4x4 0x007B |
| #define B16RF64QdeQ_PostQThr_TailYInter4x4 0x007A |
| #define LSb32RF64QdeQ_PostQThr_TailYInter4x4 24 |
| #define LSb16RF64QdeQ_PostQThr_TailYInter4x4 8 |
| #define bRF64QdeQ_PostQThr_TailYInter4x4 4 |
| #define MSK32RF64QdeQ_PostQThr_TailYInter4x4 0x0F000000 |
| |
| #define BA_RF64QdeQ_PostQThr_TailUVInter4x4 0x007B |
| #define B16RF64QdeQ_PostQThr_TailUVInter4x4 0x007A |
| #define LSb32RF64QdeQ_PostQThr_TailUVInter4x4 28 |
| #define LSb16RF64QdeQ_PostQThr_TailUVInter4x4 12 |
| #define bRF64QdeQ_PostQThr_TailUVInter4x4 4 |
| #define MSK32RF64QdeQ_PostQThr_TailUVInter4x4 0xF0000000 |
| |
| #define RA_RF64QdeQ_PostQThr1 0x007C |
| |
| #define BA_RF64QdeQ_PostQThr_ZeroYInter8x8 0x007C |
| #define B16RF64QdeQ_PostQThr_ZeroYInter8x8 0x007C |
| #define LSb32RF64QdeQ_PostQThr_ZeroYInter8x8 0 |
| #define LSb16RF64QdeQ_PostQThr_ZeroYInter8x8 0 |
| #define bRF64QdeQ_PostQThr_ZeroYInter8x8 8 |
| #define MSK32RF64QdeQ_PostQThr_ZeroYInter8x8 0x000000FF |
| |
| #define BA_RF64QdeQ_PostQThr_ZeroUVInter8x8 0x007D |
| #define B16RF64QdeQ_PostQThr_ZeroUVInter8x8 0x007C |
| #define LSb32RF64QdeQ_PostQThr_ZeroUVInter8x8 8 |
| #define LSb16RF64QdeQ_PostQThr_ZeroUVInter8x8 8 |
| #define bRF64QdeQ_PostQThr_ZeroUVInter8x8 8 |
| #define MSK32RF64QdeQ_PostQThr_ZeroUVInter8x8 0x0000FF00 |
| |
| #define BA_RF64QdeQ_PostQThr_ZeroYInter4x4 0x007E |
| #define B16RF64QdeQ_PostQThr_ZeroYInter4x4 0x007E |
| #define LSb32RF64QdeQ_PostQThr_ZeroYInter4x4 16 |
| #define LSb16RF64QdeQ_PostQThr_ZeroYInter4x4 0 |
| #define bRF64QdeQ_PostQThr_ZeroYInter4x4 8 |
| #define MSK32RF64QdeQ_PostQThr_ZeroYInter4x4 0x00FF0000 |
| |
| #define BA_RF64QdeQ_PostQThr_ZeroUVInter4x4 0x007F |
| #define B16RF64QdeQ_PostQThr_ZeroUVInter4x4 0x007E |
| #define LSb32RF64QdeQ_PostQThr_ZeroUVInter4x4 24 |
| #define LSb16RF64QdeQ_PostQThr_ZeroUVInter4x4 8 |
| #define bRF64QdeQ_PostQThr_ZeroUVInter4x4 8 |
| #define MSK32RF64QdeQ_PostQThr_ZeroUVInter4x4 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Scan8x8 0x0080 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_0i 0x0080 |
| #define B16RF64QdeQ_Scan8x8_v_0i 0x0080 |
| #define LSb32RF64QdeQ_Scan8x8_v_0i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_0i 0 |
| #define bRF64QdeQ_Scan8x8_v_0i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_0i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_1i 0x0081 |
| #define B16RF64QdeQ_Scan8x8_v_1i 0x0080 |
| #define LSb32RF64QdeQ_Scan8x8_v_1i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_1i 8 |
| #define bRF64QdeQ_Scan8x8_v_1i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_1i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_2i 0x0082 |
| #define B16RF64QdeQ_Scan8x8_v_2i 0x0082 |
| #define LSb32RF64QdeQ_Scan8x8_v_2i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_2i 0 |
| #define bRF64QdeQ_Scan8x8_v_2i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_2i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_3i 0x0083 |
| #define B16RF64QdeQ_Scan8x8_v_3i 0x0082 |
| #define LSb32RF64QdeQ_Scan8x8_v_3i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_3i 8 |
| #define bRF64QdeQ_Scan8x8_v_3i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_3i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x81 0x0084 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_4i 0x0084 |
| #define B16RF64QdeQ_Scan8x8_v_4i 0x0084 |
| #define LSb32RF64QdeQ_Scan8x8_v_4i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_4i 0 |
| #define bRF64QdeQ_Scan8x8_v_4i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_4i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_5i 0x0085 |
| #define B16RF64QdeQ_Scan8x8_v_5i 0x0084 |
| #define LSb32RF64QdeQ_Scan8x8_v_5i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_5i 8 |
| #define bRF64QdeQ_Scan8x8_v_5i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_5i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_6i 0x0086 |
| #define B16RF64QdeQ_Scan8x8_v_6i 0x0086 |
| #define LSb32RF64QdeQ_Scan8x8_v_6i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_6i 0 |
| #define bRF64QdeQ_Scan8x8_v_6i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_6i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_7i 0x0087 |
| #define B16RF64QdeQ_Scan8x8_v_7i 0x0086 |
| #define LSb32RF64QdeQ_Scan8x8_v_7i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_7i 8 |
| #define bRF64QdeQ_Scan8x8_v_7i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_7i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x82 0x0088 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_8i 0x0088 |
| #define B16RF64QdeQ_Scan8x8_v_8i 0x0088 |
| #define LSb32RF64QdeQ_Scan8x8_v_8i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_8i 0 |
| #define bRF64QdeQ_Scan8x8_v_8i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_8i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_9i 0x0089 |
| #define B16RF64QdeQ_Scan8x8_v_9i 0x0088 |
| #define LSb32RF64QdeQ_Scan8x8_v_9i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_9i 8 |
| #define bRF64QdeQ_Scan8x8_v_9i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_9i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_10i 0x008A |
| #define B16RF64QdeQ_Scan8x8_v_10i 0x008A |
| #define LSb32RF64QdeQ_Scan8x8_v_10i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_10i 0 |
| #define bRF64QdeQ_Scan8x8_v_10i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_10i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_11i 0x008B |
| #define B16RF64QdeQ_Scan8x8_v_11i 0x008A |
| #define LSb32RF64QdeQ_Scan8x8_v_11i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_11i 8 |
| #define bRF64QdeQ_Scan8x8_v_11i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_11i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x83 0x008C |
| |
| #define BA_RF64QdeQ_Scan8x8_v_12i 0x008C |
| #define B16RF64QdeQ_Scan8x8_v_12i 0x008C |
| #define LSb32RF64QdeQ_Scan8x8_v_12i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_12i 0 |
| #define bRF64QdeQ_Scan8x8_v_12i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_12i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_13i 0x008D |
| #define B16RF64QdeQ_Scan8x8_v_13i 0x008C |
| #define LSb32RF64QdeQ_Scan8x8_v_13i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_13i 8 |
| #define bRF64QdeQ_Scan8x8_v_13i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_13i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_14i 0x008E |
| #define B16RF64QdeQ_Scan8x8_v_14i 0x008E |
| #define LSb32RF64QdeQ_Scan8x8_v_14i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_14i 0 |
| #define bRF64QdeQ_Scan8x8_v_14i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_14i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_15i 0x008F |
| #define B16RF64QdeQ_Scan8x8_v_15i 0x008E |
| #define LSb32RF64QdeQ_Scan8x8_v_15i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_15i 8 |
| #define bRF64QdeQ_Scan8x8_v_15i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_15i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x84 0x0090 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_16i 0x0090 |
| #define B16RF64QdeQ_Scan8x8_v_16i 0x0090 |
| #define LSb32RF64QdeQ_Scan8x8_v_16i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_16i 0 |
| #define bRF64QdeQ_Scan8x8_v_16i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_16i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_17i 0x0091 |
| #define B16RF64QdeQ_Scan8x8_v_17i 0x0090 |
| #define LSb32RF64QdeQ_Scan8x8_v_17i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_17i 8 |
| #define bRF64QdeQ_Scan8x8_v_17i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_17i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_18i 0x0092 |
| #define B16RF64QdeQ_Scan8x8_v_18i 0x0092 |
| #define LSb32RF64QdeQ_Scan8x8_v_18i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_18i 0 |
| #define bRF64QdeQ_Scan8x8_v_18i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_18i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_19i 0x0093 |
| #define B16RF64QdeQ_Scan8x8_v_19i 0x0092 |
| #define LSb32RF64QdeQ_Scan8x8_v_19i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_19i 8 |
| #define bRF64QdeQ_Scan8x8_v_19i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_19i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x85 0x0094 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_20i 0x0094 |
| #define B16RF64QdeQ_Scan8x8_v_20i 0x0094 |
| #define LSb32RF64QdeQ_Scan8x8_v_20i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_20i 0 |
| #define bRF64QdeQ_Scan8x8_v_20i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_20i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_21i 0x0095 |
| #define B16RF64QdeQ_Scan8x8_v_21i 0x0094 |
| #define LSb32RF64QdeQ_Scan8x8_v_21i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_21i 8 |
| #define bRF64QdeQ_Scan8x8_v_21i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_21i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_22i 0x0096 |
| #define B16RF64QdeQ_Scan8x8_v_22i 0x0096 |
| #define LSb32RF64QdeQ_Scan8x8_v_22i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_22i 0 |
| #define bRF64QdeQ_Scan8x8_v_22i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_22i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_23i 0x0097 |
| #define B16RF64QdeQ_Scan8x8_v_23i 0x0096 |
| #define LSb32RF64QdeQ_Scan8x8_v_23i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_23i 8 |
| #define bRF64QdeQ_Scan8x8_v_23i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_23i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x86 0x0098 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_24i 0x0098 |
| #define B16RF64QdeQ_Scan8x8_v_24i 0x0098 |
| #define LSb32RF64QdeQ_Scan8x8_v_24i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_24i 0 |
| #define bRF64QdeQ_Scan8x8_v_24i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_24i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_25i 0x0099 |
| #define B16RF64QdeQ_Scan8x8_v_25i 0x0098 |
| #define LSb32RF64QdeQ_Scan8x8_v_25i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_25i 8 |
| #define bRF64QdeQ_Scan8x8_v_25i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_25i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_26i 0x009A |
| #define B16RF64QdeQ_Scan8x8_v_26i 0x009A |
| #define LSb32RF64QdeQ_Scan8x8_v_26i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_26i 0 |
| #define bRF64QdeQ_Scan8x8_v_26i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_26i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_27i 0x009B |
| #define B16RF64QdeQ_Scan8x8_v_27i 0x009A |
| #define LSb32RF64QdeQ_Scan8x8_v_27i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_27i 8 |
| #define bRF64QdeQ_Scan8x8_v_27i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_27i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x87 0x009C |
| |
| #define BA_RF64QdeQ_Scan8x8_v_28i 0x009C |
| #define B16RF64QdeQ_Scan8x8_v_28i 0x009C |
| #define LSb32RF64QdeQ_Scan8x8_v_28i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_28i 0 |
| #define bRF64QdeQ_Scan8x8_v_28i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_28i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_29i 0x009D |
| #define B16RF64QdeQ_Scan8x8_v_29i 0x009C |
| #define LSb32RF64QdeQ_Scan8x8_v_29i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_29i 8 |
| #define bRF64QdeQ_Scan8x8_v_29i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_29i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_30i 0x009E |
| #define B16RF64QdeQ_Scan8x8_v_30i 0x009E |
| #define LSb32RF64QdeQ_Scan8x8_v_30i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_30i 0 |
| #define bRF64QdeQ_Scan8x8_v_30i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_30i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_31i 0x009F |
| #define B16RF64QdeQ_Scan8x8_v_31i 0x009E |
| #define LSb32RF64QdeQ_Scan8x8_v_31i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_31i 8 |
| #define bRF64QdeQ_Scan8x8_v_31i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_31i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x88 0x00A0 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_32i 0x00A0 |
| #define B16RF64QdeQ_Scan8x8_v_32i 0x00A0 |
| #define LSb32RF64QdeQ_Scan8x8_v_32i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_32i 0 |
| #define bRF64QdeQ_Scan8x8_v_32i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_32i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_33i 0x00A1 |
| #define B16RF64QdeQ_Scan8x8_v_33i 0x00A0 |
| #define LSb32RF64QdeQ_Scan8x8_v_33i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_33i 8 |
| #define bRF64QdeQ_Scan8x8_v_33i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_33i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_34i 0x00A2 |
| #define B16RF64QdeQ_Scan8x8_v_34i 0x00A2 |
| #define LSb32RF64QdeQ_Scan8x8_v_34i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_34i 0 |
| #define bRF64QdeQ_Scan8x8_v_34i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_34i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_35i 0x00A3 |
| #define B16RF64QdeQ_Scan8x8_v_35i 0x00A2 |
| #define LSb32RF64QdeQ_Scan8x8_v_35i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_35i 8 |
| #define bRF64QdeQ_Scan8x8_v_35i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_35i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x89 0x00A4 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_36i 0x00A4 |
| #define B16RF64QdeQ_Scan8x8_v_36i 0x00A4 |
| #define LSb32RF64QdeQ_Scan8x8_v_36i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_36i 0 |
| #define bRF64QdeQ_Scan8x8_v_36i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_36i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_37i 0x00A5 |
| #define B16RF64QdeQ_Scan8x8_v_37i 0x00A4 |
| #define LSb32RF64QdeQ_Scan8x8_v_37i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_37i 8 |
| #define bRF64QdeQ_Scan8x8_v_37i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_37i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_38i 0x00A6 |
| #define B16RF64QdeQ_Scan8x8_v_38i 0x00A6 |
| #define LSb32RF64QdeQ_Scan8x8_v_38i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_38i 0 |
| #define bRF64QdeQ_Scan8x8_v_38i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_38i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_39i 0x00A7 |
| #define B16RF64QdeQ_Scan8x8_v_39i 0x00A6 |
| #define LSb32RF64QdeQ_Scan8x8_v_39i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_39i 8 |
| #define bRF64QdeQ_Scan8x8_v_39i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_39i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x810 0x00A8 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_40i 0x00A8 |
| #define B16RF64QdeQ_Scan8x8_v_40i 0x00A8 |
| #define LSb32RF64QdeQ_Scan8x8_v_40i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_40i 0 |
| #define bRF64QdeQ_Scan8x8_v_40i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_40i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_41i 0x00A9 |
| #define B16RF64QdeQ_Scan8x8_v_41i 0x00A8 |
| #define LSb32RF64QdeQ_Scan8x8_v_41i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_41i 8 |
| #define bRF64QdeQ_Scan8x8_v_41i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_41i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_42i 0x00AA |
| #define B16RF64QdeQ_Scan8x8_v_42i 0x00AA |
| #define LSb32RF64QdeQ_Scan8x8_v_42i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_42i 0 |
| #define bRF64QdeQ_Scan8x8_v_42i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_42i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_43i 0x00AB |
| #define B16RF64QdeQ_Scan8x8_v_43i 0x00AA |
| #define LSb32RF64QdeQ_Scan8x8_v_43i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_43i 8 |
| #define bRF64QdeQ_Scan8x8_v_43i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_43i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x811 0x00AC |
| |
| #define BA_RF64QdeQ_Scan8x8_v_44i 0x00AC |
| #define B16RF64QdeQ_Scan8x8_v_44i 0x00AC |
| #define LSb32RF64QdeQ_Scan8x8_v_44i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_44i 0 |
| #define bRF64QdeQ_Scan8x8_v_44i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_44i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_45i 0x00AD |
| #define B16RF64QdeQ_Scan8x8_v_45i 0x00AC |
| #define LSb32RF64QdeQ_Scan8x8_v_45i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_45i 8 |
| #define bRF64QdeQ_Scan8x8_v_45i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_45i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_46i 0x00AE |
| #define B16RF64QdeQ_Scan8x8_v_46i 0x00AE |
| #define LSb32RF64QdeQ_Scan8x8_v_46i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_46i 0 |
| #define bRF64QdeQ_Scan8x8_v_46i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_46i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_47i 0x00AF |
| #define B16RF64QdeQ_Scan8x8_v_47i 0x00AE |
| #define LSb32RF64QdeQ_Scan8x8_v_47i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_47i 8 |
| #define bRF64QdeQ_Scan8x8_v_47i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_47i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x812 0x00B0 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_48i 0x00B0 |
| #define B16RF64QdeQ_Scan8x8_v_48i 0x00B0 |
| #define LSb32RF64QdeQ_Scan8x8_v_48i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_48i 0 |
| #define bRF64QdeQ_Scan8x8_v_48i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_48i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_49i 0x00B1 |
| #define B16RF64QdeQ_Scan8x8_v_49i 0x00B0 |
| #define LSb32RF64QdeQ_Scan8x8_v_49i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_49i 8 |
| #define bRF64QdeQ_Scan8x8_v_49i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_49i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_50i 0x00B2 |
| #define B16RF64QdeQ_Scan8x8_v_50i 0x00B2 |
| #define LSb32RF64QdeQ_Scan8x8_v_50i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_50i 0 |
| #define bRF64QdeQ_Scan8x8_v_50i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_50i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_51i 0x00B3 |
| #define B16RF64QdeQ_Scan8x8_v_51i 0x00B2 |
| #define LSb32RF64QdeQ_Scan8x8_v_51i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_51i 8 |
| #define bRF64QdeQ_Scan8x8_v_51i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_51i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x813 0x00B4 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_52i 0x00B4 |
| #define B16RF64QdeQ_Scan8x8_v_52i 0x00B4 |
| #define LSb32RF64QdeQ_Scan8x8_v_52i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_52i 0 |
| #define bRF64QdeQ_Scan8x8_v_52i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_52i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_53i 0x00B5 |
| #define B16RF64QdeQ_Scan8x8_v_53i 0x00B4 |
| #define LSb32RF64QdeQ_Scan8x8_v_53i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_53i 8 |
| #define bRF64QdeQ_Scan8x8_v_53i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_53i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_54i 0x00B6 |
| #define B16RF64QdeQ_Scan8x8_v_54i 0x00B6 |
| #define LSb32RF64QdeQ_Scan8x8_v_54i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_54i 0 |
| #define bRF64QdeQ_Scan8x8_v_54i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_54i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_55i 0x00B7 |
| #define B16RF64QdeQ_Scan8x8_v_55i 0x00B6 |
| #define LSb32RF64QdeQ_Scan8x8_v_55i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_55i 8 |
| #define bRF64QdeQ_Scan8x8_v_55i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_55i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x814 0x00B8 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_56i 0x00B8 |
| #define B16RF64QdeQ_Scan8x8_v_56i 0x00B8 |
| #define LSb32RF64QdeQ_Scan8x8_v_56i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_56i 0 |
| #define bRF64QdeQ_Scan8x8_v_56i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_56i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_57i 0x00B9 |
| #define B16RF64QdeQ_Scan8x8_v_57i 0x00B8 |
| #define LSb32RF64QdeQ_Scan8x8_v_57i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_57i 8 |
| #define bRF64QdeQ_Scan8x8_v_57i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_57i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_58i 0x00BA |
| #define B16RF64QdeQ_Scan8x8_v_58i 0x00BA |
| #define LSb32RF64QdeQ_Scan8x8_v_58i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_58i 0 |
| #define bRF64QdeQ_Scan8x8_v_58i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_58i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_59i 0x00BB |
| #define B16RF64QdeQ_Scan8x8_v_59i 0x00BA |
| #define LSb32RF64QdeQ_Scan8x8_v_59i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_59i 8 |
| #define bRF64QdeQ_Scan8x8_v_59i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_59i 0xFF000000 |
| |
| #define RA_RF64QdeQ_Scan8x815 0x00BC |
| |
| #define BA_RF64QdeQ_Scan8x8_v_60i 0x00BC |
| #define B16RF64QdeQ_Scan8x8_v_60i 0x00BC |
| #define LSb32RF64QdeQ_Scan8x8_v_60i 0 |
| #define LSb16RF64QdeQ_Scan8x8_v_60i 0 |
| #define bRF64QdeQ_Scan8x8_v_60i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_60i 0x000000FF |
| |
| #define BA_RF64QdeQ_Scan8x8_v_61i 0x00BD |
| #define B16RF64QdeQ_Scan8x8_v_61i 0x00BC |
| #define LSb32RF64QdeQ_Scan8x8_v_61i 8 |
| #define LSb16RF64QdeQ_Scan8x8_v_61i 8 |
| #define bRF64QdeQ_Scan8x8_v_61i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_61i 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_62i 0x00BE |
| #define B16RF64QdeQ_Scan8x8_v_62i 0x00BE |
| #define LSb32RF64QdeQ_Scan8x8_v_62i 16 |
| #define LSb16RF64QdeQ_Scan8x8_v_62i 0 |
| #define bRF64QdeQ_Scan8x8_v_62i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_62i 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Scan8x8_v_63i 0x00BF |
| #define B16RF64QdeQ_Scan8x8_v_63i 0x00BE |
| #define LSb32RF64QdeQ_Scan8x8_v_63i 24 |
| #define LSb16RF64QdeQ_Scan8x8_v_63i 8 |
| #define bRF64QdeQ_Scan8x8_v_63i 8 |
| #define MSK32RF64QdeQ_Scan8x8_v_63i 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Scan4x4 0x00C0 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_0i 0x00C0 |
| #define B16RF64QdeQ_Scan4x4_v_0i 0x00C0 |
| #define LSb32RF64QdeQ_Scan4x4_v_0i 0 |
| #define LSb16RF64QdeQ_Scan4x4_v_0i 0 |
| #define bRF64QdeQ_Scan4x4_v_0i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_0i 0x0000000F |
| |
| #define BA_RF64QdeQ_Scan4x4_v_1i 0x00C0 |
| #define B16RF64QdeQ_Scan4x4_v_1i 0x00C0 |
| #define LSb32RF64QdeQ_Scan4x4_v_1i 4 |
| #define LSb16RF64QdeQ_Scan4x4_v_1i 4 |
| #define bRF64QdeQ_Scan4x4_v_1i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_1i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_2i 0x00C1 |
| #define B16RF64QdeQ_Scan4x4_v_2i 0x00C0 |
| #define LSb32RF64QdeQ_Scan4x4_v_2i 8 |
| #define LSb16RF64QdeQ_Scan4x4_v_2i 8 |
| #define bRF64QdeQ_Scan4x4_v_2i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_2i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_3i 0x00C1 |
| #define B16RF64QdeQ_Scan4x4_v_3i 0x00C0 |
| #define LSb32RF64QdeQ_Scan4x4_v_3i 12 |
| #define LSb16RF64QdeQ_Scan4x4_v_3i 12 |
| #define bRF64QdeQ_Scan4x4_v_3i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_3i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_4i 0x00C2 |
| #define B16RF64QdeQ_Scan4x4_v_4i 0x00C2 |
| #define LSb32RF64QdeQ_Scan4x4_v_4i 16 |
| #define LSb16RF64QdeQ_Scan4x4_v_4i 0 |
| #define bRF64QdeQ_Scan4x4_v_4i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_4i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_5i 0x00C2 |
| #define B16RF64QdeQ_Scan4x4_v_5i 0x00C2 |
| #define LSb32RF64QdeQ_Scan4x4_v_5i 20 |
| #define LSb16RF64QdeQ_Scan4x4_v_5i 4 |
| #define bRF64QdeQ_Scan4x4_v_5i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_5i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_6i 0x00C3 |
| #define B16RF64QdeQ_Scan4x4_v_6i 0x00C2 |
| #define LSb32RF64QdeQ_Scan4x4_v_6i 24 |
| #define LSb16RF64QdeQ_Scan4x4_v_6i 8 |
| #define bRF64QdeQ_Scan4x4_v_6i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_6i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_7i 0x00C3 |
| #define B16RF64QdeQ_Scan4x4_v_7i 0x00C2 |
| #define LSb32RF64QdeQ_Scan4x4_v_7i 28 |
| #define LSb16RF64QdeQ_Scan4x4_v_7i 12 |
| #define bRF64QdeQ_Scan4x4_v_7i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_7i 0xF0000000 |
| |
| #define RA_RF64QdeQ_Scan4x41 0x00C4 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_8i 0x00C4 |
| #define B16RF64QdeQ_Scan4x4_v_8i 0x00C4 |
| #define LSb32RF64QdeQ_Scan4x4_v_8i 0 |
| #define LSb16RF64QdeQ_Scan4x4_v_8i 0 |
| #define bRF64QdeQ_Scan4x4_v_8i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_8i 0x0000000F |
| |
| #define BA_RF64QdeQ_Scan4x4_v_9i 0x00C4 |
| #define B16RF64QdeQ_Scan4x4_v_9i 0x00C4 |
| #define LSb32RF64QdeQ_Scan4x4_v_9i 4 |
| #define LSb16RF64QdeQ_Scan4x4_v_9i 4 |
| #define bRF64QdeQ_Scan4x4_v_9i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_9i 0x000000F0 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_10i 0x00C5 |
| #define B16RF64QdeQ_Scan4x4_v_10i 0x00C4 |
| #define LSb32RF64QdeQ_Scan4x4_v_10i 8 |
| #define LSb16RF64QdeQ_Scan4x4_v_10i 8 |
| #define bRF64QdeQ_Scan4x4_v_10i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_10i 0x00000F00 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_11i 0x00C5 |
| #define B16RF64QdeQ_Scan4x4_v_11i 0x00C4 |
| #define LSb32RF64QdeQ_Scan4x4_v_11i 12 |
| #define LSb16RF64QdeQ_Scan4x4_v_11i 12 |
| #define bRF64QdeQ_Scan4x4_v_11i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_11i 0x0000F000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_12i 0x00C6 |
| #define B16RF64QdeQ_Scan4x4_v_12i 0x00C6 |
| #define LSb32RF64QdeQ_Scan4x4_v_12i 16 |
| #define LSb16RF64QdeQ_Scan4x4_v_12i 0 |
| #define bRF64QdeQ_Scan4x4_v_12i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_12i 0x000F0000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_13i 0x00C6 |
| #define B16RF64QdeQ_Scan4x4_v_13i 0x00C6 |
| #define LSb32RF64QdeQ_Scan4x4_v_13i 20 |
| #define LSb16RF64QdeQ_Scan4x4_v_13i 4 |
| #define bRF64QdeQ_Scan4x4_v_13i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_13i 0x00F00000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_14i 0x00C7 |
| #define B16RF64QdeQ_Scan4x4_v_14i 0x00C6 |
| #define LSb32RF64QdeQ_Scan4x4_v_14i 24 |
| #define LSb16RF64QdeQ_Scan4x4_v_14i 8 |
| #define bRF64QdeQ_Scan4x4_v_14i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_14i 0x0F000000 |
| |
| #define BA_RF64QdeQ_Scan4x4_v_15i 0x00C7 |
| #define B16RF64QdeQ_Scan4x4_v_15i 0x00C6 |
| #define LSb32RF64QdeQ_Scan4x4_v_15i 28 |
| #define LSb16RF64QdeQ_Scan4x4_v_15i 12 |
| #define bRF64QdeQ_Scan4x4_v_15i 4 |
| #define MSK32RF64QdeQ_Scan4x4_v_15i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Param1 0x00C8 |
| |
| #define BA_RF64QdeQ_Param1_IntraDC 0x00C8 |
| #define B16RF64QdeQ_Param1_IntraDC 0x00C8 |
| #define LSb32RF64QdeQ_Param1_IntraDC 0 |
| #define LSb16RF64QdeQ_Param1_IntraDC 0 |
| #define bRF64QdeQ_Param1_IntraDC 8 |
| #define MSK32RF64QdeQ_Param1_IntraDC 0x000000FF |
| |
| #define BA_RF64QdeQ_Param1_IntraAC 0x00C9 |
| #define B16RF64QdeQ_Param1_IntraAC 0x00C8 |
| #define LSb32RF64QdeQ_Param1_IntraAC 8 |
| #define LSb16RF64QdeQ_Param1_IntraAC 8 |
| #define bRF64QdeQ_Param1_IntraAC 8 |
| #define MSK32RF64QdeQ_Param1_IntraAC 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Param1_InterDC 0x00CA |
| #define B16RF64QdeQ_Param1_InterDC 0x00CA |
| #define LSb32RF64QdeQ_Param1_InterDC 16 |
| #define LSb16RF64QdeQ_Param1_InterDC 0 |
| #define bRF64QdeQ_Param1_InterDC 8 |
| #define MSK32RF64QdeQ_Param1_InterDC 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Param1_InterAC 0x00CB |
| #define B16RF64QdeQ_Param1_InterAC 0x00CA |
| #define LSb32RF64QdeQ_Param1_InterAC 24 |
| #define LSb16RF64QdeQ_Param1_InterAC 8 |
| #define bRF64QdeQ_Param1_InterAC 8 |
| #define MSK32RF64QdeQ_Param1_InterAC 0xFF000000 |
| |
| #define RA_RF64QdeQ_Param11 0x00CC |
| |
| #define BA_RF64QdeQ_Param1_Type 0x00CC |
| #define B16RF64QdeQ_Param1_Type 0x00CC |
| #define LSb32RF64QdeQ_Param1_Type 0 |
| #define LSb16RF64QdeQ_Param1_Type 0 |
| #define bRF64QdeQ_Param1_Type 4 |
| #define MSK32RF64QdeQ_Param1_Type 0x0000000F |
| #define RF64QdeQ_Param1_Type_mpeg2 0x0 |
| #define RF64QdeQ_Param1_Type_h263 0x1 |
| #define RF64QdeQ_Param1_Type_mpeg3 0x2 |
| #define RF64QdeQ_Param1_Type_mpeg4 0x3 |
| #define RF64QdeQ_Param1_Type_vc1ap 0x5 |
| #define RF64QdeQ_Param1_Type_wmv 0x6 |
| #define RF64QdeQ_Param1_Type_h264vlc 0x7 |
| #define RF64QdeQ_Param1_Type_h264cabac 0x8 |
| |
| #define BA_RF64QdeQ_Param1_EOB4x4 0x00CC |
| #define B16RF64QdeQ_Param1_EOB4x4 0x00CC |
| #define LSb32RF64QdeQ_Param1_EOB4x4 4 |
| #define LSb16RF64QdeQ_Param1_EOB4x4 4 |
| #define bRF64QdeQ_Param1_EOB4x4 4 |
| #define MSK32RF64QdeQ_Param1_EOB4x4 0x000000F0 |
| |
| #define BA_RF64QdeQ_Param1_QPY 0x00CD |
| #define B16RF64QdeQ_Param1_QPY 0x00CC |
| #define LSb32RF64QdeQ_Param1_QPY 8 |
| #define LSb16RF64QdeQ_Param1_QPY 8 |
| #define bRF64QdeQ_Param1_QPY 8 |
| #define MSK32RF64QdeQ_Param1_QPY 0x0000FF00 |
| |
| #define BA_RF64QdeQ_Param1_QPU 0x00CE |
| #define B16RF64QdeQ_Param1_QPU 0x00CE |
| #define LSb32RF64QdeQ_Param1_QPU 16 |
| #define LSb16RF64QdeQ_Param1_QPU 0 |
| #define bRF64QdeQ_Param1_QPU 8 |
| #define MSK32RF64QdeQ_Param1_QPU 0x00FF0000 |
| |
| #define BA_RF64QdeQ_Param1_QPV 0x00CF |
| #define B16RF64QdeQ_Param1_QPV 0x00CE |
| #define LSb32RF64QdeQ_Param1_QPV 24 |
| #define LSb16RF64QdeQ_Param1_QPV 8 |
| #define bRF64QdeQ_Param1_QPV 8 |
| #define MSK32RF64QdeQ_Param1_QPV 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Param2 0x00D0 |
| |
| #define BA_RF64QdeQ_Param2_QDcLimitL 0x00D0 |
| #define B16RF64QdeQ_Param2_QDcLimitL 0x00D0 |
| #define LSb32RF64QdeQ_Param2_QDcLimitL 0 |
| #define LSb16RF64QdeQ_Param2_QDcLimitL 0 |
| #define bRF64QdeQ_Param2_QDcLimitL 16 |
| #define MSK32RF64QdeQ_Param2_QDcLimitL 0x0000FFFF |
| |
| #define BA_RF64QdeQ_Param2_QDcLimitH 0x00D2 |
| #define B16RF64QdeQ_Param2_QDcLimitH 0x00D2 |
| #define LSb32RF64QdeQ_Param2_QDcLimitH 16 |
| #define LSb16RF64QdeQ_Param2_QDcLimitH 0 |
| #define bRF64QdeQ_Param2_QDcLimitH 16 |
| #define MSK32RF64QdeQ_Param2_QDcLimitH 0xFFFF0000 |
| |
| #define RA_RF64QdeQ_Param21 0x00D4 |
| |
| #define BA_RF64QdeQ_Param2_QAcLimitL 0x00D4 |
| #define B16RF64QdeQ_Param2_QAcLimitL 0x00D4 |
| #define LSb32RF64QdeQ_Param2_QAcLimitL 0 |
| #define LSb16RF64QdeQ_Param2_QAcLimitL 0 |
| #define bRF64QdeQ_Param2_QAcLimitL 16 |
| #define MSK32RF64QdeQ_Param2_QAcLimitL 0x0000FFFF |
| |
| #define BA_RF64QdeQ_Param2_QAcLimitH 0x00D6 |
| #define B16RF64QdeQ_Param2_QAcLimitH 0x00D6 |
| #define LSb32RF64QdeQ_Param2_QAcLimitH 16 |
| #define LSb16RF64QdeQ_Param2_QAcLimitH 0 |
| #define bRF64QdeQ_Param2_QAcLimitH 16 |
| #define MSK32RF64QdeQ_Param2_QAcLimitH 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Param3 0x00D8 |
| |
| #define BA_RF64QdeQ_Param3_istepY 0x00D8 |
| #define B16RF64QdeQ_Param3_istepY 0x00D8 |
| #define LSb32RF64QdeQ_Param3_istepY 0 |
| #define LSb16RF64QdeQ_Param3_istepY 0 |
| #define bRF64QdeQ_Param3_istepY 16 |
| #define MSK32RF64QdeQ_Param3_istepY 0x0000FFFF |
| |
| #define BA_RF64QdeQ_Param3_istepC 0x00DA |
| #define B16RF64QdeQ_Param3_istepC 0x00DA |
| #define LSb32RF64QdeQ_Param3_istepC 16 |
| #define LSb16RF64QdeQ_Param3_istepC 0 |
| #define bRF64QdeQ_Param3_istepC 16 |
| #define MSK32RF64QdeQ_Param3_istepC 0xFFFF0000 |
| |
| #define RA_RF64QdeQ_Param31 0x00DC |
| |
| #define BA_RF64QdeQ_Param3_AC_dqofs 0x00DC |
| #define B16RF64QdeQ_Param3_AC_dqofs 0x00DC |
| #define LSb32RF64QdeQ_Param3_AC_dqofs 0 |
| #define LSb16RF64QdeQ_Param3_AC_dqofs 0 |
| #define bRF64QdeQ_Param3_AC_dqofs 16 |
| #define MSK32RF64QdeQ_Param3_AC_dqofs 0x0000FFFF |
| |
| #define BA_RF64QdeQ_Param3_dQ_offset 0x00DE |
| #define B16RF64QdeQ_Param3_dQ_offset 0x00DE |
| #define LSb32RF64QdeQ_Param3_dQ_offset 16 |
| #define LSb16RF64QdeQ_Param3_dQ_offset 0 |
| #define bRF64QdeQ_Param3_dQ_offset 16 |
| #define MSK32RF64QdeQ_Param3_dQ_offset 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64QdeQ_Param4 0x00E0 |
| |
| #define BA_RF64QdeQ_Param4_EOB8x8 0x00E0 |
| #define B16RF64QdeQ_Param4_EOB8x8 0x00E0 |
| #define LSb32RF64QdeQ_Param4_EOB8x8 0 |
| #define LSb16RF64QdeQ_Param4_EOB8x8 0 |
| #define bRF64QdeQ_Param4_EOB8x8 6 |
| #define MSK32RF64QdeQ_Param4_EOB8x8 0x0000003F |
| |
| #define BA_RF64QdeQ_Param4_istepb 0x00E0 |
| #define B16RF64QdeQ_Param4_istepb 0x00E0 |
| #define LSb32RF64QdeQ_Param4_istepb 6 |
| #define LSb16RF64QdeQ_Param4_istepb 6 |
| #define bRF64QdeQ_Param4_istepb 6 |
| #define MSK32RF64QdeQ_Param4_istepb 0x00000FC0 |
| |
| #define BA_RF64QdeQ_Param4_MismatchCtrl 0x00E1 |
| #define B16RF64QdeQ_Param4_MismatchCtrl 0x00E0 |
| #define LSb32RF64QdeQ_Param4_MismatchCtrl 12 |
| #define LSb16RF64QdeQ_Param4_MismatchCtrl 12 |
| #define bRF64QdeQ_Param4_MismatchCtrl 2 |
| #define MSK32RF64QdeQ_Param4_MismatchCtrl 0x00003000 |
| #define RF64QdeQ_Param4_MismatchCtrl_disable 0x0 |
| #define RF64QdeQ_Param4_MismatchCtrl_mpeg1 0x1 |
| #define RF64QdeQ_Param4_MismatchCtrl_mpeg2 0x2 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64QdeQ { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Cost8x8_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x8 {\ |
| UNSG32 uCost8x8_v_0i : 4;\ |
| UNSG32 uCost8x8_v_1i : 4;\ |
| UNSG32 uCost8x8_v_2i : 4;\ |
| UNSG32 uCost8x8_v_3i : 4;\ |
| UNSG32 uCost8x8_v_4i : 4;\ |
| UNSG32 uCost8x8_v_5i : 4;\ |
| UNSG32 uCost8x8_v_6i : 4;\ |
| UNSG32 uCost8x8_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x8; |
| struct w32RF64QdeQ_Cost8x8; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x81 {\ |
| UNSG32 uCost8x8_v_8i : 4;\ |
| UNSG32 uCost8x8_v_9i : 4;\ |
| UNSG32 uCost8x8_v_10i : 4;\ |
| UNSG32 uCost8x8_v_11i : 4;\ |
| UNSG32 uCost8x8_v_12i : 4;\ |
| UNSG32 uCost8x8_v_13i : 4;\ |
| UNSG32 uCost8x8_v_14i : 4;\ |
| UNSG32 uCost8x8_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x81; |
| struct w32RF64QdeQ_Cost8x81; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_16i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_16i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_16i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_16i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_17i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_17i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_17i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_17i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_18i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_18i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_18i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_18i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_19i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_19i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_19i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_19i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_20i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_20i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_20i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_20i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_21i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_21i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_21i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_21i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_22i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_22i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_22i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_22i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_23i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_23i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_23i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_23i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x82 {\ |
| UNSG32 uCost8x8_v_16i : 4;\ |
| UNSG32 uCost8x8_v_17i : 4;\ |
| UNSG32 uCost8x8_v_18i : 4;\ |
| UNSG32 uCost8x8_v_19i : 4;\ |
| UNSG32 uCost8x8_v_20i : 4;\ |
| UNSG32 uCost8x8_v_21i : 4;\ |
| UNSG32 uCost8x8_v_22i : 4;\ |
| UNSG32 uCost8x8_v_23i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x82; |
| struct w32RF64QdeQ_Cost8x82; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_24i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_24i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_24i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_24i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_25i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_25i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_25i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_25i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_26i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_26i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_26i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_26i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_27i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_27i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_27i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_27i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_28i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_28i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_28i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_28i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_29i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_29i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_29i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_29i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_30i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_30i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_30i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_30i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_31i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_31i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_31i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_31i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x83 {\ |
| UNSG32 uCost8x8_v_24i : 4;\ |
| UNSG32 uCost8x8_v_25i : 4;\ |
| UNSG32 uCost8x8_v_26i : 4;\ |
| UNSG32 uCost8x8_v_27i : 4;\ |
| UNSG32 uCost8x8_v_28i : 4;\ |
| UNSG32 uCost8x8_v_29i : 4;\ |
| UNSG32 uCost8x8_v_30i : 4;\ |
| UNSG32 uCost8x8_v_31i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x83; |
| struct w32RF64QdeQ_Cost8x83; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_32i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_32i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_32i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_32i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_33i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_33i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_33i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_33i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_34i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_34i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_34i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_34i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_35i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_35i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_35i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_35i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_36i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_36i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_36i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_36i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_37i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_37i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_37i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_37i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_38i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_38i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_38i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_38i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_39i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_39i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_39i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_39i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x84 {\ |
| UNSG32 uCost8x8_v_32i : 4;\ |
| UNSG32 uCost8x8_v_33i : 4;\ |
| UNSG32 uCost8x8_v_34i : 4;\ |
| UNSG32 uCost8x8_v_35i : 4;\ |
| UNSG32 uCost8x8_v_36i : 4;\ |
| UNSG32 uCost8x8_v_37i : 4;\ |
| UNSG32 uCost8x8_v_38i : 4;\ |
| UNSG32 uCost8x8_v_39i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x84; |
| struct w32RF64QdeQ_Cost8x84; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_40i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_40i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_40i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_40i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_41i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_41i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_41i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_41i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_42i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_42i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_42i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_42i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_43i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_43i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_43i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_43i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_44i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_44i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_44i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_44i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_45i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_45i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_45i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_45i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_46i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_46i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_46i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_46i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_47i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_47i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_47i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_47i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x85 {\ |
| UNSG32 uCost8x8_v_40i : 4;\ |
| UNSG32 uCost8x8_v_41i : 4;\ |
| UNSG32 uCost8x8_v_42i : 4;\ |
| UNSG32 uCost8x8_v_43i : 4;\ |
| UNSG32 uCost8x8_v_44i : 4;\ |
| UNSG32 uCost8x8_v_45i : 4;\ |
| UNSG32 uCost8x8_v_46i : 4;\ |
| UNSG32 uCost8x8_v_47i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x85; |
| struct w32RF64QdeQ_Cost8x85; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_48i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_48i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_48i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_48i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_49i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_49i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_49i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_49i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_50i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_50i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_50i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_50i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_51i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_51i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_51i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_51i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_52i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_52i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_52i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_52i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_53i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_53i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_53i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_53i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_54i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_54i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_54i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_54i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_55i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_55i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_55i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_55i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x86 {\ |
| UNSG32 uCost8x8_v_48i : 4;\ |
| UNSG32 uCost8x8_v_49i : 4;\ |
| UNSG32 uCost8x8_v_50i : 4;\ |
| UNSG32 uCost8x8_v_51i : 4;\ |
| UNSG32 uCost8x8_v_52i : 4;\ |
| UNSG32 uCost8x8_v_53i : 4;\ |
| UNSG32 uCost8x8_v_54i : 4;\ |
| UNSG32 uCost8x8_v_55i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x86; |
| struct w32RF64QdeQ_Cost8x86; |
| }; |
| #define GET32RF64QdeQ_Cost8x8_v_56i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost8x8_v_56i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost8x8_v_56i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_56i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_57i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost8x8_v_57i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost8x8_v_57i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_57i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_58i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost8x8_v_58i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost8x8_v_58i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_58i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_59i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost8x8_v_59i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost8x8_v_59i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_59i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_60i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost8x8_v_60i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost8x8_v_60i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost8x8_v_60i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_61i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost8x8_v_61i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost8x8_v_61i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost8x8_v_61i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_62i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost8x8_v_62i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost8x8_v_62i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost8x8_v_62i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost8x8_v_63i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost8x8_v_63i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost8x8_v_63i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost8x8_v_63i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost8x87 {\ |
| UNSG32 uCost8x8_v_56i : 4;\ |
| UNSG32 uCost8x8_v_57i : 4;\ |
| UNSG32 uCost8x8_v_58i : 4;\ |
| UNSG32 uCost8x8_v_59i : 4;\ |
| UNSG32 uCost8x8_v_60i : 4;\ |
| UNSG32 uCost8x8_v_61i : 4;\ |
| UNSG32 uCost8x8_v_62i : 4;\ |
| UNSG32 uCost8x8_v_63i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost8x87; |
| struct w32RF64QdeQ_Cost8x87; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_DZ8x8Intra_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra {\ |
| UNSG32 uDZ8x8Intra_v_0i : 4;\ |
| UNSG32 uDZ8x8Intra_v_1i : 4;\ |
| UNSG32 uDZ8x8Intra_v_2i : 4;\ |
| UNSG32 uDZ8x8Intra_v_3i : 4;\ |
| UNSG32 uDZ8x8Intra_v_4i : 4;\ |
| UNSG32 uDZ8x8Intra_v_5i : 4;\ |
| UNSG32 uDZ8x8Intra_v_6i : 4;\ |
| UNSG32 uDZ8x8Intra_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra; |
| struct w32RF64QdeQ_DZ8x8Intra; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra1 {\ |
| UNSG32 uDZ8x8Intra_v_8i : 4;\ |
| UNSG32 uDZ8x8Intra_v_9i : 4;\ |
| UNSG32 uDZ8x8Intra_v_10i : 4;\ |
| UNSG32 uDZ8x8Intra_v_11i : 4;\ |
| UNSG32 uDZ8x8Intra_v_12i : 4;\ |
| UNSG32 uDZ8x8Intra_v_13i : 4;\ |
| UNSG32 uDZ8x8Intra_v_14i : 4;\ |
| UNSG32 uDZ8x8Intra_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra1; |
| struct w32RF64QdeQ_DZ8x8Intra1; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_16i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_16i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_16i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_16i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_17i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_17i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_17i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_17i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_18i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_18i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_18i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_18i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_19i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_19i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_19i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_19i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_20i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_20i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_20i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_20i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_21i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_21i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_21i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_21i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_22i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_22i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_22i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_22i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_23i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_23i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_23i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_23i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra2 {\ |
| UNSG32 uDZ8x8Intra_v_16i : 4;\ |
| UNSG32 uDZ8x8Intra_v_17i : 4;\ |
| UNSG32 uDZ8x8Intra_v_18i : 4;\ |
| UNSG32 uDZ8x8Intra_v_19i : 4;\ |
| UNSG32 uDZ8x8Intra_v_20i : 4;\ |
| UNSG32 uDZ8x8Intra_v_21i : 4;\ |
| UNSG32 uDZ8x8Intra_v_22i : 4;\ |
| UNSG32 uDZ8x8Intra_v_23i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra2; |
| struct w32RF64QdeQ_DZ8x8Intra2; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_24i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_24i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_24i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_24i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_25i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_25i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_25i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_25i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_26i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_26i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_26i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_26i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_27i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_27i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_27i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_27i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_28i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_28i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_28i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_28i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_29i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_29i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_29i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_29i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_30i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_30i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_30i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_30i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_31i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_31i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_31i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_31i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra3 {\ |
| UNSG32 uDZ8x8Intra_v_24i : 4;\ |
| UNSG32 uDZ8x8Intra_v_25i : 4;\ |
| UNSG32 uDZ8x8Intra_v_26i : 4;\ |
| UNSG32 uDZ8x8Intra_v_27i : 4;\ |
| UNSG32 uDZ8x8Intra_v_28i : 4;\ |
| UNSG32 uDZ8x8Intra_v_29i : 4;\ |
| UNSG32 uDZ8x8Intra_v_30i : 4;\ |
| UNSG32 uDZ8x8Intra_v_31i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra3; |
| struct w32RF64QdeQ_DZ8x8Intra3; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_32i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_32i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_32i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_32i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_33i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_33i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_33i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_33i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_34i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_34i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_34i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_34i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_35i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_35i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_35i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_35i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_36i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_36i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_36i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_36i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_37i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_37i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_37i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_37i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_38i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_38i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_38i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_38i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_39i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_39i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_39i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_39i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra4 {\ |
| UNSG32 uDZ8x8Intra_v_32i : 4;\ |
| UNSG32 uDZ8x8Intra_v_33i : 4;\ |
| UNSG32 uDZ8x8Intra_v_34i : 4;\ |
| UNSG32 uDZ8x8Intra_v_35i : 4;\ |
| UNSG32 uDZ8x8Intra_v_36i : 4;\ |
| UNSG32 uDZ8x8Intra_v_37i : 4;\ |
| UNSG32 uDZ8x8Intra_v_38i : 4;\ |
| UNSG32 uDZ8x8Intra_v_39i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra4; |
| struct w32RF64QdeQ_DZ8x8Intra4; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_40i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_40i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_40i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_40i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_41i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_41i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_41i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_41i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_42i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_42i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_42i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_42i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_43i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_43i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_43i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_43i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_44i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_44i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_44i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_44i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_45i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_45i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_45i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_45i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_46i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_46i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_46i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_46i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_47i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_47i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_47i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_47i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra5 {\ |
| UNSG32 uDZ8x8Intra_v_40i : 4;\ |
| UNSG32 uDZ8x8Intra_v_41i : 4;\ |
| UNSG32 uDZ8x8Intra_v_42i : 4;\ |
| UNSG32 uDZ8x8Intra_v_43i : 4;\ |
| UNSG32 uDZ8x8Intra_v_44i : 4;\ |
| UNSG32 uDZ8x8Intra_v_45i : 4;\ |
| UNSG32 uDZ8x8Intra_v_46i : 4;\ |
| UNSG32 uDZ8x8Intra_v_47i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra5; |
| struct w32RF64QdeQ_DZ8x8Intra5; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_48i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_48i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_48i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_48i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_49i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_49i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_49i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_49i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_50i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_50i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_50i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_50i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_51i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_51i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_51i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_51i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_52i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_52i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_52i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_52i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_53i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_53i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_53i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_53i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_54i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_54i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_54i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_54i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_55i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_55i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_55i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_55i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra6 {\ |
| UNSG32 uDZ8x8Intra_v_48i : 4;\ |
| UNSG32 uDZ8x8Intra_v_49i : 4;\ |
| UNSG32 uDZ8x8Intra_v_50i : 4;\ |
| UNSG32 uDZ8x8Intra_v_51i : 4;\ |
| UNSG32 uDZ8x8Intra_v_52i : 4;\ |
| UNSG32 uDZ8x8Intra_v_53i : 4;\ |
| UNSG32 uDZ8x8Intra_v_54i : 4;\ |
| UNSG32 uDZ8x8Intra_v_55i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra6; |
| struct w32RF64QdeQ_DZ8x8Intra6; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Intra_v_56i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_56i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_56i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_56i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_57i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_57i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_57i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_57i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_58i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_58i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_58i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_58i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_59i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_59i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_59i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_59i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_60i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_60i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_60i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_60i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_61i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_61i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_61i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_61i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_62i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_62i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_62i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_62i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Intra_v_63i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Intra_v_63i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Intra_v_63i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Intra_v_63i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Intra7 {\ |
| UNSG32 uDZ8x8Intra_v_56i : 4;\ |
| UNSG32 uDZ8x8Intra_v_57i : 4;\ |
| UNSG32 uDZ8x8Intra_v_58i : 4;\ |
| UNSG32 uDZ8x8Intra_v_59i : 4;\ |
| UNSG32 uDZ8x8Intra_v_60i : 4;\ |
| UNSG32 uDZ8x8Intra_v_61i : 4;\ |
| UNSG32 uDZ8x8Intra_v_62i : 4;\ |
| UNSG32 uDZ8x8Intra_v_63i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Intra7; |
| struct w32RF64QdeQ_DZ8x8Intra7; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_DZ8x8Inter_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter {\ |
| UNSG32 uDZ8x8Inter_v_0i : 4;\ |
| UNSG32 uDZ8x8Inter_v_1i : 4;\ |
| UNSG32 uDZ8x8Inter_v_2i : 4;\ |
| UNSG32 uDZ8x8Inter_v_3i : 4;\ |
| UNSG32 uDZ8x8Inter_v_4i : 4;\ |
| UNSG32 uDZ8x8Inter_v_5i : 4;\ |
| UNSG32 uDZ8x8Inter_v_6i : 4;\ |
| UNSG32 uDZ8x8Inter_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter; |
| struct w32RF64QdeQ_DZ8x8Inter; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter1 {\ |
| UNSG32 uDZ8x8Inter_v_8i : 4;\ |
| UNSG32 uDZ8x8Inter_v_9i : 4;\ |
| UNSG32 uDZ8x8Inter_v_10i : 4;\ |
| UNSG32 uDZ8x8Inter_v_11i : 4;\ |
| UNSG32 uDZ8x8Inter_v_12i : 4;\ |
| UNSG32 uDZ8x8Inter_v_13i : 4;\ |
| UNSG32 uDZ8x8Inter_v_14i : 4;\ |
| UNSG32 uDZ8x8Inter_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter1; |
| struct w32RF64QdeQ_DZ8x8Inter1; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_16i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_16i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_16i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_16i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_17i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_17i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_17i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_17i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_18i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_18i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_18i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_18i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_19i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_19i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_19i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_19i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_20i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_20i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_20i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_20i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_21i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_21i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_21i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_21i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_22i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_22i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_22i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_22i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_23i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_23i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_23i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_23i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter2 {\ |
| UNSG32 uDZ8x8Inter_v_16i : 4;\ |
| UNSG32 uDZ8x8Inter_v_17i : 4;\ |
| UNSG32 uDZ8x8Inter_v_18i : 4;\ |
| UNSG32 uDZ8x8Inter_v_19i : 4;\ |
| UNSG32 uDZ8x8Inter_v_20i : 4;\ |
| UNSG32 uDZ8x8Inter_v_21i : 4;\ |
| UNSG32 uDZ8x8Inter_v_22i : 4;\ |
| UNSG32 uDZ8x8Inter_v_23i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter2; |
| struct w32RF64QdeQ_DZ8x8Inter2; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_24i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_24i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_24i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_24i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_25i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_25i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_25i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_25i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_26i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_26i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_26i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_26i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_27i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_27i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_27i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_27i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_28i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_28i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_28i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_28i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_29i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_29i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_29i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_29i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_30i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_30i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_30i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_30i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_31i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_31i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_31i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_31i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter3 {\ |
| UNSG32 uDZ8x8Inter_v_24i : 4;\ |
| UNSG32 uDZ8x8Inter_v_25i : 4;\ |
| UNSG32 uDZ8x8Inter_v_26i : 4;\ |
| UNSG32 uDZ8x8Inter_v_27i : 4;\ |
| UNSG32 uDZ8x8Inter_v_28i : 4;\ |
| UNSG32 uDZ8x8Inter_v_29i : 4;\ |
| UNSG32 uDZ8x8Inter_v_30i : 4;\ |
| UNSG32 uDZ8x8Inter_v_31i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter3; |
| struct w32RF64QdeQ_DZ8x8Inter3; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_32i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_32i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_32i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_32i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_33i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_33i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_33i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_33i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_34i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_34i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_34i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_34i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_35i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_35i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_35i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_35i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_36i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_36i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_36i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_36i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_37i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_37i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_37i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_37i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_38i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_38i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_38i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_38i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_39i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_39i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_39i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_39i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter4 {\ |
| UNSG32 uDZ8x8Inter_v_32i : 4;\ |
| UNSG32 uDZ8x8Inter_v_33i : 4;\ |
| UNSG32 uDZ8x8Inter_v_34i : 4;\ |
| UNSG32 uDZ8x8Inter_v_35i : 4;\ |
| UNSG32 uDZ8x8Inter_v_36i : 4;\ |
| UNSG32 uDZ8x8Inter_v_37i : 4;\ |
| UNSG32 uDZ8x8Inter_v_38i : 4;\ |
| UNSG32 uDZ8x8Inter_v_39i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter4; |
| struct w32RF64QdeQ_DZ8x8Inter4; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_40i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_40i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_40i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_40i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_41i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_41i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_41i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_41i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_42i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_42i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_42i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_42i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_43i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_43i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_43i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_43i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_44i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_44i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_44i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_44i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_45i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_45i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_45i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_45i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_46i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_46i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_46i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_46i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_47i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_47i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_47i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_47i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter5 {\ |
| UNSG32 uDZ8x8Inter_v_40i : 4;\ |
| UNSG32 uDZ8x8Inter_v_41i : 4;\ |
| UNSG32 uDZ8x8Inter_v_42i : 4;\ |
| UNSG32 uDZ8x8Inter_v_43i : 4;\ |
| UNSG32 uDZ8x8Inter_v_44i : 4;\ |
| UNSG32 uDZ8x8Inter_v_45i : 4;\ |
| UNSG32 uDZ8x8Inter_v_46i : 4;\ |
| UNSG32 uDZ8x8Inter_v_47i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter5; |
| struct w32RF64QdeQ_DZ8x8Inter5; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_48i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_48i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_48i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_48i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_49i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_49i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_49i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_49i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_50i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_50i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_50i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_50i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_51i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_51i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_51i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_51i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_52i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_52i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_52i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_52i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_53i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_53i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_53i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_53i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_54i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_54i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_54i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_54i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_55i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_55i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_55i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_55i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter6 {\ |
| UNSG32 uDZ8x8Inter_v_48i : 4;\ |
| UNSG32 uDZ8x8Inter_v_49i : 4;\ |
| UNSG32 uDZ8x8Inter_v_50i : 4;\ |
| UNSG32 uDZ8x8Inter_v_51i : 4;\ |
| UNSG32 uDZ8x8Inter_v_52i : 4;\ |
| UNSG32 uDZ8x8Inter_v_53i : 4;\ |
| UNSG32 uDZ8x8Inter_v_54i : 4;\ |
| UNSG32 uDZ8x8Inter_v_55i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter6; |
| struct w32RF64QdeQ_DZ8x8Inter6; |
| }; |
| #define GET32RF64QdeQ_DZ8x8Inter_v_56i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_56i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_56i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_56i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_57i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_57i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_57i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_57i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_58i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_58i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_58i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_58i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_59i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_59i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_59i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_59i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_60i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_60i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_60i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_60i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_61i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_61i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_61i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_61i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_62i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_62i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_62i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_62i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ8x8Inter_v_63i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ8x8Inter_v_63i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ8x8Inter_v_63i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ8x8Inter_v_63i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ8x8Inter7 {\ |
| UNSG32 uDZ8x8Inter_v_56i : 4;\ |
| UNSG32 uDZ8x8Inter_v_57i : 4;\ |
| UNSG32 uDZ8x8Inter_v_58i : 4;\ |
| UNSG32 uDZ8x8Inter_v_59i : 4;\ |
| UNSG32 uDZ8x8Inter_v_60i : 4;\ |
| UNSG32 uDZ8x8Inter_v_61i : 4;\ |
| UNSG32 uDZ8x8Inter_v_62i : 4;\ |
| UNSG32 uDZ8x8Inter_v_63i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ8x8Inter7; |
| struct w32RF64QdeQ_DZ8x8Inter7; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Cost4x4_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost4x4_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost4x4_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost4x4_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost4x4_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost4x4_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost4x4_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost4x4_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost4x4_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost4x4_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost4x4_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost4x4_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost4x4_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost4x4_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost4x4_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost4x4_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost4x4_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost4x4_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost4x4_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost4x4_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost4x4_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost4x4_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost4x4_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost4x4_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost4x4_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost4x4 {\ |
| UNSG32 uCost4x4_v_0i : 4;\ |
| UNSG32 uCost4x4_v_1i : 4;\ |
| UNSG32 uCost4x4_v_2i : 4;\ |
| UNSG32 uCost4x4_v_3i : 4;\ |
| UNSG32 uCost4x4_v_4i : 4;\ |
| UNSG32 uCost4x4_v_5i : 4;\ |
| UNSG32 uCost4x4_v_6i : 4;\ |
| UNSG32 uCost4x4_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost4x4; |
| struct w32RF64QdeQ_Cost4x4; |
| }; |
| #define GET32RF64QdeQ_Cost4x4_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Cost4x4_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Cost4x4_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost4x4_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Cost4x4_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Cost4x4_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost4x4_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Cost4x4_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Cost4x4_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost4x4_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Cost4x4_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Cost4x4_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost4x4_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Cost4x4_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Cost4x4_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Cost4x4_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Cost4x4_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Cost4x4_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Cost4x4_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Cost4x4_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Cost4x4_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Cost4x4_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Cost4x4_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Cost4x4_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Cost4x4_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Cost4x4_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Cost4x41 {\ |
| UNSG32 uCost4x4_v_8i : 4;\ |
| UNSG32 uCost4x4_v_9i : 4;\ |
| UNSG32 uCost4x4_v_10i : 4;\ |
| UNSG32 uCost4x4_v_11i : 4;\ |
| UNSG32 uCost4x4_v_12i : 4;\ |
| UNSG32 uCost4x4_v_13i : 4;\ |
| UNSG32 uCost4x4_v_14i : 4;\ |
| UNSG32 uCost4x4_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Cost4x41; |
| struct w32RF64QdeQ_Cost4x41; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_DZ4x4Intra_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ4x4Intra {\ |
| UNSG32 uDZ4x4Intra_v_0i : 4;\ |
| UNSG32 uDZ4x4Intra_v_1i : 4;\ |
| UNSG32 uDZ4x4Intra_v_2i : 4;\ |
| UNSG32 uDZ4x4Intra_v_3i : 4;\ |
| UNSG32 uDZ4x4Intra_v_4i : 4;\ |
| UNSG32 uDZ4x4Intra_v_5i : 4;\ |
| UNSG32 uDZ4x4Intra_v_6i : 4;\ |
| UNSG32 uDZ4x4Intra_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ4x4Intra; |
| struct w32RF64QdeQ_DZ4x4Intra; |
| }; |
| #define GET32RF64QdeQ_DZ4x4Intra_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Intra_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ4x4Intra_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ4x4Intra_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Intra_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ4x4Intra1 {\ |
| UNSG32 uDZ4x4Intra_v_8i : 4;\ |
| UNSG32 uDZ4x4Intra_v_9i : 4;\ |
| UNSG32 uDZ4x4Intra_v_10i : 4;\ |
| UNSG32 uDZ4x4Intra_v_11i : 4;\ |
| UNSG32 uDZ4x4Intra_v_12i : 4;\ |
| UNSG32 uDZ4x4Intra_v_13i : 4;\ |
| UNSG32 uDZ4x4Intra_v_14i : 4;\ |
| UNSG32 uDZ4x4Intra_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ4x4Intra1; |
| struct w32RF64QdeQ_DZ4x4Intra1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_DZ4x4Inter_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ4x4Inter {\ |
| UNSG32 uDZ4x4Inter_v_0i : 4;\ |
| UNSG32 uDZ4x4Inter_v_1i : 4;\ |
| UNSG32 uDZ4x4Inter_v_2i : 4;\ |
| UNSG32 uDZ4x4Inter_v_3i : 4;\ |
| UNSG32 uDZ4x4Inter_v_4i : 4;\ |
| UNSG32 uDZ4x4Inter_v_5i : 4;\ |
| UNSG32 uDZ4x4Inter_v_6i : 4;\ |
| UNSG32 uDZ4x4Inter_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ4x4Inter; |
| struct w32RF64QdeQ_DZ4x4Inter; |
| }; |
| #define GET32RF64QdeQ_DZ4x4Inter_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_DZ4x4Inter_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_DZ4x4Inter_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_DZ4x4Inter_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_DZ4x4Inter_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_DZ4x4Inter1 {\ |
| UNSG32 uDZ4x4Inter_v_8i : 4;\ |
| UNSG32 uDZ4x4Inter_v_9i : 4;\ |
| UNSG32 uDZ4x4Inter_v_10i : 4;\ |
| UNSG32 uDZ4x4Inter_v_11i : 4;\ |
| UNSG32 uDZ4x4Inter_v_12i : 4;\ |
| UNSG32 uDZ4x4Inter_v_13i : 4;\ |
| UNSG32 uDZ4x4Inter_v_14i : 4;\ |
| UNSG32 uDZ4x4Inter_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_DZ4x4Inter1; |
| struct w32RF64QdeQ_DZ4x4Inter1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_PostQThr_TailYIntra8x8(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_PostQThr_TailYIntra8x8(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_PostQThr_TailYIntra8x8(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_PostQThr_TailYIntra8x8(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailUVIntra8x8(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_PostQThr_TailUVIntra8x8(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_PostQThr_TailUVIntra8x8(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_PostQThr_TailUVIntra8x8(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailYInter8x8(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_PostQThr_TailYInter8x8(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_PostQThr_TailYInter8x8(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_PostQThr_TailYInter8x8(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailUVInter8x8(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_PostQThr_TailUVInter8x8(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_PostQThr_TailUVInter8x8(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_PostQThr_TailUVInter8x8(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailYIntra4x4(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_PostQThr_TailYIntra4x4(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_PostQThr_TailYIntra4x4(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_PostQThr_TailYIntra4x4(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailUVIntra4x4(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_PostQThr_TailUVIntra4x4(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_PostQThr_TailUVIntra4x4(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_PostQThr_TailUVIntra4x4(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailYInter4x4(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_PostQThr_TailYInter4x4(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_PostQThr_TailYInter4x4(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_PostQThr_TailYInter4x4(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_PostQThr_TailUVInter4x4(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_PostQThr_TailUVInter4x4(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_PostQThr_TailUVInter4x4(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_PostQThr_TailUVInter4x4(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_PostQThr {\ |
| UNSG32 uPostQThr_TailYIntra8x8 : 4;\ |
| UNSG32 uPostQThr_TailUVIntra8x8 : 4;\ |
| UNSG32 uPostQThr_TailYInter8x8 : 4;\ |
| UNSG32 uPostQThr_TailUVInter8x8 : 4;\ |
| UNSG32 uPostQThr_TailYIntra4x4 : 4;\ |
| UNSG32 uPostQThr_TailUVIntra4x4 : 4;\ |
| UNSG32 uPostQThr_TailYInter4x4 : 4;\ |
| UNSG32 uPostQThr_TailUVInter4x4 : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_PostQThr; |
| struct w32RF64QdeQ_PostQThr; |
| }; |
| #define GET32RF64QdeQ_PostQThr_ZeroYInter8x8(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_PostQThr_ZeroYInter8x8(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_PostQThr_ZeroYInter8x8(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_PostQThr_ZeroYInter8x8(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_PostQThr_ZeroUVInter8x8(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_PostQThr_ZeroUVInter8x8(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_PostQThr_ZeroUVInter8x8(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_PostQThr_ZeroUVInter8x8(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_PostQThr_ZeroYInter4x4(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_PostQThr_ZeroYInter4x4(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_PostQThr_ZeroYInter4x4(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_PostQThr_ZeroYInter4x4(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_PostQThr_ZeroUVInter4x4(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_PostQThr_ZeroUVInter4x4(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_PostQThr_ZeroUVInter4x4(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_PostQThr_ZeroUVInter4x4(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_PostQThr1 {\ |
| UNSG32 uPostQThr_ZeroYInter8x8 : 8;\ |
| UNSG32 uPostQThr_ZeroUVInter8x8 : 8;\ |
| UNSG32 uPostQThr_ZeroYInter4x4 : 8;\ |
| UNSG32 uPostQThr_ZeroUVInter4x4 : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_PostQThr1; |
| struct w32RF64QdeQ_PostQThr1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Scan8x8_v_0i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_0i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_0i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_0i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_1i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_1i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_1i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_1i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_2i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_2i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_2i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_2i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_3i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_3i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_3i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_3i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x8 {\ |
| UNSG32 uScan8x8_v_0i : 8;\ |
| UNSG32 uScan8x8_v_1i : 8;\ |
| UNSG32 uScan8x8_v_2i : 8;\ |
| UNSG32 uScan8x8_v_3i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x8; |
| struct w32RF64QdeQ_Scan8x8; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_4i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_4i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_4i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_4i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_5i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_5i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_5i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_5i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_6i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_6i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_6i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_6i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_7i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_7i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_7i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_7i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x81 {\ |
| UNSG32 uScan8x8_v_4i : 8;\ |
| UNSG32 uScan8x8_v_5i : 8;\ |
| UNSG32 uScan8x8_v_6i : 8;\ |
| UNSG32 uScan8x8_v_7i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x81; |
| struct w32RF64QdeQ_Scan8x81; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_8i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_8i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_8i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_8i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_9i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_9i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_9i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_9i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_10i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_10i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_10i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_10i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_11i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_11i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_11i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_11i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x82 {\ |
| UNSG32 uScan8x8_v_8i : 8;\ |
| UNSG32 uScan8x8_v_9i : 8;\ |
| UNSG32 uScan8x8_v_10i : 8;\ |
| UNSG32 uScan8x8_v_11i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x82; |
| struct w32RF64QdeQ_Scan8x82; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_12i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_12i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_12i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_12i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_13i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_13i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_13i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_13i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_14i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_14i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_14i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_14i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_15i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_15i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_15i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_15i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x83 {\ |
| UNSG32 uScan8x8_v_12i : 8;\ |
| UNSG32 uScan8x8_v_13i : 8;\ |
| UNSG32 uScan8x8_v_14i : 8;\ |
| UNSG32 uScan8x8_v_15i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x83; |
| struct w32RF64QdeQ_Scan8x83; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_16i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_16i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_16i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_16i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_17i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_17i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_17i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_17i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_18i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_18i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_18i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_18i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_19i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_19i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_19i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_19i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x84 {\ |
| UNSG32 uScan8x8_v_16i : 8;\ |
| UNSG32 uScan8x8_v_17i : 8;\ |
| UNSG32 uScan8x8_v_18i : 8;\ |
| UNSG32 uScan8x8_v_19i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x84; |
| struct w32RF64QdeQ_Scan8x84; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_20i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_20i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_20i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_20i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_21i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_21i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_21i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_21i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_22i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_22i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_22i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_22i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_23i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_23i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_23i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_23i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x85 {\ |
| UNSG32 uScan8x8_v_20i : 8;\ |
| UNSG32 uScan8x8_v_21i : 8;\ |
| UNSG32 uScan8x8_v_22i : 8;\ |
| UNSG32 uScan8x8_v_23i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x85; |
| struct w32RF64QdeQ_Scan8x85; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_24i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_24i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_24i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_24i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_25i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_25i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_25i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_25i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_26i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_26i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_26i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_26i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_27i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_27i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_27i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_27i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x86 {\ |
| UNSG32 uScan8x8_v_24i : 8;\ |
| UNSG32 uScan8x8_v_25i : 8;\ |
| UNSG32 uScan8x8_v_26i : 8;\ |
| UNSG32 uScan8x8_v_27i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x86; |
| struct w32RF64QdeQ_Scan8x86; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_28i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_28i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_28i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_28i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_29i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_29i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_29i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_29i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_30i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_30i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_30i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_30i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_31i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_31i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_31i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_31i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x87 {\ |
| UNSG32 uScan8x8_v_28i : 8;\ |
| UNSG32 uScan8x8_v_29i : 8;\ |
| UNSG32 uScan8x8_v_30i : 8;\ |
| UNSG32 uScan8x8_v_31i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x87; |
| struct w32RF64QdeQ_Scan8x87; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_32i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_32i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_32i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_32i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_33i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_33i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_33i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_33i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_34i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_34i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_34i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_34i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_35i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_35i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_35i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_35i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x88 {\ |
| UNSG32 uScan8x8_v_32i : 8;\ |
| UNSG32 uScan8x8_v_33i : 8;\ |
| UNSG32 uScan8x8_v_34i : 8;\ |
| UNSG32 uScan8x8_v_35i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x88; |
| struct w32RF64QdeQ_Scan8x88; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_36i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_36i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_36i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_36i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_37i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_37i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_37i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_37i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_38i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_38i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_38i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_38i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_39i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_39i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_39i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_39i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x89 {\ |
| UNSG32 uScan8x8_v_36i : 8;\ |
| UNSG32 uScan8x8_v_37i : 8;\ |
| UNSG32 uScan8x8_v_38i : 8;\ |
| UNSG32 uScan8x8_v_39i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x89; |
| struct w32RF64QdeQ_Scan8x89; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_40i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_40i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_40i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_40i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_41i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_41i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_41i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_41i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_42i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_42i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_42i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_42i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_43i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_43i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_43i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_43i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x810 {\ |
| UNSG32 uScan8x8_v_40i : 8;\ |
| UNSG32 uScan8x8_v_41i : 8;\ |
| UNSG32 uScan8x8_v_42i : 8;\ |
| UNSG32 uScan8x8_v_43i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x810; |
| struct w32RF64QdeQ_Scan8x810; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_44i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_44i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_44i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_44i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_45i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_45i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_45i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_45i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_46i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_46i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_46i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_46i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_47i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_47i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_47i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_47i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x811 {\ |
| UNSG32 uScan8x8_v_44i : 8;\ |
| UNSG32 uScan8x8_v_45i : 8;\ |
| UNSG32 uScan8x8_v_46i : 8;\ |
| UNSG32 uScan8x8_v_47i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x811; |
| struct w32RF64QdeQ_Scan8x811; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_48i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_48i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_48i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_48i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_49i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_49i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_49i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_49i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_50i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_50i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_50i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_50i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_51i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_51i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_51i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_51i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x812 {\ |
| UNSG32 uScan8x8_v_48i : 8;\ |
| UNSG32 uScan8x8_v_49i : 8;\ |
| UNSG32 uScan8x8_v_50i : 8;\ |
| UNSG32 uScan8x8_v_51i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x812; |
| struct w32RF64QdeQ_Scan8x812; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_52i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_52i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_52i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_52i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_53i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_53i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_53i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_53i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_54i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_54i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_54i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_54i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_55i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_55i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_55i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_55i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x813 {\ |
| UNSG32 uScan8x8_v_52i : 8;\ |
| UNSG32 uScan8x8_v_53i : 8;\ |
| UNSG32 uScan8x8_v_54i : 8;\ |
| UNSG32 uScan8x8_v_55i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x813; |
| struct w32RF64QdeQ_Scan8x813; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_56i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_56i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_56i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_56i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_57i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_57i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_57i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_57i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_58i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_58i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_58i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_58i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_59i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_59i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_59i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_59i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x814 {\ |
| UNSG32 uScan8x8_v_56i : 8;\ |
| UNSG32 uScan8x8_v_57i : 8;\ |
| UNSG32 uScan8x8_v_58i : 8;\ |
| UNSG32 uScan8x8_v_59i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x814; |
| struct w32RF64QdeQ_Scan8x814; |
| }; |
| #define GET32RF64QdeQ_Scan8x8_v_60i(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Scan8x8_v_60i(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Scan8x8_v_60i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_60i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_61i(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Scan8x8_v_61i(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Scan8x8_v_61i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_61i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_62i(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Scan8x8_v_62i(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Scan8x8_v_62i(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Scan8x8_v_62i(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Scan8x8_v_63i(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Scan8x8_v_63i(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Scan8x8_v_63i(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Scan8x8_v_63i(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Scan8x815 {\ |
| UNSG32 uScan8x8_v_60i : 8;\ |
| UNSG32 uScan8x8_v_61i : 8;\ |
| UNSG32 uScan8x8_v_62i : 8;\ |
| UNSG32 uScan8x8_v_63i : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan8x815; |
| struct w32RF64QdeQ_Scan8x815; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Scan4x4_v_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Scan4x4_v_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Scan4x4_v_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Scan4x4_v_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Scan4x4_v_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Scan4x4_v_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Scan4x4_v_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Scan4x4_v_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Scan4x4_v_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Scan4x4_v_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_3i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Scan4x4_v_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Scan4x4_v_3i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Scan4x4_v_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_4i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Scan4x4_v_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Scan4x4_v_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Scan4x4_v_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_5i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Scan4x4_v_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Scan4x4_v_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Scan4x4_v_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_6i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Scan4x4_v_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Scan4x4_v_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Scan4x4_v_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_7i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Scan4x4_v_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Scan4x4_v_7i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Scan4x4_v_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Scan4x4 {\ |
| UNSG32 uScan4x4_v_0i : 4;\ |
| UNSG32 uScan4x4_v_1i : 4;\ |
| UNSG32 uScan4x4_v_2i : 4;\ |
| UNSG32 uScan4x4_v_3i : 4;\ |
| UNSG32 uScan4x4_v_4i : 4;\ |
| UNSG32 uScan4x4_v_5i : 4;\ |
| UNSG32 uScan4x4_v_6i : 4;\ |
| UNSG32 uScan4x4_v_7i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan4x4; |
| struct w32RF64QdeQ_Scan4x4; |
| }; |
| #define GET32RF64QdeQ_Scan4x4_v_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Scan4x4_v_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Scan4x4_v_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Scan4x4_v_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Scan4x4_v_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Scan4x4_v_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Scan4x4_v_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64QdeQ_Scan4x4_v_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64QdeQ_Scan4x4_v_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Scan4x4_v_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_11i(r32) _BFGET_(r32,15,12) |
| #define SET32RF64QdeQ_Scan4x4_v_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64QdeQ_Scan4x4_v_11i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Scan4x4_v_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_12i(r32) _BFGET_(r32,19,16) |
| #define SET32RF64QdeQ_Scan4x4_v_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64QdeQ_Scan4x4_v_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Scan4x4_v_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_13i(r32) _BFGET_(r32,23,20) |
| #define SET32RF64QdeQ_Scan4x4_v_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64QdeQ_Scan4x4_v_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Scan4x4_v_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_14i(r32) _BFGET_(r32,27,24) |
| #define SET32RF64QdeQ_Scan4x4_v_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64QdeQ_Scan4x4_v_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64QdeQ_Scan4x4_v_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64QdeQ_Scan4x4_v_15i(r32) _BFGET_(r32,31,28) |
| #define SET32RF64QdeQ_Scan4x4_v_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64QdeQ_Scan4x4_v_15i(r16) _BFGET_(r16,15,12) |
| #define SET16RF64QdeQ_Scan4x4_v_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64QdeQ_Scan4x41 {\ |
| UNSG32 uScan4x4_v_8i : 4;\ |
| UNSG32 uScan4x4_v_9i : 4;\ |
| UNSG32 uScan4x4_v_10i : 4;\ |
| UNSG32 uScan4x4_v_11i : 4;\ |
| UNSG32 uScan4x4_v_12i : 4;\ |
| UNSG32 uScan4x4_v_13i : 4;\ |
| UNSG32 uScan4x4_v_14i : 4;\ |
| UNSG32 uScan4x4_v_15i : 4;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Scan4x41; |
| struct w32RF64QdeQ_Scan4x41; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Param1_IntraDC(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QdeQ_Param1_IntraDC(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QdeQ_Param1_IntraDC(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Param1_IntraDC(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Param1_IntraAC(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Param1_IntraAC(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Param1_IntraAC(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Param1_IntraAC(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Param1_InterDC(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Param1_InterDC(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Param1_InterDC(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Param1_InterDC(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Param1_InterAC(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Param1_InterAC(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Param1_InterAC(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Param1_InterAC(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Param1 {\ |
| UNSG32 uParam1_IntraDC : 8;\ |
| UNSG32 uParam1_IntraAC : 8;\ |
| UNSG32 uParam1_InterDC : 8;\ |
| UNSG32 uParam1_InterAC : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param1; |
| struct w32RF64QdeQ_Param1; |
| }; |
| #define GET32RF64QdeQ_Param1_Type(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64QdeQ_Param1_Type(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64QdeQ_Param1_Type(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64QdeQ_Param1_Type(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64QdeQ_Param1_EOB4x4(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64QdeQ_Param1_EOB4x4(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64QdeQ_Param1_EOB4x4(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64QdeQ_Param1_EOB4x4(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64QdeQ_Param1_QPY(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QdeQ_Param1_QPY(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QdeQ_Param1_QPY(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Param1_QPY(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QdeQ_Param1_QPU(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QdeQ_Param1_QPU(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QdeQ_Param1_QPU(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QdeQ_Param1_QPU(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QdeQ_Param1_QPV(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QdeQ_Param1_QPV(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QdeQ_Param1_QPV(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QdeQ_Param1_QPV(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64QdeQ_Param11 {\ |
| UNSG32 uParam1_Type : 4;\ |
| UNSG32 uParam1_EOB4x4 : 4;\ |
| UNSG32 uParam1_QPY : 8;\ |
| UNSG32 uParam1_QPU : 8;\ |
| UNSG32 uParam1_QPV : 8;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param11; |
| struct w32RF64QdeQ_Param11; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Param2_QDcLimitL(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64QdeQ_Param2_QDcLimitL(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64QdeQ_Param2_QDcLimitL(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param2_QDcLimitL(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64QdeQ_Param2_QDcLimitH(r32) _BFGET_(r32,31,16) |
| #define SET32RF64QdeQ_Param2_QDcLimitH(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64QdeQ_Param2_QDcLimitH(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param2_QDcLimitH(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32RF64QdeQ_Param2 {\ |
| UNSG32 sParam2_QDcLimitL : 16;\ |
| UNSG32 sParam2_QDcLimitH : 16;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param2; |
| struct w32RF64QdeQ_Param2; |
| }; |
| #define GET32RF64QdeQ_Param2_QAcLimitL(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64QdeQ_Param2_QAcLimitL(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64QdeQ_Param2_QAcLimitL(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param2_QAcLimitL(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64QdeQ_Param2_QAcLimitH(r32) _BFGET_(r32,31,16) |
| #define SET32RF64QdeQ_Param2_QAcLimitH(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64QdeQ_Param2_QAcLimitH(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param2_QAcLimitH(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32RF64QdeQ_Param21 {\ |
| UNSG32 sParam2_QAcLimitL : 16;\ |
| UNSG32 sParam2_QAcLimitH : 16;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param21; |
| struct w32RF64QdeQ_Param21; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Param3_istepY(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64QdeQ_Param3_istepY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64QdeQ_Param3_istepY(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param3_istepY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64QdeQ_Param3_istepC(r32) _BFGET_(r32,31,16) |
| #define SET32RF64QdeQ_Param3_istepC(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64QdeQ_Param3_istepC(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param3_istepC(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32RF64QdeQ_Param3 {\ |
| UNSG32 uParam3_istepY : 16;\ |
| UNSG32 uParam3_istepC : 16;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param3; |
| struct w32RF64QdeQ_Param3; |
| }; |
| #define GET32RF64QdeQ_Param3_AC_dqofs(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64QdeQ_Param3_AC_dqofs(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64QdeQ_Param3_AC_dqofs(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param3_AC_dqofs(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64QdeQ_Param3_dQ_offset(r32) _BFGET_(r32,31,16) |
| #define SET32RF64QdeQ_Param3_dQ_offset(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64QdeQ_Param3_dQ_offset(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64QdeQ_Param3_dQ_offset(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32RF64QdeQ_Param31 {\ |
| UNSG32 uParam3_AC_dqofs : 16;\ |
| UNSG32 uParam3_dQ_offset : 16;\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param31; |
| struct w32RF64QdeQ_Param31; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QdeQ_Param4_EOB8x8(r32) _BFGET_(r32, 5, 0) |
| #define SET32RF64QdeQ_Param4_EOB8x8(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16RF64QdeQ_Param4_EOB8x8(r16) _BFGET_(r16, 5, 0) |
| #define SET16RF64QdeQ_Param4_EOB8x8(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32RF64QdeQ_Param4_istepb(r32) _BFGET_(r32,11, 6) |
| #define SET32RF64QdeQ_Param4_istepb(r32,v) _BFSET_(r32,11, 6,v) |
| #define GET16RF64QdeQ_Param4_istepb(r16) _BFGET_(r16,11, 6) |
| #define SET16RF64QdeQ_Param4_istepb(r16,v) _BFSET_(r16,11, 6,v) |
| |
| #define GET32RF64QdeQ_Param4_MismatchCtrl(r32) _BFGET_(r32,13,12) |
| #define SET32RF64QdeQ_Param4_MismatchCtrl(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16RF64QdeQ_Param4_MismatchCtrl(r16) _BFGET_(r16,13,12) |
| #define SET16RF64QdeQ_Param4_MismatchCtrl(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define w32RF64QdeQ_Param4 {\ |
| UNSG32 uParam4_EOB8x8 : 6;\ |
| UNSG32 uParam4_istepb : 6;\ |
| UNSG32 uParam4_MismatchCtrl : 2;\ |
| UNSG32 RSVDxE0_b14 : 18;\ |
| UNSG8 RSVDxE4 [4];\ |
| } |
| union { UNSG32 u32RF64QdeQ_Param4; |
| struct w32RF64QdeQ_Param4; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64QdeQ; |
| |
| typedef union T32RF64QdeQ_Cost8x8 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x8; |
| } T32RF64QdeQ_Cost8x8; |
| typedef union T32RF64QdeQ_Cost8x81 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x81; |
| } T32RF64QdeQ_Cost8x81; |
| typedef union T32RF64QdeQ_Cost8x82 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x82; |
| } T32RF64QdeQ_Cost8x82; |
| typedef union T32RF64QdeQ_Cost8x83 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x83; |
| } T32RF64QdeQ_Cost8x83; |
| typedef union T32RF64QdeQ_Cost8x84 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x84; |
| } T32RF64QdeQ_Cost8x84; |
| typedef union T32RF64QdeQ_Cost8x85 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x85; |
| } T32RF64QdeQ_Cost8x85; |
| typedef union T32RF64QdeQ_Cost8x86 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x86; |
| } T32RF64QdeQ_Cost8x86; |
| typedef union T32RF64QdeQ_Cost8x87 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost8x87; |
| } T32RF64QdeQ_Cost8x87; |
| typedef union T32RF64QdeQ_DZ8x8Intra |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra; |
| } T32RF64QdeQ_DZ8x8Intra; |
| typedef union T32RF64QdeQ_DZ8x8Intra1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra1; |
| } T32RF64QdeQ_DZ8x8Intra1; |
| typedef union T32RF64QdeQ_DZ8x8Intra2 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra2; |
| } T32RF64QdeQ_DZ8x8Intra2; |
| typedef union T32RF64QdeQ_DZ8x8Intra3 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra3; |
| } T32RF64QdeQ_DZ8x8Intra3; |
| typedef union T32RF64QdeQ_DZ8x8Intra4 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra4; |
| } T32RF64QdeQ_DZ8x8Intra4; |
| typedef union T32RF64QdeQ_DZ8x8Intra5 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra5; |
| } T32RF64QdeQ_DZ8x8Intra5; |
| typedef union T32RF64QdeQ_DZ8x8Intra6 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra6; |
| } T32RF64QdeQ_DZ8x8Intra6; |
| typedef union T32RF64QdeQ_DZ8x8Intra7 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Intra7; |
| } T32RF64QdeQ_DZ8x8Intra7; |
| typedef union T32RF64QdeQ_DZ8x8Inter |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter; |
| } T32RF64QdeQ_DZ8x8Inter; |
| typedef union T32RF64QdeQ_DZ8x8Inter1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter1; |
| } T32RF64QdeQ_DZ8x8Inter1; |
| typedef union T32RF64QdeQ_DZ8x8Inter2 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter2; |
| } T32RF64QdeQ_DZ8x8Inter2; |
| typedef union T32RF64QdeQ_DZ8x8Inter3 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter3; |
| } T32RF64QdeQ_DZ8x8Inter3; |
| typedef union T32RF64QdeQ_DZ8x8Inter4 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter4; |
| } T32RF64QdeQ_DZ8x8Inter4; |
| typedef union T32RF64QdeQ_DZ8x8Inter5 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter5; |
| } T32RF64QdeQ_DZ8x8Inter5; |
| typedef union T32RF64QdeQ_DZ8x8Inter6 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter6; |
| } T32RF64QdeQ_DZ8x8Inter6; |
| typedef union T32RF64QdeQ_DZ8x8Inter7 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ8x8Inter7; |
| } T32RF64QdeQ_DZ8x8Inter7; |
| typedef union T32RF64QdeQ_Cost4x4 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost4x4; |
| } T32RF64QdeQ_Cost4x4; |
| typedef union T32RF64QdeQ_Cost4x41 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Cost4x41; |
| } T32RF64QdeQ_Cost4x41; |
| typedef union T32RF64QdeQ_DZ4x4Intra |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ4x4Intra; |
| } T32RF64QdeQ_DZ4x4Intra; |
| typedef union T32RF64QdeQ_DZ4x4Intra1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ4x4Intra1; |
| } T32RF64QdeQ_DZ4x4Intra1; |
| typedef union T32RF64QdeQ_DZ4x4Inter |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ4x4Inter; |
| } T32RF64QdeQ_DZ4x4Inter; |
| typedef union T32RF64QdeQ_DZ4x4Inter1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_DZ4x4Inter1; |
| } T32RF64QdeQ_DZ4x4Inter1; |
| typedef union T32RF64QdeQ_PostQThr |
| { UNSG32 u32; |
| struct w32RF64QdeQ_PostQThr; |
| } T32RF64QdeQ_PostQThr; |
| typedef union T32RF64QdeQ_PostQThr1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_PostQThr1; |
| } T32RF64QdeQ_PostQThr1; |
| typedef union T32RF64QdeQ_Scan8x8 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x8; |
| } T32RF64QdeQ_Scan8x8; |
| typedef union T32RF64QdeQ_Scan8x81 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x81; |
| } T32RF64QdeQ_Scan8x81; |
| typedef union T32RF64QdeQ_Scan8x82 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x82; |
| } T32RF64QdeQ_Scan8x82; |
| typedef union T32RF64QdeQ_Scan8x83 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x83; |
| } T32RF64QdeQ_Scan8x83; |
| typedef union T32RF64QdeQ_Scan8x84 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x84; |
| } T32RF64QdeQ_Scan8x84; |
| typedef union T32RF64QdeQ_Scan8x85 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x85; |
| } T32RF64QdeQ_Scan8x85; |
| typedef union T32RF64QdeQ_Scan8x86 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x86; |
| } T32RF64QdeQ_Scan8x86; |
| typedef union T32RF64QdeQ_Scan8x87 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x87; |
| } T32RF64QdeQ_Scan8x87; |
| typedef union T32RF64QdeQ_Scan8x88 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x88; |
| } T32RF64QdeQ_Scan8x88; |
| typedef union T32RF64QdeQ_Scan8x89 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x89; |
| } T32RF64QdeQ_Scan8x89; |
| typedef union T32RF64QdeQ_Scan8x810 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x810; |
| } T32RF64QdeQ_Scan8x810; |
| typedef union T32RF64QdeQ_Scan8x811 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x811; |
| } T32RF64QdeQ_Scan8x811; |
| typedef union T32RF64QdeQ_Scan8x812 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x812; |
| } T32RF64QdeQ_Scan8x812; |
| typedef union T32RF64QdeQ_Scan8x813 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x813; |
| } T32RF64QdeQ_Scan8x813; |
| typedef union T32RF64QdeQ_Scan8x814 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x814; |
| } T32RF64QdeQ_Scan8x814; |
| typedef union T32RF64QdeQ_Scan8x815 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan8x815; |
| } T32RF64QdeQ_Scan8x815; |
| typedef union T32RF64QdeQ_Scan4x4 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan4x4; |
| } T32RF64QdeQ_Scan4x4; |
| typedef union T32RF64QdeQ_Scan4x41 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Scan4x41; |
| } T32RF64QdeQ_Scan4x41; |
| typedef union T32RF64QdeQ_Param1 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param1; |
| } T32RF64QdeQ_Param1; |
| typedef union T32RF64QdeQ_Param11 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param11; |
| } T32RF64QdeQ_Param11; |
| typedef union T32RF64QdeQ_Param2 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param2; |
| } T32RF64QdeQ_Param2; |
| typedef union T32RF64QdeQ_Param21 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param21; |
| } T32RF64QdeQ_Param21; |
| typedef union T32RF64QdeQ_Param3 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param3; |
| } T32RF64QdeQ_Param3; |
| typedef union T32RF64QdeQ_Param31 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param31; |
| } T32RF64QdeQ_Param31; |
| typedef union T32RF64QdeQ_Param4 |
| { UNSG32 u32; |
| struct w32RF64QdeQ_Param4; |
| } T32RF64QdeQ_Param4; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TRF64QdeQ_Cost8x8 |
| { UNSG32 u32[8]; |
| struct { |
| struct w32RF64QdeQ_Cost8x8; |
| struct w32RF64QdeQ_Cost8x81; |
| struct w32RF64QdeQ_Cost8x82; |
| struct w32RF64QdeQ_Cost8x83; |
| struct w32RF64QdeQ_Cost8x84; |
| struct w32RF64QdeQ_Cost8x85; |
| struct w32RF64QdeQ_Cost8x86; |
| struct w32RF64QdeQ_Cost8x87; |
| }; |
| } TRF64QdeQ_Cost8x8; |
| typedef union TRF64QdeQ_DZ8x8Intra |
| { UNSG32 u32[8]; |
| struct { |
| struct w32RF64QdeQ_DZ8x8Intra; |
| struct w32RF64QdeQ_DZ8x8Intra1; |
| struct w32RF64QdeQ_DZ8x8Intra2; |
| struct w32RF64QdeQ_DZ8x8Intra3; |
| struct w32RF64QdeQ_DZ8x8Intra4; |
| struct w32RF64QdeQ_DZ8x8Intra5; |
| struct w32RF64QdeQ_DZ8x8Intra6; |
| struct w32RF64QdeQ_DZ8x8Intra7; |
| }; |
| } TRF64QdeQ_DZ8x8Intra; |
| typedef union TRF64QdeQ_DZ8x8Inter |
| { UNSG32 u32[8]; |
| struct { |
| struct w32RF64QdeQ_DZ8x8Inter; |
| struct w32RF64QdeQ_DZ8x8Inter1; |
| struct w32RF64QdeQ_DZ8x8Inter2; |
| struct w32RF64QdeQ_DZ8x8Inter3; |
| struct w32RF64QdeQ_DZ8x8Inter4; |
| struct w32RF64QdeQ_DZ8x8Inter5; |
| struct w32RF64QdeQ_DZ8x8Inter6; |
| struct w32RF64QdeQ_DZ8x8Inter7; |
| }; |
| } TRF64QdeQ_DZ8x8Inter; |
| typedef union TRF64QdeQ_Cost4x4 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Cost4x4; |
| struct w32RF64QdeQ_Cost4x41; |
| }; |
| } TRF64QdeQ_Cost4x4; |
| typedef union TRF64QdeQ_DZ4x4Intra |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_DZ4x4Intra; |
| struct w32RF64QdeQ_DZ4x4Intra1; |
| }; |
| } TRF64QdeQ_DZ4x4Intra; |
| typedef union TRF64QdeQ_DZ4x4Inter |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_DZ4x4Inter; |
| struct w32RF64QdeQ_DZ4x4Inter1; |
| }; |
| } TRF64QdeQ_DZ4x4Inter; |
| typedef union TRF64QdeQ_PostQThr |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_PostQThr; |
| struct w32RF64QdeQ_PostQThr1; |
| }; |
| } TRF64QdeQ_PostQThr; |
| typedef union TRF64QdeQ_Scan8x8 |
| { UNSG32 u32[16]; |
| struct { |
| struct w32RF64QdeQ_Scan8x8; |
| struct w32RF64QdeQ_Scan8x81; |
| struct w32RF64QdeQ_Scan8x82; |
| struct w32RF64QdeQ_Scan8x83; |
| struct w32RF64QdeQ_Scan8x84; |
| struct w32RF64QdeQ_Scan8x85; |
| struct w32RF64QdeQ_Scan8x86; |
| struct w32RF64QdeQ_Scan8x87; |
| struct w32RF64QdeQ_Scan8x88; |
| struct w32RF64QdeQ_Scan8x89; |
| struct w32RF64QdeQ_Scan8x810; |
| struct w32RF64QdeQ_Scan8x811; |
| struct w32RF64QdeQ_Scan8x812; |
| struct w32RF64QdeQ_Scan8x813; |
| struct w32RF64QdeQ_Scan8x814; |
| struct w32RF64QdeQ_Scan8x815; |
| }; |
| } TRF64QdeQ_Scan8x8; |
| typedef union TRF64QdeQ_Scan4x4 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Scan4x4; |
| struct w32RF64QdeQ_Scan4x41; |
| }; |
| } TRF64QdeQ_Scan4x4; |
| typedef union TRF64QdeQ_Param1 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Param1; |
| struct w32RF64QdeQ_Param11; |
| }; |
| } TRF64QdeQ_Param1; |
| typedef union TRF64QdeQ_Param2 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Param2; |
| struct w32RF64QdeQ_Param21; |
| }; |
| } TRF64QdeQ_Param2; |
| typedef union TRF64QdeQ_Param3 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Param3; |
| struct w32RF64QdeQ_Param31; |
| }; |
| } TRF64QdeQ_Param3; |
| typedef union TRF64QdeQ_Param4 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64QdeQ_Param4; |
| }; |
| } TRF64QdeQ_Param4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64QdeQ_drvrd(SIE_RF64QdeQ *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64QdeQ_drvwr(SIE_RF64QdeQ *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64QdeQ_reset(SIE_RF64QdeQ *p); |
| SIGN32 RF64QdeQ_cmp (SIE_RF64QdeQ *p, SIE_RF64QdeQ *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64QdeQ_check(p,pie,pfx,hLOG) RF64QdeQ_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64QdeQ_print(p, pfx,hLOG) RF64QdeQ_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64QdeQ |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CoeffCmd (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 TotalCoeff |
| /// ### |
| /// * The number of non-zero transform |
| /// * coefficients in a 4x4 block |
| /// ### |
| /// %unsigned 1 SignTrailOne_0i |
| /// %unsigned 1 SignTrailOne_1i |
| /// %unsigned 1 SignTrailOne_2i |
| /// ### |
| /// * Sign of trailing ones. ST1[2:0] |
| /// * ST1[0] corresponds to sign of last trailing1 in the scan of transform coeffcients, St1[1] corresponds to sign of last but one trailing1 and ST1[2] corresponds to third trailing1. |
| /// ### |
| /// %unsigned 2 TrailOnes |
| /// ### |
| /// * Number of trailing ones. A trailing one transform coefficient is one of up to three consecutive non-zero transform coefficient levels having an absolute value equal to 1 at the end of a scan of non-zero transform coefficient levels. |
| /// ### |
| /// %unsigned 6 ZeroCoeff |
| /// ### |
| /// * The total number of zero-valued transform coefficients that are located before the position of the last non-zero transform coefficient level in a scan of transform coefficient levels. |
| /// ### |
| /// %unsigned 5 TotalCoeff1 |
| /// %unsigned 1 SignTrailOne1_0i |
| /// %unsigned 1 SignTrailOne1_1i |
| /// %unsigned 1 SignTrailOne1_2i |
| /// %unsigned 2 TrailOnes1 |
| /// %unsigned 6 ZeroCoeff1 |
| /// ### |
| /// * One more set to construct one 32-bit data |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CoeffCmd |
| #define h_CoeffCmd (){} |
| |
| #define BA_CoeffCmd_TotalCoeff 0x0000 |
| #define B16CoeffCmd_TotalCoeff 0x0000 |
| #define LSb32CoeffCmd_TotalCoeff 0 |
| #define LSb16CoeffCmd_TotalCoeff 0 |
| #define bCoeffCmd_TotalCoeff 5 |
| #define MSK32CoeffCmd_TotalCoeff 0x0000001F |
| |
| #define BA_CoeffCmd_SignTrailOne_0i 0x0000 |
| #define B16CoeffCmd_SignTrailOne_0i 0x0000 |
| #define LSb32CoeffCmd_SignTrailOne_0i 5 |
| #define LSb16CoeffCmd_SignTrailOne_0i 5 |
| #define bCoeffCmd_SignTrailOne_0i 1 |
| #define MSK32CoeffCmd_SignTrailOne_0i 0x00000020 |
| |
| #define BA_CoeffCmd_SignTrailOne_1i 0x0000 |
| #define B16CoeffCmd_SignTrailOne_1i 0x0000 |
| #define LSb32CoeffCmd_SignTrailOne_1i 6 |
| #define LSb16CoeffCmd_SignTrailOne_1i 6 |
| #define bCoeffCmd_SignTrailOne_1i 1 |
| #define MSK32CoeffCmd_SignTrailOne_1i 0x00000040 |
| |
| #define BA_CoeffCmd_SignTrailOne_2i 0x0000 |
| #define B16CoeffCmd_SignTrailOne_2i 0x0000 |
| #define LSb32CoeffCmd_SignTrailOne_2i 7 |
| #define LSb16CoeffCmd_SignTrailOne_2i 7 |
| #define bCoeffCmd_SignTrailOne_2i 1 |
| #define MSK32CoeffCmd_SignTrailOne_2i 0x00000080 |
| |
| #define BA_CoeffCmd_TrailOnes 0x0001 |
| #define B16CoeffCmd_TrailOnes 0x0000 |
| #define LSb32CoeffCmd_TrailOnes 8 |
| #define LSb16CoeffCmd_TrailOnes 8 |
| #define bCoeffCmd_TrailOnes 2 |
| #define MSK32CoeffCmd_TrailOnes 0x00000300 |
| |
| #define BA_CoeffCmd_ZeroCoeff 0x0001 |
| #define B16CoeffCmd_ZeroCoeff 0x0000 |
| #define LSb32CoeffCmd_ZeroCoeff 10 |
| #define LSb16CoeffCmd_ZeroCoeff 10 |
| #define bCoeffCmd_ZeroCoeff 6 |
| #define MSK32CoeffCmd_ZeroCoeff 0x0000FC00 |
| |
| #define BA_CoeffCmd_TotalCoeff1 0x0002 |
| #define B16CoeffCmd_TotalCoeff1 0x0002 |
| #define LSb32CoeffCmd_TotalCoeff1 16 |
| #define LSb16CoeffCmd_TotalCoeff1 0 |
| #define bCoeffCmd_TotalCoeff1 5 |
| #define MSK32CoeffCmd_TotalCoeff1 0x001F0000 |
| |
| #define BA_CoeffCmd_SignTrailOne1_0i 0x0002 |
| #define B16CoeffCmd_SignTrailOne1_0i 0x0002 |
| #define LSb32CoeffCmd_SignTrailOne1_0i 21 |
| #define LSb16CoeffCmd_SignTrailOne1_0i 5 |
| #define bCoeffCmd_SignTrailOne1_0i 1 |
| #define MSK32CoeffCmd_SignTrailOne1_0i 0x00200000 |
| |
| #define BA_CoeffCmd_SignTrailOne1_1i 0x0002 |
| #define B16CoeffCmd_SignTrailOne1_1i 0x0002 |
| #define LSb32CoeffCmd_SignTrailOne1_1i 22 |
| #define LSb16CoeffCmd_SignTrailOne1_1i 6 |
| #define bCoeffCmd_SignTrailOne1_1i 1 |
| #define MSK32CoeffCmd_SignTrailOne1_1i 0x00400000 |
| |
| #define BA_CoeffCmd_SignTrailOne1_2i 0x0002 |
| #define B16CoeffCmd_SignTrailOne1_2i 0x0002 |
| #define LSb32CoeffCmd_SignTrailOne1_2i 23 |
| #define LSb16CoeffCmd_SignTrailOne1_2i 7 |
| #define bCoeffCmd_SignTrailOne1_2i 1 |
| #define MSK32CoeffCmd_SignTrailOne1_2i 0x00800000 |
| |
| #define BA_CoeffCmd_TrailOnes1 0x0003 |
| #define B16CoeffCmd_TrailOnes1 0x0002 |
| #define LSb32CoeffCmd_TrailOnes1 24 |
| #define LSb16CoeffCmd_TrailOnes1 8 |
| #define bCoeffCmd_TrailOnes1 2 |
| #define MSK32CoeffCmd_TrailOnes1 0x03000000 |
| |
| #define BA_CoeffCmd_ZeroCoeff1 0x0003 |
| #define B16CoeffCmd_ZeroCoeff1 0x0002 |
| #define LSb32CoeffCmd_ZeroCoeff1 26 |
| #define LSb16CoeffCmd_ZeroCoeff1 10 |
| #define bCoeffCmd_ZeroCoeff1 6 |
| #define MSK32CoeffCmd_ZeroCoeff1 0xFC000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CoeffCmd { |
| /////////////////////////////////////////////////////////// |
| #define GET32CoeffCmd_TotalCoeff(r32) _BFGET_(r32, 4, 0) |
| #define SET32CoeffCmd_TotalCoeff(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16CoeffCmd_TotalCoeff(r16) _BFGET_(r16, 4, 0) |
| #define SET16CoeffCmd_TotalCoeff(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32CoeffCmd_SignTrailOne_0i(r32) _BFGET_(r32, 5, 5) |
| #define SET32CoeffCmd_SignTrailOne_0i(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16CoeffCmd_SignTrailOne_0i(r16) _BFGET_(r16, 5, 5) |
| #define SET16CoeffCmd_SignTrailOne_0i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32CoeffCmd_SignTrailOne_1i(r32) _BFGET_(r32, 6, 6) |
| #define SET32CoeffCmd_SignTrailOne_1i(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16CoeffCmd_SignTrailOne_1i(r16) _BFGET_(r16, 6, 6) |
| #define SET16CoeffCmd_SignTrailOne_1i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32CoeffCmd_SignTrailOne_2i(r32) _BFGET_(r32, 7, 7) |
| #define SET32CoeffCmd_SignTrailOne_2i(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16CoeffCmd_SignTrailOne_2i(r16) _BFGET_(r16, 7, 7) |
| #define SET16CoeffCmd_SignTrailOne_2i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32CoeffCmd_TrailOnes(r32) _BFGET_(r32, 9, 8) |
| #define SET32CoeffCmd_TrailOnes(r32,v) _BFSET_(r32, 9, 8,v) |
| #define GET16CoeffCmd_TrailOnes(r16) _BFGET_(r16, 9, 8) |
| #define SET16CoeffCmd_TrailOnes(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32CoeffCmd_ZeroCoeff(r32) _BFGET_(r32,15,10) |
| #define SET32CoeffCmd_ZeroCoeff(r32,v) _BFSET_(r32,15,10,v) |
| #define GET16CoeffCmd_ZeroCoeff(r16) _BFGET_(r16,15,10) |
| #define SET16CoeffCmd_ZeroCoeff(r16,v) _BFSET_(r16,15,10,v) |
| |
| #define GET32CoeffCmd_TotalCoeff1(r32) _BFGET_(r32,20,16) |
| #define SET32CoeffCmd_TotalCoeff1(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16CoeffCmd_TotalCoeff1(r16) _BFGET_(r16, 4, 0) |
| #define SET16CoeffCmd_TotalCoeff1(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32CoeffCmd_SignTrailOne1_0i(r32) _BFGET_(r32,21,21) |
| #define SET32CoeffCmd_SignTrailOne1_0i(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16CoeffCmd_SignTrailOne1_0i(r16) _BFGET_(r16, 5, 5) |
| #define SET16CoeffCmd_SignTrailOne1_0i(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32CoeffCmd_SignTrailOne1_1i(r32) _BFGET_(r32,22,22) |
| #define SET32CoeffCmd_SignTrailOne1_1i(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16CoeffCmd_SignTrailOne1_1i(r16) _BFGET_(r16, 6, 6) |
| #define SET16CoeffCmd_SignTrailOne1_1i(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32CoeffCmd_SignTrailOne1_2i(r32) _BFGET_(r32,23,23) |
| #define SET32CoeffCmd_SignTrailOne1_2i(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16CoeffCmd_SignTrailOne1_2i(r16) _BFGET_(r16, 7, 7) |
| #define SET16CoeffCmd_SignTrailOne1_2i(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32CoeffCmd_TrailOnes1(r32) _BFGET_(r32,25,24) |
| #define SET32CoeffCmd_TrailOnes1(r32,v) _BFSET_(r32,25,24,v) |
| #define GET16CoeffCmd_TrailOnes1(r16) _BFGET_(r16, 9, 8) |
| #define SET16CoeffCmd_TrailOnes1(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32CoeffCmd_ZeroCoeff1(r32) _BFGET_(r32,31,26) |
| #define SET32CoeffCmd_ZeroCoeff1(r32,v) _BFSET_(r32,31,26,v) |
| #define GET16CoeffCmd_ZeroCoeff1(r16) _BFGET_(r16,15,10) |
| #define SET16CoeffCmd_ZeroCoeff1(r16,v) _BFSET_(r16,15,10,v) |
| |
| UNSG32 u_TotalCoeff : 5; |
| UNSG32 u_SignTrailOne_0i : 1; |
| UNSG32 u_SignTrailOne_1i : 1; |
| UNSG32 u_SignTrailOne_2i : 1; |
| UNSG32 u_TrailOnes : 2; |
| UNSG32 u_ZeroCoeff : 6; |
| UNSG32 u_TotalCoeff1 : 5; |
| UNSG32 u_SignTrailOne1_0i : 1; |
| UNSG32 u_SignTrailOne1_1i : 1; |
| UNSG32 u_SignTrailOne1_2i : 1; |
| UNSG32 u_TrailOnes1 : 2; |
| UNSG32 u_ZeroCoeff1 : 6; |
| /////////////////////////////////////////////////////////// |
| } SIE_CoeffCmd; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CoeffCmd_drvrd(SIE_CoeffCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CoeffCmd_drvwr(SIE_CoeffCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CoeffCmd_reset(SIE_CoeffCmd *p); |
| SIGN32 CoeffCmd_cmp (SIE_CoeffCmd *p, SIE_CoeffCmd *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CoeffCmd_check(p,pie,pfx,hLOG) CoeffCmd_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CoeffCmd_print(p, pfx,hLOG) CoeffCmd_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CoeffCmd |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQCoeffCmdResp (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 v |
| /// $CoeffCmd v REG [2] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQCoeffCmdResp |
| #define h_QdeQCoeffCmdResp (){} |
| |
| #define RA_QdeQCoeffCmdResp_v 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQCoeffCmdResp { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_v[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQCoeffCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQCoeffCmdResp_drvrd(SIE_QdeQCoeffCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQCoeffCmdResp_drvwr(SIE_QdeQCoeffCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQCoeffCmdResp_reset(SIE_QdeQCoeffCmdResp *p); |
| SIGN32 QdeQCoeffCmdResp_cmp (SIE_QdeQCoeffCmdResp *p, SIE_QdeQCoeffCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQCoeffCmdResp_check(p,pie,pfx,hLOG) QdeQCoeffCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQCoeffCmdResp_print(p, pfx,hLOG) QdeQCoeffCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQCoeffCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CoeffCnt (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 val |
| /// %% 24 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 8b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CoeffCnt |
| #define h_CoeffCnt (){} |
| |
| #define BA_CoeffCnt_val 0x0000 |
| #define B16CoeffCnt_val 0x0000 |
| #define LSb32CoeffCnt_val 0 |
| #define LSb16CoeffCnt_val 0 |
| #define bCoeffCnt_val 8 |
| #define MSK32CoeffCnt_val 0x000000FF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CoeffCnt { |
| /////////////////////////////////////////////////////////// |
| #define GET32CoeffCnt_val(r32) _BFGET_(r32, 7, 0) |
| #define SET32CoeffCnt_val(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16CoeffCnt_val(r16) _BFGET_(r16, 7, 0) |
| #define SET16CoeffCnt_val(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| UNSG32 u_val : 8; |
| UNSG32 RSVDx0_b8 : 24; |
| /////////////////////////////////////////////////////////// |
| } SIE_CoeffCnt; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CoeffCnt_drvrd(SIE_CoeffCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CoeffCnt_drvwr(SIE_CoeffCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CoeffCnt_reset(SIE_CoeffCnt *p); |
| SIGN32 CoeffCnt_cmp (SIE_CoeffCnt *p, SIE_CoeffCnt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CoeffCnt_check(p,pie,pfx,hLOG) CoeffCnt_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CoeffCnt_print(p, pfx,hLOG) CoeffCnt_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CoeffCnt |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQCoeffCntResp (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 v |
| /// $CoeffCnt v REG [8] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 32B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQCoeffCntResp |
| #define h_QdeQCoeffCntResp (){} |
| |
| #define RA_QdeQCoeffCntResp_v 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQCoeffCntResp { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCnt ie_v[8]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQCoeffCntResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQCoeffCntResp_drvrd(SIE_QdeQCoeffCntResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQCoeffCntResp_drvwr(SIE_QdeQCoeffCntResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQCoeffCntResp_reset(SIE_QdeQCoeffCntResp *p); |
| SIGN32 QdeQCoeffCntResp_cmp (SIE_QdeQCoeffCntResp *p, SIE_QdeQCoeffCntResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQCoeffCntResp_check(p,pie,pfx,hLOG) QdeQCoeffCntResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQCoeffCntResp_print(p, pfx,hLOG) QdeQCoeffCntResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQCoeffCntResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQStatCmdResp (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 BitCnt |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQStatCmdResp |
| #define h_QdeQStatCmdResp (){} |
| |
| #define BA_QdeQStatCmdResp_BitCnt 0x0000 |
| #define B16QdeQStatCmdResp_BitCnt 0x0000 |
| #define LSb32QdeQStatCmdResp_BitCnt 0 |
| #define LSb16QdeQStatCmdResp_BitCnt 0 |
| #define bQdeQStatCmdResp_BitCnt 32 |
| #define MSK32QdeQStatCmdResp_BitCnt 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQStatCmdResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32QdeQStatCmdResp_BitCnt(r32) _BFGET_(r32,31, 0) |
| #define SET32QdeQStatCmdResp_BitCnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_BitCnt : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQStatCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQStatCmdResp_drvrd(SIE_QdeQStatCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQStatCmdResp_drvwr(SIE_QdeQStatCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQStatCmdResp_reset(SIE_QdeQStatCmdResp *p); |
| SIGN32 QdeQStatCmdResp_cmp (SIE_QdeQStatCmdResp *p, SIE_QdeQStatCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQStatCmdResp_check(p,pie,pfx,hLOG) QdeQStatCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQStatCmdResp_print(p, pfx,hLOG) QdeQStatCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQStatCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQSsdCmdResp (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 SSD_L |
| /// %unsigned 8 SSD_H |
| /// %% 24 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 40b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQSsdCmdResp |
| #define h_QdeQSsdCmdResp (){} |
| |
| #define BA_QdeQSsdCmdResp_SSD_L 0x0000 |
| #define B16QdeQSsdCmdResp_SSD_L 0x0000 |
| #define LSb32QdeQSsdCmdResp_SSD_L 0 |
| #define LSb16QdeQSsdCmdResp_SSD_L 0 |
| #define bQdeQSsdCmdResp_SSD_L 32 |
| #define MSK32QdeQSsdCmdResp_SSD_L 0xFFFFFFFF |
| |
| #define BA_QdeQSsdCmdResp_SSD_H 0x0004 |
| #define B16QdeQSsdCmdResp_SSD_H 0x0004 |
| #define LSb32QdeQSsdCmdResp_SSD_H 0 |
| #define LSb16QdeQSsdCmdResp_SSD_H 0 |
| #define bQdeQSsdCmdResp_SSD_H 8 |
| #define MSK32QdeQSsdCmdResp_SSD_H 0x000000FF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQSsdCmdResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32QdeQSsdCmdResp_SSD_L(r32) _BFGET_(r32,31, 0) |
| #define SET32QdeQSsdCmdResp_SSD_L(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_SSD_L : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32QdeQSsdCmdResp_SSD_H(r32) _BFGET_(r32, 7, 0) |
| #define SET32QdeQSsdCmdResp_SSD_H(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16QdeQSsdCmdResp_SSD_H(r16) _BFGET_(r16, 7, 0) |
| #define SET16QdeQSsdCmdResp_SSD_H(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| UNSG32 u_SSD_H : 8; |
| UNSG32 RSVDx4_b8 : 24; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQSsdCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQSsdCmdResp_drvrd(SIE_QdeQSsdCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQSsdCmdResp_drvwr(SIE_QdeQSsdCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQSsdCmdResp_reset(SIE_QdeQSsdCmdResp *p); |
| SIGN32 QdeQSsdCmdResp_cmp (SIE_QdeQSsdCmdResp *p, SIE_QdeQSsdCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQSsdCmdResp_check(p,pie,pfx,hLOG) QdeQSsdCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQSsdCmdResp_print(p, pfx,hLOG) QdeQSsdCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQSsdCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQCBPCmdResp (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 CBPDC |
| /// %unsigned 6 CBP |
| /// %unsigned 16 CBFy |
| /// %unsigned 4 CBFu |
| /// %unsigned 4 CBFv |
| /// %unsigned 1 CBF16x16I |
| /// %unsigned 1 CBF4x4U |
| /// %unsigned 1 CBF4x4V |
| /// %% 25 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 39b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQCBPCmdResp |
| #define h_QdeQCBPCmdResp (){} |
| |
| #define BA_QdeQCBPCmdResp_CBPDC 0x0000 |
| #define B16QdeQCBPCmdResp_CBPDC 0x0000 |
| #define LSb32QdeQCBPCmdResp_CBPDC 0 |
| #define LSb16QdeQCBPCmdResp_CBPDC 0 |
| #define bQdeQCBPCmdResp_CBPDC 6 |
| #define MSK32QdeQCBPCmdResp_CBPDC 0x0000003F |
| |
| #define BA_QdeQCBPCmdResp_CBP 0x0000 |
| #define B16QdeQCBPCmdResp_CBP 0x0000 |
| #define LSb32QdeQCBPCmdResp_CBP 6 |
| #define LSb16QdeQCBPCmdResp_CBP 6 |
| #define bQdeQCBPCmdResp_CBP 6 |
| #define MSK32QdeQCBPCmdResp_CBP 0x00000FC0 |
| |
| #define BA_QdeQCBPCmdResp_CBFy 0x0001 |
| #define B16QdeQCBPCmdResp_CBFy 0x0000 |
| #define LSb32QdeQCBPCmdResp_CBFy 12 |
| #define LSb16QdeQCBPCmdResp_CBFy 12 |
| #define bQdeQCBPCmdResp_CBFy 16 |
| #define MSK32QdeQCBPCmdResp_CBFy 0x0FFFF000 |
| |
| #define BA_QdeQCBPCmdResp_CBFu 0x0003 |
| #define B16QdeQCBPCmdResp_CBFu 0x0002 |
| #define LSb32QdeQCBPCmdResp_CBFu 28 |
| #define LSb16QdeQCBPCmdResp_CBFu 12 |
| #define bQdeQCBPCmdResp_CBFu 4 |
| #define MSK32QdeQCBPCmdResp_CBFu 0xF0000000 |
| |
| #define BA_QdeQCBPCmdResp_CBFv 0x0004 |
| #define B16QdeQCBPCmdResp_CBFv 0x0004 |
| #define LSb32QdeQCBPCmdResp_CBFv 0 |
| #define LSb16QdeQCBPCmdResp_CBFv 0 |
| #define bQdeQCBPCmdResp_CBFv 4 |
| #define MSK32QdeQCBPCmdResp_CBFv 0x0000000F |
| |
| #define BA_QdeQCBPCmdResp_CBF16x16I 0x0004 |
| #define B16QdeQCBPCmdResp_CBF16x16I 0x0004 |
| #define LSb32QdeQCBPCmdResp_CBF16x16I 4 |
| #define LSb16QdeQCBPCmdResp_CBF16x16I 4 |
| #define bQdeQCBPCmdResp_CBF16x16I 1 |
| #define MSK32QdeQCBPCmdResp_CBF16x16I 0x00000010 |
| |
| #define BA_QdeQCBPCmdResp_CBF4x4U 0x0004 |
| #define B16QdeQCBPCmdResp_CBF4x4U 0x0004 |
| #define LSb32QdeQCBPCmdResp_CBF4x4U 5 |
| #define LSb16QdeQCBPCmdResp_CBF4x4U 5 |
| #define bQdeQCBPCmdResp_CBF4x4U 1 |
| #define MSK32QdeQCBPCmdResp_CBF4x4U 0x00000020 |
| |
| #define BA_QdeQCBPCmdResp_CBF4x4V 0x0004 |
| #define B16QdeQCBPCmdResp_CBF4x4V 0x0004 |
| #define LSb32QdeQCBPCmdResp_CBF4x4V 6 |
| #define LSb16QdeQCBPCmdResp_CBF4x4V 6 |
| #define bQdeQCBPCmdResp_CBF4x4V 1 |
| #define MSK32QdeQCBPCmdResp_CBF4x4V 0x00000040 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQCBPCmdResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32QdeQCBPCmdResp_CBPDC(r32) _BFGET_(r32, 5, 0) |
| #define SET32QdeQCBPCmdResp_CBPDC(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16QdeQCBPCmdResp_CBPDC(r16) _BFGET_(r16, 5, 0) |
| #define SET16QdeQCBPCmdResp_CBPDC(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32QdeQCBPCmdResp_CBP(r32) _BFGET_(r32,11, 6) |
| #define SET32QdeQCBPCmdResp_CBP(r32,v) _BFSET_(r32,11, 6,v) |
| #define GET16QdeQCBPCmdResp_CBP(r16) _BFGET_(r16,11, 6) |
| #define SET16QdeQCBPCmdResp_CBP(r16,v) _BFSET_(r16,11, 6,v) |
| |
| #define GET32QdeQCBPCmdResp_CBFy(r32) _BFGET_(r32,27,12) |
| #define SET32QdeQCBPCmdResp_CBFy(r32,v) _BFSET_(r32,27,12,v) |
| |
| #define GET32QdeQCBPCmdResp_CBFu(r32) _BFGET_(r32,31,28) |
| #define SET32QdeQCBPCmdResp_CBFu(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16QdeQCBPCmdResp_CBFu(r16) _BFGET_(r16,15,12) |
| #define SET16QdeQCBPCmdResp_CBFu(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_CBPDC : 6; |
| UNSG32 u_CBP : 6; |
| UNSG32 u_CBFy : 16; |
| UNSG32 u_CBFu : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32QdeQCBPCmdResp_CBFv(r32) _BFGET_(r32, 3, 0) |
| #define SET32QdeQCBPCmdResp_CBFv(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16QdeQCBPCmdResp_CBFv(r16) _BFGET_(r16, 3, 0) |
| #define SET16QdeQCBPCmdResp_CBFv(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32QdeQCBPCmdResp_CBF16x16I(r32) _BFGET_(r32, 4, 4) |
| #define SET32QdeQCBPCmdResp_CBF16x16I(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16QdeQCBPCmdResp_CBF16x16I(r16) _BFGET_(r16, 4, 4) |
| #define SET16QdeQCBPCmdResp_CBF16x16I(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32QdeQCBPCmdResp_CBF4x4U(r32) _BFGET_(r32, 5, 5) |
| #define SET32QdeQCBPCmdResp_CBF4x4U(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16QdeQCBPCmdResp_CBF4x4U(r16) _BFGET_(r16, 5, 5) |
| #define SET16QdeQCBPCmdResp_CBF4x4U(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32QdeQCBPCmdResp_CBF4x4V(r32) _BFGET_(r32, 6, 6) |
| #define SET32QdeQCBPCmdResp_CBF4x4V(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16QdeQCBPCmdResp_CBF4x4V(r16) _BFGET_(r16, 6, 6) |
| #define SET16QdeQCBPCmdResp_CBF4x4V(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| UNSG32 u_CBFv : 4; |
| UNSG32 u_CBF16x16I : 1; |
| UNSG32 u_CBF4x4U : 1; |
| UNSG32 u_CBF4x4V : 1; |
| UNSG32 RSVDx4_b7 : 25; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQCBPCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQCBPCmdResp_drvrd(SIE_QdeQCBPCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQCBPCmdResp_drvwr(SIE_QdeQCBPCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQCBPCmdResp_reset(SIE_QdeQCBPCmdResp *p); |
| SIGN32 QdeQCBPCmdResp_cmp (SIE_QdeQCBPCmdResp *p, SIE_QdeQCBPCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQCBPCmdResp_check(p,pie,pfx,hLOG) QdeQCBPCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQCBPCmdResp_print(p, pfx,hLOG) QdeQCBPCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQCBPCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROCmd flat (8,2) |
| /// ### |
| /// * IPRO Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Category |
| /// : Function 0x0 |
| /// ### |
| /// * Functional command to do actually IPRO work. |
| /// ### |
| /// : Coeff 0x1 |
| /// ### |
| /// * VLC statistics for coefficients and trailing ones |
| /// ### |
| /// : CBP 0x2 |
| /// ### |
| /// * CBP, CBPDC, CBF, etc. |
| /// ### |
| /// : RDMBResult 0x3 |
| /// ### |
| /// * RDMB result: Best intra/inter prediction mode and best transform type for current MB. |
| /// ### |
| /// : RD16x16Result 0x4 |
| /// ### |
| /// * RD16x16 result: Best intra/inter prediction mode of Luma part of current MB. |
| /// ### |
| /// : RD8x8Result 0x5 |
| /// ### |
| /// * RD8x8 result: Best intra/inter prediction mode of current 8x8 partition. |
| /// ### |
| /// : RD4x4Result 0x6 |
| /// ### |
| /// * RD4x4 result: Best intra/inter prediction mode of current 4x4 partition. |
| /// ### |
| /// : RDUVResult 0x7 |
| /// ### |
| /// * RDUV result: Best intra/inter prediction mode of current UV partition. |
| /// ### |
| /// : BinSSDMB 0x8 |
| /// ### |
| /// * Get bin count and SSD collected in trial rounding quantization. |
| /// ### |
| /// : WrRF 0xF |
| /// ### |
| /// * program “RF64”, refer command WrRF for the bitfield definition. |
| /// ### |
| /// %unsigned 6 CandidateTag |
| /// ### |
| /// * tag to identify current RD trial which may have different predictor, QP etc. |
| /// ### |
| /// %unsigned 1 ForceZero |
| /// ### |
| /// * Specify if QiQTC and HQiHQ primitive force quantization result to 0. |
| /// ### |
| /// %unsigned 1 SkipMV |
| /// ### |
| /// * Indicate if current trial is skipped block trial. |
| /// ### |
| /// %unsigned 2 AltPredBufId |
| /// ### |
| /// * Specify which alternate predictor buffer is used for CT4x4 or CT8x8 primitive if PredBufId is 1. |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %unsigned 16 MoreBits |
| /// ### |
| /// * Bit count adjustment to be multiplied by md_lambda and added to score in RD primitives. |
| /// ### |
| /// %unsigned 10 StartAddr |
| /// ### |
| /// * Address of first primitive to execute |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// %unsigned 10 EndAddr |
| /// ### |
| /// * Address of last primitive to execute |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROCmd |
| #define h_IPROCmd (){} |
| |
| #define BA_IPROCmd_Category 0x0000 |
| #define B16IPROCmd_Category 0x0000 |
| #define LSb32IPROCmd_Category 0 |
| #define LSb16IPROCmd_Category 0 |
| #define bIPROCmd_Category 4 |
| #define MSK32IPROCmd_Category 0x0000000F |
| #define IPROCmd_Category_Function 0x0 |
| #define IPROCmd_Category_Coeff 0x1 |
| #define IPROCmd_Category_CBP 0x2 |
| #define IPROCmd_Category_RDMBResult 0x3 |
| #define IPROCmd_Category_RD16x16Result 0x4 |
| #define IPROCmd_Category_RD8x8Result 0x5 |
| #define IPROCmd_Category_RD4x4Result 0x6 |
| #define IPROCmd_Category_RDUVResult 0x7 |
| #define IPROCmd_Category_BinSSDMB 0x8 |
| #define IPROCmd_Category_WrRF 0xF |
| |
| #define BA_IPROCmd_CandidateTag 0x0000 |
| #define B16IPROCmd_CandidateTag 0x0000 |
| #define LSb32IPROCmd_CandidateTag 4 |
| #define LSb16IPROCmd_CandidateTag 4 |
| #define bIPROCmd_CandidateTag 6 |
| #define MSK32IPROCmd_CandidateTag 0x000003F0 |
| |
| #define BA_IPROCmd_ForceZero 0x0001 |
| #define B16IPROCmd_ForceZero 0x0000 |
| #define LSb32IPROCmd_ForceZero 10 |
| #define LSb16IPROCmd_ForceZero 10 |
| #define bIPROCmd_ForceZero 1 |
| #define MSK32IPROCmd_ForceZero 0x00000400 |
| |
| #define BA_IPROCmd_SkipMV 0x0001 |
| #define B16IPROCmd_SkipMV 0x0000 |
| #define LSb32IPROCmd_SkipMV 11 |
| #define LSb16IPROCmd_SkipMV 11 |
| #define bIPROCmd_SkipMV 1 |
| #define MSK32IPROCmd_SkipMV 0x00000800 |
| |
| #define BA_IPROCmd_AltPredBufId 0x0001 |
| #define B16IPROCmd_AltPredBufId 0x0000 |
| #define LSb32IPROCmd_AltPredBufId 12 |
| #define LSb16IPROCmd_AltPredBufId 12 |
| #define bIPROCmd_AltPredBufId 2 |
| #define MSK32IPROCmd_AltPredBufId 0x00003000 |
| |
| #define BA_IPROCmd_MoreBits 0x0002 |
| #define B16IPROCmd_MoreBits 0x0002 |
| #define LSb32IPROCmd_MoreBits 16 |
| #define LSb16IPROCmd_MoreBits 0 |
| #define bIPROCmd_MoreBits 16 |
| #define MSK32IPROCmd_MoreBits 0xFFFF0000 |
| |
| #define BA_IPROCmd_StartAddr 0x0004 |
| #define B16IPROCmd_StartAddr 0x0004 |
| #define LSb32IPROCmd_StartAddr 0 |
| #define LSb16IPROCmd_StartAddr 0 |
| #define bIPROCmd_StartAddr 10 |
| #define MSK32IPROCmd_StartAddr 0x000003FF |
| |
| #define BA_IPROCmd_EndAddr 0x0006 |
| #define B16IPROCmd_EndAddr 0x0006 |
| #define LSb32IPROCmd_EndAddr 16 |
| #define LSb16IPROCmd_EndAddr 0 |
| #define bIPROCmd_EndAddr 10 |
| #define MSK32IPROCmd_EndAddr 0x03FF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROCmd { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPROCmd_Category(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPROCmd_Category(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPROCmd_Category(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPROCmd_Category(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPROCmd_CandidateTag(r32) _BFGET_(r32, 9, 4) |
| #define SET32IPROCmd_CandidateTag(r32,v) _BFSET_(r32, 9, 4,v) |
| #define GET16IPROCmd_CandidateTag(r16) _BFGET_(r16, 9, 4) |
| #define SET16IPROCmd_CandidateTag(r16,v) _BFSET_(r16, 9, 4,v) |
| |
| #define GET32IPROCmd_ForceZero(r32) _BFGET_(r32,10,10) |
| #define SET32IPROCmd_ForceZero(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16IPROCmd_ForceZero(r16) _BFGET_(r16,10,10) |
| #define SET16IPROCmd_ForceZero(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32IPROCmd_SkipMV(r32) _BFGET_(r32,11,11) |
| #define SET32IPROCmd_SkipMV(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16IPROCmd_SkipMV(r16) _BFGET_(r16,11,11) |
| #define SET16IPROCmd_SkipMV(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32IPROCmd_AltPredBufId(r32) _BFGET_(r32,13,12) |
| #define SET32IPROCmd_AltPredBufId(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16IPROCmd_AltPredBufId(r16) _BFGET_(r16,13,12) |
| #define SET16IPROCmd_AltPredBufId(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32IPROCmd_MoreBits(r32) _BFGET_(r32,31,16) |
| #define SET32IPROCmd_MoreBits(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16IPROCmd_MoreBits(r16) _BFGET_(r16,15, 0) |
| #define SET16IPROCmd_MoreBits(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_Category : 4; |
| UNSG32 u_CandidateTag : 6; |
| UNSG32 u_ForceZero : 1; |
| UNSG32 u_SkipMV : 1; |
| UNSG32 u_AltPredBufId : 2; |
| UNSG32 RSVDx0_b14 : 2; |
| UNSG32 u_MoreBits : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32IPROCmd_StartAddr(r32) _BFGET_(r32, 9, 0) |
| #define SET32IPROCmd_StartAddr(r32,v) _BFSET_(r32, 9, 0,v) |
| #define GET16IPROCmd_StartAddr(r16) _BFGET_(r16, 9, 0) |
| #define SET16IPROCmd_StartAddr(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| #define GET32IPROCmd_EndAddr(r32) _BFGET_(r32,25,16) |
| #define SET32IPROCmd_EndAddr(r32,v) _BFSET_(r32,25,16,v) |
| #define GET16IPROCmd_EndAddr(r16) _BFGET_(r16, 9, 0) |
| #define SET16IPROCmd_EndAddr(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| UNSG32 u_StartAddr : 10; |
| UNSG32 RSVDx4_b10 : 6; |
| UNSG32 u_EndAddr : 10; |
| UNSG32 RSVDx4_b26 : 6; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROCmd; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROCmd_drvrd(SIE_IPROCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROCmd_drvwr(SIE_IPROCmd *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROCmd_reset(SIE_IPROCmd *p); |
| SIGN32 IPROCmd_cmp (SIE_IPROCmd *p, SIE_IPROCmd *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROCmd_check(p,pie,pfx,hLOG) IPROCmd_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROCmd_print(p, pfx,hLOG) IPROCmd_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROCmd |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROCmdWrRF flat (8,2) |
| /// ### |
| /// * IPRO Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Category |
| /// : WrRF 0xF |
| /// ### |
| /// * program “RF64”, refer command WrRF for the bitfield definition. |
| /// ### |
| /// %unsigned 28 addr |
| /// ### |
| /// * register address inside “RF64” |
| /// ### |
| /// %unsigned 32 dat |
| /// ### |
| /// * register value programed to the “RF64” |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROCmdWrRF |
| #define h_IPROCmdWrRF (){} |
| |
| #define BA_IPROCmdWrRF_Category 0x0000 |
| #define B16IPROCmdWrRF_Category 0x0000 |
| #define LSb32IPROCmdWrRF_Category 0 |
| #define LSb16IPROCmdWrRF_Category 0 |
| #define bIPROCmdWrRF_Category 4 |
| #define MSK32IPROCmdWrRF_Category 0x0000000F |
| #define IPROCmdWrRF_Category_WrRF 0xF |
| |
| #define BA_IPROCmdWrRF_addr 0x0000 |
| #define B16IPROCmdWrRF_addr 0x0000 |
| #define LSb32IPROCmdWrRF_addr 4 |
| #define LSb16IPROCmdWrRF_addr 4 |
| #define bIPROCmdWrRF_addr 28 |
| #define MSK32IPROCmdWrRF_addr 0xFFFFFFF0 |
| |
| #define BA_IPROCmdWrRF_dat 0x0004 |
| #define B16IPROCmdWrRF_dat 0x0004 |
| #define LSb32IPROCmdWrRF_dat 0 |
| #define LSb16IPROCmdWrRF_dat 0 |
| #define bIPROCmdWrRF_dat 32 |
| #define MSK32IPROCmdWrRF_dat 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROCmdWrRF { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPROCmdWrRF_Category(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPROCmdWrRF_Category(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPROCmdWrRF_Category(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPROCmdWrRF_Category(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPROCmdWrRF_addr(r32) _BFGET_(r32,31, 4) |
| #define SET32IPROCmdWrRF_addr(r32,v) _BFSET_(r32,31, 4,v) |
| |
| UNSG32 u_Category : 4; |
| UNSG32 u_addr : 28; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32IPROCmdWrRF_dat(r32) _BFGET_(r32,31, 0) |
| #define SET32IPROCmdWrRF_dat(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_dat : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROCmdWrRF; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROCmdWrRF_drvrd(SIE_IPROCmdWrRF *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROCmdWrRF_drvwr(SIE_IPROCmdWrRF *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROCmdWrRF_reset(SIE_IPROCmdWrRF *p); |
| SIGN32 IPROCmdWrRF_cmp (SIE_IPROCmdWrRF *p, SIE_IPROCmdWrRF *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROCmdWrRF_check(p,pie,pfx,hLOG) IPROCmdWrRF_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROCmdWrRF_print(p, pfx,hLOG) IPROCmdWrRF_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROCmdWrRF |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FuncPrimitive flat (4,4) |
| /// ### |
| /// * Functional Primitive Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 Type |
| /// ### |
| /// * Primitive types |
| /// ### |
| /// : PCDT4x4 0x0 |
| /// : PCT4x4 0x1 |
| /// : PCDT16x16 0x2 |
| /// : PCT16x16 0x3 |
| /// : PCDT8x8 0x4 |
| /// : PCT8x8 0x5 |
| /// : PCDTUV 0x6 |
| /// : PCTUV 0x7 |
| /// : CT4x4 0x8 |
| /// : CT8x8 0x9 |
| /// : T8x8 0xA |
| /// : QiQTC4x4I 0x20 |
| /// : QiQTC4x4I16 0x21 |
| /// : QiQTC8x8I 0x22 |
| /// : QiQTC4x4IU 0x23 |
| /// : QiQTC4x4IV 0x24 |
| /// : QiQTC4x4Inter 0x25 |
| /// : QiQTC4x4InterU 0x26 |
| /// : QiQTC4x4InterV 0x27 |
| /// : QiQTC8x8Inter 0x28 |
| /// : QiQTC8x8IU 0x29 |
| /// : QiQTC8x8IV 0x2A |
| /// : QiQTC8x8InterU 0x2B |
| /// : QiQTC8x8InterV 0x2C |
| /// : HQiHQ4x4 0x40 |
| /// : HQiHQ2x2IU 0x41 |
| /// : HQiHQ2x2IV 0x42 |
| /// : HQiHQ2x2InterU 0x43 |
| /// : HQiHQ2x2InterV 0x44 |
| /// : RDMB 0x60 |
| /// : RD16x16 0x61 |
| /// : RD8x8 0x62 |
| /// : RD4x4 0x63 |
| /// : RDUV 0x64 |
| /// : RD16x16ToMB 0x65 |
| /// : RDUVToMB 0x66 |
| /// : NOP 0xA0 |
| /// : P4x4 0xC1 |
| /// : P16x16 0xC2 |
| /// : P8x8 0xC3 |
| /// : PUV 0xC4 |
| /// : iTC4x4 0xC5 |
| /// : iTC8x8 0xC6 |
| /// %unsigned 5 BlkSubblockID |
| /// ### |
| /// * Block or Subblock ID |
| /// ### |
| /// %unsigned 6 BufferID |
| /// ### |
| /// * Input or output buffer ID |
| /// ### |
| /// %unsigned 4 Mode |
| /// ### |
| /// * Intra prediction mode for PCT* primitives or partition type for RD16x16 primitive. |
| /// * Intra prediction mode for PCT* primitives |
| /// ### |
| /// : Intra_16x16_Vertical 0x0 |
| /// : Intra_16x16_Horizontal 0x1 |
| /// : Intra_16x16_DC 0x2 |
| /// : Intra_16x16_Plane 0x3 |
| /// : Intra_4x4_Vertical 0x0 |
| /// : Intra_4x4_Horizontal 0x1 |
| /// : Intra_4x4_DC 0x2 |
| /// : Intra_4x4_Diagonal_Down_Left 0x3 |
| /// : Intra_4x4_Diagonal_Down_Right 0x4 |
| /// : Intra_4x4_Vertical_Right 0x5 |
| /// : Intra_4x4_Horizontal_Down 0x6 |
| /// : Intra_4x4_Vertical_Left 0x7 |
| /// : Intra_4x4_Horizontal_Up 0x8 |
| /// : Intra_8x8_Vertical 0x0 |
| /// : Intra_8x8_Horizontal 0x1 |
| /// : Intra_8x8_DC 0x2 |
| /// : Intra_8x8_Diagonal_Down_Left 0x3 |
| /// : Intra_8x8_Diagonal_Down_Right 0x4 |
| /// : Intra_8x8_Vertical_Right 0x5 |
| /// : Intra_8x8_Horizontal_Down 0x6 |
| /// : Intra_8x8_Vertical_Left 0x7 |
| /// : Intra_8x8_Horizontal_Up 0x8 |
| /// ### |
| /// * RD16x16 partition type |
| /// ### |
| /// : PART16x16 0x0 |
| /// : PART8x8 0x1 |
| /// : PART4x4 0x2 |
| /// %unsigned 1 FinalizeRDBuf |
| /// ### |
| /// * For RD4x4 and RD8x8, indicate if final RD trial has been done on this block/subblock so PCT* can make sure final reconstructed pixel is ready in RD buffer. |
| /// * For RDMB, indicate if c_MB buffer holds the final result for RotateMBCtx. |
| /// * It is irrelevant for RD16x16 and RDUV. |
| /// ### |
| /// %unsigned 2 RecBufId |
| /// ### |
| /// * For RD and QiQTC primitives, specify which QiQTC buffer to use. |
| /// * For other primitives, specify the buffer to store reconstructed pixels. |
| /// ### |
| /// : ID_QiQTC0 0x0 |
| /// : ID_QiQTC1 0x1 |
| /// : ID_CYNxN 0x2 |
| /// %unsigned 1 PredBufId |
| /// ### |
| /// * For CT4x4 and CT8x8 primitives, specify which set of predictor buffer is holding the predictor pixel data. |
| /// ### |
| /// : ID_PRED 0x0 |
| /// : ID_ALT 0x1 |
| /// %% 5 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FuncPrimitive |
| #define h_FuncPrimitive (){} |
| |
| #define BA_FuncPrimitive_Type 0x0000 |
| #define B16FuncPrimitive_Type 0x0000 |
| #define LSb32FuncPrimitive_Type 0 |
| #define LSb16FuncPrimitive_Type 0 |
| #define bFuncPrimitive_Type 8 |
| #define MSK32FuncPrimitive_Type 0x000000FF |
| #define FuncPrimitive_Type_PCDT4x4 0x0 |
| #define FuncPrimitive_Type_PCT4x4 0x1 |
| #define FuncPrimitive_Type_PCDT16x16 0x2 |
| #define FuncPrimitive_Type_PCT16x16 0x3 |
| #define FuncPrimitive_Type_PCDT8x8 0x4 |
| #define FuncPrimitive_Type_PCT8x8 0x5 |
| #define FuncPrimitive_Type_PCDTUV 0x6 |
| #define FuncPrimitive_Type_PCTUV 0x7 |
| #define FuncPrimitive_Type_CT4x4 0x8 |
| #define FuncPrimitive_Type_CT8x8 0x9 |
| #define FuncPrimitive_Type_T8x8 0xA |
| #define FuncPrimitive_Type_QiQTC4x4I 0x20 |
| #define FuncPrimitive_Type_QiQTC4x4I16 0x21 |
| #define FuncPrimitive_Type_QiQTC8x8I 0x22 |
| #define FuncPrimitive_Type_QiQTC4x4IU 0x23 |
| #define FuncPrimitive_Type_QiQTC4x4IV 0x24 |
| #define FuncPrimitive_Type_QiQTC4x4Inter 0x25 |
| #define FuncPrimitive_Type_QiQTC4x4InterU 0x26 |
| #define FuncPrimitive_Type_QiQTC4x4InterV 0x27 |
| #define FuncPrimitive_Type_QiQTC8x8Inter 0x28 |
| #define FuncPrimitive_Type_QiQTC8x8IU 0x29 |
| #define FuncPrimitive_Type_QiQTC8x8IV 0x2A |
| #define FuncPrimitive_Type_QiQTC8x8InterU 0x2B |
| #define FuncPrimitive_Type_QiQTC8x8InterV 0x2C |
| #define FuncPrimitive_Type_HQiHQ4x4 0x40 |
| #define FuncPrimitive_Type_HQiHQ2x2IU 0x41 |
| #define FuncPrimitive_Type_HQiHQ2x2IV 0x42 |
| #define FuncPrimitive_Type_HQiHQ2x2InterU 0x43 |
| #define FuncPrimitive_Type_HQiHQ2x2InterV 0x44 |
| #define FuncPrimitive_Type_RDMB 0x60 |
| #define FuncPrimitive_Type_RD16x16 0x61 |
| #define FuncPrimitive_Type_RD8x8 0x62 |
| #define FuncPrimitive_Type_RD4x4 0x63 |
| #define FuncPrimitive_Type_RDUV 0x64 |
| #define FuncPrimitive_Type_RD16x16ToMB 0x65 |
| #define FuncPrimitive_Type_RDUVToMB 0x66 |
| #define FuncPrimitive_Type_NOP 0xA0 |
| #define FuncPrimitive_Type_P4x4 0xC1 |
| #define FuncPrimitive_Type_P16x16 0xC2 |
| #define FuncPrimitive_Type_P8x8 0xC3 |
| #define FuncPrimitive_Type_PUV 0xC4 |
| #define FuncPrimitive_Type_iTC4x4 0xC5 |
| #define FuncPrimitive_Type_iTC8x8 0xC6 |
| |
| #define BA_FuncPrimitive_BlkSubblockID 0x0001 |
| #define B16FuncPrimitive_BlkSubblockID 0x0000 |
| #define LSb32FuncPrimitive_BlkSubblockID 8 |
| #define LSb16FuncPrimitive_BlkSubblockID 8 |
| #define bFuncPrimitive_BlkSubblockID 5 |
| #define MSK32FuncPrimitive_BlkSubblockID 0x00001F00 |
| |
| #define BA_FuncPrimitive_BufferID 0x0001 |
| #define B16FuncPrimitive_BufferID 0x0000 |
| #define LSb32FuncPrimitive_BufferID 13 |
| #define LSb16FuncPrimitive_BufferID 13 |
| #define bFuncPrimitive_BufferID 6 |
| #define MSK32FuncPrimitive_BufferID 0x0007E000 |
| |
| #define BA_FuncPrimitive_Mode 0x0002 |
| #define B16FuncPrimitive_Mode 0x0002 |
| #define LSb32FuncPrimitive_Mode 19 |
| #define LSb16FuncPrimitive_Mode 3 |
| #define bFuncPrimitive_Mode 4 |
| #define MSK32FuncPrimitive_Mode 0x00780000 |
| #define FuncPrimitive_Mode_Intra_16x16_Vertical 0x0 |
| #define FuncPrimitive_Mode_Intra_16x16_Horizontal 0x1 |
| #define FuncPrimitive_Mode_Intra_16x16_DC 0x2 |
| #define FuncPrimitive_Mode_Intra_16x16_Plane 0x3 |
| #define FuncPrimitive_Mode_Intra_4x4_Vertical 0x0 |
| #define FuncPrimitive_Mode_Intra_4x4_Horizontal 0x1 |
| #define FuncPrimitive_Mode_Intra_4x4_DC 0x2 |
| #define FuncPrimitive_Mode_Intra_4x4_Diagonal_Down_Left 0x3 |
| #define FuncPrimitive_Mode_Intra_4x4_Diagonal_Down_Right 0x4 |
| #define FuncPrimitive_Mode_Intra_4x4_Vertical_Right 0x5 |
| #define FuncPrimitive_Mode_Intra_4x4_Horizontal_Down 0x6 |
| #define FuncPrimitive_Mode_Intra_4x4_Vertical_Left 0x7 |
| #define FuncPrimitive_Mode_Intra_4x4_Horizontal_Up 0x8 |
| #define FuncPrimitive_Mode_Intra_8x8_Vertical 0x0 |
| #define FuncPrimitive_Mode_Intra_8x8_Horizontal 0x1 |
| #define FuncPrimitive_Mode_Intra_8x8_DC 0x2 |
| #define FuncPrimitive_Mode_Intra_8x8_Diagonal_Down_Left 0x3 |
| #define FuncPrimitive_Mode_Intra_8x8_Diagonal_Down_Right 0x4 |
| #define FuncPrimitive_Mode_Intra_8x8_Vertical_Right 0x5 |
| #define FuncPrimitive_Mode_Intra_8x8_Horizontal_Down 0x6 |
| #define FuncPrimitive_Mode_Intra_8x8_Vertical_Left 0x7 |
| #define FuncPrimitive_Mode_Intra_8x8_Horizontal_Up 0x8 |
| #define FuncPrimitive_Mode_PART16x16 0x0 |
| #define FuncPrimitive_Mode_PART8x8 0x1 |
| #define FuncPrimitive_Mode_PART4x4 0x2 |
| |
| #define BA_FuncPrimitive_FinalizeRDBuf 0x0002 |
| #define B16FuncPrimitive_FinalizeRDBuf 0x0002 |
| #define LSb32FuncPrimitive_FinalizeRDBuf 23 |
| #define LSb16FuncPrimitive_FinalizeRDBuf 7 |
| #define bFuncPrimitive_FinalizeRDBuf 1 |
| #define MSK32FuncPrimitive_FinalizeRDBuf 0x00800000 |
| |
| #define BA_FuncPrimitive_RecBufId 0x0003 |
| #define B16FuncPrimitive_RecBufId 0x0002 |
| #define LSb32FuncPrimitive_RecBufId 24 |
| #define LSb16FuncPrimitive_RecBufId 8 |
| #define bFuncPrimitive_RecBufId 2 |
| #define MSK32FuncPrimitive_RecBufId 0x03000000 |
| #define FuncPrimitive_RecBufId_ID_QiQTC0 0x0 |
| #define FuncPrimitive_RecBufId_ID_QiQTC1 0x1 |
| #define FuncPrimitive_RecBufId_ID_CYNxN 0x2 |
| |
| #define BA_FuncPrimitive_PredBufId 0x0003 |
| #define B16FuncPrimitive_PredBufId 0x0002 |
| #define LSb32FuncPrimitive_PredBufId 26 |
| #define LSb16FuncPrimitive_PredBufId 10 |
| #define bFuncPrimitive_PredBufId 1 |
| #define MSK32FuncPrimitive_PredBufId 0x04000000 |
| #define FuncPrimitive_PredBufId_ID_PRED 0x0 |
| #define FuncPrimitive_PredBufId_ID_ALT 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FuncPrimitive { |
| /////////////////////////////////////////////////////////// |
| #define GET32FuncPrimitive_Type(r32) _BFGET_(r32, 7, 0) |
| #define SET32FuncPrimitive_Type(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16FuncPrimitive_Type(r16) _BFGET_(r16, 7, 0) |
| #define SET16FuncPrimitive_Type(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32FuncPrimitive_BlkSubblockID(r32) _BFGET_(r32,12, 8) |
| #define SET32FuncPrimitive_BlkSubblockID(r32,v) _BFSET_(r32,12, 8,v) |
| #define GET16FuncPrimitive_BlkSubblockID(r16) _BFGET_(r16,12, 8) |
| #define SET16FuncPrimitive_BlkSubblockID(r16,v) _BFSET_(r16,12, 8,v) |
| |
| #define GET32FuncPrimitive_BufferID(r32) _BFGET_(r32,18,13) |
| #define SET32FuncPrimitive_BufferID(r32,v) _BFSET_(r32,18,13,v) |
| |
| #define GET32FuncPrimitive_Mode(r32) _BFGET_(r32,22,19) |
| #define SET32FuncPrimitive_Mode(r32,v) _BFSET_(r32,22,19,v) |
| #define GET16FuncPrimitive_Mode(r16) _BFGET_(r16, 6, 3) |
| #define SET16FuncPrimitive_Mode(r16,v) _BFSET_(r16, 6, 3,v) |
| |
| #define GET32FuncPrimitive_FinalizeRDBuf(r32) _BFGET_(r32,23,23) |
| #define SET32FuncPrimitive_FinalizeRDBuf(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16FuncPrimitive_FinalizeRDBuf(r16) _BFGET_(r16, 7, 7) |
| #define SET16FuncPrimitive_FinalizeRDBuf(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32FuncPrimitive_RecBufId(r32) _BFGET_(r32,25,24) |
| #define SET32FuncPrimitive_RecBufId(r32,v) _BFSET_(r32,25,24,v) |
| #define GET16FuncPrimitive_RecBufId(r16) _BFGET_(r16, 9, 8) |
| #define SET16FuncPrimitive_RecBufId(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32FuncPrimitive_PredBufId(r32) _BFGET_(r32,26,26) |
| #define SET32FuncPrimitive_PredBufId(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16FuncPrimitive_PredBufId(r16) _BFGET_(r16,10,10) |
| #define SET16FuncPrimitive_PredBufId(r16,v) _BFSET_(r16,10,10,v) |
| |
| UNSG32 u_Type : 8; |
| UNSG32 u_BlkSubblockID : 5; |
| UNSG32 u_BufferID : 6; |
| UNSG32 u_Mode : 4; |
| UNSG32 u_FinalizeRDBuf : 1; |
| UNSG32 u_RecBufId : 2; |
| UNSG32 u_PredBufId : 1; |
| UNSG32 RSVDx0_b27 : 5; |
| /////////////////////////////////////////////////////////// |
| } SIE_FuncPrimitive; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FuncPrimitive_drvrd(SIE_FuncPrimitive *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FuncPrimitive_drvwr(SIE_FuncPrimitive *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FuncPrimitive_reset(SIE_FuncPrimitive *p); |
| SIGN32 FuncPrimitive_cmp (SIE_FuncPrimitive *p, SIE_FuncPrimitive *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FuncPrimitive_check(p,pie,pfx,hLOG) FuncPrimitive_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FuncPrimitive_print(p, pfx,hLOG) FuncPrimitive_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FuncPrimitive |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FlowPrimitive flat (4,4) |
| /// ### |
| /// * Flow Primitive Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 Type |
| /// ### |
| /// * Primitive types |
| /// ### |
| /// : Wait 0xF0 |
| /// : PrepareRotate 0xF1 |
| /// : RotateMBCTX 0xF2 |
| /// : OutputMB 0xF3 |
| /// : RetireOriginalBuffer 0xF4 |
| /// : RetirePredictorBuffer 0xF5 |
| /// : InvalidateRDBuf 0xF6 |
| /// : WaitAlt 0xF7 |
| /// : RetireAltPredictorBuffer 0xF8 |
| /// %unsigned 4 Id |
| /// ### |
| /// * For InvalidateRDBuf primitive to identify RD buffers. Each bit corresponds to one RD buffer. |
| /// ### |
| /// : BitcMB 0x1 |
| /// : BitcY16x16 0x2 |
| /// : BitcUV 0x4 |
| /// : BitcNxN 0x8 |
| /// ### |
| /// * For RetireOriginalBuffer, RetirePredictorBuffer and RetireAltPredictorBuffer to identify which part of buffer to be retired. |
| /// ### |
| /// : RT_MB 0x0 |
| /// : RT_Y16x16 0x1 |
| /// : RT_Y8x8_0 0x2 |
| /// : RT_Y8x8_1 0x3 |
| /// : RT_Y8x8_2 0x4 |
| /// : RT_Y8x8_3 0x5 |
| /// : RT_UV 0x6 |
| /// %unsigned 15 N |
| /// ### |
| /// * For Wait primitive, it is number of 64 bit data chunks. |
| /// * For WaitAlt primitive, it is number of 128 bit data chunks. |
| /// ### |
| /// %% 5 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FlowPrimitive |
| #define h_FlowPrimitive (){} |
| |
| #define BA_FlowPrimitive_Type 0x0000 |
| #define B16FlowPrimitive_Type 0x0000 |
| #define LSb32FlowPrimitive_Type 0 |
| #define LSb16FlowPrimitive_Type 0 |
| #define bFlowPrimitive_Type 8 |
| #define MSK32FlowPrimitive_Type 0x000000FF |
| #define FlowPrimitive_Type_Wait 0xF0 |
| #define FlowPrimitive_Type_PrepareRotate 0xF1 |
| #define FlowPrimitive_Type_RotateMBCTX 0xF2 |
| #define FlowPrimitive_Type_OutputMB 0xF3 |
| #define FlowPrimitive_Type_RetireOriginalBuffer 0xF4 |
| #define FlowPrimitive_Type_RetirePredictorBuffer 0xF5 |
| #define FlowPrimitive_Type_InvalidateRDBuf 0xF6 |
| #define FlowPrimitive_Type_WaitAlt 0xF7 |
| #define FlowPrimitive_Type_RetireAltPredictorBuffer 0xF8 |
| |
| #define BA_FlowPrimitive_Id 0x0001 |
| #define B16FlowPrimitive_Id 0x0000 |
| #define LSb32FlowPrimitive_Id 8 |
| #define LSb16FlowPrimitive_Id 8 |
| #define bFlowPrimitive_Id 4 |
| #define MSK32FlowPrimitive_Id 0x00000F00 |
| #define FlowPrimitive_Id_BitcMB 0x1 |
| #define FlowPrimitive_Id_BitcY16x16 0x2 |
| #define FlowPrimitive_Id_BitcUV 0x4 |
| #define FlowPrimitive_Id_BitcNxN 0x8 |
| #define FlowPrimitive_Id_RT_MB 0x0 |
| #define FlowPrimitive_Id_RT_Y16x16 0x1 |
| #define FlowPrimitive_Id_RT_Y8x8_0 0x2 |
| #define FlowPrimitive_Id_RT_Y8x8_1 0x3 |
| #define FlowPrimitive_Id_RT_Y8x8_2 0x4 |
| #define FlowPrimitive_Id_RT_Y8x8_3 0x5 |
| #define FlowPrimitive_Id_RT_UV 0x6 |
| |
| #define BA_FlowPrimitive_N 0x0001 |
| #define B16FlowPrimitive_N 0x0000 |
| #define LSb32FlowPrimitive_N 12 |
| #define LSb16FlowPrimitive_N 12 |
| #define bFlowPrimitive_N 15 |
| #define MSK32FlowPrimitive_N 0x07FFF000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FlowPrimitive { |
| /////////////////////////////////////////////////////////// |
| #define GET32FlowPrimitive_Type(r32) _BFGET_(r32, 7, 0) |
| #define SET32FlowPrimitive_Type(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16FlowPrimitive_Type(r16) _BFGET_(r16, 7, 0) |
| #define SET16FlowPrimitive_Type(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32FlowPrimitive_Id(r32) _BFGET_(r32,11, 8) |
| #define SET32FlowPrimitive_Id(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16FlowPrimitive_Id(r16) _BFGET_(r16,11, 8) |
| #define SET16FlowPrimitive_Id(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32FlowPrimitive_N(r32) _BFGET_(r32,26,12) |
| #define SET32FlowPrimitive_N(r32,v) _BFSET_(r32,26,12,v) |
| |
| UNSG32 u_Type : 8; |
| UNSG32 u_Id : 4; |
| UNSG32 u_N : 15; |
| UNSG32 RSVDx0_b27 : 5; |
| /////////////////////////////////////////////////////////// |
| } SIE_FlowPrimitive; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FlowPrimitive_drvrd(SIE_FlowPrimitive *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FlowPrimitive_drvwr(SIE_FlowPrimitive *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FlowPrimitive_reset(SIE_FlowPrimitive *p); |
| SIGN32 FlowPrimitive_cmp (SIE_FlowPrimitive *p, SIE_FlowPrimitive *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FlowPrimitive_check(p,pie,pfx,hLOG) FlowPrimitive_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FlowPrimitive_print(p, pfx,hLOG) FlowPrimitive_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FlowPrimitive |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQ4x4 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 qm |
| /// $QdeQMatrixEntry qm REG [8] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 32B, bits: 256b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQ4x4 |
| #define h_QdeQ4x4 (){} |
| |
| #define RA_QdeQ4x4_qm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQ4x4 { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_qm[8]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQ4x4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQ4x4_drvrd(SIE_QdeQ4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQ4x4_drvwr(SIE_QdeQ4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQ4x4_reset(SIE_QdeQ4x4 *p); |
| SIGN32 QdeQ4x4_cmp (SIE_QdeQ4x4 *p, SIE_QdeQ4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQ4x4_check(p,pie,pfx,hLOG) QdeQ4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQ4x4_print(p, pfx,hLOG) QdeQ4x4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQ4x4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQRemx4x4 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 qm |
| /// $QdeQ4x4 qm REG [6] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 192B, bits: 1536b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQRemx4x4 |
| #define h_QdeQRemx4x4 (){} |
| |
| #define RA_QdeQRemx4x4_qm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQRemx4x4 { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQ4x4 ie_qm[6]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQRemx4x4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQRemx4x4_drvrd(SIE_QdeQRemx4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQRemx4x4_drvwr(SIE_QdeQRemx4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQRemx4x4_reset(SIE_QdeQRemx4x4 *p); |
| SIGN32 QdeQRemx4x4_cmp (SIE_QdeQRemx4x4 *p, SIE_QdeQRemx4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQRemx4x4_check(p,pie,pfx,hLOG) QdeQRemx4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQRemx4x4_print(p, pfx,hLOG) QdeQRemx4x4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQRemx4x4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQ8x8 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 qm |
| /// $QdeQMatrixEntry qm REG [32] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 128B, bits: 1024b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQ8x8 |
| #define h_QdeQ8x8 (){} |
| |
| #define RA_QdeQ8x8_qm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQ8x8 { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQMatrixEntry ie_qm[32]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQ8x8; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQ8x8_drvrd(SIE_QdeQ8x8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQ8x8_drvwr(SIE_QdeQ8x8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQ8x8_reset(SIE_QdeQ8x8 *p); |
| SIGN32 QdeQ8x8_cmp (SIE_QdeQ8x8 *p, SIE_QdeQ8x8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQ8x8_check(p,pie,pfx,hLOG) QdeQ8x8_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQ8x8_print(p, pfx,hLOG) QdeQ8x8_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQ8x8 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QdeQRemx8x8 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 qm |
| /// $QdeQ8x8 qm REG [6] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 768B, bits: 6144b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QdeQRemx8x8 |
| #define h_QdeQRemx8x8 (){} |
| |
| #define RA_QdeQRemx8x8_qm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QdeQRemx8x8 { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQ8x8 ie_qm[6]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QdeQRemx8x8; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QdeQRemx8x8_drvrd(SIE_QdeQRemx8x8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QdeQRemx8x8_drvwr(SIE_QdeQRemx8x8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QdeQRemx8x8_reset(SIE_QdeQRemx8x8 *p); |
| SIGN32 QdeQRemx8x8_cmp (SIE_QdeQRemx8x8 *p, SIE_QdeQRemx8x8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QdeQRemx8x8_check(p,pie,pfx,hLOG) QdeQRemx8x8_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QdeQRemx8x8_print(p, pfx,hLOG) QdeQRemx8x8_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QdeQRemx8x8 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROQMatrix biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $QdeQRemx8x8 Y8x8Intra REG |
| /// ### |
| /// * For H.264: Intra Y 8x8 block inverse Q matrix |
| /// * For other formats, intra 8x8 block inverse Q matrix, only qm[0] is used |
| /// ### |
| /// @ 0x00300 (P) |
| /// # 0x00300 Y8x8Inter |
| /// $QdeQRemx8x8 Y8x8Inter REG |
| /// ### |
| /// * For H.264: Inter Y 8x8 block inverse Q matrix |
| /// * For other formats, inter 8x8 block inverse Q matrix, only qm[0] is used |
| /// ### |
| /// @ 0x00600 (P) |
| /// # 0x00600 Y4x4Intra |
| /// $QdeQRemx4x4 Y4x4Intra REG |
| /// ### |
| /// * For H.264: Intra Y 4x4 block inverse Q matrix |
| /// ### |
| /// @ 0x006C0 (P) |
| /// # 0x006C0 U4x4Intra |
| /// $QdeQRemx4x4 U4x4Intra REG |
| /// ### |
| /// * For H.264: Intra U 4x4 block inverse Q matrix |
| /// * For MPEG4: qm[0][0] of U4x4Intra of QMatrix is used for Chroma DC quantization since Chroma DC has different dc_scaler from Luma DC. |
| /// ### |
| /// @ 0x00780 (P) |
| /// # 0x00780 V4x4Intra |
| /// $QdeQRemx4x4 V4x4Intra REG |
| /// ### |
| /// * For H.264: Intra V 4x4 block inverse Q matrix |
| /// ### |
| /// @ 0x00840 (P) |
| /// # 0x00840 Y4x4Inter |
| /// $QdeQRemx4x4 Y4x4Inter REG |
| /// ### |
| /// * For H.264: Inter Y 4x4 block inverse Q matrix |
| /// ### |
| /// @ 0x00900 (P) |
| /// # 0x00900 U4x4Inter |
| /// $QdeQRemx4x4 U4x4Inter REG |
| /// ### |
| /// * For H.264: Inter U 4x4 block inverse Q matrix |
| /// ### |
| /// @ 0x009C0 (P) |
| /// # 0x009C0 V4x4Inter |
| /// $QdeQRemx4x4 V4x4Inter REG |
| /// ### |
| /// * For H.264: Inter V 4x4 block inverse Q matrix |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 2688B, bits: 21504b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROQMatrix |
| #define h_IPROQMatrix (){} |
| |
| #define RA_IPROQMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_Y8x8Inter 0x0300 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_Y4x4Intra 0x0600 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_U4x4Intra 0x06C0 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_V4x4Intra 0x0780 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_Y4x4Inter 0x0840 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_U4x4Inter 0x0900 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROQMatrix_V4x4Inter 0x09C0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROQMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx8x8 ie_Y8x8Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx8x8 ie_Y8x8Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_Y4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_U4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_V4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_Y4x4Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_U4x4Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_V4x4Inter; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROQMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROQMatrix_drvrd(SIE_IPROQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROQMatrix_drvwr(SIE_IPROQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROQMatrix_reset(SIE_IPROQMatrix *p); |
| SIGN32 IPROQMatrix_cmp (SIE_IPROQMatrix *p, SIE_IPROQMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROQMatrix_check(p,pie,pfx,hLOG) IPROQMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROQMatrix_print(p, pfx,hLOG) IPROQMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROQMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROdeQMatrix biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Y8x8Intra |
| /// $QdeQRemx8x8 Y8x8Intra REG |
| /// ### |
| /// * For H.264: Intra Y 8x8 block deQ matrix |
| /// * For other formats, intra 8x8 block Q matrix, only qm[0] is used |
| /// ### |
| /// @ 0x00300 (P) |
| /// # 0x00300 Y8x8Inter |
| /// $QdeQRemx8x8 Y8x8Inter REG |
| /// ### |
| /// * For H.264: Inter Y 8x8 block deQ matrix |
| /// * For other formats, inter 8x8 block Q matrix, only qm[0] is used |
| /// ### |
| /// @ 0x00600 (P) |
| /// # 0x00600 Y4x4Intra |
| /// $QdeQRemx4x4 Y4x4Intra REG |
| /// ### |
| /// * For H.264: Intra Y 4x4 block deQ matrix |
| /// ### |
| /// @ 0x006C0 (P) |
| /// # 0x006C0 U4x4Intra |
| /// $QdeQRemx4x4 U4x4Intra REG |
| /// ### |
| /// * For H.264: Intra U 4x4 block deQ matrix |
| /// * For MPEG4: qm[0][0] of U4x4Intra of deQMatrix is used for Chroma DC dequantization since Chroma DC has different dc_scaler from Luma DC. |
| /// ### |
| /// @ 0x00780 (P) |
| /// # 0x00780 V4x4Intra |
| /// $QdeQRemx4x4 V4x4Intra REG |
| /// ### |
| /// * For H.264: 4 Intra V 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00840 (P) |
| /// # 0x00840 Y4x4Inter |
| /// $QdeQRemx4x4 Y4x4Inter REG |
| /// ### |
| /// * For H.264: Inter Y 4x4 block deQ matrix |
| /// ### |
| /// @ 0x00900 (P) |
| /// # 0x00900 U4x4Inter |
| /// $QdeQRemx4x4 U4x4Inter REG |
| /// ### |
| /// * For H.264: Inter U 4x4 block deQ matrix |
| /// ### |
| /// @ 0x009C0 (P) |
| /// # 0x009C0 V4x4Inter |
| /// $QdeQRemx4x4 V4x4Inter REG |
| /// ### |
| /// * For H.264: Inter V 4x4 block deQ matrix |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 2688B, bits: 21504b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROdeQMatrix |
| #define h_IPROdeQMatrix (){} |
| |
| #define RA_IPROdeQMatrix_Y8x8Intra 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_Y8x8Inter 0x0300 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_Y4x4Intra 0x0600 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_U4x4Intra 0x06C0 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_V4x4Intra 0x0780 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_Y4x4Inter 0x0840 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_U4x4Inter 0x0900 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROdeQMatrix_V4x4Inter 0x09C0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROdeQMatrix { |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx8x8 ie_Y8x8Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx8x8 ie_Y8x8Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_Y4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_U4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_V4x4Intra; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_Y4x4Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_U4x4Inter; |
| /////////////////////////////////////////////////////////// |
| SIE_QdeQRemx4x4 ie_V4x4Inter; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROdeQMatrix; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROdeQMatrix_drvrd(SIE_IPROdeQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROdeQMatrix_drvwr(SIE_IPROdeQMatrix *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROdeQMatrix_reset(SIE_IPROdeQMatrix *p); |
| SIGN32 IPROdeQMatrix_cmp (SIE_IPROdeQMatrix *p, SIE_IPROdeQMatrix *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROdeQMatrix_check(p,pie,pfx,hLOG) IPROdeQMatrix_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROdeQMatrix_print(p, pfx,hLOG) IPROdeQMatrix_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROdeQMatrix |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE Rounding biu (4,4) |
| /// ### |
| /// * Rounding value |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 val 0x0 |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_Rounding |
| #define h_Rounding (){} |
| |
| #define BA_Rounding_val 0x0000 |
| #define B16Rounding_val 0x0000 |
| #define LSb32Rounding_val 0 |
| #define LSb16Rounding_val 0 |
| #define bRounding_val 16 |
| #define MSK32Rounding_val 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_Rounding { |
| /////////////////////////////////////////////////////////// |
| #define GET32Rounding_val(r32) _BFGET_(r32,15, 0) |
| #define SET32Rounding_val(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16Rounding_val(r16) _BFGET_(r16,15, 0) |
| #define SET16Rounding_val(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_val : 16; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_Rounding; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 Rounding_drvrd(SIE_Rounding *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 Rounding_drvwr(SIE_Rounding *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void Rounding_reset(SIE_Rounding *p); |
| SIGN32 Rounding_cmp (SIE_Rounding *p, SIE_Rounding *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define Rounding_check(p,pie,pfx,hLOG) Rounding_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define Rounding_print(p, pfx,hLOG) Rounding_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: Rounding |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RmIndex biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 rm |
| /// $Rounding rm REG [3] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 12B, bits: 48b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RmIndex |
| #define h_RmIndex (){} |
| |
| #define RA_RmIndex_rm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RmIndex { |
| /////////////////////////////////////////////////////////// |
| SIE_Rounding ie_rm[3]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RmIndex; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RmIndex_drvrd(SIE_RmIndex *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RmIndex_drvwr(SIE_RmIndex *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RmIndex_reset(SIE_RmIndex *p); |
| SIGN32 RmIndex_cmp (SIE_RmIndex *p, SIE_RmIndex *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RmIndex_check(p,pie,pfx,hLOG) RmIndex_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RmIndex_print(p, pfx,hLOG) RmIndex_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RmIndex |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RmYUV biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 rm |
| /// $RmIndex rm REG [3] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 36B, bits: 144b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RmYUV |
| #define h_RmYUV (){} |
| |
| #define RA_RmYUV_rm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RmYUV { |
| /////////////////////////////////////////////////////////// |
| SIE_RmIndex ie_rm[3]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RmYUV; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RmYUV_drvrd(SIE_RmYUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RmYUV_drvwr(SIE_RmYUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RmYUV_reset(SIE_RmYUV *p); |
| SIGN32 RmYUV_cmp (SIE_RmYUV *p, SIE_RmYUV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RmYUV_check(p,pie,pfx,hLOG) RmYUV_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RmYUV_print(p, pfx,hLOG) RmYUV_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RmYUV |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RmIntraInter biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 rm |
| /// $RmYUV rm REG [2] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 72B, bits: 288b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RmIntraInter |
| #define h_RmIntraInter (){} |
| |
| #define RA_RmIntraInter_rm 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RmIntraInter { |
| /////////////////////////////////////////////////////////// |
| SIE_RmYUV ie_rm[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RmIntraInter; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RmIntraInter_drvrd(SIE_RmIntraInter *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RmIntraInter_drvwr(SIE_RmIntraInter *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RmIntraInter_reset(SIE_RmIntraInter *p); |
| SIGN32 RmIntraInter_cmp (SIE_RmIntraInter *p, SIE_RmIntraInter *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RmIntraInter_check(p,pie,pfx,hLOG) RmIntraInter_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RmIntraInter_print(p, pfx,hLOG) RmIntraInter_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RmIntraInter |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE TrellisParam biu (4,4) |
| /// ### |
| /// * Trial rounding and trellis quantization parameters, programmed at picture level |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 TrialRounding |
| /// $RmIntraInter TrialRounding REG |
| /// ### |
| /// * trial_rounding[intra: 0 ~ 1][yuv: 0 ~ 2][rounding index: 0 ~ 2] used in trial rounding quantization. |
| /// ### |
| /// @ 0x00048 (P) |
| /// %unsigned 1 QuantMode 0x1 |
| /// ### |
| /// * Quantization mode. |
| /// * 0: trial rounding quantization |
| /// * 1: trellis quantization |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 76B, bits: 289b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_TrellisParam |
| #define h_TrellisParam (){} |
| |
| #define RA_TrellisParam_TrialRounding 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_TrellisParam_QuantMode 0x0048 |
| #define B16TrellisParam_QuantMode 0x0048 |
| #define LSb32TrellisParam_QuantMode 0 |
| #define LSb16TrellisParam_QuantMode 0 |
| #define bTrellisParam_QuantMode 1 |
| #define MSK32TrellisParam_QuantMode 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_TrellisParam { |
| /////////////////////////////////////////////////////////// |
| SIE_RmIntraInter ie_TrialRounding; |
| /////////////////////////////////////////////////////////// |
| #define GET32TrellisParam_QuantMode(r32) _BFGET_(r32, 0, 0) |
| #define SET32TrellisParam_QuantMode(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16TrellisParam_QuantMode(r16) _BFGET_(r16, 0, 0) |
| #define SET16TrellisParam_QuantMode(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| UNSG32 u_QuantMode : 1; |
| UNSG32 RSVDx48_b1 : 31; |
| /////////////////////////////////////////////////////////// |
| } SIE_TrellisParam; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 TrellisParam_drvrd(SIE_TrellisParam *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 TrellisParam_drvwr(SIE_TrellisParam *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void TrellisParam_reset(SIE_TrellisParam *p); |
| SIGN32 TrellisParam_cmp (SIE_TrellisParam *p, SIE_TrellisParam *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define TrellisParam_check(p,pie,pfx,hLOG) TrellisParam_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define TrellisParam_print(p, pfx,hLOG) TrellisParam_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: TrellisParam |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE PrimitiveEntry flat (4,4) |
| /// ### |
| /// * Store primitives |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 Primitives |
| /// ### |
| /// * Memory to store primitives |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_PrimitiveEntry |
| #define h_PrimitiveEntry (){} |
| |
| #define BA_PrimitiveEntry_Primitives 0x0000 |
| #define B16PrimitiveEntry_Primitives 0x0000 |
| #define LSb32PrimitiveEntry_Primitives 0 |
| #define LSb16PrimitiveEntry_Primitives 0 |
| #define bPrimitiveEntry_Primitives 32 |
| #define MSK32PrimitiveEntry_Primitives 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_PrimitiveEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32PrimitiveEntry_Primitives(r32) _BFGET_(r32,31, 0) |
| #define SET32PrimitiveEntry_Primitives(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_Primitives : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_PrimitiveEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 PrimitiveEntry_drvrd(SIE_PrimitiveEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 PrimitiveEntry_drvwr(SIE_PrimitiveEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void PrimitiveEntry_reset(SIE_PrimitiveEntry *p); |
| SIGN32 PrimitiveEntry_cmp (SIE_PrimitiveEntry *p, SIE_PrimitiveEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define PrimitiveEntry_check(p,pie,pfx,hLOG) PrimitiveEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define PrimitiveEntry_print(p, pfx,hLOG) PrimitiveEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: PrimitiveEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROBIU biu (4,4) |
| /// ### |
| /// * IPRO BIU |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 qram |
| /// $IPROQMatrix qram MEM |
| /// @ 0x01000 (P) |
| /// # 0x01000 dqram |
| /// $IPROdeQMatrix dqram MEM |
| /// @ 0x02000 (P) |
| /// # 0x02000 pram |
| /// $PrimitiveEntry pram MEM [1024] |
| /// @ 0x03000 (P) |
| /// # 0x03000 TrellisParam |
| /// $TrellisParam TrellisParam REG |
| /// @ 0x0304C (P) |
| /// %unsigned 1 SADMode 0x0 |
| /// ### |
| /// * SAD mode: 0: flat SAD, 1: 4x4 Hadamard transformed SAD |
| /// ### |
| /// %unsigned 7 IntraCtxFifoDepth 0x0 |
| /// ### |
| /// * The depth of intra prediction context FIFO in unit of Macroblocks |
| /// ### |
| /// %% 24 # Stuffing bits... |
| /// @ 0x03050 (W-) |
| /// # # Stuffing bytes... |
| /// %% 32128 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16384B, bits: 393b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROBIU |
| #define h_IPROBIU (){} |
| |
| #define RA_IPROBIU_qram 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROBIU_dqram 0x1000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROBIU_pram 0x2000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IPROBIU_TrellisParam 0x3000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_IPROBIU_SADMode 0x304C |
| #define B16IPROBIU_SADMode 0x304C |
| #define LSb32IPROBIU_SADMode 0 |
| #define LSb16IPROBIU_SADMode 0 |
| #define bIPROBIU_SADMode 1 |
| #define MSK32IPROBIU_SADMode 0x00000001 |
| |
| #define BA_IPROBIU_IntraCtxFifoDepth 0x304C |
| #define B16IPROBIU_IntraCtxFifoDepth 0x304C |
| #define LSb32IPROBIU_IntraCtxFifoDepth 1 |
| #define LSb16IPROBIU_IntraCtxFifoDepth 1 |
| #define bIPROBIU_IntraCtxFifoDepth 7 |
| #define MSK32IPROBIU_IntraCtxFifoDepth 0x000000FE |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROBIU { |
| /////////////////////////////////////////////////////////// |
| SIE_IPROQMatrix ie_qram; |
| UNSG8 RSVD_qram [1408]; |
| /////////////////////////////////////////////////////////// |
| SIE_IPROdeQMatrix ie_dqram; |
| UNSG8 RSVD_dqram [1408]; |
| /////////////////////////////////////////////////////////// |
| SIE_PrimitiveEntry ie_pram[1024]; |
| /////////////////////////////////////////////////////////// |
| SIE_TrellisParam ie_TrellisParam; |
| /////////////////////////////////////////////////////////// |
| #define GET32IPROBIU_SADMode(r32) _BFGET_(r32, 0, 0) |
| #define SET32IPROBIU_SADMode(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16IPROBIU_SADMode(r16) _BFGET_(r16, 0, 0) |
| #define SET16IPROBIU_SADMode(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32IPROBIU_IntraCtxFifoDepth(r32) _BFGET_(r32, 7, 1) |
| #define SET32IPROBIU_IntraCtxFifoDepth(r32,v) _BFSET_(r32, 7, 1,v) |
| #define GET16IPROBIU_IntraCtxFifoDepth(r16) _BFGET_(r16, 7, 1) |
| #define SET16IPROBIU_IntraCtxFifoDepth(r16,v) _BFSET_(r16, 7, 1,v) |
| |
| UNSG32 u_SADMode : 1; |
| UNSG32 u_IntraCtxFifoDepth : 7; |
| UNSG32 RSVDx304C_b8 : 24; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx3050 [4016]; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROBIU; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROBIU_drvrd(SIE_IPROBIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROBIU_drvwr(SIE_IPROBIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROBIU_reset(SIE_IPROBIU *p); |
| SIGN32 IPROBIU_cmp (SIE_IPROBIU *p, SIE_IPROBIU *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROBIU_check(p,pie,pfx,hLOG) IPROBIU_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROBIU_print(p, pfx,hLOG) IPROBIU_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROBIU |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64IPRO biu (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 format 0x0 |
| /// : h264 0x0 |
| /// : wmv 0x1 |
| /// ### |
| /// * VC-1 Simple/Main profile |
| /// ### |
| /// : mpeg2 0x2 |
| /// : mpeg4 0x4 |
| /// : vc1ap 0x5 |
| /// ### |
| /// * VC-1 Advanced profile |
| /// ### |
| /// : h263 0x6 |
| /// : mpeg4h263 0x7 |
| /// ### |
| /// * MPEG4 with H.263 type quant |
| /// ### |
| /// %unsigned 1 cavlc 0x0 |
| /// ### |
| /// * Whether current picture is H264 CAVLC coded or not |
| /// ### |
| /// %unsigned 6 istepb 0x10 |
| /// ### |
| /// * istepb for all formats except H.264 |
| /// ### |
| /// %unsigned 2 MismatchCtrl 0x0 |
| /// ### |
| /// * Mismatch control for dequant. Mode enable |
| /// ### |
| /// : disable 0x0 |
| /// : mpeg1 0x1 |
| /// : mpeg2 0x2 |
| /// %% 3 # Stuffing bits... |
| /// %unsigned 16 NZcbpCost 0x0 |
| /// ### |
| /// * Additional cost by non-zero cbp at RDMB |
| /// ### |
| /// %unsigned 16 bonusZero4x4 0x0 |
| /// ### |
| /// * Score bonus to zero out a 4x4 block |
| /// ### |
| /// %unsigned 16 bonusZero8x8 0x0 |
| /// ### |
| /// * Score bonus to zero out an 8x8 block |
| /// ### |
| /// @ 0x00008 (P) |
| /// %unsigned 12 tqInterLambda 0x0 |
| /// ### |
| /// * [8.4] for trellis quantization of inter blocks |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 12 tqIntraLambda 0x0 |
| /// ### |
| /// * [8.4] for trellis quantization of intra blocks |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 12 mdLambda 0x0 |
| /// ### |
| /// * [8.4] for RDO mode-decision |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 4 EOB4x4 0xF |
| /// ### |
| /// * Value of 15 turns off EOB zero-out. The value range is [1:15]. |
| /// ### |
| /// %unsigned 6 EOB8x8 0x3F |
| /// ### |
| /// * Value of 63 turns off EOB zero-out. The value range is [0:63]. |
| /// ### |
| /// %unsigned 1 FieldMB 0x0 |
| /// ### |
| /// * If current MB is field coded or not |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// %unsigned 1 AvailA 0x0 |
| /// ### |
| /// * If left MB is available for intra prediction. If left MB is inter MB and constrained_intra_pred_flag is 1, treat it as not available. |
| /// ### |
| /// %unsigned 1 AvailB 0x0 |
| /// ### |
| /// * If top MB is available for intra prediction. If top MB is inter MB and constrained_intra_pred_flag is 1, treat it as not available. |
| /// ### |
| /// %unsigned 1 AvailC 0x0 |
| /// ### |
| /// * If top-right MB is available for intra prediction. If top-right MB is inter MB and constrained_intra_pred_flag is 1, treat it as not available. |
| /// ### |
| /// %unsigned 1 AvailD 0x0 |
| /// ### |
| /// * If top-left MB is available for intra prediction. If top-left MB is inter MB and constrained_intra_pred_flag is 1, treat it as not available. |
| /// ### |
| /// @ 0x00010 (P) |
| /// %unsigned 16 istepY 0x0 |
| /// ### |
| /// * Inverse Quant step size for luma AC for format other than H264, used in quantization |
| /// ### |
| /// %unsigned 16 istepC 0x0 |
| /// ### |
| /// * Inverse Quant step size for chroma AC for format other than H264, used in quantization |
| /// ### |
| /// %unsigned 16 istepYDC 0x0 |
| /// ### |
| /// * Inverse Quant step size for luma DC for format other than H264, used in quantization |
| /// ### |
| /// %unsigned 16 istepCDC 0x0 |
| /// ### |
| /// * Inverse Quant step size for chroma DC for format other than H264, used in quantization |
| /// ### |
| /// @ 0x00018 (P) |
| /// %unsigned 8 QPY 0x0 |
| /// ### |
| /// * The QPY for H264; It is qstep of AC coefficient dequantization for formats other than H264 |
| /// ### |
| /// %unsigned 8 QPU 0x0 |
| /// ### |
| /// * The QPU for H264; It is not used for formats other than H264 |
| /// ### |
| /// %unsigned 8 QPV 0x0 |
| /// ### |
| /// * The QPV for H264; It is not used for formats other than H264 |
| /// ### |
| /// %unsigned 8 AC_dqofs 0x0 |
| /// ### |
| /// * AC dequantization offset, rounding offset during dequantization, for MPEG2/MPEG4/H263. |
| /// ### |
| /// %unsigned 8 qstepYDC 0x0 |
| /// ### |
| /// * It is qstep for Luma DC dequantization of formats other than H264 |
| /// ### |
| /// %unsigned 8 qstepCDC 0x0 |
| /// ### |
| /// * It is qstep for Chroma DC dequantization of formats other than H264 |
| /// ### |
| /// %unsigned 16 pcdtLambda 0x0 |
| /// ### |
| /// * Lambda for calculating cost of intra 4x4 and intra 8x8 prediction in PCDT primitives by SAD and bits used to code intra prediction mode. It is a fixed point number with 8.8 format. |
| /// ### |
| /// @ 0x00020 (P) |
| /// %unsigned 16 QDcLimitH 0x7FF |
| /// ### |
| /// * DC saturation upper limit for Quantization for non-H264 formats |
| /// ### |
| /// %unsigned 16 QAcLimitH 0x7FFF |
| /// ### |
| /// * AC/H.264 saturation upper limit for Quantization |
| /// ### |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 40B, bits: 272b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64IPRO |
| #define h_RF64IPRO (){} |
| |
| #define BA_RF64IPRO_format 0x0000 |
| #define B16RF64IPRO_format 0x0000 |
| #define LSb32RF64IPRO_format 0 |
| #define LSb16RF64IPRO_format 0 |
| #define bRF64IPRO_format 4 |
| #define MSK32RF64IPRO_format 0x0000000F |
| #define RF64IPRO_format_h264 0x0 |
| #define RF64IPRO_format_wmv 0x1 |
| #define RF64IPRO_format_mpeg2 0x2 |
| #define RF64IPRO_format_mpeg4 0x4 |
| #define RF64IPRO_format_vc1ap 0x5 |
| #define RF64IPRO_format_h263 0x6 |
| #define RF64IPRO_format_mpeg4h263 0x7 |
| |
| #define BA_RF64IPRO_cavlc 0x0000 |
| #define B16RF64IPRO_cavlc 0x0000 |
| #define LSb32RF64IPRO_cavlc 4 |
| #define LSb16RF64IPRO_cavlc 4 |
| #define bRF64IPRO_cavlc 1 |
| #define MSK32RF64IPRO_cavlc 0x00000010 |
| |
| #define BA_RF64IPRO_istepb 0x0000 |
| #define B16RF64IPRO_istepb 0x0000 |
| #define LSb32RF64IPRO_istepb 5 |
| #define LSb16RF64IPRO_istepb 5 |
| #define bRF64IPRO_istepb 6 |
| #define MSK32RF64IPRO_istepb 0x000007E0 |
| |
| #define BA_RF64IPRO_MismatchCtrl 0x0001 |
| #define B16RF64IPRO_MismatchCtrl 0x0000 |
| #define LSb32RF64IPRO_MismatchCtrl 11 |
| #define LSb16RF64IPRO_MismatchCtrl 11 |
| #define bRF64IPRO_MismatchCtrl 2 |
| #define MSK32RF64IPRO_MismatchCtrl 0x00001800 |
| #define RF64IPRO_MismatchCtrl_disable 0x0 |
| #define RF64IPRO_MismatchCtrl_mpeg1 0x1 |
| #define RF64IPRO_MismatchCtrl_mpeg2 0x2 |
| |
| #define BA_RF64IPRO_NZcbpCost 0x0002 |
| #define B16RF64IPRO_NZcbpCost 0x0002 |
| #define LSb32RF64IPRO_NZcbpCost 16 |
| #define LSb16RF64IPRO_NZcbpCost 0 |
| #define bRF64IPRO_NZcbpCost 16 |
| #define MSK32RF64IPRO_NZcbpCost 0xFFFF0000 |
| |
| #define BA_RF64IPRO_bonusZero4x4 0x0004 |
| #define B16RF64IPRO_bonusZero4x4 0x0004 |
| #define LSb32RF64IPRO_bonusZero4x4 0 |
| #define LSb16RF64IPRO_bonusZero4x4 0 |
| #define bRF64IPRO_bonusZero4x4 16 |
| #define MSK32RF64IPRO_bonusZero4x4 0x0000FFFF |
| |
| #define BA_RF64IPRO_bonusZero8x8 0x0006 |
| #define B16RF64IPRO_bonusZero8x8 0x0006 |
| #define LSb32RF64IPRO_bonusZero8x8 16 |
| #define LSb16RF64IPRO_bonusZero8x8 0 |
| #define bRF64IPRO_bonusZero8x8 16 |
| #define MSK32RF64IPRO_bonusZero8x8 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPRO_tqInterLambda 0x0008 |
| #define B16RF64IPRO_tqInterLambda 0x0008 |
| #define LSb32RF64IPRO_tqInterLambda 0 |
| #define LSb16RF64IPRO_tqInterLambda 0 |
| #define bRF64IPRO_tqInterLambda 12 |
| #define MSK32RF64IPRO_tqInterLambda 0x00000FFF |
| |
| #define BA_RF64IPRO_tqIntraLambda 0x000A |
| #define B16RF64IPRO_tqIntraLambda 0x000A |
| #define LSb32RF64IPRO_tqIntraLambda 16 |
| #define LSb16RF64IPRO_tqIntraLambda 0 |
| #define bRF64IPRO_tqIntraLambda 12 |
| #define MSK32RF64IPRO_tqIntraLambda 0x0FFF0000 |
| |
| #define BA_RF64IPRO_mdLambda 0x000C |
| #define B16RF64IPRO_mdLambda 0x000C |
| #define LSb32RF64IPRO_mdLambda 0 |
| #define LSb16RF64IPRO_mdLambda 0 |
| #define bRF64IPRO_mdLambda 12 |
| #define MSK32RF64IPRO_mdLambda 0x00000FFF |
| |
| #define BA_RF64IPRO_EOB4x4 0x000E |
| #define B16RF64IPRO_EOB4x4 0x000E |
| #define LSb32RF64IPRO_EOB4x4 16 |
| #define LSb16RF64IPRO_EOB4x4 0 |
| #define bRF64IPRO_EOB4x4 4 |
| #define MSK32RF64IPRO_EOB4x4 0x000F0000 |
| |
| #define BA_RF64IPRO_EOB8x8 0x000E |
| #define B16RF64IPRO_EOB8x8 0x000E |
| #define LSb32RF64IPRO_EOB8x8 20 |
| #define LSb16RF64IPRO_EOB8x8 4 |
| #define bRF64IPRO_EOB8x8 6 |
| #define MSK32RF64IPRO_EOB8x8 0x03F00000 |
| |
| #define BA_RF64IPRO_FieldMB 0x000F |
| #define B16RF64IPRO_FieldMB 0x000E |
| #define LSb32RF64IPRO_FieldMB 26 |
| #define LSb16RF64IPRO_FieldMB 10 |
| #define bRF64IPRO_FieldMB 1 |
| #define MSK32RF64IPRO_FieldMB 0x04000000 |
| |
| #define BA_RF64IPRO_AvailA 0x000F |
| #define B16RF64IPRO_AvailA 0x000E |
| #define LSb32RF64IPRO_AvailA 28 |
| #define LSb16RF64IPRO_AvailA 12 |
| #define bRF64IPRO_AvailA 1 |
| #define MSK32RF64IPRO_AvailA 0x10000000 |
| |
| #define BA_RF64IPRO_AvailB 0x000F |
| #define B16RF64IPRO_AvailB 0x000E |
| #define LSb32RF64IPRO_AvailB 29 |
| #define LSb16RF64IPRO_AvailB 13 |
| #define bRF64IPRO_AvailB 1 |
| #define MSK32RF64IPRO_AvailB 0x20000000 |
| |
| #define BA_RF64IPRO_AvailC 0x000F |
| #define B16RF64IPRO_AvailC 0x000E |
| #define LSb32RF64IPRO_AvailC 30 |
| #define LSb16RF64IPRO_AvailC 14 |
| #define bRF64IPRO_AvailC 1 |
| #define MSK32RF64IPRO_AvailC 0x40000000 |
| |
| #define BA_RF64IPRO_AvailD 0x000F |
| #define B16RF64IPRO_AvailD 0x000E |
| #define LSb32RF64IPRO_AvailD 31 |
| #define LSb16RF64IPRO_AvailD 15 |
| #define bRF64IPRO_AvailD 1 |
| #define MSK32RF64IPRO_AvailD 0x80000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPRO_istepY 0x0010 |
| #define B16RF64IPRO_istepY 0x0010 |
| #define LSb32RF64IPRO_istepY 0 |
| #define LSb16RF64IPRO_istepY 0 |
| #define bRF64IPRO_istepY 16 |
| #define MSK32RF64IPRO_istepY 0x0000FFFF |
| |
| #define BA_RF64IPRO_istepC 0x0012 |
| #define B16RF64IPRO_istepC 0x0012 |
| #define LSb32RF64IPRO_istepC 16 |
| #define LSb16RF64IPRO_istepC 0 |
| #define bRF64IPRO_istepC 16 |
| #define MSK32RF64IPRO_istepC 0xFFFF0000 |
| |
| #define BA_RF64IPRO_istepYDC 0x0014 |
| #define B16RF64IPRO_istepYDC 0x0014 |
| #define LSb32RF64IPRO_istepYDC 0 |
| #define LSb16RF64IPRO_istepYDC 0 |
| #define bRF64IPRO_istepYDC 16 |
| #define MSK32RF64IPRO_istepYDC 0x0000FFFF |
| |
| #define BA_RF64IPRO_istepCDC 0x0016 |
| #define B16RF64IPRO_istepCDC 0x0016 |
| #define LSb32RF64IPRO_istepCDC 16 |
| #define LSb16RF64IPRO_istepCDC 0 |
| #define bRF64IPRO_istepCDC 16 |
| #define MSK32RF64IPRO_istepCDC 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPRO_QPY 0x0018 |
| #define B16RF64IPRO_QPY 0x0018 |
| #define LSb32RF64IPRO_QPY 0 |
| #define LSb16RF64IPRO_QPY 0 |
| #define bRF64IPRO_QPY 8 |
| #define MSK32RF64IPRO_QPY 0x000000FF |
| |
| #define BA_RF64IPRO_QPU 0x0019 |
| #define B16RF64IPRO_QPU 0x0018 |
| #define LSb32RF64IPRO_QPU 8 |
| #define LSb16RF64IPRO_QPU 8 |
| #define bRF64IPRO_QPU 8 |
| #define MSK32RF64IPRO_QPU 0x0000FF00 |
| |
| #define BA_RF64IPRO_QPV 0x001A |
| #define B16RF64IPRO_QPV 0x001A |
| #define LSb32RF64IPRO_QPV 16 |
| #define LSb16RF64IPRO_QPV 0 |
| #define bRF64IPRO_QPV 8 |
| #define MSK32RF64IPRO_QPV 0x00FF0000 |
| |
| #define BA_RF64IPRO_AC_dqofs 0x001B |
| #define B16RF64IPRO_AC_dqofs 0x001A |
| #define LSb32RF64IPRO_AC_dqofs 24 |
| #define LSb16RF64IPRO_AC_dqofs 8 |
| #define bRF64IPRO_AC_dqofs 8 |
| #define MSK32RF64IPRO_AC_dqofs 0xFF000000 |
| |
| #define BA_RF64IPRO_qstepYDC 0x001C |
| #define B16RF64IPRO_qstepYDC 0x001C |
| #define LSb32RF64IPRO_qstepYDC 0 |
| #define LSb16RF64IPRO_qstepYDC 0 |
| #define bRF64IPRO_qstepYDC 8 |
| #define MSK32RF64IPRO_qstepYDC 0x000000FF |
| |
| #define BA_RF64IPRO_qstepCDC 0x001D |
| #define B16RF64IPRO_qstepCDC 0x001C |
| #define LSb32RF64IPRO_qstepCDC 8 |
| #define LSb16RF64IPRO_qstepCDC 8 |
| #define bRF64IPRO_qstepCDC 8 |
| #define MSK32RF64IPRO_qstepCDC 0x0000FF00 |
| |
| #define BA_RF64IPRO_pcdtLambda 0x001E |
| #define B16RF64IPRO_pcdtLambda 0x001E |
| #define LSb32RF64IPRO_pcdtLambda 16 |
| #define LSb16RF64IPRO_pcdtLambda 0 |
| #define bRF64IPRO_pcdtLambda 16 |
| #define MSK32RF64IPRO_pcdtLambda 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPRO_QDcLimitH 0x0020 |
| #define B16RF64IPRO_QDcLimitH 0x0020 |
| #define LSb32RF64IPRO_QDcLimitH 0 |
| #define LSb16RF64IPRO_QDcLimitH 0 |
| #define bRF64IPRO_QDcLimitH 16 |
| #define MSK32RF64IPRO_QDcLimitH 0x0000FFFF |
| |
| #define BA_RF64IPRO_QAcLimitH 0x0022 |
| #define B16RF64IPRO_QAcLimitH 0x0022 |
| #define LSb32RF64IPRO_QAcLimitH 16 |
| #define LSb16RF64IPRO_QAcLimitH 0 |
| #define bRF64IPRO_QAcLimitH 16 |
| #define MSK32RF64IPRO_QAcLimitH 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64IPRO { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPRO_format(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64IPRO_format(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64IPRO_format(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64IPRO_format(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64IPRO_cavlc(r32) _BFGET_(r32, 4, 4) |
| #define SET32RF64IPRO_cavlc(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16RF64IPRO_cavlc(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64IPRO_cavlc(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32RF64IPRO_istepb(r32) _BFGET_(r32,10, 5) |
| #define SET32RF64IPRO_istepb(r32,v) _BFSET_(r32,10, 5,v) |
| #define GET16RF64IPRO_istepb(r16) _BFGET_(r16,10, 5) |
| #define SET16RF64IPRO_istepb(r16,v) _BFSET_(r16,10, 5,v) |
| |
| #define GET32RF64IPRO_MismatchCtrl(r32) _BFGET_(r32,12,11) |
| #define SET32RF64IPRO_MismatchCtrl(r32,v) _BFSET_(r32,12,11,v) |
| #define GET16RF64IPRO_MismatchCtrl(r16) _BFGET_(r16,12,11) |
| #define SET16RF64IPRO_MismatchCtrl(r16,v) _BFSET_(r16,12,11,v) |
| |
| #define GET32RF64IPRO_NZcbpCost(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_NZcbpCost(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_NZcbpCost(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_NZcbpCost(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_format : 4; |
| UNSG32 u_cavlc : 1; |
| UNSG32 u_istepb : 6; |
| UNSG32 u_MismatchCtrl : 2; |
| UNSG32 RSVDx0_b13 : 3; |
| UNSG32 u_NZcbpCost : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPRO_bonusZero4x4(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64IPRO_bonusZero4x4(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64IPRO_bonusZero4x4(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_bonusZero4x4(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64IPRO_bonusZero8x8(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_bonusZero8x8(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_bonusZero8x8(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_bonusZero8x8(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_bonusZero4x4 : 16; |
| UNSG32 u_bonusZero8x8 : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPRO_tqInterLambda(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPRO_tqInterLambda(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPRO_tqInterLambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPRO_tqInterLambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPRO_tqIntraLambda(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPRO_tqIntraLambda(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPRO_tqIntraLambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPRO_tqIntraLambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| UNSG32 u_tqInterLambda : 12; |
| UNSG32 RSVDx8_b12 : 4; |
| UNSG32 u_tqIntraLambda : 12; |
| UNSG32 RSVDx8_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPRO_mdLambda(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPRO_mdLambda(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPRO_mdLambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPRO_mdLambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPRO_EOB4x4(r32) _BFGET_(r32,19,16) |
| #define SET32RF64IPRO_EOB4x4(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64IPRO_EOB4x4(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64IPRO_EOB4x4(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64IPRO_EOB8x8(r32) _BFGET_(r32,25,20) |
| #define SET32RF64IPRO_EOB8x8(r32,v) _BFSET_(r32,25,20,v) |
| #define GET16RF64IPRO_EOB8x8(r16) _BFGET_(r16, 9, 4) |
| #define SET16RF64IPRO_EOB8x8(r16,v) _BFSET_(r16, 9, 4,v) |
| |
| #define GET32RF64IPRO_FieldMB(r32) _BFGET_(r32,26,26) |
| #define SET32RF64IPRO_FieldMB(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16RF64IPRO_FieldMB(r16) _BFGET_(r16,10,10) |
| #define SET16RF64IPRO_FieldMB(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32RF64IPRO_AvailA(r32) _BFGET_(r32,28,28) |
| #define SET32RF64IPRO_AvailA(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16RF64IPRO_AvailA(r16) _BFGET_(r16,12,12) |
| #define SET16RF64IPRO_AvailA(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64IPRO_AvailB(r32) _BFGET_(r32,29,29) |
| #define SET32RF64IPRO_AvailB(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16RF64IPRO_AvailB(r16) _BFGET_(r16,13,13) |
| #define SET16RF64IPRO_AvailB(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64IPRO_AvailC(r32) _BFGET_(r32,30,30) |
| #define SET32RF64IPRO_AvailC(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16RF64IPRO_AvailC(r16) _BFGET_(r16,14,14) |
| #define SET16RF64IPRO_AvailC(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32RF64IPRO_AvailD(r32) _BFGET_(r32,31,31) |
| #define SET32RF64IPRO_AvailD(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16RF64IPRO_AvailD(r16) _BFGET_(r16,15,15) |
| #define SET16RF64IPRO_AvailD(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_mdLambda : 12; |
| UNSG32 RSVDxC_b12 : 4; |
| UNSG32 u_EOB4x4 : 4; |
| UNSG32 u_EOB8x8 : 6; |
| UNSG32 u_FieldMB : 1; |
| UNSG32 RSVDxC_b27 : 1; |
| UNSG32 u_AvailA : 1; |
| UNSG32 u_AvailB : 1; |
| UNSG32 u_AvailC : 1; |
| UNSG32 u_AvailD : 1; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPRO_istepY(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64IPRO_istepY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64IPRO_istepY(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_istepY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64IPRO_istepC(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_istepC(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_istepC(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_istepC(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_istepY : 16; |
| UNSG32 u_istepC : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPRO_istepYDC(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64IPRO_istepYDC(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64IPRO_istepYDC(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_istepYDC(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64IPRO_istepCDC(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_istepCDC(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_istepCDC(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_istepCDC(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_istepYDC : 16; |
| UNSG32 u_istepCDC : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPRO_QPY(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64IPRO_QPY(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64IPRO_QPY(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64IPRO_QPY(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64IPRO_QPU(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64IPRO_QPU(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64IPRO_QPU(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64IPRO_QPU(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64IPRO_QPV(r32) _BFGET_(r32,23,16) |
| #define SET32RF64IPRO_QPV(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64IPRO_QPV(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64IPRO_QPV(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64IPRO_AC_dqofs(r32) _BFGET_(r32,31,24) |
| #define SET32RF64IPRO_AC_dqofs(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64IPRO_AC_dqofs(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64IPRO_AC_dqofs(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_QPY : 8; |
| UNSG32 u_QPU : 8; |
| UNSG32 u_QPV : 8; |
| UNSG32 u_AC_dqofs : 8; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPRO_qstepYDC(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64IPRO_qstepYDC(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64IPRO_qstepYDC(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64IPRO_qstepYDC(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64IPRO_qstepCDC(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64IPRO_qstepCDC(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64IPRO_qstepCDC(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64IPRO_qstepCDC(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64IPRO_pcdtLambda(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_pcdtLambda(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_pcdtLambda(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_pcdtLambda(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_qstepYDC : 8; |
| UNSG32 u_qstepCDC : 8; |
| UNSG32 u_pcdtLambda : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPRO_QDcLimitH(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64IPRO_QDcLimitH(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64IPRO_QDcLimitH(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_QDcLimitH(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64IPRO_QAcLimitH(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPRO_QAcLimitH(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPRO_QAcLimitH(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPRO_QAcLimitH(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_QDcLimitH : 16; |
| UNSG32 u_QAcLimitH : 16; |
| UNSG8 RSVDx24 [4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64IPRO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64IPRO_drvrd(SIE_RF64IPRO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64IPRO_drvwr(SIE_RF64IPRO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64IPRO_reset(SIE_RF64IPRO *p); |
| SIGN32 RF64IPRO_cmp (SIE_RF64IPRO *p, SIE_RF64IPRO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64IPRO_check(p,pie,pfx,hLOG) RF64IPRO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64IPRO_print(p, pfx,hLOG) RF64IPRO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64IPRO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROCoeffCmdResp biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 v |
| /// $CoeffCmd v REG [2] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROCoeffCmdResp |
| #define h_IPROCoeffCmdResp (){} |
| |
| #define RA_IPROCoeffCmdResp_v 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROCoeffCmdResp { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_v[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROCoeffCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROCoeffCmdResp_drvrd(SIE_IPROCoeffCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROCoeffCmdResp_drvwr(SIE_IPROCoeffCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROCoeffCmdResp_reset(SIE_IPROCoeffCmdResp *p); |
| SIGN32 IPROCoeffCmdResp_cmp (SIE_IPROCoeffCmdResp *p, SIE_IPROCoeffCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROCoeffCmdResp_check(p,pie,pfx,hLOG) IPROCoeffCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROCoeffCmdResp_print(p, pfx,hLOG) IPROCoeffCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROCoeffCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROCoeffCntResp flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 v |
| /// $CoeffCnt v REG [8] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 32B, bits: 256b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROCoeffCntResp |
| #define h_IPROCoeffCntResp (){} |
| |
| #define RA_IPROCoeffCntResp_v 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROCoeffCntResp { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCnt ie_v[8]; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROCoeffCntResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROCoeffCntResp_drvrd(SIE_IPROCoeffCntResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROCoeffCntResp_drvwr(SIE_IPROCoeffCntResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROCoeffCntResp_reset(SIE_IPROCoeffCntResp *p); |
| SIGN32 IPROCoeffCntResp_cmp (SIE_IPROCoeffCntResp *p, SIE_IPROCoeffCntResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROCoeffCntResp_check(p,pie,pfx,hLOG) IPROCoeffCntResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROCoeffCntResp_print(p, pfx,hLOG) IPROCoeffCntResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROCoeffCntResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPROCBPCmdResp flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 CBPDC |
| /// %unsigned 6 CBP |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 16 CBFy |
| /// %unsigned 4 CBFu |
| /// %unsigned 4 CBFv |
| /// %unsigned 1 CBF16x16I |
| /// %unsigned 1 CBF4x4U |
| /// %unsigned 1 CBF4x4V |
| /// %% 21 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPROCBPCmdResp |
| #define h_IPROCBPCmdResp (){} |
| |
| #define BA_IPROCBPCmdResp_CBPDC 0x0000 |
| #define B16IPROCBPCmdResp_CBPDC 0x0000 |
| #define LSb32IPROCBPCmdResp_CBPDC 0 |
| #define LSb16IPROCBPCmdResp_CBPDC 0 |
| #define bIPROCBPCmdResp_CBPDC 6 |
| #define MSK32IPROCBPCmdResp_CBPDC 0x0000003F |
| |
| #define BA_IPROCBPCmdResp_CBP 0x0000 |
| #define B16IPROCBPCmdResp_CBP 0x0000 |
| #define LSb32IPROCBPCmdResp_CBP 6 |
| #define LSb16IPROCBPCmdResp_CBP 6 |
| #define bIPROCBPCmdResp_CBP 6 |
| #define MSK32IPROCBPCmdResp_CBP 0x00000FC0 |
| |
| #define BA_IPROCBPCmdResp_CBFy 0x0002 |
| #define B16IPROCBPCmdResp_CBFy 0x0002 |
| #define LSb32IPROCBPCmdResp_CBFy 16 |
| #define LSb16IPROCBPCmdResp_CBFy 0 |
| #define bIPROCBPCmdResp_CBFy 16 |
| #define MSK32IPROCBPCmdResp_CBFy 0xFFFF0000 |
| |
| #define BA_IPROCBPCmdResp_CBFu 0x0004 |
| #define B16IPROCBPCmdResp_CBFu 0x0004 |
| #define LSb32IPROCBPCmdResp_CBFu 0 |
| #define LSb16IPROCBPCmdResp_CBFu 0 |
| #define bIPROCBPCmdResp_CBFu 4 |
| #define MSK32IPROCBPCmdResp_CBFu 0x0000000F |
| |
| #define BA_IPROCBPCmdResp_CBFv 0x0004 |
| #define B16IPROCBPCmdResp_CBFv 0x0004 |
| #define LSb32IPROCBPCmdResp_CBFv 4 |
| #define LSb16IPROCBPCmdResp_CBFv 4 |
| #define bIPROCBPCmdResp_CBFv 4 |
| #define MSK32IPROCBPCmdResp_CBFv 0x000000F0 |
| |
| #define BA_IPROCBPCmdResp_CBF16x16I 0x0005 |
| #define B16IPROCBPCmdResp_CBF16x16I 0x0004 |
| #define LSb32IPROCBPCmdResp_CBF16x16I 8 |
| #define LSb16IPROCBPCmdResp_CBF16x16I 8 |
| #define bIPROCBPCmdResp_CBF16x16I 1 |
| #define MSK32IPROCBPCmdResp_CBF16x16I 0x00000100 |
| |
| #define BA_IPROCBPCmdResp_CBF4x4U 0x0005 |
| #define B16IPROCBPCmdResp_CBF4x4U 0x0004 |
| #define LSb32IPROCBPCmdResp_CBF4x4U 9 |
| #define LSb16IPROCBPCmdResp_CBF4x4U 9 |
| #define bIPROCBPCmdResp_CBF4x4U 1 |
| #define MSK32IPROCBPCmdResp_CBF4x4U 0x00000200 |
| |
| #define BA_IPROCBPCmdResp_CBF4x4V 0x0005 |
| #define B16IPROCBPCmdResp_CBF4x4V 0x0004 |
| #define LSb32IPROCBPCmdResp_CBF4x4V 10 |
| #define LSb16IPROCBPCmdResp_CBF4x4V 10 |
| #define bIPROCBPCmdResp_CBF4x4V 1 |
| #define MSK32IPROCBPCmdResp_CBF4x4V 0x00000400 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPROCBPCmdResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPROCBPCmdResp_CBPDC(r32) _BFGET_(r32, 5, 0) |
| #define SET32IPROCBPCmdResp_CBPDC(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16IPROCBPCmdResp_CBPDC(r16) _BFGET_(r16, 5, 0) |
| #define SET16IPROCBPCmdResp_CBPDC(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32IPROCBPCmdResp_CBP(r32) _BFGET_(r32,11, 6) |
| #define SET32IPROCBPCmdResp_CBP(r32,v) _BFSET_(r32,11, 6,v) |
| #define GET16IPROCBPCmdResp_CBP(r16) _BFGET_(r16,11, 6) |
| #define SET16IPROCBPCmdResp_CBP(r16,v) _BFSET_(r16,11, 6,v) |
| |
| #define GET32IPROCBPCmdResp_CBFy(r32) _BFGET_(r32,31,16) |
| #define SET32IPROCBPCmdResp_CBFy(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16IPROCBPCmdResp_CBFy(r16) _BFGET_(r16,15, 0) |
| #define SET16IPROCBPCmdResp_CBFy(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_CBPDC : 6; |
| UNSG32 u_CBP : 6; |
| UNSG32 RSVDx0_b12 : 4; |
| UNSG32 u_CBFy : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32IPROCBPCmdResp_CBFu(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPROCBPCmdResp_CBFu(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPROCBPCmdResp_CBFu(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPROCBPCmdResp_CBFu(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPROCBPCmdResp_CBFv(r32) _BFGET_(r32, 7, 4) |
| #define SET32IPROCBPCmdResp_CBFv(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16IPROCBPCmdResp_CBFv(r16) _BFGET_(r16, 7, 4) |
| #define SET16IPROCBPCmdResp_CBFv(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32IPROCBPCmdResp_CBF16x16I(r32) _BFGET_(r32, 8, 8) |
| #define SET32IPROCBPCmdResp_CBF16x16I(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16IPROCBPCmdResp_CBF16x16I(r16) _BFGET_(r16, 8, 8) |
| #define SET16IPROCBPCmdResp_CBF16x16I(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32IPROCBPCmdResp_CBF4x4U(r32) _BFGET_(r32, 9, 9) |
| #define SET32IPROCBPCmdResp_CBF4x4U(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16IPROCBPCmdResp_CBF4x4U(r16) _BFGET_(r16, 9, 9) |
| #define SET16IPROCBPCmdResp_CBF4x4U(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32IPROCBPCmdResp_CBF4x4V(r32) _BFGET_(r32,10,10) |
| #define SET32IPROCBPCmdResp_CBF4x4V(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16IPROCBPCmdResp_CBF4x4V(r16) _BFGET_(r16,10,10) |
| #define SET16IPROCBPCmdResp_CBF4x4V(r16,v) _BFSET_(r16,10,10,v) |
| |
| UNSG32 u_CBFu : 4; |
| UNSG32 u_CBFv : 4; |
| UNSG32 u_CBF16x16I : 1; |
| UNSG32 u_CBF4x4U : 1; |
| UNSG32 u_CBF4x4V : 1; |
| UNSG32 RSVDx4_b11 : 21; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPROCBPCmdResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPROCBPCmdResp_drvrd(SIE_IPROCBPCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPROCBPCmdResp_drvwr(SIE_IPROCBPCmdResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPROCBPCmdResp_reset(SIE_IPROCBPCmdResp *p); |
| SIGN32 IPROCBPCmdResp_cmp (SIE_IPROCBPCmdResp *p, SIE_IPROCBPCmdResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPROCBPCmdResp_check(p,pie,pfx,hLOG) IPROCBPCmdResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPROCBPCmdResp_print(p, pfx,hLOG) IPROCBPCmdResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPROCBPCmdResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BestCatInterModeY flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 2 Best_Mode_Cat_Y |
| /// ### |
| /// * Category of the best intra prediction mode for Luma |
| /// ### |
| /// : Cat_Intra16x16 0x0 |
| /// : Cat_Intra4x4 0x1 |
| /// : Cat_Intra8x8 0x2 |
| /// : Cat_Inter 0x3 |
| /// %unsigned 6 Best_Tag_Y |
| /// ### |
| /// * Best candidate's tag for current MB or Luma 16x16 block. |
| /// ### |
| /// %unsigned 1 Best_Trans_Type |
| /// ### |
| /// * Best transform type for current MB, for H264 only |
| /// ### |
| /// : Trans4x4 0x0 |
| /// : Trans8x8 0x1 |
| /// %% 23 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BestCatInterModeY |
| #define h_BestCatInterModeY (){} |
| |
| #define BA_BestCatInterModeY_Best_Mode_Cat_Y 0x0000 |
| #define B16BestCatInterModeY_Best_Mode_Cat_Y 0x0000 |
| #define LSb32BestCatInterModeY_Best_Mode_Cat_Y 0 |
| #define LSb16BestCatInterModeY_Best_Mode_Cat_Y 0 |
| #define bBestCatInterModeY_Best_Mode_Cat_Y 2 |
| #define MSK32BestCatInterModeY_Best_Mode_Cat_Y 0x00000003 |
| #define BestCatInterModeY_Best_Mode_Cat_Y_Cat_Intra16x16 0x0 |
| #define BestCatInterModeY_Best_Mode_Cat_Y_Cat_Intra4x4 0x1 |
| #define BestCatInterModeY_Best_Mode_Cat_Y_Cat_Intra8x8 0x2 |
| #define BestCatInterModeY_Best_Mode_Cat_Y_Cat_Inter 0x3 |
| |
| #define BA_BestCatInterModeY_Best_Tag_Y 0x0000 |
| #define B16BestCatInterModeY_Best_Tag_Y 0x0000 |
| #define LSb32BestCatInterModeY_Best_Tag_Y 2 |
| #define LSb16BestCatInterModeY_Best_Tag_Y 2 |
| #define bBestCatInterModeY_Best_Tag_Y 6 |
| #define MSK32BestCatInterModeY_Best_Tag_Y 0x000000FC |
| |
| #define BA_BestCatInterModeY_Best_Trans_Type 0x0001 |
| #define B16BestCatInterModeY_Best_Trans_Type 0x0000 |
| #define LSb32BestCatInterModeY_Best_Trans_Type 8 |
| #define LSb16BestCatInterModeY_Best_Trans_Type 8 |
| #define bBestCatInterModeY_Best_Trans_Type 1 |
| #define MSK32BestCatInterModeY_Best_Trans_Type 0x00000100 |
| #define BestCatInterModeY_Best_Trans_Type_Trans4x4 0x0 |
| #define BestCatInterModeY_Best_Trans_Type_Trans8x8 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BestCatInterModeY { |
| /////////////////////////////////////////////////////////// |
| #define GET32BestCatInterModeY_Best_Mode_Cat_Y(r32) _BFGET_(r32, 1, 0) |
| #define SET32BestCatInterModeY_Best_Mode_Cat_Y(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16BestCatInterModeY_Best_Mode_Cat_Y(r16) _BFGET_(r16, 1, 0) |
| #define SET16BestCatInterModeY_Best_Mode_Cat_Y(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32BestCatInterModeY_Best_Tag_Y(r32) _BFGET_(r32, 7, 2) |
| #define SET32BestCatInterModeY_Best_Tag_Y(r32,v) _BFSET_(r32, 7, 2,v) |
| #define GET16BestCatInterModeY_Best_Tag_Y(r16) _BFGET_(r16, 7, 2) |
| #define SET16BestCatInterModeY_Best_Tag_Y(r16,v) _BFSET_(r16, 7, 2,v) |
| |
| #define GET32BestCatInterModeY_Best_Trans_Type(r32) _BFGET_(r32, 8, 8) |
| #define SET32BestCatInterModeY_Best_Trans_Type(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16BestCatInterModeY_Best_Trans_Type(r16) _BFGET_(r16, 8, 8) |
| #define SET16BestCatInterModeY_Best_Trans_Type(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| UNSG32 u_Best_Mode_Cat_Y : 2; |
| UNSG32 u_Best_Tag_Y : 6; |
| UNSG32 u_Best_Trans_Type : 1; |
| UNSG32 RSVDx0_b9 : 23; |
| /////////////////////////////////////////////////////////// |
| } SIE_BestCatInterModeY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BestCatInterModeY_drvrd(SIE_BestCatInterModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BestCatInterModeY_drvwr(SIE_BestCatInterModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BestCatInterModeY_reset(SIE_BestCatInterModeY *p); |
| SIGN32 BestCatInterModeY_cmp (SIE_BestCatInterModeY *p, SIE_BestCatInterModeY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BestCatInterModeY_check(p,pie,pfx,hLOG) BestCatInterModeY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BestCatInterModeY_print(p, pfx,hLOG) BestCatInterModeY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BestCatInterModeY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BestIntraModeY flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Best_Intra_Mode_Y_0i |
| /// %unsigned 4 Best_Intra_Mode_Y_1i |
| /// %unsigned 4 Best_Intra_Mode_Y_2i |
| /// %unsigned 4 Best_Intra_Mode_Y_3i |
| /// %unsigned 4 Best_Intra_Mode_Y_4i |
| /// %unsigned 4 Best_Intra_Mode_Y_5i |
| /// %unsigned 4 Best_Intra_Mode_Y_6i |
| /// %unsigned 4 Best_Intra_Mode_Y_7i |
| /// %unsigned 4 Best_Intra_Mode_Y_8i |
| /// %unsigned 4 Best_Intra_Mode_Y_9i |
| /// %unsigned 4 Best_Intra_Mode_Y_10i |
| /// %unsigned 4 Best_Intra_Mode_Y_11i |
| /// %unsigned 4 Best_Intra_Mode_Y_12i |
| /// %unsigned 4 Best_Intra_Mode_Y_13i |
| /// %unsigned 4 Best_Intra_Mode_Y_14i |
| /// %unsigned 4 Best_Intra_Mode_Y_15i |
| /// ### |
| /// * For Best_Mode_Cat_Y == Intra16x16, Intra 16x16 mode is stored in address 0; |
| /// * For Best_Mode_Cat_Y == Intra4x4, Intra 4x4 modes for each 16 4x4 block are stored in address 0 ~ 15; |
| /// * For Best_Mode_Cat_Y == Intra8x8, Intra 8x8 modes for each 8x8 block are stored in address 0 ~ 3; |
| /// * Intra prediction modes are defined in section 5.2.1. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BestIntraModeY |
| #define h_BestIntraModeY (){} |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_0i 0x0000 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_0i 0x0000 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_0i 0 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_0i 0 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_0i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_0i 0x0000000F |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_1i 0x0000 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_1i 0x0000 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_1i 0x000000F0 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_2i 0x0001 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_2i 0x0000 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_2i 8 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_2i 8 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_2i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_2i 0x00000F00 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_3i 0x0001 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_3i 0x0000 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_3i 12 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_3i 12 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_3i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_3i 0x0000F000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_4i 0x0002 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_4i 0x0002 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_4i 16 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_4i 0 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_4i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_4i 0x000F0000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_5i 0x0002 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_5i 0x0002 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_5i 20 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_5i 4 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_5i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_5i 0x00F00000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_6i 0x0003 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_6i 0x0002 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_6i 24 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_6i 8 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_6i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_6i 0x0F000000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_7i 0x0003 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_7i 0x0002 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_7i 28 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_7i 12 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_7i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_7i 0xF0000000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_8i 0x0004 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_8i 0x0004 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_8i 0 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_8i 0 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_8i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_8i 0x0000000F |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_9i 0x0004 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_9i 0x0004 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_9i 0x000000F0 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_10i 0x0005 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_10i 0x0004 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_10i 8 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_10i 8 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_10i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_10i 0x00000F00 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_11i 0x0005 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_11i 0x0004 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_11i 12 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_11i 12 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_11i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_11i 0x0000F000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_12i 0x0006 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_12i 0x0006 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_12i 16 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_12i 0 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_12i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_12i 0x000F0000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_13i 0x0006 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_13i 0x0006 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_13i 20 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_13i 4 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_13i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_13i 0x00F00000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_14i 0x0007 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_14i 0x0006 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_14i 24 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_14i 8 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_14i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_14i 0x0F000000 |
| |
| #define BA_BestIntraModeY_Best_Intra_Mode_Y_15i 0x0007 |
| #define B16BestIntraModeY_Best_Intra_Mode_Y_15i 0x0006 |
| #define LSb32BestIntraModeY_Best_Intra_Mode_Y_15i 28 |
| #define LSb16BestIntraModeY_Best_Intra_Mode_Y_15i 12 |
| #define bBestIntraModeY_Best_Intra_Mode_Y_15i 4 |
| #define MSK32BestIntraModeY_Best_Intra_Mode_Y_15i 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BestIntraModeY { |
| /////////////////////////////////////////////////////////// |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_3i(r32) _BFGET_(r32,15,12) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_3i(r16) _BFGET_(r16,15,12) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_4i(r32) _BFGET_(r32,19,16) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_5i(r32) _BFGET_(r32,23,20) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_6i(r32) _BFGET_(r32,27,24) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_7i(r32) _BFGET_(r32,31,28) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_7i(r16) _BFGET_(r16,15,12) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_Best_Intra_Mode_Y_0i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_1i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_2i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_3i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_4i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_5i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_6i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_7i : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_11i(r32) _BFGET_(r32,15,12) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_11i(r16) _BFGET_(r16,15,12) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_12i(r32) _BFGET_(r32,19,16) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_13i(r32) _BFGET_(r32,23,20) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_14i(r32) _BFGET_(r32,27,24) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32BestIntraModeY_Best_Intra_Mode_Y_15i(r32) _BFGET_(r32,31,28) |
| #define SET32BestIntraModeY_Best_Intra_Mode_Y_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16BestIntraModeY_Best_Intra_Mode_Y_15i(r16) _BFGET_(r16,15,12) |
| #define SET16BestIntraModeY_Best_Intra_Mode_Y_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_Best_Intra_Mode_Y_8i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_9i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_10i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_11i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_12i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_13i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_14i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_15i : 4; |
| /////////////////////////////////////////////////////////// |
| } SIE_BestIntraModeY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BestIntraModeY_drvrd(SIE_BestIntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BestIntraModeY_drvwr(SIE_BestIntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BestIntraModeY_reset(SIE_BestIntraModeY *p); |
| SIGN32 BestIntraModeY_cmp (SIE_BestIntraModeY *p, SIE_BestIntraModeY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BestIntraModeY_check(p,pie,pfx,hLOG) BestIntraModeY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BestIntraModeY_print(p, pfx,hLOG) BestIntraModeY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BestIntraModeY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BestModeUV flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 2 Best_Intra_Mode_UV |
| /// ### |
| /// * Best Chroma intra prediction mode. Modes are defined in section 5.2.1. |
| /// ### |
| /// %unsigned 6 Best_Tag_UV |
| /// ### |
| /// * Best candidate's tag for UV. |
| /// ### |
| /// %% 24 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BestModeUV |
| #define h_BestModeUV (){} |
| |
| #define BA_BestModeUV_Best_Intra_Mode_UV 0x0000 |
| #define B16BestModeUV_Best_Intra_Mode_UV 0x0000 |
| #define LSb32BestModeUV_Best_Intra_Mode_UV 0 |
| #define LSb16BestModeUV_Best_Intra_Mode_UV 0 |
| #define bBestModeUV_Best_Intra_Mode_UV 2 |
| #define MSK32BestModeUV_Best_Intra_Mode_UV 0x00000003 |
| |
| #define BA_BestModeUV_Best_Tag_UV 0x0000 |
| #define B16BestModeUV_Best_Tag_UV 0x0000 |
| #define LSb32BestModeUV_Best_Tag_UV 2 |
| #define LSb16BestModeUV_Best_Tag_UV 2 |
| #define bBestModeUV_Best_Tag_UV 6 |
| #define MSK32BestModeUV_Best_Tag_UV 0x000000FC |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BestModeUV { |
| /////////////////////////////////////////////////////////// |
| #define GET32BestModeUV_Best_Intra_Mode_UV(r32) _BFGET_(r32, 1, 0) |
| #define SET32BestModeUV_Best_Intra_Mode_UV(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16BestModeUV_Best_Intra_Mode_UV(r16) _BFGET_(r16, 1, 0) |
| #define SET16BestModeUV_Best_Intra_Mode_UV(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32BestModeUV_Best_Tag_UV(r32) _BFGET_(r32, 7, 2) |
| #define SET32BestModeUV_Best_Tag_UV(r32,v) _BFSET_(r32, 7, 2,v) |
| #define GET16BestModeUV_Best_Tag_UV(r16) _BFGET_(r16, 7, 2) |
| #define SET16BestModeUV_Best_Tag_UV(r16,v) _BFSET_(r16, 7, 2,v) |
| |
| UNSG32 u_Best_Intra_Mode_UV : 2; |
| UNSG32 u_Best_Tag_UV : 6; |
| UNSG32 RSVDx0_b8 : 24; |
| /////////////////////////////////////////////////////////// |
| } SIE_BestModeUV; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BestModeUV_drvrd(SIE_BestModeUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BestModeUV_drvwr(SIE_BestModeUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BestModeUV_reset(SIE_BestModeUV *p); |
| SIGN32 BestModeUV_cmp (SIE_BestModeUV *p, SIE_BestModeUV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BestModeUV_check(p,pie,pfx,hLOG) BestModeUV_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BestModeUV_print(p, pfx,hLOG) BestModeUV_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BestModeUV |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RDMBResultResp flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 BestCatInterModeY |
| /// $BestCatInterModeY BestCatInterModeY REG |
| /// @ 0x00004 (P) |
| /// # 0x00004 BestModeUV |
| /// $BestModeUV BestModeUV REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RDMBResultResp |
| #define h_RDMBResultResp (){} |
| |
| #define RA_RDMBResultResp_BestCatInterModeY 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RDMBResultResp_BestModeUV 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RDMBResultResp { |
| /////////////////////////////////////////////////////////// |
| SIE_BestCatInterModeY ie_BestCatInterModeY; |
| /////////////////////////////////////////////////////////// |
| SIE_BestModeUV ie_BestModeUV; |
| /////////////////////////////////////////////////////////// |
| } SIE_RDMBResultResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RDMBResultResp_drvrd(SIE_RDMBResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RDMBResultResp_drvwr(SIE_RDMBResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RDMBResultResp_reset(SIE_RDMBResultResp *p); |
| SIGN32 RDMBResultResp_cmp (SIE_RDMBResultResp *p, SIE_RDMBResultResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RDMBResultResp_check(p,pie,pfx,hLOG) RDMBResultResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RDMBResultResp_print(p, pfx,hLOG) RDMBResultResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RDMBResultResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RDMBIntraModeY flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 BestIntraModeY |
| /// $BestIntraModeY BestIntraModeY REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RDMBIntraModeY |
| #define h_RDMBIntraModeY (){} |
| |
| #define RA_RDMBIntraModeY_BestIntraModeY 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RDMBIntraModeY { |
| /////////////////////////////////////////////////////////// |
| SIE_BestIntraModeY ie_BestIntraModeY; |
| /////////////////////////////////////////////////////////// |
| } SIE_RDMBIntraModeY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RDMBIntraModeY_drvrd(SIE_RDMBIntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RDMBIntraModeY_drvwr(SIE_RDMBIntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RDMBIntraModeY_reset(SIE_RDMBIntraModeY *p); |
| SIGN32 RDMBIntraModeY_cmp (SIE_RDMBIntraModeY *p, SIE_RDMBIntraModeY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RDMBIntraModeY_check(p,pie,pfx,hLOG) RDMBIntraModeY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RDMBIntraModeY_print(p, pfx,hLOG) RDMBIntraModeY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RDMBIntraModeY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RD16x16ResultResp flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 BestCatInterModeY |
| /// $BestCatInterModeY BestCatInterModeY REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RD16x16ResultResp |
| #define h_RD16x16ResultResp (){} |
| |
| #define RA_RD16x16ResultResp_BestCatInterModeY 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RD16x16ResultResp { |
| /////////////////////////////////////////////////////////// |
| SIE_BestCatInterModeY ie_BestCatInterModeY; |
| /////////////////////////////////////////////////////////// |
| } SIE_RD16x16ResultResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RD16x16ResultResp_drvrd(SIE_RD16x16ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RD16x16ResultResp_drvwr(SIE_RD16x16ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RD16x16ResultResp_reset(SIE_RD16x16ResultResp *p); |
| SIGN32 RD16x16ResultResp_cmp (SIE_RD16x16ResultResp *p, SIE_RD16x16ResultResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RD16x16ResultResp_check(p,pie,pfx,hLOG) RD16x16ResultResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RD16x16ResultResp_print(p, pfx,hLOG) RD16x16ResultResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RD16x16ResultResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RD16x16IntraModeY flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 BestIntraModeY |
| /// $BestIntraModeY BestIntraModeY REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RD16x16IntraModeY |
| #define h_RD16x16IntraModeY (){} |
| |
| #define RA_RD16x16IntraModeY_BestIntraModeY 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RD16x16IntraModeY { |
| /////////////////////////////////////////////////////////// |
| SIE_BestIntraModeY ie_BestIntraModeY; |
| /////////////////////////////////////////////////////////// |
| } SIE_RD16x16IntraModeY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RD16x16IntraModeY_drvrd(SIE_RD16x16IntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RD16x16IntraModeY_drvwr(SIE_RD16x16IntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RD16x16IntraModeY_reset(SIE_RD16x16IntraModeY *p); |
| SIGN32 RD16x16IntraModeY_cmp (SIE_RD16x16IntraModeY *p, SIE_RD16x16IntraModeY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RD16x16IntraModeY_check(p,pie,pfx,hLOG) RD16x16IntraModeY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RD16x16IntraModeY_print(p, pfx,hLOG) RD16x16IntraModeY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RD16x16IntraModeY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RD8x8ResultResp flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 SADY |
| /// ### |
| /// * SAD for Luma |
| /// ### |
| /// %unsigned 4 Best_Intra8x8_Mode_Y |
| /// ### |
| /// * Best intra8x8 prediction mode for current Luma 8x8 block |
| /// ### |
| /// %unsigned 6 Best_Tag_Y |
| /// ### |
| /// * Best candidate's tag for current Luma 8x8 block |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RD8x8ResultResp |
| #define h_RD8x8ResultResp (){} |
| |
| #define BA_RD8x8ResultResp_SADY 0x0000 |
| #define B16RD8x8ResultResp_SADY 0x0000 |
| #define LSb32RD8x8ResultResp_SADY 0 |
| #define LSb16RD8x8ResultResp_SADY 0 |
| #define bRD8x8ResultResp_SADY 16 |
| #define MSK32RD8x8ResultResp_SADY 0x0000FFFF |
| |
| #define BA_RD8x8ResultResp_Best_Intra8x8_Mode_Y 0x0002 |
| #define B16RD8x8ResultResp_Best_Intra8x8_Mode_Y 0x0002 |
| #define LSb32RD8x8ResultResp_Best_Intra8x8_Mode_Y 16 |
| #define LSb16RD8x8ResultResp_Best_Intra8x8_Mode_Y 0 |
| #define bRD8x8ResultResp_Best_Intra8x8_Mode_Y 4 |
| #define MSK32RD8x8ResultResp_Best_Intra8x8_Mode_Y 0x000F0000 |
| |
| #define BA_RD8x8ResultResp_Best_Tag_Y 0x0002 |
| #define B16RD8x8ResultResp_Best_Tag_Y 0x0002 |
| #define LSb32RD8x8ResultResp_Best_Tag_Y 20 |
| #define LSb16RD8x8ResultResp_Best_Tag_Y 4 |
| #define bRD8x8ResultResp_Best_Tag_Y 6 |
| #define MSK32RD8x8ResultResp_Best_Tag_Y 0x03F00000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RD8x8ResultResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32RD8x8ResultResp_SADY(r32) _BFGET_(r32,15, 0) |
| #define SET32RD8x8ResultResp_SADY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RD8x8ResultResp_SADY(r16) _BFGET_(r16,15, 0) |
| #define SET16RD8x8ResultResp_SADY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RD8x8ResultResp_Best_Intra8x8_Mode_Y(r32) _BFGET_(r32,19,16) |
| #define SET32RD8x8ResultResp_Best_Intra8x8_Mode_Y(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RD8x8ResultResp_Best_Intra8x8_Mode_Y(r16) _BFGET_(r16, 3, 0) |
| #define SET16RD8x8ResultResp_Best_Intra8x8_Mode_Y(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RD8x8ResultResp_Best_Tag_Y(r32) _BFGET_(r32,25,20) |
| #define SET32RD8x8ResultResp_Best_Tag_Y(r32,v) _BFSET_(r32,25,20,v) |
| #define GET16RD8x8ResultResp_Best_Tag_Y(r16) _BFGET_(r16, 9, 4) |
| #define SET16RD8x8ResultResp_Best_Tag_Y(r16,v) _BFSET_(r16, 9, 4,v) |
| |
| UNSG32 u_SADY : 16; |
| UNSG32 u_Best_Intra8x8_Mode_Y : 4; |
| UNSG32 u_Best_Tag_Y : 6; |
| UNSG32 RSVDx0_b26 : 6; |
| /////////////////////////////////////////////////////////// |
| } SIE_RD8x8ResultResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RD8x8ResultResp_drvrd(SIE_RD8x8ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RD8x8ResultResp_drvwr(SIE_RD8x8ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RD8x8ResultResp_reset(SIE_RD8x8ResultResp *p); |
| SIGN32 RD8x8ResultResp_cmp (SIE_RD8x8ResultResp *p, SIE_RD8x8ResultResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RD8x8ResultResp_check(p,pie,pfx,hLOG) RD8x8ResultResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RD8x8ResultResp_print(p, pfx,hLOG) RD8x8ResultResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RD8x8ResultResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RD4x4ResultResp flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Best_Intra4x4_Mode_Y |
| /// ### |
| /// * Best intra4x4 prediction mode for current Luma 4x4 block |
| /// ### |
| /// %unsigned 6 Best_Tag_Y |
| /// ### |
| /// * Best candidate's tag for current Luma 4x4 block |
| /// ### |
| /// %% 22 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RD4x4ResultResp |
| #define h_RD4x4ResultResp (){} |
| |
| #define BA_RD4x4ResultResp_Best_Intra4x4_Mode_Y 0x0000 |
| #define B16RD4x4ResultResp_Best_Intra4x4_Mode_Y 0x0000 |
| #define LSb32RD4x4ResultResp_Best_Intra4x4_Mode_Y 0 |
| #define LSb16RD4x4ResultResp_Best_Intra4x4_Mode_Y 0 |
| #define bRD4x4ResultResp_Best_Intra4x4_Mode_Y 4 |
| #define MSK32RD4x4ResultResp_Best_Intra4x4_Mode_Y 0x0000000F |
| |
| #define BA_RD4x4ResultResp_Best_Tag_Y 0x0000 |
| #define B16RD4x4ResultResp_Best_Tag_Y 0x0000 |
| #define LSb32RD4x4ResultResp_Best_Tag_Y 4 |
| #define LSb16RD4x4ResultResp_Best_Tag_Y 4 |
| #define bRD4x4ResultResp_Best_Tag_Y 6 |
| #define MSK32RD4x4ResultResp_Best_Tag_Y 0x000003F0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RD4x4ResultResp { |
| /////////////////////////////////////////////////////////// |
| #define GET32RD4x4ResultResp_Best_Intra4x4_Mode_Y(r32) _BFGET_(r32, 3, 0) |
| #define SET32RD4x4ResultResp_Best_Intra4x4_Mode_Y(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RD4x4ResultResp_Best_Intra4x4_Mode_Y(r16) _BFGET_(r16, 3, 0) |
| #define SET16RD4x4ResultResp_Best_Intra4x4_Mode_Y(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RD4x4ResultResp_Best_Tag_Y(r32) _BFGET_(r32, 9, 4) |
| #define SET32RD4x4ResultResp_Best_Tag_Y(r32,v) _BFSET_(r32, 9, 4,v) |
| #define GET16RD4x4ResultResp_Best_Tag_Y(r16) _BFGET_(r16, 9, 4) |
| #define SET16RD4x4ResultResp_Best_Tag_Y(r16,v) _BFSET_(r16, 9, 4,v) |
| |
| UNSG32 u_Best_Intra4x4_Mode_Y : 4; |
| UNSG32 u_Best_Tag_Y : 6; |
| UNSG32 RSVDx0_b10 : 22; |
| /////////////////////////////////////////////////////////// |
| } SIE_RD4x4ResultResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RD4x4ResultResp_drvrd(SIE_RD4x4ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RD4x4ResultResp_drvwr(SIE_RD4x4ResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RD4x4ResultResp_reset(SIE_RD4x4ResultResp *p); |
| SIGN32 RD4x4ResultResp_cmp (SIE_RD4x4ResultResp *p, SIE_RD4x4ResultResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RD4x4ResultResp_check(p,pie,pfx,hLOG) RD4x4ResultResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RD4x4ResultResp_print(p, pfx,hLOG) RD4x4ResultResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RD4x4ResultResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RDUVResultResp flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 BestModeUV |
| /// $BestModeUV BestModeUV REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RDUVResultResp |
| #define h_RDUVResultResp (){} |
| |
| #define RA_RDUVResultResp_BestModeUV 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RDUVResultResp { |
| /////////////////////////////////////////////////////////// |
| SIE_BestModeUV ie_BestModeUV; |
| /////////////////////////////////////////////////////////// |
| } SIE_RDUVResultResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RDUVResultResp_drvrd(SIE_RDUVResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RDUVResultResp_drvwr(SIE_RDUVResultResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RDUVResultResp_reset(SIE_RDUVResultResp *p); |
| SIGN32 RDUVResultResp_cmp (SIE_RDUVResultResp *p, SIE_RDUVResultResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RDUVResultResp_check(p,pie,pfx,hLOG) RDUVResultResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RDUVResultResp_print(p, pfx,hLOG) RDUVResultResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RDUVResultResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BinSSD flat (8,2) |
| /// ### |
| /// * Bin and SSD collected by trial rounding quantization |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %% 8 # Stuffing bits... |
| /// %unsigned 24 ssd |
| /// %unsigned 14 bin |
| /// %% 18 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BinSSD |
| #define h_BinSSD (){} |
| |
| #define BA_BinSSD_ssd 0x0001 |
| #define B16BinSSD_ssd 0x0000 |
| #define LSb32BinSSD_ssd 8 |
| #define LSb16BinSSD_ssd 8 |
| #define bBinSSD_ssd 24 |
| #define MSK32BinSSD_ssd 0xFFFFFF00 |
| |
| #define BA_BinSSD_bin 0x0004 |
| #define B16BinSSD_bin 0x0004 |
| #define LSb32BinSSD_bin 0 |
| #define LSb16BinSSD_bin 0 |
| #define bBinSSD_bin 14 |
| #define MSK32BinSSD_bin 0x00003FFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BinSSD { |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSD_ssd(r32) _BFGET_(r32,31, 8) |
| #define SET32BinSSD_ssd(r32,v) _BFSET_(r32,31, 8,v) |
| |
| UNSG32 RSVDx0 : 8; |
| UNSG32 u_ssd : 24; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSD_bin(r32) _BFGET_(r32,13, 0) |
| #define SET32BinSSD_bin(r32,v) _BFSET_(r32,13, 0,v) |
| #define GET16BinSSD_bin(r16) _BFGET_(r16,13, 0) |
| #define SET16BinSSD_bin(r16,v) _BFSET_(r16,13, 0,v) |
| |
| UNSG32 u_bin : 14; |
| UNSG32 RSVDx4_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| } SIE_BinSSD; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BinSSD_drvrd(SIE_BinSSD *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BinSSD_drvwr(SIE_BinSSD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BinSSD_reset(SIE_BinSSD *p); |
| SIGN32 BinSSD_cmp (SIE_BinSSD *p, SIE_BinSSD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BinSSD_check(p,pie,pfx,hLOG) BinSSD_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BinSSD_print(p, pfx,hLOG) BinSSD_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BinSSD |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BinSSD5 flat (4,4) |
| /// ### |
| /// * [0]: for rounding[0] (closer to 0); |
| /// * [1]: for rounding[1] (target); |
| /// * [2]: for rounding[2] (closer to 0.5); |
| /// * [3]: for 4/5*Qstep & rounding[1]; |
| /// * [4]: for trellis quantization result (or rounding[1] when QuantMode=0); |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 bin_ssd |
| /// $BinSSD bin_ssd REG [5] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 40B, bits: 320b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BinSSD5 |
| #define h_BinSSD5 (){} |
| |
| #define RA_BinSSD5_bin_ssd 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BinSSD5 { |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSD ie_bin_ssd[5]; |
| /////////////////////////////////////////////////////////// |
| } SIE_BinSSD5; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BinSSD5_drvrd(SIE_BinSSD5 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BinSSD5_drvwr(SIE_BinSSD5 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BinSSD5_reset(SIE_BinSSD5 *p); |
| SIGN32 BinSSD5_cmp (SIE_BinSSD5 *p, SIE_BinSSD5 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BinSSD5_check(p,pie,pfx,hLOG) BinSSD5_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BinSSD5_print(p, pfx,hLOG) BinSSD5_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BinSSD5 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BinSSDMBResp flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 bin_ssd_mb |
| /// $BinSSD5 bin_ssd_mb REG [3] |
| /// ### |
| /// * {bin,SSD}[Y/U/V][5] |
| /// ### |
| /// @ 0x00078 (P) |
| /// %unsigned 16 SADY |
| /// ### |
| /// * SAD for Luma |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x0007C (W-) |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 128B, bits: 1024b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BinSSDMBResp |
| #define h_BinSSDMBResp (){} |
| |
| #define RA_BinSSDMBResp_bin_ssd_mb 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BinSSDMBResp_SADY 0x0078 |
| #define B16BinSSDMBResp_SADY 0x0078 |
| #define LSb32BinSSDMBResp_SADY 0 |
| #define LSb16BinSSDMBResp_SADY 0 |
| #define bBinSSDMBResp_SADY 16 |
| #define MSK32BinSSDMBResp_SADY 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BinSSDMBResp { |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSD5 ie_bin_ssd_mb[3]; |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDMBResp_SADY(r32) _BFGET_(r32,15, 0) |
| #define SET32BinSSDMBResp_SADY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16BinSSDMBResp_SADY(r16) _BFGET_(r16,15, 0) |
| #define SET16BinSSDMBResp_SADY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_SADY : 16; |
| UNSG32 RSVDx78_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx7C [4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_BinSSDMBResp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BinSSDMBResp_drvrd(SIE_BinSSDMBResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BinSSDMBResp_drvwr(SIE_BinSSDMBResp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BinSSDMBResp_reset(SIE_BinSSDMBResp *p); |
| SIGN32 BinSSDMBResp_cmp (SIE_BinSSDMBResp *p, SIE_BinSSDMBResp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BinSSDMBResp_check(p,pie,pfx,hLOG) BinSSDMBResp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BinSSDMBResp_print(p, pfx,hLOG) BinSSDMBResp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BinSSDMBResp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CoeffCmdY flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 TO_YDC |
| /// $CoeffCmd TO_YDC REG |
| /// ### |
| /// * Luma DC traling ones. Only low 16 bit is used. |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 TO_Y |
| /// $CoeffCmd TO_Y REG [8] |
| /// ### |
| /// * Traling ones for 16 4x4 Luma blocks. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 36B, bits: 288b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CoeffCmdY |
| #define h_CoeffCmdY (){} |
| |
| #define RA_CoeffCmdY_TO_YDC 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CoeffCmdY_TO_Y 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CoeffCmdY { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_YDC; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_Y[8]; |
| /////////////////////////////////////////////////////////// |
| } SIE_CoeffCmdY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CoeffCmdY_drvrd(SIE_CoeffCmdY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CoeffCmdY_drvwr(SIE_CoeffCmdY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CoeffCmdY_reset(SIE_CoeffCmdY *p); |
| SIGN32 CoeffCmdY_cmp (SIE_CoeffCmdY *p, SIE_CoeffCmdY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CoeffCmdY_check(p,pie,pfx,hLOG) CoeffCmdY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CoeffCmdY_print(p, pfx,hLOG) CoeffCmdY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CoeffCmdY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CoeffCmdUV flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 TO_UDC |
| /// $CoeffCmd TO_UDC REG |
| /// ### |
| /// * Chroma U DC traling ones. Only low 16 bit is used. |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 TO_U |
| /// $CoeffCmd TO_U REG [2] |
| /// ### |
| /// * Traling ones for 4 4x4 Chroma U blocks. |
| /// ### |
| /// @ 0x0000C (P) |
| /// # 0x0000C TO_VDC |
| /// $CoeffCmd TO_VDC REG |
| /// ### |
| /// * Chroma V DC traling ones. Only low 16 bit is used. |
| /// ### |
| /// @ 0x00010 (P) |
| /// # 0x00010 TO_V |
| /// $CoeffCmd TO_V REG [2] |
| /// ### |
| /// * Traling ones for 4 4x4 Chroma V blocks. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 24B, bits: 192b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CoeffCmdUV |
| #define h_CoeffCmdUV (){} |
| |
| #define RA_CoeffCmdUV_TO_UDC 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CoeffCmdUV_TO_U 0x0004 |
| /////////////////////////////////////////////////////////// |
| #define RA_CoeffCmdUV_TO_VDC 0x000C |
| /////////////////////////////////////////////////////////// |
| #define RA_CoeffCmdUV_TO_V 0x0010 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CoeffCmdUV { |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_UDC; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_U[2]; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_VDC; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_TO_V[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_CoeffCmdUV; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CoeffCmdUV_drvrd(SIE_CoeffCmdUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CoeffCmdUV_drvwr(SIE_CoeffCmdUV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CoeffCmdUV_reset(SIE_CoeffCmdUV *p); |
| SIGN32 CoeffCmdUV_cmp (SIE_CoeffCmdUV *p, SIE_CoeffCmdUV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CoeffCmdUV_check(p,pie,pfx,hLOG) CoeffCmdUV_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CoeffCmdUV_print(p, pfx,hLOG) CoeffCmdUV_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CoeffCmdUV |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CMBINFO flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 23 score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 23 Y_score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x00008 (P) |
| /// %unsigned 23 UV_score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x0000C (P) |
| /// # 0x0000C BestCatInterModeY |
| /// $BestCatInterModeY BestCatInterModeY REG |
| /// @ 0x00010 (P) |
| /// # 0x00010 BestModeUV |
| /// $BestModeUV BestModeUV REG |
| /// @ 0x00014 (P) |
| /// # 0x00014 BestIntraModeY |
| /// $BestIntraModeY BestIntraModeY REG |
| /// @ 0x0001C (W-) |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// @ 0x00020 (P) |
| /// # 0x00020 BinSSDMBResp |
| /// $BinSSDMBResp BinSSDMBResp REG |
| /// ### |
| /// * {bin,SSD}[Y/U/V][5] |
| /// ### |
| /// @ 0x000A0 (P) |
| /// # 0x000A0 IPROCBPCmdResp |
| /// $IPROCBPCmdResp IPROCBPCmdResp REG |
| /// ### |
| /// * CBP, CBF and CBPDC for current MB |
| /// ### |
| /// @ 0x000A8 (P) |
| /// # 0x000A8 CoeffCmdY |
| /// $CoeffCmdY CoeffCmdY REG |
| /// @ 0x000CC (P) |
| /// # 0x000CC CoeffCmdUV |
| /// $CoeffCmdUV CoeffCmdUV REG |
| /// @ 0x000E4 (W-) |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 232B, bits: 1856b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CMBINFO |
| #define h_CMBINFO (){} |
| |
| #define BA_CMBINFO_score 0x0000 |
| #define B16CMBINFO_score 0x0000 |
| #define LSb32CMBINFO_score 0 |
| #define LSb16CMBINFO_score 0 |
| #define bCMBINFO_score 23 |
| #define MSK32CMBINFO_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CMBINFO_Y_score 0x0004 |
| #define B16CMBINFO_Y_score 0x0004 |
| #define LSb32CMBINFO_Y_score 0 |
| #define LSb16CMBINFO_Y_score 0 |
| #define bCMBINFO_Y_score 23 |
| #define MSK32CMBINFO_Y_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CMBINFO_UV_score 0x0008 |
| #define B16CMBINFO_UV_score 0x0008 |
| #define LSb32CMBINFO_UV_score 0 |
| #define LSb16CMBINFO_UV_score 0 |
| #define bCMBINFO_UV_score 23 |
| #define MSK32CMBINFO_UV_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_BestCatInterModeY 0x000C |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_BestModeUV 0x0010 |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_BestIntraModeY 0x0014 |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_BinSSDMBResp 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_IPROCBPCmdResp 0x00A0 |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_CoeffCmdY 0x00A8 |
| /////////////////////////////////////////////////////////// |
| #define RA_CMBINFO_CoeffCmdUV 0x00CC |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CMBINFO { |
| /////////////////////////////////////////////////////////// |
| #define GET32CMBINFO_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CMBINFO_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_score : 23; |
| UNSG32 RSVDx0_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| #define GET32CMBINFO_Y_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CMBINFO_Y_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_Y_score : 23; |
| UNSG32 RSVDx4_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| #define GET32CMBINFO_UV_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CMBINFO_UV_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_UV_score : 23; |
| UNSG32 RSVDx8_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| SIE_BestCatInterModeY ie_BestCatInterModeY; |
| /////////////////////////////////////////////////////////// |
| SIE_BestModeUV ie_BestModeUV; |
| /////////////////////////////////////////////////////////// |
| SIE_BestIntraModeY ie_BestIntraModeY; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx1C [4]; |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSDMBResp ie_BinSSDMBResp; |
| /////////////////////////////////////////////////////////// |
| SIE_IPROCBPCmdResp ie_IPROCBPCmdResp; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmdY ie_CoeffCmdY; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmdUV ie_CoeffCmdUV; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxE4 [4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_CMBINFO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CMBINFO_drvrd(SIE_CMBINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CMBINFO_drvwr(SIE_CMBINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CMBINFO_reset(SIE_CMBINFO *p); |
| SIGN32 CMBINFO_cmp (SIE_CMBINFO *p, SIE_CMBINFO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CMBINFO_check(p,pie,pfx,hLOG) CMBINFO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CMBINFO_print(p, pfx,hLOG) CMBINFO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CMBINFO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CY16x16INFO flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 23 score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 16 SADY |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00008 (P) |
| /// # 0x00008 bestCatInterModeY |
| /// $BestCatInterModeY bestCatInterModeY REG |
| /// @ 0x0000C (P) |
| /// # 0x0000C bestIntraModeY |
| /// $BestIntraModeY bestIntraModeY REG |
| /// @ 0x00014 (W-) |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// @ 0x00018 (P) |
| /// # 0x00018 bin_ssd_y |
| /// $BinSSD5 bin_ssd_y REG |
| /// ### |
| /// * {bin,SSD}[5] |
| /// ### |
| /// @ 0x00040 (P) |
| /// %unsigned 4 CBPDCY |
| /// %unsigned 4 CBPY |
| /// %unsigned 16 CBFY |
| /// %unsigned 1 CBF16x16IDC |
| /// %% 7 # Stuffing bits... |
| /// @ 0x00044 (P) |
| /// # 0x00044 CoeffCmdY |
| /// $CoeffCmdY CoeffCmdY REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 104B, bits: 832b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CY16x16INFO |
| #define h_CY16x16INFO (){} |
| |
| #define BA_CY16x16INFO_score 0x0000 |
| #define B16CY16x16INFO_score 0x0000 |
| #define LSb32CY16x16INFO_score 0 |
| #define LSb16CY16x16INFO_score 0 |
| #define bCY16x16INFO_score 23 |
| #define MSK32CY16x16INFO_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CY16x16INFO_SADY 0x0004 |
| #define B16CY16x16INFO_SADY 0x0004 |
| #define LSb32CY16x16INFO_SADY 0 |
| #define LSb16CY16x16INFO_SADY 0 |
| #define bCY16x16INFO_SADY 16 |
| #define MSK32CY16x16INFO_SADY 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_CY16x16INFO_bestCatInterModeY 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_CY16x16INFO_bestIntraModeY 0x000C |
| /////////////////////////////////////////////////////////// |
| #define RA_CY16x16INFO_bin_ssd_y 0x0018 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CY16x16INFO_CBPDCY 0x0040 |
| #define B16CY16x16INFO_CBPDCY 0x0040 |
| #define LSb32CY16x16INFO_CBPDCY 0 |
| #define LSb16CY16x16INFO_CBPDCY 0 |
| #define bCY16x16INFO_CBPDCY 4 |
| #define MSK32CY16x16INFO_CBPDCY 0x0000000F |
| |
| #define BA_CY16x16INFO_CBPY 0x0040 |
| #define B16CY16x16INFO_CBPY 0x0040 |
| #define LSb32CY16x16INFO_CBPY 4 |
| #define LSb16CY16x16INFO_CBPY 4 |
| #define bCY16x16INFO_CBPY 4 |
| #define MSK32CY16x16INFO_CBPY 0x000000F0 |
| |
| #define BA_CY16x16INFO_CBFY 0x0041 |
| #define B16CY16x16INFO_CBFY 0x0040 |
| #define LSb32CY16x16INFO_CBFY 8 |
| #define LSb16CY16x16INFO_CBFY 8 |
| #define bCY16x16INFO_CBFY 16 |
| #define MSK32CY16x16INFO_CBFY 0x00FFFF00 |
| |
| #define BA_CY16x16INFO_CBF16x16IDC 0x0043 |
| #define B16CY16x16INFO_CBF16x16IDC 0x0042 |
| #define LSb32CY16x16INFO_CBF16x16IDC 24 |
| #define LSb16CY16x16INFO_CBF16x16IDC 8 |
| #define bCY16x16INFO_CBF16x16IDC 1 |
| #define MSK32CY16x16INFO_CBF16x16IDC 0x01000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CY16x16INFO_CoeffCmdY 0x0044 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CY16x16INFO { |
| /////////////////////////////////////////////////////////// |
| #define GET32CY16x16INFO_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CY16x16INFO_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_score : 23; |
| UNSG32 RSVDx0_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| #define GET32CY16x16INFO_SADY(r32) _BFGET_(r32,15, 0) |
| #define SET32CY16x16INFO_SADY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16CY16x16INFO_SADY(r16) _BFGET_(r16,15, 0) |
| #define SET16CY16x16INFO_SADY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_SADY : 16; |
| UNSG32 RSVDx4_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| SIE_BestCatInterModeY ie_bestCatInterModeY; |
| /////////////////////////////////////////////////////////// |
| SIE_BestIntraModeY ie_bestIntraModeY; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx14 [4]; |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSD5 ie_bin_ssd_y; |
| /////////////////////////////////////////////////////////// |
| #define GET32CY16x16INFO_CBPDCY(r32) _BFGET_(r32, 3, 0) |
| #define SET32CY16x16INFO_CBPDCY(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16CY16x16INFO_CBPDCY(r16) _BFGET_(r16, 3, 0) |
| #define SET16CY16x16INFO_CBPDCY(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32CY16x16INFO_CBPY(r32) _BFGET_(r32, 7, 4) |
| #define SET32CY16x16INFO_CBPY(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16CY16x16INFO_CBPY(r16) _BFGET_(r16, 7, 4) |
| #define SET16CY16x16INFO_CBPY(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32CY16x16INFO_CBFY(r32) _BFGET_(r32,23, 8) |
| #define SET32CY16x16INFO_CBFY(r32,v) _BFSET_(r32,23, 8,v) |
| |
| #define GET32CY16x16INFO_CBF16x16IDC(r32) _BFGET_(r32,24,24) |
| #define SET32CY16x16INFO_CBF16x16IDC(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16CY16x16INFO_CBF16x16IDC(r16) _BFGET_(r16, 8, 8) |
| #define SET16CY16x16INFO_CBF16x16IDC(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| UNSG32 u_CBPDCY : 4; |
| UNSG32 u_CBPY : 4; |
| UNSG32 u_CBFY : 16; |
| UNSG32 u_CBF16x16IDC : 1; |
| UNSG32 RSVDx40_b25 : 7; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmdY ie_CoeffCmdY; |
| /////////////////////////////////////////////////////////// |
| } SIE_CY16x16INFO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CY16x16INFO_drvrd(SIE_CY16x16INFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CY16x16INFO_drvwr(SIE_CY16x16INFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CY16x16INFO_reset(SIE_CY16x16INFO *p); |
| SIGN32 CY16x16INFO_cmp (SIE_CY16x16INFO *p, SIE_CY16x16INFO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CY16x16INFO_check(p,pie,pfx,hLOG) CY16x16INFO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CY16x16INFO_print(p, pfx,hLOG) CY16x16INFO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CY16x16INFO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CUVINFO flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 23 score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// # 0x00004 bestIntraModeUV |
| /// $BestModeUV bestIntraModeUV REG |
| /// @ 0x00008 (P) |
| /// # 0x00008 bin_ssd_uv |
| /// $BinSSD5 bin_ssd_uv REG [2] |
| /// ### |
| /// * {bin,SSD}[U/V][5F] |
| /// ### |
| /// @ 0x00058 (P) |
| /// %unsigned 2 CBPDCUV |
| /// %unsigned 2 CBPUV |
| /// %unsigned 8 CBFUV |
| /// %unsigned 1 CBFUDC |
| /// %unsigned 1 CBFVDC |
| /// %% 18 # Stuffing bits... |
| /// @ 0x0005C (P) |
| /// # 0x0005C CoeffCmdUV |
| /// $CoeffCmdUV CoeffCmdUV REG |
| /// @ 0x00074 (W-) |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 120B, bits: 960b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CUVINFO |
| #define h_CUVINFO (){} |
| |
| #define BA_CUVINFO_score 0x0000 |
| #define B16CUVINFO_score 0x0000 |
| #define LSb32CUVINFO_score 0 |
| #define LSb16CUVINFO_score 0 |
| #define bCUVINFO_score 23 |
| #define MSK32CUVINFO_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_CUVINFO_bestIntraModeUV 0x0004 |
| /////////////////////////////////////////////////////////// |
| #define RA_CUVINFO_bin_ssd_uv 0x0008 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CUVINFO_CBPDCUV 0x0058 |
| #define B16CUVINFO_CBPDCUV 0x0058 |
| #define LSb32CUVINFO_CBPDCUV 0 |
| #define LSb16CUVINFO_CBPDCUV 0 |
| #define bCUVINFO_CBPDCUV 2 |
| #define MSK32CUVINFO_CBPDCUV 0x00000003 |
| |
| #define BA_CUVINFO_CBPUV 0x0058 |
| #define B16CUVINFO_CBPUV 0x0058 |
| #define LSb32CUVINFO_CBPUV 2 |
| #define LSb16CUVINFO_CBPUV 2 |
| #define bCUVINFO_CBPUV 2 |
| #define MSK32CUVINFO_CBPUV 0x0000000C |
| |
| #define BA_CUVINFO_CBFUV 0x0058 |
| #define B16CUVINFO_CBFUV 0x0058 |
| #define LSb32CUVINFO_CBFUV 4 |
| #define LSb16CUVINFO_CBFUV 4 |
| #define bCUVINFO_CBFUV 8 |
| #define MSK32CUVINFO_CBFUV 0x00000FF0 |
| |
| #define BA_CUVINFO_CBFUDC 0x0059 |
| #define B16CUVINFO_CBFUDC 0x0058 |
| #define LSb32CUVINFO_CBFUDC 12 |
| #define LSb16CUVINFO_CBFUDC 12 |
| #define bCUVINFO_CBFUDC 1 |
| #define MSK32CUVINFO_CBFUDC 0x00001000 |
| |
| #define BA_CUVINFO_CBFVDC 0x0059 |
| #define B16CUVINFO_CBFVDC 0x0058 |
| #define LSb32CUVINFO_CBFVDC 13 |
| #define LSb16CUVINFO_CBFVDC 13 |
| #define bCUVINFO_CBFVDC 1 |
| #define MSK32CUVINFO_CBFVDC 0x00002000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CUVINFO_CoeffCmdUV 0x005C |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CUVINFO { |
| /////////////////////////////////////////////////////////// |
| #define GET32CUVINFO_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CUVINFO_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_score : 23; |
| UNSG32 RSVDx0_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| SIE_BestModeUV ie_bestIntraModeUV; |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSD5 ie_bin_ssd_uv[2]; |
| /////////////////////////////////////////////////////////// |
| #define GET32CUVINFO_CBPDCUV(r32) _BFGET_(r32, 1, 0) |
| #define SET32CUVINFO_CBPDCUV(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16CUVINFO_CBPDCUV(r16) _BFGET_(r16, 1, 0) |
| #define SET16CUVINFO_CBPDCUV(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32CUVINFO_CBPUV(r32) _BFGET_(r32, 3, 2) |
| #define SET32CUVINFO_CBPUV(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16CUVINFO_CBPUV(r16) _BFGET_(r16, 3, 2) |
| #define SET16CUVINFO_CBPUV(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32CUVINFO_CBFUV(r32) _BFGET_(r32,11, 4) |
| #define SET32CUVINFO_CBFUV(r32,v) _BFSET_(r32,11, 4,v) |
| #define GET16CUVINFO_CBFUV(r16) _BFGET_(r16,11, 4) |
| #define SET16CUVINFO_CBFUV(r16,v) _BFSET_(r16,11, 4,v) |
| |
| #define GET32CUVINFO_CBFUDC(r32) _BFGET_(r32,12,12) |
| #define SET32CUVINFO_CBFUDC(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16CUVINFO_CBFUDC(r16) _BFGET_(r16,12,12) |
| #define SET16CUVINFO_CBFUDC(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32CUVINFO_CBFVDC(r32) _BFGET_(r32,13,13) |
| #define SET32CUVINFO_CBFVDC(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16CUVINFO_CBFVDC(r16) _BFGET_(r16,13,13) |
| #define SET16CUVINFO_CBFVDC(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_CBPDCUV : 2; |
| UNSG32 u_CBPUV : 2; |
| UNSG32 u_CBFUV : 8; |
| UNSG32 u_CBFUDC : 1; |
| UNSG32 u_CBFVDC : 1; |
| UNSG32 RSVDx58_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmdUV ie_CoeffCmdUV; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx74 [4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_CUVINFO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CUVINFO_drvrd(SIE_CUVINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CUVINFO_drvwr(SIE_CUVINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CUVINFO_reset(SIE_CUVINFO *p); |
| SIGN32 CUVINFO_cmp (SIE_CUVINFO *p, SIE_CUVINFO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CUVINFO_check(p,pie,pfx,hLOG) CUVINFO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CUVINFO_print(p, pfx,hLOG) CUVINFO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CUVINFO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CNxNINFOUnit flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 23 score |
| /// %% 9 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 16 SADY |
| /// ### |
| /// * SAD for Luma |
| /// ### |
| /// %unsigned 2 Best_Mode_Cat |
| /// %unsigned 6 Best_tag |
| /// %unsigned 1 Best_Trans_Type |
| /// %unsigned 4 Best_Intra_Mode |
| /// %unsigned 1 valid |
| /// ### |
| /// * Block is valid or not. Used in QiQTC buffer. If invalid, RD will not update RD buffer by this block. |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// @ 0x00008 (P) |
| /// # 0x00008 bin_ssd |
| /// $BinSSD5 bin_ssd REG |
| /// ### |
| /// * {bin,SSD}[5] |
| /// ### |
| /// @ 0x00030 (P) |
| /// %unsigned 1 CBPDC |
| /// ### |
| /// * CBPDC for 8x8 block,only valid for 8x8 mode. |
| /// ### |
| /// %unsigned 1 CBPDC4x4 |
| /// ### |
| /// * CBPDC for 4x4 block, only valid for 4x4 mode. 1 means there is none-zero DC coefficient but no none-zero AC coeffcient. Otherwise, it's 0. |
| /// ### |
| /// %unsigned 1 CBP |
| /// ### |
| /// * Only valid for 8x8 mode. |
| /// ### |
| /// %unsigned 1 CBF |
| /// ### |
| /// * Only valid for 4x4 mode. |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x00034 (P) |
| /// # 0x00034 CoeffCmd |
| /// $CoeffCmd CoeffCmd REG |
| /// ### |
| /// * Total coefficient, trailing ones. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 56B, bits: 448b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CNxNINFOUnit |
| #define h_CNxNINFOUnit (){} |
| |
| #define BA_CNxNINFOUnit_score 0x0000 |
| #define B16CNxNINFOUnit_score 0x0000 |
| #define LSb32CNxNINFOUnit_score 0 |
| #define LSb16CNxNINFOUnit_score 0 |
| #define bCNxNINFOUnit_score 23 |
| #define MSK32CNxNINFOUnit_score 0x007FFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CNxNINFOUnit_SADY 0x0004 |
| #define B16CNxNINFOUnit_SADY 0x0004 |
| #define LSb32CNxNINFOUnit_SADY 0 |
| #define LSb16CNxNINFOUnit_SADY 0 |
| #define bCNxNINFOUnit_SADY 16 |
| #define MSK32CNxNINFOUnit_SADY 0x0000FFFF |
| |
| #define BA_CNxNINFOUnit_Best_Mode_Cat 0x0006 |
| #define B16CNxNINFOUnit_Best_Mode_Cat 0x0006 |
| #define LSb32CNxNINFOUnit_Best_Mode_Cat 16 |
| #define LSb16CNxNINFOUnit_Best_Mode_Cat 0 |
| #define bCNxNINFOUnit_Best_Mode_Cat 2 |
| #define MSK32CNxNINFOUnit_Best_Mode_Cat 0x00030000 |
| |
| #define BA_CNxNINFOUnit_Best_tag 0x0006 |
| #define B16CNxNINFOUnit_Best_tag 0x0006 |
| #define LSb32CNxNINFOUnit_Best_tag 18 |
| #define LSb16CNxNINFOUnit_Best_tag 2 |
| #define bCNxNINFOUnit_Best_tag 6 |
| #define MSK32CNxNINFOUnit_Best_tag 0x00FC0000 |
| |
| #define BA_CNxNINFOUnit_Best_Trans_Type 0x0007 |
| #define B16CNxNINFOUnit_Best_Trans_Type 0x0006 |
| #define LSb32CNxNINFOUnit_Best_Trans_Type 24 |
| #define LSb16CNxNINFOUnit_Best_Trans_Type 8 |
| #define bCNxNINFOUnit_Best_Trans_Type 1 |
| #define MSK32CNxNINFOUnit_Best_Trans_Type 0x01000000 |
| |
| #define BA_CNxNINFOUnit_Best_Intra_Mode 0x0007 |
| #define B16CNxNINFOUnit_Best_Intra_Mode 0x0006 |
| #define LSb32CNxNINFOUnit_Best_Intra_Mode 25 |
| #define LSb16CNxNINFOUnit_Best_Intra_Mode 9 |
| #define bCNxNINFOUnit_Best_Intra_Mode 4 |
| #define MSK32CNxNINFOUnit_Best_Intra_Mode 0x1E000000 |
| |
| #define BA_CNxNINFOUnit_valid 0x0007 |
| #define B16CNxNINFOUnit_valid 0x0006 |
| #define LSb32CNxNINFOUnit_valid 29 |
| #define LSb16CNxNINFOUnit_valid 13 |
| #define bCNxNINFOUnit_valid 1 |
| #define MSK32CNxNINFOUnit_valid 0x20000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CNxNINFOUnit_bin_ssd 0x0008 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_CNxNINFOUnit_CBPDC 0x0030 |
| #define B16CNxNINFOUnit_CBPDC 0x0030 |
| #define LSb32CNxNINFOUnit_CBPDC 0 |
| #define LSb16CNxNINFOUnit_CBPDC 0 |
| #define bCNxNINFOUnit_CBPDC 1 |
| #define MSK32CNxNINFOUnit_CBPDC 0x00000001 |
| |
| #define BA_CNxNINFOUnit_CBPDC4x4 0x0030 |
| #define B16CNxNINFOUnit_CBPDC4x4 0x0030 |
| #define LSb32CNxNINFOUnit_CBPDC4x4 1 |
| #define LSb16CNxNINFOUnit_CBPDC4x4 1 |
| #define bCNxNINFOUnit_CBPDC4x4 1 |
| #define MSK32CNxNINFOUnit_CBPDC4x4 0x00000002 |
| |
| #define BA_CNxNINFOUnit_CBP 0x0030 |
| #define B16CNxNINFOUnit_CBP 0x0030 |
| #define LSb32CNxNINFOUnit_CBP 2 |
| #define LSb16CNxNINFOUnit_CBP 2 |
| #define bCNxNINFOUnit_CBP 1 |
| #define MSK32CNxNINFOUnit_CBP 0x00000004 |
| |
| #define BA_CNxNINFOUnit_CBF 0x0030 |
| #define B16CNxNINFOUnit_CBF 0x0030 |
| #define LSb32CNxNINFOUnit_CBF 3 |
| #define LSb16CNxNINFOUnit_CBF 3 |
| #define bCNxNINFOUnit_CBF 1 |
| #define MSK32CNxNINFOUnit_CBF 0x00000008 |
| /////////////////////////////////////////////////////////// |
| #define RA_CNxNINFOUnit_CoeffCmd 0x0034 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CNxNINFOUnit { |
| /////////////////////////////////////////////////////////// |
| #define GET32CNxNINFOUnit_score(r32) _BFGET_(r32,22, 0) |
| #define SET32CNxNINFOUnit_score(r32,v) _BFSET_(r32,22, 0,v) |
| |
| UNSG32 u_score : 23; |
| UNSG32 RSVDx0_b23 : 9; |
| /////////////////////////////////////////////////////////// |
| #define GET32CNxNINFOUnit_SADY(r32) _BFGET_(r32,15, 0) |
| #define SET32CNxNINFOUnit_SADY(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16CNxNINFOUnit_SADY(r16) _BFGET_(r16,15, 0) |
| #define SET16CNxNINFOUnit_SADY(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32CNxNINFOUnit_Best_Mode_Cat(r32) _BFGET_(r32,17,16) |
| #define SET32CNxNINFOUnit_Best_Mode_Cat(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16CNxNINFOUnit_Best_Mode_Cat(r16) _BFGET_(r16, 1, 0) |
| #define SET16CNxNINFOUnit_Best_Mode_Cat(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32CNxNINFOUnit_Best_tag(r32) _BFGET_(r32,23,18) |
| #define SET32CNxNINFOUnit_Best_tag(r32,v) _BFSET_(r32,23,18,v) |
| #define GET16CNxNINFOUnit_Best_tag(r16) _BFGET_(r16, 7, 2) |
| #define SET16CNxNINFOUnit_Best_tag(r16,v) _BFSET_(r16, 7, 2,v) |
| |
| #define GET32CNxNINFOUnit_Best_Trans_Type(r32) _BFGET_(r32,24,24) |
| #define SET32CNxNINFOUnit_Best_Trans_Type(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16CNxNINFOUnit_Best_Trans_Type(r16) _BFGET_(r16, 8, 8) |
| #define SET16CNxNINFOUnit_Best_Trans_Type(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32CNxNINFOUnit_Best_Intra_Mode(r32) _BFGET_(r32,28,25) |
| #define SET32CNxNINFOUnit_Best_Intra_Mode(r32,v) _BFSET_(r32,28,25,v) |
| #define GET16CNxNINFOUnit_Best_Intra_Mode(r16) _BFGET_(r16,12, 9) |
| #define SET16CNxNINFOUnit_Best_Intra_Mode(r16,v) _BFSET_(r16,12, 9,v) |
| |
| #define GET32CNxNINFOUnit_valid(r32) _BFGET_(r32,29,29) |
| #define SET32CNxNINFOUnit_valid(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16CNxNINFOUnit_valid(r16) _BFGET_(r16,13,13) |
| #define SET16CNxNINFOUnit_valid(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_SADY : 16; |
| UNSG32 u_Best_Mode_Cat : 2; |
| UNSG32 u_Best_tag : 6; |
| UNSG32 u_Best_Trans_Type : 1; |
| UNSG32 u_Best_Intra_Mode : 4; |
| UNSG32 u_valid : 1; |
| UNSG32 RSVDx4_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| SIE_BinSSD5 ie_bin_ssd; |
| /////////////////////////////////////////////////////////// |
| #define GET32CNxNINFOUnit_CBPDC(r32) _BFGET_(r32, 0, 0) |
| #define SET32CNxNINFOUnit_CBPDC(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16CNxNINFOUnit_CBPDC(r16) _BFGET_(r16, 0, 0) |
| #define SET16CNxNINFOUnit_CBPDC(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32CNxNINFOUnit_CBPDC4x4(r32) _BFGET_(r32, 1, 1) |
| #define SET32CNxNINFOUnit_CBPDC4x4(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16CNxNINFOUnit_CBPDC4x4(r16) _BFGET_(r16, 1, 1) |
| #define SET16CNxNINFOUnit_CBPDC4x4(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32CNxNINFOUnit_CBP(r32) _BFGET_(r32, 2, 2) |
| #define SET32CNxNINFOUnit_CBP(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16CNxNINFOUnit_CBP(r16) _BFGET_(r16, 2, 2) |
| #define SET16CNxNINFOUnit_CBP(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32CNxNINFOUnit_CBF(r32) _BFGET_(r32, 3, 3) |
| #define SET32CNxNINFOUnit_CBF(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16CNxNINFOUnit_CBF(r16) _BFGET_(r16, 3, 3) |
| #define SET16CNxNINFOUnit_CBF(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| UNSG32 u_CBPDC : 1; |
| UNSG32 u_CBPDC4x4 : 1; |
| UNSG32 u_CBP : 1; |
| UNSG32 u_CBF : 1; |
| UNSG32 RSVDx30_b4 : 28; |
| /////////////////////////////////////////////////////////// |
| SIE_CoeffCmd ie_CoeffCmd; |
| /////////////////////////////////////////////////////////// |
| } SIE_CNxNINFOUnit; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CNxNINFOUnit_drvrd(SIE_CNxNINFOUnit *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CNxNINFOUnit_drvwr(SIE_CNxNINFOUnit *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CNxNINFOUnit_reset(SIE_CNxNINFOUnit *p); |
| SIGN32 CNxNINFOUnit_cmp (SIE_CNxNINFOUnit *p, SIE_CNxNINFOUnit *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CNxNINFOUnit_check(p,pie,pfx,hLOG) CNxNINFOUnit_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CNxNINFOUnit_print(p, pfx,hLOG) CNxNINFOUnit_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CNxNINFOUnit |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CNxNINFO flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 CNxNINFOUnit |
| /// $CNxNINFOUnit CNxNINFOUnit REG [16] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 896B, bits: 7168b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CNxNINFO |
| #define h_CNxNINFO (){} |
| |
| #define RA_CNxNINFO_CNxNINFOUnit 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CNxNINFO { |
| /////////////////////////////////////////////////////////// |
| SIE_CNxNINFOUnit ie_CNxNINFOUnit[16]; |
| /////////////////////////////////////////////////////////// |
| } SIE_CNxNINFO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CNxNINFO_drvrd(SIE_CNxNINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CNxNINFO_drvwr(SIE_CNxNINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CNxNINFO_reset(SIE_CNxNINFO *p); |
| SIGN32 CNxNINFO_cmp (SIE_CNxNINFO *p, SIE_CNxNINFO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CNxNINFO_check(p,pie,pfx,hLOG) CNxNINFO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CNxNINFO_print(p, pfx,hLOG) CNxNINFO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CNxNINFO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE QiQTCINFO flat (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 QiQTCYInfo |
| /// $CNxNINFOUnit QiQTCYInfo REG [27] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 1512B, bits: 12096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_QiQTCINFO |
| #define h_QiQTCINFO (){} |
| |
| #define RA_QiQTCINFO_QiQTCYInfo 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_QiQTCINFO { |
| /////////////////////////////////////////////////////////// |
| SIE_CNxNINFOUnit ie_QiQTCYInfo[27]; |
| /////////////////////////////////////////////////////////// |
| } SIE_QiQTCINFO; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 QiQTCINFO_drvrd(SIE_QiQTCINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 QiQTCINFO_drvwr(SIE_QiQTCINFO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void QiQTCINFO_reset(SIE_QiQTCINFO *p); |
| SIGN32 QiQTCINFO_cmp (SIE_QiQTCINFO *p, SIE_QiQTCINFO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define QiQTCINFO_check(p,pie,pfx,hLOG) QiQTCINFO_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define QiQTCINFO_print(p, pfx,hLOG) QiQTCINFO_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: QiQTCINFO |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ADDRWA flat (4,4) |
| /// ### |
| /// * Address bases for buffers accessed by WA |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 addrwa |
| /// : Orig_base 0x0 |
| /// : Orig_size 0x180 |
| /// ### |
| /// * Original pixel buffer base address and size |
| /// ### |
| /// : Orig_Y_base 0x0 |
| /// : Orig_Y_size 0x100 |
| /// ### |
| /// * Original pixel buffer base address and size for Y |
| /// ### |
| /// : Orig_UV_base 0x100 |
| /// : Orig_UV_size 0x80 |
| /// ### |
| /// * Original pixel buffer base address and size for UV |
| /// ### |
| /// : Pred_base 0x200 |
| /// : Pred_size 0x180 |
| /// ### |
| /// * Predictor pixel buffer base address and size |
| /// ### |
| /// : Pred_Y_base 0x200 |
| /// : Pred_Y_size 0x100 |
| /// ### |
| /// * Predictor pixel buffer base address and size for Y |
| /// ### |
| /// : Pred_UV_base 0x300 |
| /// : Pred_UV_size 0x80 |
| /// ### |
| /// * Predictor pixel buffer base address and size for UV |
| /// ### |
| /// : TCP_Pred_base 0x400 |
| /// : TCP_Pred_size 0x400 |
| /// ### |
| /// * TCP buffer base address and size for predictor part. |
| /// ### |
| /// : TCP_Coef_base 0x800 |
| /// : TCP_Coef_size 0x800 |
| /// ### |
| /// * TCP buffer base address and size for coefficient part. |
| /// ### |
| /// : IPC_in_base 0x2000 |
| /// ### |
| /// * Intra prediction context buffer for WA to write |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ADDRWA |
| #define h_ADDRWA (){} |
| |
| #define BA_ADDRWA_addrwa 0x0000 |
| #define B16ADDRWA_addrwa 0x0000 |
| #define LSb32ADDRWA_addrwa 0 |
| #define LSb16ADDRWA_addrwa 0 |
| #define bADDRWA_addrwa 16 |
| #define MSK32ADDRWA_addrwa 0x0000FFFF |
| #define ADDRWA_addrwa_Orig_base 0x0 |
| #define ADDRWA_addrwa_Orig_size 0x180 |
| #define ADDRWA_addrwa_Orig_Y_base 0x0 |
| #define ADDRWA_addrwa_Orig_Y_size 0x100 |
| #define ADDRWA_addrwa_Orig_UV_base 0x100 |
| #define ADDRWA_addrwa_Orig_UV_size 0x80 |
| #define ADDRWA_addrwa_Pred_base 0x200 |
| #define ADDRWA_addrwa_Pred_size 0x180 |
| #define ADDRWA_addrwa_Pred_Y_base 0x200 |
| #define ADDRWA_addrwa_Pred_Y_size 0x100 |
| #define ADDRWA_addrwa_Pred_UV_base 0x300 |
| #define ADDRWA_addrwa_Pred_UV_size 0x80 |
| #define ADDRWA_addrwa_TCP_Pred_base 0x400 |
| #define ADDRWA_addrwa_TCP_Pred_size 0x400 |
| #define ADDRWA_addrwa_TCP_Coef_base 0x800 |
| #define ADDRWA_addrwa_TCP_Coef_size 0x800 |
| #define ADDRWA_addrwa_IPC_in_base 0x2000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ADDRWA { |
| /////////////////////////////////////////////////////////// |
| #define GET32ADDRWA_addrwa(r32) _BFGET_(r32,15, 0) |
| #define SET32ADDRWA_addrwa(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16ADDRWA_addrwa(r16) _BFGET_(r16,15, 0) |
| #define SET16ADDRWA_addrwa(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_addrwa : 16; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_ADDRWA; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ADDRWA_drvrd(SIE_ADDRWA *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ADDRWA_drvwr(SIE_ADDRWA *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ADDRWA_reset(SIE_ADDRWA *p); |
| SIGN32 ADDRWA_cmp (SIE_ADDRWA *p, SIE_ADDRWA *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ADDRWA_check(p,pie,pfx,hLOG) ADDRWA_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ADDRWA_print(p, pfx,hLOG) ADDRWA_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ADDRWA |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ADDRRA flat (4,4) |
| /// ### |
| /// * Address bases for buffers accessed by RA |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 addrra |
| /// : Recon_base 0x0 |
| /// : Recon_size 0x100 |
| /// ### |
| /// * Reconstructed pixel buffer base address and size |
| /// ### |
| /// : Recon_Y_base 0x0 |
| /// : Recon_Y_size 0x100 |
| /// ### |
| /// * Reconstructed pixel buffer base address and size for Y |
| /// ### |
| /// : Recon_UV_base 0x100 |
| /// : Recon_UV_size 0x80 |
| /// ### |
| /// * Reconstructed pixel buffer base address and size for UV |
| /// ### |
| /// : IPC_out_base 0x2000 |
| /// ### |
| /// * Intra prediction context buffer for RA to read |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ADDRRA |
| #define h_ADDRRA (){} |
| |
| #define BA_ADDRRA_addrra 0x0000 |
| #define B16ADDRRA_addrra 0x0000 |
| #define LSb32ADDRRA_addrra 0 |
| #define LSb16ADDRRA_addrra 0 |
| #define bADDRRA_addrra 16 |
| #define MSK32ADDRRA_addrra 0x0000FFFF |
| #define ADDRRA_addrra_Recon_base 0x0 |
| #define ADDRRA_addrra_Recon_size 0x100 |
| #define ADDRRA_addrra_Recon_Y_base 0x0 |
| #define ADDRRA_addrra_Recon_Y_size 0x100 |
| #define ADDRRA_addrra_Recon_UV_base 0x100 |
| #define ADDRRA_addrra_Recon_UV_size 0x80 |
| #define ADDRRA_addrra_IPC_out_base 0x2000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ADDRRA { |
| /////////////////////////////////////////////////////////// |
| #define GET32ADDRRA_addrra(r32) _BFGET_(r32,15, 0) |
| #define SET32ADDRRA_addrra(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16ADDRRA_addrra(r16) _BFGET_(r16,15, 0) |
| #define SET16ADDRRA_addrra(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_addrra : 16; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_ADDRRA; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ADDRRA_drvrd(SIE_ADDRRA *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ADDRRA_drvwr(SIE_ADDRRA *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ADDRRA_reset(SIE_ADDRRA *p); |
| SIGN32 ADDRRA_cmp (SIE_ADDRRA *p, SIE_ADDRRA *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ADDRRA_check(p,pie,pfx,hLOG) ADDRRA_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ADDRRA_print(p, pfx,hLOG) ADDRRA_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ADDRRA |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPLUSCmdR16M flat (4,2) |
| /// ### |
| /// * IPLUS Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 Address |
| /// ### |
| /// * Quantization/DeQuantization matrix SRAM address for QdeQMatrix command |
| /// ### |
| /// %% 24 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPLUSCmdR16M |
| #define h_IPLUSCmdR16M (){} |
| |
| #define BA_IPLUSCmdR16M_Address 0x0000 |
| #define B16IPLUSCmdR16M_Address 0x0000 |
| #define LSb32IPLUSCmdR16M_Address 0 |
| #define LSb16IPLUSCmdR16M_Address 0 |
| #define bIPLUSCmdR16M_Address 8 |
| #define MSK32IPLUSCmdR16M_Address 0x000000FF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPLUSCmdR16M { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPLUSCmdR16M_Address(r32) _BFGET_(r32, 7, 0) |
| #define SET32IPLUSCmdR16M_Address(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16IPLUSCmdR16M_Address(r16) _BFGET_(r16, 7, 0) |
| #define SET16IPLUSCmdR16M_Address(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| UNSG32 u_Address : 8; |
| UNSG32 RSVDx0_b8 : 24; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPLUSCmdR16M; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPLUSCmdR16M_drvrd(SIE_IPLUSCmdR16M *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPLUSCmdR16M_drvwr(SIE_IPLUSCmdR16M *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPLUSCmdR16M_reset(SIE_IPLUSCmdR16M *p); |
| SIGN32 IPLUSCmdR16M_cmp (SIE_IPLUSCmdR16M *p, SIE_IPLUSCmdR16M *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPLUSCmdR16M_check(p,pie,pfx,hLOG) IPLUSCmdR16M_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPLUSCmdR16M_print(p, pfx,hLOG) IPLUSCmdR16M_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPLUSCmdR16M |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPLUSCmdR16D flat (4,2) |
| /// ### |
| /// * IPLUS Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Type |
| /// : EncMB 0x0 |
| /// ### |
| /// * Tell IPLUS to start process a MB |
| /// ### |
| /// : EncInterParam 0x1 |
| /// ### |
| /// * Send inter parameter to IPLUS. |
| /// ### |
| /// : BinSSDPIC 0x2 |
| /// ### |
| /// * Retrieve accumulated Bin/SSD data and reset them. |
| /// ### |
| /// %unsigned 6 MV_cost |
| /// ### |
| /// * Moition vector bin count of inter mode. |
| /// ### |
| /// %unsigned 1 transform_size_flag |
| /// ### |
| /// * This flag is used for EncInterParam |
| /// * For VP82, this bit is used to indicate if second transform is used or not for inter condidate. For intra prediction mode, only intra16x16 predicted MB uses second transform, so IPLUS has to decide it internally. For DIRECT mode, second transform is always used, so it is decided in IPLUS internally also. For inter mode, second transform is only used for16x16 prediction, so software has to use this bit to indicate if second transform is used or not. |
| /// ### |
| /// : transform_4x4 0x0 |
| /// : transform_8x8 0x1 |
| /// %unsigned 2 inter_predictor_idx |
| /// ### |
| /// * This index specify which one of four inter candidate is winner. For EncInterParam only. |
| /// ### |
| /// %% 19 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPLUSCmdR16D |
| #define h_IPLUSCmdR16D (){} |
| |
| #define BA_IPLUSCmdR16D_Type 0x0000 |
| #define B16IPLUSCmdR16D_Type 0x0000 |
| #define LSb32IPLUSCmdR16D_Type 0 |
| #define LSb16IPLUSCmdR16D_Type 0 |
| #define bIPLUSCmdR16D_Type 4 |
| #define MSK32IPLUSCmdR16D_Type 0x0000000F |
| #define IPLUSCmdR16D_Type_EncMB 0x0 |
| #define IPLUSCmdR16D_Type_EncInterParam 0x1 |
| #define IPLUSCmdR16D_Type_BinSSDPIC 0x2 |
| |
| #define BA_IPLUSCmdR16D_MV_cost 0x0000 |
| #define B16IPLUSCmdR16D_MV_cost 0x0000 |
| #define LSb32IPLUSCmdR16D_MV_cost 4 |
| #define LSb16IPLUSCmdR16D_MV_cost 4 |
| #define bIPLUSCmdR16D_MV_cost 6 |
| #define MSK32IPLUSCmdR16D_MV_cost 0x000003F0 |
| |
| #define BA_IPLUSCmdR16D_transform_size_flag 0x0001 |
| #define B16IPLUSCmdR16D_transform_size_flag 0x0000 |
| #define LSb32IPLUSCmdR16D_transform_size_flag 10 |
| #define LSb16IPLUSCmdR16D_transform_size_flag 10 |
| #define bIPLUSCmdR16D_transform_size_flag 1 |
| #define MSK32IPLUSCmdR16D_transform_size_flag 0x00000400 |
| #define IPLUSCmdR16D_transform_size_flag_transform_4x4 0x0 |
| #define IPLUSCmdR16D_transform_size_flag_transform_8x8 0x1 |
| |
| #define BA_IPLUSCmdR16D_inter_predictor_idx 0x0001 |
| #define B16IPLUSCmdR16D_inter_predictor_idx 0x0000 |
| #define LSb32IPLUSCmdR16D_inter_predictor_idx 11 |
| #define LSb16IPLUSCmdR16D_inter_predictor_idx 11 |
| #define bIPLUSCmdR16D_inter_predictor_idx 2 |
| #define MSK32IPLUSCmdR16D_inter_predictor_idx 0x00001800 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPLUSCmdR16D { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPLUSCmdR16D_Type(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPLUSCmdR16D_Type(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPLUSCmdR16D_Type(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPLUSCmdR16D_Type(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPLUSCmdR16D_MV_cost(r32) _BFGET_(r32, 9, 4) |
| #define SET32IPLUSCmdR16D_MV_cost(r32,v) _BFSET_(r32, 9, 4,v) |
| #define GET16IPLUSCmdR16D_MV_cost(r16) _BFGET_(r16, 9, 4) |
| #define SET16IPLUSCmdR16D_MV_cost(r16,v) _BFSET_(r16, 9, 4,v) |
| |
| #define GET32IPLUSCmdR16D_transform_size_flag(r32) _BFGET_(r32,10,10) |
| #define SET32IPLUSCmdR16D_transform_size_flag(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16IPLUSCmdR16D_transform_size_flag(r16) _BFGET_(r16,10,10) |
| #define SET16IPLUSCmdR16D_transform_size_flag(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32IPLUSCmdR16D_inter_predictor_idx(r32) _BFGET_(r32,12,11) |
| #define SET32IPLUSCmdR16D_inter_predictor_idx(r32,v) _BFSET_(r32,12,11,v) |
| #define GET16IPLUSCmdR16D_inter_predictor_idx(r16) _BFGET_(r16,12,11) |
| #define SET16IPLUSCmdR16D_inter_predictor_idx(r16,v) _BFSET_(r16,12,11,v) |
| |
| UNSG32 u_Type : 4; |
| UNSG32 u_MV_cost : 6; |
| UNSG32 u_transform_size_flag : 1; |
| UNSG32 u_inter_predictor_idx : 2; |
| UNSG32 RSVDx0_b13 : 19; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPLUSCmdR16D; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPLUSCmdR16D_drvrd(SIE_IPLUSCmdR16D *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPLUSCmdR16D_drvwr(SIE_IPLUSCmdR16D *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPLUSCmdR16D_reset(SIE_IPLUSCmdR16D *p); |
| SIGN32 IPLUSCmdR16D_cmp (SIE_IPLUSCmdR16D *p, SIE_IPLUSCmdR16D *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPLUSCmdR16D_check(p,pie,pfx,hLOG) IPLUSCmdR16D_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPLUSCmdR16D_print(p, pfx,hLOG) IPLUSCmdR16D_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPLUSCmdR16D |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPLUSCmdR16Dec0 flat (4,2) |
| /// ### |
| /// * IPLUS Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Type |
| /// : DecMB 0x3 |
| /// ### |
| /// * Tell IPLUS to start decoding a MB. It is used for all video formats to load quantized coefficients, intra context or inter predictor. For H264, AVS, RV8/9 and VP82, intra MB will needs DecMB followed by DecIntraLuma and DecIntraChroma to finish a MB decoding; inter MB and H264 IPCM MB only needs DecMB command to finish a MB decoding. For VP6, only DecMB command is needed to finish a MB decoding. For other formats, DecMB is followed by Dec8x8 command to finish a MB decoding. Please refer to section 6.1.2.2. |
| /// ### |
| /// : DecIntraLuma 0x4 |
| /// ### |
| /// * Decode one intra prediction partition (4x4, 8x8 or 16x16) of Luma part of an intra coded MB. Software has to apply this command in the order described in Section 4.1. |
| /// ### |
| /// : DecIntraChroma 0x5 |
| /// ### |
| /// * Decode one intra prediction partition (4x4 or 8x8) Chroma part (U and V together) of an intra coded MB. Only RV8/9 uses 4x4 intra prediction for Chroma when its MB type is intraNxN. Software has to apply this command in the order described in Section 4.1. |
| /// ### |
| /// %unsigned 1 transform_size_flag |
| /// ### |
| /// * Transform type as defined in IPLUSCmdR16D. |
| /// * For RV8/9, this bit is used to indicate if second transform is used or not. |
| /// * For VP82, this bit is used to indicate if second transform is used or not. |
| /// ### |
| /// : RV_SECOND_TRANS_OFF 0x0 |
| /// : RV_SECOND_TRANS_ON 0x1 |
| /// %unsigned 4 ip_type |
| /// ### |
| /// * Intra prediction mode. H264 intra prediction mode is defined in IntraModeY. AVS, RV8/9 and VP82 intra prediction is defined as following: |
| /// ### |
| /// : AVS_Intra_8x8_Vertical 0x0 |
| /// : AVS_Intra_8x8_Horizontal 0x1 |
| /// : AVS_Intra_8x8_DC 0x2 |
| /// : AVS_Intra_8x8_Down_Left 0x3 |
| /// : AVS_Intra_8x8_Down_Right 0x4 |
| /// : AVS_Intra_Chroma_DC 0x0 |
| /// : AVS_Intra_Chroma_Horizontal 0x1 |
| /// : AVS_Intra_Chroma_Vertical 0x2 |
| /// : AVS_Intra_Chroma_Plane 0x3 |
| /// : RV_Intra_4x4_DC 0x0 |
| /// : RV_Intra_4x4_Vertical 0x1 |
| /// : RV_Intra_4x4_Horizontal 0x2 |
| /// : RV_Intra_4x4_Diagonal_Down_Right 0x3 |
| /// : RV_Intra_4x4_Diagonal_Down_Left 0x4 |
| /// : RV_Intra_4x4_Vertical_Right 0x5 |
| /// : RV_Intra_4x4_Vertical_Left 0x6 |
| /// : RV_Intra_4x4_Horizontal_Up 0x7 |
| /// : RV_Intra_4x4_Horizontal_Down 0x8 |
| /// : RV_Intra_16x16_DC 0x0 |
| /// : RV_Intra_16x16_Vertical 0x1 |
| /// : RV_Intra_16x16_Horizontal 0x2 |
| /// : RV_Intra_16x16_Planar 0x3 |
| /// : VP82_Intra_Chroma_DC_PRED 0x0 |
| /// : VP82_Intra_Chroma_V_PRED 0x1 |
| /// : VP82_Intra_Chroma_H_PRED 0x2 |
| /// : VP82_Intra_Chroma_TM_PRED 0x3 |
| /// : VP82_Intra_16x16_DC_PRED 0x0 |
| /// : VP82_Intra_16x16_V_PRED 0x1 |
| /// : VP82_Intra_16x16_H_PRED 0x2 |
| /// : VP82_Intra_16x16_TM_PRED 0x3 |
| /// : VP82_Intra_4x4_DC_PRED 0x0 |
| /// : VP82_Intra_4x4_TM_PRED 0x1 |
| /// : VP82_Intra_4x4_VE_PRED 0x2 |
| /// : VP82_Intra_4x4_HE_PRED 0x3 |
| /// : VP82_Intra_4x4_LD_PRED 0x4 |
| /// : VP82_Intra_4x4_RD_PRED 0x5 |
| /// : VP82_Intra_4x4_VR_PRED 0x6 |
| /// : VP82_Intra_4x4_VL_PRED 0x7 |
| /// : VP82_Intra_4x4_HD_PRED 0x8 |
| /// : VP82_Intra_4x4_HU_PRED 0x9 |
| /// %unsigned 3 MB_Type |
| /// ### |
| /// * MB type as defined in RDMBResult. |
| /// * Note, For VC1AP/WMV 4MV MB, if all 4 8x8 blocks in this MB are intra coded, set MB type as intra16x16; Otherwise, set MB type as inter (at least one inter block in MB). |
| /// ### |
| /// %% 20 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPLUSCmdR16Dec0 |
| #define h_IPLUSCmdR16Dec0 (){} |
| |
| #define BA_IPLUSCmdR16Dec0_Type 0x0000 |
| #define B16IPLUSCmdR16Dec0_Type 0x0000 |
| #define LSb32IPLUSCmdR16Dec0_Type 0 |
| #define LSb16IPLUSCmdR16Dec0_Type 0 |
| #define bIPLUSCmdR16Dec0_Type 4 |
| #define MSK32IPLUSCmdR16Dec0_Type 0x0000000F |
| #define IPLUSCmdR16Dec0_Type_DecMB 0x3 |
| #define IPLUSCmdR16Dec0_Type_DecIntraLuma 0x4 |
| #define IPLUSCmdR16Dec0_Type_DecIntraChroma 0x5 |
| |
| #define BA_IPLUSCmdR16Dec0_transform_size_flag 0x0000 |
| #define B16IPLUSCmdR16Dec0_transform_size_flag 0x0000 |
| #define LSb32IPLUSCmdR16Dec0_transform_size_flag 4 |
| #define LSb16IPLUSCmdR16Dec0_transform_size_flag 4 |
| #define bIPLUSCmdR16Dec0_transform_size_flag 1 |
| #define MSK32IPLUSCmdR16Dec0_transform_size_flag 0x00000010 |
| #define IPLUSCmdR16Dec0_transform_size_flag_RV_SECOND_TRANS_OFF 0x0 |
| #define IPLUSCmdR16Dec0_transform_size_flag_RV_SECOND_TRANS_ON 0x1 |
| |
| #define BA_IPLUSCmdR16Dec0_ip_type 0x0000 |
| #define B16IPLUSCmdR16Dec0_ip_type 0x0000 |
| #define LSb32IPLUSCmdR16Dec0_ip_type 5 |
| #define LSb16IPLUSCmdR16Dec0_ip_type 5 |
| #define bIPLUSCmdR16Dec0_ip_type 4 |
| #define MSK32IPLUSCmdR16Dec0_ip_type 0x000001E0 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_8x8_Vertical 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_8x8_Horizontal 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_8x8_DC 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_8x8_Down_Left 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_8x8_Down_Right 0x4 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_Chroma_DC 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_Chroma_Horizontal 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_Chroma_Vertical 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_AVS_Intra_Chroma_Plane 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_DC 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Vertical 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Horizontal 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Diagonal_Down_Right 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Diagonal_Down_Left 0x4 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Vertical_Right 0x5 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Vertical_Left 0x6 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Horizontal_Up 0x7 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_4x4_Horizontal_Down 0x8 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_16x16_DC 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_16x16_Vertical 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_16x16_Horizontal 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_RV_Intra_16x16_Planar 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_Chroma_DC_PRED 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_Chroma_V_PRED 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_Chroma_H_PRED 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_Chroma_TM_PRED 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_16x16_DC_PRED 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_16x16_V_PRED 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_16x16_H_PRED 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_16x16_TM_PRED 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_DC_PRED 0x0 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_TM_PRED 0x1 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_VE_PRED 0x2 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_HE_PRED 0x3 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_LD_PRED 0x4 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_RD_PRED 0x5 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_VR_PRED 0x6 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_VL_PRED 0x7 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_HD_PRED 0x8 |
| #define IPLUSCmdR16Dec0_ip_type_VP82_Intra_4x4_HU_PRED 0x9 |
| |
| #define BA_IPLUSCmdR16Dec0_MB_Type 0x0001 |
| #define B16IPLUSCmdR16Dec0_MB_Type 0x0000 |
| #define LSb32IPLUSCmdR16Dec0_MB_Type 9 |
| #define LSb16IPLUSCmdR16Dec0_MB_Type 9 |
| #define bIPLUSCmdR16Dec0_MB_Type 3 |
| #define MSK32IPLUSCmdR16Dec0_MB_Type 0x00000E00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPLUSCmdR16Dec0 { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPLUSCmdR16Dec0_Type(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPLUSCmdR16Dec0_Type(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPLUSCmdR16Dec0_Type(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPLUSCmdR16Dec0_Type(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPLUSCmdR16Dec0_transform_size_flag(r32) _BFGET_(r32, 4, 4) |
| #define SET32IPLUSCmdR16Dec0_transform_size_flag(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16IPLUSCmdR16Dec0_transform_size_flag(r16) _BFGET_(r16, 4, 4) |
| #define SET16IPLUSCmdR16Dec0_transform_size_flag(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32IPLUSCmdR16Dec0_ip_type(r32) _BFGET_(r32, 8, 5) |
| #define SET32IPLUSCmdR16Dec0_ip_type(r32,v) _BFSET_(r32, 8, 5,v) |
| #define GET16IPLUSCmdR16Dec0_ip_type(r16) _BFGET_(r16, 8, 5) |
| #define SET16IPLUSCmdR16Dec0_ip_type(r16,v) _BFSET_(r16, 8, 5,v) |
| |
| #define GET32IPLUSCmdR16Dec0_MB_Type(r32) _BFGET_(r32,11, 9) |
| #define SET32IPLUSCmdR16Dec0_MB_Type(r32,v) _BFSET_(r32,11, 9,v) |
| #define GET16IPLUSCmdR16Dec0_MB_Type(r16) _BFGET_(r16,11, 9) |
| #define SET16IPLUSCmdR16Dec0_MB_Type(r16,v) _BFSET_(r16,11, 9,v) |
| |
| UNSG32 u_Type : 4; |
| UNSG32 u_transform_size_flag : 1; |
| UNSG32 u_ip_type : 4; |
| UNSG32 u_MB_Type : 3; |
| UNSG32 RSVDx0_b12 : 20; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPLUSCmdR16Dec0; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPLUSCmdR16Dec0_drvrd(SIE_IPLUSCmdR16Dec0 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPLUSCmdR16Dec0_drvwr(SIE_IPLUSCmdR16Dec0 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPLUSCmdR16Dec0_reset(SIE_IPLUSCmdR16Dec0 *p); |
| SIGN32 IPLUSCmdR16Dec0_cmp (SIE_IPLUSCmdR16Dec0 *p, SIE_IPLUSCmdR16Dec0 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPLUSCmdR16Dec0_check(p,pie,pfx,hLOG) IPLUSCmdR16Dec0_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPLUSCmdR16Dec0_print(p, pfx,hLOG) IPLUSCmdR16Dec0_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPLUSCmdR16Dec0 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPLUSCmdR16Dec1 flat (4,2) |
| /// ### |
| /// * IPLUS Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Type |
| /// : Dec8x8 0x6 |
| /// ### |
| /// * Tell IPLUS to start decoding a 8x8 block. This command has to be applied in the order of Y0, Y1, Y2, Y3, U, V and Y blocks are in raster scan order here. |
| /// ### |
| /// %unsigned 1 intra |
| /// ### |
| /// * Intra coded or not. 0: non-intra coded, 1: intra coded. |
| /// ### |
| /// %unsigned 2 transform_type |
| /// ### |
| /// * Transform type, 4x4 and 8x8 type is defined in IPLUSCmdR16D. |
| /// ### |
| /// : transform_8x4 0x2 |
| /// : transform_4x8 0x3 |
| /// %unsigned 4 blk_idx |
| /// ### |
| /// * Current 8x8 block's index. it implies the current 8x8 is Luma or Chroma block and implies if current is the last 8x8 block of current MB based on recon_format in RF64. |
| /// * YUV420: 0 ~ 3 for Y, 4 for U and 5 for V |
| /// * YUV422: 0 ~ 3 for Y, 4 ~ 5 for U and 6 ~ 7 for V |
| /// * YUV444: 0 ~ 3 for Y, 4 ~ 7 for U and 8 ~ 11 for V |
| /// ### |
| /// %% 21 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPLUSCmdR16Dec1 |
| #define h_IPLUSCmdR16Dec1 (){} |
| |
| #define BA_IPLUSCmdR16Dec1_Type 0x0000 |
| #define B16IPLUSCmdR16Dec1_Type 0x0000 |
| #define LSb32IPLUSCmdR16Dec1_Type 0 |
| #define LSb16IPLUSCmdR16Dec1_Type 0 |
| #define bIPLUSCmdR16Dec1_Type 4 |
| #define MSK32IPLUSCmdR16Dec1_Type 0x0000000F |
| #define IPLUSCmdR16Dec1_Type_Dec8x8 0x6 |
| |
| #define BA_IPLUSCmdR16Dec1_intra 0x0000 |
| #define B16IPLUSCmdR16Dec1_intra 0x0000 |
| #define LSb32IPLUSCmdR16Dec1_intra 4 |
| #define LSb16IPLUSCmdR16Dec1_intra 4 |
| #define bIPLUSCmdR16Dec1_intra 1 |
| #define MSK32IPLUSCmdR16Dec1_intra 0x00000010 |
| |
| #define BA_IPLUSCmdR16Dec1_transform_type 0x0000 |
| #define B16IPLUSCmdR16Dec1_transform_type 0x0000 |
| #define LSb32IPLUSCmdR16Dec1_transform_type 5 |
| #define LSb16IPLUSCmdR16Dec1_transform_type 5 |
| #define bIPLUSCmdR16Dec1_transform_type 2 |
| #define MSK32IPLUSCmdR16Dec1_transform_type 0x00000060 |
| #define IPLUSCmdR16Dec1_transform_type_transform_8x4 0x2 |
| #define IPLUSCmdR16Dec1_transform_type_transform_4x8 0x3 |
| |
| #define BA_IPLUSCmdR16Dec1_blk_idx 0x0000 |
| #define B16IPLUSCmdR16Dec1_blk_idx 0x0000 |
| #define LSb32IPLUSCmdR16Dec1_blk_idx 7 |
| #define LSb16IPLUSCmdR16Dec1_blk_idx 7 |
| #define bIPLUSCmdR16Dec1_blk_idx 4 |
| #define MSK32IPLUSCmdR16Dec1_blk_idx 0x00000780 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPLUSCmdR16Dec1 { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPLUSCmdR16Dec1_Type(r32) _BFGET_(r32, 3, 0) |
| #define SET32IPLUSCmdR16Dec1_Type(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IPLUSCmdR16Dec1_Type(r16) _BFGET_(r16, 3, 0) |
| #define SET16IPLUSCmdR16Dec1_Type(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IPLUSCmdR16Dec1_intra(r32) _BFGET_(r32, 4, 4) |
| #define SET32IPLUSCmdR16Dec1_intra(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16IPLUSCmdR16Dec1_intra(r16) _BFGET_(r16, 4, 4) |
| #define SET16IPLUSCmdR16Dec1_intra(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32IPLUSCmdR16Dec1_transform_type(r32) _BFGET_(r32, 6, 5) |
| #define SET32IPLUSCmdR16Dec1_transform_type(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16IPLUSCmdR16Dec1_transform_type(r16) _BFGET_(r16, 6, 5) |
| #define SET16IPLUSCmdR16Dec1_transform_type(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32IPLUSCmdR16Dec1_blk_idx(r32) _BFGET_(r32,10, 7) |
| #define SET32IPLUSCmdR16Dec1_blk_idx(r32,v) _BFSET_(r32,10, 7,v) |
| #define GET16IPLUSCmdR16Dec1_blk_idx(r16) _BFGET_(r16,10, 7) |
| #define SET16IPLUSCmdR16Dec1_blk_idx(r16,v) _BFSET_(r16,10, 7,v) |
| |
| UNSG32 u_Type : 4; |
| UNSG32 u_intra : 1; |
| UNSG32 u_transform_type : 2; |
| UNSG32 u_blk_idx : 4; |
| UNSG32 RSVDx0_b11 : 21; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPLUSCmdR16Dec1; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPLUSCmdR16Dec1_drvrd(SIE_IPLUSCmdR16Dec1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPLUSCmdR16Dec1_drvwr(SIE_IPLUSCmdR16Dec1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPLUSCmdR16Dec1_reset(SIE_IPLUSCmdR16Dec1 *p); |
| SIGN32 IPLUSCmdR16Dec1_cmp (SIE_IPLUSCmdR16Dec1 *p, SIE_IPLUSCmdR16Dec1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPLUSCmdR16Dec1_check(p,pie,pfx,hLOG) IPLUSCmdR16Dec1_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPLUSCmdR16Dec1_print(p, pfx,hLOG) IPLUSCmdR16Dec1_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPLUSCmdR16Dec1 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IPLUSCmdA64 flat (8,2) |
| /// ### |
| /// * IPLUS Quantization/DeQuantization matrix programming Command Definition |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 L32 |
| /// ### |
| /// * Low 32 bit to be programmed. |
| /// ### |
| /// %unsigned 32 H32 |
| /// ### |
| /// * High 32 bit to be programmed. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IPLUSCmdA64 |
| #define h_IPLUSCmdA64 (){} |
| |
| #define BA_IPLUSCmdA64_L32 0x0000 |
| #define B16IPLUSCmdA64_L32 0x0000 |
| #define LSb32IPLUSCmdA64_L32 0 |
| #define LSb16IPLUSCmdA64_L32 0 |
| #define bIPLUSCmdA64_L32 32 |
| #define MSK32IPLUSCmdA64_L32 0xFFFFFFFF |
| |
| #define BA_IPLUSCmdA64_H32 0x0004 |
| #define B16IPLUSCmdA64_H32 0x0004 |
| #define LSb32IPLUSCmdA64_H32 0 |
| #define LSb16IPLUSCmdA64_H32 0 |
| #define bIPLUSCmdA64_H32 32 |
| #define MSK32IPLUSCmdA64_H32 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IPLUSCmdA64 { |
| /////////////////////////////////////////////////////////// |
| #define GET32IPLUSCmdA64_L32(r32) _BFGET_(r32,31, 0) |
| #define SET32IPLUSCmdA64_L32(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_L32 : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32IPLUSCmdA64_H32(r32) _BFGET_(r32,31, 0) |
| #define SET32IPLUSCmdA64_H32(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_H32 : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_IPLUSCmdA64; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IPLUSCmdA64_drvrd(SIE_IPLUSCmdA64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IPLUSCmdA64_drvwr(SIE_IPLUSCmdA64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IPLUSCmdA64_reset(SIE_IPLUSCmdA64 *p); |
| SIGN32 IPLUSCmdA64_cmp (SIE_IPLUSCmdA64 *p, SIE_IPLUSCmdA64 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IPLUSCmdA64_check(p,pie,pfx,hLOG) IPLUSCmdA64_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IPLUSCmdA64_print(p, pfx,hLOG) IPLUSCmdA64_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IPLUSCmdA64 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64IPLUS flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 format 0x0 |
| /// : h264 0x0 |
| /// : wmv 0x1 |
| /// ### |
| /// * VC-1 Simple/Main profile |
| /// ### |
| /// : mpeg2 0x2 |
| /// : mpeg4 0x4 |
| /// : vc1ap 0x5 |
| /// ### |
| /// * VC-1 Advanced profile |
| /// ### |
| /// : h263 0x6 |
| /// : avs 0x7 |
| /// : rv8 0x8 |
| /// : rv9 0x9 |
| /// : jpeg 0xA |
| /// : mpeg1 0xB |
| /// : vp6 0xC |
| /// : vp82 0xD |
| /// %unsigned 4 QSatDCIdx 0x5 |
| /// ### |
| /// * DC quantization saturation lower / upper limit. Apply to DC coefficient. |
| /// * 0: [0, 0] |
| /// * 1: [0, 127] |
| /// * 2: [0, 255] |
| /// * 3: [0, 511] |
| /// * 4: [0, 2047] |
| /// * 5: [0, 32767] |
| /// * 6: [1, 254] |
| /// * 7: [0, 1023] |
| /// ### |
| /// %unsigned 4 QSatACIdx 0x5 |
| /// ### |
| /// * AC Quantization saturation lower / upper limit. Apply to AC coefficient. |
| /// * 0: [0, 0] |
| /// * 1: [0, 127] |
| /// * 2: [0, 255] |
| /// * 3: [0, 511] |
| /// * 4: [0, 2047] |
| /// * 5: [0, 32767] |
| /// * 6: [1, 254] |
| /// * 7: [0, 1023] |
| /// ### |
| /// %unsigned 4 dQSatIdx 0x5 |
| /// ### |
| /// * DeQuantization saturation lower / upper limit. |
| /// * 0: No saturation is applied. CUT to SIGN 16 bit. |
| /// * 1: [-128, 127] |
| /// * 2: [-256, 255] |
| /// * 3: [-512, 511] |
| /// * 4: [-2048, 2047] |
| /// * 5: [-32768, 32767] |
| /// * 6: [-8192, 8191] |
| /// ### |
| /// %unsigned 2 MismatchCtrl 0x0 |
| /// ### |
| /// * Mismatch control mode for dequantization. |
| /// ### |
| /// : disable 0x0 |
| /// : mpeg1 0x1 |
| /// : mpeg2 0x2 |
| /// %unsigned 1 special_DC 0x0 |
| /// ### |
| /// * set 1 for formats MPEG1/2/4, H263, VC1AP/WMV and VP6/VP82 , otherwise, set 0. |
| /// ### |
| /// %unsigned 1 abs_on 0x0 |
| /// ### |
| /// * Dequantization needs to use absolute value of quantized coefficient or not. Set to 1 for MPEG1/2/4, H263 and VC1AP/WMV. Set 0 for other formats. |
| /// ### |
| /// %unsigned 1 RDO_mode 0x0 |
| /// ### |
| /// * RDO mode |
| /// ### |
| /// : RDO_MB 0x0 |
| /// : RDO_Luma_only 0x1 |
| /// %unsigned 1 direct_trans_size 0x0 |
| /// : transform_4x4 0x0 |
| /// : transform_8x8 0x1 |
| /// %unsigned 1 force_skip 0x0 |
| /// ### |
| /// * If this flag is 1, then force all coefficient to be zero for direct mode. |
| /// ### |
| /// %unsigned 1 dc_only 0x0 |
| /// ### |
| /// * Apply for all modes. |
| /// ### |
| /// %unsigned 1 loadNB 0x0 |
| /// ### |
| /// * If to load left, up-left and up intra prediction context pixels from DMEM, Or use internal registers updated in last MB. |
| /// ### |
| /// : LOAD_UPRIGHT 0x0 |
| /// ### |
| /// * Only load up-right pixels from DMEM. Left pixels are maintained in internal registers, up-left and up pixels are derived from previous MB's up-right pixels. |
| /// * Note, when zeroOutOn is 1, LOAD_UPRIGHT mode can not be used. |
| /// * Note, when LOAD_UPRIGHT is chosen, IPLUS needs to load upright pixel from DMEM regardless current MB's type (intra/inter). |
| /// ### |
| /// : LOAD_ALL 0x1 |
| /// ### |
| /// * Load all left, up-left, up and up-right pixels from DMEM. |
| /// ### |
| /// %unsigned 2 recon_format 0x0 |
| /// ### |
| /// * Reconstructed pixel's format. It also indicates the input pixel format for JPEG encoding. |
| /// ### |
| /// : YUV420 0x0 |
| /// : YUV422 0x1 |
| /// : YUV444 0x2 |
| /// : MONO 0x3 |
| /// %unsigned 1 I_picture 0x0 |
| /// ### |
| /// * Current picture is I picture or not. Used by RV8. It is a picture level parameter. |
| /// ### |
| /// %unsigned 1 dq_rounding_on_intra 0x0 |
| /// ### |
| /// * If rounding is on or off for intra block. For MPEG1/2 and MPEG4 with MPEG style quantization (mismatchCtrl == mpeg2), it is 0. For H263 and MPEG4 with H263 style quantization (mismatchCtrl == mpeg1), it is 1. For VC1AP/WMV, it is 1 for nonuniform quantization picture and is 0 for uniform quantization picture. It is 0 for other video formats. This is a picture level parameter. |
| /// ### |
| /// %unsigned 1 dq_rounding_on_inter 0x0 |
| /// ### |
| /// * If rounding is on or off for inter block. For MPEG1/2 and MPEG4 with MPEG style quantization (mismatchCtrl == mpeg2), it is 1 for inter block. For H263 and MPEG4 with H263 style quantization (mismatchCtrl == mpeg1), it is 1. For VC1AP/WMV, it is 1 for nonuniform quantization picture and is 0 for uniform quantization picture. It is 0 for other video formats. This is a picture level parameter. |
| /// ### |
| /// %unsigned 1 zeroOutOn 0x0 |
| /// ### |
| /// * Flag to turn on/off zeroOut. 0: off, 1: on. Once zerOut is truned off, software doesn't need to check CBP or CBF to see if current coefficient block is zero out or not. Otherwise, software needs to check CBP or CBF and if a block is zero out then software need to use corresponding predictor pixels to replace reconstructed pixels outputted by IPLUS and treat this block as all zero coefficient block. |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// %unsigned 16 SSD_zeroOutThresh4x4 0x0 |
| /// %unsigned 16 SSD_zeroOutThresh8x8 0x0 |
| /// ### |
| /// * These two thresholds are effective only in inter mode. If (score < threshold) then do zeroOut for inter case. |
| /// ### |
| /// @ 0x00008 (P) |
| /// %unsigned 12 left_mb_pixels_addr |
| /// ### |
| /// * Left MB pixel address (in 16B) for intra prediction. Pixel in format 16Y, 8U, 8V. |
| /// ### |
| /// %unsigned 4 ID_IN 0x0 |
| /// ### |
| /// * Semaphore ID for IN semaphore. |
| /// ### |
| /// %unsigned 12 upleft_mb_pixels_addr |
| /// ### |
| /// * UpLeft MB neighbor pixel address (in 16B) for intra precition. Pixel in format 16Y, 8U, 8V. |
| /// ### |
| /// %unsigned 4 ID_ORIGINAL 0x1 |
| /// ### |
| /// * Semaphore ID for ORIGINAL semaphore. |
| /// ### |
| /// %unsigned 12 up_mb_pixels_addr |
| /// ### |
| /// * Up MB neighbor pixel address (in 16B) for intra precition. Pixel in format 16Y, 8U, 8V. |
| /// ### |
| /// %unsigned 4 ID_DIRECT 0x2 |
| /// ### |
| /// * Semaphore ID for DIRECT semaphore. |
| /// ### |
| /// %unsigned 12 upright_mb_pixels_addr |
| /// ### |
| /// * UpRight MB neighbor pixel address (in 16B) for intra precition. Pixel in format 16Y, 8U, 8V. |
| /// ### |
| /// %unsigned 4 ID_INTER_LUMA 0x3 |
| /// ### |
| /// * Semaphore ID for INTER_LUMA semaphore. |
| /// ### |
| /// @ 0x00010 (P) |
| /// %unsigned 12 original_addr |
| /// ### |
| /// * DMEM address of original MB Luma. Stride is fixed value 4. And Luma is followed by Chroma, there is no interval between them. Chroma_addr = original_addr + 16. |
| /// ### |
| /// %unsigned 4 ID_INTER_CHROMA 0x4 |
| /// ### |
| /// * Semaphore ID for INTER_CHROMA semaphore. |
| /// ### |
| /// %unsigned 12 inter_addr |
| /// ### |
| /// * Since there are four Luma inter predictor buffers, so chroma address = inter_addr + 16 * 4 |
| /// * And to get Luma address, we need a index to specify which one of four candidates are chosen, this index is in IPLUSCmdR16D. |
| /// * Luma address = inter_addr + idx * 16. |
| /// ### |
| /// %unsigned 4 ID_RECONSTRUCTED 0x5 |
| /// ### |
| /// * Semaphore ID for RECONSTRUCTED semaphore. |
| /// ### |
| /// %unsigned 12 direct_addr |
| /// ### |
| /// * DMEM address of direct predictor Luma. Stride is fixed value 4. And Luma is followed by Chroma, there is no interval between them. Chroma_addr = direct_addr + 16. |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 12 recon_addr |
| /// ### |
| /// * DMEM address of reconstructed MB Luma. Stride is fixed value 4. And Luma is followed by Chroma, there is no interval between them. Chroma_addr = recon_addr + 16. |
| /// * For VC1, since each pixel occupies 16 bit, the stride becomes 8, and Chroma_addr = recon_addr + 32. |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// @ 0x00018 (P) |
| /// %unsigned 9 QPY 0x0 |
| /// ### |
| /// * QP for Y. It has range 0 ~ 51 for H264, range 1 ~ 112 for MPEG2, range 2 ~ 62 for MPEG4 and H263, range 1 ~ 62 for VC1AP/WMV, range 0 ~ 63 for AVS, range 2 ~ 62 for MPEG1. |
| /// * For RV8/9, it stores QP for regular Luma coefficient and has range 0 ~ 31. |
| /// * For VP6, it stores QP for Luma AC coefficients and has range 4 ~ 376. |
| /// * For VP82, it stores QP for Luma AC coefficients (other than second transform coefficients) and has range 4 ~ 284. |
| /// ### |
| /// %signed 5 shift_cnt_Y 0 |
| /// ### |
| /// * Luma dequantization shift count with typical range [-14, 4] |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %unsigned 12 ip_lambda 0x0 |
| /// ### |
| /// * [8.4] for H264 intra prediction mode-decision |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 12 md_intra_lambda 0x0 |
| /// ### |
| /// * [8.4] for RDO mode-decision, used in intra case |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %unsigned 12 md_inter_lambda 0x0 |
| /// ### |
| /// * [8.4] for RDO mode-decision, used in inter case |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// @ 0x00020 (P) |
| /// %unsigned 9 QPU 0x0 |
| /// ### |
| /// * QP for U. It has range 0 ~ 39 for H264, range 1 ~ 112 for MPEG2, range 2 ~ 62 for MPEG4 and H263, range 1 ~ 62 for VC1AP/WMV, range 0 ~ 63 for AVS, range 2 ~ 62 for MPEG1. |
| /// * For RV8/9, it stores QP of Chroma U coefficient with raster scan index 1 ~ 15 and has range 0 ~ 25. |
| /// * For VP6, it stores QP for Chroma U AC coefficients and has range 4 ~ 376. |
| /// * Note, for VP82, it stores QP for Chroma U AC coefficients and has range 4 ~ 284. |
| /// ### |
| /// %signed 5 shift_cnt_U 0 |
| /// ### |
| /// * U dequantization shift count with typical range [-14, 4] |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %unsigned 9 QPV 0x0 |
| /// ### |
| /// * QP for V. It has range 0 ~ 39 for H264, range 1 ~ 112 for MPEG2, range 2 ~ 62 for MPEG4 and H263, range 1 ~ 62 for VC1AP/WMV, range 0 ~ 63 for AVS, range 2 ~ 62 for MPEG1. |
| /// * For RV8/9, it stores QP for Chroma V coefficient with raster scan index 1 ~ 15 and has range 0 ~ 25. |
| /// * For VP6, it stores QP for Chroma V AC coefficients and has range 4 ~ 376. |
| /// * For VP82, it stores QP for Chroma V AC coefficients and has range 4 ~ 284. |
| /// ### |
| /// %signed 5 shift_cnt_V 0 |
| /// ### |
| /// * V dequantization shift count with typical range [-14, 4] |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %unsigned 9 qstepDCY 0x8 |
| /// ### |
| /// * Quantization step for Luma DC. It is for formats other than H264 and AVS. It has range 1 ~ 8 for MPEG2, range 8 ~ 46 for MPEG4. It is always 8 for H263. For MPEG1, it is 8. For VC1AP/WMV, it has range 2 ~ 21. For RV8, it stores QP for second transform coefficient in I picture (other second transform coefficient uses QPY), and it has range 0 ~ 25. For RV9, it stores QP for three low frequency second transform coefficient (other second transform coefficient uses QPY), and it has range 0 ~ 24. |
| /// * For VP6, it stores QP for Luma DC coefficients (other than second transform coefficient) and has range 8 ~ 188. |
| /// * For VP82, it stores QP for Luma DC coefficients (other than second transform coefficient) and has range 4 ~ 157. |
| /// ### |
| /// %% 7 # Stuffing bits... |
| /// %unsigned 9 qstepDCC 0x8 |
| /// ### |
| /// * Quantization step for Chroma DC. It is for formats other than H264 and AVS. It has range 1 ~ 8 for MPEG2, range 8 ~ 25 for MPEG4. It is always 8 for H263. For MPEG1, it is 8. For VC1AP/WMV, it has range 2 ~ 21. For RV8, it stores QP for Chroma coefficient with raster scan index 0, and it has range 0 ~ 23. For RV9, it stores QP for Chroma coefficient with raster scan index 0, and it has range 0 ~ 23. |
| /// * For VP6, it stores QP for Chroma DC coefficients and has range 8 ~ 188. |
| /// * For VP82, it stores QP for Chroma DC coefficients and has range 4 ~ 132. |
| /// ### |
| /// %% 7 # Stuffing bits... |
| /// @ 0x00028 (P) |
| /// %unsigned 9 qstepDCY2 0x8 |
| /// ### |
| /// * For VP82 only, it stores QP for Y2 (second transform) DC coefficients and has range 8 ~ 314. |
| /// ### |
| /// %% 7 # Stuffing bits... |
| /// %unsigned 9 qstepACY2 0x8 |
| /// ### |
| /// * For VP82 only, it stores QP for Y2 (second transform) AC coefficients and has range 8 ~ 440. |
| /// ### |
| /// %% 7 # Stuffing bits... |
| /// %unsigned 8 extra_cost_intra 0x0 |
| /// ### |
| /// * Extra cost for best intra mode of current MB. |
| /// ### |
| /// %unsigned 8 extra_cost_direct 0x0 |
| /// ### |
| /// * Extra cost for direct mode of current MB. |
| /// ### |
| /// %unsigned 8 extra_cost_inter 0x0 |
| /// ### |
| /// * Extra cost for inter mode of current MB. |
| /// ### |
| /// %% 8 # Stuffing bits... |
| /// @ 0x00030 (P) |
| /// %unsigned 4 intra_mode_left0 0x2 |
| /// ### |
| /// * For 4x4 block 0 of left neighbor, set to the intra prediction mode when block 0 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 0 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_left1 0x2 |
| /// ### |
| /// * For 4x4 block 1 of left neighbor, set to the intra prediction mode when block 1 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 1 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_left2 0x2 |
| /// ### |
| /// * For 4x4 block 2 of left neighbor, set to the intra prediction mode when block 2 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 2 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_left3 0x2 |
| /// ### |
| /// * For 4x4 block 3 of left neighbor, set to the intra prediction mode when block 3 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 3 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_up0 0x2 |
| /// ### |
| /// * For 4x4 block 0 of up neighbor, set to the intra prediction mode when block 0 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 0 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_up1 0x2 |
| /// ### |
| /// * For 4x4 block 1 of up neighbor, set to the intra prediction mode when block 1 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 1 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_up2 0x2 |
| /// ### |
| /// * For 4x4 block 2 of up neighbor, set to the intra prediction mode when block 2 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 2 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 4 intra_mode_up3 0x2 |
| /// ### |
| /// * For 4x4 block 3 of up neighbor, set to the intra prediction mode when block 3 is available and is intra 4x4 or intra 8x8 predicted. Set to 2 when block 3 is not available or is not intra 4x4 or intra 8x8 predicted. |
| /// ### |
| /// %unsigned 1 frm_fld_pred 0x0 |
| /// ### |
| /// * Frame or field prediction. 0: frame, 1: field. Used to choose scan table for encoder. |
| /// ### |
| /// %unsigned 1 turnon_I4 0x1 |
| /// ### |
| /// * If this flag is on, Intra 4x4 will be done in Command EncIntra. |
| /// ### |
| /// %unsigned 1 turnon_I16 0x1 |
| /// ### |
| /// * If this flag is on, Intra 16x16 will be done in Command EncIntra. |
| /// ### |
| /// %unsigned 1 turnon_I8 0x1 |
| /// ### |
| /// * If this flag is on, Intra 8x8 will be done in Command EncDirect. |
| /// ### |
| /// %unsigned 1 turnon_direct 0x1 |
| /// ### |
| /// * If this flag is on, direct mode will be calculated in Command EncDirect. |
| /// ### |
| /// %unsigned 1 turnon_inter 0x1 |
| /// ### |
| /// * If this flag is on, Inter mode will be calculated in Command EncInter. |
| /// ### |
| /// %unsigned 1 not_upd_input 0x0 |
| /// ### |
| /// * 0 – check check & update IN, ORIGINAL, DIRECT, INTER_LUMA and INTER_CHROMA semaphores. Update input buffers, which are IP context, DIRECT predictor, INTER predictor and original MB, from DMEM. |
| /// * 1 -- don't check & update input semaphores. Don't update input buffers from DMEM. |
| /// ### |
| /// %unsigned 1 not_upd_output 0x0 |
| /// ### |
| /// * If this flag is on, don't check & update RECONSTRUCTED semaphore, don't output reconstructed MB, don't update IPLUS internal Intra prediction context, don't output QC, and no pop data. |
| /// * If this flag is off, check & update RECONSTRUCTED semaphore, output reconstructed MB and update IPLUS internal Intra prediction context, output QC and pop data. |
| /// * NOTE: |
| /// * BIN_SSD accumulation is not affected by these two flags. |
| /// * These two flags are only effective in Encoding. |
| /// ### |
| /// %unsigned 1 NoOverlapMB 0x0 |
| /// ### |
| /// * If the flag is on, there is no overlap between two MB's operations. |
| /// ### |
| /// %unsigned 1 dbgMode 0x0 |
| /// %unsigned 1 AvailAMode 0x0 |
| /// : AVAILA_FRAME 0x0 |
| /// : AVAILA_FIELD 0x1 |
| /// ### |
| /// * If format is not H264, AvailAMode always equal to AVAILA_FRAME. |
| /// * If format is H264 but not MBAFF, AvailMode always equal to AVAILA_FRAME. |
| /// * For H264 MBAFF case, |
| /// * Left MB pair , current MB pair , AvailAMode |
| /// * Field Field AVAILA_FRAME |
| /// * Frame Frame AVAILA_FRAME |
| /// * Field Frame AVAILA_FIELD |
| /// * Frame Field AVAILA_FRAME |
| /// ### |
| /// %unsigned 1 AvailA0 0x0 |
| /// ### |
| /// * For AvailAMode = AVAILA_FRAME |
| /// * If left MB pixel[0~7] is available for intra prediction. Set to 0 when left MB pixel[0~7] is not available or belong to an inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// * For AvailAMode = AVAILA_FIELD |
| /// * If left MB even pixel[0, 2, ... 14] is available for intra prediction. Set to 0 when left MB pixel[0, 2, ... 14] is not available or belong to an inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// * Note, the left MB pixels are organized in the same frame or field way as current MB. If current MB is a frame MB then left MB pixels are organized in frame way, and if current MB is a field MB then left MB pixels are organized in field way. |
| /// ### |
| /// %unsigned 1 AvailA1 0x0 |
| /// ### |
| /// * For AvailAMode = AVAILA_FRAME |
| /// * If left MB pixel[8~15] is available for intra prediction. Set to 0 when left MB pixel[8~15] is not available or belong to an inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// * For AvailAMode = AVAILA_FIELD |
| /// * If left MB odd pixel[1,3,...15] is available for intra prediction. Set to 0 when left MB pixel[1,3,...15] is not available or belong to an inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// * Note, the left MB pixels are organized in the same frame or field way as current MB. If current MB is a frame MB then left MB pixels are organized in frame way, and if current MB is a field MB then left MB pixels are organized in field way. |
| /// ### |
| /// %unsigned 1 AvailB 0x0 |
| /// ### |
| /// * If top MB is available for intra prediction. Set to 0 when top MB is not available or is inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// ### |
| /// %unsigned 1 AvailC 0x0 |
| /// ### |
| /// * If top-right MB is available for intra prediction. Set to 0 when top-right MB is not available or is inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// ### |
| /// %unsigned 1 AvailD 0x0 |
| /// ### |
| /// * If top-left MB is available for intra prediction. Set to 0 when top-left MB is not available or is inter MB and constrained_intra_pred_flag is 1. Otherwise, set to 1. |
| /// ### |
| /// %unsigned 12 NZBP 0x0 |
| /// ### |
| /// * For decoder, each bit indicate if corresponding 8x8 coefficient block has any non-zero coefficient or not. The bit order is from LSB to MSB. |
| /// * For reconstructed pixel format asYUV420, |
| /// * NZBP[0:3] – Luma, NZBP[4:5] – Chroma |
| /// * For reconstructed pixel format asYUV422, |
| /// * NZBP[0:3] – Luma, NZBP[4:5] – U, NZBP[6:7] - V |
| /// * For reconstructed pixel format asYUV444, |
| /// * NZBP[0:11] follows the order of input quantized coefficient block. |
| /// * For each bit, |
| /// * 0: no non-zero coefficient in the block |
| /// * 1: there is at least 1 non-zero coefficient in the block |
| /// * If the corresponding bit of a 8x8 coefficient block is 0, this coefficient block is not present in HBO so it should not be to be loaded from HBO and IPLUS should assume all coefficients in this block are 0. |
| /// ### |
| /// %unsigned 1 frm_fld_dct 0x0 |
| /// ### |
| /// * Frame or field DCT. |
| /// ### |
| /// : frame_dct 0x0 |
| /// : field_dct 0x1 |
| /// %unsigned 1 NoOverlapInMem 0x0 |
| /// ### |
| /// * If the flag is on, actual encode/decode will not start until all data from DMEM and/or HBO have been retrieved. |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 56B, bits: 448b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64IPLUS |
| #define h_RF64IPLUS (){} |
| |
| #define BA_RF64IPLUS_format 0x0000 |
| #define B16RF64IPLUS_format 0x0000 |
| #define LSb32RF64IPLUS_format 0 |
| #define LSb16RF64IPLUS_format 0 |
| #define bRF64IPLUS_format 4 |
| #define MSK32RF64IPLUS_format 0x0000000F |
| #define RF64IPLUS_format_h264 0x0 |
| #define RF64IPLUS_format_wmv 0x1 |
| #define RF64IPLUS_format_mpeg2 0x2 |
| #define RF64IPLUS_format_mpeg4 0x4 |
| #define RF64IPLUS_format_vc1ap 0x5 |
| #define RF64IPLUS_format_h263 0x6 |
| #define RF64IPLUS_format_avs 0x7 |
| #define RF64IPLUS_format_rv8 0x8 |
| #define RF64IPLUS_format_rv9 0x9 |
| #define RF64IPLUS_format_jpeg 0xA |
| #define RF64IPLUS_format_mpeg1 0xB |
| #define RF64IPLUS_format_vp6 0xC |
| #define RF64IPLUS_format_vp82 0xD |
| |
| #define BA_RF64IPLUS_QSatDCIdx 0x0000 |
| #define B16RF64IPLUS_QSatDCIdx 0x0000 |
| #define LSb32RF64IPLUS_QSatDCIdx 4 |
| #define LSb16RF64IPLUS_QSatDCIdx 4 |
| #define bRF64IPLUS_QSatDCIdx 4 |
| #define MSK32RF64IPLUS_QSatDCIdx 0x000000F0 |
| |
| #define BA_RF64IPLUS_QSatACIdx 0x0001 |
| #define B16RF64IPLUS_QSatACIdx 0x0000 |
| #define LSb32RF64IPLUS_QSatACIdx 8 |
| #define LSb16RF64IPLUS_QSatACIdx 8 |
| #define bRF64IPLUS_QSatACIdx 4 |
| #define MSK32RF64IPLUS_QSatACIdx 0x00000F00 |
| |
| #define BA_RF64IPLUS_dQSatIdx 0x0001 |
| #define B16RF64IPLUS_dQSatIdx 0x0000 |
| #define LSb32RF64IPLUS_dQSatIdx 12 |
| #define LSb16RF64IPLUS_dQSatIdx 12 |
| #define bRF64IPLUS_dQSatIdx 4 |
| #define MSK32RF64IPLUS_dQSatIdx 0x0000F000 |
| |
| #define BA_RF64IPLUS_MismatchCtrl 0x0002 |
| #define B16RF64IPLUS_MismatchCtrl 0x0002 |
| #define LSb32RF64IPLUS_MismatchCtrl 16 |
| #define LSb16RF64IPLUS_MismatchCtrl 0 |
| #define bRF64IPLUS_MismatchCtrl 2 |
| #define MSK32RF64IPLUS_MismatchCtrl 0x00030000 |
| #define RF64IPLUS_MismatchCtrl_disable 0x0 |
| #define RF64IPLUS_MismatchCtrl_mpeg1 0x1 |
| #define RF64IPLUS_MismatchCtrl_mpeg2 0x2 |
| |
| #define BA_RF64IPLUS_special_DC 0x0002 |
| #define B16RF64IPLUS_special_DC 0x0002 |
| #define LSb32RF64IPLUS_special_DC 18 |
| #define LSb16RF64IPLUS_special_DC 2 |
| #define bRF64IPLUS_special_DC 1 |
| #define MSK32RF64IPLUS_special_DC 0x00040000 |
| |
| #define BA_RF64IPLUS_abs_on 0x0002 |
| #define B16RF64IPLUS_abs_on 0x0002 |
| #define LSb32RF64IPLUS_abs_on 19 |
| #define LSb16RF64IPLUS_abs_on 3 |
| #define bRF64IPLUS_abs_on 1 |
| #define MSK32RF64IPLUS_abs_on 0x00080000 |
| |
| #define BA_RF64IPLUS_RDO_mode 0x0002 |
| #define B16RF64IPLUS_RDO_mode 0x0002 |
| #define LSb32RF64IPLUS_RDO_mode 20 |
| #define LSb16RF64IPLUS_RDO_mode 4 |
| #define bRF64IPLUS_RDO_mode 1 |
| #define MSK32RF64IPLUS_RDO_mode 0x00100000 |
| #define RF64IPLUS_RDO_mode_RDO_MB 0x0 |
| #define RF64IPLUS_RDO_mode_RDO_Luma_only 0x1 |
| |
| #define BA_RF64IPLUS_direct_trans_size 0x0002 |
| #define B16RF64IPLUS_direct_trans_size 0x0002 |
| #define LSb32RF64IPLUS_direct_trans_size 21 |
| #define LSb16RF64IPLUS_direct_trans_size 5 |
| #define bRF64IPLUS_direct_trans_size 1 |
| #define MSK32RF64IPLUS_direct_trans_size 0x00200000 |
| #define RF64IPLUS_direct_trans_size_transform_4x4 0x0 |
| #define RF64IPLUS_direct_trans_size_transform_8x8 0x1 |
| |
| #define BA_RF64IPLUS_force_skip 0x0002 |
| #define B16RF64IPLUS_force_skip 0x0002 |
| #define LSb32RF64IPLUS_force_skip 22 |
| #define LSb16RF64IPLUS_force_skip 6 |
| #define bRF64IPLUS_force_skip 1 |
| #define MSK32RF64IPLUS_force_skip 0x00400000 |
| |
| #define BA_RF64IPLUS_dc_only 0x0002 |
| #define B16RF64IPLUS_dc_only 0x0002 |
| #define LSb32RF64IPLUS_dc_only 23 |
| #define LSb16RF64IPLUS_dc_only 7 |
| #define bRF64IPLUS_dc_only 1 |
| #define MSK32RF64IPLUS_dc_only 0x00800000 |
| |
| #define BA_RF64IPLUS_loadNB 0x0003 |
| #define B16RF64IPLUS_loadNB 0x0002 |
| #define LSb32RF64IPLUS_loadNB 24 |
| #define LSb16RF64IPLUS_loadNB 8 |
| #define bRF64IPLUS_loadNB 1 |
| #define MSK32RF64IPLUS_loadNB 0x01000000 |
| #define RF64IPLUS_loadNB_LOAD_UPRIGHT 0x0 |
| #define RF64IPLUS_loadNB_LOAD_ALL 0x1 |
| |
| #define BA_RF64IPLUS_recon_format 0x0003 |
| #define B16RF64IPLUS_recon_format 0x0002 |
| #define LSb32RF64IPLUS_recon_format 25 |
| #define LSb16RF64IPLUS_recon_format 9 |
| #define bRF64IPLUS_recon_format 2 |
| #define MSK32RF64IPLUS_recon_format 0x06000000 |
| #define RF64IPLUS_recon_format_YUV420 0x0 |
| #define RF64IPLUS_recon_format_YUV422 0x1 |
| #define RF64IPLUS_recon_format_YUV444 0x2 |
| #define RF64IPLUS_recon_format_MONO 0x3 |
| |
| #define BA_RF64IPLUS_I_picture 0x0003 |
| #define B16RF64IPLUS_I_picture 0x0002 |
| #define LSb32RF64IPLUS_I_picture 27 |
| #define LSb16RF64IPLUS_I_picture 11 |
| #define bRF64IPLUS_I_picture 1 |
| #define MSK32RF64IPLUS_I_picture 0x08000000 |
| |
| #define BA_RF64IPLUS_dq_rounding_on_intra 0x0003 |
| #define B16RF64IPLUS_dq_rounding_on_intra 0x0002 |
| #define LSb32RF64IPLUS_dq_rounding_on_intra 28 |
| #define LSb16RF64IPLUS_dq_rounding_on_intra 12 |
| #define bRF64IPLUS_dq_rounding_on_intra 1 |
| #define MSK32RF64IPLUS_dq_rounding_on_intra 0x10000000 |
| |
| #define BA_RF64IPLUS_dq_rounding_on_inter 0x0003 |
| #define B16RF64IPLUS_dq_rounding_on_inter 0x0002 |
| #define LSb32RF64IPLUS_dq_rounding_on_inter 29 |
| #define LSb16RF64IPLUS_dq_rounding_on_inter 13 |
| #define bRF64IPLUS_dq_rounding_on_inter 1 |
| #define MSK32RF64IPLUS_dq_rounding_on_inter 0x20000000 |
| |
| #define BA_RF64IPLUS_zeroOutOn 0x0003 |
| #define B16RF64IPLUS_zeroOutOn 0x0002 |
| #define LSb32RF64IPLUS_zeroOutOn 30 |
| #define LSb16RF64IPLUS_zeroOutOn 14 |
| #define bRF64IPLUS_zeroOutOn 1 |
| #define MSK32RF64IPLUS_zeroOutOn 0x40000000 |
| |
| #define BA_RF64IPLUS_SSD_zeroOutThresh4x4 0x0004 |
| #define B16RF64IPLUS_SSD_zeroOutThresh4x4 0x0004 |
| #define LSb32RF64IPLUS_SSD_zeroOutThresh4x4 0 |
| #define LSb16RF64IPLUS_SSD_zeroOutThresh4x4 0 |
| #define bRF64IPLUS_SSD_zeroOutThresh4x4 16 |
| #define MSK32RF64IPLUS_SSD_zeroOutThresh4x4 0x0000FFFF |
| |
| #define BA_RF64IPLUS_SSD_zeroOutThresh8x8 0x0006 |
| #define B16RF64IPLUS_SSD_zeroOutThresh8x8 0x0006 |
| #define LSb32RF64IPLUS_SSD_zeroOutThresh8x8 16 |
| #define LSb16RF64IPLUS_SSD_zeroOutThresh8x8 0 |
| #define bRF64IPLUS_SSD_zeroOutThresh8x8 16 |
| #define MSK32RF64IPLUS_SSD_zeroOutThresh8x8 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_left_mb_pixels_addr 0x0008 |
| #define B16RF64IPLUS_left_mb_pixels_addr 0x0008 |
| #define LSb32RF64IPLUS_left_mb_pixels_addr 0 |
| #define LSb16RF64IPLUS_left_mb_pixels_addr 0 |
| #define bRF64IPLUS_left_mb_pixels_addr 12 |
| #define MSK32RF64IPLUS_left_mb_pixels_addr 0x00000FFF |
| |
| #define BA_RF64IPLUS_ID_IN 0x0009 |
| #define B16RF64IPLUS_ID_IN 0x0008 |
| #define LSb32RF64IPLUS_ID_IN 12 |
| #define LSb16RF64IPLUS_ID_IN 12 |
| #define bRF64IPLUS_ID_IN 4 |
| #define MSK32RF64IPLUS_ID_IN 0x0000F000 |
| |
| #define BA_RF64IPLUS_upleft_mb_pixels_addr 0x000A |
| #define B16RF64IPLUS_upleft_mb_pixels_addr 0x000A |
| #define LSb32RF64IPLUS_upleft_mb_pixels_addr 16 |
| #define LSb16RF64IPLUS_upleft_mb_pixels_addr 0 |
| #define bRF64IPLUS_upleft_mb_pixels_addr 12 |
| #define MSK32RF64IPLUS_upleft_mb_pixels_addr 0x0FFF0000 |
| |
| #define BA_RF64IPLUS_ID_ORIGINAL 0x000B |
| #define B16RF64IPLUS_ID_ORIGINAL 0x000A |
| #define LSb32RF64IPLUS_ID_ORIGINAL 28 |
| #define LSb16RF64IPLUS_ID_ORIGINAL 12 |
| #define bRF64IPLUS_ID_ORIGINAL 4 |
| #define MSK32RF64IPLUS_ID_ORIGINAL 0xF0000000 |
| |
| #define BA_RF64IPLUS_up_mb_pixels_addr 0x000C |
| #define B16RF64IPLUS_up_mb_pixels_addr 0x000C |
| #define LSb32RF64IPLUS_up_mb_pixels_addr 0 |
| #define LSb16RF64IPLUS_up_mb_pixels_addr 0 |
| #define bRF64IPLUS_up_mb_pixels_addr 12 |
| #define MSK32RF64IPLUS_up_mb_pixels_addr 0x00000FFF |
| |
| #define BA_RF64IPLUS_ID_DIRECT 0x000D |
| #define B16RF64IPLUS_ID_DIRECT 0x000C |
| #define LSb32RF64IPLUS_ID_DIRECT 12 |
| #define LSb16RF64IPLUS_ID_DIRECT 12 |
| #define bRF64IPLUS_ID_DIRECT 4 |
| #define MSK32RF64IPLUS_ID_DIRECT 0x0000F000 |
| |
| #define BA_RF64IPLUS_upright_mb_pixels_addr 0x000E |
| #define B16RF64IPLUS_upright_mb_pixels_addr 0x000E |
| #define LSb32RF64IPLUS_upright_mb_pixels_addr 16 |
| #define LSb16RF64IPLUS_upright_mb_pixels_addr 0 |
| #define bRF64IPLUS_upright_mb_pixels_addr 12 |
| #define MSK32RF64IPLUS_upright_mb_pixels_addr 0x0FFF0000 |
| |
| #define BA_RF64IPLUS_ID_INTER_LUMA 0x000F |
| #define B16RF64IPLUS_ID_INTER_LUMA 0x000E |
| #define LSb32RF64IPLUS_ID_INTER_LUMA 28 |
| #define LSb16RF64IPLUS_ID_INTER_LUMA 12 |
| #define bRF64IPLUS_ID_INTER_LUMA 4 |
| #define MSK32RF64IPLUS_ID_INTER_LUMA 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_original_addr 0x0010 |
| #define B16RF64IPLUS_original_addr 0x0010 |
| #define LSb32RF64IPLUS_original_addr 0 |
| #define LSb16RF64IPLUS_original_addr 0 |
| #define bRF64IPLUS_original_addr 12 |
| #define MSK32RF64IPLUS_original_addr 0x00000FFF |
| |
| #define BA_RF64IPLUS_ID_INTER_CHROMA 0x0011 |
| #define B16RF64IPLUS_ID_INTER_CHROMA 0x0010 |
| #define LSb32RF64IPLUS_ID_INTER_CHROMA 12 |
| #define LSb16RF64IPLUS_ID_INTER_CHROMA 12 |
| #define bRF64IPLUS_ID_INTER_CHROMA 4 |
| #define MSK32RF64IPLUS_ID_INTER_CHROMA 0x0000F000 |
| |
| #define BA_RF64IPLUS_inter_addr 0x0012 |
| #define B16RF64IPLUS_inter_addr 0x0012 |
| #define LSb32RF64IPLUS_inter_addr 16 |
| #define LSb16RF64IPLUS_inter_addr 0 |
| #define bRF64IPLUS_inter_addr 12 |
| #define MSK32RF64IPLUS_inter_addr 0x0FFF0000 |
| |
| #define BA_RF64IPLUS_ID_RECONSTRUCTED 0x0013 |
| #define B16RF64IPLUS_ID_RECONSTRUCTED 0x0012 |
| #define LSb32RF64IPLUS_ID_RECONSTRUCTED 28 |
| #define LSb16RF64IPLUS_ID_RECONSTRUCTED 12 |
| #define bRF64IPLUS_ID_RECONSTRUCTED 4 |
| #define MSK32RF64IPLUS_ID_RECONSTRUCTED 0xF0000000 |
| |
| #define BA_RF64IPLUS_direct_addr 0x0014 |
| #define B16RF64IPLUS_direct_addr 0x0014 |
| #define LSb32RF64IPLUS_direct_addr 0 |
| #define LSb16RF64IPLUS_direct_addr 0 |
| #define bRF64IPLUS_direct_addr 12 |
| #define MSK32RF64IPLUS_direct_addr 0x00000FFF |
| |
| #define BA_RF64IPLUS_recon_addr 0x0016 |
| #define B16RF64IPLUS_recon_addr 0x0016 |
| #define LSb32RF64IPLUS_recon_addr 16 |
| #define LSb16RF64IPLUS_recon_addr 0 |
| #define bRF64IPLUS_recon_addr 12 |
| #define MSK32RF64IPLUS_recon_addr 0x0FFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_QPY 0x0018 |
| #define B16RF64IPLUS_QPY 0x0018 |
| #define LSb32RF64IPLUS_QPY 0 |
| #define LSb16RF64IPLUS_QPY 0 |
| #define bRF64IPLUS_QPY 9 |
| #define MSK32RF64IPLUS_QPY 0x000001FF |
| |
| #define BA_RF64IPLUS_shift_cnt_Y 0x0019 |
| #define B16RF64IPLUS_shift_cnt_Y 0x0018 |
| #define LSb32RF64IPLUS_shift_cnt_Y 9 |
| #define LSb16RF64IPLUS_shift_cnt_Y 9 |
| #define bRF64IPLUS_shift_cnt_Y 5 |
| #define MSK32RF64IPLUS_shift_cnt_Y 0x00003E00 |
| |
| #define BA_RF64IPLUS_ip_lambda 0x001A |
| #define B16RF64IPLUS_ip_lambda 0x001A |
| #define LSb32RF64IPLUS_ip_lambda 16 |
| #define LSb16RF64IPLUS_ip_lambda 0 |
| #define bRF64IPLUS_ip_lambda 12 |
| #define MSK32RF64IPLUS_ip_lambda 0x0FFF0000 |
| |
| #define BA_RF64IPLUS_md_intra_lambda 0x001C |
| #define B16RF64IPLUS_md_intra_lambda 0x001C |
| #define LSb32RF64IPLUS_md_intra_lambda 0 |
| #define LSb16RF64IPLUS_md_intra_lambda 0 |
| #define bRF64IPLUS_md_intra_lambda 12 |
| #define MSK32RF64IPLUS_md_intra_lambda 0x00000FFF |
| |
| #define BA_RF64IPLUS_md_inter_lambda 0x001E |
| #define B16RF64IPLUS_md_inter_lambda 0x001E |
| #define LSb32RF64IPLUS_md_inter_lambda 16 |
| #define LSb16RF64IPLUS_md_inter_lambda 0 |
| #define bRF64IPLUS_md_inter_lambda 12 |
| #define MSK32RF64IPLUS_md_inter_lambda 0x0FFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_QPU 0x0020 |
| #define B16RF64IPLUS_QPU 0x0020 |
| #define LSb32RF64IPLUS_QPU 0 |
| #define LSb16RF64IPLUS_QPU 0 |
| #define bRF64IPLUS_QPU 9 |
| #define MSK32RF64IPLUS_QPU 0x000001FF |
| |
| #define BA_RF64IPLUS_shift_cnt_U 0x0021 |
| #define B16RF64IPLUS_shift_cnt_U 0x0020 |
| #define LSb32RF64IPLUS_shift_cnt_U 9 |
| #define LSb16RF64IPLUS_shift_cnt_U 9 |
| #define bRF64IPLUS_shift_cnt_U 5 |
| #define MSK32RF64IPLUS_shift_cnt_U 0x00003E00 |
| |
| #define BA_RF64IPLUS_QPV 0x0022 |
| #define B16RF64IPLUS_QPV 0x0022 |
| #define LSb32RF64IPLUS_QPV 16 |
| #define LSb16RF64IPLUS_QPV 0 |
| #define bRF64IPLUS_QPV 9 |
| #define MSK32RF64IPLUS_QPV 0x01FF0000 |
| |
| #define BA_RF64IPLUS_shift_cnt_V 0x0023 |
| #define B16RF64IPLUS_shift_cnt_V 0x0022 |
| #define LSb32RF64IPLUS_shift_cnt_V 25 |
| #define LSb16RF64IPLUS_shift_cnt_V 9 |
| #define bRF64IPLUS_shift_cnt_V 5 |
| #define MSK32RF64IPLUS_shift_cnt_V 0x3E000000 |
| |
| #define BA_RF64IPLUS_qstepDCY 0x0024 |
| #define B16RF64IPLUS_qstepDCY 0x0024 |
| #define LSb32RF64IPLUS_qstepDCY 0 |
| #define LSb16RF64IPLUS_qstepDCY 0 |
| #define bRF64IPLUS_qstepDCY 9 |
| #define MSK32RF64IPLUS_qstepDCY 0x000001FF |
| |
| #define BA_RF64IPLUS_qstepDCC 0x0026 |
| #define B16RF64IPLUS_qstepDCC 0x0026 |
| #define LSb32RF64IPLUS_qstepDCC 16 |
| #define LSb16RF64IPLUS_qstepDCC 0 |
| #define bRF64IPLUS_qstepDCC 9 |
| #define MSK32RF64IPLUS_qstepDCC 0x01FF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_qstepDCY2 0x0028 |
| #define B16RF64IPLUS_qstepDCY2 0x0028 |
| #define LSb32RF64IPLUS_qstepDCY2 0 |
| #define LSb16RF64IPLUS_qstepDCY2 0 |
| #define bRF64IPLUS_qstepDCY2 9 |
| #define MSK32RF64IPLUS_qstepDCY2 0x000001FF |
| |
| #define BA_RF64IPLUS_qstepACY2 0x002A |
| #define B16RF64IPLUS_qstepACY2 0x002A |
| #define LSb32RF64IPLUS_qstepACY2 16 |
| #define LSb16RF64IPLUS_qstepACY2 0 |
| #define bRF64IPLUS_qstepACY2 9 |
| #define MSK32RF64IPLUS_qstepACY2 0x01FF0000 |
| |
| #define BA_RF64IPLUS_extra_cost_intra 0x002C |
| #define B16RF64IPLUS_extra_cost_intra 0x002C |
| #define LSb32RF64IPLUS_extra_cost_intra 0 |
| #define LSb16RF64IPLUS_extra_cost_intra 0 |
| #define bRF64IPLUS_extra_cost_intra 8 |
| #define MSK32RF64IPLUS_extra_cost_intra 0x000000FF |
| |
| #define BA_RF64IPLUS_extra_cost_direct 0x002D |
| #define B16RF64IPLUS_extra_cost_direct 0x002C |
| #define LSb32RF64IPLUS_extra_cost_direct 8 |
| #define LSb16RF64IPLUS_extra_cost_direct 8 |
| #define bRF64IPLUS_extra_cost_direct 8 |
| #define MSK32RF64IPLUS_extra_cost_direct 0x0000FF00 |
| |
| #define BA_RF64IPLUS_extra_cost_inter 0x002E |
| #define B16RF64IPLUS_extra_cost_inter 0x002E |
| #define LSb32RF64IPLUS_extra_cost_inter 16 |
| #define LSb16RF64IPLUS_extra_cost_inter 0 |
| #define bRF64IPLUS_extra_cost_inter 8 |
| #define MSK32RF64IPLUS_extra_cost_inter 0x00FF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64IPLUS_intra_mode_left0 0x0030 |
| #define B16RF64IPLUS_intra_mode_left0 0x0030 |
| #define LSb32RF64IPLUS_intra_mode_left0 0 |
| #define LSb16RF64IPLUS_intra_mode_left0 0 |
| #define bRF64IPLUS_intra_mode_left0 4 |
| #define MSK32RF64IPLUS_intra_mode_left0 0x0000000F |
| |
| #define BA_RF64IPLUS_intra_mode_left1 0x0030 |
| #define B16RF64IPLUS_intra_mode_left1 0x0030 |
| #define LSb32RF64IPLUS_intra_mode_left1 4 |
| #define LSb16RF64IPLUS_intra_mode_left1 4 |
| #define bRF64IPLUS_intra_mode_left1 4 |
| #define MSK32RF64IPLUS_intra_mode_left1 0x000000F0 |
| |
| #define BA_RF64IPLUS_intra_mode_left2 0x0031 |
| #define B16RF64IPLUS_intra_mode_left2 0x0030 |
| #define LSb32RF64IPLUS_intra_mode_left2 8 |
| #define LSb16RF64IPLUS_intra_mode_left2 8 |
| #define bRF64IPLUS_intra_mode_left2 4 |
| #define MSK32RF64IPLUS_intra_mode_left2 0x00000F00 |
| |
| #define BA_RF64IPLUS_intra_mode_left3 0x0031 |
| #define B16RF64IPLUS_intra_mode_left3 0x0030 |
| #define LSb32RF64IPLUS_intra_mode_left3 12 |
| #define LSb16RF64IPLUS_intra_mode_left3 12 |
| #define bRF64IPLUS_intra_mode_left3 4 |
| #define MSK32RF64IPLUS_intra_mode_left3 0x0000F000 |
| |
| #define BA_RF64IPLUS_intra_mode_up0 0x0032 |
| #define B16RF64IPLUS_intra_mode_up0 0x0032 |
| #define LSb32RF64IPLUS_intra_mode_up0 16 |
| #define LSb16RF64IPLUS_intra_mode_up0 0 |
| #define bRF64IPLUS_intra_mode_up0 4 |
| #define MSK32RF64IPLUS_intra_mode_up0 0x000F0000 |
| |
| #define BA_RF64IPLUS_intra_mode_up1 0x0032 |
| #define B16RF64IPLUS_intra_mode_up1 0x0032 |
| #define LSb32RF64IPLUS_intra_mode_up1 20 |
| #define LSb16RF64IPLUS_intra_mode_up1 4 |
| #define bRF64IPLUS_intra_mode_up1 4 |
| #define MSK32RF64IPLUS_intra_mode_up1 0x00F00000 |
| |
| #define BA_RF64IPLUS_intra_mode_up2 0x0033 |
| #define B16RF64IPLUS_intra_mode_up2 0x0032 |
| #define LSb32RF64IPLUS_intra_mode_up2 24 |
| #define LSb16RF64IPLUS_intra_mode_up2 8 |
| #define bRF64IPLUS_intra_mode_up2 4 |
| #define MSK32RF64IPLUS_intra_mode_up2 0x0F000000 |
| |
| #define BA_RF64IPLUS_intra_mode_up3 0x0033 |
| #define B16RF64IPLUS_intra_mode_up3 0x0032 |
| #define LSb32RF64IPLUS_intra_mode_up3 28 |
| #define LSb16RF64IPLUS_intra_mode_up3 12 |
| #define bRF64IPLUS_intra_mode_up3 4 |
| #define MSK32RF64IPLUS_intra_mode_up3 0xF0000000 |
| |
| #define BA_RF64IPLUS_frm_fld_pred 0x0034 |
| #define B16RF64IPLUS_frm_fld_pred 0x0034 |
| #define LSb32RF64IPLUS_frm_fld_pred 0 |
| #define LSb16RF64IPLUS_frm_fld_pred 0 |
| #define bRF64IPLUS_frm_fld_pred 1 |
| #define MSK32RF64IPLUS_frm_fld_pred 0x00000001 |
| |
| #define BA_RF64IPLUS_turnon_I4 0x0034 |
| #define B16RF64IPLUS_turnon_I4 0x0034 |
| #define LSb32RF64IPLUS_turnon_I4 1 |
| #define LSb16RF64IPLUS_turnon_I4 1 |
| #define bRF64IPLUS_turnon_I4 1 |
| #define MSK32RF64IPLUS_turnon_I4 0x00000002 |
| |
| #define BA_RF64IPLUS_turnon_I16 0x0034 |
| #define B16RF64IPLUS_turnon_I16 0x0034 |
| #define LSb32RF64IPLUS_turnon_I16 2 |
| #define LSb16RF64IPLUS_turnon_I16 2 |
| #define bRF64IPLUS_turnon_I16 1 |
| #define MSK32RF64IPLUS_turnon_I16 0x00000004 |
| |
| #define BA_RF64IPLUS_turnon_I8 0x0034 |
| #define B16RF64IPLUS_turnon_I8 0x0034 |
| #define LSb32RF64IPLUS_turnon_I8 3 |
| #define LSb16RF64IPLUS_turnon_I8 3 |
| #define bRF64IPLUS_turnon_I8 1 |
| #define MSK32RF64IPLUS_turnon_I8 0x00000008 |
| |
| #define BA_RF64IPLUS_turnon_direct 0x0034 |
| #define B16RF64IPLUS_turnon_direct 0x0034 |
| #define LSb32RF64IPLUS_turnon_direct 4 |
| #define LSb16RF64IPLUS_turnon_direct 4 |
| #define bRF64IPLUS_turnon_direct 1 |
| #define MSK32RF64IPLUS_turnon_direct 0x00000010 |
| |
| #define BA_RF64IPLUS_turnon_inter 0x0034 |
| #define B16RF64IPLUS_turnon_inter 0x0034 |
| #define LSb32RF64IPLUS_turnon_inter 5 |
| #define LSb16RF64IPLUS_turnon_inter 5 |
| #define bRF64IPLUS_turnon_inter 1 |
| #define MSK32RF64IPLUS_turnon_inter 0x00000020 |
| |
| #define BA_RF64IPLUS_not_upd_input 0x0034 |
| #define B16RF64IPLUS_not_upd_input 0x0034 |
| #define LSb32RF64IPLUS_not_upd_input 6 |
| #define LSb16RF64IPLUS_not_upd_input 6 |
| #define bRF64IPLUS_not_upd_input 1 |
| #define MSK32RF64IPLUS_not_upd_input 0x00000040 |
| |
| #define BA_RF64IPLUS_not_upd_output 0x0034 |
| #define B16RF64IPLUS_not_upd_output 0x0034 |
| #define LSb32RF64IPLUS_not_upd_output 7 |
| #define LSb16RF64IPLUS_not_upd_output 7 |
| #define bRF64IPLUS_not_upd_output 1 |
| #define MSK32RF64IPLUS_not_upd_output 0x00000080 |
| |
| #define BA_RF64IPLUS_NoOverlapMB 0x0035 |
| #define B16RF64IPLUS_NoOverlapMB 0x0034 |
| #define LSb32RF64IPLUS_NoOverlapMB 8 |
| #define LSb16RF64IPLUS_NoOverlapMB 8 |
| #define bRF64IPLUS_NoOverlapMB 1 |
| #define MSK32RF64IPLUS_NoOverlapMB 0x00000100 |
| |
| #define BA_RF64IPLUS_dbgMode 0x0035 |
| #define B16RF64IPLUS_dbgMode 0x0034 |
| #define LSb32RF64IPLUS_dbgMode 9 |
| #define LSb16RF64IPLUS_dbgMode 9 |
| #define bRF64IPLUS_dbgMode 1 |
| #define MSK32RF64IPLUS_dbgMode 0x00000200 |
| |
| #define BA_RF64IPLUS_AvailAMode 0x0035 |
| #define B16RF64IPLUS_AvailAMode 0x0034 |
| #define LSb32RF64IPLUS_AvailAMode 10 |
| #define LSb16RF64IPLUS_AvailAMode 10 |
| #define bRF64IPLUS_AvailAMode 1 |
| #define MSK32RF64IPLUS_AvailAMode 0x00000400 |
| #define RF64IPLUS_AvailAMode_AVAILA_FRAME 0x0 |
| #define RF64IPLUS_AvailAMode_AVAILA_FIELD 0x1 |
| |
| #define BA_RF64IPLUS_AvailA0 0x0035 |
| #define B16RF64IPLUS_AvailA0 0x0034 |
| #define LSb32RF64IPLUS_AvailA0 11 |
| #define LSb16RF64IPLUS_AvailA0 11 |
| #define bRF64IPLUS_AvailA0 1 |
| #define MSK32RF64IPLUS_AvailA0 0x00000800 |
| |
| #define BA_RF64IPLUS_AvailA1 0x0035 |
| #define B16RF64IPLUS_AvailA1 0x0034 |
| #define LSb32RF64IPLUS_AvailA1 12 |
| #define LSb16RF64IPLUS_AvailA1 12 |
| #define bRF64IPLUS_AvailA1 1 |
| #define MSK32RF64IPLUS_AvailA1 0x00001000 |
| |
| #define BA_RF64IPLUS_AvailB 0x0035 |
| #define B16RF64IPLUS_AvailB 0x0034 |
| #define LSb32RF64IPLUS_AvailB 13 |
| #define LSb16RF64IPLUS_AvailB 13 |
| #define bRF64IPLUS_AvailB 1 |
| #define MSK32RF64IPLUS_AvailB 0x00002000 |
| |
| #define BA_RF64IPLUS_AvailC 0x0035 |
| #define B16RF64IPLUS_AvailC 0x0034 |
| #define LSb32RF64IPLUS_AvailC 14 |
| #define LSb16RF64IPLUS_AvailC 14 |
| #define bRF64IPLUS_AvailC 1 |
| #define MSK32RF64IPLUS_AvailC 0x00004000 |
| |
| #define BA_RF64IPLUS_AvailD 0x0035 |
| #define B16RF64IPLUS_AvailD 0x0034 |
| #define LSb32RF64IPLUS_AvailD 15 |
| #define LSb16RF64IPLUS_AvailD 15 |
| #define bRF64IPLUS_AvailD 1 |
| #define MSK32RF64IPLUS_AvailD 0x00008000 |
| |
| #define BA_RF64IPLUS_NZBP 0x0036 |
| #define B16RF64IPLUS_NZBP 0x0036 |
| #define LSb32RF64IPLUS_NZBP 16 |
| #define LSb16RF64IPLUS_NZBP 0 |
| #define bRF64IPLUS_NZBP 12 |
| #define MSK32RF64IPLUS_NZBP 0x0FFF0000 |
| |
| #define BA_RF64IPLUS_frm_fld_dct 0x0037 |
| #define B16RF64IPLUS_frm_fld_dct 0x0036 |
| #define LSb32RF64IPLUS_frm_fld_dct 28 |
| #define LSb16RF64IPLUS_frm_fld_dct 12 |
| #define bRF64IPLUS_frm_fld_dct 1 |
| #define MSK32RF64IPLUS_frm_fld_dct 0x10000000 |
| #define RF64IPLUS_frm_fld_dct_frame_dct 0x0 |
| #define RF64IPLUS_frm_fld_dct_field_dct 0x1 |
| |
| #define BA_RF64IPLUS_NoOverlapInMem 0x0037 |
| #define B16RF64IPLUS_NoOverlapInMem 0x0036 |
| #define LSb32RF64IPLUS_NoOverlapInMem 29 |
| #define LSb16RF64IPLUS_NoOverlapInMem 13 |
| #define bRF64IPLUS_NoOverlapInMem 1 |
| #define MSK32RF64IPLUS_NoOverlapInMem 0x20000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64IPLUS { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_format(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64IPLUS_format(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64IPLUS_format(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64IPLUS_format(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64IPLUS_QSatDCIdx(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64IPLUS_QSatDCIdx(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64IPLUS_QSatDCIdx(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64IPLUS_QSatDCIdx(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64IPLUS_QSatACIdx(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64IPLUS_QSatACIdx(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64IPLUS_QSatACIdx(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64IPLUS_QSatACIdx(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64IPLUS_dQSatIdx(r32) _BFGET_(r32,15,12) |
| #define SET32RF64IPLUS_dQSatIdx(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64IPLUS_dQSatIdx(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_dQSatIdx(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64IPLUS_MismatchCtrl(r32) _BFGET_(r32,17,16) |
| #define SET32RF64IPLUS_MismatchCtrl(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16RF64IPLUS_MismatchCtrl(r16) _BFGET_(r16, 1, 0) |
| #define SET16RF64IPLUS_MismatchCtrl(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32RF64IPLUS_special_DC(r32) _BFGET_(r32,18,18) |
| #define SET32RF64IPLUS_special_DC(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16RF64IPLUS_special_DC(r16) _BFGET_(r16, 2, 2) |
| #define SET16RF64IPLUS_special_DC(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32RF64IPLUS_abs_on(r32) _BFGET_(r32,19,19) |
| #define SET32RF64IPLUS_abs_on(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16RF64IPLUS_abs_on(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64IPLUS_abs_on(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64IPLUS_RDO_mode(r32) _BFGET_(r32,20,20) |
| #define SET32RF64IPLUS_RDO_mode(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16RF64IPLUS_RDO_mode(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64IPLUS_RDO_mode(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32RF64IPLUS_direct_trans_size(r32) _BFGET_(r32,21,21) |
| #define SET32RF64IPLUS_direct_trans_size(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16RF64IPLUS_direct_trans_size(r16) _BFGET_(r16, 5, 5) |
| #define SET16RF64IPLUS_direct_trans_size(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32RF64IPLUS_force_skip(r32) _BFGET_(r32,22,22) |
| #define SET32RF64IPLUS_force_skip(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16RF64IPLUS_force_skip(r16) _BFGET_(r16, 6, 6) |
| #define SET16RF64IPLUS_force_skip(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32RF64IPLUS_dc_only(r32) _BFGET_(r32,23,23) |
| #define SET32RF64IPLUS_dc_only(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16RF64IPLUS_dc_only(r16) _BFGET_(r16, 7, 7) |
| #define SET16RF64IPLUS_dc_only(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32RF64IPLUS_loadNB(r32) _BFGET_(r32,24,24) |
| #define SET32RF64IPLUS_loadNB(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16RF64IPLUS_loadNB(r16) _BFGET_(r16, 8, 8) |
| #define SET16RF64IPLUS_loadNB(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32RF64IPLUS_recon_format(r32) _BFGET_(r32,26,25) |
| #define SET32RF64IPLUS_recon_format(r32,v) _BFSET_(r32,26,25,v) |
| #define GET16RF64IPLUS_recon_format(r16) _BFGET_(r16,10, 9) |
| #define SET16RF64IPLUS_recon_format(r16,v) _BFSET_(r16,10, 9,v) |
| |
| #define GET32RF64IPLUS_I_picture(r32) _BFGET_(r32,27,27) |
| #define SET32RF64IPLUS_I_picture(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16RF64IPLUS_I_picture(r16) _BFGET_(r16,11,11) |
| #define SET16RF64IPLUS_I_picture(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32RF64IPLUS_dq_rounding_on_intra(r32) _BFGET_(r32,28,28) |
| #define SET32RF64IPLUS_dq_rounding_on_intra(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16RF64IPLUS_dq_rounding_on_intra(r16) _BFGET_(r16,12,12) |
| #define SET16RF64IPLUS_dq_rounding_on_intra(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64IPLUS_dq_rounding_on_inter(r32) _BFGET_(r32,29,29) |
| #define SET32RF64IPLUS_dq_rounding_on_inter(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16RF64IPLUS_dq_rounding_on_inter(r16) _BFGET_(r16,13,13) |
| #define SET16RF64IPLUS_dq_rounding_on_inter(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64IPLUS_zeroOutOn(r32) _BFGET_(r32,30,30) |
| #define SET32RF64IPLUS_zeroOutOn(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16RF64IPLUS_zeroOutOn(r16) _BFGET_(r16,14,14) |
| #define SET16RF64IPLUS_zeroOutOn(r16,v) _BFSET_(r16,14,14,v) |
| |
| UNSG32 u_format : 4; |
| UNSG32 u_QSatDCIdx : 4; |
| UNSG32 u_QSatACIdx : 4; |
| UNSG32 u_dQSatIdx : 4; |
| UNSG32 u_MismatchCtrl : 2; |
| UNSG32 u_special_DC : 1; |
| UNSG32 u_abs_on : 1; |
| UNSG32 u_RDO_mode : 1; |
| UNSG32 u_direct_trans_size : 1; |
| UNSG32 u_force_skip : 1; |
| UNSG32 u_dc_only : 1; |
| UNSG32 u_loadNB : 1; |
| UNSG32 u_recon_format : 2; |
| UNSG32 u_I_picture : 1; |
| UNSG32 u_dq_rounding_on_intra : 1; |
| UNSG32 u_dq_rounding_on_inter : 1; |
| UNSG32 u_zeroOutOn : 1; |
| UNSG32 RSVDx0_b31 : 1; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_SSD_zeroOutThresh4x4(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64IPLUS_SSD_zeroOutThresh4x4(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64IPLUS_SSD_zeroOutThresh4x4(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPLUS_SSD_zeroOutThresh4x4(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64IPLUS_SSD_zeroOutThresh8x8(r32) _BFGET_(r32,31,16) |
| #define SET32RF64IPLUS_SSD_zeroOutThresh8x8(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RF64IPLUS_SSD_zeroOutThresh8x8(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64IPLUS_SSD_zeroOutThresh8x8(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_SSD_zeroOutThresh4x4 : 16; |
| UNSG32 u_SSD_zeroOutThresh8x8 : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_left_mb_pixels_addr(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPLUS_left_mb_pixels_addr(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPLUS_left_mb_pixels_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_left_mb_pixels_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_IN(r32) _BFGET_(r32,15,12) |
| #define SET32RF64IPLUS_ID_IN(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64IPLUS_ID_IN(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_IN(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64IPLUS_upleft_mb_pixels_addr(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_upleft_mb_pixels_addr(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_upleft_mb_pixels_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_upleft_mb_pixels_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_ORIGINAL(r32) _BFGET_(r32,31,28) |
| #define SET32RF64IPLUS_ID_ORIGINAL(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64IPLUS_ID_ORIGINAL(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_ORIGINAL(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_left_mb_pixels_addr : 12; |
| UNSG32 u_ID_IN : 4; |
| UNSG32 u_upleft_mb_pixels_addr : 12; |
| UNSG32 u_ID_ORIGINAL : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_up_mb_pixels_addr(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPLUS_up_mb_pixels_addr(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPLUS_up_mb_pixels_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_up_mb_pixels_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_DIRECT(r32) _BFGET_(r32,15,12) |
| #define SET32RF64IPLUS_ID_DIRECT(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64IPLUS_ID_DIRECT(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_DIRECT(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64IPLUS_upright_mb_pixels_addr(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_upright_mb_pixels_addr(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_upright_mb_pixels_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_upright_mb_pixels_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_INTER_LUMA(r32) _BFGET_(r32,31,28) |
| #define SET32RF64IPLUS_ID_INTER_LUMA(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64IPLUS_ID_INTER_LUMA(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_INTER_LUMA(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_up_mb_pixels_addr : 12; |
| UNSG32 u_ID_DIRECT : 4; |
| UNSG32 u_upright_mb_pixels_addr : 12; |
| UNSG32 u_ID_INTER_LUMA : 4; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_original_addr(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPLUS_original_addr(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPLUS_original_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_original_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_INTER_CHROMA(r32) _BFGET_(r32,15,12) |
| #define SET32RF64IPLUS_ID_INTER_CHROMA(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64IPLUS_ID_INTER_CHROMA(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_INTER_CHROMA(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64IPLUS_inter_addr(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_inter_addr(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_inter_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_inter_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_ID_RECONSTRUCTED(r32) _BFGET_(r32,31,28) |
| #define SET32RF64IPLUS_ID_RECONSTRUCTED(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64IPLUS_ID_RECONSTRUCTED(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_ID_RECONSTRUCTED(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_original_addr : 12; |
| UNSG32 u_ID_INTER_CHROMA : 4; |
| UNSG32 u_inter_addr : 12; |
| UNSG32 u_ID_RECONSTRUCTED : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_direct_addr(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPLUS_direct_addr(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPLUS_direct_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_direct_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_recon_addr(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_recon_addr(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_recon_addr(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_recon_addr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| UNSG32 u_direct_addr : 12; |
| UNSG32 RSVDx14_b12 : 4; |
| UNSG32 u_recon_addr : 12; |
| UNSG32 RSVDx14_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_QPY(r32) _BFGET_(r32, 8, 0) |
| #define SET32RF64IPLUS_QPY(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16RF64IPLUS_QPY(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_QPY(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32RF64IPLUS_shift_cnt_Y(r32) _BFGET_(r32,13, 9) |
| #define SET32RF64IPLUS_shift_cnt_Y(r32,v) _BFSET_(r32,13, 9,v) |
| #define GET16RF64IPLUS_shift_cnt_Y(r16) _BFGET_(r16,13, 9) |
| #define SET16RF64IPLUS_shift_cnt_Y(r16,v) _BFSET_(r16,13, 9,v) |
| |
| #define GET32RF64IPLUS_ip_lambda(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_ip_lambda(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_ip_lambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_ip_lambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| UNSG32 u_QPY : 9; |
| UNSG32 s_shift_cnt_Y : 5; |
| UNSG32 RSVDx18_b14 : 2; |
| UNSG32 u_ip_lambda : 12; |
| UNSG32 RSVDx18_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_md_intra_lambda(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64IPLUS_md_intra_lambda(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64IPLUS_md_intra_lambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_md_intra_lambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_md_inter_lambda(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_md_inter_lambda(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_md_inter_lambda(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_md_inter_lambda(r16,v) _BFSET_(r16,11, 0,v) |
| |
| UNSG32 u_md_intra_lambda : 12; |
| UNSG32 RSVDx1C_b12 : 4; |
| UNSG32 u_md_inter_lambda : 12; |
| UNSG32 RSVDx1C_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_QPU(r32) _BFGET_(r32, 8, 0) |
| #define SET32RF64IPLUS_QPU(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16RF64IPLUS_QPU(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_QPU(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32RF64IPLUS_shift_cnt_U(r32) _BFGET_(r32,13, 9) |
| #define SET32RF64IPLUS_shift_cnt_U(r32,v) _BFSET_(r32,13, 9,v) |
| #define GET16RF64IPLUS_shift_cnt_U(r16) _BFGET_(r16,13, 9) |
| #define SET16RF64IPLUS_shift_cnt_U(r16,v) _BFSET_(r16,13, 9,v) |
| |
| #define GET32RF64IPLUS_QPV(r32) _BFGET_(r32,24,16) |
| #define SET32RF64IPLUS_QPV(r32,v) _BFSET_(r32,24,16,v) |
| #define GET16RF64IPLUS_QPV(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_QPV(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32RF64IPLUS_shift_cnt_V(r32) _BFGET_(r32,29,25) |
| #define SET32RF64IPLUS_shift_cnt_V(r32,v) _BFSET_(r32,29,25,v) |
| #define GET16RF64IPLUS_shift_cnt_V(r16) _BFGET_(r16,13, 9) |
| #define SET16RF64IPLUS_shift_cnt_V(r16,v) _BFSET_(r16,13, 9,v) |
| |
| UNSG32 u_QPU : 9; |
| UNSG32 s_shift_cnt_U : 5; |
| UNSG32 RSVDx20_b14 : 2; |
| UNSG32 u_QPV : 9; |
| UNSG32 s_shift_cnt_V : 5; |
| UNSG32 RSVDx20_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_qstepDCY(r32) _BFGET_(r32, 8, 0) |
| #define SET32RF64IPLUS_qstepDCY(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16RF64IPLUS_qstepDCY(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_qstepDCY(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32RF64IPLUS_qstepDCC(r32) _BFGET_(r32,24,16) |
| #define SET32RF64IPLUS_qstepDCC(r32,v) _BFSET_(r32,24,16,v) |
| #define GET16RF64IPLUS_qstepDCC(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_qstepDCC(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| UNSG32 u_qstepDCY : 9; |
| UNSG32 RSVDx24_b9 : 7; |
| UNSG32 u_qstepDCC : 9; |
| UNSG32 RSVDx24_b25 : 7; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_qstepDCY2(r32) _BFGET_(r32, 8, 0) |
| #define SET32RF64IPLUS_qstepDCY2(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16RF64IPLUS_qstepDCY2(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_qstepDCY2(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32RF64IPLUS_qstepACY2(r32) _BFGET_(r32,24,16) |
| #define SET32RF64IPLUS_qstepACY2(r32,v) _BFSET_(r32,24,16,v) |
| #define GET16RF64IPLUS_qstepACY2(r16) _BFGET_(r16, 8, 0) |
| #define SET16RF64IPLUS_qstepACY2(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| UNSG32 u_qstepDCY2 : 9; |
| UNSG32 RSVDx28_b9 : 7; |
| UNSG32 u_qstepACY2 : 9; |
| UNSG32 RSVDx28_b25 : 7; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_extra_cost_intra(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64IPLUS_extra_cost_intra(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64IPLUS_extra_cost_intra(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64IPLUS_extra_cost_intra(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64IPLUS_extra_cost_direct(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64IPLUS_extra_cost_direct(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64IPLUS_extra_cost_direct(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64IPLUS_extra_cost_direct(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64IPLUS_extra_cost_inter(r32) _BFGET_(r32,23,16) |
| #define SET32RF64IPLUS_extra_cost_inter(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64IPLUS_extra_cost_inter(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64IPLUS_extra_cost_inter(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| UNSG32 u_extra_cost_intra : 8; |
| UNSG32 u_extra_cost_direct : 8; |
| UNSG32 u_extra_cost_inter : 8; |
| UNSG32 RSVDx2C_b24 : 8; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64IPLUS_intra_mode_left0(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64IPLUS_intra_mode_left0(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64IPLUS_intra_mode_left0(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64IPLUS_intra_mode_left0(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64IPLUS_intra_mode_left1(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64IPLUS_intra_mode_left1(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64IPLUS_intra_mode_left1(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64IPLUS_intra_mode_left1(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64IPLUS_intra_mode_left2(r32) _BFGET_(r32,11, 8) |
| #define SET32RF64IPLUS_intra_mode_left2(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16RF64IPLUS_intra_mode_left2(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64IPLUS_intra_mode_left2(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64IPLUS_intra_mode_left3(r32) _BFGET_(r32,15,12) |
| #define SET32RF64IPLUS_intra_mode_left3(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64IPLUS_intra_mode_left3(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_intra_mode_left3(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64IPLUS_intra_mode_up0(r32) _BFGET_(r32,19,16) |
| #define SET32RF64IPLUS_intra_mode_up0(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16RF64IPLUS_intra_mode_up0(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64IPLUS_intra_mode_up0(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64IPLUS_intra_mode_up1(r32) _BFGET_(r32,23,20) |
| #define SET32RF64IPLUS_intra_mode_up1(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16RF64IPLUS_intra_mode_up1(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64IPLUS_intra_mode_up1(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64IPLUS_intra_mode_up2(r32) _BFGET_(r32,27,24) |
| #define SET32RF64IPLUS_intra_mode_up2(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16RF64IPLUS_intra_mode_up2(r16) _BFGET_(r16,11, 8) |
| #define SET16RF64IPLUS_intra_mode_up2(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32RF64IPLUS_intra_mode_up3(r32) _BFGET_(r32,31,28) |
| #define SET32RF64IPLUS_intra_mode_up3(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64IPLUS_intra_mode_up3(r16) _BFGET_(r16,15,12) |
| #define SET16RF64IPLUS_intra_mode_up3(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_intra_mode_left0 : 4; |
| UNSG32 u_intra_mode_left1 : 4; |
| UNSG32 u_intra_mode_left2 : 4; |
| UNSG32 u_intra_mode_left3 : 4; |
| UNSG32 u_intra_mode_up0 : 4; |
| UNSG32 u_intra_mode_up1 : 4; |
| UNSG32 u_intra_mode_up2 : 4; |
| UNSG32 u_intra_mode_up3 : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RF64IPLUS_frm_fld_pred(r32) _BFGET_(r32, 0, 0) |
| #define SET32RF64IPLUS_frm_fld_pred(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16RF64IPLUS_frm_fld_pred(r16) _BFGET_(r16, 0, 0) |
| #define SET16RF64IPLUS_frm_fld_pred(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32RF64IPLUS_turnon_I4(r32) _BFGET_(r32, 1, 1) |
| #define SET32RF64IPLUS_turnon_I4(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16RF64IPLUS_turnon_I4(r16) _BFGET_(r16, 1, 1) |
| #define SET16RF64IPLUS_turnon_I4(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32RF64IPLUS_turnon_I16(r32) _BFGET_(r32, 2, 2) |
| #define SET32RF64IPLUS_turnon_I16(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16RF64IPLUS_turnon_I16(r16) _BFGET_(r16, 2, 2) |
| #define SET16RF64IPLUS_turnon_I16(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32RF64IPLUS_turnon_I8(r32) _BFGET_(r32, 3, 3) |
| #define SET32RF64IPLUS_turnon_I8(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16RF64IPLUS_turnon_I8(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64IPLUS_turnon_I8(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64IPLUS_turnon_direct(r32) _BFGET_(r32, 4, 4) |
| #define SET32RF64IPLUS_turnon_direct(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16RF64IPLUS_turnon_direct(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64IPLUS_turnon_direct(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32RF64IPLUS_turnon_inter(r32) _BFGET_(r32, 5, 5) |
| #define SET32RF64IPLUS_turnon_inter(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16RF64IPLUS_turnon_inter(r16) _BFGET_(r16, 5, 5) |
| #define SET16RF64IPLUS_turnon_inter(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32RF64IPLUS_not_upd_input(r32) _BFGET_(r32, 6, 6) |
| #define SET32RF64IPLUS_not_upd_input(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16RF64IPLUS_not_upd_input(r16) _BFGET_(r16, 6, 6) |
| #define SET16RF64IPLUS_not_upd_input(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32RF64IPLUS_not_upd_output(r32) _BFGET_(r32, 7, 7) |
| #define SET32RF64IPLUS_not_upd_output(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16RF64IPLUS_not_upd_output(r16) _BFGET_(r16, 7, 7) |
| #define SET16RF64IPLUS_not_upd_output(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32RF64IPLUS_NoOverlapMB(r32) _BFGET_(r32, 8, 8) |
| #define SET32RF64IPLUS_NoOverlapMB(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16RF64IPLUS_NoOverlapMB(r16) _BFGET_(r16, 8, 8) |
| #define SET16RF64IPLUS_NoOverlapMB(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32RF64IPLUS_dbgMode(r32) _BFGET_(r32, 9, 9) |
| #define SET32RF64IPLUS_dbgMode(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16RF64IPLUS_dbgMode(r16) _BFGET_(r16, 9, 9) |
| #define SET16RF64IPLUS_dbgMode(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32RF64IPLUS_AvailAMode(r32) _BFGET_(r32,10,10) |
| #define SET32RF64IPLUS_AvailAMode(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16RF64IPLUS_AvailAMode(r16) _BFGET_(r16,10,10) |
| #define SET16RF64IPLUS_AvailAMode(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32RF64IPLUS_AvailA0(r32) _BFGET_(r32,11,11) |
| #define SET32RF64IPLUS_AvailA0(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16RF64IPLUS_AvailA0(r16) _BFGET_(r16,11,11) |
| #define SET16RF64IPLUS_AvailA0(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32RF64IPLUS_AvailA1(r32) _BFGET_(r32,12,12) |
| #define SET32RF64IPLUS_AvailA1(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16RF64IPLUS_AvailA1(r16) _BFGET_(r16,12,12) |
| #define SET16RF64IPLUS_AvailA1(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64IPLUS_AvailB(r32) _BFGET_(r32,13,13) |
| #define SET32RF64IPLUS_AvailB(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16RF64IPLUS_AvailB(r16) _BFGET_(r16,13,13) |
| #define SET16RF64IPLUS_AvailB(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64IPLUS_AvailC(r32) _BFGET_(r32,14,14) |
| #define SET32RF64IPLUS_AvailC(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16RF64IPLUS_AvailC(r16) _BFGET_(r16,14,14) |
| #define SET16RF64IPLUS_AvailC(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32RF64IPLUS_AvailD(r32) _BFGET_(r32,15,15) |
| #define SET32RF64IPLUS_AvailD(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16RF64IPLUS_AvailD(r16) _BFGET_(r16,15,15) |
| #define SET16RF64IPLUS_AvailD(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32RF64IPLUS_NZBP(r32) _BFGET_(r32,27,16) |
| #define SET32RF64IPLUS_NZBP(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64IPLUS_NZBP(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64IPLUS_NZBP(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64IPLUS_frm_fld_dct(r32) _BFGET_(r32,28,28) |
| #define SET32RF64IPLUS_frm_fld_dct(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16RF64IPLUS_frm_fld_dct(r16) _BFGET_(r16,12,12) |
| #define SET16RF64IPLUS_frm_fld_dct(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64IPLUS_NoOverlapInMem(r32) _BFGET_(r32,29,29) |
| #define SET32RF64IPLUS_NoOverlapInMem(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16RF64IPLUS_NoOverlapInMem(r16) _BFGET_(r16,13,13) |
| #define SET16RF64IPLUS_NoOverlapInMem(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_frm_fld_pred : 1; |
| UNSG32 u_turnon_I4 : 1; |
| UNSG32 u_turnon_I16 : 1; |
| UNSG32 u_turnon_I8 : 1; |
| UNSG32 u_turnon_direct : 1; |
| UNSG32 u_turnon_inter : 1; |
| UNSG32 u_not_upd_input : 1; |
| UNSG32 u_not_upd_output : 1; |
| UNSG32 u_NoOverlapMB : 1; |
| UNSG32 u_dbgMode : 1; |
| UNSG32 u_AvailAMode : 1; |
| UNSG32 u_AvailA0 : 1; |
| UNSG32 u_AvailA1 : 1; |
| UNSG32 u_AvailB : 1; |
| UNSG32 u_AvailC : 1; |
| UNSG32 u_AvailD : 1; |
| UNSG32 u_NZBP : 12; |
| UNSG32 u_frm_fld_dct : 1; |
| UNSG32 u_NoOverlapInMem : 1; |
| UNSG32 RSVDx34_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64IPLUS; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64IPLUS_drvrd(SIE_RF64IPLUS *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64IPLUS_drvwr(SIE_RF64IPLUS *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64IPLUS_reset(SIE_RF64IPLUS *p); |
| SIGN32 RF64IPLUS_cmp (SIE_RF64IPLUS *p, SIE_RF64IPLUS *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64IPLUS_check(p,pie,pfx,hLOG) RF64IPLUS_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64IPLUS_print(p, pfx,hLOG) RF64IPLUS_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64IPLUS |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RDMBResult flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 3 MB_Type |
| /// ### |
| /// * Macroblock type |
| /// ### |
| /// : skip 0x0 |
| /// ### |
| /// * For direct MB, if its CBP is 0, set its MB type as skip. |
| /// ### |
| /// : direct16x16 0x1 |
| /// : 4BLK 0x2 |
| /// : inter 0x3 |
| /// : IPCM 0x4 |
| /// : intra16x16 0x5 |
| /// : intraNxN 0x6 |
| /// ### |
| /// * Used MB type in IPLUS: |
| /// * H264: skip, direct16x16, inter, intra16x16, intraNxN |
| /// * MPEG4: skip, direct16x16, inter, intra16x16 |
| /// * MPEG2/H263: inter, intra16x16 |
| /// * If current mode is direct and CBP is 0, set to skip type. |
| /// ### |
| /// %unsigned 1 Transform_Type |
| /// ### |
| /// * Luma transform type as defined in Section 6.1.1 (IPLUS command) |
| /// ### |
| /// %unsigned 2 Best_Intra_Mode_UV |
| /// ### |
| /// * Best Chroma intra prediction mode. |
| /// ### |
| /// : Intra_Chroma_DC 0x0 |
| /// : Intra_Chroma_Horizontal 0x1 |
| /// : Intra_Chroma_Vertical 0x2 |
| /// : Intra_Chroma_Plane 0x3 |
| /// %% 2 # Stuffing bits... |
| /// %unsigned 8 CBP |
| /// ### |
| /// * CBP[3:0] – luma, |
| /// * CBP[5:4] – YUV420 chroma |
| /// * CBP[7:4] – YUV422 chroma |
| /// * Fill 0 for unused bits. |
| /// ### |
| /// %unsigned 16 CBFy |
| /// ### |
| /// * one bit for each 4x4 Luma block. For H264 intra 16x16 MB, the bit is 1 if there’s any nonzero AC coefficient in the 4x4 block; For H264 4x4 transform block, the bit is 1 if there’s any nonzero coefficient (DC or AC) in the 4x4 block; For H264 8x8 transform block, the 4 bits are 0xF if there’s any nonzero coefficient (DC or AC) in the 8x8 block, otherwise, the 4 bits are 0; For JPEG, the bits is set to 0. For VP82, if Y2 coefficient presents, the bit is 1 if there’s any nonzero AC coefficient in the 4x4 block; if there is no Y2 coefficient, the bit is 1 if there’s any nonzero coefficient (DC or AC) in the 4x4 block. For other formats, the bit is 1 if there’s any nonzero coefficient (DC or AC) in the 4x4 block; |
| /// ### |
| /// %unsigned 4 CBFu |
| /// ### |
| /// * For H264, one bit for each 4x4 chroma U block. The bit is 1 if there’s any nonzero AC coefficient for the corresponding 4x4 chroma U block within the MB. For JPEG, the bits is set to 0. For VP82, the bit is 1 if there’s any nonzero coefficient (DC or AC) in the 4x4 Chroma U block. For other formats, the bit is 1 if there’s any nonzero coefficient (DC or AC) for the corresponding 4x4 chroma U block. |
| /// ### |
| /// %unsigned 4 CBFv |
| /// ### |
| /// * one bit for each H264 4x4 chroma V block. The bit is 1 if there’s any nonzero AC coefficient for the corresponding 4x4 chroma V block within the MB. For JPEG, the bits is set to 0. For VP82, the bit is 1 if there’s any nonzero coefficient (DC or AC) in the 4x4 Chroma V block. For other formats, the bit is 1 if there’s any nonzero coefficient (DC or AC) for the corresponding 4x4 chroma V block. |
| /// ### |
| /// %unsigned 1 CBF16x16I |
| /// ### |
| /// * only valid for H264 intra 16x16 MB and VP82 Y2 block; For H264, the bit is set to 1 if any DC coefficient of any 4x4 luma block is nonzero; otherwise it’s set to zero. For VP82, the bit is set to 1 if any Y2 coefficient of Y2 block is nonzero; otherwise it’s set to zero. For other cases, the bit is set to 0. |
| /// ### |
| /// %unsigned 1 CBF4x4U |
| /// ### |
| /// * only valid for H264 chroma block; the bit is set to 1 if any DC coefficient of any 4x4 chroma U block is nonzero; otherwise it’s set to zero. For other cases, the bit is set to 0. |
| /// ### |
| /// %unsigned 1 CBF4x4V |
| /// ### |
| /// * only valid for H264 chroma block; the bit is set to 1 if any DC coefficient of any 4x4 chroma V block is nonzero; otherwise it’s set to zero. For other cases, the bit is set to 0. |
| /// ### |
| /// %% 21 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RDMBResult |
| #define h_RDMBResult (){} |
| |
| #define BA_RDMBResult_MB_Type 0x0000 |
| #define B16RDMBResult_MB_Type 0x0000 |
| #define LSb32RDMBResult_MB_Type 0 |
| #define LSb16RDMBResult_MB_Type 0 |
| #define bRDMBResult_MB_Type 3 |
| #define MSK32RDMBResult_MB_Type 0x00000007 |
| #define RDMBResult_MB_Type_skip 0x0 |
| #define RDMBResult_MB_Type_direct16x16 0x1 |
| #define RDMBResult_MB_Type_4BLK 0x2 |
| #define RDMBResult_MB_Type_inter 0x3 |
| #define RDMBResult_MB_Type_IPCM 0x4 |
| #define RDMBResult_MB_Type_intra16x16 0x5 |
| #define RDMBResult_MB_Type_intraNxN 0x6 |
| |
| #define BA_RDMBResult_Transform_Type 0x0000 |
| #define B16RDMBResult_Transform_Type 0x0000 |
| #define LSb32RDMBResult_Transform_Type 3 |
| #define LSb16RDMBResult_Transform_Type 3 |
| #define bRDMBResult_Transform_Type 1 |
| #define MSK32RDMBResult_Transform_Type 0x00000008 |
| |
| #define BA_RDMBResult_Best_Intra_Mode_UV 0x0000 |
| #define B16RDMBResult_Best_Intra_Mode_UV 0x0000 |
| #define LSb32RDMBResult_Best_Intra_Mode_UV 4 |
| #define LSb16RDMBResult_Best_Intra_Mode_UV 4 |
| #define bRDMBResult_Best_Intra_Mode_UV 2 |
| #define MSK32RDMBResult_Best_Intra_Mode_UV 0x00000030 |
| #define RDMBResult_Best_Intra_Mode_UV_Intra_Chroma_DC 0x0 |
| #define RDMBResult_Best_Intra_Mode_UV_Intra_Chroma_Horizontal 0x1 |
| #define RDMBResult_Best_Intra_Mode_UV_Intra_Chroma_Vertical 0x2 |
| #define RDMBResult_Best_Intra_Mode_UV_Intra_Chroma_Plane 0x3 |
| |
| #define BA_RDMBResult_CBP 0x0001 |
| #define B16RDMBResult_CBP 0x0000 |
| #define LSb32RDMBResult_CBP 8 |
| #define LSb16RDMBResult_CBP 8 |
| #define bRDMBResult_CBP 8 |
| #define MSK32RDMBResult_CBP 0x0000FF00 |
| |
| #define BA_RDMBResult_CBFy 0x0002 |
| #define B16RDMBResult_CBFy 0x0002 |
| #define LSb32RDMBResult_CBFy 16 |
| #define LSb16RDMBResult_CBFy 0 |
| #define bRDMBResult_CBFy 16 |
| #define MSK32RDMBResult_CBFy 0xFFFF0000 |
| |
| #define BA_RDMBResult_CBFu 0x0004 |
| #define B16RDMBResult_CBFu 0x0004 |
| #define LSb32RDMBResult_CBFu 0 |
| #define LSb16RDMBResult_CBFu 0 |
| #define bRDMBResult_CBFu 4 |
| #define MSK32RDMBResult_CBFu 0x0000000F |
| |
| #define BA_RDMBResult_CBFv 0x0004 |
| #define B16RDMBResult_CBFv 0x0004 |
| #define LSb32RDMBResult_CBFv 4 |
| #define LSb16RDMBResult_CBFv 4 |
| #define bRDMBResult_CBFv 4 |
| #define MSK32RDMBResult_CBFv 0x000000F0 |
| |
| #define BA_RDMBResult_CBF16x16I 0x0005 |
| #define B16RDMBResult_CBF16x16I 0x0004 |
| #define LSb32RDMBResult_CBF16x16I 8 |
| #define LSb16RDMBResult_CBF16x16I 8 |
| #define bRDMBResult_CBF16x16I 1 |
| #define MSK32RDMBResult_CBF16x16I 0x00000100 |
| |
| #define BA_RDMBResult_CBF4x4U 0x0005 |
| #define B16RDMBResult_CBF4x4U 0x0004 |
| #define LSb32RDMBResult_CBF4x4U 9 |
| #define LSb16RDMBResult_CBF4x4U 9 |
| #define bRDMBResult_CBF4x4U 1 |
| #define MSK32RDMBResult_CBF4x4U 0x00000200 |
| |
| #define BA_RDMBResult_CBF4x4V 0x0005 |
| #define B16RDMBResult_CBF4x4V 0x0004 |
| #define LSb32RDMBResult_CBF4x4V 10 |
| #define LSb16RDMBResult_CBF4x4V 10 |
| #define bRDMBResult_CBF4x4V 1 |
| #define MSK32RDMBResult_CBF4x4V 0x00000400 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RDMBResult { |
| /////////////////////////////////////////////////////////// |
| #define GET32RDMBResult_MB_Type(r32) _BFGET_(r32, 2, 0) |
| #define SET32RDMBResult_MB_Type(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16RDMBResult_MB_Type(r16) _BFGET_(r16, 2, 0) |
| #define SET16RDMBResult_MB_Type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32RDMBResult_Transform_Type(r32) _BFGET_(r32, 3, 3) |
| #define SET32RDMBResult_Transform_Type(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16RDMBResult_Transform_Type(r16) _BFGET_(r16, 3, 3) |
| #define SET16RDMBResult_Transform_Type(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RDMBResult_Best_Intra_Mode_UV(r32) _BFGET_(r32, 5, 4) |
| #define SET32RDMBResult_Best_Intra_Mode_UV(r32,v) _BFSET_(r32, 5, 4,v) |
| #define GET16RDMBResult_Best_Intra_Mode_UV(r16) _BFGET_(r16, 5, 4) |
| #define SET16RDMBResult_Best_Intra_Mode_UV(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| #define GET32RDMBResult_CBP(r32) _BFGET_(r32,15, 8) |
| #define SET32RDMBResult_CBP(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RDMBResult_CBP(r16) _BFGET_(r16,15, 8) |
| #define SET16RDMBResult_CBP(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RDMBResult_CBFy(r32) _BFGET_(r32,31,16) |
| #define SET32RDMBResult_CBFy(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16RDMBResult_CBFy(r16) _BFGET_(r16,15, 0) |
| #define SET16RDMBResult_CBFy(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_MB_Type : 3; |
| UNSG32 u_Transform_Type : 1; |
| UNSG32 u_Best_Intra_Mode_UV : 2; |
| UNSG32 RSVDx0_b6 : 2; |
| UNSG32 u_CBP : 8; |
| UNSG32 u_CBFy : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32RDMBResult_CBFu(r32) _BFGET_(r32, 3, 0) |
| #define SET32RDMBResult_CBFu(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RDMBResult_CBFu(r16) _BFGET_(r16, 3, 0) |
| #define SET16RDMBResult_CBFu(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RDMBResult_CBFv(r32) _BFGET_(r32, 7, 4) |
| #define SET32RDMBResult_CBFv(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RDMBResult_CBFv(r16) _BFGET_(r16, 7, 4) |
| #define SET16RDMBResult_CBFv(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RDMBResult_CBF16x16I(r32) _BFGET_(r32, 8, 8) |
| #define SET32RDMBResult_CBF16x16I(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16RDMBResult_CBF16x16I(r16) _BFGET_(r16, 8, 8) |
| #define SET16RDMBResult_CBF16x16I(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32RDMBResult_CBF4x4U(r32) _BFGET_(r32, 9, 9) |
| #define SET32RDMBResult_CBF4x4U(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16RDMBResult_CBF4x4U(r16) _BFGET_(r16, 9, 9) |
| #define SET16RDMBResult_CBF4x4U(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32RDMBResult_CBF4x4V(r32) _BFGET_(r32,10,10) |
| #define SET32RDMBResult_CBF4x4V(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16RDMBResult_CBF4x4V(r16) _BFGET_(r16,10,10) |
| #define SET16RDMBResult_CBF4x4V(r16,v) _BFSET_(r16,10,10,v) |
| |
| UNSG32 u_CBFu : 4; |
| UNSG32 u_CBFv : 4; |
| UNSG32 u_CBF16x16I : 1; |
| UNSG32 u_CBF4x4U : 1; |
| UNSG32 u_CBF4x4V : 1; |
| UNSG32 RSVDx4_b11 : 21; |
| /////////////////////////////////////////////////////////// |
| } SIE_RDMBResult; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RDMBResult_drvrd(SIE_RDMBResult *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RDMBResult_drvwr(SIE_RDMBResult *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RDMBResult_reset(SIE_RDMBResult *p); |
| SIGN32 RDMBResult_cmp (SIE_RDMBResult *p, SIE_RDMBResult *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RDMBResult_check(p,pie,pfx,hLOG) RDMBResult_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RDMBResult_print(p, pfx,hLOG) RDMBResult_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RDMBResult |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IntraModeY flat (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 Best_Intra_Mode_Y_0i |
| /// %unsigned 4 Best_Intra_Mode_Y_1i |
| /// %unsigned 4 Best_Intra_Mode_Y_2i |
| /// %unsigned 4 Best_Intra_Mode_Y_3i |
| /// %unsigned 4 Best_Intra_Mode_Y_4i |
| /// %unsigned 4 Best_Intra_Mode_Y_5i |
| /// %unsigned 4 Best_Intra_Mode_Y_6i |
| /// %unsigned 4 Best_Intra_Mode_Y_7i |
| /// %unsigned 4 Best_Intra_Mode_Y_8i |
| /// %unsigned 4 Best_Intra_Mode_Y_9i |
| /// %unsigned 4 Best_Intra_Mode_Y_10i |
| /// %unsigned 4 Best_Intra_Mode_Y_11i |
| /// %unsigned 4 Best_Intra_Mode_Y_12i |
| /// %unsigned 4 Best_Intra_Mode_Y_13i |
| /// %unsigned 4 Best_Intra_Mode_Y_14i |
| /// %unsigned 4 Best_Intra_Mode_Y_15i |
| /// ### |
| /// * For Best_Mode_Cat_Y == Intra16x16, Intra 16x16 mode is stored in address 0; |
| /// * For Best_Mode_Cat_Y == Intra4x4, Intra 4x4 modes for each 16 4x4 block are stored in address 0 ~ 15; |
| /// * For Best_Mode_Cat_Y == Intra8x8, Intra 8x8 modes for each 8x8 block are stored in address 0 ~ 3; |
| /// ### |
| /// : Intra_16x16_Vertical 0x0 |
| /// : Intra_16x16_Horizontal 0x1 |
| /// : Intra_16x16_DC 0x2 |
| /// : Intra_16x16_Plane 0x3 |
| /// : Intra_4x4_Vertical 0x0 |
| /// : Intra_4x4_Horizontal 0x1 |
| /// : Intra_4x4_DC 0x2 |
| /// : Intra_4x4_Diagonal_Down_Left 0x3 |
| /// : Intra_4x4_Diagonal_Down_Right 0x4 |
| /// : Intra_4x4_Vertical_Right 0x5 |
| /// : Intra_4x4_Horizontal_Down 0x6 |
| /// : Intra_4x4_Vertical_Left 0x7 |
| /// : Intra_4x4_Horizontal_Up 0x8 |
| /// : Intra_8x8_Vertical 0x0 |
| /// : Intra_8x8_Horizontal 0x1 |
| /// : Intra_8x8_DC 0x2 |
| /// : Intra_8x8_Diagonal_Down_Left 0x3 |
| /// : Intra_8x8_Diagonal_Down_Right 0x4 |
| /// : Intra_8x8_Vertical_Right 0x5 |
| /// : Intra_8x8_Horizontal_Down 0x6 |
| /// : Intra_8x8_Vertical_Left 0x7 |
| /// : Intra_8x8_Horizontal_Up 0x8 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IntraModeY |
| #define h_IntraModeY (){} |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_0i 0x0000 |
| #define B16IntraModeY_Best_Intra_Mode_Y_0i 0x0000 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_0i 0 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_0i 0 |
| #define bIntraModeY_Best_Intra_Mode_Y_0i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_0i 0x0000000F |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_1i 0x0000 |
| #define B16IntraModeY_Best_Intra_Mode_Y_1i 0x0000 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define bIntraModeY_Best_Intra_Mode_Y_1i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_1i 0x000000F0 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_2i 0x0001 |
| #define B16IntraModeY_Best_Intra_Mode_Y_2i 0x0000 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_2i 8 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_2i 8 |
| #define bIntraModeY_Best_Intra_Mode_Y_2i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_2i 0x00000F00 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_3i 0x0001 |
| #define B16IntraModeY_Best_Intra_Mode_Y_3i 0x0000 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_3i 12 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_3i 12 |
| #define bIntraModeY_Best_Intra_Mode_Y_3i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_3i 0x0000F000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_4i 0x0002 |
| #define B16IntraModeY_Best_Intra_Mode_Y_4i 0x0002 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_4i 16 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_4i 0 |
| #define bIntraModeY_Best_Intra_Mode_Y_4i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_4i 0x000F0000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_5i 0x0002 |
| #define B16IntraModeY_Best_Intra_Mode_Y_5i 0x0002 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_5i 20 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_5i 4 |
| #define bIntraModeY_Best_Intra_Mode_Y_5i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_5i 0x00F00000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_6i 0x0003 |
| #define B16IntraModeY_Best_Intra_Mode_Y_6i 0x0002 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_6i 24 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_6i 8 |
| #define bIntraModeY_Best_Intra_Mode_Y_6i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_6i 0x0F000000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_7i 0x0003 |
| #define B16IntraModeY_Best_Intra_Mode_Y_7i 0x0002 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_7i 28 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_7i 12 |
| #define bIntraModeY_Best_Intra_Mode_Y_7i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_7i 0xF0000000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_8i 0x0004 |
| #define B16IntraModeY_Best_Intra_Mode_Y_8i 0x0004 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_8i 0 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_8i 0 |
| #define bIntraModeY_Best_Intra_Mode_Y_8i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_8i 0x0000000F |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_9i 0x0004 |
| #define B16IntraModeY_Best_Intra_Mode_Y_9i 0x0004 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define bIntraModeY_Best_Intra_Mode_Y_9i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_9i 0x000000F0 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_10i 0x0005 |
| #define B16IntraModeY_Best_Intra_Mode_Y_10i 0x0004 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_10i 8 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_10i 8 |
| #define bIntraModeY_Best_Intra_Mode_Y_10i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_10i 0x00000F00 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_11i 0x0005 |
| #define B16IntraModeY_Best_Intra_Mode_Y_11i 0x0004 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_11i 12 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_11i 12 |
| #define bIntraModeY_Best_Intra_Mode_Y_11i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_11i 0x0000F000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_12i 0x0006 |
| #define B16IntraModeY_Best_Intra_Mode_Y_12i 0x0006 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_12i 16 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_12i 0 |
| #define bIntraModeY_Best_Intra_Mode_Y_12i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_12i 0x000F0000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_13i 0x0006 |
| #define B16IntraModeY_Best_Intra_Mode_Y_13i 0x0006 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_13i 20 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_13i 4 |
| #define bIntraModeY_Best_Intra_Mode_Y_13i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_13i 0x00F00000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_14i 0x0007 |
| #define B16IntraModeY_Best_Intra_Mode_Y_14i 0x0006 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_14i 24 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_14i 8 |
| #define bIntraModeY_Best_Intra_Mode_Y_14i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_14i 0x0F000000 |
| |
| #define BA_IntraModeY_Best_Intra_Mode_Y_15i 0x0007 |
| #define B16IntraModeY_Best_Intra_Mode_Y_15i 0x0006 |
| #define LSb32IntraModeY_Best_Intra_Mode_Y_15i 28 |
| #define LSb16IntraModeY_Best_Intra_Mode_Y_15i 12 |
| #define bIntraModeY_Best_Intra_Mode_Y_15i 4 |
| #define MSK32IntraModeY_Best_Intra_Mode_Y_15i 0xF0000000 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_16x16_Vertical 0x0 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_16x16_Horizontal 0x1 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_16x16_DC 0x2 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_16x16_Plane 0x3 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Vertical 0x0 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Horizontal 0x1 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_DC 0x2 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Diagonal_Down_Left 0x3 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Diagonal_Down_Right 0x4 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Vertical_Right 0x5 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Horizontal_Down 0x6 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Vertical_Left 0x7 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_4x4_Horizontal_Up 0x8 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Vertical 0x0 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Horizontal 0x1 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_DC 0x2 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Diagonal_Down_Left 0x3 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Diagonal_Down_Right 0x4 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Vertical_Right 0x5 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Horizontal_Down 0x6 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Vertical_Left 0x7 |
| #define IntraModeY_Best_Intra_Mode_Y_Intra_8x8_Horizontal_Up 0x8 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IntraModeY { |
| /////////////////////////////////////////////////////////// |
| #define GET32IntraModeY_Best_Intra_Mode_Y_0i(r32) _BFGET_(r32, 3, 0) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_0i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_1i(r32) _BFGET_(r32, 7, 4) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_1i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_2i(r32) _BFGET_(r32,11, 8) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_2i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_3i(r32) _BFGET_(r32,15,12) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_3i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_3i(r16) _BFGET_(r16,15,12) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_4i(r32) _BFGET_(r32,19,16) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_4i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_4i(r16) _BFGET_(r16, 3, 0) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_4i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_5i(r32) _BFGET_(r32,23,20) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_5i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_5i(r16) _BFGET_(r16, 7, 4) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_5i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_6i(r32) _BFGET_(r32,27,24) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_6i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_6i(r16) _BFGET_(r16,11, 8) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_6i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_7i(r32) _BFGET_(r32,31,28) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_7i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_7i(r16) _BFGET_(r16,15,12) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_7i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_Best_Intra_Mode_Y_0i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_1i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_2i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_3i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_4i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_5i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_6i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_7i : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_8i(r32) _BFGET_(r32, 3, 0) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_8i(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_8i(r16) _BFGET_(r16, 3, 0) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_8i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_9i(r32) _BFGET_(r32, 7, 4) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_9i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_9i(r16) _BFGET_(r16, 7, 4) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_9i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_10i(r32) _BFGET_(r32,11, 8) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_10i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_10i(r16) _BFGET_(r16,11, 8) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_10i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_11i(r32) _BFGET_(r32,15,12) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_11i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_11i(r16) _BFGET_(r16,15,12) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_11i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_12i(r32) _BFGET_(r32,19,16) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_12i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_12i(r16) _BFGET_(r16, 3, 0) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_12i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_13i(r32) _BFGET_(r32,23,20) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_13i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_13i(r16) _BFGET_(r16, 7, 4) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_13i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_14i(r32) _BFGET_(r32,27,24) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_14i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_14i(r16) _BFGET_(r16,11, 8) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_14i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32IntraModeY_Best_Intra_Mode_Y_15i(r32) _BFGET_(r32,31,28) |
| #define SET32IntraModeY_Best_Intra_Mode_Y_15i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16IntraModeY_Best_Intra_Mode_Y_15i(r16) _BFGET_(r16,15,12) |
| #define SET16IntraModeY_Best_Intra_Mode_Y_15i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_Best_Intra_Mode_Y_8i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_9i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_10i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_11i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_12i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_13i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_14i : 4; |
| UNSG32 u_Best_Intra_Mode_Y_15i : 4; |
| /////////////////////////////////////////////////////////// |
| } SIE_IntraModeY; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IntraModeY_drvrd(SIE_IntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IntraModeY_drvwr(SIE_IntraModeY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IntraModeY_reset(SIE_IntraModeY *p); |
| SIGN32 IntraModeY_cmp (SIE_IntraModeY *p, SIE_IntraModeY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IntraModeY_check(p,pie,pfx,hLOG) IntraModeY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IntraModeY_print(p, pfx,hLOG) IntraModeY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IntraModeY |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BinSSDPIC flat (8,2) |
| /// ### |
| /// * Accumulated Bin and SSD of winners collected by quantization across a picture |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 ssd0_Y_intra |
| /// ### |
| /// * Accumulated Luma SSD for zero-out case of winners that is intra mode |
| /// ### |
| /// %unsigned 32 ssd0_Y |
| /// ### |
| /// * Accumulated Luma SSD for zero-out case of all winners |
| /// ### |
| /// @ 0x00008 (P) |
| /// %unsigned 32 bin0_Y_intra |
| /// ### |
| /// * Accumulated Luma bin count for zero-out case of winners that is intra mode |
| /// ### |
| /// %unsigned 32 bin0_Y |
| /// ### |
| /// * Accumulated Luma bin count for zero-out case of all winners |
| /// ### |
| /// @ 0x00010 (P) |
| /// %unsigned 32 ssd_Y_intra |
| /// ### |
| /// * Accumulated Luma SSD of winners that is intra mode |
| /// ### |
| /// %unsigned 32 ssd_Y |
| /// ### |
| /// * Accumulated Luma SSD of all winners |
| /// ### |
| /// @ 0x00018 (P) |
| /// %unsigned 32 bin_Y_intra |
| /// ### |
| /// * Accumulated Luma bin count of all winners that is intra mode |
| /// ### |
| /// %unsigned 32 bin_Y |
| /// ### |
| /// * Accumulated Luma bin count all winners |
| /// ### |
| /// @ 0x00020 (P) |
| /// %unsigned 32 ssd_U |
| /// ### |
| /// * Accumulated U SSD of all winners |
| /// ### |
| /// %unsigned 32 ssd_V |
| /// ### |
| /// * Accumulated V SSD of all winners |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 40B, bits: 320b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BinSSDPIC |
| #define h_BinSSDPIC (){} |
| |
| #define BA_BinSSDPIC_ssd0_Y_intra 0x0000 |
| #define B16BinSSDPIC_ssd0_Y_intra 0x0000 |
| #define LSb32BinSSDPIC_ssd0_Y_intra 0 |
| #define LSb16BinSSDPIC_ssd0_Y_intra 0 |
| #define bBinSSDPIC_ssd0_Y_intra 32 |
| #define MSK32BinSSDPIC_ssd0_Y_intra 0xFFFFFFFF |
| |
| #define BA_BinSSDPIC_ssd0_Y 0x0004 |
| #define B16BinSSDPIC_ssd0_Y 0x0004 |
| #define LSb32BinSSDPIC_ssd0_Y 0 |
| #define LSb16BinSSDPIC_ssd0_Y 0 |
| #define bBinSSDPIC_ssd0_Y 32 |
| #define MSK32BinSSDPIC_ssd0_Y 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BinSSDPIC_bin0_Y_intra 0x0008 |
| #define B16BinSSDPIC_bin0_Y_intra 0x0008 |
| #define LSb32BinSSDPIC_bin0_Y_intra 0 |
| #define LSb16BinSSDPIC_bin0_Y_intra 0 |
| #define bBinSSDPIC_bin0_Y_intra 32 |
| #define MSK32BinSSDPIC_bin0_Y_intra 0xFFFFFFFF |
| |
| #define BA_BinSSDPIC_bin0_Y 0x000C |
| #define B16BinSSDPIC_bin0_Y 0x000C |
| #define LSb32BinSSDPIC_bin0_Y 0 |
| #define LSb16BinSSDPIC_bin0_Y 0 |
| #define bBinSSDPIC_bin0_Y 32 |
| #define MSK32BinSSDPIC_bin0_Y 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BinSSDPIC_ssd_Y_intra 0x0010 |
| #define B16BinSSDPIC_ssd_Y_intra 0x0010 |
| #define LSb32BinSSDPIC_ssd_Y_intra 0 |
| #define LSb16BinSSDPIC_ssd_Y_intra 0 |
| #define bBinSSDPIC_ssd_Y_intra 32 |
| #define MSK32BinSSDPIC_ssd_Y_intra 0xFFFFFFFF |
| |
| #define BA_BinSSDPIC_ssd_Y 0x0014 |
| #define B16BinSSDPIC_ssd_Y 0x0014 |
| #define LSb32BinSSDPIC_ssd_Y 0 |
| #define LSb16BinSSDPIC_ssd_Y 0 |
| #define bBinSSDPIC_ssd_Y 32 |
| #define MSK32BinSSDPIC_ssd_Y 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BinSSDPIC_bin_Y_intra 0x0018 |
| #define B16BinSSDPIC_bin_Y_intra 0x0018 |
| #define LSb32BinSSDPIC_bin_Y_intra 0 |
| #define LSb16BinSSDPIC_bin_Y_intra 0 |
| #define bBinSSDPIC_bin_Y_intra 32 |
| #define MSK32BinSSDPIC_bin_Y_intra 0xFFFFFFFF |
| |
| #define BA_BinSSDPIC_bin_Y 0x001C |
| #define B16BinSSDPIC_bin_Y 0x001C |
| #define LSb32BinSSDPIC_bin_Y 0 |
| #define LSb16BinSSDPIC_bin_Y 0 |
| #define bBinSSDPIC_bin_Y 32 |
| #define MSK32BinSSDPIC_bin_Y 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BinSSDPIC_ssd_U 0x0020 |
| #define B16BinSSDPIC_ssd_U 0x0020 |
| #define LSb32BinSSDPIC_ssd_U 0 |
| #define LSb16BinSSDPIC_ssd_U 0 |
| #define bBinSSDPIC_ssd_U 32 |
| #define MSK32BinSSDPIC_ssd_U 0xFFFFFFFF |
| |
| #define BA_BinSSDPIC_ssd_V 0x0024 |
| #define B16BinSSDPIC_ssd_V 0x0024 |
| #define LSb32BinSSDPIC_ssd_V 0 |
| #define LSb16BinSSDPIC_ssd_V 0 |
| #define bBinSSDPIC_ssd_V 32 |
| #define MSK32BinSSDPIC_ssd_V 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BinSSDPIC { |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDPIC_ssd0_Y_intra(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd0_Y_intra(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd0_Y_intra : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSDPIC_ssd0_Y(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd0_Y(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd0_Y : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDPIC_bin0_Y_intra(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_bin0_Y_intra(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_bin0_Y_intra : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSDPIC_bin0_Y(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_bin0_Y(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_bin0_Y : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDPIC_ssd_Y_intra(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd_Y_intra(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd_Y_intra : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSDPIC_ssd_Y(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd_Y(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd_Y : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDPIC_bin_Y_intra(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_bin_Y_intra(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_bin_Y_intra : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSDPIC_bin_Y(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_bin_Y(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_bin_Y : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32BinSSDPIC_ssd_U(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd_U(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd_U : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32BinSSDPIC_ssd_V(r32) _BFGET_(r32,31, 0) |
| #define SET32BinSSDPIC_ssd_V(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_ssd_V : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_BinSSDPIC; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BinSSDPIC_drvrd(SIE_BinSSDPIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BinSSDPIC_drvwr(SIE_BinSSDPIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BinSSDPIC_reset(SIE_BinSSDPIC *p); |
| SIGN32 BinSSDPIC_cmp (SIE_BinSSDPIC *p, SIE_BinSSDPIC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BinSSDPIC_check(p,pie,pfx,hLOG) BinSSDPIC_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BinSSDPIC_print(p, pfx,hLOG) BinSSDPIC_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BinSSDPIC |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE refwinProp flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 Loc (P) |
| /// %unsigned 12 rdADDR |
| /// ### |
| /// * Base address of ref window (in 128b DMEM entry) |
| /// ### |
| /// %unsigned 4 rdSTRIDE |
| /// ### |
| /// * Reference window stride size (in 128b DMEM entry) |
| /// ### |
| /// %unsigned 12 wrADDR |
| /// ### |
| /// * Base address of predictor write-back (in 128b DMEM entry). This field will be no use from TP530 |
| /// ### |
| /// %unsigned 4 wrSTRIDE |
| /// ### |
| /// * Predictor write-back stride size (in 128b DMEM entry). This field will be no use from TP530 |
| /// ### |
| /// # 0x00004 Loc1 |
| /// %signed 8 dx4x4 |
| /// ### |
| /// * Horizontal offset from upper-left corner of the co-located MB to the upper-left corner of the reference. |
| /// ### |
| /// %signed 8 dy4x4 |
| /// ### |
| /// * Vertical offset from upper-left corner of the co-located MB to the upper-left corner of the reference window. |
| /// ### |
| /// %signed 8 mvxBase |
| /// ### |
| /// * Reference baseMV for load reference |
| /// ### |
| /// %signed 8 mvyBase |
| /// ### |
| /// * Reference baseMV for load reference |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_refwinProp |
| #define h_refwinProp (){} |
| |
| #define RA_refwinProp_Loc 0x0000 |
| |
| #define BA_refwinProp_Loc_rdADDR 0x0000 |
| #define B16refwinProp_Loc_rdADDR 0x0000 |
| #define LSb32refwinProp_Loc_rdADDR 0 |
| #define LSb16refwinProp_Loc_rdADDR 0 |
| #define brefwinProp_Loc_rdADDR 12 |
| #define MSK32refwinProp_Loc_rdADDR 0x00000FFF |
| |
| #define BA_refwinProp_Loc_rdSTRIDE 0x0001 |
| #define B16refwinProp_Loc_rdSTRIDE 0x0000 |
| #define LSb32refwinProp_Loc_rdSTRIDE 12 |
| #define LSb16refwinProp_Loc_rdSTRIDE 12 |
| #define brefwinProp_Loc_rdSTRIDE 4 |
| #define MSK32refwinProp_Loc_rdSTRIDE 0x0000F000 |
| |
| #define BA_refwinProp_Loc_wrADDR 0x0002 |
| #define B16refwinProp_Loc_wrADDR 0x0002 |
| #define LSb32refwinProp_Loc_wrADDR 16 |
| #define LSb16refwinProp_Loc_wrADDR 0 |
| #define brefwinProp_Loc_wrADDR 12 |
| #define MSK32refwinProp_Loc_wrADDR 0x0FFF0000 |
| |
| #define BA_refwinProp_Loc_wrSTRIDE 0x0003 |
| #define B16refwinProp_Loc_wrSTRIDE 0x0002 |
| #define LSb32refwinProp_Loc_wrSTRIDE 28 |
| #define LSb16refwinProp_Loc_wrSTRIDE 12 |
| #define brefwinProp_Loc_wrSTRIDE 4 |
| #define MSK32refwinProp_Loc_wrSTRIDE 0xF0000000 |
| |
| #define RA_refwinProp_Loc1 0x0004 |
| |
| #define BA_refwinProp_Loc_dx4x4 0x0004 |
| #define B16refwinProp_Loc_dx4x4 0x0004 |
| #define LSb32refwinProp_Loc_dx4x4 0 |
| #define LSb16refwinProp_Loc_dx4x4 0 |
| #define brefwinProp_Loc_dx4x4 8 |
| #define MSK32refwinProp_Loc_dx4x4 0x000000FF |
| |
| #define BA_refwinProp_Loc_dy4x4 0x0005 |
| #define B16refwinProp_Loc_dy4x4 0x0004 |
| #define LSb32refwinProp_Loc_dy4x4 8 |
| #define LSb16refwinProp_Loc_dy4x4 8 |
| #define brefwinProp_Loc_dy4x4 8 |
| #define MSK32refwinProp_Loc_dy4x4 0x0000FF00 |
| |
| #define BA_refwinProp_Loc_mvxBase 0x0006 |
| #define B16refwinProp_Loc_mvxBase 0x0006 |
| #define LSb32refwinProp_Loc_mvxBase 16 |
| #define LSb16refwinProp_Loc_mvxBase 0 |
| #define brefwinProp_Loc_mvxBase 8 |
| #define MSK32refwinProp_Loc_mvxBase 0x00FF0000 |
| |
| #define BA_refwinProp_Loc_mvyBase 0x0007 |
| #define B16refwinProp_Loc_mvyBase 0x0006 |
| #define LSb32refwinProp_Loc_mvyBase 24 |
| #define LSb16refwinProp_Loc_mvyBase 8 |
| #define brefwinProp_Loc_mvyBase 8 |
| #define MSK32refwinProp_Loc_mvyBase 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_refwinProp { |
| /////////////////////////////////////////////////////////// |
| #define GET32refwinProp_Loc_rdADDR(r32) _BFGET_(r32,11, 0) |
| #define SET32refwinProp_Loc_rdADDR(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16refwinProp_Loc_rdADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16refwinProp_Loc_rdADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32refwinProp_Loc_rdSTRIDE(r32) _BFGET_(r32,15,12) |
| #define SET32refwinProp_Loc_rdSTRIDE(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16refwinProp_Loc_rdSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16refwinProp_Loc_rdSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32refwinProp_Loc_wrADDR(r32) _BFGET_(r32,27,16) |
| #define SET32refwinProp_Loc_wrADDR(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16refwinProp_Loc_wrADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16refwinProp_Loc_wrADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32refwinProp_Loc_wrSTRIDE(r32) _BFGET_(r32,31,28) |
| #define SET32refwinProp_Loc_wrSTRIDE(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16refwinProp_Loc_wrSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16refwinProp_Loc_wrSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32refwinProp_Loc {\ |
| UNSG32 uLoc_rdADDR : 12;\ |
| UNSG32 uLoc_rdSTRIDE : 4;\ |
| UNSG32 uLoc_wrADDR : 12;\ |
| UNSG32 uLoc_wrSTRIDE : 4;\ |
| } |
| union { UNSG32 u32refwinProp_Loc; |
| struct w32refwinProp_Loc; |
| }; |
| #define GET32refwinProp_Loc_dx4x4(r32) _BFGET_(r32, 7, 0) |
| #define SET32refwinProp_Loc_dx4x4(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16refwinProp_Loc_dx4x4(r16) _BFGET_(r16, 7, 0) |
| #define SET16refwinProp_Loc_dx4x4(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32refwinProp_Loc_dy4x4(r32) _BFGET_(r32,15, 8) |
| #define SET32refwinProp_Loc_dy4x4(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16refwinProp_Loc_dy4x4(r16) _BFGET_(r16,15, 8) |
| #define SET16refwinProp_Loc_dy4x4(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32refwinProp_Loc_mvxBase(r32) _BFGET_(r32,23,16) |
| #define SET32refwinProp_Loc_mvxBase(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16refwinProp_Loc_mvxBase(r16) _BFGET_(r16, 7, 0) |
| #define SET16refwinProp_Loc_mvxBase(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32refwinProp_Loc_mvyBase(r32) _BFGET_(r32,31,24) |
| #define SET32refwinProp_Loc_mvyBase(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16refwinProp_Loc_mvyBase(r16) _BFGET_(r16,15, 8) |
| #define SET16refwinProp_Loc_mvyBase(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32refwinProp_Loc1 {\ |
| UNSG32 sLoc_dx4x4 : 8;\ |
| UNSG32 sLoc_dy4x4 : 8;\ |
| UNSG32 sLoc_mvxBase : 8;\ |
| UNSG32 sLoc_mvyBase : 8;\ |
| } |
| union { UNSG32 u32refwinProp_Loc1; |
| struct w32refwinProp_Loc1; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_refwinProp; |
| |
| typedef union T32refwinProp_Loc |
| { UNSG32 u32; |
| struct w32refwinProp_Loc; |
| } T32refwinProp_Loc; |
| typedef union T32refwinProp_Loc1 |
| { UNSG32 u32; |
| struct w32refwinProp_Loc1; |
| } T32refwinProp_Loc1; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TrefwinProp_Loc |
| { UNSG32 u32[2]; |
| struct { |
| struct w32refwinProp_Loc; |
| struct w32refwinProp_Loc1; |
| }; |
| } TrefwinProp_Loc; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 refwinProp_drvrd(SIE_refwinProp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 refwinProp_drvwr(SIE_refwinProp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void refwinProp_reset(SIE_refwinProp *p); |
| SIGN32 refwinProp_cmp (SIE_refwinProp *p, SIE_refwinProp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define refwinProp_check(p,pie,pfx,hLOG) refwinProp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define refwinProp_print(p, pfx,hLOG) refwinProp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: refwinProp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE MEE64b (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 data_0i |
| /// %unsigned 32 data_1i |
| /// ### |
| /// * Any 64b data |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_MEE64b |
| #define h_MEE64b (){} |
| |
| #define BA_MEE64b_data_0i 0x0000 |
| #define B16MEE64b_data_0i 0x0000 |
| #define LSb32MEE64b_data_0i 0 |
| #define LSb16MEE64b_data_0i 0 |
| #define bMEE64b_data_0i 32 |
| #define MSK32MEE64b_data_0i 0xFFFFFFFF |
| |
| #define BA_MEE64b_data_1i 0x0004 |
| #define B16MEE64b_data_1i 0x0004 |
| #define LSb32MEE64b_data_1i 0 |
| #define LSb16MEE64b_data_1i 0 |
| #define bMEE64b_data_1i 32 |
| #define MSK32MEE64b_data_1i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_MEE64b { |
| /////////////////////////////////////////////////////////// |
| #define GET32MEE64b_data_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32MEE64b_data_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32MEE64b_data_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32MEE64b_data_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_1i : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_MEE64b; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 MEE64b_drvrd(SIE_MEE64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 MEE64b_drvwr(SIE_MEE64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void MEE64b_reset(SIE_MEE64b *p); |
| SIGN32 MEE64b_cmp (SIE_MEE64b *p, SIE_MEE64b *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define MEE64b_check(p,pie,pfx,hLOG) MEE64b_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define MEE64b_print(p, pfx,hLOG) MEE64b_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: MEE64b |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE VprSfLut (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 6 data0 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %signed 6 data1 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %signed 6 data2 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// %signed 6 data3 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 24b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_VprSfLut |
| #define h_VprSfLut (){} |
| |
| #define BA_VprSfLut_data0 0x0000 |
| #define B16VprSfLut_data0 0x0000 |
| #define LSb32VprSfLut_data0 0 |
| #define LSb16VprSfLut_data0 0 |
| #define bVprSfLut_data0 6 |
| #define MSK32VprSfLut_data0 0x0000003F |
| |
| #define BA_VprSfLut_data1 0x0001 |
| #define B16VprSfLut_data1 0x0000 |
| #define LSb32VprSfLut_data1 8 |
| #define LSb16VprSfLut_data1 8 |
| #define bVprSfLut_data1 6 |
| #define MSK32VprSfLut_data1 0x00003F00 |
| |
| #define BA_VprSfLut_data2 0x0002 |
| #define B16VprSfLut_data2 0x0002 |
| #define LSb32VprSfLut_data2 16 |
| #define LSb16VprSfLut_data2 0 |
| #define bVprSfLut_data2 6 |
| #define MSK32VprSfLut_data2 0x003F0000 |
| |
| #define BA_VprSfLut_data3 0x0003 |
| #define B16VprSfLut_data3 0x0002 |
| #define LSb32VprSfLut_data3 24 |
| #define LSb16VprSfLut_data3 8 |
| #define bVprSfLut_data3 6 |
| #define MSK32VprSfLut_data3 0x3F000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_VprSfLut { |
| /////////////////////////////////////////////////////////// |
| #define GET32VprSfLut_data0(r32) _BFGET_(r32, 5, 0) |
| #define SET32VprSfLut_data0(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16VprSfLut_data0(r16) _BFGET_(r16, 5, 0) |
| #define SET16VprSfLut_data0(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32VprSfLut_data1(r32) _BFGET_(r32,13, 8) |
| #define SET32VprSfLut_data1(r32,v) _BFSET_(r32,13, 8,v) |
| #define GET16VprSfLut_data1(r16) _BFGET_(r16,13, 8) |
| #define SET16VprSfLut_data1(r16,v) _BFSET_(r16,13, 8,v) |
| |
| #define GET32VprSfLut_data2(r32) _BFGET_(r32,21,16) |
| #define SET32VprSfLut_data2(r32,v) _BFSET_(r32,21,16,v) |
| #define GET16VprSfLut_data2(r16) _BFGET_(r16, 5, 0) |
| #define SET16VprSfLut_data2(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32VprSfLut_data3(r32) _BFGET_(r32,29,24) |
| #define SET32VprSfLut_data3(r32,v) _BFSET_(r32,29,24,v) |
| #define GET16VprSfLut_data3(r16) _BFGET_(r16,13, 8) |
| #define SET16VprSfLut_data3(r16,v) _BFSET_(r16,13, 8,v) |
| |
| UNSG32 s_data0 : 6; |
| UNSG32 RSVDx0_b6 : 2; |
| UNSG32 s_data1 : 6; |
| UNSG32 RSVDx0_b14 : 2; |
| UNSG32 s_data2 : 6; |
| UNSG32 RSVDx0_b22 : 2; |
| UNSG32 s_data3 : 6; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| } SIE_VprSfLut; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 VprSfLut_drvrd(SIE_VprSfLut *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 VprSfLut_drvwr(SIE_VprSfLut *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void VprSfLut_reset(SIE_VprSfLut *p); |
| SIGN32 VprSfLut_cmp (SIE_VprSfLut *p, SIE_VprSfLut *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define VprSfLut_check(p,pie,pfx,hLOG) VprSfLut_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define VprSfLut_print(p, pfx,hLOG) VprSfLut_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: VprSfLut |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE VprTfLut (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 data0 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 3 # Stuffing bits... |
| /// %unsigned 5 data1 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 3 # Stuffing bits... |
| /// %unsigned 5 data2 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 3 # Stuffing bits... |
| /// %unsigned 5 data3 |
| /// ### |
| /// * Data entry |
| /// ### |
| /// %% 3 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 20b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_VprTfLut |
| #define h_VprTfLut (){} |
| |
| #define BA_VprTfLut_data0 0x0000 |
| #define B16VprTfLut_data0 0x0000 |
| #define LSb32VprTfLut_data0 0 |
| #define LSb16VprTfLut_data0 0 |
| #define bVprTfLut_data0 5 |
| #define MSK32VprTfLut_data0 0x0000001F |
| |
| #define BA_VprTfLut_data1 0x0001 |
| #define B16VprTfLut_data1 0x0000 |
| #define LSb32VprTfLut_data1 8 |
| #define LSb16VprTfLut_data1 8 |
| #define bVprTfLut_data1 5 |
| #define MSK32VprTfLut_data1 0x00001F00 |
| |
| #define BA_VprTfLut_data2 0x0002 |
| #define B16VprTfLut_data2 0x0002 |
| #define LSb32VprTfLut_data2 16 |
| #define LSb16VprTfLut_data2 0 |
| #define bVprTfLut_data2 5 |
| #define MSK32VprTfLut_data2 0x001F0000 |
| |
| #define BA_VprTfLut_data3 0x0003 |
| #define B16VprTfLut_data3 0x0002 |
| #define LSb32VprTfLut_data3 24 |
| #define LSb16VprTfLut_data3 8 |
| #define bVprTfLut_data3 5 |
| #define MSK32VprTfLut_data3 0x1F000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_VprTfLut { |
| /////////////////////////////////////////////////////////// |
| #define GET32VprTfLut_data0(r32) _BFGET_(r32, 4, 0) |
| #define SET32VprTfLut_data0(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16VprTfLut_data0(r16) _BFGET_(r16, 4, 0) |
| #define SET16VprTfLut_data0(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32VprTfLut_data1(r32) _BFGET_(r32,12, 8) |
| #define SET32VprTfLut_data1(r32,v) _BFSET_(r32,12, 8,v) |
| #define GET16VprTfLut_data1(r16) _BFGET_(r16,12, 8) |
| #define SET16VprTfLut_data1(r16,v) _BFSET_(r16,12, 8,v) |
| |
| #define GET32VprTfLut_data2(r32) _BFGET_(r32,20,16) |
| #define SET32VprTfLut_data2(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16VprTfLut_data2(r16) _BFGET_(r16, 4, 0) |
| #define SET16VprTfLut_data2(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32VprTfLut_data3(r32) _BFGET_(r32,28,24) |
| #define SET32VprTfLut_data3(r32,v) _BFSET_(r32,28,24,v) |
| #define GET16VprTfLut_data3(r16) _BFGET_(r16,12, 8) |
| #define SET16VprTfLut_data3(r16,v) _BFSET_(r16,12, 8,v) |
| |
| UNSG32 u_data0 : 5; |
| UNSG32 RSVDx0_b5 : 3; |
| UNSG32 u_data1 : 5; |
| UNSG32 RSVDx0_b13 : 3; |
| UNSG32 u_data2 : 5; |
| UNSG32 RSVDx0_b21 : 3; |
| UNSG32 u_data3 : 5; |
| UNSG32 RSVDx0_b29 : 3; |
| /////////////////////////////////////////////////////////// |
| } SIE_VprTfLut; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 VprTfLut_drvrd(SIE_VprTfLut *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 VprTfLut_drvwr(SIE_VprTfLut *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void VprTfLut_reset(SIE_VprTfLut *p); |
| SIGN32 VprTfLut_cmp (SIE_VprTfLut *p, SIE_VprTfLut *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define VprTfLut_check(p,pie,pfx,hLOG) VprTfLut_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define VprTfLut_print(p, pfx,hLOG) VprTfLut_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: VprTfLut |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64MEE flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 RSVD |
| /// $MEE64b RSVD REG [17] |
| /// ### |
| /// * [1088: ] |
| /// ### |
| /// @ 0x00088 Loc (P) |
| /// %unsigned 12 rdADDR |
| /// ### |
| /// * Base address of current MB, in 128b (16-byte) unit (one DMEM entry = 128b) |
| /// ### |
| /// %unsigned 4 rdSTRIDE |
| /// ### |
| /// * Current MB stride size (in 128b DMEM entry) |
| /// ### |
| /// %unsigned 12 wrADDR |
| /// ### |
| /// * Base address of residual write-back in 128b unit (DMEM entry) |
| /// ### |
| /// %unsigned 4 wrSTRIDE |
| /// ### |
| /// * Residual write-back stride size (in 128b DMEM entry) |
| /// ### |
| /// # 0x0008C Loc1 |
| /// %unsigned 8 mvxMin |
| /// ### |
| /// * The top bound of the potential IME search area. No motion vector point above this point will be searched. |
| /// * (integer-pix precision) MV.X >= -mvxMin |
| /// ### |
| /// %unsigned 8 mvxMax |
| /// ### |
| /// * The bottom bound of the potential IME search area. No motion vector point below this point will be searched. |
| /// * (integer-pix precision) MV.X <= +mvxMax |
| /// ### |
| /// %unsigned 8 mvyMin |
| /// ### |
| /// * The left bound of the potential IME search area. No motion vector point to the left of this point will be searched. |
| /// * (integer-pix precision) MV.Y >= -mvyMin |
| /// ### |
| /// %unsigned 8 mvyMax |
| /// ### |
| /// * The right bound of the potential IME search area. No motion vector point to the right of this point will be searched. |
| /// * (integer-pix precision) MV.Y <= +mvyMax |
| /// ### |
| /// @ 0x00090 Param (P) |
| /// %unsigned 16 lambda |
| /// ### |
| /// * Fix point 8.8 for MVD lambda: |
| /// * SAD += |MVD| * lambda |
| /// ### |
| /// %unsigned 8 zeromvThresh |
| /// ### |
| /// * Additional favor to MV=0 |
| /// * SAD += (MV!=0) ? zeromvThresh : 0 |
| /// ### |
| /// %unsigned 8 zeromvdThresh |
| /// ### |
| /// * Additional favor to MVD=0 |
| /// * SAD += (MVD!=0) ? zeromvdThresh : 0 |
| /// ### |
| /// # 0x00094 Param1 |
| /// %unsigned 3 fractionMode |
| /// : h264qpix 0x0 |
| /// : mpeghalfpix 0x1 |
| /// : vc1bilinear 0x2 |
| /// : avshalfpix 0x3 |
| /// : vc1bicubic 0x4 |
| /// : vp8BicubicHalfPixel 0x5 |
| /// ### |
| /// * Fractional pixel interpolation method |
| /// ### |
| /// %unsigned 1 roundingCtrlH |
| /// ### |
| /// * Horizontal Rounding control bit |
| /// * for H264 & MPEG2 always 0 |
| /// * for MPEG4, vertical & horizontal are same |
| /// * for vc1 bilinear, vertical & horizontal are same |
| /// * for vc1 bicubic, vertical & horizontal are reversed |
| /// ### |
| /// %unsigned 1 roundingCtrlV |
| /// ### |
| /// * Vertical Rounding control bit. |
| /// * for H264 & MPEG2 always 0 |
| /// ### |
| /// %% 27 # Stuffing bits... |
| /// @ 0x00098 VprSFLut (P) |
| /// # 0x00098 SFLUT |
| /// $MEE64b SFLUT REG [4] |
| /// ### |
| /// * Lookup table for spatial filter |
| /// ### |
| /// @ 0x000B8 VprTFLut (P) |
| /// # 0x000B8 TFLUT |
| /// $MEE64b TFLUT REG [2] |
| /// ### |
| /// * Lookup table for temporal filter |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 200B, bits: 1600b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64MEE |
| #define h_RF64MEE (){} |
| |
| #define RA_RF64MEE_RSVD 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64MEE_Loc 0x0088 |
| |
| #define BA_RF64MEE_Loc_rdADDR 0x0088 |
| #define B16RF64MEE_Loc_rdADDR 0x0088 |
| #define LSb32RF64MEE_Loc_rdADDR 0 |
| #define LSb16RF64MEE_Loc_rdADDR 0 |
| #define bRF64MEE_Loc_rdADDR 12 |
| #define MSK32RF64MEE_Loc_rdADDR 0x00000FFF |
| |
| #define BA_RF64MEE_Loc_rdSTRIDE 0x0089 |
| #define B16RF64MEE_Loc_rdSTRIDE 0x0088 |
| #define LSb32RF64MEE_Loc_rdSTRIDE 12 |
| #define LSb16RF64MEE_Loc_rdSTRIDE 12 |
| #define bRF64MEE_Loc_rdSTRIDE 4 |
| #define MSK32RF64MEE_Loc_rdSTRIDE 0x0000F000 |
| |
| #define BA_RF64MEE_Loc_wrADDR 0x008A |
| #define B16RF64MEE_Loc_wrADDR 0x008A |
| #define LSb32RF64MEE_Loc_wrADDR 16 |
| #define LSb16RF64MEE_Loc_wrADDR 0 |
| #define bRF64MEE_Loc_wrADDR 12 |
| #define MSK32RF64MEE_Loc_wrADDR 0x0FFF0000 |
| |
| #define BA_RF64MEE_Loc_wrSTRIDE 0x008B |
| #define B16RF64MEE_Loc_wrSTRIDE 0x008A |
| #define LSb32RF64MEE_Loc_wrSTRIDE 28 |
| #define LSb16RF64MEE_Loc_wrSTRIDE 12 |
| #define bRF64MEE_Loc_wrSTRIDE 4 |
| #define MSK32RF64MEE_Loc_wrSTRIDE 0xF0000000 |
| |
| #define RA_RF64MEE_Loc1 0x008C |
| |
| #define BA_RF64MEE_Loc_mvxMin 0x008C |
| #define B16RF64MEE_Loc_mvxMin 0x008C |
| #define LSb32RF64MEE_Loc_mvxMin 0 |
| #define LSb16RF64MEE_Loc_mvxMin 0 |
| #define bRF64MEE_Loc_mvxMin 8 |
| #define MSK32RF64MEE_Loc_mvxMin 0x000000FF |
| |
| #define BA_RF64MEE_Loc_mvxMax 0x008D |
| #define B16RF64MEE_Loc_mvxMax 0x008C |
| #define LSb32RF64MEE_Loc_mvxMax 8 |
| #define LSb16RF64MEE_Loc_mvxMax 8 |
| #define bRF64MEE_Loc_mvxMax 8 |
| #define MSK32RF64MEE_Loc_mvxMax 0x0000FF00 |
| |
| #define BA_RF64MEE_Loc_mvyMin 0x008E |
| #define B16RF64MEE_Loc_mvyMin 0x008E |
| #define LSb32RF64MEE_Loc_mvyMin 16 |
| #define LSb16RF64MEE_Loc_mvyMin 0 |
| #define bRF64MEE_Loc_mvyMin 8 |
| #define MSK32RF64MEE_Loc_mvyMin 0x00FF0000 |
| |
| #define BA_RF64MEE_Loc_mvyMax 0x008F |
| #define B16RF64MEE_Loc_mvyMax 0x008E |
| #define LSb32RF64MEE_Loc_mvyMax 24 |
| #define LSb16RF64MEE_Loc_mvyMax 8 |
| #define bRF64MEE_Loc_mvyMax 8 |
| #define MSK32RF64MEE_Loc_mvyMax 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64MEE_Param 0x0090 |
| |
| #define BA_RF64MEE_Param_lambda 0x0090 |
| #define B16RF64MEE_Param_lambda 0x0090 |
| #define LSb32RF64MEE_Param_lambda 0 |
| #define LSb16RF64MEE_Param_lambda 0 |
| #define bRF64MEE_Param_lambda 16 |
| #define MSK32RF64MEE_Param_lambda 0x0000FFFF |
| |
| #define BA_RF64MEE_Param_zeromvThresh 0x0092 |
| #define B16RF64MEE_Param_zeromvThresh 0x0092 |
| #define LSb32RF64MEE_Param_zeromvThresh 16 |
| #define LSb16RF64MEE_Param_zeromvThresh 0 |
| #define bRF64MEE_Param_zeromvThresh 8 |
| #define MSK32RF64MEE_Param_zeromvThresh 0x00FF0000 |
| |
| #define BA_RF64MEE_Param_zeromvdThresh 0x0093 |
| #define B16RF64MEE_Param_zeromvdThresh 0x0092 |
| #define LSb32RF64MEE_Param_zeromvdThresh 24 |
| #define LSb16RF64MEE_Param_zeromvdThresh 8 |
| #define bRF64MEE_Param_zeromvdThresh 8 |
| #define MSK32RF64MEE_Param_zeromvdThresh 0xFF000000 |
| |
| #define RA_RF64MEE_Param1 0x0094 |
| |
| #define BA_RF64MEE_Param_fractionMode 0x0094 |
| #define B16RF64MEE_Param_fractionMode 0x0094 |
| #define LSb32RF64MEE_Param_fractionMode 0 |
| #define LSb16RF64MEE_Param_fractionMode 0 |
| #define bRF64MEE_Param_fractionMode 3 |
| #define MSK32RF64MEE_Param_fractionMode 0x00000007 |
| #define RF64MEE_Param_fractionMode_h264qpix 0x0 |
| #define RF64MEE_Param_fractionMode_mpeghalfpix 0x1 |
| #define RF64MEE_Param_fractionMode_vc1bilinear 0x2 |
| #define RF64MEE_Param_fractionMode_avshalfpix 0x3 |
| #define RF64MEE_Param_fractionMode_vc1bicubic 0x4 |
| #define RF64MEE_Param_fractionMode_vp8BicubicHalfPixel 0x5 |
| |
| #define BA_RF64MEE_Param_roundingCtrlH 0x0094 |
| #define B16RF64MEE_Param_roundingCtrlH 0x0094 |
| #define LSb32RF64MEE_Param_roundingCtrlH 3 |
| #define LSb16RF64MEE_Param_roundingCtrlH 3 |
| #define bRF64MEE_Param_roundingCtrlH 1 |
| #define MSK32RF64MEE_Param_roundingCtrlH 0x00000008 |
| |
| #define BA_RF64MEE_Param_roundingCtrlV 0x0094 |
| #define B16RF64MEE_Param_roundingCtrlV 0x0094 |
| #define LSb32RF64MEE_Param_roundingCtrlV 4 |
| #define LSb16RF64MEE_Param_roundingCtrlV 4 |
| #define bRF64MEE_Param_roundingCtrlV 1 |
| #define MSK32RF64MEE_Param_roundingCtrlV 0x00000010 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64MEE_VprSFLut 0x0098 |
| #define RA_RF64MEE_SFLUT 0x0098 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64MEE_VprTFLut 0x00B8 |
| #define RA_RF64MEE_TFLUT 0x00B8 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64MEE { |
| /////////////////////////////////////////////////////////// |
| SIE_MEE64b ie_RSVD[17]; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64MEE_Loc_rdADDR(r32) _BFGET_(r32,11, 0) |
| #define SET32RF64MEE_Loc_rdADDR(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16RF64MEE_Loc_rdADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64MEE_Loc_rdADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64MEE_Loc_rdSTRIDE(r32) _BFGET_(r32,15,12) |
| #define SET32RF64MEE_Loc_rdSTRIDE(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16RF64MEE_Loc_rdSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16RF64MEE_Loc_rdSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32RF64MEE_Loc_wrADDR(r32) _BFGET_(r32,27,16) |
| #define SET32RF64MEE_Loc_wrADDR(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16RF64MEE_Loc_wrADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16RF64MEE_Loc_wrADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32RF64MEE_Loc_wrSTRIDE(r32) _BFGET_(r32,31,28) |
| #define SET32RF64MEE_Loc_wrSTRIDE(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16RF64MEE_Loc_wrSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16RF64MEE_Loc_wrSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define w32RF64MEE_Loc {\ |
| UNSG32 uLoc_rdADDR : 12;\ |
| UNSG32 uLoc_rdSTRIDE : 4;\ |
| UNSG32 uLoc_wrADDR : 12;\ |
| UNSG32 uLoc_wrSTRIDE : 4;\ |
| } |
| union { UNSG32 u32RF64MEE_Loc; |
| struct w32RF64MEE_Loc; |
| }; |
| #define GET32RF64MEE_Loc_mvxMin(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64MEE_Loc_mvxMin(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64MEE_Loc_mvxMin(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MEE_Loc_mvxMin(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MEE_Loc_mvxMax(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64MEE_Loc_mvxMax(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64MEE_Loc_mvxMax(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MEE_Loc_mvxMax(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64MEE_Loc_mvyMin(r32) _BFGET_(r32,23,16) |
| #define SET32RF64MEE_Loc_mvyMin(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64MEE_Loc_mvyMin(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MEE_Loc_mvyMin(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MEE_Loc_mvyMax(r32) _BFGET_(r32,31,24) |
| #define SET32RF64MEE_Loc_mvyMax(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64MEE_Loc_mvyMax(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MEE_Loc_mvyMax(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64MEE_Loc1 {\ |
| UNSG32 uLoc_mvxMin : 8;\ |
| UNSG32 uLoc_mvxMax : 8;\ |
| UNSG32 uLoc_mvyMin : 8;\ |
| UNSG32 uLoc_mvyMax : 8;\ |
| } |
| union { UNSG32 u32RF64MEE_Loc1; |
| struct w32RF64MEE_Loc1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64MEE_Param_lambda(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64MEE_Param_lambda(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64MEE_Param_lambda(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64MEE_Param_lambda(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64MEE_Param_zeromvThresh(r32) _BFGET_(r32,23,16) |
| #define SET32RF64MEE_Param_zeromvThresh(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64MEE_Param_zeromvThresh(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MEE_Param_zeromvThresh(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MEE_Param_zeromvdThresh(r32) _BFGET_(r32,31,24) |
| #define SET32RF64MEE_Param_zeromvdThresh(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64MEE_Param_zeromvdThresh(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MEE_Param_zeromvdThresh(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32RF64MEE_Param {\ |
| UNSG32 uParam_lambda : 16;\ |
| UNSG32 uParam_zeromvThresh : 8;\ |
| UNSG32 uParam_zeromvdThresh : 8;\ |
| } |
| union { UNSG32 u32RF64MEE_Param; |
| struct w32RF64MEE_Param; |
| }; |
| #define GET32RF64MEE_Param_fractionMode(r32) _BFGET_(r32, 2, 0) |
| #define SET32RF64MEE_Param_fractionMode(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16RF64MEE_Param_fractionMode(r16) _BFGET_(r16, 2, 0) |
| #define SET16RF64MEE_Param_fractionMode(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32RF64MEE_Param_roundingCtrlH(r32) _BFGET_(r32, 3, 3) |
| #define SET32RF64MEE_Param_roundingCtrlH(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16RF64MEE_Param_roundingCtrlH(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64MEE_Param_roundingCtrlH(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64MEE_Param_roundingCtrlV(r32) _BFGET_(r32, 4, 4) |
| #define SET32RF64MEE_Param_roundingCtrlV(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16RF64MEE_Param_roundingCtrlV(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64MEE_Param_roundingCtrlV(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32RF64MEE_Param1 {\ |
| UNSG32 uParam_fractionMode : 3;\ |
| UNSG32 uParam_roundingCtrlH : 1;\ |
| UNSG32 uParam_roundingCtrlV : 1;\ |
| UNSG32 RSVDx94_b5 : 27;\ |
| } |
| union { UNSG32 u32RF64MEE_Param1; |
| struct w32RF64MEE_Param1; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_MEE64b ie_SFLUT[4]; |
| /////////////////////////////////////////////////////////// |
| SIE_MEE64b ie_TFLUT[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64MEE; |
| |
| typedef union T32RF64MEE_Loc |
| { UNSG32 u32; |
| struct w32RF64MEE_Loc; |
| } T32RF64MEE_Loc; |
| typedef union T32RF64MEE_Loc1 |
| { UNSG32 u32; |
| struct w32RF64MEE_Loc1; |
| } T32RF64MEE_Loc1; |
| typedef union T32RF64MEE_Param |
| { UNSG32 u32; |
| struct w32RF64MEE_Param; |
| } T32RF64MEE_Param; |
| typedef union T32RF64MEE_Param1 |
| { UNSG32 u32; |
| struct w32RF64MEE_Param1; |
| } T32RF64MEE_Param1; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TRF64MEE_Loc |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64MEE_Loc; |
| struct w32RF64MEE_Loc1; |
| }; |
| } TRF64MEE_Loc; |
| typedef union TRF64MEE_Param |
| { UNSG32 u32[2]; |
| struct { |
| struct w32RF64MEE_Param; |
| struct w32RF64MEE_Param1; |
| }; |
| } TRF64MEE_Param; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64MEE_drvrd(SIE_RF64MEE *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64MEE_drvwr(SIE_RF64MEE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64MEE_reset(SIE_RF64MEE *p); |
| SIGN32 RF64MEE_cmp (SIE_RF64MEE *p, SIE_RF64MEE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64MEE_check(p,pie,pfx,hLOG) RF64MEE_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64MEE_print(p, pfx,hLOG) RF64MEE_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64MEE |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME16 flat (4,4) |
| /// ### |
| /// * 16-bit MEE command format for SAD collection |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 CMD |
| /// : SAD 0x0 |
| /// ### |
| /// * SAD collection |
| /// * Generate and store the SADs for each valid MV point in the given search area. IME command. |
| /// ### |
| /// : IMD 0x1 |
| /// ### |
| /// * Integer-MV decision |
| /// * Parse through the stored SADs and determine the integer MV point with the lowest cost. IME command. |
| /// ### |
| /// : FRC 0x2 |
| /// ### |
| /// * Fraction refinement & compensation without write-back |
| /// * Perform the fractional pixel interpolations, collect SADs for each fract MV point, store winning cost and motion vector. FME command. |
| /// ### |
| /// : LDORI 0x3 |
| /// ### |
| /// * Load Original data |
| /// * FME command. |
| /// ### |
| /// : ISR 0x5 |
| /// ### |
| /// * indexed SAD return |
| /// * Return 4 SAD values from memory given an integer MV search point. |
| /// * IME command. |
| /// ### |
| /// : WBO 0x7 |
| /// ### |
| /// * Write back compensation result only. |
| /// * Generate and output the residual block data given the fractional motion vector. The partial predictor data would be stored in internal memory (all ½ pixel data). FRC or IC command must be run prior to this command. There will be no need to fetch any reference data for this command. |
| /// * FRC+WBO = FRCO |
| /// * FME command. |
| /// ### |
| /// : RWUI 0x8 |
| /// ### |
| /// * Update refwinProp used by the IMD thread. |
| /// * IME command. |
| /// ### |
| /// : RWUF 0x9 |
| /// ### |
| /// * Update refwinProp used by the FRC thread. |
| /// * FME command. |
| /// ### |
| /// : DMA 0xA |
| /// ### |
| /// * DMEM memory copy command. |
| /// * Copy one block of DMEM data |
| /// * FME command. |
| /// ### |
| /// : FRCOP 0xB |
| /// ### |
| /// * Fraction refinement & compensation with predictor output write-back |
| /// * Perform the FRC command plus output the predictor data to DMEM. |
| /// * FME command. |
| /// ### |
| /// : IC 0xC |
| /// ### |
| /// * Single-MV interpolation & compensation without write-back. |
| /// * Generate the predictor block given the fractional motion vector. Store the generated predictor block in internal buffer, no output to DMEM. |
| /// * FME command. |
| /// ### |
| /// : CC 0xE |
| /// ### |
| /// * Compensation and cost calculation without write-back output. |
| /// * Load source and predictor data, output SAD. No reference data loading. |
| /// * FME command. |
| /// ### |
| /// : WBOP 0xF |
| /// ### |
| /// * Write back predictor data only. |
| /// * Generate and output the predictor data given the fractional motion vector. The partial predictor data would be stored in memory (all ½ pixel data). FRC or IC command must be run prior to this command. There will be no need to fetch any reference data for this command. |
| /// * FME command. |
| /// ### |
| /// : GRADIENT 0x4 |
| /// ### |
| /// * Calculate 1st order & 2nd order gradient value |
| /// ### |
| /// : SF 0x6 |
| /// ### |
| /// * Spatial filter in VPR |
| /// ### |
| /// : TF 0xD |
| /// ### |
| /// * Temporal filter in VPR |
| /// ### |
| /// %unsigned 1 level |
| /// : MB 0x0 |
| /// : BLK8x8 0x1 |
| /// ### |
| /// * MB or 8x8-block level motion search |
| /// * Used by RWU, SAD and LDORI. |
| /// ### |
| /// %unsigned 2 BLK |
| /// ### |
| /// * For level=BLK8x8 only, 0~3 as index in MB, referenced in raster order. |
| /// * Used by RWU, SAD and LDORI. |
| /// ### |
| /// %unsigned 1 refSel |
| /// ### |
| /// * Reference window selection. Reference windows are stored in MEE internally. |
| /// * Used by RWU, SAD. |
| /// ### |
| /// %unsigned 4 RefineX |
| /// ### |
| /// * For SAD collection & RWU: |
| /// * Horizontal refine window size |
| /// * RefineX and RefineY are used by RWU & SAD. Must be same for SAD & RWU at same direction. |
| /// * -RefineX <= mvx-base.mvx <= RefineX |
| /// ### |
| /// %unsigned 4 RefineY |
| /// ### |
| /// * Vertical refine window size. Total refine window are constrained by SAD buffer size (512), which makes (2*RefineX+1)*(2*RefineY+1) <= 512 |
| /// * -RefineY <= mvy-base.mvy <= RefineY |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME16 |
| #define h_A64ME16 (){} |
| |
| #define BA_A64ME16_CMD 0x0000 |
| #define B16A64ME16_CMD 0x0000 |
| #define LSb32A64ME16_CMD 0 |
| #define LSb16A64ME16_CMD 0 |
| #define bA64ME16_CMD 4 |
| #define MSK32A64ME16_CMD 0x0000000F |
| #define A64ME16_CMD_SAD 0x0 |
| #define A64ME16_CMD_IMD 0x1 |
| #define A64ME16_CMD_FRC 0x2 |
| #define A64ME16_CMD_LDORI 0x3 |
| #define A64ME16_CMD_ISR 0x5 |
| #define A64ME16_CMD_WBO 0x7 |
| #define A64ME16_CMD_RWUI 0x8 |
| #define A64ME16_CMD_RWUF 0x9 |
| #define A64ME16_CMD_DMA 0xA |
| #define A64ME16_CMD_FRCOP 0xB |
| #define A64ME16_CMD_IC 0xC |
| #define A64ME16_CMD_CC 0xE |
| #define A64ME16_CMD_WBOP 0xF |
| #define A64ME16_CMD_GRADIENT 0x4 |
| #define A64ME16_CMD_SF 0x6 |
| #define A64ME16_CMD_TF 0xD |
| |
| #define BA_A64ME16_level 0x0000 |
| #define B16A64ME16_level 0x0000 |
| #define LSb32A64ME16_level 4 |
| #define LSb16A64ME16_level 4 |
| #define bA64ME16_level 1 |
| #define MSK32A64ME16_level 0x00000010 |
| #define A64ME16_level_MB 0x0 |
| #define A64ME16_level_BLK8x8 0x1 |
| |
| #define BA_A64ME16_BLK 0x0000 |
| #define B16A64ME16_BLK 0x0000 |
| #define LSb32A64ME16_BLK 5 |
| #define LSb16A64ME16_BLK 5 |
| #define bA64ME16_BLK 2 |
| #define MSK32A64ME16_BLK 0x00000060 |
| |
| #define BA_A64ME16_refSel 0x0000 |
| #define B16A64ME16_refSel 0x0000 |
| #define LSb32A64ME16_refSel 7 |
| #define LSb16A64ME16_refSel 7 |
| #define bA64ME16_refSel 1 |
| #define MSK32A64ME16_refSel 0x00000080 |
| |
| #define BA_A64ME16_RefineX 0x0001 |
| #define B16A64ME16_RefineX 0x0000 |
| #define LSb32A64ME16_RefineX 8 |
| #define LSb16A64ME16_RefineX 8 |
| #define bA64ME16_RefineX 4 |
| #define MSK32A64ME16_RefineX 0x00000F00 |
| |
| #define BA_A64ME16_RefineY 0x0001 |
| #define B16A64ME16_RefineY 0x0000 |
| #define LSb32A64ME16_RefineY 12 |
| #define LSb16A64ME16_RefineY 12 |
| #define bA64ME16_RefineY 4 |
| #define MSK32A64ME16_RefineY 0x0000F000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME16 { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME16_CMD(r32) _BFGET_(r32, 3, 0) |
| #define SET32A64ME16_CMD(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16A64ME16_CMD(r16) _BFGET_(r16, 3, 0) |
| #define SET16A64ME16_CMD(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32A64ME16_level(r32) _BFGET_(r32, 4, 4) |
| #define SET32A64ME16_level(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16A64ME16_level(r16) _BFGET_(r16, 4, 4) |
| #define SET16A64ME16_level(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32A64ME16_BLK(r32) _BFGET_(r32, 6, 5) |
| #define SET32A64ME16_BLK(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16A64ME16_BLK(r16) _BFGET_(r16, 6, 5) |
| #define SET16A64ME16_BLK(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32A64ME16_refSel(r32) _BFGET_(r32, 7, 7) |
| #define SET32A64ME16_refSel(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16A64ME16_refSel(r16) _BFGET_(r16, 7, 7) |
| #define SET16A64ME16_refSel(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32A64ME16_RefineX(r32) _BFGET_(r32,11, 8) |
| #define SET32A64ME16_RefineX(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16A64ME16_RefineX(r16) _BFGET_(r16,11, 8) |
| #define SET16A64ME16_RefineX(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32A64ME16_RefineY(r32) _BFGET_(r32,15,12) |
| #define SET32A64ME16_RefineY(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16A64ME16_RefineY(r16) _BFGET_(r16,15,12) |
| #define SET16A64ME16_RefineY(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_CMD : 4; |
| UNSG32 u_level : 1; |
| UNSG32 u_BLK : 2; |
| UNSG32 u_refSel : 1; |
| UNSG32 u_RefineX : 4; |
| UNSG32 u_RefineY : 4; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME16; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME16_drvrd(SIE_A64ME16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME16_drvwr(SIE_A64ME16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME16_reset(SIE_A64ME16 *p); |
| SIGN32 A64ME16_cmp (SIE_A64ME16 *p, SIE_A64ME16 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME16_check(p,pie,pfx,hLOG) A64ME16_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME16_print(p, pfx,hLOG) A64ME16_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME16 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME16D flat (4,4) |
| /// ### |
| /// * 16-bit MEE command format for commands other than SAD collection |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 CMD |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 1 level |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 2 BLK |
| /// ### |
| /// * For level=BLK8x8 only, 0~3 as index in MB, referenced in raster order. |
| /// ### |
| /// %unsigned 1 refSel |
| /// ### |
| /// * For all ME commands |
| /// * Reference window selection (in RF64MEE) |
| /// ### |
| /// %unsigned 2 Partition |
| /// ### |
| /// * Partition shape within MB or 8x8-block, used in conjunction with the IDX field to determine which block in being processed. |
| /// ### |
| /// : 1mv 0x0 |
| /// ### |
| /// * 16x16 or 8x8 |
| /// ### |
| /// : 2mvLR 0x1 |
| /// ### |
| /// * 8x16 or 4x8 |
| /// ### |
| /// : 2mvTB 0x2 |
| /// ### |
| /// * 16x8 or 8x4 |
| /// ### |
| /// : 4mv 0x3 |
| /// ### |
| /// * 8x8 or 4x4 |
| /// ### |
| /// %unsigned 2 IDX |
| /// ### |
| /// * Partition index within MB or 8x8-block: |
| /// * 1mv: 0 |
| /// * 2mvLR/2mvTB: 0/1 |
| /// * 4mv: 0/1/2/3 |
| /// * Used in conjunction with the Partition field to determine which block is being processed. |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME16D |
| #define h_A64ME16D (){} |
| |
| #define BA_A64ME16D_CMD 0x0000 |
| #define B16A64ME16D_CMD 0x0000 |
| #define LSb32A64ME16D_CMD 0 |
| #define LSb16A64ME16D_CMD 0 |
| #define bA64ME16D_CMD 4 |
| #define MSK32A64ME16D_CMD 0x0000000F |
| |
| #define BA_A64ME16D_level 0x0000 |
| #define B16A64ME16D_level 0x0000 |
| #define LSb32A64ME16D_level 4 |
| #define LSb16A64ME16D_level 4 |
| #define bA64ME16D_level 1 |
| #define MSK32A64ME16D_level 0x00000010 |
| |
| #define BA_A64ME16D_BLK 0x0000 |
| #define B16A64ME16D_BLK 0x0000 |
| #define LSb32A64ME16D_BLK 5 |
| #define LSb16A64ME16D_BLK 5 |
| #define bA64ME16D_BLK 2 |
| #define MSK32A64ME16D_BLK 0x00000060 |
| |
| #define BA_A64ME16D_refSel 0x0000 |
| #define B16A64ME16D_refSel 0x0000 |
| #define LSb32A64ME16D_refSel 7 |
| #define LSb16A64ME16D_refSel 7 |
| #define bA64ME16D_refSel 1 |
| #define MSK32A64ME16D_refSel 0x00000080 |
| |
| #define BA_A64ME16D_Partition 0x0001 |
| #define B16A64ME16D_Partition 0x0000 |
| #define LSb32A64ME16D_Partition 8 |
| #define LSb16A64ME16D_Partition 8 |
| #define bA64ME16D_Partition 2 |
| #define MSK32A64ME16D_Partition 0x00000300 |
| #define A64ME16D_Partition_1mv 0x0 |
| #define A64ME16D_Partition_2mvLR 0x1 |
| #define A64ME16D_Partition_2mvTB 0x2 |
| #define A64ME16D_Partition_4mv 0x3 |
| |
| #define BA_A64ME16D_IDX 0x0001 |
| #define B16A64ME16D_IDX 0x0000 |
| #define LSb32A64ME16D_IDX 10 |
| #define LSb16A64ME16D_IDX 10 |
| #define bA64ME16D_IDX 2 |
| #define MSK32A64ME16D_IDX 0x00000C00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME16D { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME16D_CMD(r32) _BFGET_(r32, 3, 0) |
| #define SET32A64ME16D_CMD(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16A64ME16D_CMD(r16) _BFGET_(r16, 3, 0) |
| #define SET16A64ME16D_CMD(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32A64ME16D_level(r32) _BFGET_(r32, 4, 4) |
| #define SET32A64ME16D_level(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16A64ME16D_level(r16) _BFGET_(r16, 4, 4) |
| #define SET16A64ME16D_level(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32A64ME16D_BLK(r32) _BFGET_(r32, 6, 5) |
| #define SET32A64ME16D_BLK(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16A64ME16D_BLK(r16) _BFGET_(r16, 6, 5) |
| #define SET16A64ME16D_BLK(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32A64ME16D_refSel(r32) _BFGET_(r32, 7, 7) |
| #define SET32A64ME16D_refSel(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16A64ME16D_refSel(r16) _BFGET_(r16, 7, 7) |
| #define SET16A64ME16D_refSel(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32A64ME16D_Partition(r32) _BFGET_(r32, 9, 8) |
| #define SET32A64ME16D_Partition(r32,v) _BFSET_(r32, 9, 8,v) |
| #define GET16A64ME16D_Partition(r16) _BFGET_(r16, 9, 8) |
| #define SET16A64ME16D_Partition(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32A64ME16D_IDX(r32) _BFGET_(r32,11,10) |
| #define SET32A64ME16D_IDX(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16A64ME16D_IDX(r16) _BFGET_(r16,11,10) |
| #define SET16A64ME16D_IDX(r16,v) _BFSET_(r16,11,10,v) |
| |
| UNSG32 u_CMD : 4; |
| UNSG32 u_level : 1; |
| UNSG32 u_BLK : 2; |
| UNSG32 u_refSel : 1; |
| UNSG32 u_Partition : 2; |
| UNSG32 u_IDX : 2; |
| UNSG32 RSVDx0_b12 : 4; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME16D; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME16D_drvrd(SIE_A64ME16D *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME16D_drvwr(SIE_A64ME16D *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME16D_reset(SIE_A64ME16D *p); |
| SIGN32 A64ME16D_cmp (SIE_A64ME16D *p, SIE_A64ME16D *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME16D_check(p,pie,pfx,hLOG) A64ME16D_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME16D_print(p, pfx,hLOG) A64ME16D_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME16D |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME16VPR flat (4,4) |
| /// ### |
| /// * 16-bit MEE command format for commands other than SAD collection |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 CMD |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 1 level |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 2 BLK |
| /// ### |
| /// * For level=BLK8x8 only, 0~3 as index in MB, referenced in raster order. |
| /// ### |
| /// %unsigned 1 refSel |
| /// ### |
| /// * For all ME commands |
| /// * Reference window selection (in RF64MEE) |
| /// ### |
| /// %unsigned 8 gradientThresh |
| /// ### |
| /// * h, when CMD is GRADIENT |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME16VPR |
| #define h_A64ME16VPR (){} |
| |
| #define BA_A64ME16VPR_CMD 0x0000 |
| #define B16A64ME16VPR_CMD 0x0000 |
| #define LSb32A64ME16VPR_CMD 0 |
| #define LSb16A64ME16VPR_CMD 0 |
| #define bA64ME16VPR_CMD 4 |
| #define MSK32A64ME16VPR_CMD 0x0000000F |
| |
| #define BA_A64ME16VPR_level 0x0000 |
| #define B16A64ME16VPR_level 0x0000 |
| #define LSb32A64ME16VPR_level 4 |
| #define LSb16A64ME16VPR_level 4 |
| #define bA64ME16VPR_level 1 |
| #define MSK32A64ME16VPR_level 0x00000010 |
| |
| #define BA_A64ME16VPR_BLK 0x0000 |
| #define B16A64ME16VPR_BLK 0x0000 |
| #define LSb32A64ME16VPR_BLK 5 |
| #define LSb16A64ME16VPR_BLK 5 |
| #define bA64ME16VPR_BLK 2 |
| #define MSK32A64ME16VPR_BLK 0x00000060 |
| |
| #define BA_A64ME16VPR_refSel 0x0000 |
| #define B16A64ME16VPR_refSel 0x0000 |
| #define LSb32A64ME16VPR_refSel 7 |
| #define LSb16A64ME16VPR_refSel 7 |
| #define bA64ME16VPR_refSel 1 |
| #define MSK32A64ME16VPR_refSel 0x00000080 |
| |
| #define BA_A64ME16VPR_gradientThresh 0x0001 |
| #define B16A64ME16VPR_gradientThresh 0x0000 |
| #define LSb32A64ME16VPR_gradientThresh 8 |
| #define LSb16A64ME16VPR_gradientThresh 8 |
| #define bA64ME16VPR_gradientThresh 8 |
| #define MSK32A64ME16VPR_gradientThresh 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME16VPR { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME16VPR_CMD(r32) _BFGET_(r32, 3, 0) |
| #define SET32A64ME16VPR_CMD(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16A64ME16VPR_CMD(r16) _BFGET_(r16, 3, 0) |
| #define SET16A64ME16VPR_CMD(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32A64ME16VPR_level(r32) _BFGET_(r32, 4, 4) |
| #define SET32A64ME16VPR_level(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16A64ME16VPR_level(r16) _BFGET_(r16, 4, 4) |
| #define SET16A64ME16VPR_level(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32A64ME16VPR_BLK(r32) _BFGET_(r32, 6, 5) |
| #define SET32A64ME16VPR_BLK(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16A64ME16VPR_BLK(r16) _BFGET_(r16, 6, 5) |
| #define SET16A64ME16VPR_BLK(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32A64ME16VPR_refSel(r32) _BFGET_(r32, 7, 7) |
| #define SET32A64ME16VPR_refSel(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16A64ME16VPR_refSel(r16) _BFGET_(r16, 7, 7) |
| #define SET16A64ME16VPR_refSel(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32A64ME16VPR_gradientThresh(r32) _BFGET_(r32,15, 8) |
| #define SET32A64ME16VPR_gradientThresh(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16A64ME16VPR_gradientThresh(r16) _BFGET_(r16,15, 8) |
| #define SET16A64ME16VPR_gradientThresh(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_CMD : 4; |
| UNSG32 u_level : 1; |
| UNSG32 u_BLK : 2; |
| UNSG32 u_refSel : 1; |
| UNSG32 u_gradientThresh : 8; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME16VPR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME16VPR_drvrd(SIE_A64ME16VPR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME16VPR_drvwr(SIE_A64ME16VPR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME16VPR_reset(SIE_A64ME16VPR *p); |
| SIGN32 A64ME16VPR_cmp (SIE_A64ME16VPR *p, SIE_A64ME16VPR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME16VPR_check(p,pie,pfx,hLOG) A64ME16VPR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME16VPR_print(p, pfx,hLOG) A64ME16VPR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME16VPR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME16VPRD flat (4,4) |
| /// ### |
| /// * 16-bit MEE command format for commands other than SAD collection |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 CMD |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 1 level |
| /// ### |
| /// * Use defined values in A64ME16 |
| /// ### |
| /// %unsigned 2 BLK |
| /// ### |
| /// * For level=BLK8x8 only, 0~3 as index in MB, referenced in raster order. |
| /// ### |
| /// %unsigned 1 refSel |
| /// ### |
| /// * For all ME commands |
| /// * Reference window selection (in RF64MEE) |
| /// ### |
| /// %unsigned 4 tfStrength |
| /// ### |
| /// * For temporal filter, every bit stands for the filter strength of one corner. |
| /// ### |
| /// %% 20 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME16VPRD |
| #define h_A64ME16VPRD (){} |
| |
| #define BA_A64ME16VPRD_CMD 0x0000 |
| #define B16A64ME16VPRD_CMD 0x0000 |
| #define LSb32A64ME16VPRD_CMD 0 |
| #define LSb16A64ME16VPRD_CMD 0 |
| #define bA64ME16VPRD_CMD 4 |
| #define MSK32A64ME16VPRD_CMD 0x0000000F |
| |
| #define BA_A64ME16VPRD_level 0x0000 |
| #define B16A64ME16VPRD_level 0x0000 |
| #define LSb32A64ME16VPRD_level 4 |
| #define LSb16A64ME16VPRD_level 4 |
| #define bA64ME16VPRD_level 1 |
| #define MSK32A64ME16VPRD_level 0x00000010 |
| |
| #define BA_A64ME16VPRD_BLK 0x0000 |
| #define B16A64ME16VPRD_BLK 0x0000 |
| #define LSb32A64ME16VPRD_BLK 5 |
| #define LSb16A64ME16VPRD_BLK 5 |
| #define bA64ME16VPRD_BLK 2 |
| #define MSK32A64ME16VPRD_BLK 0x00000060 |
| |
| #define BA_A64ME16VPRD_refSel 0x0000 |
| #define B16A64ME16VPRD_refSel 0x0000 |
| #define LSb32A64ME16VPRD_refSel 7 |
| #define LSb16A64ME16VPRD_refSel 7 |
| #define bA64ME16VPRD_refSel 1 |
| #define MSK32A64ME16VPRD_refSel 0x00000080 |
| |
| #define BA_A64ME16VPRD_tfStrength 0x0001 |
| #define B16A64ME16VPRD_tfStrength 0x0000 |
| #define LSb32A64ME16VPRD_tfStrength 8 |
| #define LSb16A64ME16VPRD_tfStrength 8 |
| #define bA64ME16VPRD_tfStrength 4 |
| #define MSK32A64ME16VPRD_tfStrength 0x00000F00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME16VPRD { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME16VPRD_CMD(r32) _BFGET_(r32, 3, 0) |
| #define SET32A64ME16VPRD_CMD(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16A64ME16VPRD_CMD(r16) _BFGET_(r16, 3, 0) |
| #define SET16A64ME16VPRD_CMD(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32A64ME16VPRD_level(r32) _BFGET_(r32, 4, 4) |
| #define SET32A64ME16VPRD_level(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16A64ME16VPRD_level(r16) _BFGET_(r16, 4, 4) |
| #define SET16A64ME16VPRD_level(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32A64ME16VPRD_BLK(r32) _BFGET_(r32, 6, 5) |
| #define SET32A64ME16VPRD_BLK(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16A64ME16VPRD_BLK(r16) _BFGET_(r16, 6, 5) |
| #define SET16A64ME16VPRD_BLK(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32A64ME16VPRD_refSel(r32) _BFGET_(r32, 7, 7) |
| #define SET32A64ME16VPRD_refSel(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16A64ME16VPRD_refSel(r16) _BFGET_(r16, 7, 7) |
| #define SET16A64ME16VPRD_refSel(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32A64ME16VPRD_tfStrength(r32) _BFGET_(r32,11, 8) |
| #define SET32A64ME16VPRD_tfStrength(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16A64ME16VPRD_tfStrength(r16) _BFGET_(r16,11, 8) |
| #define SET16A64ME16VPRD_tfStrength(r16,v) _BFSET_(r16,11, 8,v) |
| |
| UNSG32 u_CMD : 4; |
| UNSG32 u_level : 1; |
| UNSG32 u_BLK : 2; |
| UNSG32 u_refSel : 1; |
| UNSG32 u_tfStrength : 4; |
| UNSG32 RSVDx0_b12 : 20; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME16VPRD; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME16VPRD_drvrd(SIE_A64ME16VPRD *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME16VPRD_drvwr(SIE_A64ME16VPRD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME16VPRD_reset(SIE_A64ME16VPRD *p); |
| SIGN32 A64ME16VPRD_cmp (SIE_A64ME16VPRD *p, SIE_A64ME16VPRD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME16VPRD_check(p,pie,pfx,hLOG) A64ME16VPRD_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME16VPRD_print(p, pfx,hLOG) A64ME16VPRD_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME16VPRD |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME64 flat (8,2) |
| /// ### |
| /// * 64-bit MEE parameter format for all commands other than CCO |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 16 pmvx |
| /// ### |
| /// * For SAD, FRC, or FRCO: |
| /// * PMV.X in quarter-pix precision, used for MV cost calculation; unrelated to search/refinement range |
| /// * For ICO: |
| /// * Given MV input for compensation |
| /// * For TF: |
| /// * Given MV to generate predictor, lowest two bit should be zero. |
| /// * For ISR: |
| /// * signed refineX value |
| /// ### |
| /// %signed 16 pmvy |
| /// ### |
| /// * For SAD, FRC, or FRCO: |
| /// * PMV.Y in quarter-pix precision, used for MV cost calculation; unrelated to search/refinement range |
| /// * For ICO |
| /// * Given MV input for compensation |
| /// * For TF: |
| /// * Given MV to generate predictor, lowest two bit should be zero. |
| /// * For ISR: |
| /// * signed refineY value |
| /// ### |
| /// %signed 8 mvxBase |
| /// ### |
| /// * For IMD, FRC, or FRCO: |
| /// * Base MV.X to start refinement, in pixel-precision (-128 ~ 127). This is the best integer MV candidate so far; how it's determined is outside MEE's knowledge. |
| /// ### |
| /// %signed 8 mvyBase |
| /// ### |
| /// * For IMD, FRC, or FRCO: |
| /// * Base MV.Y to start refinement, in pixel-precision (-128 ~ 127). This is the best integer MV candidate so far; how it's determined is outside MEE's knowledge |
| /// ### |
| /// %unsigned 12 wrADDR |
| /// ### |
| /// * For FRCOP, WBOP, SF and TF: |
| /// * Base address of predictor write-back (in 128b DMEM entry). This field will be used from TP530 |
| /// ### |
| /// %unsigned 4 wrSTRIDE |
| /// ### |
| /// * For FRCOP, WBOP, SF and TF: |
| /// * Predictor write-back stride size (in 128b DMEM entry). This field will be used from TP530 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME64 |
| #define h_A64ME64 (){} |
| |
| #define BA_A64ME64_pmvx 0x0000 |
| #define B16A64ME64_pmvx 0x0000 |
| #define LSb32A64ME64_pmvx 0 |
| #define LSb16A64ME64_pmvx 0 |
| #define bA64ME64_pmvx 16 |
| #define MSK32A64ME64_pmvx 0x0000FFFF |
| |
| #define BA_A64ME64_pmvy 0x0002 |
| #define B16A64ME64_pmvy 0x0002 |
| #define LSb32A64ME64_pmvy 16 |
| #define LSb16A64ME64_pmvy 0 |
| #define bA64ME64_pmvy 16 |
| #define MSK32A64ME64_pmvy 0xFFFF0000 |
| |
| #define BA_A64ME64_mvxBase 0x0004 |
| #define B16A64ME64_mvxBase 0x0004 |
| #define LSb32A64ME64_mvxBase 0 |
| #define LSb16A64ME64_mvxBase 0 |
| #define bA64ME64_mvxBase 8 |
| #define MSK32A64ME64_mvxBase 0x000000FF |
| |
| #define BA_A64ME64_mvyBase 0x0005 |
| #define B16A64ME64_mvyBase 0x0004 |
| #define LSb32A64ME64_mvyBase 8 |
| #define LSb16A64ME64_mvyBase 8 |
| #define bA64ME64_mvyBase 8 |
| #define MSK32A64ME64_mvyBase 0x0000FF00 |
| |
| #define BA_A64ME64_wrADDR 0x0006 |
| #define B16A64ME64_wrADDR 0x0006 |
| #define LSb32A64ME64_wrADDR 16 |
| #define LSb16A64ME64_wrADDR 0 |
| #define bA64ME64_wrADDR 12 |
| #define MSK32A64ME64_wrADDR 0x0FFF0000 |
| |
| #define BA_A64ME64_wrSTRIDE 0x0007 |
| #define B16A64ME64_wrSTRIDE 0x0006 |
| #define LSb32A64ME64_wrSTRIDE 28 |
| #define LSb16A64ME64_wrSTRIDE 12 |
| #define bA64ME64_wrSTRIDE 4 |
| #define MSK32A64ME64_wrSTRIDE 0xF0000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME64 { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME64_pmvx(r32) _BFGET_(r32,15, 0) |
| #define SET32A64ME64_pmvx(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64ME64_pmvx(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ME64_pmvx(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64ME64_pmvy(r32) _BFGET_(r32,31,16) |
| #define SET32A64ME64_pmvy(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64ME64_pmvy(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ME64_pmvy(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 s_pmvx : 16; |
| UNSG32 s_pmvy : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32A64ME64_mvxBase(r32) _BFGET_(r32, 7, 0) |
| #define SET32A64ME64_mvxBase(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16A64ME64_mvxBase(r16) _BFGET_(r16, 7, 0) |
| #define SET16A64ME64_mvxBase(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32A64ME64_mvyBase(r32) _BFGET_(r32,15, 8) |
| #define SET32A64ME64_mvyBase(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16A64ME64_mvyBase(r16) _BFGET_(r16,15, 8) |
| #define SET16A64ME64_mvyBase(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32A64ME64_wrADDR(r32) _BFGET_(r32,27,16) |
| #define SET32A64ME64_wrADDR(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16A64ME64_wrADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16A64ME64_wrADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32A64ME64_wrSTRIDE(r32) _BFGET_(r32,31,28) |
| #define SET32A64ME64_wrSTRIDE(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16A64ME64_wrSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16A64ME64_wrSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 s_mvxBase : 8; |
| UNSG32 s_mvyBase : 8; |
| UNSG32 u_wrADDR : 12; |
| UNSG32 u_wrSTRIDE : 4; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME64; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME64_drvrd(SIE_A64ME64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME64_drvwr(SIE_A64ME64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME64_reset(SIE_A64ME64 *p); |
| SIGN32 A64ME64_cmp (SIE_A64ME64 *p, SIE_A64ME64 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME64_check(p,pie,pfx,hLOG) A64ME64_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME64_print(p, pfx,hLOG) A64ME64_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME64 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME64D flat (8,2) |
| /// ### |
| /// * 64-bit MEE parameter format for CCO command |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 12 prdADDR |
| /// ### |
| /// * DMEM read address for predictor, in128b DMEM entry |
| /// ### |
| /// %unsigned 4 prdSTRIDE |
| /// ### |
| /// * DMEM read address for predictor, in128b DMEM entry |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # Stuffing bytes... |
| /// %% 32 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME64D |
| #define h_A64ME64D (){} |
| |
| #define BA_A64ME64D_prdADDR 0x0000 |
| #define B16A64ME64D_prdADDR 0x0000 |
| #define LSb32A64ME64D_prdADDR 0 |
| #define LSb16A64ME64D_prdADDR 0 |
| #define bA64ME64D_prdADDR 12 |
| #define MSK32A64ME64D_prdADDR 0x00000FFF |
| |
| #define BA_A64ME64D_prdSTRIDE 0x0001 |
| #define B16A64ME64D_prdSTRIDE 0x0000 |
| #define LSb32A64ME64D_prdSTRIDE 12 |
| #define LSb16A64ME64D_prdSTRIDE 12 |
| #define bA64ME64D_prdSTRIDE 4 |
| #define MSK32A64ME64D_prdSTRIDE 0x0000F000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME64D { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME64D_prdADDR(r32) _BFGET_(r32,11, 0) |
| #define SET32A64ME64D_prdADDR(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16A64ME64D_prdADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16A64ME64D_prdADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32A64ME64D_prdSTRIDE(r32) _BFGET_(r32,15,12) |
| #define SET32A64ME64D_prdSTRIDE(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16A64ME64D_prdSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16A64ME64D_prdSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_prdADDR : 12; |
| UNSG32 u_prdSTRIDE : 4; |
| UNSG32 RSVDx0_b16 : 16; |
| UNSG8 RSVDx4 [4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME64D; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME64D_drvrd(SIE_A64ME64D *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME64D_drvwr(SIE_A64ME64D *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME64D_reset(SIE_A64ME64D *p); |
| SIGN32 A64ME64D_cmp (SIE_A64ME64D *p, SIE_A64ME64D *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME64D_check(p,pie,pfx,hLOG) A64ME64D_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME64D_print(p, pfx,hLOG) A64ME64D_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME64D |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ME64DMA flat (8,2) |
| /// ### |
| /// * 64-bit MEE parameter format for CCO command |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 12 srcADDR |
| /// ### |
| /// * DMEM source address for DMA, in128b DMEM entry |
| /// ### |
| /// %unsigned 4 srcSTRIDE |
| /// ### |
| /// * DMEM source address for DMA, in128b DMEM entry |
| /// ### |
| /// %unsigned 12 dstADDR |
| /// ### |
| /// * DMEM destination address for DMA, in128b DMEM entry |
| /// ### |
| /// %unsigned 4 dstSTRIDE |
| /// ### |
| /// * DMEM destination address for DMA, in128b DMEM entry |
| /// ### |
| /// %unsigned 16 xSIZE |
| /// ### |
| /// * Number of 4x4 blocks to copy in X direction. Maximum value is 4. |
| /// ### |
| /// %unsigned 16 ySIZE |
| /// ### |
| /// * rNumber of 4x4 blocks to copy in Y direction. Maximum value is 4. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ME64DMA |
| #define h_A64ME64DMA (){} |
| |
| #define BA_A64ME64DMA_srcADDR 0x0000 |
| #define B16A64ME64DMA_srcADDR 0x0000 |
| #define LSb32A64ME64DMA_srcADDR 0 |
| #define LSb16A64ME64DMA_srcADDR 0 |
| #define bA64ME64DMA_srcADDR 12 |
| #define MSK32A64ME64DMA_srcADDR 0x00000FFF |
| |
| #define BA_A64ME64DMA_srcSTRIDE 0x0001 |
| #define B16A64ME64DMA_srcSTRIDE 0x0000 |
| #define LSb32A64ME64DMA_srcSTRIDE 12 |
| #define LSb16A64ME64DMA_srcSTRIDE 12 |
| #define bA64ME64DMA_srcSTRIDE 4 |
| #define MSK32A64ME64DMA_srcSTRIDE 0x0000F000 |
| |
| #define BA_A64ME64DMA_dstADDR 0x0002 |
| #define B16A64ME64DMA_dstADDR 0x0002 |
| #define LSb32A64ME64DMA_dstADDR 16 |
| #define LSb16A64ME64DMA_dstADDR 0 |
| #define bA64ME64DMA_dstADDR 12 |
| #define MSK32A64ME64DMA_dstADDR 0x0FFF0000 |
| |
| #define BA_A64ME64DMA_dstSTRIDE 0x0003 |
| #define B16A64ME64DMA_dstSTRIDE 0x0002 |
| #define LSb32A64ME64DMA_dstSTRIDE 28 |
| #define LSb16A64ME64DMA_dstSTRIDE 12 |
| #define bA64ME64DMA_dstSTRIDE 4 |
| #define MSK32A64ME64DMA_dstSTRIDE 0xF0000000 |
| |
| #define BA_A64ME64DMA_xSIZE 0x0004 |
| #define B16A64ME64DMA_xSIZE 0x0004 |
| #define LSb32A64ME64DMA_xSIZE 0 |
| #define LSb16A64ME64DMA_xSIZE 0 |
| #define bA64ME64DMA_xSIZE 16 |
| #define MSK32A64ME64DMA_xSIZE 0x0000FFFF |
| |
| #define BA_A64ME64DMA_ySIZE 0x0006 |
| #define B16A64ME64DMA_ySIZE 0x0006 |
| #define LSb32A64ME64DMA_ySIZE 16 |
| #define LSb16A64ME64DMA_ySIZE 0 |
| #define bA64ME64DMA_ySIZE 16 |
| #define MSK32A64ME64DMA_ySIZE 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ME64DMA { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ME64DMA_srcADDR(r32) _BFGET_(r32,11, 0) |
| #define SET32A64ME64DMA_srcADDR(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16A64ME64DMA_srcADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16A64ME64DMA_srcADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32A64ME64DMA_srcSTRIDE(r32) _BFGET_(r32,15,12) |
| #define SET32A64ME64DMA_srcSTRIDE(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16A64ME64DMA_srcSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16A64ME64DMA_srcSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32A64ME64DMA_dstADDR(r32) _BFGET_(r32,27,16) |
| #define SET32A64ME64DMA_dstADDR(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16A64ME64DMA_dstADDR(r16) _BFGET_(r16,11, 0) |
| #define SET16A64ME64DMA_dstADDR(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32A64ME64DMA_dstSTRIDE(r32) _BFGET_(r32,31,28) |
| #define SET32A64ME64DMA_dstSTRIDE(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16A64ME64DMA_dstSTRIDE(r16) _BFGET_(r16,15,12) |
| #define SET16A64ME64DMA_dstSTRIDE(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_srcADDR : 12; |
| UNSG32 u_srcSTRIDE : 4; |
| UNSG32 u_dstADDR : 12; |
| UNSG32 u_dstSTRIDE : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32A64ME64DMA_xSIZE(r32) _BFGET_(r32,15, 0) |
| #define SET32A64ME64DMA_xSIZE(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64ME64DMA_xSIZE(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ME64DMA_xSIZE(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64ME64DMA_ySIZE(r32) _BFGET_(r32,31,16) |
| #define SET32A64ME64DMA_ySIZE(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64ME64DMA_ySIZE(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ME64DMA_ySIZE(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_xSIZE : 16; |
| UNSG32 u_ySIZE : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ME64DMA; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ME64DMA_drvrd(SIE_A64ME64DMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ME64DMA_drvwr(SIE_A64ME64DMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ME64DMA_reset(SIE_A64ME64DMA *p); |
| SIGN32 A64ME64DMA_cmp (SIE_A64ME64DMA *p, SIE_A64ME64DMA *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ME64DMA_check(p,pie,pfx,hLOG) A64ME64DMA_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ME64DMA_print(p, pfx,hLOG) A64ME64DMA_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ME64DMA |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64MERTN flat (8,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 16 mvx |
| /// ### |
| /// * Return MV.X in quarter-pix precision |
| /// ### |
| /// %signed 16 mvy |
| /// ### |
| /// * Return MV.Y in quarter-pix precision |
| /// ### |
| /// %unsigned 16 sad |
| /// ### |
| /// * SAD corresponding the cost. Used after TP530 |
| /// ### |
| /// %unsigned 16 cost |
| /// ### |
| /// * = SAD + lambda * MVD |
| /// * + (MVD!=0 ? zero_mvd_thresh : 0) |
| /// * + (MV!=0 ? zero_mv_thresh : 0) |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64MERTN |
| #define h_A64MERTN (){} |
| |
| #define BA_A64MERTN_mvx 0x0000 |
| #define B16A64MERTN_mvx 0x0000 |
| #define LSb32A64MERTN_mvx 0 |
| #define LSb16A64MERTN_mvx 0 |
| #define bA64MERTN_mvx 16 |
| #define MSK32A64MERTN_mvx 0x0000FFFF |
| |
| #define BA_A64MERTN_mvy 0x0002 |
| #define B16A64MERTN_mvy 0x0002 |
| #define LSb32A64MERTN_mvy 16 |
| #define LSb16A64MERTN_mvy 0 |
| #define bA64MERTN_mvy 16 |
| #define MSK32A64MERTN_mvy 0xFFFF0000 |
| |
| #define BA_A64MERTN_sad 0x0004 |
| #define B16A64MERTN_sad 0x0004 |
| #define LSb32A64MERTN_sad 0 |
| #define LSb16A64MERTN_sad 0 |
| #define bA64MERTN_sad 16 |
| #define MSK32A64MERTN_sad 0x0000FFFF |
| |
| #define BA_A64MERTN_cost 0x0006 |
| #define B16A64MERTN_cost 0x0006 |
| #define LSb32A64MERTN_cost 16 |
| #define LSb16A64MERTN_cost 0 |
| #define bA64MERTN_cost 16 |
| #define MSK32A64MERTN_cost 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64MERTN { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64MERTN_mvx(r32) _BFGET_(r32,15, 0) |
| #define SET32A64MERTN_mvx(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64MERTN_mvx(r16) _BFGET_(r16,15, 0) |
| #define SET16A64MERTN_mvx(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64MERTN_mvy(r32) _BFGET_(r32,31,16) |
| #define SET32A64MERTN_mvy(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64MERTN_mvy(r16) _BFGET_(r16,15, 0) |
| #define SET16A64MERTN_mvy(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 s_mvx : 16; |
| UNSG32 s_mvy : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32A64MERTN_sad(r32) _BFGET_(r32,15, 0) |
| #define SET32A64MERTN_sad(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64MERTN_sad(r16) _BFGET_(r16,15, 0) |
| #define SET16A64MERTN_sad(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64MERTN_cost(r32) _BFGET_(r32,31,16) |
| #define SET32A64MERTN_cost(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64MERTN_cost(r16) _BFGET_(r16,15, 0) |
| #define SET16A64MERTN_cost(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_sad : 16; |
| UNSG32 u_cost : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64MERTN; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64MERTN_drvrd(SIE_A64MERTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64MERTN_drvwr(SIE_A64MERTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64MERTN_reset(SIE_A64MERTN *p); |
| SIGN32 A64MERTN_cmp (SIE_A64MERTN *p, SIE_A64MERTN *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64MERTN_check(p,pie,pfx,hLOG) A64MERTN_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64MERTN_print(p, pfx,hLOG) A64MERTN_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64MERTN |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64ISRTN flat (8,2) |
| /// ### |
| /// * Return format used by ISR and CCO commands |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 SAD0 |
| /// ### |
| /// * SAD for block 0 of selected MV candidate |
| /// ### |
| /// %unsigned 16 SAD1 |
| /// ### |
| /// * SAD for block 1 of selected MV candidate |
| /// ### |
| /// %unsigned 16 SAD2 |
| /// ### |
| /// * SAD for block 2 of selected MV candidate |
| /// ### |
| /// %unsigned 16 SAD3 |
| /// ### |
| /// * SAD for block 3 of selected MV candidate |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64ISRTN |
| #define h_A64ISRTN (){} |
| |
| #define BA_A64ISRTN_SAD0 0x0000 |
| #define B16A64ISRTN_SAD0 0x0000 |
| #define LSb32A64ISRTN_SAD0 0 |
| #define LSb16A64ISRTN_SAD0 0 |
| #define bA64ISRTN_SAD0 16 |
| #define MSK32A64ISRTN_SAD0 0x0000FFFF |
| |
| #define BA_A64ISRTN_SAD1 0x0002 |
| #define B16A64ISRTN_SAD1 0x0002 |
| #define LSb32A64ISRTN_SAD1 16 |
| #define LSb16A64ISRTN_SAD1 0 |
| #define bA64ISRTN_SAD1 16 |
| #define MSK32A64ISRTN_SAD1 0xFFFF0000 |
| |
| #define BA_A64ISRTN_SAD2 0x0004 |
| #define B16A64ISRTN_SAD2 0x0004 |
| #define LSb32A64ISRTN_SAD2 0 |
| #define LSb16A64ISRTN_SAD2 0 |
| #define bA64ISRTN_SAD2 16 |
| #define MSK32A64ISRTN_SAD2 0x0000FFFF |
| |
| #define BA_A64ISRTN_SAD3 0x0006 |
| #define B16A64ISRTN_SAD3 0x0006 |
| #define LSb32A64ISRTN_SAD3 16 |
| #define LSb16A64ISRTN_SAD3 0 |
| #define bA64ISRTN_SAD3 16 |
| #define MSK32A64ISRTN_SAD3 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64ISRTN { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64ISRTN_SAD0(r32) _BFGET_(r32,15, 0) |
| #define SET32A64ISRTN_SAD0(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64ISRTN_SAD0(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ISRTN_SAD0(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64ISRTN_SAD1(r32) _BFGET_(r32,31,16) |
| #define SET32A64ISRTN_SAD1(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64ISRTN_SAD1(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ISRTN_SAD1(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_SAD0 : 16; |
| UNSG32 u_SAD1 : 16; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32A64ISRTN_SAD2(r32) _BFGET_(r32,15, 0) |
| #define SET32A64ISRTN_SAD2(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16A64ISRTN_SAD2(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ISRTN_SAD2(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32A64ISRTN_SAD3(r32) _BFGET_(r32,31,16) |
| #define SET32A64ISRTN_SAD3(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16A64ISRTN_SAD3(r16) _BFGET_(r16,15, 0) |
| #define SET16A64ISRTN_SAD3(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_SAD2 : 16; |
| UNSG32 u_SAD3 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64ISRTN; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64ISRTN_drvrd(SIE_A64ISRTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64ISRTN_drvwr(SIE_A64ISRTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64ISRTN_reset(SIE_A64ISRTN *p); |
| SIGN32 A64ISRTN_cmp (SIE_A64ISRTN *p, SIE_A64ISRTN *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64ISRTN_check(p,pie,pfx,hLOG) A64ISRTN_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64ISRTN_print(p, pfx,hLOG) A64ISRTN_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64ISRTN |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE A64GRADRTN flat (8,2) |
| /// ### |
| /// * Return format used by GRADIENT commands |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 10 avg_fx |
| /// ### |
| /// * Average value of first order horizontal gradient. |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// %unsigned 10 avg_fy |
| /// ### |
| /// * Average value of first order vertical gradient. |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// %unsigned 15 sum_g |
| /// ### |
| /// * Sum of second order gradient. |
| /// * CLIP to range ( 0 ~ 32767) |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// %unsigned 12 valid_g |
| /// ### |
| /// * Number of points has valid 2nd order gradient. |
| /// ### |
| /// %% 4 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_A64GRADRTN |
| #define h_A64GRADRTN (){} |
| |
| #define BA_A64GRADRTN_avg_fx 0x0000 |
| #define B16A64GRADRTN_avg_fx 0x0000 |
| #define LSb32A64GRADRTN_avg_fx 0 |
| #define LSb16A64GRADRTN_avg_fx 0 |
| #define bA64GRADRTN_avg_fx 10 |
| #define MSK32A64GRADRTN_avg_fx 0x000003FF |
| |
| #define BA_A64GRADRTN_avg_fy 0x0002 |
| #define B16A64GRADRTN_avg_fy 0x0002 |
| #define LSb32A64GRADRTN_avg_fy 16 |
| #define LSb16A64GRADRTN_avg_fy 0 |
| #define bA64GRADRTN_avg_fy 10 |
| #define MSK32A64GRADRTN_avg_fy 0x03FF0000 |
| |
| #define BA_A64GRADRTN_sum_g 0x0004 |
| #define B16A64GRADRTN_sum_g 0x0004 |
| #define LSb32A64GRADRTN_sum_g 0 |
| #define LSb16A64GRADRTN_sum_g 0 |
| #define bA64GRADRTN_sum_g 15 |
| #define MSK32A64GRADRTN_sum_g 0x00007FFF |
| |
| #define BA_A64GRADRTN_valid_g 0x0006 |
| #define B16A64GRADRTN_valid_g 0x0006 |
| #define LSb32A64GRADRTN_valid_g 16 |
| #define LSb16A64GRADRTN_valid_g 0 |
| #define bA64GRADRTN_valid_g 12 |
| #define MSK32A64GRADRTN_valid_g 0x0FFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_A64GRADRTN { |
| /////////////////////////////////////////////////////////// |
| #define GET32A64GRADRTN_avg_fx(r32) _BFGET_(r32, 9, 0) |
| #define SET32A64GRADRTN_avg_fx(r32,v) _BFSET_(r32, 9, 0,v) |
| #define GET16A64GRADRTN_avg_fx(r16) _BFGET_(r16, 9, 0) |
| #define SET16A64GRADRTN_avg_fx(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| #define GET32A64GRADRTN_avg_fy(r32) _BFGET_(r32,25,16) |
| #define SET32A64GRADRTN_avg_fy(r32,v) _BFSET_(r32,25,16,v) |
| #define GET16A64GRADRTN_avg_fy(r16) _BFGET_(r16, 9, 0) |
| #define SET16A64GRADRTN_avg_fy(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| UNSG32 u_avg_fx : 10; |
| UNSG32 RSVDx0_b10 : 6; |
| UNSG32 u_avg_fy : 10; |
| UNSG32 RSVDx0_b26 : 6; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32A64GRADRTN_sum_g(r32) _BFGET_(r32,14, 0) |
| #define SET32A64GRADRTN_sum_g(r32,v) _BFSET_(r32,14, 0,v) |
| #define GET16A64GRADRTN_sum_g(r16) _BFGET_(r16,14, 0) |
| #define SET16A64GRADRTN_sum_g(r16,v) _BFSET_(r16,14, 0,v) |
| |
| #define GET32A64GRADRTN_valid_g(r32) _BFGET_(r32,27,16) |
| #define SET32A64GRADRTN_valid_g(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16A64GRADRTN_valid_g(r16) _BFGET_(r16,11, 0) |
| #define SET16A64GRADRTN_valid_g(r16,v) _BFSET_(r16,11, 0,v) |
| |
| UNSG32 u_sum_g : 15; |
| UNSG32 RSVDx4_b15 : 1; |
| UNSG32 u_valid_g : 12; |
| UNSG32 RSVDx4_b28 : 4; |
| /////////////////////////////////////////////////////////// |
| } SIE_A64GRADRTN; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 A64GRADRTN_drvrd(SIE_A64GRADRTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 A64GRADRTN_drvwr(SIE_A64GRADRTN *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void A64GRADRTN_reset(SIE_A64GRADRTN *p); |
| SIGN32 A64GRADRTN_cmp (SIE_A64GRADRTN *p, SIE_A64GRADRTN *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define A64GRADRTN_check(p,pie,pfx,hLOG) A64GRADRTN_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define A64GRADRTN_print(p, pfx,hLOG) A64GRADRTN_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: A64GRADRTN |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dirMvScale biu (4,4) |
| /// ### |
| /// * Scaling factors for temporal direct MV calculation |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 12 factor |
| /// ### |
| /// * = clip(-1024, 1023, (tb*tx+32)>>6) |
| /// ### |
| /// %unsigned 20 RSVD20 |
| /// ### |
| /// * pad to 32 bits |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 32 RSVD32 |
| /// ### |
| /// * pad to 64 bits |
| /// * End dirMvScale |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dirMvScale |
| #define h_dirMvScale (){} |
| |
| #define BA_dirMvScale_factor 0x0000 |
| #define B16dirMvScale_factor 0x0000 |
| #define LSb32dirMvScale_factor 0 |
| #define LSb16dirMvScale_factor 0 |
| #define bdirMvScale_factor 12 |
| #define MSK32dirMvScale_factor 0x00000FFF |
| |
| #define BA_dirMvScale_RSVD20 0x0001 |
| #define B16dirMvScale_RSVD20 0x0000 |
| #define LSb32dirMvScale_RSVD20 12 |
| #define LSb16dirMvScale_RSVD20 12 |
| #define bdirMvScale_RSVD20 20 |
| #define MSK32dirMvScale_RSVD20 0xFFFFF000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_dirMvScale_RSVD32 0x0004 |
| #define B16dirMvScale_RSVD32 0x0004 |
| #define LSb32dirMvScale_RSVD32 0 |
| #define LSb16dirMvScale_RSVD32 0 |
| #define bdirMvScale_RSVD32 32 |
| #define MSK32dirMvScale_RSVD32 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dirMvScale { |
| /////////////////////////////////////////////////////////// |
| #define GET32dirMvScale_factor(r32) _BFGET_(r32,11, 0) |
| #define SET32dirMvScale_factor(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16dirMvScale_factor(r16) _BFGET_(r16,11, 0) |
| #define SET16dirMvScale_factor(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32dirMvScale_RSVD20(r32) _BFGET_(r32,31,12) |
| #define SET32dirMvScale_RSVD20(r32,v) _BFSET_(r32,31,12,v) |
| |
| UNSG32 s_factor : 12; |
| UNSG32 u_RSVD20 : 20; |
| /////////////////////////////////////////////////////////// |
| #define GET32dirMvScale_RSVD32(r32) _BFGET_(r32,31, 0) |
| #define SET32dirMvScale_RSVD32(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_RSVD32 : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_dirMvScale; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dirMvScale_drvrd(SIE_dirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dirMvScale_drvwr(SIE_dirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dirMvScale_reset(SIE_dirMvScale *p); |
| SIGN32 dirMvScale_cmp (SIE_dirMvScale *p, SIE_dirMvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dirMvScale_check(p,pie,pfx,hLOG) dirMvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dirMvScale_print(p, pfx,hLOG) dirMvScale_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dirMvScale |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE avsDirMvScale biu (4,4) |
| /// ### |
| /// * Scaling factors for temporal direct MV calculation for AVS |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 BlockDistanceFw |
| /// ### |
| /// * Block Distance between current block and forward reference block. |
| /// ### |
| /// %unsigned 16 BlockDistanceBw |
| /// ### |
| /// * Block Distance between backward reference block and current block. |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 16 invBlockDistanceRef |
| /// ### |
| /// * 16384/BlockDistanceRef, where BlockDistanceRef is the block distance between backward reference block and reference block of the co-located block. |
| /// ### |
| /// %unsigned 16 RSVD16 |
| /// ### |
| /// * pad to 64 bits |
| /// * End avsDirMvScale |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_avsDirMvScale |
| #define h_avsDirMvScale (){} |
| |
| #define BA_avsDirMvScale_BlockDistanceFw 0x0000 |
| #define B16avsDirMvScale_BlockDistanceFw 0x0000 |
| #define LSb32avsDirMvScale_BlockDistanceFw 0 |
| #define LSb16avsDirMvScale_BlockDistanceFw 0 |
| #define bavsDirMvScale_BlockDistanceFw 16 |
| #define MSK32avsDirMvScale_BlockDistanceFw 0x0000FFFF |
| |
| #define BA_avsDirMvScale_BlockDistanceBw 0x0002 |
| #define B16avsDirMvScale_BlockDistanceBw 0x0002 |
| #define LSb32avsDirMvScale_BlockDistanceBw 16 |
| #define LSb16avsDirMvScale_BlockDistanceBw 0 |
| #define bavsDirMvScale_BlockDistanceBw 16 |
| #define MSK32avsDirMvScale_BlockDistanceBw 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_avsDirMvScale_invBlockDistanceRef 0x0004 |
| #define B16avsDirMvScale_invBlockDistanceRef 0x0004 |
| #define LSb32avsDirMvScale_invBlockDistanceRef 0 |
| #define LSb16avsDirMvScale_invBlockDistanceRef 0 |
| #define bavsDirMvScale_invBlockDistanceRef 16 |
| #define MSK32avsDirMvScale_invBlockDistanceRef 0x0000FFFF |
| |
| #define BA_avsDirMvScale_RSVD16 0x0006 |
| #define B16avsDirMvScale_RSVD16 0x0006 |
| #define LSb32avsDirMvScale_RSVD16 16 |
| #define LSb16avsDirMvScale_RSVD16 0 |
| #define bavsDirMvScale_RSVD16 16 |
| #define MSK32avsDirMvScale_RSVD16 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_avsDirMvScale { |
| /////////////////////////////////////////////////////////// |
| #define GET32avsDirMvScale_BlockDistanceFw(r32) _BFGET_(r32,15, 0) |
| #define SET32avsDirMvScale_BlockDistanceFw(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16avsDirMvScale_BlockDistanceFw(r16) _BFGET_(r16,15, 0) |
| #define SET16avsDirMvScale_BlockDistanceFw(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32avsDirMvScale_BlockDistanceBw(r32) _BFGET_(r32,31,16) |
| #define SET32avsDirMvScale_BlockDistanceBw(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16avsDirMvScale_BlockDistanceBw(r16) _BFGET_(r16,15, 0) |
| #define SET16avsDirMvScale_BlockDistanceBw(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_BlockDistanceFw : 16; |
| UNSG32 u_BlockDistanceBw : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32avsDirMvScale_invBlockDistanceRef(r32) _BFGET_(r32,15, 0) |
| #define SET32avsDirMvScale_invBlockDistanceRef(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16avsDirMvScale_invBlockDistanceRef(r16) _BFGET_(r16,15, 0) |
| #define SET16avsDirMvScale_invBlockDistanceRef(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32avsDirMvScale_RSVD16(r32) _BFGET_(r32,31,16) |
| #define SET32avsDirMvScale_RSVD16(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16avsDirMvScale_RSVD16(r16) _BFGET_(r16,15, 0) |
| #define SET16avsDirMvScale_RSVD16(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_invBlockDistanceRef : 16; |
| UNSG32 u_RSVD16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_avsDirMvScale; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 avsDirMvScale_drvrd(SIE_avsDirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 avsDirMvScale_drvwr(SIE_avsDirMvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void avsDirMvScale_reset(SIE_avsDirMvScale *p); |
| SIGN32 avsDirMvScale_cmp (SIE_avsDirMvScale *p, SIE_avsDirMvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define avsDirMvScale_check(p,pie,pfx,hLOG) avsDirMvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define avsDirMvScale_print(p, pfx,hLOG) avsDirMvScale_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: avsDirMvScale |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BitOpX4 biu (4,4) |
| /// ### |
| /// * Operator format for BitOp extension |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 idx |
| /// ### |
| /// * rS[idx] or xT[idx] is used as source bit |
| /// * In case src==rS, idx[5:4] specifies the operation mode: |
| /// * idx[5:4]==2'b0x: output is from rS |
| /// * idx[5:4]==2'b10: output bit is forced to 0 |
| /// * idx[5:4]==2'b11: output bit is forced to 1 |
| /// ### |
| /// %unsigned 1 src |
| /// : xT 0x0 |
| /// : rS 0x1 |
| /// ### |
| /// * If src=rS, the source is from 16-bit input |
| /// * If src=xT, the source is from 64-bit input |
| /// ### |
| /// %unsigned 1 mode |
| /// : copy 0x0 |
| /// : inv 0x1 |
| /// ### |
| /// * copy: target bit copied from source bit |
| /// * inv: target bit copied from source bit then inverted |
| /// * Not used when src==rS & idx[5]==1'b1 |
| /// ### |
| /// %unsigned 6 idx1 |
| /// %unsigned 1 src1 |
| /// %unsigned 1 mode1 |
| /// %unsigned 6 idx2 |
| /// %unsigned 1 src2 |
| /// %unsigned 1 mode2 |
| /// %unsigned 6 idx3 |
| /// %unsigned 1 src3 |
| /// %unsigned 1 mode3 |
| /// ### |
| /// * End BitOpX4 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BitOpX4 |
| #define h_BitOpX4 (){} |
| |
| #define BA_BitOpX4_idx 0x0000 |
| #define B16BitOpX4_idx 0x0000 |
| #define LSb32BitOpX4_idx 0 |
| #define LSb16BitOpX4_idx 0 |
| #define bBitOpX4_idx 6 |
| #define MSK32BitOpX4_idx 0x0000003F |
| |
| #define BA_BitOpX4_src 0x0000 |
| #define B16BitOpX4_src 0x0000 |
| #define LSb32BitOpX4_src 6 |
| #define LSb16BitOpX4_src 6 |
| #define bBitOpX4_src 1 |
| #define MSK32BitOpX4_src 0x00000040 |
| #define BitOpX4_src_xT 0x0 |
| #define BitOpX4_src_rS 0x1 |
| |
| #define BA_BitOpX4_mode 0x0000 |
| #define B16BitOpX4_mode 0x0000 |
| #define LSb32BitOpX4_mode 7 |
| #define LSb16BitOpX4_mode 7 |
| #define bBitOpX4_mode 1 |
| #define MSK32BitOpX4_mode 0x00000080 |
| #define BitOpX4_mode_copy 0x0 |
| #define BitOpX4_mode_inv 0x1 |
| |
| #define BA_BitOpX4_idx1 0x0001 |
| #define B16BitOpX4_idx1 0x0000 |
| #define LSb32BitOpX4_idx1 8 |
| #define LSb16BitOpX4_idx1 8 |
| #define bBitOpX4_idx1 6 |
| #define MSK32BitOpX4_idx1 0x00003F00 |
| |
| #define BA_BitOpX4_src1 0x0001 |
| #define B16BitOpX4_src1 0x0000 |
| #define LSb32BitOpX4_src1 14 |
| #define LSb16BitOpX4_src1 14 |
| #define bBitOpX4_src1 1 |
| #define MSK32BitOpX4_src1 0x00004000 |
| |
| #define BA_BitOpX4_mode1 0x0001 |
| #define B16BitOpX4_mode1 0x0000 |
| #define LSb32BitOpX4_mode1 15 |
| #define LSb16BitOpX4_mode1 15 |
| #define bBitOpX4_mode1 1 |
| #define MSK32BitOpX4_mode1 0x00008000 |
| |
| #define BA_BitOpX4_idx2 0x0002 |
| #define B16BitOpX4_idx2 0x0002 |
| #define LSb32BitOpX4_idx2 16 |
| #define LSb16BitOpX4_idx2 0 |
| #define bBitOpX4_idx2 6 |
| #define MSK32BitOpX4_idx2 0x003F0000 |
| |
| #define BA_BitOpX4_src2 0x0002 |
| #define B16BitOpX4_src2 0x0002 |
| #define LSb32BitOpX4_src2 22 |
| #define LSb16BitOpX4_src2 6 |
| #define bBitOpX4_src2 1 |
| #define MSK32BitOpX4_src2 0x00400000 |
| |
| #define BA_BitOpX4_mode2 0x0002 |
| #define B16BitOpX4_mode2 0x0002 |
| #define LSb32BitOpX4_mode2 23 |
| #define LSb16BitOpX4_mode2 7 |
| #define bBitOpX4_mode2 1 |
| #define MSK32BitOpX4_mode2 0x00800000 |
| |
| #define BA_BitOpX4_idx3 0x0003 |
| #define B16BitOpX4_idx3 0x0002 |
| #define LSb32BitOpX4_idx3 24 |
| #define LSb16BitOpX4_idx3 8 |
| #define bBitOpX4_idx3 6 |
| #define MSK32BitOpX4_idx3 0x3F000000 |
| |
| #define BA_BitOpX4_src3 0x0003 |
| #define B16BitOpX4_src3 0x0002 |
| #define LSb32BitOpX4_src3 30 |
| #define LSb16BitOpX4_src3 14 |
| #define bBitOpX4_src3 1 |
| #define MSK32BitOpX4_src3 0x40000000 |
| |
| #define BA_BitOpX4_mode3 0x0003 |
| #define B16BitOpX4_mode3 0x0002 |
| #define LSb32BitOpX4_mode3 31 |
| #define LSb16BitOpX4_mode3 15 |
| #define bBitOpX4_mode3 1 |
| #define MSK32BitOpX4_mode3 0x80000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BitOpX4 { |
| /////////////////////////////////////////////////////////// |
| #define GET32BitOpX4_idx(r32) _BFGET_(r32, 5, 0) |
| #define SET32BitOpX4_idx(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16BitOpX4_idx(r16) _BFGET_(r16, 5, 0) |
| #define SET16BitOpX4_idx(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32BitOpX4_src(r32) _BFGET_(r32, 6, 6) |
| #define SET32BitOpX4_src(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16BitOpX4_src(r16) _BFGET_(r16, 6, 6) |
| #define SET16BitOpX4_src(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32BitOpX4_mode(r32) _BFGET_(r32, 7, 7) |
| #define SET32BitOpX4_mode(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16BitOpX4_mode(r16) _BFGET_(r16, 7, 7) |
| #define SET16BitOpX4_mode(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32BitOpX4_idx1(r32) _BFGET_(r32,13, 8) |
| #define SET32BitOpX4_idx1(r32,v) _BFSET_(r32,13, 8,v) |
| #define GET16BitOpX4_idx1(r16) _BFGET_(r16,13, 8) |
| #define SET16BitOpX4_idx1(r16,v) _BFSET_(r16,13, 8,v) |
| |
| #define GET32BitOpX4_src1(r32) _BFGET_(r32,14,14) |
| #define SET32BitOpX4_src1(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16BitOpX4_src1(r16) _BFGET_(r16,14,14) |
| #define SET16BitOpX4_src1(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32BitOpX4_mode1(r32) _BFGET_(r32,15,15) |
| #define SET32BitOpX4_mode1(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16BitOpX4_mode1(r16) _BFGET_(r16,15,15) |
| #define SET16BitOpX4_mode1(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32BitOpX4_idx2(r32) _BFGET_(r32,21,16) |
| #define SET32BitOpX4_idx2(r32,v) _BFSET_(r32,21,16,v) |
| #define GET16BitOpX4_idx2(r16) _BFGET_(r16, 5, 0) |
| #define SET16BitOpX4_idx2(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32BitOpX4_src2(r32) _BFGET_(r32,22,22) |
| #define SET32BitOpX4_src2(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16BitOpX4_src2(r16) _BFGET_(r16, 6, 6) |
| #define SET16BitOpX4_src2(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32BitOpX4_mode2(r32) _BFGET_(r32,23,23) |
| #define SET32BitOpX4_mode2(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16BitOpX4_mode2(r16) _BFGET_(r16, 7, 7) |
| #define SET16BitOpX4_mode2(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32BitOpX4_idx3(r32) _BFGET_(r32,29,24) |
| #define SET32BitOpX4_idx3(r32,v) _BFSET_(r32,29,24,v) |
| #define GET16BitOpX4_idx3(r16) _BFGET_(r16,13, 8) |
| #define SET16BitOpX4_idx3(r16,v) _BFSET_(r16,13, 8,v) |
| |
| #define GET32BitOpX4_src3(r32) _BFGET_(r32,30,30) |
| #define SET32BitOpX4_src3(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16BitOpX4_src3(r16) _BFGET_(r16,14,14) |
| #define SET16BitOpX4_src3(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32BitOpX4_mode3(r32) _BFGET_(r32,31,31) |
| #define SET32BitOpX4_mode3(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16BitOpX4_mode3(r16) _BFGET_(r16,15,15) |
| #define SET16BitOpX4_mode3(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_idx : 6; |
| UNSG32 u_src : 1; |
| UNSG32 u_mode : 1; |
| UNSG32 u_idx1 : 6; |
| UNSG32 u_src1 : 1; |
| UNSG32 u_mode1 : 1; |
| UNSG32 u_idx2 : 6; |
| UNSG32 u_src2 : 1; |
| UNSG32 u_mode2 : 1; |
| UNSG32 u_idx3 : 6; |
| UNSG32 u_src3 : 1; |
| UNSG32 u_mode3 : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_BitOpX4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BitOpX4_drvrd(SIE_BitOpX4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BitOpX4_drvwr(SIE_BitOpX4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BitOpX4_reset(SIE_BitOpX4 *p); |
| SIGN32 BitOpX4_cmp (SIE_BitOpX4 *p, SIE_BitOpX4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BitOpX4_check(p,pie,pfx,hLOG) BitOpX4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BitOpX4_print(p, pfx,hLOG) BitOpX4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BitOpX4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BITOPRF64 biu (4,4) |
| /// ### |
| /// * Operator format for BitOp extension |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// : BitOp0 0x20 |
| /// : BitOp1 0x21 |
| /// : BitOp2 0x22 |
| /// : BitOp3 0x23 |
| /// ### |
| /// * extension ID definition; must be consistent with vScope_F0A64_BitOp0~3 |
| /// ### |
| /// @ 0x00000 (P) |
| /// # 0x00000 cmd0 |
| /// $BitOpX4 cmd0 REG [4] |
| /// @ 0x00010 (P) |
| /// # 0x00010 cmd1 |
| /// $BitOpX4 cmd1 REG [4] |
| /// @ 0x00020 (P) |
| /// # 0x00020 cmd2 |
| /// $BitOpX4 cmd2 REG [4] |
| /// @ 0x00030 (P) |
| /// # 0x00030 cmd3 |
| /// $BitOpX4 cmd3 REG [4] |
| /// ### |
| /// * Four BitOp commands, selected by extension ID |
| /// * End BitOpCtx |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 64B, bits: 512b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BITOPRF64 |
| #define h_BITOPRF64 (){} |
| |
| #define BITOPRF64_BitOp0 0x20 |
| #define BITOPRF64_BitOp1 0x21 |
| #define BITOPRF64_BitOp2 0x22 |
| #define BITOPRF64_BitOp3 0x23 |
| /////////////////////////////////////////////////////////// |
| #define RA_BITOPRF64_cmd0 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_BITOPRF64_cmd1 0x0010 |
| /////////////////////////////////////////////////////////// |
| #define RA_BITOPRF64_cmd2 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_BITOPRF64_cmd3 0x0030 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BITOPRF64 { |
| /////////////////////////////////////////////////////////// |
| SIE_BitOpX4 ie_cmd0[4]; |
| /////////////////////////////////////////////////////////// |
| SIE_BitOpX4 ie_cmd1[4]; |
| /////////////////////////////////////////////////////////// |
| SIE_BitOpX4 ie_cmd2[4]; |
| /////////////////////////////////////////////////////////// |
| SIE_BitOpX4 ie_cmd3[4]; |
| /////////////////////////////////////////////////////////// |
| } SIE_BITOPRF64; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BITOPRF64_drvrd(SIE_BITOPRF64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BITOPRF64_drvwr(SIE_BITOPRF64 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BITOPRF64_reset(SIE_BITOPRF64 *p); |
| SIGN32 BITOPRF64_cmp (SIE_BITOPRF64 *p, SIE_BITOPRF64 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BITOPRF64_check(p,pie,pfx,hLOG) BITOPRF64_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BITOPRF64_print(p, pfx,hLOG) BITOPRF64_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BITOPRF64 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE LUT8b (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 data |
| /// ### |
| /// * Any 8b data |
| /// ### |
| /// %unsigned 8 data1 |
| /// %unsigned 8 data2 |
| /// %unsigned 8 data3 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_LUT8b |
| #define h_LUT8b (){} |
| |
| #define BA_LUT8b_data 0x0000 |
| #define B16LUT8b_data 0x0000 |
| #define LSb32LUT8b_data 0 |
| #define LSb16LUT8b_data 0 |
| #define bLUT8b_data 8 |
| #define MSK32LUT8b_data 0x000000FF |
| |
| #define BA_LUT8b_data1 0x0001 |
| #define B16LUT8b_data1 0x0000 |
| #define LSb32LUT8b_data1 8 |
| #define LSb16LUT8b_data1 8 |
| #define bLUT8b_data1 8 |
| #define MSK32LUT8b_data1 0x0000FF00 |
| |
| #define BA_LUT8b_data2 0x0002 |
| #define B16LUT8b_data2 0x0002 |
| #define LSb32LUT8b_data2 16 |
| #define LSb16LUT8b_data2 0 |
| #define bLUT8b_data2 8 |
| #define MSK32LUT8b_data2 0x00FF0000 |
| |
| #define BA_LUT8b_data3 0x0003 |
| #define B16LUT8b_data3 0x0002 |
| #define LSb32LUT8b_data3 24 |
| #define LSb16LUT8b_data3 8 |
| #define bLUT8b_data3 8 |
| #define MSK32LUT8b_data3 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_LUT8b { |
| /////////////////////////////////////////////////////////// |
| #define GET32LUT8b_data(r32) _BFGET_(r32, 7, 0) |
| #define SET32LUT8b_data(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16LUT8b_data(r16) _BFGET_(r16, 7, 0) |
| #define SET16LUT8b_data(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32LUT8b_data1(r32) _BFGET_(r32,15, 8) |
| #define SET32LUT8b_data1(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16LUT8b_data1(r16) _BFGET_(r16,15, 8) |
| #define SET16LUT8b_data1(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32LUT8b_data2(r32) _BFGET_(r32,23,16) |
| #define SET32LUT8b_data2(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16LUT8b_data2(r16) _BFGET_(r16, 7, 0) |
| #define SET16LUT8b_data2(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32LUT8b_data3(r32) _BFGET_(r32,31,24) |
| #define SET32LUT8b_data3(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16LUT8b_data3(r16) _BFGET_(r16,15, 8) |
| #define SET16LUT8b_data3(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_data : 8; |
| UNSG32 u_data1 : 8; |
| UNSG32 u_data2 : 8; |
| UNSG32 u_data3 : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_LUT8b; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 LUT8b_drvrd(SIE_LUT8b *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 LUT8b_drvwr(SIE_LUT8b *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void LUT8b_reset(SIE_LUT8b *p); |
| SIGN32 LUT8b_cmp (SIE_LUT8b *p, SIE_LUT8b *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define LUT8b_check(p,pie,pfx,hLOG) LUT8b_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define LUT8b_print(p, pfx,hLOG) LUT8b_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: LUT8b |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE LUT64b (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 data_0i |
| /// %unsigned 32 data_1i |
| /// ### |
| /// * Any 64b data |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_LUT64b |
| #define h_LUT64b (){} |
| |
| #define BA_LUT64b_data_0i 0x0000 |
| #define B16LUT64b_data_0i 0x0000 |
| #define LSb32LUT64b_data_0i 0 |
| #define LSb16LUT64b_data_0i 0 |
| #define bLUT64b_data_0i 32 |
| #define MSK32LUT64b_data_0i 0xFFFFFFFF |
| |
| #define BA_LUT64b_data_1i 0x0004 |
| #define B16LUT64b_data_1i 0x0004 |
| #define LSb32LUT64b_data_1i 0 |
| #define LSb16LUT64b_data_1i 0 |
| #define bLUT64b_data_1i 32 |
| #define MSK32LUT64b_data_1i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_LUT64b { |
| /////////////////////////////////////////////////////////// |
| #define GET32LUT64b_data_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32LUT64b_data_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32LUT64b_data_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32LUT64b_data_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_data_1i : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_LUT64b; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 LUT64b_drvrd(SIE_LUT64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 LUT64b_drvwr(SIE_LUT64b *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void LUT64b_reset(SIE_LUT64b *p); |
| SIGN32 LUT64b_cmp (SIE_LUT64b *p, SIE_LUT64b *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define LUT64b_check(p,pie,pfx,hLOG) LUT64b_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define LUT64b_print(p, pfx,hLOG) LUT64b_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: LUT64b |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE NLoc (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 BLK |
| /// ### |
| /// * Block index |
| /// ### |
| /// %unsigned 4 category |
| /// : 16x16 0x8 |
| /// : 8x16 0x9 |
| /// : 16x8 0xA |
| /// : 4mv 0xB |
| /// : 8x8 0xC |
| /// : 4x8 0xD |
| /// : 8x4 0xE |
| /// : 4x4 0xF |
| /// ### |
| /// * Consistent with vcMsg{RSVD,level,partition} |
| /// * Valid cases for Neighbor: |
| /// * 16x16=16x8 |
| /// * 8x16=4mv=8x8=8x4 |
| /// * 4x8=4x4=ACY |
| /// * Valid cases for PMV: |
| /// * 16x16=16x8 |
| /// * 8x16 |
| /// * 4mv=8x8=8x4 |
| /// * 4x8=4x4=ACY |
| /// ### |
| /// : ACY 0x0 |
| /// ### |
| /// * Valid block index: |
| /// * 0~15 (every 4x4 indexed by coding order) |
| /// ### |
| /// : ACU 0x2 |
| /// ### |
| /// * Valid block index: |
| /// * 0~3 (3rd 4x4 in every 8x8) |
| /// ### |
| /// : ACV 0x3 |
| /// ### |
| /// * Valid block index: |
| /// * 0~3 (4th 4x4 in every 8x8) |
| /// ### |
| /// : I16AC 0x4 |
| /// ### |
| /// * Only used as category, should be converted to ACY for neighbor look-up |
| /// ### |
| /// : DCI 0x4 |
| /// ### |
| /// * Valid block index: |
| /// * 0 (3rd 4x4 in 4th 8x8 only) |
| /// ### |
| /// : DCY 0x5 |
| /// ### |
| /// * Valid block index: |
| /// * 0 (4th 4x4 in 4th 8x8 only) |
| /// ### |
| /// : SDPMV 0x5 |
| /// ### |
| /// * Reuse DCY in PMV extension, for Spatial Direct mode rIDX recovery. |
| /// ### |
| /// : DCU 0x6 |
| /// ### |
| /// * Valid block index: |
| /// * 0 (3rd 4x4 in 3rd 8x8 only) |
| /// ### |
| /// : DCV 0x7 |
| /// ### |
| /// * Valid block index: |
| /// * 0 (4th 4x4 in 3rd 8x8 only) |
| /// ### |
| /// %unsigned 1 parity |
| /// ### |
| /// * 0/1 as even/odd, only for loop-filter |
| /// ### |
| /// %unsigned 1 direct |
| /// ### |
| /// * FW use only: if direct mode |
| /// * AVS: use for sym mode in hardware. |
| /// ### |
| /// %unsigned 2 motion |
| /// ### |
| /// * FW use only: motion type |
| /// ### |
| /// %unsigned 1 A |
| /// ### |
| /// * Left macroblock/block availability |
| /// ### |
| /// %unsigned 1 B |
| /// ### |
| /// * Upper macroblock/block availability |
| /// ### |
| /// %unsigned 1 C |
| /// ### |
| /// * Upper-right macroblock/block availability |
| /// ### |
| /// %unsigned 1 D |
| /// ### |
| /// * Upper-left macroblock/block availability |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_NLoc |
| #define h_NLoc (){} |
| |
| #define BA_NLoc_BLK 0x0000 |
| #define B16NLoc_BLK 0x0000 |
| #define LSb32NLoc_BLK 0 |
| #define LSb16NLoc_BLK 0 |
| #define bNLoc_BLK 4 |
| #define MSK32NLoc_BLK 0x0000000F |
| |
| #define BA_NLoc_category 0x0000 |
| #define B16NLoc_category 0x0000 |
| #define LSb32NLoc_category 4 |
| #define LSb16NLoc_category 4 |
| #define bNLoc_category 4 |
| #define MSK32NLoc_category 0x000000F0 |
| #define NLoc_category_16x16 0x8 |
| #define NLoc_category_8x16 0x9 |
| #define NLoc_category_16x8 0xA |
| #define NLoc_category_4mv 0xB |
| #define NLoc_category_8x8 0xC |
| #define NLoc_category_4x8 0xD |
| #define NLoc_category_8x4 0xE |
| #define NLoc_category_4x4 0xF |
| #define NLoc_category_ACY 0x0 |
| #define NLoc_category_ACU 0x2 |
| #define NLoc_category_ACV 0x3 |
| #define NLoc_category_I16AC 0x4 |
| #define NLoc_category_DCI 0x4 |
| #define NLoc_category_DCY 0x5 |
| #define NLoc_category_SDPMV 0x5 |
| #define NLoc_category_DCU 0x6 |
| #define NLoc_category_DCV 0x7 |
| |
| #define BA_NLoc_parity 0x0001 |
| #define B16NLoc_parity 0x0000 |
| #define LSb32NLoc_parity 8 |
| #define LSb16NLoc_parity 8 |
| #define bNLoc_parity 1 |
| #define MSK32NLoc_parity 0x00000100 |
| |
| #define BA_NLoc_direct 0x0001 |
| #define B16NLoc_direct 0x0000 |
| #define LSb32NLoc_direct 9 |
| #define LSb16NLoc_direct 9 |
| #define bNLoc_direct 1 |
| #define MSK32NLoc_direct 0x00000200 |
| |
| #define BA_NLoc_motion 0x0001 |
| #define B16NLoc_motion 0x0000 |
| #define LSb32NLoc_motion 10 |
| #define LSb16NLoc_motion 10 |
| #define bNLoc_motion 2 |
| #define MSK32NLoc_motion 0x00000C00 |
| |
| #define BA_NLoc_A 0x0001 |
| #define B16NLoc_A 0x0000 |
| #define LSb32NLoc_A 12 |
| #define LSb16NLoc_A 12 |
| #define bNLoc_A 1 |
| #define MSK32NLoc_A 0x00001000 |
| |
| #define BA_NLoc_B 0x0001 |
| #define B16NLoc_B 0x0000 |
| #define LSb32NLoc_B 13 |
| #define LSb16NLoc_B 13 |
| #define bNLoc_B 1 |
| #define MSK32NLoc_B 0x00002000 |
| |
| #define BA_NLoc_C 0x0001 |
| #define B16NLoc_C 0x0000 |
| #define LSb32NLoc_C 14 |
| #define LSb16NLoc_C 14 |
| #define bNLoc_C 1 |
| #define MSK32NLoc_C 0x00004000 |
| |
| #define BA_NLoc_D 0x0001 |
| #define B16NLoc_D 0x0000 |
| #define LSb32NLoc_D 15 |
| #define LSb16NLoc_D 15 |
| #define bNLoc_D 1 |
| #define MSK32NLoc_D 0x00008000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_NLoc { |
| /////////////////////////////////////////////////////////// |
| #define GET32NLoc_BLK(r32) _BFGET_(r32, 3, 0) |
| #define SET32NLoc_BLK(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16NLoc_BLK(r16) _BFGET_(r16, 3, 0) |
| #define SET16NLoc_BLK(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32NLoc_category(r32) _BFGET_(r32, 7, 4) |
| #define SET32NLoc_category(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16NLoc_category(r16) _BFGET_(r16, 7, 4) |
| #define SET16NLoc_category(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32NLoc_parity(r32) _BFGET_(r32, 8, 8) |
| #define SET32NLoc_parity(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16NLoc_parity(r16) _BFGET_(r16, 8, 8) |
| #define SET16NLoc_parity(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32NLoc_direct(r32) _BFGET_(r32, 9, 9) |
| #define SET32NLoc_direct(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16NLoc_direct(r16) _BFGET_(r16, 9, 9) |
| #define SET16NLoc_direct(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32NLoc_motion(r32) _BFGET_(r32,11,10) |
| #define SET32NLoc_motion(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16NLoc_motion(r16) _BFGET_(r16,11,10) |
| #define SET16NLoc_motion(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32NLoc_A(r32) _BFGET_(r32,12,12) |
| #define SET32NLoc_A(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16NLoc_A(r16) _BFGET_(r16,12,12) |
| #define SET16NLoc_A(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32NLoc_B(r32) _BFGET_(r32,13,13) |
| #define SET32NLoc_B(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16NLoc_B(r16) _BFGET_(r16,13,13) |
| #define SET16NLoc_B(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32NLoc_C(r32) _BFGET_(r32,14,14) |
| #define SET32NLoc_C(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16NLoc_C(r16) _BFGET_(r16,14,14) |
| #define SET16NLoc_C(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32NLoc_D(r32) _BFGET_(r32,15,15) |
| #define SET32NLoc_D(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16NLoc_D(r16) _BFGET_(r16,15,15) |
| #define SET16NLoc_D(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_BLK : 4; |
| UNSG32 u_category : 4; |
| UNSG32 u_parity : 1; |
| UNSG32 u_direct : 1; |
| UNSG32 u_motion : 2; |
| UNSG32 u_A : 1; |
| UNSG32 u_B : 1; |
| UNSG32 u_C : 1; |
| UNSG32 u_D : 1; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_NLoc; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 NLoc_drvrd(SIE_NLoc *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 NLoc_drvwr(SIE_NLoc *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void NLoc_reset(SIE_NLoc *p); |
| SIGN32 NLoc_cmp (SIE_NLoc *p, SIE_NLoc *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define NLoc_check(p,pie,pfx,hLOG) NLoc_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define NLoc_print(p, pfx,hLOG) NLoc_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: NLoc |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BLK (4,4) |
| /// # # ---------------------------------------------------------- |
| /// : skip 0x0 |
| /// : direct16x16 0x1 |
| /// : 4BLK 0x2 |
| /// : inter 0x3 |
| /// : IPCM 0x4 |
| /// : intra16x16 0x5 |
| /// : intraNxN 0x6 |
| /// ### |
| /// * Sub-set of mb_type |
| /// * MPEG2: only skip, inter, intra (intra16x16) |
| /// * MPEG4/VC-1: only 1 intra type (intra16x16) |
| /// * AVS: skip, direct16x16, 4BLK, inter, intra16x16 (only 1 intra type) |
| /// ### |
| /// @ 0x00000 (P) |
| /// %unsigned 2 motion |
| /// : Intra 0x0 |
| /// : Forward 0x1 |
| /// : Backward 0x2 |
| /// : Bi 0x3 |
| /// ### |
| /// * Derived 8x8 block motion type |
| /// * NOTE: direct mode uses 'Bi' |
| /// ### |
| /// %unsigned 2 partition |
| /// : 1mv 0x0 |
| /// : 2mvLR 0x1 |
| /// : 2mvTB 0x2 |
| /// ### |
| /// * MPEG2: 2mvTB used for field prediction |
| /// * VC-1: 2-field-mv |
| /// ### |
| /// : 4mv 0x3 |
| /// ### |
| /// * Block/macroblock level partitioning |
| /// * MPEG4: 1mv & 4mv |
| /// ### |
| /// : 4mvFLD 0x1 |
| /// ### |
| /// * VC-1: 4-field-mv |
| /// ### |
| /// %unsigned 1 direct |
| /// ### |
| /// * Direct mode flag |
| /// * MPEG2: dual-prime prediction |
| /// ### |
| /// %unsigned 3 mvs |
| /// ### |
| /// * Number of motion vectors: 0/1/2/4 |
| /// ### |
| /// %unsigned 2 motion1 |
| /// %unsigned 2 partition1 |
| /// %unsigned 1 direct1 |
| /// %unsigned 3 mvs1 |
| /// %unsigned 2 motion2 |
| /// %unsigned 2 partition2 |
| /// %unsigned 1 direct2 |
| /// %unsigned 3 mvs2 |
| /// %unsigned 2 motion3 |
| /// %unsigned 2 partition3 |
| /// %unsigned 1 direct3 |
| /// %unsigned 3 mvs3 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BLK |
| #define h_BLK (){} |
| |
| #define BLK_skip 0x0 |
| #define BLK_direct16x16 0x1 |
| #define BLK_4BLK 0x2 |
| #define BLK_inter 0x3 |
| #define BLK_IPCM 0x4 |
| #define BLK_intra16x16 0x5 |
| #define BLK_intraNxN 0x6 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_BLK_motion 0x0000 |
| #define B16BLK_motion 0x0000 |
| #define LSb32BLK_motion 0 |
| #define LSb16BLK_motion 0 |
| #define bBLK_motion 2 |
| #define MSK32BLK_motion 0x00000003 |
| #define BLK_motion_Intra 0x0 |
| #define BLK_motion_Forward 0x1 |
| #define BLK_motion_Backward 0x2 |
| #define BLK_motion_Bi 0x3 |
| |
| #define BA_BLK_partition 0x0000 |
| #define B16BLK_partition 0x0000 |
| #define LSb32BLK_partition 2 |
| #define LSb16BLK_partition 2 |
| #define bBLK_partition 2 |
| #define MSK32BLK_partition 0x0000000C |
| #define BLK_partition_1mv 0x0 |
| #define BLK_partition_2mvLR 0x1 |
| #define BLK_partition_2mvTB 0x2 |
| #define BLK_partition_4mv 0x3 |
| #define BLK_partition_4mvFLD 0x1 |
| |
| #define BA_BLK_direct 0x0000 |
| #define B16BLK_direct 0x0000 |
| #define LSb32BLK_direct 4 |
| #define LSb16BLK_direct 4 |
| #define bBLK_direct 1 |
| #define MSK32BLK_direct 0x00000010 |
| |
| #define BA_BLK_mvs 0x0000 |
| #define B16BLK_mvs 0x0000 |
| #define LSb32BLK_mvs 5 |
| #define LSb16BLK_mvs 5 |
| #define bBLK_mvs 3 |
| #define MSK32BLK_mvs 0x000000E0 |
| |
| #define BA_BLK_motion1 0x0001 |
| #define B16BLK_motion1 0x0000 |
| #define LSb32BLK_motion1 8 |
| #define LSb16BLK_motion1 8 |
| #define bBLK_motion1 2 |
| #define MSK32BLK_motion1 0x00000300 |
| |
| #define BA_BLK_partition1 0x0001 |
| #define B16BLK_partition1 0x0000 |
| #define LSb32BLK_partition1 10 |
| #define LSb16BLK_partition1 10 |
| #define bBLK_partition1 2 |
| #define MSK32BLK_partition1 0x00000C00 |
| |
| #define BA_BLK_direct1 0x0001 |
| #define B16BLK_direct1 0x0000 |
| #define LSb32BLK_direct1 12 |
| #define LSb16BLK_direct1 12 |
| #define bBLK_direct1 1 |
| #define MSK32BLK_direct1 0x00001000 |
| |
| #define BA_BLK_mvs1 0x0001 |
| #define B16BLK_mvs1 0x0000 |
| #define LSb32BLK_mvs1 13 |
| #define LSb16BLK_mvs1 13 |
| #define bBLK_mvs1 3 |
| #define MSK32BLK_mvs1 0x0000E000 |
| |
| #define BA_BLK_motion2 0x0002 |
| #define B16BLK_motion2 0x0002 |
| #define LSb32BLK_motion2 16 |
| #define LSb16BLK_motion2 0 |
| #define bBLK_motion2 2 |
| #define MSK32BLK_motion2 0x00030000 |
| |
| #define BA_BLK_partition2 0x0002 |
| #define B16BLK_partition2 0x0002 |
| #define LSb32BLK_partition2 18 |
| #define LSb16BLK_partition2 2 |
| #define bBLK_partition2 2 |
| #define MSK32BLK_partition2 0x000C0000 |
| |
| #define BA_BLK_direct2 0x0002 |
| #define B16BLK_direct2 0x0002 |
| #define LSb32BLK_direct2 20 |
| #define LSb16BLK_direct2 4 |
| #define bBLK_direct2 1 |
| #define MSK32BLK_direct2 0x00100000 |
| |
| #define BA_BLK_mvs2 0x0002 |
| #define B16BLK_mvs2 0x0002 |
| #define LSb32BLK_mvs2 21 |
| #define LSb16BLK_mvs2 5 |
| #define bBLK_mvs2 3 |
| #define MSK32BLK_mvs2 0x00E00000 |
| |
| #define BA_BLK_motion3 0x0003 |
| #define B16BLK_motion3 0x0002 |
| #define LSb32BLK_motion3 24 |
| #define LSb16BLK_motion3 8 |
| #define bBLK_motion3 2 |
| #define MSK32BLK_motion3 0x03000000 |
| |
| #define BA_BLK_partition3 0x0003 |
| #define B16BLK_partition3 0x0002 |
| #define LSb32BLK_partition3 26 |
| #define LSb16BLK_partition3 10 |
| #define bBLK_partition3 2 |
| #define MSK32BLK_partition3 0x0C000000 |
| |
| #define BA_BLK_direct3 0x0003 |
| #define B16BLK_direct3 0x0002 |
| #define LSb32BLK_direct3 28 |
| #define LSb16BLK_direct3 12 |
| #define bBLK_direct3 1 |
| #define MSK32BLK_direct3 0x10000000 |
| |
| #define BA_BLK_mvs3 0x0003 |
| #define B16BLK_mvs3 0x0002 |
| #define LSb32BLK_mvs3 29 |
| #define LSb16BLK_mvs3 13 |
| #define bBLK_mvs3 3 |
| #define MSK32BLK_mvs3 0xE0000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BLK { |
| /////////////////////////////////////////////////////////// |
| #define GET32BLK_motion(r32) _BFGET_(r32, 1, 0) |
| #define SET32BLK_motion(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16BLK_motion(r16) _BFGET_(r16, 1, 0) |
| #define SET16BLK_motion(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32BLK_partition(r32) _BFGET_(r32, 3, 2) |
| #define SET32BLK_partition(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16BLK_partition(r16) _BFGET_(r16, 3, 2) |
| #define SET16BLK_partition(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32BLK_direct(r32) _BFGET_(r32, 4, 4) |
| #define SET32BLK_direct(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16BLK_direct(r16) _BFGET_(r16, 4, 4) |
| #define SET16BLK_direct(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32BLK_mvs(r32) _BFGET_(r32, 7, 5) |
| #define SET32BLK_mvs(r32,v) _BFSET_(r32, 7, 5,v) |
| #define GET16BLK_mvs(r16) _BFGET_(r16, 7, 5) |
| #define SET16BLK_mvs(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32BLK_motion1(r32) _BFGET_(r32, 9, 8) |
| #define SET32BLK_motion1(r32,v) _BFSET_(r32, 9, 8,v) |
| #define GET16BLK_motion1(r16) _BFGET_(r16, 9, 8) |
| #define SET16BLK_motion1(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32BLK_partition1(r32) _BFGET_(r32,11,10) |
| #define SET32BLK_partition1(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16BLK_partition1(r16) _BFGET_(r16,11,10) |
| #define SET16BLK_partition1(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32BLK_direct1(r32) _BFGET_(r32,12,12) |
| #define SET32BLK_direct1(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16BLK_direct1(r16) _BFGET_(r16,12,12) |
| #define SET16BLK_direct1(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32BLK_mvs1(r32) _BFGET_(r32,15,13) |
| #define SET32BLK_mvs1(r32,v) _BFSET_(r32,15,13,v) |
| #define GET16BLK_mvs1(r16) _BFGET_(r16,15,13) |
| #define SET16BLK_mvs1(r16,v) _BFSET_(r16,15,13,v) |
| |
| #define GET32BLK_motion2(r32) _BFGET_(r32,17,16) |
| #define SET32BLK_motion2(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16BLK_motion2(r16) _BFGET_(r16, 1, 0) |
| #define SET16BLK_motion2(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32BLK_partition2(r32) _BFGET_(r32,19,18) |
| #define SET32BLK_partition2(r32,v) _BFSET_(r32,19,18,v) |
| #define GET16BLK_partition2(r16) _BFGET_(r16, 3, 2) |
| #define SET16BLK_partition2(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32BLK_direct2(r32) _BFGET_(r32,20,20) |
| #define SET32BLK_direct2(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16BLK_direct2(r16) _BFGET_(r16, 4, 4) |
| #define SET16BLK_direct2(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32BLK_mvs2(r32) _BFGET_(r32,23,21) |
| #define SET32BLK_mvs2(r32,v) _BFSET_(r32,23,21,v) |
| #define GET16BLK_mvs2(r16) _BFGET_(r16, 7, 5) |
| #define SET16BLK_mvs2(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32BLK_motion3(r32) _BFGET_(r32,25,24) |
| #define SET32BLK_motion3(r32,v) _BFSET_(r32,25,24,v) |
| #define GET16BLK_motion3(r16) _BFGET_(r16, 9, 8) |
| #define SET16BLK_motion3(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32BLK_partition3(r32) _BFGET_(r32,27,26) |
| #define SET32BLK_partition3(r32,v) _BFSET_(r32,27,26,v) |
| #define GET16BLK_partition3(r16) _BFGET_(r16,11,10) |
| #define SET16BLK_partition3(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32BLK_direct3(r32) _BFGET_(r32,28,28) |
| #define SET32BLK_direct3(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16BLK_direct3(r16) _BFGET_(r16,12,12) |
| #define SET16BLK_direct3(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32BLK_mvs3(r32) _BFGET_(r32,31,29) |
| #define SET32BLK_mvs3(r32,v) _BFSET_(r32,31,29,v) |
| #define GET16BLK_mvs3(r16) _BFGET_(r16,15,13) |
| #define SET16BLK_mvs3(r16,v) _BFSET_(r16,15,13,v) |
| |
| UNSG32 u_motion : 2; |
| UNSG32 u_partition : 2; |
| UNSG32 u_direct : 1; |
| UNSG32 u_mvs : 3; |
| UNSG32 u_motion1 : 2; |
| UNSG32 u_partition1 : 2; |
| UNSG32 u_direct1 : 1; |
| UNSG32 u_mvs1 : 3; |
| UNSG32 u_motion2 : 2; |
| UNSG32 u_partition2 : 2; |
| UNSG32 u_direct2 : 1; |
| UNSG32 u_mvs2 : 3; |
| UNSG32 u_motion3 : 2; |
| UNSG32 u_partition3 : 2; |
| UNSG32 u_direct3 : 1; |
| UNSG32 u_mvs3 : 3; |
| /////////////////////////////////////////////////////////// |
| } SIE_BLK; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BLK_drvrd(SIE_BLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BLK_drvwr(SIE_BLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BLK_reset(SIE_BLK *p); |
| SIGN32 BLK_cmp (SIE_BLK *p, SIE_BLK *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BLK_check(p,pie,pfx,hLOG) BLK_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BLK_print(p, pfx,hLOG) BLK_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BLK |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE MV (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 2 motion |
| /// ### |
| /// * Derived 8x8 block motion type (direct mode uses 'Bi'), see BLK.motion above |
| /// ### |
| /// %signed 14 X |
| /// ### |
| /// * Horizontal motion vector, |
| /// * Or MVD between parser & syntax processor |
| /// ### |
| /// %unsigned 3 type |
| /// ### |
| /// * Sub-set of mb_type, see MBPROP.type above |
| /// ### |
| /// %signed 13 Y |
| /// ### |
| /// * Vertical motion vector, |
| /// * Or MVD between parser & syntax processor |
| /// * End of MV |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_MV |
| #define h_MV (){} |
| |
| #define BA_MV_motion 0x0000 |
| #define B16MV_motion 0x0000 |
| #define LSb32MV_motion 0 |
| #define LSb16MV_motion 0 |
| #define bMV_motion 2 |
| #define MSK32MV_motion 0x00000003 |
| |
| #define BA_MV_X 0x0000 |
| #define B16MV_X 0x0000 |
| #define LSb32MV_X 2 |
| #define LSb16MV_X 2 |
| #define bMV_X 14 |
| #define MSK32MV_X 0x0000FFFC |
| |
| #define BA_MV_type 0x0002 |
| #define B16MV_type 0x0002 |
| #define LSb32MV_type 16 |
| #define LSb16MV_type 0 |
| #define bMV_type 3 |
| #define MSK32MV_type 0x00070000 |
| |
| #define BA_MV_Y 0x0002 |
| #define B16MV_Y 0x0002 |
| #define LSb32MV_Y 19 |
| #define LSb16MV_Y 3 |
| #define bMV_Y 13 |
| #define MSK32MV_Y 0xFFF80000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_MV { |
| /////////////////////////////////////////////////////////// |
| #define GET32MV_motion(r32) _BFGET_(r32, 1, 0) |
| #define SET32MV_motion(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16MV_motion(r16) _BFGET_(r16, 1, 0) |
| #define SET16MV_motion(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32MV_X(r32) _BFGET_(r32,15, 2) |
| #define SET32MV_X(r32,v) _BFSET_(r32,15, 2,v) |
| #define GET16MV_X(r16) _BFGET_(r16,15, 2) |
| #define SET16MV_X(r16,v) _BFSET_(r16,15, 2,v) |
| |
| #define GET32MV_type(r32) _BFGET_(r32,18,16) |
| #define SET32MV_type(r32,v) _BFSET_(r32,18,16,v) |
| #define GET16MV_type(r16) _BFGET_(r16, 2, 0) |
| #define SET16MV_type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32MV_Y(r32) _BFGET_(r32,31,19) |
| #define SET32MV_Y(r32,v) _BFSET_(r32,31,19,v) |
| #define GET16MV_Y(r16) _BFGET_(r16,15, 3) |
| #define SET16MV_Y(r16,v) _BFSET_(r16,15, 3,v) |
| |
| UNSG32 u_motion : 2; |
| UNSG32 s_X : 14; |
| UNSG32 u_type : 3; |
| UNSG32 s_Y : 13; |
| /////////////////////////////////////////////////////////// |
| } SIE_MV; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 MV_drvrd(SIE_MV *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 MV_drvwr(SIE_MV *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void MV_reset(SIE_MV *p); |
| SIGN32 MV_cmp (SIE_MV *p, SIE_MV *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define MV_check(p,pie,pfx,hLOG) MV_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define MV_print(p, pfx,hLOG) MV_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: MV |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FCTX biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 rBID |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as direct mode between parser & syntax processor): |
| /// * Reference buffer ID, last 1b indicates access mode: |
| /// * 0: frame/progressive or top field |
| /// * 1: bottom field |
| /// ### |
| /// %unsigned 5 rIDX |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor): |
| /// * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded) |
| /// ### |
| /// %unsigned 1 FLD |
| /// ### |
| /// * Flatten 4x4s in each 8x8: |
| /// * 1 for MBAFF field MB, 0 for otherwise |
| /// ### |
| /// %unsigned 1 equalpred |
| /// ### |
| /// * BLK property for CABAC only: |
| /// * Using block category ACV, |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !Intra && !skipped && (bi-pred || fore-pred) |
| /// * NOTE: = 0 for direct mode |
| /// * VC-1: |
| /// * PMV output: for hybridPred |
| /// * PMV input: predictor_flag (0: use dominant PMV) |
| /// ### |
| /// %unsigned 1 transform |
| /// ### |
| /// * MB property (flatten in all 4x4s): |
| /// * H.264: if 8x8 transform |
| /// * Others: if field transform |
| /// ### |
| /// %unsigned 1 NCBPY |
| /// ### |
| /// * Loop-filter & CABAC use only: |
| /// * Luma using block category ACV (4th 4x4), |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !(IPCM || cbp_luma) |
| /// ### |
| /// %unsigned 1 MixFLG |
| /// ### |
| /// * CABAC use only: |
| /// * CBP chroma using block category DCU/DCV, |
| /// * (Only at 3rd & 4th 4x4s in 3rd 8x8): |
| /// * bin[0]: IPCM || !(skipped || (cbp_chroma == 0)) |
| /// * bin[1]: IPCM || !(skipped || (cbp_chroma != 2)) |
| /// * Or: |
| /// * mb_type using block category DCY, |
| /// * (Only at 4th 4x4 in 4th 8x8): |
| /// * I_SLICE: = !I_NXN |
| /// * P_SLICE: = 0 |
| /// * B_SLICE: = !skipped && !direct_16x16 |
| /// * Or: |
| /// * intra-chroma_pred using block category DCI, |
| /// * (Only at 3rd 4x4 in 4th 8x8): |
| /// * = Intra && !IPCM && (intra_chroma_pred != 0) |
| /// * Or: |
| /// * Temporal context buffers for direct mode use |
| /// ### |
| /// : 8x8 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 1st 8x8: |
| /// * = if MB contains no sub-8x8 partition |
| /// ### |
| /// : 16x16 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 2nd 8x8: |
| /// * = if MB contains only 1 partition (16x16) |
| /// ### |
| /// %unsigned 1 CBFY |
| /// ### |
| /// * Loop-filter & CABAC use only: |
| /// * Using block category ACY (every 4x4s): |
| /// * = IPCM || cbf_luma_ac |
| /// ### |
| /// %unsigned 1 CBFUV |
| /// ### |
| /// * CABAC use only: |
| /// * Using block category ACU/ACV, |
| /// * (Only at 3rd & 4th 4x4 in each 8x8s): |
| /// * = IPCM || cbf_chroma_ac |
| /// ### |
| /// %unsigned 1 CBFDC |
| /// ### |
| /// * CABAC use only: |
| /// * LumaDC using block category DCY, |
| /// * (Only at 4th 4x4 in 4th 8x8): |
| /// * = IPCM || (I_16x16 && cbf_luma_dc) |
| /// * ChromaDC using block category DCU/DCV, |
| /// * (Only at 3rd 4x4 in 3rd & 4th 8x8): |
| /// * = IPCM || cbf_chroma_dc |
| /// ### |
| /// %unsigned 6 ABSMVDX |
| /// ### |
| /// * CABAC use only: |
| /// * MIN( ABS(MVD.x), 63 ) |
| /// ### |
| /// %unsigned 7 ABSMVDY |
| /// ### |
| /// * CABAC use only: |
| /// * MIN( ABS(MVD.y), 127 ) |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 mv |
| /// $MV mv REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FCTX |
| #define h_FCTX (){} |
| |
| #define BA_FCTX_rBID 0x0000 |
| #define B16FCTX_rBID 0x0000 |
| #define LSb32FCTX_rBID 0 |
| #define LSb16FCTX_rBID 0 |
| #define bFCTX_rBID 6 |
| #define MSK32FCTX_rBID 0x0000003F |
| |
| #define BA_FCTX_rIDX 0x0000 |
| #define B16FCTX_rIDX 0x0000 |
| #define LSb32FCTX_rIDX 6 |
| #define LSb16FCTX_rIDX 6 |
| #define bFCTX_rIDX 5 |
| #define MSK32FCTX_rIDX 0x000007C0 |
| |
| #define BA_FCTX_FLD 0x0001 |
| #define B16FCTX_FLD 0x0000 |
| #define LSb32FCTX_FLD 11 |
| #define LSb16FCTX_FLD 11 |
| #define bFCTX_FLD 1 |
| #define MSK32FCTX_FLD 0x00000800 |
| |
| #define BA_FCTX_equalpred 0x0001 |
| #define B16FCTX_equalpred 0x0000 |
| #define LSb32FCTX_equalpred 12 |
| #define LSb16FCTX_equalpred 12 |
| #define bFCTX_equalpred 1 |
| #define MSK32FCTX_equalpred 0x00001000 |
| |
| #define BA_FCTX_transform 0x0001 |
| #define B16FCTX_transform 0x0000 |
| #define LSb32FCTX_transform 13 |
| #define LSb16FCTX_transform 13 |
| #define bFCTX_transform 1 |
| #define MSK32FCTX_transform 0x00002000 |
| |
| #define BA_FCTX_NCBPY 0x0001 |
| #define B16FCTX_NCBPY 0x0000 |
| #define LSb32FCTX_NCBPY 14 |
| #define LSb16FCTX_NCBPY 14 |
| #define bFCTX_NCBPY 1 |
| #define MSK32FCTX_NCBPY 0x00004000 |
| |
| #define BA_FCTX_MixFLG 0x0001 |
| #define B16FCTX_MixFLG 0x0000 |
| #define LSb32FCTX_MixFLG 15 |
| #define LSb16FCTX_MixFLG 15 |
| #define bFCTX_MixFLG 1 |
| #define MSK32FCTX_MixFLG 0x00008000 |
| #define FCTX_MixFLG_8x8 0x1 |
| #define FCTX_MixFLG_16x16 0x1 |
| |
| #define BA_FCTX_CBFY 0x0002 |
| #define B16FCTX_CBFY 0x0002 |
| #define LSb32FCTX_CBFY 16 |
| #define LSb16FCTX_CBFY 0 |
| #define bFCTX_CBFY 1 |
| #define MSK32FCTX_CBFY 0x00010000 |
| |
| #define BA_FCTX_CBFUV 0x0002 |
| #define B16FCTX_CBFUV 0x0002 |
| #define LSb32FCTX_CBFUV 17 |
| #define LSb16FCTX_CBFUV 1 |
| #define bFCTX_CBFUV 1 |
| #define MSK32FCTX_CBFUV 0x00020000 |
| |
| #define BA_FCTX_CBFDC 0x0002 |
| #define B16FCTX_CBFDC 0x0002 |
| #define LSb32FCTX_CBFDC 18 |
| #define LSb16FCTX_CBFDC 2 |
| #define bFCTX_CBFDC 1 |
| #define MSK32FCTX_CBFDC 0x00040000 |
| |
| #define BA_FCTX_ABSMVDX 0x0002 |
| #define B16FCTX_ABSMVDX 0x0002 |
| #define LSb32FCTX_ABSMVDX 19 |
| #define LSb16FCTX_ABSMVDX 3 |
| #define bFCTX_ABSMVDX 6 |
| #define MSK32FCTX_ABSMVDX 0x01F80000 |
| |
| #define BA_FCTX_ABSMVDY 0x0003 |
| #define B16FCTX_ABSMVDY 0x0002 |
| #define LSb32FCTX_ABSMVDY 25 |
| #define LSb16FCTX_ABSMVDY 9 |
| #define bFCTX_ABSMVDY 7 |
| #define MSK32FCTX_ABSMVDY 0xFE000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FCTX_mv 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FCTX { |
| /////////////////////////////////////////////////////////// |
| #define GET32FCTX_rBID(r32) _BFGET_(r32, 5, 0) |
| #define SET32FCTX_rBID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16FCTX_rBID(r16) _BFGET_(r16, 5, 0) |
| #define SET16FCTX_rBID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32FCTX_rIDX(r32) _BFGET_(r32,10, 6) |
| #define SET32FCTX_rIDX(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16FCTX_rIDX(r16) _BFGET_(r16,10, 6) |
| #define SET16FCTX_rIDX(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32FCTX_FLD(r32) _BFGET_(r32,11,11) |
| #define SET32FCTX_FLD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16FCTX_FLD(r16) _BFGET_(r16,11,11) |
| #define SET16FCTX_FLD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32FCTX_equalpred(r32) _BFGET_(r32,12,12) |
| #define SET32FCTX_equalpred(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16FCTX_equalpred(r16) _BFGET_(r16,12,12) |
| #define SET16FCTX_equalpred(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32FCTX_transform(r32) _BFGET_(r32,13,13) |
| #define SET32FCTX_transform(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16FCTX_transform(r16) _BFGET_(r16,13,13) |
| #define SET16FCTX_transform(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32FCTX_NCBPY(r32) _BFGET_(r32,14,14) |
| #define SET32FCTX_NCBPY(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16FCTX_NCBPY(r16) _BFGET_(r16,14,14) |
| #define SET16FCTX_NCBPY(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32FCTX_MixFLG(r32) _BFGET_(r32,15,15) |
| #define SET32FCTX_MixFLG(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16FCTX_MixFLG(r16) _BFGET_(r16,15,15) |
| #define SET16FCTX_MixFLG(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32FCTX_CBFY(r32) _BFGET_(r32,16,16) |
| #define SET32FCTX_CBFY(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16FCTX_CBFY(r16) _BFGET_(r16, 0, 0) |
| #define SET16FCTX_CBFY(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32FCTX_CBFUV(r32) _BFGET_(r32,17,17) |
| #define SET32FCTX_CBFUV(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16FCTX_CBFUV(r16) _BFGET_(r16, 1, 1) |
| #define SET16FCTX_CBFUV(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32FCTX_CBFDC(r32) _BFGET_(r32,18,18) |
| #define SET32FCTX_CBFDC(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16FCTX_CBFDC(r16) _BFGET_(r16, 2, 2) |
| #define SET16FCTX_CBFDC(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32FCTX_ABSMVDX(r32) _BFGET_(r32,24,19) |
| #define SET32FCTX_ABSMVDX(r32,v) _BFSET_(r32,24,19,v) |
| #define GET16FCTX_ABSMVDX(r16) _BFGET_(r16, 8, 3) |
| #define SET16FCTX_ABSMVDX(r16,v) _BFSET_(r16, 8, 3,v) |
| |
| #define GET32FCTX_ABSMVDY(r32) _BFGET_(r32,31,25) |
| #define SET32FCTX_ABSMVDY(r32,v) _BFSET_(r32,31,25,v) |
| #define GET16FCTX_ABSMVDY(r16) _BFGET_(r16,15, 9) |
| #define SET16FCTX_ABSMVDY(r16,v) _BFSET_(r16,15, 9,v) |
| |
| UNSG32 u_rBID : 6; |
| UNSG32 u_rIDX : 5; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_equalpred : 1; |
| UNSG32 u_transform : 1; |
| UNSG32 u_NCBPY : 1; |
| UNSG32 u_MixFLG : 1; |
| UNSG32 u_CBFY : 1; |
| UNSG32 u_CBFUV : 1; |
| UNSG32 u_CBFDC : 1; |
| UNSG32 u_ABSMVDX : 6; |
| UNSG32 u_ABSMVDY : 7; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_mv; |
| /////////////////////////////////////////////////////////// |
| } SIE_FCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FCTX_drvrd(SIE_FCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FCTX_drvwr(SIE_FCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FCTX_reset(SIE_FCTX *p); |
| SIGN32 FCTX_cmp (SIE_FCTX *p, SIE_FCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FCTX_check(p,pie,pfx,hLOG) FCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FCTX_print(p, pfx,hLOG) FCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FCTX_VC1 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 rBID |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as direct mode between parser & syntax processor): |
| /// * Reference buffer ID, last 1b indicates access mode: |
| /// * 0: frame/progressive or top field |
| /// * 1: bottom field |
| /// ### |
| /// %unsigned 5 rIDX |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor): |
| /// * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded) |
| /// ### |
| /// %unsigned 1 FLD |
| /// ### |
| /// * Flatten 4x4s in each 8x8: |
| /// * 1 for MBAFF field MB, 0 for otherwise |
| /// ### |
| /// %unsigned 1 equalpred |
| /// ### |
| /// * BLK property for CABAC only: |
| /// * Using block category ACV, |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !Intra && !skipped && (bi-pred || fore-pred) |
| /// * NOTE: = 0 for direct mode |
| /// * VC-1: |
| /// * PMV output: for hybridPred |
| /// * PMV input: predictor_flag (0: use dominant PMV) |
| /// ### |
| /// %unsigned 1 transform |
| /// ### |
| /// * MB property (flatten in all 4x4s): |
| /// * H.264: if 8x8 transform |
| /// * Others: if field transform |
| /// ### |
| /// %unsigned 1 NCBPY |
| /// ### |
| /// * Loop-filter & CABAC use only: |
| /// * Luma using block category ACV (4th 4x4), |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !(IPCM || cbp_luma) |
| /// ### |
| /// %unsigned 1 MixFLG |
| /// ### |
| /// * CABAC use only: |
| /// * CBP chroma using block category DCU/DCV, |
| /// * (Only at 3rd & 4th 4x4s in 3rd 8x8): |
| /// * bin[0]: IPCM || !(skipped || (cbp_chroma == 0)) |
| /// * bin[1]: IPCM || !(skipped || (cbp_chroma != 2)) |
| /// * Or: |
| /// * mb_type using block category DCY, |
| /// * (Only at 4th 4x4 in 4th 8x8): |
| /// * I_SLICE: = !I_NXN |
| /// * P_SLICE: = 0 |
| /// * B_SLICE: = !skipped && !direct_16x16 |
| /// * Or: |
| /// * intra-chroma_pred using block category DCI, |
| /// * (Only at 3rd 4x4 in 4th 8x8): |
| /// * = Intra && !IPCM && (intra_chroma_pred != 0) |
| /// * Or: |
| /// * Temporal context buffers for direct mode use |
| /// ### |
| /// : 8x8 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 1st 8x8: |
| /// * = if MB contains no sub-8x8 partition |
| /// ### |
| /// : 16x16 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 2nd 8x8: |
| /// * = if MB contains only 1 partition (16x16) |
| /// ### |
| /// %unsigned 2 dctSelY |
| /// : 4x4 0x0 |
| /// : 8x8 0x1 |
| /// : 4x8 0x2 |
| /// : 8x4 0x3 |
| /// ### |
| /// * DCT transform type for Y, used for VC-1 Fop |
| /// * flattened to all 4x4 blocks within transform block |
| /// ### |
| /// %unsigned 1 CBFY |
| /// ### |
| /// * coded block (4x4) flag for Y, used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 CBFY8x8 |
| /// ### |
| /// * coded block (8x8) flag for Y, used for VC-1 MP Fop |
| /// ### |
| /// %unsigned 12 RSVD12 |
| /// @ 0x00004 (P) |
| /// # 0x00004 mv |
| /// $MV mv REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FCTX_VC1 |
| #define h_FCTX_VC1 (){} |
| |
| #define BA_FCTX_VC1_rBID 0x0000 |
| #define B16FCTX_VC1_rBID 0x0000 |
| #define LSb32FCTX_VC1_rBID 0 |
| #define LSb16FCTX_VC1_rBID 0 |
| #define bFCTX_VC1_rBID 6 |
| #define MSK32FCTX_VC1_rBID 0x0000003F |
| |
| #define BA_FCTX_VC1_rIDX 0x0000 |
| #define B16FCTX_VC1_rIDX 0x0000 |
| #define LSb32FCTX_VC1_rIDX 6 |
| #define LSb16FCTX_VC1_rIDX 6 |
| #define bFCTX_VC1_rIDX 5 |
| #define MSK32FCTX_VC1_rIDX 0x000007C0 |
| |
| #define BA_FCTX_VC1_FLD 0x0001 |
| #define B16FCTX_VC1_FLD 0x0000 |
| #define LSb32FCTX_VC1_FLD 11 |
| #define LSb16FCTX_VC1_FLD 11 |
| #define bFCTX_VC1_FLD 1 |
| #define MSK32FCTX_VC1_FLD 0x00000800 |
| |
| #define BA_FCTX_VC1_equalpred 0x0001 |
| #define B16FCTX_VC1_equalpred 0x0000 |
| #define LSb32FCTX_VC1_equalpred 12 |
| #define LSb16FCTX_VC1_equalpred 12 |
| #define bFCTX_VC1_equalpred 1 |
| #define MSK32FCTX_VC1_equalpred 0x00001000 |
| |
| #define BA_FCTX_VC1_transform 0x0001 |
| #define B16FCTX_VC1_transform 0x0000 |
| #define LSb32FCTX_VC1_transform 13 |
| #define LSb16FCTX_VC1_transform 13 |
| #define bFCTX_VC1_transform 1 |
| #define MSK32FCTX_VC1_transform 0x00002000 |
| |
| #define BA_FCTX_VC1_NCBPY 0x0001 |
| #define B16FCTX_VC1_NCBPY 0x0000 |
| #define LSb32FCTX_VC1_NCBPY 14 |
| #define LSb16FCTX_VC1_NCBPY 14 |
| #define bFCTX_VC1_NCBPY 1 |
| #define MSK32FCTX_VC1_NCBPY 0x00004000 |
| |
| #define BA_FCTX_VC1_MixFLG 0x0001 |
| #define B16FCTX_VC1_MixFLG 0x0000 |
| #define LSb32FCTX_VC1_MixFLG 15 |
| #define LSb16FCTX_VC1_MixFLG 15 |
| #define bFCTX_VC1_MixFLG 1 |
| #define MSK32FCTX_VC1_MixFLG 0x00008000 |
| #define FCTX_VC1_MixFLG_8x8 0x1 |
| #define FCTX_VC1_MixFLG_16x16 0x1 |
| |
| #define BA_FCTX_VC1_dctSelY 0x0002 |
| #define B16FCTX_VC1_dctSelY 0x0002 |
| #define LSb32FCTX_VC1_dctSelY 16 |
| #define LSb16FCTX_VC1_dctSelY 0 |
| #define bFCTX_VC1_dctSelY 2 |
| #define MSK32FCTX_VC1_dctSelY 0x00030000 |
| #define FCTX_VC1_dctSelY_4x4 0x0 |
| #define FCTX_VC1_dctSelY_8x8 0x1 |
| #define FCTX_VC1_dctSelY_4x8 0x2 |
| #define FCTX_VC1_dctSelY_8x4 0x3 |
| |
| #define BA_FCTX_VC1_CBFY 0x0002 |
| #define B16FCTX_VC1_CBFY 0x0002 |
| #define LSb32FCTX_VC1_CBFY 18 |
| #define LSb16FCTX_VC1_CBFY 2 |
| #define bFCTX_VC1_CBFY 1 |
| #define MSK32FCTX_VC1_CBFY 0x00040000 |
| |
| #define BA_FCTX_VC1_CBFY8x8 0x0002 |
| #define B16FCTX_VC1_CBFY8x8 0x0002 |
| #define LSb32FCTX_VC1_CBFY8x8 19 |
| #define LSb16FCTX_VC1_CBFY8x8 3 |
| #define bFCTX_VC1_CBFY8x8 1 |
| #define MSK32FCTX_VC1_CBFY8x8 0x00080000 |
| |
| #define BA_FCTX_VC1_RSVD12 0x0002 |
| #define B16FCTX_VC1_RSVD12 0x0002 |
| #define LSb32FCTX_VC1_RSVD12 20 |
| #define LSb16FCTX_VC1_RSVD12 4 |
| #define bFCTX_VC1_RSVD12 12 |
| #define MSK32FCTX_VC1_RSVD12 0xFFF00000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FCTX_VC1_mv 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FCTX_VC1 { |
| /////////////////////////////////////////////////////////// |
| #define GET32FCTX_VC1_rBID(r32) _BFGET_(r32, 5, 0) |
| #define SET32FCTX_VC1_rBID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16FCTX_VC1_rBID(r16) _BFGET_(r16, 5, 0) |
| #define SET16FCTX_VC1_rBID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32FCTX_VC1_rIDX(r32) _BFGET_(r32,10, 6) |
| #define SET32FCTX_VC1_rIDX(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16FCTX_VC1_rIDX(r16) _BFGET_(r16,10, 6) |
| #define SET16FCTX_VC1_rIDX(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32FCTX_VC1_FLD(r32) _BFGET_(r32,11,11) |
| #define SET32FCTX_VC1_FLD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16FCTX_VC1_FLD(r16) _BFGET_(r16,11,11) |
| #define SET16FCTX_VC1_FLD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32FCTX_VC1_equalpred(r32) _BFGET_(r32,12,12) |
| #define SET32FCTX_VC1_equalpred(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16FCTX_VC1_equalpred(r16) _BFGET_(r16,12,12) |
| #define SET16FCTX_VC1_equalpred(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32FCTX_VC1_transform(r32) _BFGET_(r32,13,13) |
| #define SET32FCTX_VC1_transform(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16FCTX_VC1_transform(r16) _BFGET_(r16,13,13) |
| #define SET16FCTX_VC1_transform(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32FCTX_VC1_NCBPY(r32) _BFGET_(r32,14,14) |
| #define SET32FCTX_VC1_NCBPY(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16FCTX_VC1_NCBPY(r16) _BFGET_(r16,14,14) |
| #define SET16FCTX_VC1_NCBPY(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32FCTX_VC1_MixFLG(r32) _BFGET_(r32,15,15) |
| #define SET32FCTX_VC1_MixFLG(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16FCTX_VC1_MixFLG(r16) _BFGET_(r16,15,15) |
| #define SET16FCTX_VC1_MixFLG(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32FCTX_VC1_dctSelY(r32) _BFGET_(r32,17,16) |
| #define SET32FCTX_VC1_dctSelY(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16FCTX_VC1_dctSelY(r16) _BFGET_(r16, 1, 0) |
| #define SET16FCTX_VC1_dctSelY(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32FCTX_VC1_CBFY(r32) _BFGET_(r32,18,18) |
| #define SET32FCTX_VC1_CBFY(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16FCTX_VC1_CBFY(r16) _BFGET_(r16, 2, 2) |
| #define SET16FCTX_VC1_CBFY(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32FCTX_VC1_CBFY8x8(r32) _BFGET_(r32,19,19) |
| #define SET32FCTX_VC1_CBFY8x8(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16FCTX_VC1_CBFY8x8(r16) _BFGET_(r16, 3, 3) |
| #define SET16FCTX_VC1_CBFY8x8(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32FCTX_VC1_RSVD12(r32) _BFGET_(r32,31,20) |
| #define SET32FCTX_VC1_RSVD12(r32,v) _BFSET_(r32,31,20,v) |
| #define GET16FCTX_VC1_RSVD12(r16) _BFGET_(r16,15, 4) |
| #define SET16FCTX_VC1_RSVD12(r16,v) _BFSET_(r16,15, 4,v) |
| |
| UNSG32 u_rBID : 6; |
| UNSG32 u_rIDX : 5; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_equalpred : 1; |
| UNSG32 u_transform : 1; |
| UNSG32 u_NCBPY : 1; |
| UNSG32 u_MixFLG : 1; |
| UNSG32 u_dctSelY : 2; |
| UNSG32 u_CBFY : 1; |
| UNSG32 u_CBFY8x8 : 1; |
| UNSG32 u_RSVD12 : 12; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_mv; |
| /////////////////////////////////////////////////////////// |
| } SIE_FCTX_VC1; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FCTX_VC1_drvrd(SIE_FCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FCTX_VC1_drvwr(SIE_FCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FCTX_VC1_reset(SIE_FCTX_VC1 *p); |
| SIGN32 FCTX_VC1_cmp (SIE_FCTX_VC1 *p, SIE_FCTX_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FCTX_VC1_check(p,pie,pfx,hLOG) FCTX_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FCTX_VC1_print(p, pfx,hLOG) FCTX_VC1_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FCTX_VC1 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FCTX_RV9 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 rBID |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as direct mode between parser & syntax processor): |
| /// * Reference buffer ID, last 1b indicates access mode: |
| /// * 0: frame/progressive or top field |
| /// * 1: bottom field |
| /// ### |
| /// %unsigned 5 rIDX |
| /// ### |
| /// * Flatten 4x4s in each 8x8, |
| /// * 0 for intra (as well as P/B-skip & direct mode between parser & syntax processor): |
| /// * Syntax 'RefListIdx' directly decoded from bit stream (field information embedded) |
| /// ### |
| /// %unsigned 1 FLD |
| /// ### |
| /// * Flatten 4x4s in each 8x8: |
| /// * 1 for MBAFF field MB, 0 for otherwise |
| /// ### |
| /// %unsigned 1 equalpred |
| /// ### |
| /// * BLK property for CABAC only: |
| /// * Using block category ACV, |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !Intra && !skipped && (bi-pred || fore-pred) |
| /// * NOTE: = 0 for direct mode |
| /// * VC-1: |
| /// * PMV output: for hybridPred |
| /// * PMV input: predictor_flag (0: use dominant PMV) |
| /// ### |
| /// %unsigned 1 transform |
| /// ### |
| /// * MB property (flatten in all 4x4s): |
| /// * H.264: if 8x8 transform |
| /// * Others: if field transform |
| /// ### |
| /// %unsigned 1 NCBPY |
| /// ### |
| /// * Loop-filter & CABAC use only: |
| /// * Luma using block category ACV (4th 4x4), |
| /// * (But flatten to all 4x4s in each 8x8s): |
| /// * = !(IPCM || cbp_luma) |
| /// ### |
| /// %unsigned 1 MixFLG |
| /// ### |
| /// * CABAC use only: |
| /// * CBP chroma using block category DCU/DCV, |
| /// * (Only at 3rd & 4th 4x4s in 3rd 8x8): |
| /// * bin[0]: IPCM || !(skipped || (cbp_chroma == 0)) |
| /// * bin[1]: IPCM || !(skipped || (cbp_chroma != 2)) |
| /// * Or: |
| /// * mb_type using block category DCY, |
| /// * (Only at 4th 4x4 in 4th 8x8): |
| /// * I_SLICE: = !I_NXN |
| /// * P_SLICE: = 0 |
| /// * B_SLICE: = !skipped && !direct_16x16 |
| /// * Or: |
| /// * intra-chroma_pred using block category DCI, |
| /// * (Only at 3rd 4x4 in 4th 8x8): |
| /// * = Intra && !IPCM && (intra_chroma_pred != 0) |
| /// * Or: |
| /// * Temporal context buffers for direct mode use |
| /// ### |
| /// : 8x8 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 1st 8x8: |
| /// * = if MB contains no sub-8x8 partition |
| /// ### |
| /// : 16x16 0x1 |
| /// ### |
| /// * Only at 1st 4x4 in 2nd 8x8: |
| /// * = if MB contains only 1 partition (16x16) |
| /// ### |
| /// %unsigned 1 CBPY |
| /// ### |
| /// * CBP for Y |
| /// ### |
| /// %unsigned 1 CBPU |
| /// ### |
| /// * CBP for U |
| /// ### |
| /// %unsigned 1 CBPV |
| /// ### |
| /// * CBP for Y |
| /// ### |
| /// %unsigned 2 BsY |
| /// ### |
| /// * Block strength for Y |
| /// ### |
| /// %unsigned 2 BsU |
| /// ### |
| /// * Block strength for U |
| /// ### |
| /// %unsigned 2 BsV |
| /// ### |
| /// * Block strength for V |
| /// ### |
| /// %unsigned 7 Rsvd |
| /// ### |
| /// * Reserved |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 mv |
| /// $MV mv REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FCTX_RV9 |
| #define h_FCTX_RV9 (){} |
| |
| #define BA_FCTX_RV9_rBID 0x0000 |
| #define B16FCTX_RV9_rBID 0x0000 |
| #define LSb32FCTX_RV9_rBID 0 |
| #define LSb16FCTX_RV9_rBID 0 |
| #define bFCTX_RV9_rBID 6 |
| #define MSK32FCTX_RV9_rBID 0x0000003F |
| |
| #define BA_FCTX_RV9_rIDX 0x0000 |
| #define B16FCTX_RV9_rIDX 0x0000 |
| #define LSb32FCTX_RV9_rIDX 6 |
| #define LSb16FCTX_RV9_rIDX 6 |
| #define bFCTX_RV9_rIDX 5 |
| #define MSK32FCTX_RV9_rIDX 0x000007C0 |
| |
| #define BA_FCTX_RV9_FLD 0x0001 |
| #define B16FCTX_RV9_FLD 0x0000 |
| #define LSb32FCTX_RV9_FLD 11 |
| #define LSb16FCTX_RV9_FLD 11 |
| #define bFCTX_RV9_FLD 1 |
| #define MSK32FCTX_RV9_FLD 0x00000800 |
| |
| #define BA_FCTX_RV9_equalpred 0x0001 |
| #define B16FCTX_RV9_equalpred 0x0000 |
| #define LSb32FCTX_RV9_equalpred 12 |
| #define LSb16FCTX_RV9_equalpred 12 |
| #define bFCTX_RV9_equalpred 1 |
| #define MSK32FCTX_RV9_equalpred 0x00001000 |
| |
| #define BA_FCTX_RV9_transform 0x0001 |
| #define B16FCTX_RV9_transform 0x0000 |
| #define LSb32FCTX_RV9_transform 13 |
| #define LSb16FCTX_RV9_transform 13 |
| #define bFCTX_RV9_transform 1 |
| #define MSK32FCTX_RV9_transform 0x00002000 |
| |
| #define BA_FCTX_RV9_NCBPY 0x0001 |
| #define B16FCTX_RV9_NCBPY 0x0000 |
| #define LSb32FCTX_RV9_NCBPY 14 |
| #define LSb16FCTX_RV9_NCBPY 14 |
| #define bFCTX_RV9_NCBPY 1 |
| #define MSK32FCTX_RV9_NCBPY 0x00004000 |
| |
| #define BA_FCTX_RV9_MixFLG 0x0001 |
| #define B16FCTX_RV9_MixFLG 0x0000 |
| #define LSb32FCTX_RV9_MixFLG 15 |
| #define LSb16FCTX_RV9_MixFLG 15 |
| #define bFCTX_RV9_MixFLG 1 |
| #define MSK32FCTX_RV9_MixFLG 0x00008000 |
| #define FCTX_RV9_MixFLG_8x8 0x1 |
| #define FCTX_RV9_MixFLG_16x16 0x1 |
| |
| #define BA_FCTX_RV9_CBPY 0x0002 |
| #define B16FCTX_RV9_CBPY 0x0002 |
| #define LSb32FCTX_RV9_CBPY 16 |
| #define LSb16FCTX_RV9_CBPY 0 |
| #define bFCTX_RV9_CBPY 1 |
| #define MSK32FCTX_RV9_CBPY 0x00010000 |
| |
| #define BA_FCTX_RV9_CBPU 0x0002 |
| #define B16FCTX_RV9_CBPU 0x0002 |
| #define LSb32FCTX_RV9_CBPU 17 |
| #define LSb16FCTX_RV9_CBPU 1 |
| #define bFCTX_RV9_CBPU 1 |
| #define MSK32FCTX_RV9_CBPU 0x00020000 |
| |
| #define BA_FCTX_RV9_CBPV 0x0002 |
| #define B16FCTX_RV9_CBPV 0x0002 |
| #define LSb32FCTX_RV9_CBPV 18 |
| #define LSb16FCTX_RV9_CBPV 2 |
| #define bFCTX_RV9_CBPV 1 |
| #define MSK32FCTX_RV9_CBPV 0x00040000 |
| |
| #define BA_FCTX_RV9_BsY 0x0002 |
| #define B16FCTX_RV9_BsY 0x0002 |
| #define LSb32FCTX_RV9_BsY 19 |
| #define LSb16FCTX_RV9_BsY 3 |
| #define bFCTX_RV9_BsY 2 |
| #define MSK32FCTX_RV9_BsY 0x00180000 |
| |
| #define BA_FCTX_RV9_BsU 0x0002 |
| #define B16FCTX_RV9_BsU 0x0002 |
| #define LSb32FCTX_RV9_BsU 21 |
| #define LSb16FCTX_RV9_BsU 5 |
| #define bFCTX_RV9_BsU 2 |
| #define MSK32FCTX_RV9_BsU 0x00600000 |
| |
| #define BA_FCTX_RV9_BsV 0x0002 |
| #define B16FCTX_RV9_BsV 0x0002 |
| #define LSb32FCTX_RV9_BsV 23 |
| #define LSb16FCTX_RV9_BsV 7 |
| #define bFCTX_RV9_BsV 2 |
| #define MSK32FCTX_RV9_BsV 0x01800000 |
| |
| #define BA_FCTX_RV9_Rsvd 0x0003 |
| #define B16FCTX_RV9_Rsvd 0x0002 |
| #define LSb32FCTX_RV9_Rsvd 25 |
| #define LSb16FCTX_RV9_Rsvd 9 |
| #define bFCTX_RV9_Rsvd 7 |
| #define MSK32FCTX_RV9_Rsvd 0xFE000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FCTX_RV9_mv 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FCTX_RV9 { |
| /////////////////////////////////////////////////////////// |
| #define GET32FCTX_RV9_rBID(r32) _BFGET_(r32, 5, 0) |
| #define SET32FCTX_RV9_rBID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16FCTX_RV9_rBID(r16) _BFGET_(r16, 5, 0) |
| #define SET16FCTX_RV9_rBID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32FCTX_RV9_rIDX(r32) _BFGET_(r32,10, 6) |
| #define SET32FCTX_RV9_rIDX(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16FCTX_RV9_rIDX(r16) _BFGET_(r16,10, 6) |
| #define SET16FCTX_RV9_rIDX(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32FCTX_RV9_FLD(r32) _BFGET_(r32,11,11) |
| #define SET32FCTX_RV9_FLD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16FCTX_RV9_FLD(r16) _BFGET_(r16,11,11) |
| #define SET16FCTX_RV9_FLD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32FCTX_RV9_equalpred(r32) _BFGET_(r32,12,12) |
| #define SET32FCTX_RV9_equalpred(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16FCTX_RV9_equalpred(r16) _BFGET_(r16,12,12) |
| #define SET16FCTX_RV9_equalpred(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32FCTX_RV9_transform(r32) _BFGET_(r32,13,13) |
| #define SET32FCTX_RV9_transform(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16FCTX_RV9_transform(r16) _BFGET_(r16,13,13) |
| #define SET16FCTX_RV9_transform(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32FCTX_RV9_NCBPY(r32) _BFGET_(r32,14,14) |
| #define SET32FCTX_RV9_NCBPY(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16FCTX_RV9_NCBPY(r16) _BFGET_(r16,14,14) |
| #define SET16FCTX_RV9_NCBPY(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32FCTX_RV9_MixFLG(r32) _BFGET_(r32,15,15) |
| #define SET32FCTX_RV9_MixFLG(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16FCTX_RV9_MixFLG(r16) _BFGET_(r16,15,15) |
| #define SET16FCTX_RV9_MixFLG(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32FCTX_RV9_CBPY(r32) _BFGET_(r32,16,16) |
| #define SET32FCTX_RV9_CBPY(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16FCTX_RV9_CBPY(r16) _BFGET_(r16, 0, 0) |
| #define SET16FCTX_RV9_CBPY(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32FCTX_RV9_CBPU(r32) _BFGET_(r32,17,17) |
| #define SET32FCTX_RV9_CBPU(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16FCTX_RV9_CBPU(r16) _BFGET_(r16, 1, 1) |
| #define SET16FCTX_RV9_CBPU(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32FCTX_RV9_CBPV(r32) _BFGET_(r32,18,18) |
| #define SET32FCTX_RV9_CBPV(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16FCTX_RV9_CBPV(r16) _BFGET_(r16, 2, 2) |
| #define SET16FCTX_RV9_CBPV(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32FCTX_RV9_BsY(r32) _BFGET_(r32,20,19) |
| #define SET32FCTX_RV9_BsY(r32,v) _BFSET_(r32,20,19,v) |
| #define GET16FCTX_RV9_BsY(r16) _BFGET_(r16, 4, 3) |
| #define SET16FCTX_RV9_BsY(r16,v) _BFSET_(r16, 4, 3,v) |
| |
| #define GET32FCTX_RV9_BsU(r32) _BFGET_(r32,22,21) |
| #define SET32FCTX_RV9_BsU(r32,v) _BFSET_(r32,22,21,v) |
| #define GET16FCTX_RV9_BsU(r16) _BFGET_(r16, 6, 5) |
| #define SET16FCTX_RV9_BsU(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32FCTX_RV9_BsV(r32) _BFGET_(r32,24,23) |
| #define SET32FCTX_RV9_BsV(r32,v) _BFSET_(r32,24,23,v) |
| #define GET16FCTX_RV9_BsV(r16) _BFGET_(r16, 8, 7) |
| #define SET16FCTX_RV9_BsV(r16,v) _BFSET_(r16, 8, 7,v) |
| |
| #define GET32FCTX_RV9_Rsvd(r32) _BFGET_(r32,31,25) |
| #define SET32FCTX_RV9_Rsvd(r32,v) _BFSET_(r32,31,25,v) |
| #define GET16FCTX_RV9_Rsvd(r16) _BFGET_(r16,15, 9) |
| #define SET16FCTX_RV9_Rsvd(r16,v) _BFSET_(r16,15, 9,v) |
| |
| UNSG32 u_rBID : 6; |
| UNSG32 u_rIDX : 5; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_equalpred : 1; |
| UNSG32 u_transform : 1; |
| UNSG32 u_NCBPY : 1; |
| UNSG32 u_MixFLG : 1; |
| UNSG32 u_CBPY : 1; |
| UNSG32 u_CBPU : 1; |
| UNSG32 u_CBPV : 1; |
| UNSG32 u_BsY : 2; |
| UNSG32 u_BsU : 2; |
| UNSG32 u_BsV : 2; |
| UNSG32 u_Rsvd : 7; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_mv; |
| /////////////////////////////////////////////////////////// |
| } SIE_FCTX_RV9; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FCTX_RV9_drvrd(SIE_FCTX_RV9 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FCTX_RV9_drvwr(SIE_FCTX_RV9 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FCTX_RV9_reset(SIE_FCTX_RV9 *p); |
| SIGN32 FCTX_RV9_cmp (SIE_FCTX_RV9 *p, SIE_FCTX_RV9 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FCTX_RV9_check(p,pie,pfx,hLOG) FCTX_RV9_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FCTX_RV9_print(p, pfx,hLOG) FCTX_RV9_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FCTX_RV9 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BCTX biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 rBID |
| /// %unsigned 5 rIDX |
| /// %unsigned 1 FLD |
| /// %unsigned 1 equalpred |
| /// ### |
| /// * BLK property for CABAC only: |
| /// * Using block category ACV, |
| /// * (Only at 4th 4x4 in each 8x8s): |
| /// * = !Intra && !skipped && (bi-pred || back-pred) |
| /// * NOTE: = 0 for direct mode |
| /// ### |
| /// %unsigned 3 RSVD |
| /// ### |
| /// * Reserved |
| /// ### |
| /// %unsigned 3 dctSel |
| /// : 8x8 0x0 |
| /// : 8x4 0x1 |
| /// : 4x8 0x2 |
| /// : 4x4 0x3 |
| /// ### |
| /// * VC-1 use only |
| /// ### |
| /// %unsigned 6 ABSMVDX |
| /// %unsigned 7 ABSMVDY |
| /// @ 0x00004 (P) |
| /// # 0x00004 mv |
| /// $MV mv REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BCTX |
| #define h_BCTX (){} |
| |
| #define BA_BCTX_rBID 0x0000 |
| #define B16BCTX_rBID 0x0000 |
| #define LSb32BCTX_rBID 0 |
| #define LSb16BCTX_rBID 0 |
| #define bBCTX_rBID 6 |
| #define MSK32BCTX_rBID 0x0000003F |
| |
| #define BA_BCTX_rIDX 0x0000 |
| #define B16BCTX_rIDX 0x0000 |
| #define LSb32BCTX_rIDX 6 |
| #define LSb16BCTX_rIDX 6 |
| #define bBCTX_rIDX 5 |
| #define MSK32BCTX_rIDX 0x000007C0 |
| |
| #define BA_BCTX_FLD 0x0001 |
| #define B16BCTX_FLD 0x0000 |
| #define LSb32BCTX_FLD 11 |
| #define LSb16BCTX_FLD 11 |
| #define bBCTX_FLD 1 |
| #define MSK32BCTX_FLD 0x00000800 |
| |
| #define BA_BCTX_equalpred 0x0001 |
| #define B16BCTX_equalpred 0x0000 |
| #define LSb32BCTX_equalpred 12 |
| #define LSb16BCTX_equalpred 12 |
| #define bBCTX_equalpred 1 |
| #define MSK32BCTX_equalpred 0x00001000 |
| |
| #define BA_BCTX_RSVD 0x0001 |
| #define B16BCTX_RSVD 0x0000 |
| #define LSb32BCTX_RSVD 13 |
| #define LSb16BCTX_RSVD 13 |
| #define bBCTX_RSVD 3 |
| #define MSK32BCTX_RSVD 0x0000E000 |
| |
| #define BA_BCTX_dctSel 0x0002 |
| #define B16BCTX_dctSel 0x0002 |
| #define LSb32BCTX_dctSel 16 |
| #define LSb16BCTX_dctSel 0 |
| #define bBCTX_dctSel 3 |
| #define MSK32BCTX_dctSel 0x00070000 |
| #define BCTX_dctSel_8x8 0x0 |
| #define BCTX_dctSel_8x4 0x1 |
| #define BCTX_dctSel_4x8 0x2 |
| #define BCTX_dctSel_4x4 0x3 |
| |
| #define BA_BCTX_ABSMVDX 0x0002 |
| #define B16BCTX_ABSMVDX 0x0002 |
| #define LSb32BCTX_ABSMVDX 19 |
| #define LSb16BCTX_ABSMVDX 3 |
| #define bBCTX_ABSMVDX 6 |
| #define MSK32BCTX_ABSMVDX 0x01F80000 |
| |
| #define BA_BCTX_ABSMVDY 0x0003 |
| #define B16BCTX_ABSMVDY 0x0002 |
| #define LSb32BCTX_ABSMVDY 25 |
| #define LSb16BCTX_ABSMVDY 9 |
| #define bBCTX_ABSMVDY 7 |
| #define MSK32BCTX_ABSMVDY 0xFE000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_BCTX_mv 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BCTX { |
| /////////////////////////////////////////////////////////// |
| #define GET32BCTX_rBID(r32) _BFGET_(r32, 5, 0) |
| #define SET32BCTX_rBID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16BCTX_rBID(r16) _BFGET_(r16, 5, 0) |
| #define SET16BCTX_rBID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32BCTX_rIDX(r32) _BFGET_(r32,10, 6) |
| #define SET32BCTX_rIDX(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16BCTX_rIDX(r16) _BFGET_(r16,10, 6) |
| #define SET16BCTX_rIDX(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32BCTX_FLD(r32) _BFGET_(r32,11,11) |
| #define SET32BCTX_FLD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16BCTX_FLD(r16) _BFGET_(r16,11,11) |
| #define SET16BCTX_FLD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32BCTX_equalpred(r32) _BFGET_(r32,12,12) |
| #define SET32BCTX_equalpred(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16BCTX_equalpred(r16) _BFGET_(r16,12,12) |
| #define SET16BCTX_equalpred(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32BCTX_RSVD(r32) _BFGET_(r32,15,13) |
| #define SET32BCTX_RSVD(r32,v) _BFSET_(r32,15,13,v) |
| #define GET16BCTX_RSVD(r16) _BFGET_(r16,15,13) |
| #define SET16BCTX_RSVD(r16,v) _BFSET_(r16,15,13,v) |
| |
| #define GET32BCTX_dctSel(r32) _BFGET_(r32,18,16) |
| #define SET32BCTX_dctSel(r32,v) _BFSET_(r32,18,16,v) |
| #define GET16BCTX_dctSel(r16) _BFGET_(r16, 2, 0) |
| #define SET16BCTX_dctSel(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32BCTX_ABSMVDX(r32) _BFGET_(r32,24,19) |
| #define SET32BCTX_ABSMVDX(r32,v) _BFSET_(r32,24,19,v) |
| #define GET16BCTX_ABSMVDX(r16) _BFGET_(r16, 8, 3) |
| #define SET16BCTX_ABSMVDX(r16,v) _BFSET_(r16, 8, 3,v) |
| |
| #define GET32BCTX_ABSMVDY(r32) _BFGET_(r32,31,25) |
| #define SET32BCTX_ABSMVDY(r32,v) _BFSET_(r32,31,25,v) |
| #define GET16BCTX_ABSMVDY(r16) _BFGET_(r16,15, 9) |
| #define SET16BCTX_ABSMVDY(r16,v) _BFSET_(r16,15, 9,v) |
| |
| UNSG32 u_rBID : 6; |
| UNSG32 u_rIDX : 5; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_equalpred : 1; |
| UNSG32 u_RSVD : 3; |
| UNSG32 u_dctSel : 3; |
| UNSG32 u_ABSMVDX : 6; |
| UNSG32 u_ABSMVDY : 7; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_mv; |
| /////////////////////////////////////////////////////////// |
| } SIE_BCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BCTX_drvrd(SIE_BCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BCTX_drvwr(SIE_BCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BCTX_reset(SIE_BCTX *p); |
| SIGN32 BCTX_cmp (SIE_BCTX *p, SIE_BCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BCTX_check(p,pie,pfx,hLOG) BCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BCTX_print(p, pfx,hLOG) BCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BCTX_VC1 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 rBID |
| /// %unsigned 5 rIDX |
| /// %unsigned 1 FLD |
| /// %unsigned 1 equalpred |
| /// ### |
| /// * BLK property for CABAC only: |
| /// * Using block category ACV, |
| /// * (Only at 4th 4x4 in each 8x8s): |
| /// * = !Intra && !skipped && (bi-pred || back-pred) |
| /// * NOTE: = 0 for direct mode |
| /// ### |
| /// %unsigned 3 RSVD |
| /// ### |
| /// * Reserved |
| /// ### |
| /// %unsigned 2 dctSelU |
| /// ### |
| /// * DCT transform type for U; used for VC-1 Fop |
| /// ### |
| /// %unsigned 2 dctSelV |
| /// ### |
| /// * DCT transform type for V; used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 CBFU |
| /// ### |
| /// * coded block (4x4) flag for U; used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 CBFV |
| /// ### |
| /// * coded block (4x4) flag for V; used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 CBFU8x8 |
| /// ### |
| /// * coded block (8x8) flag for U, used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 CBFV8x8 |
| /// ### |
| /// * coded block (8x8) flag for V, used for VC-1 Fop |
| /// ### |
| /// %unsigned 8 RSVD8 |
| /// @ 0x00004 (P) |
| /// # 0x00004 mv |
| /// $MV mv REG |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BCTX_VC1 |
| #define h_BCTX_VC1 (){} |
| |
| #define BA_BCTX_VC1_rBID 0x0000 |
| #define B16BCTX_VC1_rBID 0x0000 |
| #define LSb32BCTX_VC1_rBID 0 |
| #define LSb16BCTX_VC1_rBID 0 |
| #define bBCTX_VC1_rBID 6 |
| #define MSK32BCTX_VC1_rBID 0x0000003F |
| |
| #define BA_BCTX_VC1_rIDX 0x0000 |
| #define B16BCTX_VC1_rIDX 0x0000 |
| #define LSb32BCTX_VC1_rIDX 6 |
| #define LSb16BCTX_VC1_rIDX 6 |
| #define bBCTX_VC1_rIDX 5 |
| #define MSK32BCTX_VC1_rIDX 0x000007C0 |
| |
| #define BA_BCTX_VC1_FLD 0x0001 |
| #define B16BCTX_VC1_FLD 0x0000 |
| #define LSb32BCTX_VC1_FLD 11 |
| #define LSb16BCTX_VC1_FLD 11 |
| #define bBCTX_VC1_FLD 1 |
| #define MSK32BCTX_VC1_FLD 0x00000800 |
| |
| #define BA_BCTX_VC1_equalpred 0x0001 |
| #define B16BCTX_VC1_equalpred 0x0000 |
| #define LSb32BCTX_VC1_equalpred 12 |
| #define LSb16BCTX_VC1_equalpred 12 |
| #define bBCTX_VC1_equalpred 1 |
| #define MSK32BCTX_VC1_equalpred 0x00001000 |
| |
| #define BA_BCTX_VC1_RSVD 0x0001 |
| #define B16BCTX_VC1_RSVD 0x0000 |
| #define LSb32BCTX_VC1_RSVD 13 |
| #define LSb16BCTX_VC1_RSVD 13 |
| #define bBCTX_VC1_RSVD 3 |
| #define MSK32BCTX_VC1_RSVD 0x0000E000 |
| |
| #define BA_BCTX_VC1_dctSelU 0x0002 |
| #define B16BCTX_VC1_dctSelU 0x0002 |
| #define LSb32BCTX_VC1_dctSelU 16 |
| #define LSb16BCTX_VC1_dctSelU 0 |
| #define bBCTX_VC1_dctSelU 2 |
| #define MSK32BCTX_VC1_dctSelU 0x00030000 |
| |
| #define BA_BCTX_VC1_dctSelV 0x0002 |
| #define B16BCTX_VC1_dctSelV 0x0002 |
| #define LSb32BCTX_VC1_dctSelV 18 |
| #define LSb16BCTX_VC1_dctSelV 2 |
| #define bBCTX_VC1_dctSelV 2 |
| #define MSK32BCTX_VC1_dctSelV 0x000C0000 |
| |
| #define BA_BCTX_VC1_CBFU 0x0002 |
| #define B16BCTX_VC1_CBFU 0x0002 |
| #define LSb32BCTX_VC1_CBFU 20 |
| #define LSb16BCTX_VC1_CBFU 4 |
| #define bBCTX_VC1_CBFU 1 |
| #define MSK32BCTX_VC1_CBFU 0x00100000 |
| |
| #define BA_BCTX_VC1_CBFV 0x0002 |
| #define B16BCTX_VC1_CBFV 0x0002 |
| #define LSb32BCTX_VC1_CBFV 21 |
| #define LSb16BCTX_VC1_CBFV 5 |
| #define bBCTX_VC1_CBFV 1 |
| #define MSK32BCTX_VC1_CBFV 0x00200000 |
| |
| #define BA_BCTX_VC1_CBFU8x8 0x0002 |
| #define B16BCTX_VC1_CBFU8x8 0x0002 |
| #define LSb32BCTX_VC1_CBFU8x8 22 |
| #define LSb16BCTX_VC1_CBFU8x8 6 |
| #define bBCTX_VC1_CBFU8x8 1 |
| #define MSK32BCTX_VC1_CBFU8x8 0x00400000 |
| |
| #define BA_BCTX_VC1_CBFV8x8 0x0002 |
| #define B16BCTX_VC1_CBFV8x8 0x0002 |
| #define LSb32BCTX_VC1_CBFV8x8 23 |
| #define LSb16BCTX_VC1_CBFV8x8 7 |
| #define bBCTX_VC1_CBFV8x8 1 |
| #define MSK32BCTX_VC1_CBFV8x8 0x00800000 |
| |
| #define BA_BCTX_VC1_RSVD8 0x0003 |
| #define B16BCTX_VC1_RSVD8 0x0002 |
| #define LSb32BCTX_VC1_RSVD8 24 |
| #define LSb16BCTX_VC1_RSVD8 8 |
| #define bBCTX_VC1_RSVD8 8 |
| #define MSK32BCTX_VC1_RSVD8 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_BCTX_VC1_mv 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BCTX_VC1 { |
| /////////////////////////////////////////////////////////// |
| #define GET32BCTX_VC1_rBID(r32) _BFGET_(r32, 5, 0) |
| #define SET32BCTX_VC1_rBID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16BCTX_VC1_rBID(r16) _BFGET_(r16, 5, 0) |
| #define SET16BCTX_VC1_rBID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32BCTX_VC1_rIDX(r32) _BFGET_(r32,10, 6) |
| #define SET32BCTX_VC1_rIDX(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16BCTX_VC1_rIDX(r16) _BFGET_(r16,10, 6) |
| #define SET16BCTX_VC1_rIDX(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32BCTX_VC1_FLD(r32) _BFGET_(r32,11,11) |
| #define SET32BCTX_VC1_FLD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16BCTX_VC1_FLD(r16) _BFGET_(r16,11,11) |
| #define SET16BCTX_VC1_FLD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32BCTX_VC1_equalpred(r32) _BFGET_(r32,12,12) |
| #define SET32BCTX_VC1_equalpred(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16BCTX_VC1_equalpred(r16) _BFGET_(r16,12,12) |
| #define SET16BCTX_VC1_equalpred(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32BCTX_VC1_RSVD(r32) _BFGET_(r32,15,13) |
| #define SET32BCTX_VC1_RSVD(r32,v) _BFSET_(r32,15,13,v) |
| #define GET16BCTX_VC1_RSVD(r16) _BFGET_(r16,15,13) |
| #define SET16BCTX_VC1_RSVD(r16,v) _BFSET_(r16,15,13,v) |
| |
| #define GET32BCTX_VC1_dctSelU(r32) _BFGET_(r32,17,16) |
| #define SET32BCTX_VC1_dctSelU(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16BCTX_VC1_dctSelU(r16) _BFGET_(r16, 1, 0) |
| #define SET16BCTX_VC1_dctSelU(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32BCTX_VC1_dctSelV(r32) _BFGET_(r32,19,18) |
| #define SET32BCTX_VC1_dctSelV(r32,v) _BFSET_(r32,19,18,v) |
| #define GET16BCTX_VC1_dctSelV(r16) _BFGET_(r16, 3, 2) |
| #define SET16BCTX_VC1_dctSelV(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32BCTX_VC1_CBFU(r32) _BFGET_(r32,20,20) |
| #define SET32BCTX_VC1_CBFU(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16BCTX_VC1_CBFU(r16) _BFGET_(r16, 4, 4) |
| #define SET16BCTX_VC1_CBFU(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32BCTX_VC1_CBFV(r32) _BFGET_(r32,21,21) |
| #define SET32BCTX_VC1_CBFV(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16BCTX_VC1_CBFV(r16) _BFGET_(r16, 5, 5) |
| #define SET16BCTX_VC1_CBFV(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32BCTX_VC1_CBFU8x8(r32) _BFGET_(r32,22,22) |
| #define SET32BCTX_VC1_CBFU8x8(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16BCTX_VC1_CBFU8x8(r16) _BFGET_(r16, 6, 6) |
| #define SET16BCTX_VC1_CBFU8x8(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32BCTX_VC1_CBFV8x8(r32) _BFGET_(r32,23,23) |
| #define SET32BCTX_VC1_CBFV8x8(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16BCTX_VC1_CBFV8x8(r16) _BFGET_(r16, 7, 7) |
| #define SET16BCTX_VC1_CBFV8x8(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32BCTX_VC1_RSVD8(r32) _BFGET_(r32,31,24) |
| #define SET32BCTX_VC1_RSVD8(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16BCTX_VC1_RSVD8(r16) _BFGET_(r16,15, 8) |
| #define SET16BCTX_VC1_RSVD8(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_rBID : 6; |
| UNSG32 u_rIDX : 5; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_equalpred : 1; |
| UNSG32 u_RSVD : 3; |
| UNSG32 u_dctSelU : 2; |
| UNSG32 u_dctSelV : 2; |
| UNSG32 u_CBFU : 1; |
| UNSG32 u_CBFV : 1; |
| UNSG32 u_CBFU8x8 : 1; |
| UNSG32 u_CBFV8x8 : 1; |
| UNSG32 u_RSVD8 : 8; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_mv; |
| /////////////////////////////////////////////////////////// |
| } SIE_BCTX_VC1; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BCTX_VC1_drvrd(SIE_BCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BCTX_VC1_drvwr(SIE_BCTX_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BCTX_VC1_reset(SIE_BCTX_VC1 *p); |
| SIGN32 BCTX_VC1_cmp (SIE_BCTX_VC1 *p, SIE_BCTX_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BCTX_VC1_check(p,pie,pfx,hLOG) BCTX_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BCTX_VC1_print(p, pfx,hLOG) BCTX_VC1_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BCTX_VC1 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FCTXI biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 22 RSVD |
| /// %unsigned 5 NCUV |
| /// ### |
| /// * CAVLC use only: |
| /// * Using block category ACU/ACV: 0~15 |
| /// ### |
| /// %unsigned 5 NCY |
| /// ### |
| /// * CAVLC use only: |
| /// * Using block category ACY (every 4x4s): 0~16 |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 20 RSVD20 |
| /// %unsigned 4 intraChroma |
| /// ### |
| /// * For encoder: Intra prediction mode for chormablocks, see IntraChroma.mode above. Only appears in DCI, one per MB. |
| /// ### |
| /// %unsigned 8 intraLuma |
| /// ### |
| /// * Intra 16x16/NxN prediction mode for luma blocks, see IntraLuma.mode above |
| /// * =0 between parser & syntax processor |
| /// * End of FCTXI |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FCTXI |
| #define h_FCTXI (){} |
| |
| #define BA_FCTXI_RSVD 0x0000 |
| #define B16FCTXI_RSVD 0x0000 |
| #define LSb32FCTXI_RSVD 0 |
| #define LSb16FCTXI_RSVD 0 |
| #define bFCTXI_RSVD 22 |
| #define MSK32FCTXI_RSVD 0x003FFFFF |
| |
| #define BA_FCTXI_NCUV 0x0002 |
| #define B16FCTXI_NCUV 0x0002 |
| #define LSb32FCTXI_NCUV 22 |
| #define LSb16FCTXI_NCUV 6 |
| #define bFCTXI_NCUV 5 |
| #define MSK32FCTXI_NCUV 0x07C00000 |
| |
| #define BA_FCTXI_NCY 0x0003 |
| #define B16FCTXI_NCY 0x0002 |
| #define LSb32FCTXI_NCY 27 |
| #define LSb16FCTXI_NCY 11 |
| #define bFCTXI_NCY 5 |
| #define MSK32FCTXI_NCY 0xF8000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_FCTXI_RSVD20 0x0004 |
| #define B16FCTXI_RSVD20 0x0004 |
| #define LSb32FCTXI_RSVD20 0 |
| #define LSb16FCTXI_RSVD20 0 |
| #define bFCTXI_RSVD20 20 |
| #define MSK32FCTXI_RSVD20 0x000FFFFF |
| |
| #define BA_FCTXI_intraChroma 0x0006 |
| #define B16FCTXI_intraChroma 0x0006 |
| #define LSb32FCTXI_intraChroma 20 |
| #define LSb16FCTXI_intraChroma 4 |
| #define bFCTXI_intraChroma 4 |
| #define MSK32FCTXI_intraChroma 0x00F00000 |
| |
| #define BA_FCTXI_intraLuma 0x0007 |
| #define B16FCTXI_intraLuma 0x0006 |
| #define LSb32FCTXI_intraLuma 24 |
| #define LSb16FCTXI_intraLuma 8 |
| #define bFCTXI_intraLuma 8 |
| #define MSK32FCTXI_intraLuma 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FCTXI { |
| /////////////////////////////////////////////////////////// |
| #define GET32FCTXI_RSVD(r32) _BFGET_(r32,21, 0) |
| #define SET32FCTXI_RSVD(r32,v) _BFSET_(r32,21, 0,v) |
| |
| #define GET32FCTXI_NCUV(r32) _BFGET_(r32,26,22) |
| #define SET32FCTXI_NCUV(r32,v) _BFSET_(r32,26,22,v) |
| #define GET16FCTXI_NCUV(r16) _BFGET_(r16,10, 6) |
| #define SET16FCTXI_NCUV(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32FCTXI_NCY(r32) _BFGET_(r32,31,27) |
| #define SET32FCTXI_NCY(r32,v) _BFSET_(r32,31,27,v) |
| #define GET16FCTXI_NCY(r16) _BFGET_(r16,15,11) |
| #define SET16FCTXI_NCY(r16,v) _BFSET_(r16,15,11,v) |
| |
| UNSG32 u_RSVD : 22; |
| UNSG32 u_NCUV : 5; |
| UNSG32 u_NCY : 5; |
| /////////////////////////////////////////////////////////// |
| #define GET32FCTXI_RSVD20(r32) _BFGET_(r32,19, 0) |
| #define SET32FCTXI_RSVD20(r32,v) _BFSET_(r32,19, 0,v) |
| |
| #define GET32FCTXI_intraChroma(r32) _BFGET_(r32,23,20) |
| #define SET32FCTXI_intraChroma(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16FCTXI_intraChroma(r16) _BFGET_(r16, 7, 4) |
| #define SET16FCTXI_intraChroma(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32FCTXI_intraLuma(r32) _BFGET_(r32,31,24) |
| #define SET32FCTXI_intraLuma(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16FCTXI_intraLuma(r16) _BFGET_(r16,15, 8) |
| #define SET16FCTXI_intraLuma(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_RSVD20 : 20; |
| UNSG32 u_intraChroma : 4; |
| UNSG32 u_intraLuma : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_FCTXI; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FCTXI_drvrd(SIE_FCTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FCTXI_drvwr(SIE_FCTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FCTXI_reset(SIE_FCTXI *p); |
| SIGN32 FCTXI_cmp (SIE_FCTXI *p, SIE_FCTXI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FCTXI_check(p,pie,pfx,hLOG) FCTXI_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FCTXI_print(p, pfx,hLOG) FCTXI_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FCTXI |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE HCTX4x4 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 fore |
| /// $FCTX fore REG |
| /// ### |
| /// * Forward prediction |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 back |
| /// $BCTX back REG |
| /// ### |
| /// * Backward prediction |
| /// * End of HCTX4x4 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_HCTX4x4 |
| #define h_HCTX4x4 (){} |
| |
| #define RA_HCTX4x4_fore 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_HCTX4x4_back 0x0008 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_HCTX4x4 { |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_fore; |
| /////////////////////////////////////////////////////////// |
| SIE_BCTX ie_back; |
| /////////////////////////////////////////////////////////// |
| } SIE_HCTX4x4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 HCTX4x4_drvrd(SIE_HCTX4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 HCTX4x4_drvwr(SIE_HCTX4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void HCTX4x4_reset(SIE_HCTX4x4 *p); |
| SIGN32 HCTX4x4_cmp (SIE_HCTX4x4 *p, SIE_HCTX4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define HCTX4x4_check(p,pie,pfx,hLOG) HCTX4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define HCTX4x4_print(p, pfx,hLOG) HCTX4x4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: HCTX4x4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CTXI biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %signed 16 AC0 |
| /// ### |
| /// * DC or horizontal/vertical AC coefficient |
| /// ### |
| /// %signed 13 AC1 |
| /// ### |
| /// * 2nd horizontal/vertical AC coefficient |
| /// ### |
| /// %unsigned 1 cbpcy |
| /// ### |
| /// * Flatten all 4x4s in a 8x8 block, coded or not |
| /// ### |
| /// %unsigned 2 mquantL |
| /// ### |
| /// * Low 2 bits of mquant, flatten all 4x4s in a macroblock |
| /// ### |
| /// %unsigned 3 mquantH |
| /// ### |
| /// * High 3 bits of mquant, flatten all 4x4s in a macroblock |
| /// ### |
| /// %signed 13 AC2 |
| /// ### |
| /// * 3rd horizontal/vertical AC coefficient |
| /// ### |
| /// %unsigned 3 type |
| /// ### |
| /// * Sub-set of mb_type, see MBPROP.type above |
| /// * = intra16x16 |
| /// ### |
| /// %signed 13 AC3 |
| /// ### |
| /// * 4th horizontal/vertical AC coefficient |
| /// * End of CTXI |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CTXI |
| #define h_CTXI (){} |
| |
| #define BA_CTXI_AC0 0x0000 |
| #define B16CTXI_AC0 0x0000 |
| #define LSb32CTXI_AC0 0 |
| #define LSb16CTXI_AC0 0 |
| #define bCTXI_AC0 16 |
| #define MSK32CTXI_AC0 0x0000FFFF |
| |
| #define BA_CTXI_AC1 0x0002 |
| #define B16CTXI_AC1 0x0002 |
| #define LSb32CTXI_AC1 16 |
| #define LSb16CTXI_AC1 0 |
| #define bCTXI_AC1 13 |
| #define MSK32CTXI_AC1 0x1FFF0000 |
| |
| #define BA_CTXI_cbpcy 0x0003 |
| #define B16CTXI_cbpcy 0x0002 |
| #define LSb32CTXI_cbpcy 29 |
| #define LSb16CTXI_cbpcy 13 |
| #define bCTXI_cbpcy 1 |
| #define MSK32CTXI_cbpcy 0x20000000 |
| |
| #define BA_CTXI_mquantL 0x0003 |
| #define B16CTXI_mquantL 0x0002 |
| #define LSb32CTXI_mquantL 30 |
| #define LSb16CTXI_mquantL 14 |
| #define bCTXI_mquantL 2 |
| #define MSK32CTXI_mquantL 0xC0000000 |
| |
| #define BA_CTXI_mquantH 0x0004 |
| #define B16CTXI_mquantH 0x0004 |
| #define LSb32CTXI_mquantH 0 |
| #define LSb16CTXI_mquantH 0 |
| #define bCTXI_mquantH 3 |
| #define MSK32CTXI_mquantH 0x00000007 |
| |
| #define BA_CTXI_AC2 0x0004 |
| #define B16CTXI_AC2 0x0004 |
| #define LSb32CTXI_AC2 3 |
| #define LSb16CTXI_AC2 3 |
| #define bCTXI_AC2 13 |
| #define MSK32CTXI_AC2 0x0000FFF8 |
| |
| #define BA_CTXI_type 0x0006 |
| #define B16CTXI_type 0x0006 |
| #define LSb32CTXI_type 16 |
| #define LSb16CTXI_type 0 |
| #define bCTXI_type 3 |
| #define MSK32CTXI_type 0x00070000 |
| |
| #define BA_CTXI_AC3 0x0006 |
| #define B16CTXI_AC3 0x0006 |
| #define LSb32CTXI_AC3 19 |
| #define LSb16CTXI_AC3 3 |
| #define bCTXI_AC3 13 |
| #define MSK32CTXI_AC3 0xFFF80000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CTXI { |
| /////////////////////////////////////////////////////////// |
| #define GET32CTXI_AC0(r32) _BFGET_(r32,15, 0) |
| #define SET32CTXI_AC0(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16CTXI_AC0(r16) _BFGET_(r16,15, 0) |
| #define SET16CTXI_AC0(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32CTXI_AC1(r32) _BFGET_(r32,28,16) |
| #define SET32CTXI_AC1(r32,v) _BFSET_(r32,28,16,v) |
| #define GET16CTXI_AC1(r16) _BFGET_(r16,12, 0) |
| #define SET16CTXI_AC1(r16,v) _BFSET_(r16,12, 0,v) |
| |
| #define GET32CTXI_cbpcy(r32) _BFGET_(r32,29,29) |
| #define SET32CTXI_cbpcy(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16CTXI_cbpcy(r16) _BFGET_(r16,13,13) |
| #define SET16CTXI_cbpcy(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32CTXI_mquantL(r32) _BFGET_(r32,31,30) |
| #define SET32CTXI_mquantL(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16CTXI_mquantL(r16) _BFGET_(r16,15,14) |
| #define SET16CTXI_mquantL(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 s_AC0 : 16; |
| UNSG32 s_AC1 : 13; |
| UNSG32 u_cbpcy : 1; |
| UNSG32 u_mquantL : 2; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32CTXI_mquantH(r32) _BFGET_(r32, 2, 0) |
| #define SET32CTXI_mquantH(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16CTXI_mquantH(r16) _BFGET_(r16, 2, 0) |
| #define SET16CTXI_mquantH(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32CTXI_AC2(r32) _BFGET_(r32,15, 3) |
| #define SET32CTXI_AC2(r32,v) _BFSET_(r32,15, 3,v) |
| #define GET16CTXI_AC2(r16) _BFGET_(r16,15, 3) |
| #define SET16CTXI_AC2(r16,v) _BFSET_(r16,15, 3,v) |
| |
| #define GET32CTXI_type(r32) _BFGET_(r32,18,16) |
| #define SET32CTXI_type(r32,v) _BFSET_(r32,18,16,v) |
| #define GET16CTXI_type(r16) _BFGET_(r16, 2, 0) |
| #define SET16CTXI_type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32CTXI_AC3(r32) _BFGET_(r32,31,19) |
| #define SET32CTXI_AC3(r32,v) _BFSET_(r32,31,19,v) |
| #define GET16CTXI_AC3(r16) _BFGET_(r16,15, 3) |
| #define SET16CTXI_AC3(r16,v) _BFSET_(r16,15, 3,v) |
| |
| UNSG32 u_mquantH : 3; |
| UNSG32 s_AC2 : 13; |
| UNSG32 u_type : 3; |
| UNSG32 s_AC3 : 13; |
| /////////////////////////////////////////////////////////// |
| } SIE_CTXI; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CTXI_drvrd(SIE_CTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CTXI_drvwr(SIE_CTXI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CTXI_reset(SIE_CTXI *p); |
| SIGN32 CTXI_cmp (SIE_CTXI *p, SIE_CTXI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CTXI_check(p,pie,pfx,hLOG) CTXI_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CTXI_print(p, pfx,hLOG) CTXI_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CTXI |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE CTXI4x4 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 luma |
| /// $CTXI luma REG |
| /// ### |
| /// * DC/AC for Y |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 chroma |
| /// $CTXI chroma REG |
| /// ### |
| /// * DC/AC for UV |
| /// * End of CTXI4x4 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_CTXI4x4 |
| #define h_CTXI4x4 (){} |
| |
| #define RA_CTXI4x4_luma 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_CTXI4x4_chroma 0x0008 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_CTXI4x4 { |
| /////////////////////////////////////////////////////////// |
| SIE_CTXI ie_luma; |
| /////////////////////////////////////////////////////////// |
| SIE_CTXI ie_chroma; |
| /////////////////////////////////////////////////////////// |
| } SIE_CTXI4x4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 CTXI4x4_drvrd(SIE_CTXI4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 CTXI4x4_drvwr(SIE_CTXI4x4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void CTXI4x4_reset(SIE_CTXI4x4 *p); |
| SIGN32 CTXI4x4_cmp (SIE_CTXI4x4 *p, SIE_CTXI4x4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define CTXI4x4_check(p,pie,pfx,hLOG) CTXI4x4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define CTXI4x4_print(p, pfx,hLOG) CTXI4x4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: CTXI4x4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IDX2BID (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 frmIDX2BID |
| /// $LUT8b frmIDX2BID REG [16] |
| /// ### |
| /// * Cast to 8b rBID[32:rIDX][2:L0/L1] |
| /// * Note: field picture use this table (32 rIDX)! |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 topIDX2BID |
| /// $LUT8b topIDX2BID REG [16] |
| /// ### |
| /// * Cast to 8b rBID[32:rIDX][2:L0/L1] |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 btmIDX2BID |
| /// $LUT8b btmIDX2BID REG [16] |
| /// ### |
| /// * Cast to 8b rBID[32:rIDX][2:L0/L1] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 192B, bits: 1536b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IDX2BID |
| #define h_IDX2BID (){} |
| |
| #define RA_IDX2BID_frmIDX2BID 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_IDX2BID_topIDX2BID 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_IDX2BID_btmIDX2BID 0x0080 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IDX2BID { |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_frmIDX2BID[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_topIDX2BID[16]; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_btmIDX2BID[16]; |
| /////////////////////////////////////////////////////////// |
| } SIE_IDX2BID; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IDX2BID_drvrd(SIE_IDX2BID *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IDX2BID_drvwr(SIE_IDX2BID *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IDX2BID_reset(SIE_IDX2BID *p); |
| SIGN32 IDX2BID_cmp (SIE_IDX2BID *p, SIE_IDX2BID *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IDX2BID_check(p,pie,pfx,hLOG) IDX2BID_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IDX2BID_print(p, pfx,hLOG) IDX2BID_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IDX2BID |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BID2IDX (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 frmBID2IDX |
| /// $LUT8b frmBID2IDX REG [10] |
| /// ### |
| /// * Cast to 8b L0.min.rIDX[34:rBID] |
| /// * Note: field picture use this table (32 rIDX)! |
| /// ### |
| /// @ 0x00028 (P) |
| /// # 0x00028 topBID2IDX |
| /// $LUT8b topBID2IDX REG [10] |
| /// ### |
| /// * Cast to 8b L0.min.rIDX[34:rBID] |
| /// ### |
| /// @ 0x00050 (P) |
| /// # 0x00050 btmBID2IDX |
| /// $LUT8b btmBID2IDX REG [10] |
| /// ### |
| /// * Cast to 8b L0.min.rIDX[34:rBID] |
| /// * Note: direct mode corner case |
| /// * Alternative method (not used) if not adjust rIDX: |
| /// * rBID = CoL.rBID | (CoL.Frm & Cur.Btm) |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 120B, bits: 960b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BID2IDX |
| #define h_BID2IDX (){} |
| |
| #define RA_BID2IDX_frmBID2IDX 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_BID2IDX_topBID2IDX 0x0028 |
| /////////////////////////////////////////////////////////// |
| #define RA_BID2IDX_btmBID2IDX 0x0050 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BID2IDX { |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_frmBID2IDX[10]; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_topBID2IDX[10]; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT8b ie_btmBID2IDX[10]; |
| /////////////////////////////////////////////////////////// |
| } SIE_BID2IDX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BID2IDX_drvrd(SIE_BID2IDX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BID2IDX_drvwr(SIE_BID2IDX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BID2IDX_reset(SIE_BID2IDX *p); |
| SIGN32 BID2IDX_cmp (SIE_BID2IDX *p, SIE_BID2IDX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BID2IDX_check(p,pie,pfx,hLOG) BID2IDX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BID2IDX_print(p, pfx,hLOG) BID2IDX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BID2IDX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ASPSET biu (4,4) |
| /// ### |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 3 type |
| /// ### |
| /// * MB type |
| /// ### |
| /// %unsigned 2 chroma |
| /// ### |
| /// * Intra MB only: intra_chroma_pred |
| /// ### |
| /// %unsigned 1 t8x8 |
| /// ### |
| /// * 8x8 transform; used by AspInit & residual. |
| /// * End of ASPSET |
| /// ### |
| /// %% 26 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 6b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ASPSET |
| #define h_ASPSET (){} |
| |
| #define BA_ASPSET_type 0x0000 |
| #define B16ASPSET_type 0x0000 |
| #define LSb32ASPSET_type 0 |
| #define LSb16ASPSET_type 0 |
| #define bASPSET_type 3 |
| #define MSK32ASPSET_type 0x00000007 |
| |
| #define BA_ASPSET_chroma 0x0000 |
| #define B16ASPSET_chroma 0x0000 |
| #define LSb32ASPSET_chroma 3 |
| #define LSb16ASPSET_chroma 3 |
| #define bASPSET_chroma 2 |
| #define MSK32ASPSET_chroma 0x00000018 |
| |
| #define BA_ASPSET_t8x8 0x0000 |
| #define B16ASPSET_t8x8 0x0000 |
| #define LSb32ASPSET_t8x8 5 |
| #define LSb16ASPSET_t8x8 5 |
| #define bASPSET_t8x8 1 |
| #define MSK32ASPSET_t8x8 0x00000020 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ASPSET { |
| /////////////////////////////////////////////////////////// |
| #define GET32ASPSET_type(r32) _BFGET_(r32, 2, 0) |
| #define SET32ASPSET_type(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16ASPSET_type(r16) _BFGET_(r16, 2, 0) |
| #define SET16ASPSET_type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32ASPSET_chroma(r32) _BFGET_(r32, 4, 3) |
| #define SET32ASPSET_chroma(r32,v) _BFSET_(r32, 4, 3,v) |
| #define GET16ASPSET_chroma(r16) _BFGET_(r16, 4, 3) |
| #define SET16ASPSET_chroma(r16,v) _BFSET_(r16, 4, 3,v) |
| |
| #define GET32ASPSET_t8x8(r32) _BFGET_(r32, 5, 5) |
| #define SET32ASPSET_t8x8(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16ASPSET_t8x8(r16) _BFGET_(r16, 5, 5) |
| #define SET16ASPSET_t8x8(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| UNSG32 u_type : 3; |
| UNSG32 u_chroma : 2; |
| UNSG32 u_t8x8 : 1; |
| UNSG32 RSVDx0_b6 : 26; |
| /////////////////////////////////////////////////////////// |
| } SIE_ASPSET; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ASPSET_drvrd(SIE_ASPSET *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ASPSET_drvwr(SIE_ASPSET *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ASPSET_reset(SIE_ASPSET *p); |
| SIGN32 ASPSET_cmp (SIE_ASPSET *p, SIE_ASPSET *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ASPSET_check(p,pie,pfx,hLOG) ASPSET_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ASPSET_print(p, pfx,hLOG) ASPSET_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ASPSET |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE IntraPROP (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 3 type |
| /// ### |
| /// * See BLK.type above, |
| /// * LUT: IPCM or intraNxN or intra16x16 |
| /// ### |
| /// %unsigned 1 8x8IDX0 |
| /// ### |
| /// * LUT: 0 (P_8x8ref0) |
| /// ### |
| /// %unsigned 1 t8x8I |
| /// ### |
| /// * LUT: MB.transform8x8 & intraNxN |
| /// ### |
| /// %unsigned 1 t8x8PB |
| /// ### |
| /// * LUT: 0 |
| /// ### |
| /// %unsigned 2 luma16x16 |
| /// ### |
| /// * LUT: intra 16x16 prediction mode |
| /// ### |
| /// %unsigned 6 CBP |
| /// ### |
| /// * LUT: intra 16x16 coded block pattern |
| /// * MPEG4 LUT: Chroma cbp |
| /// * End of IntraPROP |
| /// ### |
| /// %% 18 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 14b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_IntraPROP |
| #define h_IntraPROP (){} |
| |
| #define BA_IntraPROP_type 0x0000 |
| #define B16IntraPROP_type 0x0000 |
| #define LSb32IntraPROP_type 0 |
| #define LSb16IntraPROP_type 0 |
| #define bIntraPROP_type 3 |
| #define MSK32IntraPROP_type 0x00000007 |
| |
| #define BA_IntraPROP_8x8IDX0 0x0000 |
| #define B16IntraPROP_8x8IDX0 0x0000 |
| #define LSb32IntraPROP_8x8IDX0 3 |
| #define LSb16IntraPROP_8x8IDX0 3 |
| #define bIntraPROP_8x8IDX0 1 |
| #define MSK32IntraPROP_8x8IDX0 0x00000008 |
| |
| #define BA_IntraPROP_t8x8I 0x0000 |
| #define B16IntraPROP_t8x8I 0x0000 |
| #define LSb32IntraPROP_t8x8I 4 |
| #define LSb16IntraPROP_t8x8I 4 |
| #define bIntraPROP_t8x8I 1 |
| #define MSK32IntraPROP_t8x8I 0x00000010 |
| |
| #define BA_IntraPROP_t8x8PB 0x0000 |
| #define B16IntraPROP_t8x8PB 0x0000 |
| #define LSb32IntraPROP_t8x8PB 5 |
| #define LSb16IntraPROP_t8x8PB 5 |
| #define bIntraPROP_t8x8PB 1 |
| #define MSK32IntraPROP_t8x8PB 0x00000020 |
| |
| #define BA_IntraPROP_luma16x16 0x0000 |
| #define B16IntraPROP_luma16x16 0x0000 |
| #define LSb32IntraPROP_luma16x16 6 |
| #define LSb16IntraPROP_luma16x16 6 |
| #define bIntraPROP_luma16x16 2 |
| #define MSK32IntraPROP_luma16x16 0x000000C0 |
| |
| #define BA_IntraPROP_CBP 0x0001 |
| #define B16IntraPROP_CBP 0x0000 |
| #define LSb32IntraPROP_CBP 8 |
| #define LSb16IntraPROP_CBP 8 |
| #define bIntraPROP_CBP 6 |
| #define MSK32IntraPROP_CBP 0x00003F00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_IntraPROP { |
| /////////////////////////////////////////////////////////// |
| #define GET32IntraPROP_type(r32) _BFGET_(r32, 2, 0) |
| #define SET32IntraPROP_type(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16IntraPROP_type(r16) _BFGET_(r16, 2, 0) |
| #define SET16IntraPROP_type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32IntraPROP_8x8IDX0(r32) _BFGET_(r32, 3, 3) |
| #define SET32IntraPROP_8x8IDX0(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16IntraPROP_8x8IDX0(r16) _BFGET_(r16, 3, 3) |
| #define SET16IntraPROP_8x8IDX0(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32IntraPROP_t8x8I(r32) _BFGET_(r32, 4, 4) |
| #define SET32IntraPROP_t8x8I(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16IntraPROP_t8x8I(r16) _BFGET_(r16, 4, 4) |
| #define SET16IntraPROP_t8x8I(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32IntraPROP_t8x8PB(r32) _BFGET_(r32, 5, 5) |
| #define SET32IntraPROP_t8x8PB(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16IntraPROP_t8x8PB(r16) _BFGET_(r16, 5, 5) |
| #define SET16IntraPROP_t8x8PB(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32IntraPROP_luma16x16(r32) _BFGET_(r32, 7, 6) |
| #define SET32IntraPROP_luma16x16(r32,v) _BFSET_(r32, 7, 6,v) |
| #define GET16IntraPROP_luma16x16(r16) _BFGET_(r16, 7, 6) |
| #define SET16IntraPROP_luma16x16(r16,v) _BFSET_(r16, 7, 6,v) |
| |
| #define GET32IntraPROP_CBP(r32) _BFGET_(r32,13, 8) |
| #define SET32IntraPROP_CBP(r32,v) _BFSET_(r32,13, 8,v) |
| #define GET16IntraPROP_CBP(r16) _BFGET_(r16,13, 8) |
| #define SET16IntraPROP_CBP(r16,v) _BFSET_(r16,13, 8,v) |
| |
| UNSG32 u_type : 3; |
| UNSG32 u_8x8IDX0 : 1; |
| UNSG32 u_t8x8I : 1; |
| UNSG32 u_t8x8PB : 1; |
| UNSG32 u_luma16x16 : 2; |
| UNSG32 u_CBP : 6; |
| UNSG32 RSVDx0_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| } SIE_IntraPROP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 IntraPROP_drvrd(SIE_IntraPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 IntraPROP_drvwr(SIE_IntraPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void IntraPROP_reset(SIE_IntraPROP *p); |
| SIGN32 IntraPROP_cmp (SIE_IntraPROP *p, SIE_IntraPROP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define IntraPROP_check(p,pie,pfx,hLOG) IntraPROP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define IntraPROP_print(p, pfx,hLOG) IntraPROP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: IntraPROP |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE InterPROP (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 3 type |
| /// ### |
| /// * See MBPROP.type above, |
| /// * LUT: inter or 8x8PB or 8x8IDX0 or direct16x16 |
| /// ### |
| /// %unsigned 1 8x8IDX0 |
| /// ### |
| /// * LUT: P_8x8ref0 |
| /// ### |
| /// %unsigned 1 t8x8I |
| /// ### |
| /// * LUT: 0 |
| /// ### |
| /// %unsigned 1 t8x8PB |
| /// ### |
| /// * LUT: MB.transform8x8 & inter & |
| /// * (MB.direct8x8 | !direct16x16) |
| /// ### |
| /// %unsigned 2 partition |
| /// ### |
| /// * See MBPROP.partition above |
| /// ### |
| /// %unsigned 2 motion_0i |
| /// %unsigned 2 motion_1i |
| /// ### |
| /// * LUT: intra/forward/backward/bi, see BLK.motion above |
| /// ### |
| /// %unsigned 2 mvs_0i |
| /// %unsigned 2 mvs_1i |
| /// ### |
| /// * Number of motion vectors for each directions |
| /// * End of InterPROP |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_InterPROP |
| #define h_InterPROP (){} |
| |
| #define BA_InterPROP_type 0x0000 |
| #define B16InterPROP_type 0x0000 |
| #define LSb32InterPROP_type 0 |
| #define LSb16InterPROP_type 0 |
| #define bInterPROP_type 3 |
| #define MSK32InterPROP_type 0x00000007 |
| |
| #define BA_InterPROP_8x8IDX0 0x0000 |
| #define B16InterPROP_8x8IDX0 0x0000 |
| #define LSb32InterPROP_8x8IDX0 3 |
| #define LSb16InterPROP_8x8IDX0 3 |
| #define bInterPROP_8x8IDX0 1 |
| #define MSK32InterPROP_8x8IDX0 0x00000008 |
| |
| #define BA_InterPROP_t8x8I 0x0000 |
| #define B16InterPROP_t8x8I 0x0000 |
| #define LSb32InterPROP_t8x8I 4 |
| #define LSb16InterPROP_t8x8I 4 |
| #define bInterPROP_t8x8I 1 |
| #define MSK32InterPROP_t8x8I 0x00000010 |
| |
| #define BA_InterPROP_t8x8PB 0x0000 |
| #define B16InterPROP_t8x8PB 0x0000 |
| #define LSb32InterPROP_t8x8PB 5 |
| #define LSb16InterPROP_t8x8PB 5 |
| #define bInterPROP_t8x8PB 1 |
| #define MSK32InterPROP_t8x8PB 0x00000020 |
| |
| #define BA_InterPROP_partition 0x0000 |
| #define B16InterPROP_partition 0x0000 |
| #define LSb32InterPROP_partition 6 |
| #define LSb16InterPROP_partition 6 |
| #define bInterPROP_partition 2 |
| #define MSK32InterPROP_partition 0x000000C0 |
| |
| #define BA_InterPROP_motion_0i 0x0001 |
| #define B16InterPROP_motion_0i 0x0000 |
| #define LSb32InterPROP_motion_0i 8 |
| #define LSb16InterPROP_motion_0i 8 |
| #define bInterPROP_motion_0i 2 |
| #define MSK32InterPROP_motion_0i 0x00000300 |
| |
| #define BA_InterPROP_motion_1i 0x0001 |
| #define B16InterPROP_motion_1i 0x0000 |
| #define LSb32InterPROP_motion_1i 10 |
| #define LSb16InterPROP_motion_1i 10 |
| #define bInterPROP_motion_1i 2 |
| #define MSK32InterPROP_motion_1i 0x00000C00 |
| |
| #define BA_InterPROP_mvs_0i 0x0001 |
| #define B16InterPROP_mvs_0i 0x0000 |
| #define LSb32InterPROP_mvs_0i 12 |
| #define LSb16InterPROP_mvs_0i 12 |
| #define bInterPROP_mvs_0i 2 |
| #define MSK32InterPROP_mvs_0i 0x00003000 |
| |
| #define BA_InterPROP_mvs_1i 0x0001 |
| #define B16InterPROP_mvs_1i 0x0000 |
| #define LSb32InterPROP_mvs_1i 14 |
| #define LSb16InterPROP_mvs_1i 14 |
| #define bInterPROP_mvs_1i 2 |
| #define MSK32InterPROP_mvs_1i 0x0000C000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_InterPROP { |
| /////////////////////////////////////////////////////////// |
| #define GET32InterPROP_type(r32) _BFGET_(r32, 2, 0) |
| #define SET32InterPROP_type(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16InterPROP_type(r16) _BFGET_(r16, 2, 0) |
| #define SET16InterPROP_type(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32InterPROP_8x8IDX0(r32) _BFGET_(r32, 3, 3) |
| #define SET32InterPROP_8x8IDX0(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16InterPROP_8x8IDX0(r16) _BFGET_(r16, 3, 3) |
| #define SET16InterPROP_8x8IDX0(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32InterPROP_t8x8I(r32) _BFGET_(r32, 4, 4) |
| #define SET32InterPROP_t8x8I(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16InterPROP_t8x8I(r16) _BFGET_(r16, 4, 4) |
| #define SET16InterPROP_t8x8I(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32InterPROP_t8x8PB(r32) _BFGET_(r32, 5, 5) |
| #define SET32InterPROP_t8x8PB(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16InterPROP_t8x8PB(r16) _BFGET_(r16, 5, 5) |
| #define SET16InterPROP_t8x8PB(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32InterPROP_partition(r32) _BFGET_(r32, 7, 6) |
| #define SET32InterPROP_partition(r32,v) _BFSET_(r32, 7, 6,v) |
| #define GET16InterPROP_partition(r16) _BFGET_(r16, 7, 6) |
| #define SET16InterPROP_partition(r16,v) _BFSET_(r16, 7, 6,v) |
| |
| #define GET32InterPROP_motion_0i(r32) _BFGET_(r32, 9, 8) |
| #define SET32InterPROP_motion_0i(r32,v) _BFSET_(r32, 9, 8,v) |
| #define GET16InterPROP_motion_0i(r16) _BFGET_(r16, 9, 8) |
| #define SET16InterPROP_motion_0i(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32InterPROP_motion_1i(r32) _BFGET_(r32,11,10) |
| #define SET32InterPROP_motion_1i(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16InterPROP_motion_1i(r16) _BFGET_(r16,11,10) |
| #define SET16InterPROP_motion_1i(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32InterPROP_mvs_0i(r32) _BFGET_(r32,13,12) |
| #define SET32InterPROP_mvs_0i(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16InterPROP_mvs_0i(r16) _BFGET_(r16,13,12) |
| #define SET16InterPROP_mvs_0i(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32InterPROP_mvs_1i(r32) _BFGET_(r32,15,14) |
| #define SET32InterPROP_mvs_1i(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16InterPROP_mvs_1i(r16) _BFGET_(r16,15,14) |
| #define SET16InterPROP_mvs_1i(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_type : 3; |
| UNSG32 u_8x8IDX0 : 1; |
| UNSG32 u_t8x8I : 1; |
| UNSG32 u_t8x8PB : 1; |
| UNSG32 u_partition : 2; |
| UNSG32 u_motion_0i : 2; |
| UNSG32 u_motion_1i : 2; |
| UNSG32 u_mvs_0i : 2; |
| UNSG32 u_mvs_1i : 2; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_InterPROP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 InterPROP_drvrd(SIE_InterPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 InterPROP_drvwr(SIE_InterPROP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void InterPROP_reset(SIE_InterPROP *p); |
| SIGN32 InterPROP_cmp (SIE_InterPROP *p, SIE_InterPROP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define InterPROP_check(p,pie,pfx,hLOG) InterPROP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define InterPROP_print(p, pfx,hLOG) InterPROP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: InterPROP |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ResPROP_VC1 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 MaxNumCoeff |
| /// ### |
| /// * Maximal number of coefficients to decode, |
| /// * The valid number is: 16, 32, 63, and 64 |
| /// ### |
| /// %unsigned 3 eBlk |
| /// ### |
| /// * 8x8 Block index. 0~3 for Y, 4 for Cb, 5 for Cr |
| /// ### |
| /// %unsigned 1 IsIntra |
| /// ### |
| /// * 1: intra block |
| /// * 0: inter block |
| /// ### |
| /// %unsigned 2 SubBlkIdx |
| /// ### |
| /// * Sub-block index in 8x8 block. Unit is 4x4 regardless of transform type. |
| /// ### |
| /// %unsigned 2 TransTypeOrIpMode |
| /// ### |
| /// * For inter block, this field contain transform type information. |
| /// ### |
| /// : TRANS_4x4 0x0 |
| /// : TRANS_4x8 0x1 |
| /// : TRANS_8x4 0x2 |
| /// : TRANS_8x8 0x3 |
| /// ### |
| /// * For intra block, this field is intra prediction mode. |
| /// ### |
| /// : IP_NORMAL 0x0 |
| /// : IP_HORIZONTAL 0x1 |
| /// : IP_VERTICAL 0x2 |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ResPROP_VC1 |
| #define h_ResPROP_VC1 (){} |
| |
| #define BA_ResPROP_VC1_MaxNumCoeff 0x0000 |
| #define B16ResPROP_VC1_MaxNumCoeff 0x0000 |
| #define LSb32ResPROP_VC1_MaxNumCoeff 0 |
| #define LSb16ResPROP_VC1_MaxNumCoeff 0 |
| #define bResPROP_VC1_MaxNumCoeff 8 |
| #define MSK32ResPROP_VC1_MaxNumCoeff 0x000000FF |
| |
| #define BA_ResPROP_VC1_eBlk 0x0001 |
| #define B16ResPROP_VC1_eBlk 0x0000 |
| #define LSb32ResPROP_VC1_eBlk 8 |
| #define LSb16ResPROP_VC1_eBlk 8 |
| #define bResPROP_VC1_eBlk 3 |
| #define MSK32ResPROP_VC1_eBlk 0x00000700 |
| |
| #define BA_ResPROP_VC1_IsIntra 0x0001 |
| #define B16ResPROP_VC1_IsIntra 0x0000 |
| #define LSb32ResPROP_VC1_IsIntra 11 |
| #define LSb16ResPROP_VC1_IsIntra 11 |
| #define bResPROP_VC1_IsIntra 1 |
| #define MSK32ResPROP_VC1_IsIntra 0x00000800 |
| |
| #define BA_ResPROP_VC1_SubBlkIdx 0x0001 |
| #define B16ResPROP_VC1_SubBlkIdx 0x0000 |
| #define LSb32ResPROP_VC1_SubBlkIdx 12 |
| #define LSb16ResPROP_VC1_SubBlkIdx 12 |
| #define bResPROP_VC1_SubBlkIdx 2 |
| #define MSK32ResPROP_VC1_SubBlkIdx 0x00003000 |
| |
| #define BA_ResPROP_VC1_TransTypeOrIpMode 0x0001 |
| #define B16ResPROP_VC1_TransTypeOrIpMode 0x0000 |
| #define LSb32ResPROP_VC1_TransTypeOrIpMode 14 |
| #define LSb16ResPROP_VC1_TransTypeOrIpMode 14 |
| #define bResPROP_VC1_TransTypeOrIpMode 2 |
| #define MSK32ResPROP_VC1_TransTypeOrIpMode 0x0000C000 |
| #define ResPROP_VC1_TransTypeOrIpMode_TRANS_4x4 0x0 |
| #define ResPROP_VC1_TransTypeOrIpMode_TRANS_4x8 0x1 |
| #define ResPROP_VC1_TransTypeOrIpMode_TRANS_8x4 0x2 |
| #define ResPROP_VC1_TransTypeOrIpMode_TRANS_8x8 0x3 |
| #define ResPROP_VC1_TransTypeOrIpMode_IP_NORMAL 0x0 |
| #define ResPROP_VC1_TransTypeOrIpMode_IP_HORIZONTAL 0x1 |
| #define ResPROP_VC1_TransTypeOrIpMode_IP_VERTICAL 0x2 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ResPROP_VC1 { |
| /////////////////////////////////////////////////////////// |
| #define GET32ResPROP_VC1_MaxNumCoeff(r32) _BFGET_(r32, 7, 0) |
| #define SET32ResPROP_VC1_MaxNumCoeff(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16ResPROP_VC1_MaxNumCoeff(r16) _BFGET_(r16, 7, 0) |
| #define SET16ResPROP_VC1_MaxNumCoeff(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32ResPROP_VC1_eBlk(r32) _BFGET_(r32,10, 8) |
| #define SET32ResPROP_VC1_eBlk(r32,v) _BFSET_(r32,10, 8,v) |
| #define GET16ResPROP_VC1_eBlk(r16) _BFGET_(r16,10, 8) |
| #define SET16ResPROP_VC1_eBlk(r16,v) _BFSET_(r16,10, 8,v) |
| |
| #define GET32ResPROP_VC1_IsIntra(r32) _BFGET_(r32,11,11) |
| #define SET32ResPROP_VC1_IsIntra(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16ResPROP_VC1_IsIntra(r16) _BFGET_(r16,11,11) |
| #define SET16ResPROP_VC1_IsIntra(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32ResPROP_VC1_SubBlkIdx(r32) _BFGET_(r32,13,12) |
| #define SET32ResPROP_VC1_SubBlkIdx(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16ResPROP_VC1_SubBlkIdx(r16) _BFGET_(r16,13,12) |
| #define SET16ResPROP_VC1_SubBlkIdx(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32ResPROP_VC1_TransTypeOrIpMode(r32) _BFGET_(r32,15,14) |
| #define SET32ResPROP_VC1_TransTypeOrIpMode(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16ResPROP_VC1_TransTypeOrIpMode(r16) _BFGET_(r16,15,14) |
| #define SET16ResPROP_VC1_TransTypeOrIpMode(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_MaxNumCoeff : 8; |
| UNSG32 u_eBlk : 3; |
| UNSG32 u_IsIntra : 1; |
| UNSG32 u_SubBlkIdx : 2; |
| UNSG32 u_TransTypeOrIpMode : 2; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_ResPROP_VC1; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ResPROP_VC1_drvrd(SIE_ResPROP_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ResPROP_VC1_drvwr(SIE_ResPROP_VC1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ResPROP_VC1_reset(SIE_ResPROP_VC1 *p); |
| SIGN32 ResPROP_VC1_cmp (SIE_ResPROP_VC1 *p, SIE_ResPROP_VC1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ResPROP_VC1_check(p,pie,pfx,hLOG) ResPROP_VC1_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ResPROP_VC1_print(p, pfx,hLOG) ResPROP_VC1_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ResPROP_VC1 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ResPROP_MPEG2 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 Intra_MB |
| /// : inter 0x0 |
| /// : intra 0x1 |
| /// ### |
| /// * Indicate current MB is inter-coded or intra-coded |
| /// ### |
| /// %unsigned 1 CC |
| /// : luma 0x0 |
| /// : chroma 0x1 |
| /// ### |
| /// * Color component (to select VLC table) |
| /// ### |
| /// %unsigned 1 intra_vlc_format |
| /// ### |
| /// * Whether to use intra VLC DC table or inter table |
| /// * End of ResProp_MPEG2 |
| /// ### |
| /// %% 29 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 3b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ResPROP_MPEG2 |
| #define h_ResPROP_MPEG2 (){} |
| |
| #define BA_ResPROP_MPEG2_Intra_MB 0x0000 |
| #define B16ResPROP_MPEG2_Intra_MB 0x0000 |
| #define LSb32ResPROP_MPEG2_Intra_MB 0 |
| #define LSb16ResPROP_MPEG2_Intra_MB 0 |
| #define bResPROP_MPEG2_Intra_MB 1 |
| #define MSK32ResPROP_MPEG2_Intra_MB 0x00000001 |
| #define ResPROP_MPEG2_Intra_MB_inter 0x0 |
| #define ResPROP_MPEG2_Intra_MB_intra 0x1 |
| |
| #define BA_ResPROP_MPEG2_CC 0x0000 |
| #define B16ResPROP_MPEG2_CC 0x0000 |
| #define LSb32ResPROP_MPEG2_CC 1 |
| #define LSb16ResPROP_MPEG2_CC 1 |
| #define bResPROP_MPEG2_CC 1 |
| #define MSK32ResPROP_MPEG2_CC 0x00000002 |
| #define ResPROP_MPEG2_CC_luma 0x0 |
| #define ResPROP_MPEG2_CC_chroma 0x1 |
| |
| #define BA_ResPROP_MPEG2_intra_vlc_format 0x0000 |
| #define B16ResPROP_MPEG2_intra_vlc_format 0x0000 |
| #define LSb32ResPROP_MPEG2_intra_vlc_format 2 |
| #define LSb16ResPROP_MPEG2_intra_vlc_format 2 |
| #define bResPROP_MPEG2_intra_vlc_format 1 |
| #define MSK32ResPROP_MPEG2_intra_vlc_format 0x00000004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ResPROP_MPEG2 { |
| /////////////////////////////////////////////////////////// |
| #define GET32ResPROP_MPEG2_Intra_MB(r32) _BFGET_(r32, 0, 0) |
| #define SET32ResPROP_MPEG2_Intra_MB(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ResPROP_MPEG2_Intra_MB(r16) _BFGET_(r16, 0, 0) |
| #define SET16ResPROP_MPEG2_Intra_MB(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ResPROP_MPEG2_CC(r32) _BFGET_(r32, 1, 1) |
| #define SET32ResPROP_MPEG2_CC(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ResPROP_MPEG2_CC(r16) _BFGET_(r16, 1, 1) |
| #define SET16ResPROP_MPEG2_CC(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32ResPROP_MPEG2_intra_vlc_format(r32) _BFGET_(r32, 2, 2) |
| #define SET32ResPROP_MPEG2_intra_vlc_format(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16ResPROP_MPEG2_intra_vlc_format(r16) _BFGET_(r16, 2, 2) |
| #define SET16ResPROP_MPEG2_intra_vlc_format(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| UNSG32 u_Intra_MB : 1; |
| UNSG32 u_CC : 1; |
| UNSG32 u_intra_vlc_format : 1; |
| UNSG32 RSVDx0_b3 : 29; |
| /////////////////////////////////////////////////////////// |
| } SIE_ResPROP_MPEG2; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ResPROP_MPEG2_drvrd(SIE_ResPROP_MPEG2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ResPROP_MPEG2_drvwr(SIE_ResPROP_MPEG2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ResPROP_MPEG2_reset(SIE_ResPROP_MPEG2 *p); |
| SIGN32 ResPROP_MPEG2_cmp (SIE_ResPROP_MPEG2 *p, SIE_ResPROP_MPEG2 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ResPROP_MPEG2_check(p,pie,pfx,hLOG) ResPROP_MPEG2_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ResPROP_MPEG2_print(p, pfx,hLOG) ResPROP_MPEG2_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ResPROP_MPEG2 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ResPROP_MPEG4 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 Intra_MB |
| /// : inter 0x0 |
| /// : intra 0x1 |
| /// ### |
| /// * Indicate current MB is inter-coded or intra-coded |
| /// ### |
| /// %unsigned 1 CC |
| /// : luma 0x0 |
| /// : chroma 0x1 |
| /// ### |
| /// * Color component (to select VLC table) |
| /// ### |
| /// %unsigned 1 use_intra_dc_vlc |
| /// ### |
| /// * Whether to use intra VLC DC table or inter table |
| /// ### |
| /// %unsigned 1 pattern_code |
| /// ### |
| /// * Indicate whether to encode AC coefficients |
| /// ### |
| /// %unsigned 2 scan_order |
| /// : normal 0x0 |
| /// : horizontal 0x1 |
| /// : vertical 0x2 |
| /// ### |
| /// * Indicate zigzag scan order of 8x8 coefficients |
| /// * End of ResProp_MPEG4 |
| /// ### |
| /// %% 26 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 6b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ResPROP_MPEG4 |
| #define h_ResPROP_MPEG4 (){} |
| |
| #define BA_ResPROP_MPEG4_Intra_MB 0x0000 |
| #define B16ResPROP_MPEG4_Intra_MB 0x0000 |
| #define LSb32ResPROP_MPEG4_Intra_MB 0 |
| #define LSb16ResPROP_MPEG4_Intra_MB 0 |
| #define bResPROP_MPEG4_Intra_MB 1 |
| #define MSK32ResPROP_MPEG4_Intra_MB 0x00000001 |
| #define ResPROP_MPEG4_Intra_MB_inter 0x0 |
| #define ResPROP_MPEG4_Intra_MB_intra 0x1 |
| |
| #define BA_ResPROP_MPEG4_CC 0x0000 |
| #define B16ResPROP_MPEG4_CC 0x0000 |
| #define LSb32ResPROP_MPEG4_CC 1 |
| #define LSb16ResPROP_MPEG4_CC 1 |
| #define bResPROP_MPEG4_CC 1 |
| #define MSK32ResPROP_MPEG4_CC 0x00000002 |
| #define ResPROP_MPEG4_CC_luma 0x0 |
| #define ResPROP_MPEG4_CC_chroma 0x1 |
| |
| #define BA_ResPROP_MPEG4_use_intra_dc_vlc 0x0000 |
| #define B16ResPROP_MPEG4_use_intra_dc_vlc 0x0000 |
| #define LSb32ResPROP_MPEG4_use_intra_dc_vlc 2 |
| #define LSb16ResPROP_MPEG4_use_intra_dc_vlc 2 |
| #define bResPROP_MPEG4_use_intra_dc_vlc 1 |
| #define MSK32ResPROP_MPEG4_use_intra_dc_vlc 0x00000004 |
| |
| #define BA_ResPROP_MPEG4_pattern_code 0x0000 |
| #define B16ResPROP_MPEG4_pattern_code 0x0000 |
| #define LSb32ResPROP_MPEG4_pattern_code 3 |
| #define LSb16ResPROP_MPEG4_pattern_code 3 |
| #define bResPROP_MPEG4_pattern_code 1 |
| #define MSK32ResPROP_MPEG4_pattern_code 0x00000008 |
| |
| #define BA_ResPROP_MPEG4_scan_order 0x0000 |
| #define B16ResPROP_MPEG4_scan_order 0x0000 |
| #define LSb32ResPROP_MPEG4_scan_order 4 |
| #define LSb16ResPROP_MPEG4_scan_order 4 |
| #define bResPROP_MPEG4_scan_order 2 |
| #define MSK32ResPROP_MPEG4_scan_order 0x00000030 |
| #define ResPROP_MPEG4_scan_order_normal 0x0 |
| #define ResPROP_MPEG4_scan_order_horizontal 0x1 |
| #define ResPROP_MPEG4_scan_order_vertical 0x2 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ResPROP_MPEG4 { |
| /////////////////////////////////////////////////////////// |
| #define GET32ResPROP_MPEG4_Intra_MB(r32) _BFGET_(r32, 0, 0) |
| #define SET32ResPROP_MPEG4_Intra_MB(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ResPROP_MPEG4_Intra_MB(r16) _BFGET_(r16, 0, 0) |
| #define SET16ResPROP_MPEG4_Intra_MB(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ResPROP_MPEG4_CC(r32) _BFGET_(r32, 1, 1) |
| #define SET32ResPROP_MPEG4_CC(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ResPROP_MPEG4_CC(r16) _BFGET_(r16, 1, 1) |
| #define SET16ResPROP_MPEG4_CC(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32ResPROP_MPEG4_use_intra_dc_vlc(r32) _BFGET_(r32, 2, 2) |
| #define SET32ResPROP_MPEG4_use_intra_dc_vlc(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16ResPROP_MPEG4_use_intra_dc_vlc(r16) _BFGET_(r16, 2, 2) |
| #define SET16ResPROP_MPEG4_use_intra_dc_vlc(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32ResPROP_MPEG4_pattern_code(r32) _BFGET_(r32, 3, 3) |
| #define SET32ResPROP_MPEG4_pattern_code(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16ResPROP_MPEG4_pattern_code(r16) _BFGET_(r16, 3, 3) |
| #define SET16ResPROP_MPEG4_pattern_code(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32ResPROP_MPEG4_scan_order(r32) _BFGET_(r32, 5, 4) |
| #define SET32ResPROP_MPEG4_scan_order(r32,v) _BFSET_(r32, 5, 4,v) |
| #define GET16ResPROP_MPEG4_scan_order(r16) _BFGET_(r16, 5, 4) |
| #define SET16ResPROP_MPEG4_scan_order(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| UNSG32 u_Intra_MB : 1; |
| UNSG32 u_CC : 1; |
| UNSG32 u_use_intra_dc_vlc : 1; |
| UNSG32 u_pattern_code : 1; |
| UNSG32 u_scan_order : 2; |
| UNSG32 RSVDx0_b6 : 26; |
| /////////////////////////////////////////////////////////// |
| } SIE_ResPROP_MPEG4; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ResPROP_MPEG4_drvrd(SIE_ResPROP_MPEG4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ResPROP_MPEG4_drvwr(SIE_ResPROP_MPEG4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ResPROP_MPEG4_reset(SIE_ResPROP_MPEG4 *p); |
| SIGN32 ResPROP_MPEG4_cmp (SIE_ResPROP_MPEG4 *p, SIE_ResPROP_MPEG4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ResPROP_MPEG4_check(p,pie,pfx,hLOG) ResPROP_MPEG4_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ResPROP_MPEG4_print(p, pfx,hLOG) ResPROP_MPEG4_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ResPROP_MPEG4 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ResPROP_JPEG (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 DCTblId |
| /// : luma 0x0 |
| /// : chroma 0x1 |
| /// ### |
| /// * Selects Huffman table used to decode or encode DC coefficients |
| /// ### |
| /// %unsigned 1 ACTblId |
| /// : luma 0x0 |
| /// : chroma 0x1 |
| /// ### |
| /// * Selects Huffman table used to decode or encode AC coefficients |
| /// * End of ResPROP_JPEG |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 2b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ResPROP_JPEG |
| #define h_ResPROP_JPEG (){} |
| |
| #define BA_ResPROP_JPEG_DCTblId 0x0000 |
| #define B16ResPROP_JPEG_DCTblId 0x0000 |
| #define LSb32ResPROP_JPEG_DCTblId 0 |
| #define LSb16ResPROP_JPEG_DCTblId 0 |
| #define bResPROP_JPEG_DCTblId 1 |
| #define MSK32ResPROP_JPEG_DCTblId 0x00000001 |
| #define ResPROP_JPEG_DCTblId_luma 0x0 |
| #define ResPROP_JPEG_DCTblId_chroma 0x1 |
| |
| #define BA_ResPROP_JPEG_ACTblId 0x0000 |
| #define B16ResPROP_JPEG_ACTblId 0x0000 |
| #define LSb32ResPROP_JPEG_ACTblId 1 |
| #define LSb16ResPROP_JPEG_ACTblId 1 |
| #define bResPROP_JPEG_ACTblId 1 |
| #define MSK32ResPROP_JPEG_ACTblId 0x00000002 |
| #define ResPROP_JPEG_ACTblId_luma 0x0 |
| #define ResPROP_JPEG_ACTblId_chroma 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ResPROP_JPEG { |
| /////////////////////////////////////////////////////////// |
| #define GET32ResPROP_JPEG_DCTblId(r32) _BFGET_(r32, 0, 0) |
| #define SET32ResPROP_JPEG_DCTblId(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ResPROP_JPEG_DCTblId(r16) _BFGET_(r16, 0, 0) |
| #define SET16ResPROP_JPEG_DCTblId(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ResPROP_JPEG_ACTblId(r32) _BFGET_(r32, 1, 1) |
| #define SET32ResPROP_JPEG_ACTblId(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ResPROP_JPEG_ACTblId(r16) _BFGET_(r16, 1, 1) |
| #define SET16ResPROP_JPEG_ACTblId(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| UNSG32 u_DCTblId : 1; |
| UNSG32 u_ACTblId : 1; |
| UNSG32 RSVDx0_b2 : 30; |
| /////////////////////////////////////////////////////////// |
| } SIE_ResPROP_JPEG; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ResPROP_JPEG_drvrd(SIE_ResPROP_JPEG *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ResPROP_JPEG_drvwr(SIE_ResPROP_JPEG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ResPROP_JPEG_reset(SIE_ResPROP_JPEG *p); |
| SIGN32 ResPROP_JPEG_cmp (SIE_ResPROP_JPEG *p, SIE_ResPROP_JPEG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ResPROP_JPEG_check(p,pie,pfx,hLOG) ResPROP_JPEG_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ResPROP_JPEG_print(p, pfx,hLOG) ResPROP_JPEG_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ResPROP_JPEG |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE TotalCoeff6 (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 nc_0i |
| /// %unsigned 5 nc_1i |
| /// %unsigned 5 nc_2i |
| /// ### |
| /// * The number of non-zero transform coefficients in a 4x4 Y or UV coefficient block. Totally 3 blocks are in order 0 ~ 2. |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// %unsigned 5 nc1_0i |
| /// %unsigned 5 nc1_1i |
| /// %unsigned 5 nc1_2i |
| /// %% 1 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 30b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_TotalCoeff6 |
| #define h_TotalCoeff6 (){} |
| |
| #define BA_TotalCoeff6_nc_0i 0x0000 |
| #define B16TotalCoeff6_nc_0i 0x0000 |
| #define LSb32TotalCoeff6_nc_0i 0 |
| #define LSb16TotalCoeff6_nc_0i 0 |
| #define bTotalCoeff6_nc_0i 5 |
| #define MSK32TotalCoeff6_nc_0i 0x0000001F |
| |
| #define BA_TotalCoeff6_nc_1i 0x0000 |
| #define B16TotalCoeff6_nc_1i 0x0000 |
| #define LSb32TotalCoeff6_nc_1i 5 |
| #define LSb16TotalCoeff6_nc_1i 5 |
| #define bTotalCoeff6_nc_1i 5 |
| #define MSK32TotalCoeff6_nc_1i 0x000003E0 |
| |
| #define BA_TotalCoeff6_nc_2i 0x0001 |
| #define B16TotalCoeff6_nc_2i 0x0000 |
| #define LSb32TotalCoeff6_nc_2i 10 |
| #define LSb16TotalCoeff6_nc_2i 10 |
| #define bTotalCoeff6_nc_2i 5 |
| #define MSK32TotalCoeff6_nc_2i 0x00007C00 |
| |
| #define BA_TotalCoeff6_nc1_0i 0x0002 |
| #define B16TotalCoeff6_nc1_0i 0x0002 |
| #define LSb32TotalCoeff6_nc1_0i 16 |
| #define LSb16TotalCoeff6_nc1_0i 0 |
| #define bTotalCoeff6_nc1_0i 5 |
| #define MSK32TotalCoeff6_nc1_0i 0x001F0000 |
| |
| #define BA_TotalCoeff6_nc1_1i 0x0002 |
| #define B16TotalCoeff6_nc1_1i 0x0002 |
| #define LSb32TotalCoeff6_nc1_1i 21 |
| #define LSb16TotalCoeff6_nc1_1i 5 |
| #define bTotalCoeff6_nc1_1i 5 |
| #define MSK32TotalCoeff6_nc1_1i 0x03E00000 |
| |
| #define BA_TotalCoeff6_nc1_2i 0x0003 |
| #define B16TotalCoeff6_nc1_2i 0x0002 |
| #define LSb32TotalCoeff6_nc1_2i 26 |
| #define LSb16TotalCoeff6_nc1_2i 10 |
| #define bTotalCoeff6_nc1_2i 5 |
| #define MSK32TotalCoeff6_nc1_2i 0x7C000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_TotalCoeff6 { |
| /////////////////////////////////////////////////////////// |
| #define GET32TotalCoeff6_nc_0i(r32) _BFGET_(r32, 4, 0) |
| #define SET32TotalCoeff6_nc_0i(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16TotalCoeff6_nc_0i(r16) _BFGET_(r16, 4, 0) |
| #define SET16TotalCoeff6_nc_0i(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32TotalCoeff6_nc_1i(r32) _BFGET_(r32, 9, 5) |
| #define SET32TotalCoeff6_nc_1i(r32,v) _BFSET_(r32, 9, 5,v) |
| #define GET16TotalCoeff6_nc_1i(r16) _BFGET_(r16, 9, 5) |
| #define SET16TotalCoeff6_nc_1i(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32TotalCoeff6_nc_2i(r32) _BFGET_(r32,14,10) |
| #define SET32TotalCoeff6_nc_2i(r32,v) _BFSET_(r32,14,10,v) |
| #define GET16TotalCoeff6_nc_2i(r16) _BFGET_(r16,14,10) |
| #define SET16TotalCoeff6_nc_2i(r16,v) _BFSET_(r16,14,10,v) |
| |
| #define GET32TotalCoeff6_nc1_0i(r32) _BFGET_(r32,20,16) |
| #define SET32TotalCoeff6_nc1_0i(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16TotalCoeff6_nc1_0i(r16) _BFGET_(r16, 4, 0) |
| #define SET16TotalCoeff6_nc1_0i(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32TotalCoeff6_nc1_1i(r32) _BFGET_(r32,25,21) |
| #define SET32TotalCoeff6_nc1_1i(r32,v) _BFSET_(r32,25,21,v) |
| #define GET16TotalCoeff6_nc1_1i(r16) _BFGET_(r16, 9, 5) |
| #define SET16TotalCoeff6_nc1_1i(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32TotalCoeff6_nc1_2i(r32) _BFGET_(r32,30,26) |
| #define SET32TotalCoeff6_nc1_2i(r32,v) _BFSET_(r32,30,26,v) |
| #define GET16TotalCoeff6_nc1_2i(r16) _BFGET_(r16,14,10) |
| #define SET16TotalCoeff6_nc1_2i(r16,v) _BFSET_(r16,14,10,v) |
| |
| UNSG32 u_nc_0i : 5; |
| UNSG32 u_nc_1i : 5; |
| UNSG32 u_nc_2i : 5; |
| UNSG32 RSVDx0_b15 : 1; |
| UNSG32 u_nc1_0i : 5; |
| UNSG32 u_nc1_1i : 5; |
| UNSG32 u_nc1_2i : 5; |
| UNSG32 RSVDx0_b31 : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_TotalCoeff6; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 TotalCoeff6_drvrd(SIE_TotalCoeff6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 TotalCoeff6_drvwr(SIE_TotalCoeff6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void TotalCoeff6_reset(SIE_TotalCoeff6 *p); |
| SIGN32 TotalCoeff6_cmp (SIE_TotalCoeff6 *p, SIE_TotalCoeff6 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define TotalCoeff6_check(p,pie,pfx,hLOG) TotalCoeff6_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define TotalCoeff6_print(p, pfx,hLOG) TotalCoeff6_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: TotalCoeff6 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ASEPopTotalCoeff (4,2) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 TotalCoeff |
| /// $TotalCoeff6 TotalCoeff REG [2] |
| /// ### |
| /// * The number of non-zero transform coefficients in a 4x4 Y or UV coefficient block in 3 block group. Totally 12 blocks in 4 groups are in order 0 ~ 11. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 60b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ASEPopTotalCoeff |
| #define h_ASEPopTotalCoeff (){} |
| |
| #define RA_ASEPopTotalCoeff_TotalCoeff 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ASEPopTotalCoeff { |
| /////////////////////////////////////////////////////////// |
| SIE_TotalCoeff6 ie_TotalCoeff[2]; |
| /////////////////////////////////////////////////////////// |
| } SIE_ASEPopTotalCoeff; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ASEPopTotalCoeff_drvrd(SIE_ASEPopTotalCoeff *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ASEPopTotalCoeff_drvwr(SIE_ASEPopTotalCoeff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ASEPopTotalCoeff_reset(SIE_ASEPopTotalCoeff *p); |
| SIGN32 ASEPopTotalCoeff_cmp (SIE_ASEPopTotalCoeff *p, SIE_ASEPopTotalCoeff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ASEPopTotalCoeff_check(p,pie,pfx,hLOG) ASEPopTotalCoeff_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ASEPopTotalCoeff_print(p, pfx,hLOG) ASEPopTotalCoeff_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ASEPopTotalCoeff |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64PIC biu (4,4) |
| /// ### |
| /// * RF64 picture-level information for ALU64 extensions; padded to 64b. Used in placed of BIU register for efficiency. Parameters in this interface should only be updated at the slice boundary. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 3 format |
| /// : h264 0x0 |
| /// : wmv 0x1 |
| /// ### |
| /// * VC-1 Main Profile |
| /// ### |
| /// : mpg2 0x2 |
| /// : other 0x3 |
| /// : mpg4 0x4 |
| /// : vc1ap 0x5 |
| /// ### |
| /// * VC-1 Advanced Profile |
| /// ### |
| /// : h263 0x6 |
| /// : avs 0x7 |
| /// ### |
| /// * Format of the current video stream |
| /// ### |
| /// %unsigned 1 cabac |
| /// ### |
| /// * Whether current slice is coded in CABAC |
| /// ### |
| /// %unsigned 2 picType |
| /// : I 0x0 |
| /// : P 0x1 |
| /// : B 0x2 |
| /// ### |
| /// * Used by PMV to qualify between P_skip & B_skip |
| /// ### |
| /// %unsigned 5 maxL0 |
| /// ### |
| /// * H264: num_ref_idx_l0_active_minus1 |
| /// ### |
| /// %unsigned 5 maxL1 |
| /// ### |
| /// * H264: num_ref_idx_l1_active_minus1 |
| /// ### |
| /// %unsigned 1 MbaffPic |
| /// ### |
| /// * Whether current picture is Mbaff pic or not; for FOP |
| /// * For VC-1: |
| /// * (~Mbaffpic && ~fieldPic) -> progressive |
| /// * (Mbaffpic && ~fieldPic) -> interlace frame |
| /// ### |
| /// %unsigned 1 fieldPic |
| /// ### |
| /// * Whether current picture is field coded or not; for FOP |
| /// * For VC-1: |
| /// * (~MbaffPic && fieldPic) -> interlace field, one ref; |
| /// * (MbaffPic && fieldPic) -> interlace field, two ref |
| /// ### |
| /// %unsigned 1 spatialPred |
| /// ### |
| /// * Spatial direct prediction modee; for dirMV. |
| /// ### |
| /// %unsigned 1 colPicMbaff |
| /// ### |
| /// * Whether colocated pic is Mbaff pic or not; for dirMV |
| /// ### |
| /// %unsigned 1 colPicField |
| /// ### |
| /// * Whether colocated picture is field pic or not; for dirMV |
| /// ### |
| /// %unsigned 1 colPicST |
| /// ### |
| /// * Co-located picture is a long-term (0) or short-term (1) reference picture; for dirMV. |
| /// ### |
| /// %signed 5 AC0Offset |
| /// ### |
| /// * = slice_alpha_c0_offset_div2<<1, -12 ~ +12, inclusive, even numbers only. For FOP only. |
| /// ### |
| /// %signed 5 BetaOffset |
| /// ### |
| /// * = slice_beta_offset_div2<<1, -12 ~ +12, inclusive, even numbers only. For FOP only. |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 16 dqAcLimit |
| /// ### |
| /// * Saturation limit for AC dequantization |
| /// * Also apply for universal dequantization |
| /// ### |
| /// %unsigned 14 dqDcLimit |
| /// ### |
| /// * Saturation limit for DC dequantization |
| /// ### |
| /// %unsigned 2 mismatch |
| /// : none 0x0 |
| /// : mpeg1 0x1 |
| /// : mpeg2 0x2 |
| /// ### |
| /// * mismatch control, for AC dequant only |
| /// ### |
| /// @ 0x00008 (P) |
| /// %unsigned 16 picW |
| /// ### |
| /// * Width of current picture; up to 2047 |
| /// ### |
| /// %unsigned 13 picH |
| /// ### |
| /// * Height of current picture; up to 2047. For vcMsg only |
| /// ### |
| /// %unsigned 1 btmFldPic |
| /// ### |
| /// * H.264: Current picture is bottom field; for vcMsg. Valid only when fieldPic==1. |
| /// ### |
| /// %unsigned 2 hint |
| /// ### |
| /// * Same as CacheMsg.hint; for vcMsg only |
| /// ### |
| /// @ 0x0000C (P) |
| /// %unsigned 8 shiftLumaX |
| /// ### |
| /// * (For vcMsg only) Shift amount lookup table for Luma X direction. 4 entries, 2-bit per entry, indexed by mvx[1:0] in little-endian format |
| /// ### |
| /// %unsigned 8 shiftLumaY |
| /// ### |
| /// * (For vcMsg only) Shift amount lookup table for Luma Y direction. 4 entries, 2-bit per entry, indexed by mvy[1:0] in little-endian format |
| /// ### |
| /// %unsigned 8 shiftChromaX |
| /// ### |
| /// * (For vcMsg only) Shift amount lookup table for Chroma X direction. 4 entries, 2-bit per entry, indexed by mvx[1:0] in little-endian format |
| /// ### |
| /// %unsigned 8 shiftChromaY |
| /// ### |
| /// * (For vcMsg only) Shift amount lookup table for Chroma Y direction. 4 entries, 2-bit per entry, indexed by mvy[1:0] in little-endian format |
| /// ### |
| /// @ 0x00010 (P) |
| /// %unsigned 4 fracTapDiv2Y |
| /// ### |
| /// * (Tap size / 2) for luma fractional MV interpolation |
| /// ### |
| /// %unsigned 4 fracTapDiv2C |
| /// ### |
| /// * (Tap size / 2) for chroma fractional MV interpolation |
| /// ### |
| /// %unsigned 6 IPCM_QPU |
| /// ### |
| /// * QPU for IPCM coded MBs; for H.264 FOP |
| /// ### |
| /// %unsigned 6 IPCM_QPV |
| /// ### |
| /// * QPV for IPCM coded MBs; for H.264 FOP |
| /// ### |
| /// %unsigned 12 RSVD12 |
| /// ### |
| /// * padding to 32 bits |
| /// ### |
| /// @ 0x00014 (P) |
| /// %unsigned 5 PQUANT |
| /// ### |
| /// * picture-level quantization factor |
| /// ### |
| /// %unsigned 2 FRFD |
| /// ### |
| /// * Forward reference picture distance, 0~3. |
| /// * Used by VC1 for interlace P field PMV, or for interlace B field forward PMV |
| /// ### |
| /// %unsigned 2 BRFD |
| /// ### |
| /// * Backward reference picture distance, 0~3. |
| /// * Used by VC1 for interlace B field backward PMV |
| /// ### |
| /// %unsigned 1 secondFld |
| /// ### |
| /// * Used by PMV for interlace field picture: whether current field is 1st field or 2nd field of display picture |
| /// ### |
| /// %unsigned 2 mvRange |
| /// ### |
| /// * 0~3; used to lookup range_x & range_y for PMV; see VC-1 spec table 75. |
| /// ### |
| /// %unsigned 1 hybridMvThres |
| /// ### |
| /// * 0: threshold = 16; 1: threshold = 32 |
| /// ### |
| /// %unsigned 1 firstMbIntra |
| /// ### |
| /// * 0: first MB or block is inter coded; 1: intra coded; used for VC-1 Fop |
| /// ### |
| /// %unsigned 1 halfPixel |
| /// ### |
| /// * Half pixel flag, for VC-1 PMV interlace field mode. |
| /// ### |
| /// %unsigned 1 forwRefInterlace |
| /// ### |
| /// * For VC-1 interlace frame picture in VCMSG extension forward reference is 0: progressive coded; 1: interlace coded |
| /// ### |
| /// %unsigned 1 backRefInterlace |
| /// ### |
| /// * For VC-1 interlace frame picture in VCMSG extension backward reference is 0: progressive coded; 1: interlace coded |
| /// ### |
| /// %unsigned 2 FrmTransACSet |
| /// ### |
| /// * For VC-1 frame-level transform AC coding set selection (for Cb and Cr block; and inter Y block). |
| /// * Valid values are 0, 1, and 2 |
| /// ### |
| /// %unsigned 2 FrmTransACSet2 |
| /// ### |
| /// * For VC-1 frame-level transform AC table-2 index selection (for I-frame Y block) |
| /// * Valid values are 0, 1, and 2 |
| /// ### |
| /// %unsigned 1 PQIndexGT8 |
| /// ### |
| /// * Indicator to represent whether Picture Quantized Index (PQIndexG8, defined in Table 36 in VC-1 spec) is greater than 8. |
| /// * 0: value of PQIndex is less than or equal to 8 |
| /// * 1: value of PQIndex is greater than 8 |
| /// ### |
| /// %unsigned 1 EscapeTBL |
| /// ### |
| /// * For VC-1 to select escape table in residual decoding |
| /// ### |
| /// %unsigned 4 format1 |
| /// : RV9 0x0 |
| /// : RV8 0x1 |
| /// : vp8 0x2 |
| /// : jpeg 0x3 |
| /// %unsigned 1 noReorder |
| /// ### |
| /// * For ASE, disable coefficient reorder. |
| /// ### |
| /// %unsigned 1 iplusModeOn |
| /// ### |
| /// * For ASE, IPLUS mode is on or not. |
| /// ### |
| /// %unsigned 3 RSVD3 |
| /// ### |
| /// * padding to 32 bits |
| /// ### |
| /// @ 0x00018 (P) |
| /// # 0x00018 RSVD |
| /// $LUT64b RSVD REG [5] |
| /// ### |
| /// * Reserved for alignment |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 rIDX2BID |
| /// $IDX2BID rIDX2BID REG |
| /// ### |
| /// * Defined in 'decHal_mbLvl.sxw.txt.txt' |
| /// * End of RF64PIC |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 256B, bits: 2048b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64PIC |
| #define h_RF64PIC (){} |
| |
| #define BA_RF64PIC_format 0x0000 |
| #define B16RF64PIC_format 0x0000 |
| #define LSb32RF64PIC_format 0 |
| #define LSb16RF64PIC_format 0 |
| #define bRF64PIC_format 3 |
| #define MSK32RF64PIC_format 0x00000007 |
| #define RF64PIC_format_h264 0x0 |
| #define RF64PIC_format_wmv 0x1 |
| #define RF64PIC_format_mpg2 0x2 |
| #define RF64PIC_format_other 0x3 |
| #define RF64PIC_format_mpg4 0x4 |
| #define RF64PIC_format_vc1ap 0x5 |
| #define RF64PIC_format_h263 0x6 |
| #define RF64PIC_format_avs 0x7 |
| |
| #define BA_RF64PIC_cabac 0x0000 |
| #define B16RF64PIC_cabac 0x0000 |
| #define LSb32RF64PIC_cabac 3 |
| #define LSb16RF64PIC_cabac 3 |
| #define bRF64PIC_cabac 1 |
| #define MSK32RF64PIC_cabac 0x00000008 |
| |
| #define BA_RF64PIC_picType 0x0000 |
| #define B16RF64PIC_picType 0x0000 |
| #define LSb32RF64PIC_picType 4 |
| #define LSb16RF64PIC_picType 4 |
| #define bRF64PIC_picType 2 |
| #define MSK32RF64PIC_picType 0x00000030 |
| #define RF64PIC_picType_I 0x0 |
| #define RF64PIC_picType_P 0x1 |
| #define RF64PIC_picType_B 0x2 |
| |
| #define BA_RF64PIC_maxL0 0x0000 |
| #define B16RF64PIC_maxL0 0x0000 |
| #define LSb32RF64PIC_maxL0 6 |
| #define LSb16RF64PIC_maxL0 6 |
| #define bRF64PIC_maxL0 5 |
| #define MSK32RF64PIC_maxL0 0x000007C0 |
| |
| #define BA_RF64PIC_maxL1 0x0001 |
| #define B16RF64PIC_maxL1 0x0000 |
| #define LSb32RF64PIC_maxL1 11 |
| #define LSb16RF64PIC_maxL1 11 |
| #define bRF64PIC_maxL1 5 |
| #define MSK32RF64PIC_maxL1 0x0000F800 |
| |
| #define BA_RF64PIC_MbaffPic 0x0002 |
| #define B16RF64PIC_MbaffPic 0x0002 |
| #define LSb32RF64PIC_MbaffPic 16 |
| #define LSb16RF64PIC_MbaffPic 0 |
| #define bRF64PIC_MbaffPic 1 |
| #define MSK32RF64PIC_MbaffPic 0x00010000 |
| |
| #define BA_RF64PIC_fieldPic 0x0002 |
| #define B16RF64PIC_fieldPic 0x0002 |
| #define LSb32RF64PIC_fieldPic 17 |
| #define LSb16RF64PIC_fieldPic 1 |
| #define bRF64PIC_fieldPic 1 |
| #define MSK32RF64PIC_fieldPic 0x00020000 |
| |
| #define BA_RF64PIC_spatialPred 0x0002 |
| #define B16RF64PIC_spatialPred 0x0002 |
| #define LSb32RF64PIC_spatialPred 18 |
| #define LSb16RF64PIC_spatialPred 2 |
| #define bRF64PIC_spatialPred 1 |
| #define MSK32RF64PIC_spatialPred 0x00040000 |
| |
| #define BA_RF64PIC_colPicMbaff 0x0002 |
| #define B16RF64PIC_colPicMbaff 0x0002 |
| #define LSb32RF64PIC_colPicMbaff 19 |
| #define LSb16RF64PIC_colPicMbaff 3 |
| #define bRF64PIC_colPicMbaff 1 |
| #define MSK32RF64PIC_colPicMbaff 0x00080000 |
| |
| #define BA_RF64PIC_colPicField 0x0002 |
| #define B16RF64PIC_colPicField 0x0002 |
| #define LSb32RF64PIC_colPicField 20 |
| #define LSb16RF64PIC_colPicField 4 |
| #define bRF64PIC_colPicField 1 |
| #define MSK32RF64PIC_colPicField 0x00100000 |
| |
| #define BA_RF64PIC_colPicST 0x0002 |
| #define B16RF64PIC_colPicST 0x0002 |
| #define LSb32RF64PIC_colPicST 21 |
| #define LSb16RF64PIC_colPicST 5 |
| #define bRF64PIC_colPicST 1 |
| #define MSK32RF64PIC_colPicST 0x00200000 |
| |
| #define BA_RF64PIC_AC0Offset 0x0002 |
| #define B16RF64PIC_AC0Offset 0x0002 |
| #define LSb32RF64PIC_AC0Offset 22 |
| #define LSb16RF64PIC_AC0Offset 6 |
| #define bRF64PIC_AC0Offset 5 |
| #define MSK32RF64PIC_AC0Offset 0x07C00000 |
| |
| #define BA_RF64PIC_BetaOffset 0x0003 |
| #define B16RF64PIC_BetaOffset 0x0002 |
| #define LSb32RF64PIC_BetaOffset 27 |
| #define LSb16RF64PIC_BetaOffset 11 |
| #define bRF64PIC_BetaOffset 5 |
| #define MSK32RF64PIC_BetaOffset 0xF8000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64PIC_dqAcLimit 0x0004 |
| #define B16RF64PIC_dqAcLimit 0x0004 |
| #define LSb32RF64PIC_dqAcLimit 0 |
| #define LSb16RF64PIC_dqAcLimit 0 |
| #define bRF64PIC_dqAcLimit 16 |
| #define MSK32RF64PIC_dqAcLimit 0x0000FFFF |
| |
| #define BA_RF64PIC_dqDcLimit 0x0006 |
| #define B16RF64PIC_dqDcLimit 0x0006 |
| #define LSb32RF64PIC_dqDcLimit 16 |
| #define LSb16RF64PIC_dqDcLimit 0 |
| #define bRF64PIC_dqDcLimit 14 |
| #define MSK32RF64PIC_dqDcLimit 0x3FFF0000 |
| |
| #define BA_RF64PIC_mismatch 0x0007 |
| #define B16RF64PIC_mismatch 0x0006 |
| #define LSb32RF64PIC_mismatch 30 |
| #define LSb16RF64PIC_mismatch 14 |
| #define bRF64PIC_mismatch 2 |
| #define MSK32RF64PIC_mismatch 0xC0000000 |
| #define RF64PIC_mismatch_none 0x0 |
| #define RF64PIC_mismatch_mpeg1 0x1 |
| #define RF64PIC_mismatch_mpeg2 0x2 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64PIC_picW 0x0008 |
| #define B16RF64PIC_picW 0x0008 |
| #define LSb32RF64PIC_picW 0 |
| #define LSb16RF64PIC_picW 0 |
| #define bRF64PIC_picW 16 |
| #define MSK32RF64PIC_picW 0x0000FFFF |
| |
| #define BA_RF64PIC_picH 0x000A |
| #define B16RF64PIC_picH 0x000A |
| #define LSb32RF64PIC_picH 16 |
| #define LSb16RF64PIC_picH 0 |
| #define bRF64PIC_picH 13 |
| #define MSK32RF64PIC_picH 0x1FFF0000 |
| |
| #define BA_RF64PIC_btmFldPic 0x000B |
| #define B16RF64PIC_btmFldPic 0x000A |
| #define LSb32RF64PIC_btmFldPic 29 |
| #define LSb16RF64PIC_btmFldPic 13 |
| #define bRF64PIC_btmFldPic 1 |
| #define MSK32RF64PIC_btmFldPic 0x20000000 |
| |
| #define BA_RF64PIC_hint 0x000B |
| #define B16RF64PIC_hint 0x000A |
| #define LSb32RF64PIC_hint 30 |
| #define LSb16RF64PIC_hint 14 |
| #define bRF64PIC_hint 2 |
| #define MSK32RF64PIC_hint 0xC0000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64PIC_shiftLumaX 0x000C |
| #define B16RF64PIC_shiftLumaX 0x000C |
| #define LSb32RF64PIC_shiftLumaX 0 |
| #define LSb16RF64PIC_shiftLumaX 0 |
| #define bRF64PIC_shiftLumaX 8 |
| #define MSK32RF64PIC_shiftLumaX 0x000000FF |
| |
| #define BA_RF64PIC_shiftLumaY 0x000D |
| #define B16RF64PIC_shiftLumaY 0x000C |
| #define LSb32RF64PIC_shiftLumaY 8 |
| #define LSb16RF64PIC_shiftLumaY 8 |
| #define bRF64PIC_shiftLumaY 8 |
| #define MSK32RF64PIC_shiftLumaY 0x0000FF00 |
| |
| #define BA_RF64PIC_shiftChromaX 0x000E |
| #define B16RF64PIC_shiftChromaX 0x000E |
| #define LSb32RF64PIC_shiftChromaX 16 |
| #define LSb16RF64PIC_shiftChromaX 0 |
| #define bRF64PIC_shiftChromaX 8 |
| #define MSK32RF64PIC_shiftChromaX 0x00FF0000 |
| |
| #define BA_RF64PIC_shiftChromaY 0x000F |
| #define B16RF64PIC_shiftChromaY 0x000E |
| #define LSb32RF64PIC_shiftChromaY 24 |
| #define LSb16RF64PIC_shiftChromaY 8 |
| #define bRF64PIC_shiftChromaY 8 |
| #define MSK32RF64PIC_shiftChromaY 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64PIC_fracTapDiv2Y 0x0010 |
| #define B16RF64PIC_fracTapDiv2Y 0x0010 |
| #define LSb32RF64PIC_fracTapDiv2Y 0 |
| #define LSb16RF64PIC_fracTapDiv2Y 0 |
| #define bRF64PIC_fracTapDiv2Y 4 |
| #define MSK32RF64PIC_fracTapDiv2Y 0x0000000F |
| |
| #define BA_RF64PIC_fracTapDiv2C 0x0010 |
| #define B16RF64PIC_fracTapDiv2C 0x0010 |
| #define LSb32RF64PIC_fracTapDiv2C 4 |
| #define LSb16RF64PIC_fracTapDiv2C 4 |
| #define bRF64PIC_fracTapDiv2C 4 |
| #define MSK32RF64PIC_fracTapDiv2C 0x000000F0 |
| |
| #define BA_RF64PIC_IPCM_QPU 0x0011 |
| #define B16RF64PIC_IPCM_QPU 0x0010 |
| #define LSb32RF64PIC_IPCM_QPU 8 |
| #define LSb16RF64PIC_IPCM_QPU 8 |
| #define bRF64PIC_IPCM_QPU 6 |
| #define MSK32RF64PIC_IPCM_QPU 0x00003F00 |
| |
| #define BA_RF64PIC_IPCM_QPV 0x0011 |
| #define B16RF64PIC_IPCM_QPV 0x0010 |
| #define LSb32RF64PIC_IPCM_QPV 14 |
| #define LSb16RF64PIC_IPCM_QPV 14 |
| #define bRF64PIC_IPCM_QPV 6 |
| #define MSK32RF64PIC_IPCM_QPV 0x000FC000 |
| |
| #define BA_RF64PIC_RSVD12 0x0012 |
| #define B16RF64PIC_RSVD12 0x0012 |
| #define LSb32RF64PIC_RSVD12 20 |
| #define LSb16RF64PIC_RSVD12 4 |
| #define bRF64PIC_RSVD12 12 |
| #define MSK32RF64PIC_RSVD12 0xFFF00000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64PIC_PQUANT 0x0014 |
| #define B16RF64PIC_PQUANT 0x0014 |
| #define LSb32RF64PIC_PQUANT 0 |
| #define LSb16RF64PIC_PQUANT 0 |
| #define bRF64PIC_PQUANT 5 |
| #define MSK32RF64PIC_PQUANT 0x0000001F |
| |
| #define BA_RF64PIC_FRFD 0x0014 |
| #define B16RF64PIC_FRFD 0x0014 |
| #define LSb32RF64PIC_FRFD 5 |
| #define LSb16RF64PIC_FRFD 5 |
| #define bRF64PIC_FRFD 2 |
| #define MSK32RF64PIC_FRFD 0x00000060 |
| |
| #define BA_RF64PIC_BRFD 0x0014 |
| #define B16RF64PIC_BRFD 0x0014 |
| #define LSb32RF64PIC_BRFD 7 |
| #define LSb16RF64PIC_BRFD 7 |
| #define bRF64PIC_BRFD 2 |
| #define MSK32RF64PIC_BRFD 0x00000180 |
| |
| #define BA_RF64PIC_secondFld 0x0015 |
| #define B16RF64PIC_secondFld 0x0014 |
| #define LSb32RF64PIC_secondFld 9 |
| #define LSb16RF64PIC_secondFld 9 |
| #define bRF64PIC_secondFld 1 |
| #define MSK32RF64PIC_secondFld 0x00000200 |
| |
| #define BA_RF64PIC_mvRange 0x0015 |
| #define B16RF64PIC_mvRange 0x0014 |
| #define LSb32RF64PIC_mvRange 10 |
| #define LSb16RF64PIC_mvRange 10 |
| #define bRF64PIC_mvRange 2 |
| #define MSK32RF64PIC_mvRange 0x00000C00 |
| |
| #define BA_RF64PIC_hybridMvThres 0x0015 |
| #define B16RF64PIC_hybridMvThres 0x0014 |
| #define LSb32RF64PIC_hybridMvThres 12 |
| #define LSb16RF64PIC_hybridMvThres 12 |
| #define bRF64PIC_hybridMvThres 1 |
| #define MSK32RF64PIC_hybridMvThres 0x00001000 |
| |
| #define BA_RF64PIC_firstMbIntra 0x0015 |
| #define B16RF64PIC_firstMbIntra 0x0014 |
| #define LSb32RF64PIC_firstMbIntra 13 |
| #define LSb16RF64PIC_firstMbIntra 13 |
| #define bRF64PIC_firstMbIntra 1 |
| #define MSK32RF64PIC_firstMbIntra 0x00002000 |
| |
| #define BA_RF64PIC_halfPixel 0x0015 |
| #define B16RF64PIC_halfPixel 0x0014 |
| #define LSb32RF64PIC_halfPixel 14 |
| #define LSb16RF64PIC_halfPixel 14 |
| #define bRF64PIC_halfPixel 1 |
| #define MSK32RF64PIC_halfPixel 0x00004000 |
| |
| #define BA_RF64PIC_forwRefInterlace 0x0015 |
| #define B16RF64PIC_forwRefInterlace 0x0014 |
| #define LSb32RF64PIC_forwRefInterlace 15 |
| #define LSb16RF64PIC_forwRefInterlace 15 |
| #define bRF64PIC_forwRefInterlace 1 |
| #define MSK32RF64PIC_forwRefInterlace 0x00008000 |
| |
| #define BA_RF64PIC_backRefInterlace 0x0016 |
| #define B16RF64PIC_backRefInterlace 0x0016 |
| #define LSb32RF64PIC_backRefInterlace 16 |
| #define LSb16RF64PIC_backRefInterlace 0 |
| #define bRF64PIC_backRefInterlace 1 |
| #define MSK32RF64PIC_backRefInterlace 0x00010000 |
| |
| #define BA_RF64PIC_FrmTransACSet 0x0016 |
| #define B16RF64PIC_FrmTransACSet 0x0016 |
| #define LSb32RF64PIC_FrmTransACSet 17 |
| #define LSb16RF64PIC_FrmTransACSet 1 |
| #define bRF64PIC_FrmTransACSet 2 |
| #define MSK32RF64PIC_FrmTransACSet 0x00060000 |
| |
| #define BA_RF64PIC_FrmTransACSet2 0x0016 |
| #define B16RF64PIC_FrmTransACSet2 0x0016 |
| #define LSb32RF64PIC_FrmTransACSet2 19 |
| #define LSb16RF64PIC_FrmTransACSet2 3 |
| #define bRF64PIC_FrmTransACSet2 2 |
| #define MSK32RF64PIC_FrmTransACSet2 0x00180000 |
| |
| #define BA_RF64PIC_PQIndexGT8 0x0016 |
| #define B16RF64PIC_PQIndexGT8 0x0016 |
| #define LSb32RF64PIC_PQIndexGT8 21 |
| #define LSb16RF64PIC_PQIndexGT8 5 |
| #define bRF64PIC_PQIndexGT8 1 |
| #define MSK32RF64PIC_PQIndexGT8 0x00200000 |
| |
| #define BA_RF64PIC_EscapeTBL 0x0016 |
| #define B16RF64PIC_EscapeTBL 0x0016 |
| #define LSb32RF64PIC_EscapeTBL 22 |
| #define LSb16RF64PIC_EscapeTBL 6 |
| #define bRF64PIC_EscapeTBL 1 |
| #define MSK32RF64PIC_EscapeTBL 0x00400000 |
| |
| #define BA_RF64PIC_format1 0x0016 |
| #define B16RF64PIC_format1 0x0016 |
| #define LSb32RF64PIC_format1 23 |
| #define LSb16RF64PIC_format1 7 |
| #define bRF64PIC_format1 4 |
| #define MSK32RF64PIC_format1 0x07800000 |
| #define RF64PIC_format1_RV9 0x0 |
| #define RF64PIC_format1_RV8 0x1 |
| #define RF64PIC_format1_vp8 0x2 |
| #define RF64PIC_format1_jpeg 0x3 |
| |
| #define BA_RF64PIC_noReorder 0x0017 |
| #define B16RF64PIC_noReorder 0x0016 |
| #define LSb32RF64PIC_noReorder 27 |
| #define LSb16RF64PIC_noReorder 11 |
| #define bRF64PIC_noReorder 1 |
| #define MSK32RF64PIC_noReorder 0x08000000 |
| |
| #define BA_RF64PIC_iplusModeOn 0x0017 |
| #define B16RF64PIC_iplusModeOn 0x0016 |
| #define LSb32RF64PIC_iplusModeOn 28 |
| #define LSb16RF64PIC_iplusModeOn 12 |
| #define bRF64PIC_iplusModeOn 1 |
| #define MSK32RF64PIC_iplusModeOn 0x10000000 |
| |
| #define BA_RF64PIC_RSVD3 0x0017 |
| #define B16RF64PIC_RSVD3 0x0016 |
| #define LSb32RF64PIC_RSVD3 29 |
| #define LSb16RF64PIC_RSVD3 13 |
| #define bRF64PIC_RSVD3 3 |
| #define MSK32RF64PIC_RSVD3 0xE0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64PIC_RSVD 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_RF64PIC_rIDX2BID 0x0040 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64PIC { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_format(r32) _BFGET_(r32, 2, 0) |
| #define SET32RF64PIC_format(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16RF64PIC_format(r16) _BFGET_(r16, 2, 0) |
| #define SET16RF64PIC_format(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32RF64PIC_cabac(r32) _BFGET_(r32, 3, 3) |
| #define SET32RF64PIC_cabac(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16RF64PIC_cabac(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64PIC_cabac(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64PIC_picType(r32) _BFGET_(r32, 5, 4) |
| #define SET32RF64PIC_picType(r32,v) _BFSET_(r32, 5, 4,v) |
| #define GET16RF64PIC_picType(r16) _BFGET_(r16, 5, 4) |
| #define SET16RF64PIC_picType(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| #define GET32RF64PIC_maxL0(r32) _BFGET_(r32,10, 6) |
| #define SET32RF64PIC_maxL0(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16RF64PIC_maxL0(r16) _BFGET_(r16,10, 6) |
| #define SET16RF64PIC_maxL0(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32RF64PIC_maxL1(r32) _BFGET_(r32,15,11) |
| #define SET32RF64PIC_maxL1(r32,v) _BFSET_(r32,15,11,v) |
| #define GET16RF64PIC_maxL1(r16) _BFGET_(r16,15,11) |
| #define SET16RF64PIC_maxL1(r16,v) _BFSET_(r16,15,11,v) |
| |
| #define GET32RF64PIC_MbaffPic(r32) _BFGET_(r32,16,16) |
| #define SET32RF64PIC_MbaffPic(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16RF64PIC_MbaffPic(r16) _BFGET_(r16, 0, 0) |
| #define SET16RF64PIC_MbaffPic(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32RF64PIC_fieldPic(r32) _BFGET_(r32,17,17) |
| #define SET32RF64PIC_fieldPic(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16RF64PIC_fieldPic(r16) _BFGET_(r16, 1, 1) |
| #define SET16RF64PIC_fieldPic(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32RF64PIC_spatialPred(r32) _BFGET_(r32,18,18) |
| #define SET32RF64PIC_spatialPred(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16RF64PIC_spatialPred(r16) _BFGET_(r16, 2, 2) |
| #define SET16RF64PIC_spatialPred(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32RF64PIC_colPicMbaff(r32) _BFGET_(r32,19,19) |
| #define SET32RF64PIC_colPicMbaff(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16RF64PIC_colPicMbaff(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64PIC_colPicMbaff(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64PIC_colPicField(r32) _BFGET_(r32,20,20) |
| #define SET32RF64PIC_colPicField(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16RF64PIC_colPicField(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64PIC_colPicField(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32RF64PIC_colPicST(r32) _BFGET_(r32,21,21) |
| #define SET32RF64PIC_colPicST(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16RF64PIC_colPicST(r16) _BFGET_(r16, 5, 5) |
| #define SET16RF64PIC_colPicST(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32RF64PIC_AC0Offset(r32) _BFGET_(r32,26,22) |
| #define SET32RF64PIC_AC0Offset(r32,v) _BFSET_(r32,26,22,v) |
| #define GET16RF64PIC_AC0Offset(r16) _BFGET_(r16,10, 6) |
| #define SET16RF64PIC_AC0Offset(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32RF64PIC_BetaOffset(r32) _BFGET_(r32,31,27) |
| #define SET32RF64PIC_BetaOffset(r32,v) _BFSET_(r32,31,27,v) |
| #define GET16RF64PIC_BetaOffset(r16) _BFGET_(r16,15,11) |
| #define SET16RF64PIC_BetaOffset(r16,v) _BFSET_(r16,15,11,v) |
| |
| UNSG32 u_format : 3; |
| UNSG32 u_cabac : 1; |
| UNSG32 u_picType : 2; |
| UNSG32 u_maxL0 : 5; |
| UNSG32 u_maxL1 : 5; |
| UNSG32 u_MbaffPic : 1; |
| UNSG32 u_fieldPic : 1; |
| UNSG32 u_spatialPred : 1; |
| UNSG32 u_colPicMbaff : 1; |
| UNSG32 u_colPicField : 1; |
| UNSG32 u_colPicST : 1; |
| UNSG32 s_AC0Offset : 5; |
| UNSG32 s_BetaOffset : 5; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_dqAcLimit(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64PIC_dqAcLimit(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64PIC_dqAcLimit(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64PIC_dqAcLimit(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64PIC_dqDcLimit(r32) _BFGET_(r32,29,16) |
| #define SET32RF64PIC_dqDcLimit(r32,v) _BFSET_(r32,29,16,v) |
| #define GET16RF64PIC_dqDcLimit(r16) _BFGET_(r16,13, 0) |
| #define SET16RF64PIC_dqDcLimit(r16,v) _BFSET_(r16,13, 0,v) |
| |
| #define GET32RF64PIC_mismatch(r32) _BFGET_(r32,31,30) |
| #define SET32RF64PIC_mismatch(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16RF64PIC_mismatch(r16) _BFGET_(r16,15,14) |
| #define SET16RF64PIC_mismatch(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_dqAcLimit : 16; |
| UNSG32 u_dqDcLimit : 14; |
| UNSG32 u_mismatch : 2; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_picW(r32) _BFGET_(r32,15, 0) |
| #define SET32RF64PIC_picW(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16RF64PIC_picW(r16) _BFGET_(r16,15, 0) |
| #define SET16RF64PIC_picW(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32RF64PIC_picH(r32) _BFGET_(r32,28,16) |
| #define SET32RF64PIC_picH(r32,v) _BFSET_(r32,28,16,v) |
| #define GET16RF64PIC_picH(r16) _BFGET_(r16,12, 0) |
| #define SET16RF64PIC_picH(r16,v) _BFSET_(r16,12, 0,v) |
| |
| #define GET32RF64PIC_btmFldPic(r32) _BFGET_(r32,29,29) |
| #define SET32RF64PIC_btmFldPic(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16RF64PIC_btmFldPic(r16) _BFGET_(r16,13,13) |
| #define SET16RF64PIC_btmFldPic(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64PIC_hint(r32) _BFGET_(r32,31,30) |
| #define SET32RF64PIC_hint(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16RF64PIC_hint(r16) _BFGET_(r16,15,14) |
| #define SET16RF64PIC_hint(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_picW : 16; |
| UNSG32 u_picH : 13; |
| UNSG32 u_btmFldPic : 1; |
| UNSG32 u_hint : 2; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_shiftLumaX(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64PIC_shiftLumaX(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64PIC_shiftLumaX(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64PIC_shiftLumaX(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64PIC_shiftLumaY(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64PIC_shiftLumaY(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64PIC_shiftLumaY(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64PIC_shiftLumaY(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64PIC_shiftChromaX(r32) _BFGET_(r32,23,16) |
| #define SET32RF64PIC_shiftChromaX(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64PIC_shiftChromaX(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64PIC_shiftChromaX(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64PIC_shiftChromaY(r32) _BFGET_(r32,31,24) |
| #define SET32RF64PIC_shiftChromaY(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64PIC_shiftChromaY(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64PIC_shiftChromaY(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_shiftLumaX : 8; |
| UNSG32 u_shiftLumaY : 8; |
| UNSG32 u_shiftChromaX : 8; |
| UNSG32 u_shiftChromaY : 8; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_fracTapDiv2Y(r32) _BFGET_(r32, 3, 0) |
| #define SET32RF64PIC_fracTapDiv2Y(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16RF64PIC_fracTapDiv2Y(r16) _BFGET_(r16, 3, 0) |
| #define SET16RF64PIC_fracTapDiv2Y(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32RF64PIC_fracTapDiv2C(r32) _BFGET_(r32, 7, 4) |
| #define SET32RF64PIC_fracTapDiv2C(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16RF64PIC_fracTapDiv2C(r16) _BFGET_(r16, 7, 4) |
| #define SET16RF64PIC_fracTapDiv2C(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32RF64PIC_IPCM_QPU(r32) _BFGET_(r32,13, 8) |
| #define SET32RF64PIC_IPCM_QPU(r32,v) _BFSET_(r32,13, 8,v) |
| #define GET16RF64PIC_IPCM_QPU(r16) _BFGET_(r16,13, 8) |
| #define SET16RF64PIC_IPCM_QPU(r16,v) _BFSET_(r16,13, 8,v) |
| |
| #define GET32RF64PIC_IPCM_QPV(r32) _BFGET_(r32,19,14) |
| #define SET32RF64PIC_IPCM_QPV(r32,v) _BFSET_(r32,19,14,v) |
| |
| #define GET32RF64PIC_RSVD12(r32) _BFGET_(r32,31,20) |
| #define SET32RF64PIC_RSVD12(r32,v) _BFSET_(r32,31,20,v) |
| #define GET16RF64PIC_RSVD12(r16) _BFGET_(r16,15, 4) |
| #define SET16RF64PIC_RSVD12(r16,v) _BFSET_(r16,15, 4,v) |
| |
| UNSG32 u_fracTapDiv2Y : 4; |
| UNSG32 u_fracTapDiv2C : 4; |
| UNSG32 u_IPCM_QPU : 6; |
| UNSG32 u_IPCM_QPV : 6; |
| UNSG32 u_RSVD12 : 12; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64PIC_PQUANT(r32) _BFGET_(r32, 4, 0) |
| #define SET32RF64PIC_PQUANT(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16RF64PIC_PQUANT(r16) _BFGET_(r16, 4, 0) |
| #define SET16RF64PIC_PQUANT(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32RF64PIC_FRFD(r32) _BFGET_(r32, 6, 5) |
| #define SET32RF64PIC_FRFD(r32,v) _BFSET_(r32, 6, 5,v) |
| #define GET16RF64PIC_FRFD(r16) _BFGET_(r16, 6, 5) |
| #define SET16RF64PIC_FRFD(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32RF64PIC_BRFD(r32) _BFGET_(r32, 8, 7) |
| #define SET32RF64PIC_BRFD(r32,v) _BFSET_(r32, 8, 7,v) |
| #define GET16RF64PIC_BRFD(r16) _BFGET_(r16, 8, 7) |
| #define SET16RF64PIC_BRFD(r16,v) _BFSET_(r16, 8, 7,v) |
| |
| #define GET32RF64PIC_secondFld(r32) _BFGET_(r32, 9, 9) |
| #define SET32RF64PIC_secondFld(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16RF64PIC_secondFld(r16) _BFGET_(r16, 9, 9) |
| #define SET16RF64PIC_secondFld(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32RF64PIC_mvRange(r32) _BFGET_(r32,11,10) |
| #define SET32RF64PIC_mvRange(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16RF64PIC_mvRange(r16) _BFGET_(r16,11,10) |
| #define SET16RF64PIC_mvRange(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32RF64PIC_hybridMvThres(r32) _BFGET_(r32,12,12) |
| #define SET32RF64PIC_hybridMvThres(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16RF64PIC_hybridMvThres(r16) _BFGET_(r16,12,12) |
| #define SET16RF64PIC_hybridMvThres(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64PIC_firstMbIntra(r32) _BFGET_(r32,13,13) |
| #define SET32RF64PIC_firstMbIntra(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16RF64PIC_firstMbIntra(r16) _BFGET_(r16,13,13) |
| #define SET16RF64PIC_firstMbIntra(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64PIC_halfPixel(r32) _BFGET_(r32,14,14) |
| #define SET32RF64PIC_halfPixel(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16RF64PIC_halfPixel(r16) _BFGET_(r16,14,14) |
| #define SET16RF64PIC_halfPixel(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32RF64PIC_forwRefInterlace(r32) _BFGET_(r32,15,15) |
| #define SET32RF64PIC_forwRefInterlace(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16RF64PIC_forwRefInterlace(r16) _BFGET_(r16,15,15) |
| #define SET16RF64PIC_forwRefInterlace(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32RF64PIC_backRefInterlace(r32) _BFGET_(r32,16,16) |
| #define SET32RF64PIC_backRefInterlace(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16RF64PIC_backRefInterlace(r16) _BFGET_(r16, 0, 0) |
| #define SET16RF64PIC_backRefInterlace(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32RF64PIC_FrmTransACSet(r32) _BFGET_(r32,18,17) |
| #define SET32RF64PIC_FrmTransACSet(r32,v) _BFSET_(r32,18,17,v) |
| #define GET16RF64PIC_FrmTransACSet(r16) _BFGET_(r16, 2, 1) |
| #define SET16RF64PIC_FrmTransACSet(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32RF64PIC_FrmTransACSet2(r32) _BFGET_(r32,20,19) |
| #define SET32RF64PIC_FrmTransACSet2(r32,v) _BFSET_(r32,20,19,v) |
| #define GET16RF64PIC_FrmTransACSet2(r16) _BFGET_(r16, 4, 3) |
| #define SET16RF64PIC_FrmTransACSet2(r16,v) _BFSET_(r16, 4, 3,v) |
| |
| #define GET32RF64PIC_PQIndexGT8(r32) _BFGET_(r32,21,21) |
| #define SET32RF64PIC_PQIndexGT8(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16RF64PIC_PQIndexGT8(r16) _BFGET_(r16, 5, 5) |
| #define SET16RF64PIC_PQIndexGT8(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32RF64PIC_EscapeTBL(r32) _BFGET_(r32,22,22) |
| #define SET32RF64PIC_EscapeTBL(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16RF64PIC_EscapeTBL(r16) _BFGET_(r16, 6, 6) |
| #define SET16RF64PIC_EscapeTBL(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32RF64PIC_format1(r32) _BFGET_(r32,26,23) |
| #define SET32RF64PIC_format1(r32,v) _BFSET_(r32,26,23,v) |
| #define GET16RF64PIC_format1(r16) _BFGET_(r16,10, 7) |
| #define SET16RF64PIC_format1(r16,v) _BFSET_(r16,10, 7,v) |
| |
| #define GET32RF64PIC_noReorder(r32) _BFGET_(r32,27,27) |
| #define SET32RF64PIC_noReorder(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16RF64PIC_noReorder(r16) _BFGET_(r16,11,11) |
| #define SET16RF64PIC_noReorder(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32RF64PIC_iplusModeOn(r32) _BFGET_(r32,28,28) |
| #define SET32RF64PIC_iplusModeOn(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16RF64PIC_iplusModeOn(r16) _BFGET_(r16,12,12) |
| #define SET16RF64PIC_iplusModeOn(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64PIC_RSVD3(r32) _BFGET_(r32,31,29) |
| #define SET32RF64PIC_RSVD3(r32,v) _BFSET_(r32,31,29,v) |
| #define GET16RF64PIC_RSVD3(r16) _BFGET_(r16,15,13) |
| #define SET16RF64PIC_RSVD3(r16,v) _BFSET_(r16,15,13,v) |
| |
| UNSG32 u_PQUANT : 5; |
| UNSG32 u_FRFD : 2; |
| UNSG32 u_BRFD : 2; |
| UNSG32 u_secondFld : 1; |
| UNSG32 u_mvRange : 2; |
| UNSG32 u_hybridMvThres : 1; |
| UNSG32 u_firstMbIntra : 1; |
| UNSG32 u_halfPixel : 1; |
| UNSG32 u_forwRefInterlace : 1; |
| UNSG32 u_backRefInterlace : 1; |
| UNSG32 u_FrmTransACSet : 2; |
| UNSG32 u_FrmTransACSet2 : 2; |
| UNSG32 u_PQIndexGT8 : 1; |
| UNSG32 u_EscapeTBL : 1; |
| UNSG32 u_format1 : 4; |
| UNSG32 u_noReorder : 1; |
| UNSG32 u_iplusModeOn : 1; |
| UNSG32 u_RSVD3 : 3; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[5]; |
| /////////////////////////////////////////////////////////// |
| SIE_IDX2BID ie_rIDX2BID; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64PIC; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64PIC_drvrd(SIE_RF64PIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64PIC_drvwr(SIE_RF64PIC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64PIC_reset(SIE_RF64PIC *p); |
| SIGN32 RF64PIC_cmp (SIE_RF64PIC *p, SIE_RF64PIC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64PIC_check(p,pie,pfx,hLOG) RF64PIC_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64PIC_print(p, pfx,hLOG) RF64PIC_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64PIC |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64MB biu (4,4) |
| /// ### |
| /// * RF64 macroblock-level information for ALU64 extensions; padded to 64b |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// ### |
| /// * [0:15] casted from MBPROP[0:15] in decHal_mbLvl.sxw.txt.txt |
| /// ### |
| /// %unsigned 3 BANK |
| /// ### |
| /// * Bank[0] indicates whether current MB is even or odd in an MB pair. |
| /// ### |
| /// %unsigned 1 Inter |
| /// ### |
| /// * Intra (0) or inter (1) macroblock, for DQmatrix selection in dQuant only |
| /// ### |
| /// %unsigned 1 lastMbRow |
| /// ### |
| /// * Current MB row is the last in slice; for VC-1 FOP |
| /// ### |
| /// %unsigned 1 lastMbRowPic |
| /// ### |
| /// * Current MB row is the last in picture; for VC-1 FOP |
| /// ### |
| /// %unsigned 1 RSVD |
| /// ### |
| /// * reserved for bitfield alignment. Removed RF64MB.Mbaff. |
| /// ### |
| /// %unsigned 1 FLD |
| /// ### |
| /// * - if current MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1. |
| /// ### |
| /// %unsigned 1 FLDNeighborA |
| /// ### |
| /// * - if left MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1. |
| /// ### |
| /// %unsigned 1 FLDNeighborB |
| /// ### |
| /// * - if upper MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1. |
| /// ### |
| /// %unsigned 1 FLDNeighborC |
| /// ### |
| /// * - if upper-right MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1. |
| /// ### |
| /// %unsigned 1 FLDNeighborD |
| /// ### |
| /// * - if upper-left MB is MBAFF field MB. Only valid when RF64PIC.MbaffPic = 1. |
| /// ### |
| /// %unsigned 1 NeighborA |
| /// ### |
| /// * From stream-parser to syntax-processor: |
| /// * - if left MB is available |
| /// * From vScope to PCube: |
| /// * - if left MB is available as intra predictor |
| /// ### |
| /// %unsigned 1 NeighborB |
| /// ### |
| /// * From stream-parser to syntax-processor: |
| /// * - if upper MB is available |
| /// * From vScope to PCube: |
| /// * - if upper MB is available as intra predictor |
| /// ### |
| /// %unsigned 1 NeighborC |
| /// ### |
| /// * From stream-parser to syntax-processor: |
| /// * - if upper-right MB is available |
| /// * From vScope to PCube: |
| /// * - if upper-right MB is available as intra predictor |
| /// ### |
| /// %unsigned 1 NeighborD |
| /// ### |
| /// * From stream-parser to syntax-processor: |
| /// * - if upper-left MB is available |
| /// * From vScope to PCube: |
| /// * - if upper-left MB is available as intra predictor |
| /// ### |
| /// %unsigned 8 FopAddr2 |
| /// ### |
| /// * VC-1: base addr 2 for FOP output, 16-byte based |
| /// ### |
| /// %unsigned 8 FopAddr3 |
| /// ### |
| /// * VC-1: base addr 3 for FOP output, 16-byte based |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 8 FopAddr |
| /// ### |
| /// * H.264: FOP output addr |
| /// * VC-1: base addr 0 for FOP output, 16-byte based |
| /// ### |
| /// %unsigned 8 FopAddr1 |
| /// ### |
| /// * VC-1: base addr 1 for FOP output, 16-byte based |
| /// ### |
| /// %unsigned 8 MbX |
| /// ### |
| /// * Current MB index in X direction; |
| /// * from 0 up to ((picW+15)>>4) -1 |
| /// ### |
| /// %unsigned 8 MbY |
| /// ### |
| /// * Current MB index in Y direction; |
| /// * from 0 up to ((picH+15)>>4) -1 |
| /// * End of RF64MB |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64MB |
| #define h_RF64MB (){} |
| |
| #define BA_RF64MB_BANK 0x0000 |
| #define B16RF64MB_BANK 0x0000 |
| #define LSb32RF64MB_BANK 0 |
| #define LSb16RF64MB_BANK 0 |
| #define bRF64MB_BANK 3 |
| #define MSK32RF64MB_BANK 0x00000007 |
| |
| #define BA_RF64MB_Inter 0x0000 |
| #define B16RF64MB_Inter 0x0000 |
| #define LSb32RF64MB_Inter 3 |
| #define LSb16RF64MB_Inter 3 |
| #define bRF64MB_Inter 1 |
| #define MSK32RF64MB_Inter 0x00000008 |
| |
| #define BA_RF64MB_lastMbRow 0x0000 |
| #define B16RF64MB_lastMbRow 0x0000 |
| #define LSb32RF64MB_lastMbRow 4 |
| #define LSb16RF64MB_lastMbRow 4 |
| #define bRF64MB_lastMbRow 1 |
| #define MSK32RF64MB_lastMbRow 0x00000010 |
| |
| #define BA_RF64MB_lastMbRowPic 0x0000 |
| #define B16RF64MB_lastMbRowPic 0x0000 |
| #define LSb32RF64MB_lastMbRowPic 5 |
| #define LSb16RF64MB_lastMbRowPic 5 |
| #define bRF64MB_lastMbRowPic 1 |
| #define MSK32RF64MB_lastMbRowPic 0x00000020 |
| |
| #define BA_RF64MB_RSVD 0x0000 |
| #define B16RF64MB_RSVD 0x0000 |
| #define LSb32RF64MB_RSVD 6 |
| #define LSb16RF64MB_RSVD 6 |
| #define bRF64MB_RSVD 1 |
| #define MSK32RF64MB_RSVD 0x00000040 |
| |
| #define BA_RF64MB_FLD 0x0000 |
| #define B16RF64MB_FLD 0x0000 |
| #define LSb32RF64MB_FLD 7 |
| #define LSb16RF64MB_FLD 7 |
| #define bRF64MB_FLD 1 |
| #define MSK32RF64MB_FLD 0x00000080 |
| |
| #define BA_RF64MB_FLDNeighborA 0x0001 |
| #define B16RF64MB_FLDNeighborA 0x0000 |
| #define LSb32RF64MB_FLDNeighborA 8 |
| #define LSb16RF64MB_FLDNeighborA 8 |
| #define bRF64MB_FLDNeighborA 1 |
| #define MSK32RF64MB_FLDNeighborA 0x00000100 |
| |
| #define BA_RF64MB_FLDNeighborB 0x0001 |
| #define B16RF64MB_FLDNeighborB 0x0000 |
| #define LSb32RF64MB_FLDNeighborB 9 |
| #define LSb16RF64MB_FLDNeighborB 9 |
| #define bRF64MB_FLDNeighborB 1 |
| #define MSK32RF64MB_FLDNeighborB 0x00000200 |
| |
| #define BA_RF64MB_FLDNeighborC 0x0001 |
| #define B16RF64MB_FLDNeighborC 0x0000 |
| #define LSb32RF64MB_FLDNeighborC 10 |
| #define LSb16RF64MB_FLDNeighborC 10 |
| #define bRF64MB_FLDNeighborC 1 |
| #define MSK32RF64MB_FLDNeighborC 0x00000400 |
| |
| #define BA_RF64MB_FLDNeighborD 0x0001 |
| #define B16RF64MB_FLDNeighborD 0x0000 |
| #define LSb32RF64MB_FLDNeighborD 11 |
| #define LSb16RF64MB_FLDNeighborD 11 |
| #define bRF64MB_FLDNeighborD 1 |
| #define MSK32RF64MB_FLDNeighborD 0x00000800 |
| |
| #define BA_RF64MB_NeighborA 0x0001 |
| #define B16RF64MB_NeighborA 0x0000 |
| #define LSb32RF64MB_NeighborA 12 |
| #define LSb16RF64MB_NeighborA 12 |
| #define bRF64MB_NeighborA 1 |
| #define MSK32RF64MB_NeighborA 0x00001000 |
| |
| #define BA_RF64MB_NeighborB 0x0001 |
| #define B16RF64MB_NeighborB 0x0000 |
| #define LSb32RF64MB_NeighborB 13 |
| #define LSb16RF64MB_NeighborB 13 |
| #define bRF64MB_NeighborB 1 |
| #define MSK32RF64MB_NeighborB 0x00002000 |
| |
| #define BA_RF64MB_NeighborC 0x0001 |
| #define B16RF64MB_NeighborC 0x0000 |
| #define LSb32RF64MB_NeighborC 14 |
| #define LSb16RF64MB_NeighborC 14 |
| #define bRF64MB_NeighborC 1 |
| #define MSK32RF64MB_NeighborC 0x00004000 |
| |
| #define BA_RF64MB_NeighborD 0x0001 |
| #define B16RF64MB_NeighborD 0x0000 |
| #define LSb32RF64MB_NeighborD 15 |
| #define LSb16RF64MB_NeighborD 15 |
| #define bRF64MB_NeighborD 1 |
| #define MSK32RF64MB_NeighborD 0x00008000 |
| |
| #define BA_RF64MB_FopAddr2 0x0002 |
| #define B16RF64MB_FopAddr2 0x0002 |
| #define LSb32RF64MB_FopAddr2 16 |
| #define LSb16RF64MB_FopAddr2 0 |
| #define bRF64MB_FopAddr2 8 |
| #define MSK32RF64MB_FopAddr2 0x00FF0000 |
| |
| #define BA_RF64MB_FopAddr3 0x0003 |
| #define B16RF64MB_FopAddr3 0x0002 |
| #define LSb32RF64MB_FopAddr3 24 |
| #define LSb16RF64MB_FopAddr3 8 |
| #define bRF64MB_FopAddr3 8 |
| #define MSK32RF64MB_FopAddr3 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64MB_FopAddr 0x0004 |
| #define B16RF64MB_FopAddr 0x0004 |
| #define LSb32RF64MB_FopAddr 0 |
| #define LSb16RF64MB_FopAddr 0 |
| #define bRF64MB_FopAddr 8 |
| #define MSK32RF64MB_FopAddr 0x000000FF |
| |
| #define BA_RF64MB_FopAddr1 0x0005 |
| #define B16RF64MB_FopAddr1 0x0004 |
| #define LSb32RF64MB_FopAddr1 8 |
| #define LSb16RF64MB_FopAddr1 8 |
| #define bRF64MB_FopAddr1 8 |
| #define MSK32RF64MB_FopAddr1 0x0000FF00 |
| |
| #define BA_RF64MB_MbX 0x0006 |
| #define B16RF64MB_MbX 0x0006 |
| #define LSb32RF64MB_MbX 16 |
| #define LSb16RF64MB_MbX 0 |
| #define bRF64MB_MbX 8 |
| #define MSK32RF64MB_MbX 0x00FF0000 |
| |
| #define BA_RF64MB_MbY 0x0007 |
| #define B16RF64MB_MbY 0x0006 |
| #define LSb32RF64MB_MbY 24 |
| #define LSb16RF64MB_MbY 8 |
| #define bRF64MB_MbY 8 |
| #define MSK32RF64MB_MbY 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64MB { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64MB_BANK(r32) _BFGET_(r32, 2, 0) |
| #define SET32RF64MB_BANK(r32,v) _BFSET_(r32, 2, 0,v) |
| #define GET16RF64MB_BANK(r16) _BFGET_(r16, 2, 0) |
| #define SET16RF64MB_BANK(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32RF64MB_Inter(r32) _BFGET_(r32, 3, 3) |
| #define SET32RF64MB_Inter(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16RF64MB_Inter(r16) _BFGET_(r16, 3, 3) |
| #define SET16RF64MB_Inter(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32RF64MB_lastMbRow(r32) _BFGET_(r32, 4, 4) |
| #define SET32RF64MB_lastMbRow(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16RF64MB_lastMbRow(r16) _BFGET_(r16, 4, 4) |
| #define SET16RF64MB_lastMbRow(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32RF64MB_lastMbRowPic(r32) _BFGET_(r32, 5, 5) |
| #define SET32RF64MB_lastMbRowPic(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16RF64MB_lastMbRowPic(r16) _BFGET_(r16, 5, 5) |
| #define SET16RF64MB_lastMbRowPic(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32RF64MB_RSVD(r32) _BFGET_(r32, 6, 6) |
| #define SET32RF64MB_RSVD(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16RF64MB_RSVD(r16) _BFGET_(r16, 6, 6) |
| #define SET16RF64MB_RSVD(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32RF64MB_FLD(r32) _BFGET_(r32, 7, 7) |
| #define SET32RF64MB_FLD(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16RF64MB_FLD(r16) _BFGET_(r16, 7, 7) |
| #define SET16RF64MB_FLD(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32RF64MB_FLDNeighborA(r32) _BFGET_(r32, 8, 8) |
| #define SET32RF64MB_FLDNeighborA(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16RF64MB_FLDNeighborA(r16) _BFGET_(r16, 8, 8) |
| #define SET16RF64MB_FLDNeighborA(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32RF64MB_FLDNeighborB(r32) _BFGET_(r32, 9, 9) |
| #define SET32RF64MB_FLDNeighborB(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16RF64MB_FLDNeighborB(r16) _BFGET_(r16, 9, 9) |
| #define SET16RF64MB_FLDNeighborB(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32RF64MB_FLDNeighborC(r32) _BFGET_(r32,10,10) |
| #define SET32RF64MB_FLDNeighborC(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16RF64MB_FLDNeighborC(r16) _BFGET_(r16,10,10) |
| #define SET16RF64MB_FLDNeighborC(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32RF64MB_FLDNeighborD(r32) _BFGET_(r32,11,11) |
| #define SET32RF64MB_FLDNeighborD(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16RF64MB_FLDNeighborD(r16) _BFGET_(r16,11,11) |
| #define SET16RF64MB_FLDNeighborD(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32RF64MB_NeighborA(r32) _BFGET_(r32,12,12) |
| #define SET32RF64MB_NeighborA(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16RF64MB_NeighborA(r16) _BFGET_(r16,12,12) |
| #define SET16RF64MB_NeighborA(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32RF64MB_NeighborB(r32) _BFGET_(r32,13,13) |
| #define SET32RF64MB_NeighborB(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16RF64MB_NeighborB(r16) _BFGET_(r16,13,13) |
| #define SET16RF64MB_NeighborB(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32RF64MB_NeighborC(r32) _BFGET_(r32,14,14) |
| #define SET32RF64MB_NeighborC(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16RF64MB_NeighborC(r16) _BFGET_(r16,14,14) |
| #define SET16RF64MB_NeighborC(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32RF64MB_NeighborD(r32) _BFGET_(r32,15,15) |
| #define SET32RF64MB_NeighborD(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16RF64MB_NeighborD(r16) _BFGET_(r16,15,15) |
| #define SET16RF64MB_NeighborD(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32RF64MB_FopAddr2(r32) _BFGET_(r32,23,16) |
| #define SET32RF64MB_FopAddr2(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64MB_FopAddr2(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MB_FopAddr2(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MB_FopAddr3(r32) _BFGET_(r32,31,24) |
| #define SET32RF64MB_FopAddr3(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64MB_FopAddr3(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MB_FopAddr3(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_BANK : 3; |
| UNSG32 u_Inter : 1; |
| UNSG32 u_lastMbRow : 1; |
| UNSG32 u_lastMbRowPic : 1; |
| UNSG32 u_RSVD : 1; |
| UNSG32 u_FLD : 1; |
| UNSG32 u_FLDNeighborA : 1; |
| UNSG32 u_FLDNeighborB : 1; |
| UNSG32 u_FLDNeighborC : 1; |
| UNSG32 u_FLDNeighborD : 1; |
| UNSG32 u_NeighborA : 1; |
| UNSG32 u_NeighborB : 1; |
| UNSG32 u_NeighborC : 1; |
| UNSG32 u_NeighborD : 1; |
| UNSG32 u_FopAddr2 : 8; |
| UNSG32 u_FopAddr3 : 8; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64MB_FopAddr(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64MB_FopAddr(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64MB_FopAddr(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MB_FopAddr(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MB_FopAddr1(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64MB_FopAddr1(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64MB_FopAddr1(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MB_FopAddr1(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64MB_MbX(r32) _BFGET_(r32,23,16) |
| #define SET32RF64MB_MbX(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64MB_MbX(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64MB_MbX(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64MB_MbY(r32) _BFGET_(r32,31,24) |
| #define SET32RF64MB_MbY(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64MB_MbY(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64MB_MbY(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_FopAddr : 8; |
| UNSG32 u_FopAddr1 : 8; |
| UNSG32 u_MbX : 8; |
| UNSG32 u_MbY : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64MB; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64MB_drvrd(SIE_RF64MB *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64MB_drvwr(SIE_RF64MB *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64MB_reset(SIE_RF64MB *p); |
| SIGN32 RF64MB_cmp (SIE_RF64MB *p, SIE_RF64MB *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64MB_check(p,pie,pfx,hLOG) RF64MB_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64MB_print(p, pfx,hLOG) RF64MB_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64MB |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE RF64QP biu (4,4) |
| /// ### |
| /// * QP for neighboring macroblocks; used by FOP only. Padded to 64b |
| /// * Same as {BLK,chroma,RSVD,QP,Qu,Qv} in MBPROP in decHal_mbLvl.sxw.txt.txt |
| /// * Also added DC/ACstep_* for coefficient scaling for DC/AC prediction for MPEG-4/VC-1 |
| /// * [0:31] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 DCstep_Y |
| /// ### |
| /// * VC-1: DCSTEP for coeff scaling in DC prediction (only 6 bits are used) |
| /// * MPEG-4: qstep luma coeff scaling in DC prediction |
| /// ### |
| /// %unsigned 8 ACstep_Y |
| /// ### |
| /// * VC-1: DCSTEP for coeff scaling in AC prediction (only 6 bits are used) |
| /// * MPEG-4: qstep luma coeff scaling in AC prediction |
| /// ### |
| /// %unsigned 8 DCstep_C |
| /// ### |
| /// * VC-1: not used |
| /// * MPEG-4: qstep chroma coeff scaling in DC prediction |
| /// ### |
| /// %unsigned 8 ACstep_C |
| /// ### |
| /// * VC-1: not used |
| /// * MPEG-4: qstep chroma coeff scaling in AC prediction |
| /// * [32:63] |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 8 RSVD8 |
| /// %unsigned 8 QPY |
| /// ### |
| /// * H.264: QP for Luma; 0~51 inclusive |
| /// * MPEG-4: QP_AC (used to determine if coeff scaling is required for AC prediction) |
| /// ### |
| /// %unsigned 8 QPU |
| /// ### |
| /// * H.264: QP fo Cb; 0~51 inclusive |
| /// ### |
| /// %unsigned 8 QPV |
| /// ### |
| /// * H.264: QP for Cr; 0~51 inclusive |
| /// * End of RF64QP |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_RF64QP |
| #define h_RF64QP (){} |
| |
| #define BA_RF64QP_DCstep_Y 0x0000 |
| #define B16RF64QP_DCstep_Y 0x0000 |
| #define LSb32RF64QP_DCstep_Y 0 |
| #define LSb16RF64QP_DCstep_Y 0 |
| #define bRF64QP_DCstep_Y 8 |
| #define MSK32RF64QP_DCstep_Y 0x000000FF |
| |
| #define BA_RF64QP_ACstep_Y 0x0001 |
| #define B16RF64QP_ACstep_Y 0x0000 |
| #define LSb32RF64QP_ACstep_Y 8 |
| #define LSb16RF64QP_ACstep_Y 8 |
| #define bRF64QP_ACstep_Y 8 |
| #define MSK32RF64QP_ACstep_Y 0x0000FF00 |
| |
| #define BA_RF64QP_DCstep_C 0x0002 |
| #define B16RF64QP_DCstep_C 0x0002 |
| #define LSb32RF64QP_DCstep_C 16 |
| #define LSb16RF64QP_DCstep_C 0 |
| #define bRF64QP_DCstep_C 8 |
| #define MSK32RF64QP_DCstep_C 0x00FF0000 |
| |
| #define BA_RF64QP_ACstep_C 0x0003 |
| #define B16RF64QP_ACstep_C 0x0002 |
| #define LSb32RF64QP_ACstep_C 24 |
| #define LSb16RF64QP_ACstep_C 8 |
| #define bRF64QP_ACstep_C 8 |
| #define MSK32RF64QP_ACstep_C 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_RF64QP_RSVD8 0x0004 |
| #define B16RF64QP_RSVD8 0x0004 |
| #define LSb32RF64QP_RSVD8 0 |
| #define LSb16RF64QP_RSVD8 0 |
| #define bRF64QP_RSVD8 8 |
| #define MSK32RF64QP_RSVD8 0x000000FF |
| |
| #define BA_RF64QP_QPY 0x0005 |
| #define B16RF64QP_QPY 0x0004 |
| #define LSb32RF64QP_QPY 8 |
| #define LSb16RF64QP_QPY 8 |
| #define bRF64QP_QPY 8 |
| #define MSK32RF64QP_QPY 0x0000FF00 |
| |
| #define BA_RF64QP_QPU 0x0006 |
| #define B16RF64QP_QPU 0x0006 |
| #define LSb32RF64QP_QPU 16 |
| #define LSb16RF64QP_QPU 0 |
| #define bRF64QP_QPU 8 |
| #define MSK32RF64QP_QPU 0x00FF0000 |
| |
| #define BA_RF64QP_QPV 0x0007 |
| #define B16RF64QP_QPV 0x0006 |
| #define LSb32RF64QP_QPV 24 |
| #define LSb16RF64QP_QPV 8 |
| #define bRF64QP_QPV 8 |
| #define MSK32RF64QP_QPV 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_RF64QP { |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QP_DCstep_Y(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QP_DCstep_Y(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QP_DCstep_Y(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QP_DCstep_Y(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QP_ACstep_Y(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QP_ACstep_Y(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QP_ACstep_Y(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QP_ACstep_Y(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QP_DCstep_C(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QP_DCstep_C(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QP_DCstep_C(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QP_DCstep_C(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QP_ACstep_C(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QP_ACstep_C(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QP_ACstep_C(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QP_ACstep_C(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_DCstep_Y : 8; |
| UNSG32 u_ACstep_Y : 8; |
| UNSG32 u_DCstep_C : 8; |
| UNSG32 u_ACstep_C : 8; |
| /////////////////////////////////////////////////////////// |
| #define GET32RF64QP_RSVD8(r32) _BFGET_(r32, 7, 0) |
| #define SET32RF64QP_RSVD8(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16RF64QP_RSVD8(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QP_RSVD8(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QP_QPY(r32) _BFGET_(r32,15, 8) |
| #define SET32RF64QP_QPY(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16RF64QP_QPY(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QP_QPY(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32RF64QP_QPU(r32) _BFGET_(r32,23,16) |
| #define SET32RF64QP_QPU(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16RF64QP_QPU(r16) _BFGET_(r16, 7, 0) |
| #define SET16RF64QP_QPU(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32RF64QP_QPV(r32) _BFGET_(r32,31,24) |
| #define SET32RF64QP_QPV(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16RF64QP_QPV(r16) _BFGET_(r16,15, 8) |
| #define SET16RF64QP_QPV(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_RSVD8 : 8; |
| UNSG32 u_QPY : 8; |
| UNSG32 u_QPU : 8; |
| UNSG32 u_QPV : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_RF64QP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 RF64QP_drvrd(SIE_RF64QP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 RF64QP_drvwr(SIE_RF64QP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void RF64QP_reset(SIE_RF64QP *p); |
| SIGN32 RF64QP_cmp (SIE_RF64QP *p, SIE_RF64QP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define RF64QP_check(p,pie,pfx,hLOG) RF64QP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define RF64QP_print(p, pfx,hLOG) RF64QP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: RF64QP |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE NLUTCTX biu (4,4) |
| /// ### |
| /// * RF64 context for nLut |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock |
| /// * [64:2047] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD |
| /// $LUT64b RSVD REG [31] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End NLUTCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_NLUTCTX |
| #define h_NLUTCTX (){} |
| |
| #define RA_NLUTCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_NLUTCTX_RSVD 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_NLUTCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_NLUTCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[31]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_NLUTCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 NLUTCTX_drvrd(SIE_NLUTCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 NLUTCTX_drvwr(SIE_NLUTCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void NLUTCTX_reset(SIE_NLUTCTX *p); |
| SIGN32 NLUTCTX_cmp (SIE_NLUTCTX *p, SIE_NLUTCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define NLUTCTX_check(p,pie,pfx,hLOG) NLUTCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define NLUTCTX_print(p, pfx,hLOG) NLUTCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: NLUTCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE BITOPCTX biu (4,4) |
| /// ### |
| /// * Operator format for BitOp extension |
| /// * [0:3583] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 RSVD |
| /// $LUT64b RSVD REG [56] |
| /// ### |
| /// * padding to 3583 |
| /// * [3584:3711] |
| /// ### |
| /// @ 0x001C0 (P) |
| /// # 0x001C0 CTX |
| /// $BITOPRF64 CTX REG |
| /// ### |
| /// * Four BitOp commands, selected by extension ID |
| /// * End BitOpCtx |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_BITOPCTX |
| #define h_BITOPCTX (){} |
| |
| #define RA_BITOPCTX_RSVD 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_BITOPCTX_CTX 0x01C0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_BITOPCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[56]; |
| /////////////////////////////////////////////////////////// |
| SIE_BITOPRF64 ie_CTX; |
| /////////////////////////////////////////////////////////// |
| } SIE_BITOPCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 BITOPCTX_drvrd(SIE_BITOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 BITOPCTX_drvwr(SIE_BITOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void BITOPCTX_reset(SIE_BITOPCTX *p); |
| SIGN32 BITOPCTX_cmp (SIE_BITOPCTX *p, SIE_BITOPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define BITOPCTX_check(p,pie,pfx,hLOG) BITOPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define BITOPCTX_print(p, pfx,hLOG) BITOPCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: BITOPCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE DQCTX biu (4,4) |
| /// ### |
| /// * RF64 context for dQuant |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Reserved for RF64MB |
| /// * [64:191] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 QPX |
| /// $RF64QP QPX REG |
| /// ### |
| /// * QP of current block |
| /// ### |
| /// @ 0x00010 (P) |
| /// # 0x00010 QPN |
| /// $RF64QP QPN REG |
| /// ### |
| /// * QP of neighboring block |
| /// * Used for VC-1/MPEG-4 DC/AC prediction |
| /// * [192:2047] |
| /// ### |
| /// @ 0x00018 (P) |
| /// # 0x00018 RSVD |
| /// $LUT64b RSVD REG [29] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End DQCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_DQCTX |
| #define h_DQCTX (){} |
| |
| #define RA_DQCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_DQCTX_QPX 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_DQCTX_QPN 0x0010 |
| /////////////////////////////////////////////////////////// |
| #define RA_DQCTX_RSVD 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_DQCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_DQCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPX; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPN; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[29]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_DQCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 DQCTX_drvrd(SIE_DQCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 DQCTX_drvwr(SIE_DQCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void DQCTX_reset(SIE_DQCTX *p); |
| SIGN32 DQCTX_cmp (SIE_DQCTX *p, SIE_DQCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define DQCTX_check(p,pie,pfx,hLOG) DQCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define DQCTX_print(p, pfx,hLOG) DQCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: DQCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ASPCTX biu (4,4) |
| /// ### |
| /// * RF64 context for ASP |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Reserved for RF64MB |
| /// * [64:255] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD |
| /// $LUT64b RSVD REG [3] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// ### |
| /// @ 0x00020 (P) |
| /// # 0x00020 D33 |
| /// $HCTX4x4 D33 REG |
| /// ### |
| /// * Y(-1,-1) |
| /// ### |
| /// @ 0x00030 (P) |
| /// # 0x00030 B30 |
| /// $HCTX4x4 B30 REG |
| /// ### |
| /// * Y(0,-1) or U(0,-1) or DCU(0,-1) |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 B31 |
| /// $HCTX4x4 B31 REG |
| /// ### |
| /// * Y(1,-1) or V(0,-1) or DCV(0,-1) |
| /// ### |
| /// @ 0x00050 (P) |
| /// # 0x00050 B32 |
| /// $HCTX4x4 B32 REG |
| /// ### |
| /// * Y(2,-1) or U(1,-1) |
| /// ### |
| /// @ 0x00060 (P) |
| /// # 0x00060 B33 |
| /// $HCTX4x4 B33 REG |
| /// ### |
| /// * Y(3,-1) or V(1,-1) or DCY(0,-1) |
| /// ### |
| /// @ 0x00070 (P) |
| /// # 0x00070 C30 |
| /// $HCTX4x4 C30 REG |
| /// ### |
| /// * Y(4,-1) |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 A03 |
| /// $HCTX4x4 A03 REG |
| /// ### |
| /// * Y(-1,0) |
| /// ### |
| /// @ 0x00090 (P) |
| /// # 0x00090 A12 |
| /// $HCTX4x4 A12 REG |
| /// ### |
| /// * U(-1,0) & V(-1,0) |
| /// ### |
| /// @ 0x000A0 (P) |
| /// # 0x000A0 A13 |
| /// $HCTX4x4 A13 REG |
| /// ### |
| /// * Y(-1,1) |
| /// ### |
| /// @ 0x000B0 (P) |
| /// # 0x000B0 A23 |
| /// $HCTX4x4 A23 REG |
| /// ### |
| /// * Y(-1,2) |
| /// ### |
| /// @ 0x000C0 (P) |
| /// # 0x000C0 A30 |
| /// $HCTX4x4 A30 REG |
| /// ### |
| /// * DCU(-1,0) & DCV(-1,0) |
| /// ### |
| /// @ 0x000D0 (P) |
| /// # 0x000D0 A31 |
| /// $HCTX4x4 A31 REG |
| /// ### |
| /// * DCI(-1,0) & DCY(-1,0) |
| /// ### |
| /// @ 0x000E0 (P) |
| /// # 0x000E0 A32 |
| /// $HCTX4x4 A32 REG |
| /// ### |
| /// * U(-1,1) & V(-1,1) |
| /// ### |
| /// @ 0x000F0 (P) |
| /// # 0x000F0 A33 |
| /// $HCTX4x4 A33 REG |
| /// ### |
| /// * Y(-1,3) |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End ASPCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ASPCTX |
| #define h_ASPCTX (){} |
| |
| #define RA_ASPCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_RSVD 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_D33 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_B30 0x0030 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_B31 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_B32 0x0050 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_B33 0x0060 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_C30 0x0070 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A03 0x0080 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A12 0x0090 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A13 0x00A0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A23 0x00B0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A30 0x00C0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A31 0x00D0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A32 0x00E0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_A33 0x00F0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASPCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ASPCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[3]; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_D33; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B31; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B32; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B33; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_C30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A03; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A12; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A13; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A23; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A31; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A32; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A33; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_ASPCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ASPCTX_drvrd(SIE_ASPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ASPCTX_drvwr(SIE_ASPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ASPCTX_reset(SIE_ASPCTX *p); |
| SIGN32 ASPCTX_cmp (SIE_ASPCTX *p, SIE_ASPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ASPCTX_check(p,pie,pfx,hLOG) ASPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ASPCTX_print(p, pfx,hLOG) ASPCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ASPCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE HCTX_ARR biu (4,4) |
| /// ### |
| /// * 16 * HCTX4x4 for ASP |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 CTX |
| /// $HCTX4x4 CTX REG [16] |
| /// ### |
| /// * HCTX4x4 |
| /// * End HCTX_ARR |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 256B, bits: 2048b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_HCTX_ARR |
| #define h_HCTX_ARR (){} |
| |
| #define RA_HCTX_ARR_CTX 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_HCTX_ARR { |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_CTX[16]; |
| /////////////////////////////////////////////////////////// |
| } SIE_HCTX_ARR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 HCTX_ARR_drvrd(SIE_HCTX_ARR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 HCTX_ARR_drvwr(SIE_HCTX_ARR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void HCTX_ARR_reset(SIE_HCTX_ARR *p); |
| SIGN32 HCTX_ARR_cmp (SIE_HCTX_ARR *p, SIE_HCTX_ARR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define HCTX_ARR_check(p,pie,pfx,hLOG) HCTX_ARR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define HCTX_ARR_print(p, pfx,hLOG) HCTX_ARR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: HCTX_ARR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ASECTX biu (4,4) |
| /// ### |
| /// * RF64 context for ASE |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Reserved for RF64MB |
| /// * [64:255] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD |
| /// $LUT64b RSVD REG [3] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// ### |
| /// @ 0x00020 (P) |
| /// # 0x00020 D33 |
| /// $HCTX4x4 D33 REG |
| /// ### |
| /// * Y(-1,-1) |
| /// ### |
| /// @ 0x00030 (P) |
| /// # 0x00030 B30 |
| /// $HCTX4x4 B30 REG |
| /// ### |
| /// * Y(0,-1) or U(0,-1) or DCU(0,-1) |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 B31 |
| /// $HCTX4x4 B31 REG |
| /// ### |
| /// * Y(1,-1) or V(0,-1) or DCV(0,-1) |
| /// ### |
| /// @ 0x00050 (P) |
| /// # 0x00050 B32 |
| /// $HCTX4x4 B32 REG |
| /// ### |
| /// * Y(2,-1) or U(1,-1) |
| /// ### |
| /// @ 0x00060 (P) |
| /// # 0x00060 B33 |
| /// $HCTX4x4 B33 REG |
| /// ### |
| /// * Y(3,-1) or V(1,-1) or DCY(0,-1) |
| /// ### |
| /// @ 0x00070 (P) |
| /// # 0x00070 C30 |
| /// $HCTX4x4 C30 REG |
| /// ### |
| /// * Y(4,-1) |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 A03 |
| /// $HCTX4x4 A03 REG |
| /// ### |
| /// * Y(-1,0) |
| /// ### |
| /// @ 0x00090 (P) |
| /// # 0x00090 A12 |
| /// $HCTX4x4 A12 REG |
| /// ### |
| /// * U(-1,0) & V(-1,0) |
| /// ### |
| /// @ 0x000A0 (P) |
| /// # 0x000A0 A13 |
| /// $HCTX4x4 A13 REG |
| /// ### |
| /// * Y(-1,1) |
| /// ### |
| /// @ 0x000B0 (P) |
| /// # 0x000B0 A23 |
| /// $HCTX4x4 A23 REG |
| /// ### |
| /// * Y(-1,2) |
| /// ### |
| /// @ 0x000C0 (P) |
| /// # 0x000C0 A30 |
| /// $HCTX4x4 A30 REG |
| /// ### |
| /// * DCU(-1,0) & DCV(-1,0) |
| /// ### |
| /// @ 0x000D0 (P) |
| /// # 0x000D0 A31 |
| /// $HCTX4x4 A31 REG |
| /// ### |
| /// * DCI(-1,0) & DCY(-1,0) |
| /// ### |
| /// @ 0x000E0 (P) |
| /// # 0x000E0 A32 |
| /// $HCTX4x4 A32 REG |
| /// ### |
| /// * U(-1,1) & V(-1,1) |
| /// ### |
| /// @ 0x000F0 (P) |
| /// # 0x000F0 A33 |
| /// $HCTX4x4 A33 REG |
| /// ### |
| /// * Y(-1,3) |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End ASECTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ASECTX |
| #define h_ASECTX (){} |
| |
| #define RA_ASECTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_RSVD 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_D33 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_B30 0x0030 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_B31 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_B32 0x0050 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_B33 0x0060 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_C30 0x0070 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A03 0x0080 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A12 0x0090 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A13 0x00A0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A23 0x00B0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A30 0x00C0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A31 0x00D0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A32 0x00E0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_A33 0x00F0 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASECTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ASECTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[3]; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_D33; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B31; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B32; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_B33; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_C30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A03; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A12; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A13; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A23; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A30; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A31; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A32; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A33; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_ASECTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ASECTX_drvrd(SIE_ASECTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ASECTX_drvwr(SIE_ASECTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ASECTX_reset(SIE_ASECTX *p); |
| SIGN32 ASECTX_cmp (SIE_ASECTX *p, SIE_ASECTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ASECTX_check(p,pie,pfx,hLOG) ASECTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ASECTX_print(p, pfx,hLOG) ASECTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ASECTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ASE_ND_CTX biu (4,4) |
| /// ### |
| /// * RF64 context for ASE (to store Neighbor D in MBAFF mode) |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 RSVD |
| /// $LUT64b RSVD REG |
| /// ### |
| /// * Reserved for RF64MB |
| /// * [64:191] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 A03m |
| /// $HCTX4x4 A03m REG |
| /// ### |
| /// * Neighbor D for when locating at A03 in MBAFF mode |
| /// * [192:255] |
| /// ### |
| /// @ 0x00018 (P) |
| /// # 0x00018 RSVD1 |
| /// $LUT64b RSVD1 REG [32] |
| /// ### |
| /// * [2240:2367] |
| /// ### |
| /// @ 0x00118 (P) |
| /// # 0x00118 A13m |
| /// $HCTX4x4 A13m REG |
| /// ### |
| /// * Neighbor D for when locating at A13 in MBAFF mode |
| /// * [2368:2495] |
| /// ### |
| /// @ 0x00128 (P) |
| /// # 0x00128 A23m |
| /// $HCTX4x4 A23m REG |
| /// ### |
| /// * Neighbor D for when locating at A23 in MBAFF mode |
| /// * [2496:4097] |
| /// ### |
| /// @ 0x00138 (P) |
| /// # 0x00138 RSVD2 |
| /// $LUT64b RSVD2 REG [25] |
| /// ### |
| /// * Padding to the end |
| /// * End ASE_ND_CTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ASE_ND_CTX |
| #define h_ASE_ND_CTX (){} |
| |
| #define RA_ASE_ND_CTX_RSVD 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASE_ND_CTX_A03m 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASE_ND_CTX_RSVD1 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASE_ND_CTX_A13m 0x0118 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASE_ND_CTX_A23m 0x0128 |
| /////////////////////////////////////////////////////////// |
| #define RA_ASE_ND_CTX_RSVD2 0x0138 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ASE_ND_CTX { |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A03m; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD1[32]; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A13m; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_A23m; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD2[25]; |
| /////////////////////////////////////////////////////////// |
| } SIE_ASE_ND_CTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ASE_ND_CTX_drvrd(SIE_ASE_ND_CTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ASE_ND_CTX_drvwr(SIE_ASE_ND_CTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ASE_ND_CTX_reset(SIE_ASE_ND_CTX *p); |
| SIGN32 ASE_ND_CTX_cmp (SIE_ASE_ND_CTX *p, SIE_ASE_ND_CTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ASE_ND_CTX_check(p,pie,pfx,hLOG) ASE_ND_CTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ASE_ND_CTX_print(p, pfx,hLOG) ASE_ND_CTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ASE_ND_CTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE FOPCTX biu (4,4) |
| /// ### |
| /// * RF64 context for FOP |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock |
| /// * [64:447] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 QPX0 |
| /// $RF64QP QPX0 REG |
| /// ### |
| /// * QP of current MB |
| /// ### |
| /// @ 0x00010 (P) |
| /// # 0x00010 QPX1 |
| /// $RF64QP QPX1 REG |
| /// ### |
| /// * QP of current MB |
| /// ### |
| /// @ 0x00018 (P) |
| /// # 0x00018 QPA0 |
| /// $RF64QP QPA0 REG |
| /// ### |
| /// * QP of even MB of left MB pair |
| /// ### |
| /// @ 0x00020 (P) |
| /// # 0x00020 QPA1 |
| /// $RF64QP QPA1 REG |
| /// ### |
| /// * QP of odd MB of left MB pair |
| /// ### |
| /// @ 0x00028 (P) |
| /// # 0x00028 QPB0 |
| /// $RF64QP QPB0 REG |
| /// ### |
| /// * QP of even MB of top MB pair |
| /// ### |
| /// @ 0x00030 (P) |
| /// # 0x00030 QPB1 |
| /// $RF64QP QPB1 REG |
| /// ### |
| /// * QP of odd MB of top MB pair |
| /// * [448:831] |
| /// ### |
| /// @ 0x00038 (P) |
| /// # 0x00038 BlkX |
| /// $HCTX4x4 BlkX REG |
| /// ### |
| /// * Context for current block |
| /// ### |
| /// @ 0x00048 (P) |
| /// # 0x00048 BlkA |
| /// $HCTX4x4 BlkA REG |
| /// ### |
| /// * Context for left neighbor |
| /// ### |
| /// @ 0x00058 (P) |
| /// # 0x00058 BlkB |
| /// $HCTX4x4 BlkB REG |
| /// ### |
| /// * Context for top block |
| /// ### |
| /// @ 0x00068 (P) |
| /// # 0x00068 BlkC |
| /// $HCTX4x4 BlkC REG |
| /// ### |
| /// * Block context used in VC-1 main profile P exception 2. |
| /// * [960:2047] |
| /// ### |
| /// @ 0x00078 (P) |
| /// # 0x00078 RSVD |
| /// $LUT64b RSVD REG [17] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End RF64CTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_FOPCTX |
| #define h_FOPCTX (){} |
| |
| #define RA_FOPCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPX0 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPX1 0x0010 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPA0 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPA1 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPB0 0x0028 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_QPB1 0x0030 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_BlkX 0x0038 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_BlkA 0x0048 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_BlkB 0x0058 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_BlkC 0x0068 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_RSVD 0x0078 |
| /////////////////////////////////////////////////////////// |
| #define RA_FOPCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_FOPCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPX0; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPX1; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPA0; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPA1; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPB0; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64QP ie_QPB1; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_BlkX; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_BlkA; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_BlkB; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_BlkC; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[17]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_FOPCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 FOPCTX_drvrd(SIE_FOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 FOPCTX_drvwr(SIE_FOPCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void FOPCTX_reset(SIE_FOPCTX *p); |
| SIGN32 FOPCTX_cmp (SIE_FOPCTX *p, SIE_FOPCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define FOPCTX_check(p,pie,pfx,hLOG) FOPCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define FOPCTX_print(p, pfx,hLOG) FOPCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: FOPCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pmvScale biu (4,4) |
| /// ### |
| /// * Scaling factors for PMV calculation (for AVS) |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 scaleA |
| /// ### |
| /// * Scaling factor for MVs of block A |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 32 scaleB |
| /// ### |
| /// * Scaling factor for MVs of block B |
| /// * [64:127] |
| /// ### |
| /// @ 0x00008 (P) |
| /// %unsigned 32 scaleC |
| /// ### |
| /// * Scaling factor for MVs of block C |
| /// ### |
| /// @ 0x0000C (P) |
| /// %unsigned 32 scaleD |
| /// ### |
| /// * Scaling factor for MVs of block D |
| /// * End pmvScale |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pmvScale |
| #define h_pmvScale (){} |
| |
| #define BA_pmvScale_scaleA 0x0000 |
| #define B16pmvScale_scaleA 0x0000 |
| #define LSb32pmvScale_scaleA 0 |
| #define LSb16pmvScale_scaleA 0 |
| #define bpmvScale_scaleA 32 |
| #define MSK32pmvScale_scaleA 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_pmvScale_scaleB 0x0004 |
| #define B16pmvScale_scaleB 0x0004 |
| #define LSb32pmvScale_scaleB 0 |
| #define LSb16pmvScale_scaleB 0 |
| #define bpmvScale_scaleB 32 |
| #define MSK32pmvScale_scaleB 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_pmvScale_scaleC 0x0008 |
| #define B16pmvScale_scaleC 0x0008 |
| #define LSb32pmvScale_scaleC 0 |
| #define LSb16pmvScale_scaleC 0 |
| #define bpmvScale_scaleC 32 |
| #define MSK32pmvScale_scaleC 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_pmvScale_scaleD 0x000C |
| #define B16pmvScale_scaleD 0x000C |
| #define LSb32pmvScale_scaleD 0 |
| #define LSb16pmvScale_scaleD 0 |
| #define bpmvScale_scaleD 32 |
| #define MSK32pmvScale_scaleD 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pmvScale { |
| /////////////////////////////////////////////////////////// |
| #define GET32pmvScale_scaleA(r32) _BFGET_(r32,31, 0) |
| #define SET32pmvScale_scaleA(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_scaleA : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32pmvScale_scaleB(r32) _BFGET_(r32,31, 0) |
| #define SET32pmvScale_scaleB(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_scaleB : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32pmvScale_scaleC(r32) _BFGET_(r32,31, 0) |
| #define SET32pmvScale_scaleC(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_scaleC : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32pmvScale_scaleD(r32) _BFGET_(r32,31, 0) |
| #define SET32pmvScale_scaleD(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_scaleD : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_pmvScale; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pmvScale_drvrd(SIE_pmvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pmvScale_drvwr(SIE_pmvScale *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pmvScale_reset(SIE_pmvScale *p); |
| SIGN32 pmvScale_cmp (SIE_pmvScale *p, SIE_pmvScale *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pmvScale_check(p,pie,pfx,hLOG) pmvScale_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pmvScale_print(p, pfx,hLOG) pmvScale_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pmvScale |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE PMVCTX biu (4,4) |
| /// ### |
| /// * RF64 context for PMV |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock |
| /// * [64:447] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD0 |
| /// $LUT64b RSVD0 REG [6] |
| /// ### |
| /// * padding to align block-level context |
| /// * [448:1087] |
| /// ### |
| /// @ 0x00038 (P) |
| /// # 0x00038 BlkX |
| /// $FCTX BlkX REG |
| /// ### |
| /// * Context for current block |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 ChromaMV |
| /// $MV ChromaMV REG |
| /// ### |
| /// * MPEG-4 chroma MV |
| /// ### |
| /// @ 0x00044 (P) |
| /// %unsigned 32 RSVDX |
| /// ### |
| /// * padding to 128-bit |
| /// ### |
| /// @ 0x00048 (P) |
| /// # 0x00048 BlkA |
| /// $FCTX BlkA REG |
| /// ### |
| /// * Context for left neighbor |
| /// ### |
| /// @ 0x00050 (P) |
| /// # 0x00050 BlkD |
| /// $FCTX BlkD REG |
| /// ### |
| /// * Context for upper-left neighbor |
| /// ### |
| /// @ 0x00058 (P) |
| /// # 0x00058 BlkB |
| /// $FCTX BlkB REG |
| /// ### |
| /// * Context for top neighbor |
| /// ### |
| /// @ 0x00060 (P) |
| /// # 0x00060 BlkC |
| /// $FCTX BlkC REG |
| /// ### |
| /// * Context for upper-right neighbor |
| /// ### |
| /// @ 0x00068 (P) |
| /// # 0x00068 BlkA1 |
| /// $FCTX BlkA1 REG |
| /// ### |
| /// * Context for 2nd left neighbor, interlace frame |
| /// ### |
| /// @ 0x00070 (P) |
| /// # 0x00070 BlkD1 |
| /// $FCTX BlkD1 REG |
| /// ### |
| /// * Context for 2nd upper-left neighbor, interlace frame |
| /// ### |
| /// @ 0x00078 (P) |
| /// # 0x00078 BlkB1 |
| /// $FCTX BlkB1 REG |
| /// ### |
| /// * Context for 2nd top neighbor, interlace frame |
| /// ### |
| /// @ 0x00080 (P) |
| /// # 0x00080 BlkC1 |
| /// $FCTX BlkC1 REG |
| /// ### |
| /// * Context for 2nd up-right neighbor, interlace frame only |
| /// * [1088:1727] |
| /// ### |
| /// @ 0x00088 (P) |
| /// %unsigned 32 pmvScale_0i |
| /// %unsigned 32 pmvScale_1i |
| /// %unsigned 32 pmvScale_2i |
| /// %unsigned 32 pmvScale_3i |
| /// %unsigned 32 pmvScale_4i |
| /// %unsigned 32 pmvScale_5i |
| /// %unsigned 32 pmvScale_6i |
| /// %unsigned 32 pmvScale_7i |
| /// %unsigned 32 pmvScale_8i |
| /// %unsigned 32 pmvScale_9i |
| /// %unsigned 32 pmvScale_10i |
| /// %unsigned 32 pmvScale_11i |
| /// %unsigned 32 pmvScale_12i |
| /// %unsigned 32 pmvScale_13i |
| /// %unsigned 32 pmvScale_14i |
| /// %unsigned 32 pmvScale_15i |
| /// %unsigned 32 pmvScale_16i |
| /// %unsigned 32 pmvScale_17i |
| /// %unsigned 32 pmvScale_18i |
| /// %unsigned 32 pmvScale_19i |
| /// ### |
| /// * Scale candidates for PMV. |
| /// * [1727:2047] |
| /// ### |
| /// @ 0x000D8 (P) |
| /// # 0x000D8 RSVD |
| /// $LUT64b RSVD REG [5] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End PMVCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_PMVCTX |
| #define h_PMVCTX (){} |
| |
| #define RA_PMVCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_RSVD0 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkX 0x0038 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_ChromaMV 0x0040 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_PMVCTX_RSVDX 0x0044 |
| #define B16PMVCTX_RSVDX 0x0044 |
| #define LSb32PMVCTX_RSVDX 0 |
| #define LSb16PMVCTX_RSVDX 0 |
| #define bPMVCTX_RSVDX 32 |
| #define MSK32PMVCTX_RSVDX 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkA 0x0048 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkD 0x0050 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkB 0x0058 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkC 0x0060 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkA1 0x0068 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkD1 0x0070 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkB1 0x0078 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_BlkC1 0x0080 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_PMVCTX_pmvScale_0i 0x0088 |
| #define B16PMVCTX_pmvScale_0i 0x0088 |
| #define LSb32PMVCTX_pmvScale_0i 0 |
| #define LSb16PMVCTX_pmvScale_0i 0 |
| #define bPMVCTX_pmvScale_0i 32 |
| #define MSK32PMVCTX_pmvScale_0i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_1i 0x008C |
| #define B16PMVCTX_pmvScale_1i 0x008C |
| #define LSb32PMVCTX_pmvScale_1i 0 |
| #define LSb16PMVCTX_pmvScale_1i 0 |
| #define bPMVCTX_pmvScale_1i 32 |
| #define MSK32PMVCTX_pmvScale_1i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_2i 0x0090 |
| #define B16PMVCTX_pmvScale_2i 0x0090 |
| #define LSb32PMVCTX_pmvScale_2i 0 |
| #define LSb16PMVCTX_pmvScale_2i 0 |
| #define bPMVCTX_pmvScale_2i 32 |
| #define MSK32PMVCTX_pmvScale_2i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_3i 0x0094 |
| #define B16PMVCTX_pmvScale_3i 0x0094 |
| #define LSb32PMVCTX_pmvScale_3i 0 |
| #define LSb16PMVCTX_pmvScale_3i 0 |
| #define bPMVCTX_pmvScale_3i 32 |
| #define MSK32PMVCTX_pmvScale_3i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_4i 0x0098 |
| #define B16PMVCTX_pmvScale_4i 0x0098 |
| #define LSb32PMVCTX_pmvScale_4i 0 |
| #define LSb16PMVCTX_pmvScale_4i 0 |
| #define bPMVCTX_pmvScale_4i 32 |
| #define MSK32PMVCTX_pmvScale_4i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_5i 0x009C |
| #define B16PMVCTX_pmvScale_5i 0x009C |
| #define LSb32PMVCTX_pmvScale_5i 0 |
| #define LSb16PMVCTX_pmvScale_5i 0 |
| #define bPMVCTX_pmvScale_5i 32 |
| #define MSK32PMVCTX_pmvScale_5i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_6i 0x00A0 |
| #define B16PMVCTX_pmvScale_6i 0x00A0 |
| #define LSb32PMVCTX_pmvScale_6i 0 |
| #define LSb16PMVCTX_pmvScale_6i 0 |
| #define bPMVCTX_pmvScale_6i 32 |
| #define MSK32PMVCTX_pmvScale_6i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_7i 0x00A4 |
| #define B16PMVCTX_pmvScale_7i 0x00A4 |
| #define LSb32PMVCTX_pmvScale_7i 0 |
| #define LSb16PMVCTX_pmvScale_7i 0 |
| #define bPMVCTX_pmvScale_7i 32 |
| #define MSK32PMVCTX_pmvScale_7i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_8i 0x00A8 |
| #define B16PMVCTX_pmvScale_8i 0x00A8 |
| #define LSb32PMVCTX_pmvScale_8i 0 |
| #define LSb16PMVCTX_pmvScale_8i 0 |
| #define bPMVCTX_pmvScale_8i 32 |
| #define MSK32PMVCTX_pmvScale_8i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_9i 0x00AC |
| #define B16PMVCTX_pmvScale_9i 0x00AC |
| #define LSb32PMVCTX_pmvScale_9i 0 |
| #define LSb16PMVCTX_pmvScale_9i 0 |
| #define bPMVCTX_pmvScale_9i 32 |
| #define MSK32PMVCTX_pmvScale_9i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_10i 0x00B0 |
| #define B16PMVCTX_pmvScale_10i 0x00B0 |
| #define LSb32PMVCTX_pmvScale_10i 0 |
| #define LSb16PMVCTX_pmvScale_10i 0 |
| #define bPMVCTX_pmvScale_10i 32 |
| #define MSK32PMVCTX_pmvScale_10i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_11i 0x00B4 |
| #define B16PMVCTX_pmvScale_11i 0x00B4 |
| #define LSb32PMVCTX_pmvScale_11i 0 |
| #define LSb16PMVCTX_pmvScale_11i 0 |
| #define bPMVCTX_pmvScale_11i 32 |
| #define MSK32PMVCTX_pmvScale_11i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_12i 0x00B8 |
| #define B16PMVCTX_pmvScale_12i 0x00B8 |
| #define LSb32PMVCTX_pmvScale_12i 0 |
| #define LSb16PMVCTX_pmvScale_12i 0 |
| #define bPMVCTX_pmvScale_12i 32 |
| #define MSK32PMVCTX_pmvScale_12i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_13i 0x00BC |
| #define B16PMVCTX_pmvScale_13i 0x00BC |
| #define LSb32PMVCTX_pmvScale_13i 0 |
| #define LSb16PMVCTX_pmvScale_13i 0 |
| #define bPMVCTX_pmvScale_13i 32 |
| #define MSK32PMVCTX_pmvScale_13i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_14i 0x00C0 |
| #define B16PMVCTX_pmvScale_14i 0x00C0 |
| #define LSb32PMVCTX_pmvScale_14i 0 |
| #define LSb16PMVCTX_pmvScale_14i 0 |
| #define bPMVCTX_pmvScale_14i 32 |
| #define MSK32PMVCTX_pmvScale_14i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_15i 0x00C4 |
| #define B16PMVCTX_pmvScale_15i 0x00C4 |
| #define LSb32PMVCTX_pmvScale_15i 0 |
| #define LSb16PMVCTX_pmvScale_15i 0 |
| #define bPMVCTX_pmvScale_15i 32 |
| #define MSK32PMVCTX_pmvScale_15i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_16i 0x00C8 |
| #define B16PMVCTX_pmvScale_16i 0x00C8 |
| #define LSb32PMVCTX_pmvScale_16i 0 |
| #define LSb16PMVCTX_pmvScale_16i 0 |
| #define bPMVCTX_pmvScale_16i 32 |
| #define MSK32PMVCTX_pmvScale_16i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_17i 0x00CC |
| #define B16PMVCTX_pmvScale_17i 0x00CC |
| #define LSb32PMVCTX_pmvScale_17i 0 |
| #define LSb16PMVCTX_pmvScale_17i 0 |
| #define bPMVCTX_pmvScale_17i 32 |
| #define MSK32PMVCTX_pmvScale_17i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_18i 0x00D0 |
| #define B16PMVCTX_pmvScale_18i 0x00D0 |
| #define LSb32PMVCTX_pmvScale_18i 0 |
| #define LSb16PMVCTX_pmvScale_18i 0 |
| #define bPMVCTX_pmvScale_18i 32 |
| #define MSK32PMVCTX_pmvScale_18i 0xFFFFFFFF |
| |
| #define BA_PMVCTX_pmvScale_19i 0x00D4 |
| #define B16PMVCTX_pmvScale_19i 0x00D4 |
| #define LSb32PMVCTX_pmvScale_19i 0 |
| #define LSb16PMVCTX_pmvScale_19i 0 |
| #define bPMVCTX_pmvScale_19i 32 |
| #define MSK32PMVCTX_pmvScale_19i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_RSVD 0x00D8 |
| /////////////////////////////////////////////////////////// |
| #define RA_PMVCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_PMVCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD0[6]; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkX; |
| /////////////////////////////////////////////////////////// |
| SIE_MV ie_ChromaMV; |
| /////////////////////////////////////////////////////////// |
| #define GET32PMVCTX_RSVDX(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_RSVDX(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_RSVDX : 32; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkA; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkD; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkB; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkC; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkA1; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkD1; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkB1; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkC1; |
| /////////////////////////////////////////////////////////// |
| #define GET32PMVCTX_pmvScale_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_1i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_2i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_2i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_2i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_3i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_3i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_3i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_4i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_4i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_4i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_5i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_5i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_5i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_6i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_6i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_6i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_7i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_7i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_7i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_8i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_8i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_8i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_9i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_9i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_9i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_10i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_10i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_10i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_11i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_11i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_11i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_12i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_12i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_12i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_13i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_13i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_13i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_14i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_14i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_14i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_15i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_15i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_15i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_16i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_16i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_16i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_17i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_17i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_17i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_18i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_18i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_18i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32PMVCTX_pmvScale_19i(r32) _BFGET_(r32,31, 0) |
| #define SET32PMVCTX_pmvScale_19i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_pmvScale_19i : 32; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[5]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_PMVCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 PMVCTX_drvrd(SIE_PMVCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 PMVCTX_drvwr(SIE_PMVCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void PMVCTX_reset(SIE_PMVCTX *p); |
| SIGN32 PMVCTX_cmp (SIE_PMVCTX *p, SIE_PMVCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define PMVCTX_check(p,pie,pfx,hLOG) PMVCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define PMVCTX_print(p, pfx,hLOG) PMVCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: PMVCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE dirMvCTX biu (4,4) |
| /// ### |
| /// * RF64 context for direct mode MV calculation |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Reserved for RF64MB |
| /// * [64:447] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD0 |
| /// $LUT64b RSVD0 REG [6] |
| /// ### |
| /// * padding to align block-level context |
| /// * [448:575] |
| /// ### |
| /// @ 0x00038 (P) |
| /// # 0x00038 BlkX |
| /// $HCTX4x4 BlkX REG |
| /// ### |
| /// * Context of the current block; 128-bit. |
| /// * [576:639] |
| /// ### |
| /// @ 0x00048 (P) |
| /// # 0x00048 BlkCol |
| /// $FCTX BlkCol REG |
| /// ### |
| /// * Context of co-located block; 64-bit. |
| /// * [640:703] |
| /// ### |
| /// @ 0x00050 (P) |
| /// # 0x00050 mvScale |
| /// $dirMvScale mvScale REG |
| /// ### |
| /// * MV scaling factor for temporal direct mode; 64 bits |
| /// * [704:1919] |
| /// ### |
| /// @ 0x00058 (P) |
| /// # 0x00058 RSVD |
| /// $LUT64b RSVD REG [19] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [1920:2047] |
| /// ### |
| /// @ 0x000F0 (P) |
| /// # 0x000F0 MbPMV |
| /// $HCTX4x4 MbPMV REG |
| /// ### |
| /// * Macroblock PMV, for spatial direct mode only |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End dirMvCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_dirMvCTX |
| #define h_dirMvCTX (){} |
| |
| #define RA_dirMvCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_RSVD0 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_BlkX 0x0038 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_BlkCol 0x0048 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_mvScale 0x0050 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_RSVD 0x0058 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_MbPMV 0x00F0 |
| /////////////////////////////////////////////////////////// |
| #define RA_dirMvCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_dirMvCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD0[6]; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_BlkX; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_BlkCol; |
| /////////////////////////////////////////////////////////// |
| SIE_dirMvScale ie_mvScale; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[19]; |
| /////////////////////////////////////////////////////////// |
| SIE_HCTX4x4 ie_MbPMV; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_dirMvCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 dirMvCTX_drvrd(SIE_dirMvCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 dirMvCTX_drvwr(SIE_dirMvCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void dirMvCTX_reset(SIE_dirMvCTX *p); |
| SIGN32 dirMvCTX_cmp (SIE_dirMvCTX *p, SIE_dirMvCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define dirMvCTX_check(p,pie,pfx,hLOG) dirMvCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define dirMvCTX_print(p, pfx,hLOG) dirMvCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: dirMvCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE vcMsgCTX biu (4,4) |
| /// ### |
| /// * RF64 context for the vcMsg extension |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * 64b macroblock-level parameter |
| /// * [64:447] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD0 |
| /// $LUT64b RSVD0 REG [6] |
| /// ### |
| /// * padding to align block-level context |
| /// * [448:511] |
| /// ### |
| /// @ 0x00038 (P) |
| /// # 0x00038 blkX |
| /// $FCTX blkX REG |
| /// ### |
| /// * Motion information context of current partition |
| /// * [512:2047] |
| /// ### |
| /// @ 0x00040 (P) |
| /// # 0x00040 RSVD |
| /// $LUT64b RSVD REG [24] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End vcMsgCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_vcMsgCTX |
| #define h_vcMsgCTX (){} |
| |
| #define RA_vcMsgCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_vcMsgCTX_RSVD0 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_vcMsgCTX_blkX 0x0038 |
| /////////////////////////////////////////////////////////// |
| #define RA_vcMsgCTX_RSVD 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_vcMsgCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_vcMsgCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD0[6]; |
| /////////////////////////////////////////////////////////// |
| SIE_FCTX ie_blkX; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[24]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_vcMsgCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 vcMsgCTX_drvrd(SIE_vcMsgCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 vcMsgCTX_drvwr(SIE_vcMsgCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void vcMsgCTX_reset(SIE_vcMsgCTX *p); |
| SIGN32 vcMsgCTX_cmp (SIE_vcMsgCTX *p, SIE_vcMsgCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define vcMsgCTX_check(p,pie,pfx,hLOG) vcMsgCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define vcMsgCTX_print(p, pfx,hLOG) vcMsgCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: vcMsgCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE vldCTX biu (4,4) |
| /// ### |
| /// * RF64 context for vld |
| /// * [0:63] |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 MB |
| /// $RF64MB MB REG |
| /// ### |
| /// * Macroblock-level information; reprogrammed by FIGO at the start of every macroblock |
| /// * [64:2047] |
| /// ### |
| /// @ 0x00008 (P) |
| /// # 0x00008 RSVD |
| /// $LUT64b RSVD REG [31] |
| /// ### |
| /// * padding to 2048-bit boundary |
| /// * [2048:4095] |
| /// ### |
| /// @ 0x00100 (P) |
| /// # 0x00100 PIC |
| /// $RF64PIC PIC REG |
| /// ### |
| /// * Picture-level Parameters for ALU64 extensions. |
| /// * End vldCTX |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 512B, bits: 4096b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_vldCTX |
| #define h_vldCTX (){} |
| |
| #define RA_vldCTX_MB 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_vldCTX_RSVD 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_vldCTX_PIC 0x0100 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_vldCTX { |
| /////////////////////////////////////////////////////////// |
| SIE_RF64MB ie_MB; |
| /////////////////////////////////////////////////////////// |
| SIE_LUT64b ie_RSVD[31]; |
| /////////////////////////////////////////////////////////// |
| SIE_RF64PIC ie_PIC; |
| /////////////////////////////////////////////////////////// |
| } SIE_vldCTX; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 vldCTX_drvrd(SIE_vldCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 vldCTX_drvwr(SIE_vldCTX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void vldCTX_reset(SIE_vldCTX *p); |
| SIGN32 vldCTX_cmp (SIE_vldCTX *p, SIE_vldCTX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define vldCTX_check(p,pie,pfx,hLOG) vldCTX_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define vldCTX_print(p, pfx,hLOG) vldCTX_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: vldCTX |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ClkRstBiu biu (4,4) |
| /// ### |
| /// * Common Biu Unit used for block level reset and clock gating control |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CRCtl (P) |
| /// ### |
| /// * Clock Reset Control Register |
| /// ### |
| /// %unsigned 1 rst 0x1 |
| /// ### |
| /// * Software reset. The reset signal is active low. |
| /// * 0 -> the block will be under reset. |
| /// * 1-> the block will be out of reset. |
| /// ### |
| /// %unsigned 1 swClk_en 0x1 |
| /// ### |
| /// * Software controlled clock enable. |
| /// * 0 -> The corresponding block will be disabled (gated) |
| /// * 1 -> The corresponding clock will be enabled (ungated) |
| /// ### |
| /// %unsigned 1 dyCG_en 0x1 |
| /// ### |
| /// * This is used to control (enalbe/disable) the HW self dynamic clock gating unit. |
| /// * 0 -> the dynamic clock gating will be disabled (the clock can not be turned off by dynamic clock gating unit). |
| /// * 1 -> the dynamic clock gating will be enabled (the clock can be dynamically turned on/off by the dynamic clock control unit). |
| /// * Here is the glue logic to generate the block level clock enable signal. |
| /// * ClkEn = swClk_en & (~dyCG_en | dyClk_en). |
| /// * swClk_en and dyCG_en are from this biu, and dyClk_en is the signal generated by the dynamic clock control unit. |
| /// * End of ClkRstBiu |
| /// ### |
| /// %% 29 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 3b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ClkRstBiu |
| #define h_ClkRstBiu (){} |
| |
| #define RA_ClkRstBiu_CRCtl 0x0000 |
| |
| #define BA_ClkRstBiu_CRCtl_rst 0x0000 |
| #define B16ClkRstBiu_CRCtl_rst 0x0000 |
| #define LSb32ClkRstBiu_CRCtl_rst 0 |
| #define LSb16ClkRstBiu_CRCtl_rst 0 |
| #define bClkRstBiu_CRCtl_rst 1 |
| #define MSK32ClkRstBiu_CRCtl_rst 0x00000001 |
| |
| #define BA_ClkRstBiu_CRCtl_swClk_en 0x0000 |
| #define B16ClkRstBiu_CRCtl_swClk_en 0x0000 |
| #define LSb32ClkRstBiu_CRCtl_swClk_en 1 |
| #define LSb16ClkRstBiu_CRCtl_swClk_en 1 |
| #define bClkRstBiu_CRCtl_swClk_en 1 |
| #define MSK32ClkRstBiu_CRCtl_swClk_en 0x00000002 |
| |
| #define BA_ClkRstBiu_CRCtl_dyCG_en 0x0000 |
| #define B16ClkRstBiu_CRCtl_dyCG_en 0x0000 |
| #define LSb32ClkRstBiu_CRCtl_dyCG_en 2 |
| #define LSb16ClkRstBiu_CRCtl_dyCG_en 2 |
| #define bClkRstBiu_CRCtl_dyCG_en 1 |
| #define MSK32ClkRstBiu_CRCtl_dyCG_en 0x00000004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ClkRstBiu { |
| /////////////////////////////////////////////////////////// |
| #define GET32ClkRstBiu_CRCtl_rst(r32) _BFGET_(r32, 0, 0) |
| #define SET32ClkRstBiu_CRCtl_rst(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ClkRstBiu_CRCtl_rst(r16) _BFGET_(r16, 0, 0) |
| #define SET16ClkRstBiu_CRCtl_rst(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ClkRstBiu_CRCtl_swClk_en(r32) _BFGET_(r32, 1, 1) |
| #define SET32ClkRstBiu_CRCtl_swClk_en(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ClkRstBiu_CRCtl_swClk_en(r16) _BFGET_(r16, 1, 1) |
| #define SET16ClkRstBiu_CRCtl_swClk_en(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32ClkRstBiu_CRCtl_dyCG_en(r32) _BFGET_(r32, 2, 2) |
| #define SET32ClkRstBiu_CRCtl_dyCG_en(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16ClkRstBiu_CRCtl_dyCG_en(r16) _BFGET_(r16, 2, 2) |
| #define SET16ClkRstBiu_CRCtl_dyCG_en(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define w32ClkRstBiu_CRCtl {\ |
| UNSG32 uCRCtl_rst : 1;\ |
| UNSG32 uCRCtl_swClk_en : 1;\ |
| UNSG32 uCRCtl_dyCG_en : 1;\ |
| UNSG32 RSVDx0_b3 : 29;\ |
| } |
| union { UNSG32 u32ClkRstBiu_CRCtl; |
| struct w32ClkRstBiu_CRCtl; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_ClkRstBiu; |
| |
| typedef union T32ClkRstBiu_CRCtl |
| { UNSG32 u32; |
| struct w32ClkRstBiu_CRCtl; |
| } T32ClkRstBiu_CRCtl; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TClkRstBiu_CRCtl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ClkRstBiu_CRCtl; |
| }; |
| } TClkRstBiu_CRCtl; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ClkRstBiu_drvrd(SIE_ClkRstBiu *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ClkRstBiu_drvwr(SIE_ClkRstBiu *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ClkRstBiu_reset(SIE_ClkRstBiu *p); |
| SIGN32 ClkRstBiu_cmp (SIE_ClkRstBiu *p, SIE_ClkRstBiu *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ClkRstBiu_check(p,pie,pfx,hLOG) ClkRstBiu_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ClkRstBiu_print(p, pfx,hLOG) ClkRstBiu_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ClkRstBiu |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pixFmt_adrMap flat (4,4) |
| /// ### |
| /// * Input descriptor |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 adr (P) |
| /// %unsigned 2 byteAdr |
| /// ### |
| /// * Stuffing bit, not used |
| /// ### |
| /// %unsigned 1 bufFlush 0x0 |
| /// ### |
| /// * Used to flush the current buffer specified by the “id” field. “1” indicates the last write of the current buffer. |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// %unsigned 2 blkX |
| /// ### |
| /// * 4x4 block address |
| /// ### |
| /// %unsigned 11 blkY |
| /// %unsigned 9 MBX |
| /// %unsigned 3 id |
| /// %unsigned 1 selPFU |
| /// ### |
| /// * Should be constant “1” |
| /// * End of pixFmt_idesc |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pixFmt_adrMap |
| #define h_pixFmt_adrMap (){} |
| |
| #define RA_pixFmt_adrMap_adr 0x0000 |
| |
| #define BA_pixFmt_adrMap_adr_byteAdr 0x0000 |
| #define B16pixFmt_adrMap_adr_byteAdr 0x0000 |
| #define LSb32pixFmt_adrMap_adr_byteAdr 0 |
| #define LSb16pixFmt_adrMap_adr_byteAdr 0 |
| #define bpixFmt_adrMap_adr_byteAdr 2 |
| #define MSK32pixFmt_adrMap_adr_byteAdr 0x00000003 |
| |
| #define BA_pixFmt_adrMap_adr_bufFlush 0x0000 |
| #define B16pixFmt_adrMap_adr_bufFlush 0x0000 |
| #define LSb32pixFmt_adrMap_adr_bufFlush 2 |
| #define LSb16pixFmt_adrMap_adr_bufFlush 2 |
| #define bpixFmt_adrMap_adr_bufFlush 1 |
| #define MSK32pixFmt_adrMap_adr_bufFlush 0x00000004 |
| |
| #define BA_pixFmt_adrMap_adr_blkX 0x0000 |
| #define B16pixFmt_adrMap_adr_blkX 0x0000 |
| #define LSb32pixFmt_adrMap_adr_blkX 4 |
| #define LSb16pixFmt_adrMap_adr_blkX 4 |
| #define bpixFmt_adrMap_adr_blkX 2 |
| #define MSK32pixFmt_adrMap_adr_blkX 0x00000030 |
| |
| #define BA_pixFmt_adrMap_adr_blkY 0x0000 |
| #define B16pixFmt_adrMap_adr_blkY 0x0000 |
| #define LSb32pixFmt_adrMap_adr_blkY 6 |
| #define LSb16pixFmt_adrMap_adr_blkY 6 |
| #define bpixFmt_adrMap_adr_blkY 11 |
| #define MSK32pixFmt_adrMap_adr_blkY 0x0001FFC0 |
| |
| #define BA_pixFmt_adrMap_adr_MBX 0x0002 |
| #define B16pixFmt_adrMap_adr_MBX 0x0002 |
| #define LSb32pixFmt_adrMap_adr_MBX 17 |
| #define LSb16pixFmt_adrMap_adr_MBX 1 |
| #define bpixFmt_adrMap_adr_MBX 9 |
| #define MSK32pixFmt_adrMap_adr_MBX 0x03FE0000 |
| |
| #define BA_pixFmt_adrMap_adr_id 0x0003 |
| #define B16pixFmt_adrMap_adr_id 0x0002 |
| #define LSb32pixFmt_adrMap_adr_id 26 |
| #define LSb16pixFmt_adrMap_adr_id 10 |
| #define bpixFmt_adrMap_adr_id 3 |
| #define MSK32pixFmt_adrMap_adr_id 0x1C000000 |
| |
| #define BA_pixFmt_adrMap_adr_selPFU 0x0003 |
| #define B16pixFmt_adrMap_adr_selPFU 0x0002 |
| #define LSb32pixFmt_adrMap_adr_selPFU 29 |
| #define LSb16pixFmt_adrMap_adr_selPFU 13 |
| #define bpixFmt_adrMap_adr_selPFU 1 |
| #define MSK32pixFmt_adrMap_adr_selPFU 0x20000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pixFmt_adrMap { |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_adrMap_adr_byteAdr(r32) _BFGET_(r32, 1, 0) |
| #define SET32pixFmt_adrMap_adr_byteAdr(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16pixFmt_adrMap_adr_byteAdr(r16) _BFGET_(r16, 1, 0) |
| #define SET16pixFmt_adrMap_adr_byteAdr(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32pixFmt_adrMap_adr_bufFlush(r32) _BFGET_(r32, 2, 2) |
| #define SET32pixFmt_adrMap_adr_bufFlush(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16pixFmt_adrMap_adr_bufFlush(r16) _BFGET_(r16, 2, 2) |
| #define SET16pixFmt_adrMap_adr_bufFlush(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pixFmt_adrMap_adr_blkX(r32) _BFGET_(r32, 5, 4) |
| #define SET32pixFmt_adrMap_adr_blkX(r32,v) _BFSET_(r32, 5, 4,v) |
| #define GET16pixFmt_adrMap_adr_blkX(r16) _BFGET_(r16, 5, 4) |
| #define SET16pixFmt_adrMap_adr_blkX(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| #define GET32pixFmt_adrMap_adr_blkY(r32) _BFGET_(r32,16, 6) |
| #define SET32pixFmt_adrMap_adr_blkY(r32,v) _BFSET_(r32,16, 6,v) |
| |
| #define GET32pixFmt_adrMap_adr_MBX(r32) _BFGET_(r32,25,17) |
| #define SET32pixFmt_adrMap_adr_MBX(r32,v) _BFSET_(r32,25,17,v) |
| #define GET16pixFmt_adrMap_adr_MBX(r16) _BFGET_(r16, 9, 1) |
| #define SET16pixFmt_adrMap_adr_MBX(r16,v) _BFSET_(r16, 9, 1,v) |
| |
| #define GET32pixFmt_adrMap_adr_id(r32) _BFGET_(r32,28,26) |
| #define SET32pixFmt_adrMap_adr_id(r32,v) _BFSET_(r32,28,26,v) |
| #define GET16pixFmt_adrMap_adr_id(r16) _BFGET_(r16,12,10) |
| #define SET16pixFmt_adrMap_adr_id(r16,v) _BFSET_(r16,12,10,v) |
| |
| #define GET32pixFmt_adrMap_adr_selPFU(r32) _BFGET_(r32,29,29) |
| #define SET32pixFmt_adrMap_adr_selPFU(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16pixFmt_adrMap_adr_selPFU(r16) _BFGET_(r16,13,13) |
| #define SET16pixFmt_adrMap_adr_selPFU(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define w32pixFmt_adrMap_adr {\ |
| UNSG32 uadr_byteAdr : 2;\ |
| UNSG32 uadr_bufFlush : 1;\ |
| UNSG32 RSVDx0_b3 : 1;\ |
| UNSG32 uadr_blkX : 2;\ |
| UNSG32 uadr_blkY : 11;\ |
| UNSG32 uadr_MBX : 9;\ |
| UNSG32 uadr_id : 3;\ |
| UNSG32 uadr_selPFU : 1;\ |
| UNSG32 RSVDx0_b30 : 2;\ |
| } |
| union { UNSG32 u32pixFmt_adrMap_adr; |
| struct w32pixFmt_adrMap_adr; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pixFmt_adrMap; |
| |
| typedef union T32pixFmt_adrMap_adr |
| { UNSG32 u32; |
| struct w32pixFmt_adrMap_adr; |
| } T32pixFmt_adrMap_adr; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpixFmt_adrMap_adr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_adrMap_adr; |
| }; |
| } TpixFmt_adrMap_adr; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pixFmt_adrMap_drvrd(SIE_pixFmt_adrMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pixFmt_adrMap_drvwr(SIE_pixFmt_adrMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pixFmt_adrMap_reset(SIE_pixFmt_adrMap *p); |
| SIGN32 pixFmt_adrMap_cmp (SIE_pixFmt_adrMap *p, SIE_pixFmt_adrMap *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pixFmt_adrMap_check(p,pie,pfx,hLOG) pixFmt_adrMap_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pixFmt_adrMap_print(p, pfx,hLOG) pixFmt_adrMap_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pixFmt_adrMap |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pixFmt_idesc biu (4,4) |
| /// ### |
| /// * Input descriptor |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 desc (P) |
| /// %unsigned 12 baseAdr 0x0 |
| /// ### |
| /// * The base address of the input buffer as for the internal sram, In the unit of 8x4 tile (256-bit), support upto 128KB |
| /// * Note: baseAdr should be two tiles aligned (baseAdr[0]) should always be 0, and HW will ignore this bit |
| /// * Currently, the memory size is 512 tiles, hence only baseAdr[8:0] is used. |
| /// ### |
| /// %unsigned 3 tileStrideB 0x2 |
| /// ### |
| /// * TileStide = 1 << tileStrideB. |
| /// * TielStride/2 is the width in tile for one of the working buffer. |
| /// ### |
| /// %unsigned 4 numRow 0x0 |
| /// ### |
| /// * Number of tile rows for the MB |
| /// * tileStride * numRow will be the whole buffer size in tile. |
| /// * Note:For tile mode, the internal buffer is used as 2D buffer, and for byPass mode, the numRow should be set to 1. |
| /// ### |
| /// %unsigned 2 inFmt |
| /// : byPass 0x0 |
| /// : tile 0x1 |
| /// ### |
| /// * For byPass mode, for any in-consecutive address write,will cause the buffer flush. |
| /// ### |
| /// %unsigned 2 lineOrder |
| /// : 0123 0x0 |
| /// : 0213 0x1 |
| /// ### |
| /// * lastTile |
| /// * (P) |
| /// * 24 |
| /// * adr |
| /// * Byte address, should be tile aligned. |
| /// * This is used for the internal buffer flush purpose. For byPass mode, any two consecutive tile with different address will cause the previously accumulated data get flushed. |
| /// * End of pixFmt_idesc |
| /// ### |
| /// %% 9 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 23b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pixFmt_idesc |
| #define h_pixFmt_idesc (){} |
| |
| #define RA_pixFmt_idesc_desc 0x0000 |
| |
| #define BA_pixFmt_idesc_desc_baseAdr 0x0000 |
| #define B16pixFmt_idesc_desc_baseAdr 0x0000 |
| #define LSb32pixFmt_idesc_desc_baseAdr 0 |
| #define LSb16pixFmt_idesc_desc_baseAdr 0 |
| #define bpixFmt_idesc_desc_baseAdr 12 |
| #define MSK32pixFmt_idesc_desc_baseAdr 0x00000FFF |
| |
| #define BA_pixFmt_idesc_desc_tileStrideB 0x0001 |
| #define B16pixFmt_idesc_desc_tileStrideB 0x0000 |
| #define LSb32pixFmt_idesc_desc_tileStrideB 12 |
| #define LSb16pixFmt_idesc_desc_tileStrideB 12 |
| #define bpixFmt_idesc_desc_tileStrideB 3 |
| #define MSK32pixFmt_idesc_desc_tileStrideB 0x00007000 |
| |
| #define BA_pixFmt_idesc_desc_numRow 0x0001 |
| #define B16pixFmt_idesc_desc_numRow 0x0000 |
| #define LSb32pixFmt_idesc_desc_numRow 15 |
| #define LSb16pixFmt_idesc_desc_numRow 15 |
| #define bpixFmt_idesc_desc_numRow 4 |
| #define MSK32pixFmt_idesc_desc_numRow 0x00078000 |
| |
| #define BA_pixFmt_idesc_desc_inFmt 0x0002 |
| #define B16pixFmt_idesc_desc_inFmt 0x0002 |
| #define LSb32pixFmt_idesc_desc_inFmt 19 |
| #define LSb16pixFmt_idesc_desc_inFmt 3 |
| #define bpixFmt_idesc_desc_inFmt 2 |
| #define MSK32pixFmt_idesc_desc_inFmt 0x00180000 |
| #define pixFmt_idesc_desc_inFmt_byPass 0x0 |
| #define pixFmt_idesc_desc_inFmt_tile 0x1 |
| |
| #define BA_pixFmt_idesc_desc_lineOrder 0x0002 |
| #define B16pixFmt_idesc_desc_lineOrder 0x0002 |
| #define LSb32pixFmt_idesc_desc_lineOrder 21 |
| #define LSb16pixFmt_idesc_desc_lineOrder 5 |
| #define bpixFmt_idesc_desc_lineOrder 2 |
| #define MSK32pixFmt_idesc_desc_lineOrder 0x00600000 |
| #define pixFmt_idesc_desc_lineOrder_0123 0x0 |
| #define pixFmt_idesc_desc_lineOrder_0213 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pixFmt_idesc { |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_idesc_desc_baseAdr(r32) _BFGET_(r32,11, 0) |
| #define SET32pixFmt_idesc_desc_baseAdr(r32,v) _BFSET_(r32,11, 0,v) |
| #define GET16pixFmt_idesc_desc_baseAdr(r16) _BFGET_(r16,11, 0) |
| #define SET16pixFmt_idesc_desc_baseAdr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32pixFmt_idesc_desc_tileStrideB(r32) _BFGET_(r32,14,12) |
| #define SET32pixFmt_idesc_desc_tileStrideB(r32,v) _BFSET_(r32,14,12,v) |
| #define GET16pixFmt_idesc_desc_tileStrideB(r16) _BFGET_(r16,14,12) |
| #define SET16pixFmt_idesc_desc_tileStrideB(r16,v) _BFSET_(r16,14,12,v) |
| |
| #define GET32pixFmt_idesc_desc_numRow(r32) _BFGET_(r32,18,15) |
| #define SET32pixFmt_idesc_desc_numRow(r32,v) _BFSET_(r32,18,15,v) |
| |
| #define GET32pixFmt_idesc_desc_inFmt(r32) _BFGET_(r32,20,19) |
| #define SET32pixFmt_idesc_desc_inFmt(r32,v) _BFSET_(r32,20,19,v) |
| #define GET16pixFmt_idesc_desc_inFmt(r16) _BFGET_(r16, 4, 3) |
| #define SET16pixFmt_idesc_desc_inFmt(r16,v) _BFSET_(r16, 4, 3,v) |
| |
| #define GET32pixFmt_idesc_desc_lineOrder(r32) _BFGET_(r32,22,21) |
| #define SET32pixFmt_idesc_desc_lineOrder(r32,v) _BFSET_(r32,22,21,v) |
| #define GET16pixFmt_idesc_desc_lineOrder(r16) _BFGET_(r16, 6, 5) |
| #define SET16pixFmt_idesc_desc_lineOrder(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define w32pixFmt_idesc_desc {\ |
| UNSG32 udesc_baseAdr : 12;\ |
| UNSG32 udesc_tileStrideB : 3;\ |
| UNSG32 udesc_numRow : 4;\ |
| UNSG32 udesc_inFmt : 2;\ |
| UNSG32 udesc_lineOrder : 2;\ |
| UNSG32 RSVDx0_b23 : 9;\ |
| } |
| union { UNSG32 u32pixFmt_idesc_desc; |
| struct w32pixFmt_idesc_desc; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pixFmt_idesc; |
| |
| typedef union T32pixFmt_idesc_desc |
| { UNSG32 u32; |
| struct w32pixFmt_idesc_desc; |
| } T32pixFmt_idesc_desc; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpixFmt_idesc_desc |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_idesc_desc; |
| }; |
| } TpixFmt_idesc_desc; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pixFmt_idesc_drvrd(SIE_pixFmt_idesc *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pixFmt_idesc_drvwr(SIE_pixFmt_idesc *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pixFmt_idesc_reset(SIE_pixFmt_idesc *p); |
| SIGN32 pixFmt_idesc_cmp (SIE_pixFmt_idesc *p, SIE_pixFmt_idesc *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pixFmt_idesc_check(p,pie,pfx,hLOG) pixFmt_idesc_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pixFmt_idesc_print(p, pfx,hLOG) pixFmt_idesc_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pixFmt_idesc |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pixFmt_odesc biu (4,4) |
| /// ### |
| /// * Input descriptor |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 base (P) |
| /// %unsigned 32 adr 0x0 |
| /// ### |
| /// * The base address of the frame buffer inside DDR. (Byte address) |
| /// ### |
| /// @ 0x00004 line (P) |
| /// %unsigned 11 stride 0x0 |
| /// ### |
| /// * Line stride for the raster scan frame buffer (32-Byte), which is upto 32KB, or tile pages (4KB). |
| /// ### |
| /// %% 21 # Stuffing bits... |
| /// @ 0x00008 desc (P) |
| /// %unsigned 1 picType 0x0 |
| /// : frame 0x0 |
| /// : field 0x1 |
| /// ### |
| /// * For field mode, the cropping parameter of Y direction need to be adjusted by half. |
| /// ### |
| /// %unsigned 1 tileType |
| /// : progressive 0x0 |
| /// : interleave 0x1 |
| /// ### |
| /// * This bit is only applied to display output. |
| /// * When it is tile-interleaved, the display output should output the line order as 0,4,1,5,2,6,3,7... |
| /// ### |
| /// %unsigned 1 filterType 0x0 |
| /// : progressive 0x0 |
| /// : interleave 0x1 |
| /// ### |
| /// * This is to indicate the filter option, select interleaved or progressive filtering. |
| /// ### |
| /// %unsigned 1 evenOfst 0x0 |
| /// %unsigned 1 oddOfst 0x0 |
| /// %unsigned 3 fltMode 0x0 |
| /// ### |
| /// * Upsampling filter parameters. |
| /// ### |
| /// %unsigned 1 compType 0x1 |
| /// : luma 0x0 |
| /// : chroma 0x1 |
| /// ### |
| /// * For chroma mode, the cropping parameter of Y direction need to be adjusted to half of the luma.Y. |
| /// ### |
| /// %unsigned 3 oFmt |
| /// ### |
| /// * oFmt only applies to the tile input format, and not byPass mode. |
| /// ### |
| /// : Tile_luma 0x0 |
| /// : Tile_chroma 0x0 |
| /// : uyvy_luma 0x1 |
| /// : uyvy_chroma 0x1 |
| /// : 420sp_y 0x2 |
| /// : 420sp_uv 0x2 |
| /// : 420p_y 0x3 |
| /// : 420p_u 0x3 |
| /// : 420p_v 0x4 |
| /// ### |
| /// * For uyvy_luma, the next output descriptor will contain the info for the chroma input buffer. |
| /// * For chroma, the Y direction need to be adjusted for the cropping function. |
| /// * For example, when output ID #3 is uyvy_luma, then output ID #4 should be uyvy_chroma |
| /// ### |
| /// %unsigned 2 pixOrder |
| /// ### |
| /// * For uyvy |
| /// ### |
| /// : uyvy 0x0 |
| /// : vyuy 0x1 |
| /// : yuyv 0x2 |
| /// : yvyu 0x3 |
| /// ### |
| /// * For 420spuv |
| /// ### |
| /// : uv 0x0 |
| /// : vu 0x1 |
| /// %unsigned 4 inID 0x0 |
| /// : NOP 0x0 |
| /// ### |
| /// * If the inID is 'NOP', the output thread is disabled. |
| /// * For UYVY output, inID is pointing to the luma buffer, and the chroma buffer is defined by the next oDesc.inID. |
| /// * Note : inID[3] indicate the validness of the output thread. |
| /// ### |
| /// %unsigned 1 crop_ref |
| /// %unsigned 1 crop_disp |
| /// ### |
| /// * Switch to turn on/off the reference or display cropping. |
| /// * Note : For reference output, only crop_ref can be used. |
| /// * For display output, usually, crop_ref and crop_disp are both enabled. |
| /// ### |
| /// %% 12 # Stuffing bits... |
| /// @ 0x0000C mb (P) |
| /// %unsigned 8 y |
| /// ### |
| /// * Number of lines for the output MB, the unit is in 422 scale. |
| /// ### |
| /// %unsigned 8 yOfst |
| /// ### |
| /// * Number of lines need to be cropped, ie the y position of the output MB in the input MB. For reference, it should be tile (4-pixel) aligned . The unit is in 422 scale. |
| /// * End of pixFmt_odesc |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 79b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pixFmt_odesc |
| #define h_pixFmt_odesc (){} |
| |
| #define RA_pixFmt_odesc_base 0x0000 |
| |
| #define BA_pixFmt_odesc_base_adr 0x0000 |
| #define B16pixFmt_odesc_base_adr 0x0000 |
| #define LSb32pixFmt_odesc_base_adr 0 |
| #define LSb16pixFmt_odesc_base_adr 0 |
| #define bpixFmt_odesc_base_adr 32 |
| #define MSK32pixFmt_odesc_base_adr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_odesc_line 0x0004 |
| |
| #define BA_pixFmt_odesc_line_stride 0x0004 |
| #define B16pixFmt_odesc_line_stride 0x0004 |
| #define LSb32pixFmt_odesc_line_stride 0 |
| #define LSb16pixFmt_odesc_line_stride 0 |
| #define bpixFmt_odesc_line_stride 11 |
| #define MSK32pixFmt_odesc_line_stride 0x000007FF |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_odesc_desc 0x0008 |
| |
| #define BA_pixFmt_odesc_desc_picType 0x0008 |
| #define B16pixFmt_odesc_desc_picType 0x0008 |
| #define LSb32pixFmt_odesc_desc_picType 0 |
| #define LSb16pixFmt_odesc_desc_picType 0 |
| #define bpixFmt_odesc_desc_picType 1 |
| #define MSK32pixFmt_odesc_desc_picType 0x00000001 |
| #define pixFmt_odesc_desc_picType_frame 0x0 |
| #define pixFmt_odesc_desc_picType_field 0x1 |
| |
| #define BA_pixFmt_odesc_desc_tileType 0x0008 |
| #define B16pixFmt_odesc_desc_tileType 0x0008 |
| #define LSb32pixFmt_odesc_desc_tileType 1 |
| #define LSb16pixFmt_odesc_desc_tileType 1 |
| #define bpixFmt_odesc_desc_tileType 1 |
| #define MSK32pixFmt_odesc_desc_tileType 0x00000002 |
| #define pixFmt_odesc_desc_tileType_progressive 0x0 |
| #define pixFmt_odesc_desc_tileType_interleave 0x1 |
| |
| #define BA_pixFmt_odesc_desc_filterType 0x0008 |
| #define B16pixFmt_odesc_desc_filterType 0x0008 |
| #define LSb32pixFmt_odesc_desc_filterType 2 |
| #define LSb16pixFmt_odesc_desc_filterType 2 |
| #define bpixFmt_odesc_desc_filterType 1 |
| #define MSK32pixFmt_odesc_desc_filterType 0x00000004 |
| #define pixFmt_odesc_desc_filterType_progressive 0x0 |
| #define pixFmt_odesc_desc_filterType_interleave 0x1 |
| |
| #define BA_pixFmt_odesc_desc_evenOfst 0x0008 |
| #define B16pixFmt_odesc_desc_evenOfst 0x0008 |
| #define LSb32pixFmt_odesc_desc_evenOfst 3 |
| #define LSb16pixFmt_odesc_desc_evenOfst 3 |
| #define bpixFmt_odesc_desc_evenOfst 1 |
| #define MSK32pixFmt_odesc_desc_evenOfst 0x00000008 |
| |
| #define BA_pixFmt_odesc_desc_oddOfst 0x0008 |
| #define B16pixFmt_odesc_desc_oddOfst 0x0008 |
| #define LSb32pixFmt_odesc_desc_oddOfst 4 |
| #define LSb16pixFmt_odesc_desc_oddOfst 4 |
| #define bpixFmt_odesc_desc_oddOfst 1 |
| #define MSK32pixFmt_odesc_desc_oddOfst 0x00000010 |
| |
| #define BA_pixFmt_odesc_desc_fltMode 0x0008 |
| #define B16pixFmt_odesc_desc_fltMode 0x0008 |
| #define LSb32pixFmt_odesc_desc_fltMode 5 |
| #define LSb16pixFmt_odesc_desc_fltMode 5 |
| #define bpixFmt_odesc_desc_fltMode 3 |
| #define MSK32pixFmt_odesc_desc_fltMode 0x000000E0 |
| |
| #define BA_pixFmt_odesc_desc_compType 0x0009 |
| #define B16pixFmt_odesc_desc_compType 0x0008 |
| #define LSb32pixFmt_odesc_desc_compType 8 |
| #define LSb16pixFmt_odesc_desc_compType 8 |
| #define bpixFmt_odesc_desc_compType 1 |
| #define MSK32pixFmt_odesc_desc_compType 0x00000100 |
| #define pixFmt_odesc_desc_compType_luma 0x0 |
| #define pixFmt_odesc_desc_compType_chroma 0x1 |
| |
| #define BA_pixFmt_odesc_desc_oFmt 0x0009 |
| #define B16pixFmt_odesc_desc_oFmt 0x0008 |
| #define LSb32pixFmt_odesc_desc_oFmt 9 |
| #define LSb16pixFmt_odesc_desc_oFmt 9 |
| #define bpixFmt_odesc_desc_oFmt 3 |
| #define MSK32pixFmt_odesc_desc_oFmt 0x00000E00 |
| #define pixFmt_odesc_desc_oFmt_Tile_luma 0x0 |
| #define pixFmt_odesc_desc_oFmt_Tile_chroma 0x0 |
| #define pixFmt_odesc_desc_oFmt_uyvy_luma 0x1 |
| #define pixFmt_odesc_desc_oFmt_uyvy_chroma 0x1 |
| #define pixFmt_odesc_desc_oFmt_420sp_y 0x2 |
| #define pixFmt_odesc_desc_oFmt_420sp_uv 0x2 |
| #define pixFmt_odesc_desc_oFmt_420p_y 0x3 |
| #define pixFmt_odesc_desc_oFmt_420p_u 0x3 |
| #define pixFmt_odesc_desc_oFmt_420p_v 0x4 |
| |
| #define BA_pixFmt_odesc_desc_pixOrder 0x0009 |
| #define B16pixFmt_odesc_desc_pixOrder 0x0008 |
| #define LSb32pixFmt_odesc_desc_pixOrder 12 |
| #define LSb16pixFmt_odesc_desc_pixOrder 12 |
| #define bpixFmt_odesc_desc_pixOrder 2 |
| #define MSK32pixFmt_odesc_desc_pixOrder 0x00003000 |
| #define pixFmt_odesc_desc_pixOrder_uyvy 0x0 |
| #define pixFmt_odesc_desc_pixOrder_vyuy 0x1 |
| #define pixFmt_odesc_desc_pixOrder_yuyv 0x2 |
| #define pixFmt_odesc_desc_pixOrder_yvyu 0x3 |
| #define pixFmt_odesc_desc_pixOrder_uv 0x0 |
| #define pixFmt_odesc_desc_pixOrder_vu 0x1 |
| |
| #define BA_pixFmt_odesc_desc_inID 0x0009 |
| #define B16pixFmt_odesc_desc_inID 0x0008 |
| #define LSb32pixFmt_odesc_desc_inID 14 |
| #define LSb16pixFmt_odesc_desc_inID 14 |
| #define bpixFmt_odesc_desc_inID 4 |
| #define MSK32pixFmt_odesc_desc_inID 0x0003C000 |
| #define pixFmt_odesc_desc_inID_NOP 0x0 |
| |
| #define BA_pixFmt_odesc_desc_crop_ref 0x000A |
| #define B16pixFmt_odesc_desc_crop_ref 0x000A |
| #define LSb32pixFmt_odesc_desc_crop_ref 18 |
| #define LSb16pixFmt_odesc_desc_crop_ref 2 |
| #define bpixFmt_odesc_desc_crop_ref 1 |
| #define MSK32pixFmt_odesc_desc_crop_ref 0x00040000 |
| |
| #define BA_pixFmt_odesc_desc_crop_disp 0x000A |
| #define B16pixFmt_odesc_desc_crop_disp 0x000A |
| #define LSb32pixFmt_odesc_desc_crop_disp 19 |
| #define LSb16pixFmt_odesc_desc_crop_disp 3 |
| #define bpixFmt_odesc_desc_crop_disp 1 |
| #define MSK32pixFmt_odesc_desc_crop_disp 0x00080000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_odesc_mb 0x000C |
| |
| #define BA_pixFmt_odesc_mb_y 0x000C |
| #define B16pixFmt_odesc_mb_y 0x000C |
| #define LSb32pixFmt_odesc_mb_y 0 |
| #define LSb16pixFmt_odesc_mb_y 0 |
| #define bpixFmt_odesc_mb_y 8 |
| #define MSK32pixFmt_odesc_mb_y 0x000000FF |
| |
| #define BA_pixFmt_odesc_mb_yOfst 0x000D |
| #define B16pixFmt_odesc_mb_yOfst 0x000C |
| #define LSb32pixFmt_odesc_mb_yOfst 8 |
| #define LSb16pixFmt_odesc_mb_yOfst 8 |
| #define bpixFmt_odesc_mb_yOfst 8 |
| #define MSK32pixFmt_odesc_mb_yOfst 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pixFmt_odesc { |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_odesc_base_adr(r32) _BFGET_(r32,31, 0) |
| #define SET32pixFmt_odesc_base_adr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32pixFmt_odesc_base {\ |
| UNSG32 ubase_adr : 32;\ |
| } |
| union { UNSG32 u32pixFmt_odesc_base; |
| struct w32pixFmt_odesc_base; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_odesc_line_stride(r32) _BFGET_(r32,10, 0) |
| #define SET32pixFmt_odesc_line_stride(r32,v) _BFSET_(r32,10, 0,v) |
| #define GET16pixFmt_odesc_line_stride(r16) _BFGET_(r16,10, 0) |
| #define SET16pixFmt_odesc_line_stride(r16,v) _BFSET_(r16,10, 0,v) |
| |
| #define w32pixFmt_odesc_line {\ |
| UNSG32 uline_stride : 11;\ |
| UNSG32 RSVDx4_b11 : 21;\ |
| } |
| union { UNSG32 u32pixFmt_odesc_line; |
| struct w32pixFmt_odesc_line; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_odesc_desc_picType(r32) _BFGET_(r32, 0, 0) |
| #define SET32pixFmt_odesc_desc_picType(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pixFmt_odesc_desc_picType(r16) _BFGET_(r16, 0, 0) |
| #define SET16pixFmt_odesc_desc_picType(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pixFmt_odesc_desc_tileType(r32) _BFGET_(r32, 1, 1) |
| #define SET32pixFmt_odesc_desc_tileType(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16pixFmt_odesc_desc_tileType(r16) _BFGET_(r16, 1, 1) |
| #define SET16pixFmt_odesc_desc_tileType(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32pixFmt_odesc_desc_filterType(r32) _BFGET_(r32, 2, 2) |
| #define SET32pixFmt_odesc_desc_filterType(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16pixFmt_odesc_desc_filterType(r16) _BFGET_(r16, 2, 2) |
| #define SET16pixFmt_odesc_desc_filterType(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pixFmt_odesc_desc_evenOfst(r32) _BFGET_(r32, 3, 3) |
| #define SET32pixFmt_odesc_desc_evenOfst(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16pixFmt_odesc_desc_evenOfst(r16) _BFGET_(r16, 3, 3) |
| #define SET16pixFmt_odesc_desc_evenOfst(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32pixFmt_odesc_desc_oddOfst(r32) _BFGET_(r32, 4, 4) |
| #define SET32pixFmt_odesc_desc_oddOfst(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16pixFmt_odesc_desc_oddOfst(r16) _BFGET_(r16, 4, 4) |
| #define SET16pixFmt_odesc_desc_oddOfst(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32pixFmt_odesc_desc_fltMode(r32) _BFGET_(r32, 7, 5) |
| #define SET32pixFmt_odesc_desc_fltMode(r32,v) _BFSET_(r32, 7, 5,v) |
| #define GET16pixFmt_odesc_desc_fltMode(r16) _BFGET_(r16, 7, 5) |
| #define SET16pixFmt_odesc_desc_fltMode(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32pixFmt_odesc_desc_compType(r32) _BFGET_(r32, 8, 8) |
| #define SET32pixFmt_odesc_desc_compType(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16pixFmt_odesc_desc_compType(r16) _BFGET_(r16, 8, 8) |
| #define SET16pixFmt_odesc_desc_compType(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32pixFmt_odesc_desc_oFmt(r32) _BFGET_(r32,11, 9) |
| #define SET32pixFmt_odesc_desc_oFmt(r32,v) _BFSET_(r32,11, 9,v) |
| #define GET16pixFmt_odesc_desc_oFmt(r16) _BFGET_(r16,11, 9) |
| #define SET16pixFmt_odesc_desc_oFmt(r16,v) _BFSET_(r16,11, 9,v) |
| |
| #define GET32pixFmt_odesc_desc_pixOrder(r32) _BFGET_(r32,13,12) |
| #define SET32pixFmt_odesc_desc_pixOrder(r32,v) _BFSET_(r32,13,12,v) |
| #define GET16pixFmt_odesc_desc_pixOrder(r16) _BFGET_(r16,13,12) |
| #define SET16pixFmt_odesc_desc_pixOrder(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32pixFmt_odesc_desc_inID(r32) _BFGET_(r32,17,14) |
| #define SET32pixFmt_odesc_desc_inID(r32,v) _BFSET_(r32,17,14,v) |
| |
| #define GET32pixFmt_odesc_desc_crop_ref(r32) _BFGET_(r32,18,18) |
| #define SET32pixFmt_odesc_desc_crop_ref(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16pixFmt_odesc_desc_crop_ref(r16) _BFGET_(r16, 2, 2) |
| #define SET16pixFmt_odesc_desc_crop_ref(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pixFmt_odesc_desc_crop_disp(r32) _BFGET_(r32,19,19) |
| #define SET32pixFmt_odesc_desc_crop_disp(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16pixFmt_odesc_desc_crop_disp(r16) _BFGET_(r16, 3, 3) |
| #define SET16pixFmt_odesc_desc_crop_disp(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32pixFmt_odesc_desc {\ |
| UNSG32 udesc_picType : 1;\ |
| UNSG32 udesc_tileType : 1;\ |
| UNSG32 udesc_filterType : 1;\ |
| UNSG32 udesc_evenOfst : 1;\ |
| UNSG32 udesc_oddOfst : 1;\ |
| UNSG32 udesc_fltMode : 3;\ |
| UNSG32 udesc_compType : 1;\ |
| UNSG32 udesc_oFmt : 3;\ |
| UNSG32 udesc_pixOrder : 2;\ |
| UNSG32 udesc_inID : 4;\ |
| UNSG32 udesc_crop_ref : 1;\ |
| UNSG32 udesc_crop_disp : 1;\ |
| UNSG32 RSVDx8_b20 : 12;\ |
| } |
| union { UNSG32 u32pixFmt_odesc_desc; |
| struct w32pixFmt_odesc_desc; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_odesc_mb_y(r32) _BFGET_(r32, 7, 0) |
| #define SET32pixFmt_odesc_mb_y(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16pixFmt_odesc_mb_y(r16) _BFGET_(r16, 7, 0) |
| #define SET16pixFmt_odesc_mb_y(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32pixFmt_odesc_mb_yOfst(r32) _BFGET_(r32,15, 8) |
| #define SET32pixFmt_odesc_mb_yOfst(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16pixFmt_odesc_mb_yOfst(r16) _BFGET_(r16,15, 8) |
| #define SET16pixFmt_odesc_mb_yOfst(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32pixFmt_odesc_mb {\ |
| UNSG32 umb_y : 8;\ |
| UNSG32 umb_yOfst : 8;\ |
| UNSG32 RSVDxC_b16 : 16;\ |
| } |
| union { UNSG32 u32pixFmt_odesc_mb; |
| struct w32pixFmt_odesc_mb; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pixFmt_odesc; |
| |
| typedef union T32pixFmt_odesc_base |
| { UNSG32 u32; |
| struct w32pixFmt_odesc_base; |
| } T32pixFmt_odesc_base; |
| typedef union T32pixFmt_odesc_line |
| { UNSG32 u32; |
| struct w32pixFmt_odesc_line; |
| } T32pixFmt_odesc_line; |
| typedef union T32pixFmt_odesc_desc |
| { UNSG32 u32; |
| struct w32pixFmt_odesc_desc; |
| } T32pixFmt_odesc_desc; |
| typedef union T32pixFmt_odesc_mb |
| { UNSG32 u32; |
| struct w32pixFmt_odesc_mb; |
| } T32pixFmt_odesc_mb; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpixFmt_odesc_base |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_odesc_base; |
| }; |
| } TpixFmt_odesc_base; |
| typedef union TpixFmt_odesc_line |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_odesc_line; |
| }; |
| } TpixFmt_odesc_line; |
| typedef union TpixFmt_odesc_desc |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_odesc_desc; |
| }; |
| } TpixFmt_odesc_desc; |
| typedef union TpixFmt_odesc_mb |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_odesc_mb; |
| }; |
| } TpixFmt_odesc_mb; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pixFmt_odesc_drvrd(SIE_pixFmt_odesc *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pixFmt_odesc_drvwr(SIE_pixFmt_odesc *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pixFmt_odesc_reset(SIE_pixFmt_odesc *p); |
| SIGN32 pixFmt_odesc_cmp (SIE_pixFmt_odesc *p, SIE_pixFmt_odesc *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pixFmt_odesc_check(p,pie,pfx,hLOG) pixFmt_odesc_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pixFmt_odesc_print(p, pfx,hLOG) pixFmt_odesc_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pixFmt_odesc |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pixFmt_ROI biu (4,4) |
| /// ### |
| /// * Range of interest |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ref_tr (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// ### |
| /// * Tile output cropping top-right coordinate, this pixel should fall into the most top-right tile of the top rectangle. |
| /// ### |
| /// @ 0x00004 ref_bl (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// ### |
| /// * Tile output cropping bottom-left coordinate, this pixel should fall into the most bottom-left tile of the bottom rectangle. |
| /// ### |
| /// @ 0x00008 ref_in_t (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// ### |
| /// * Tile output cropping inner top corner coordinate, this pixel should fall into the most bottom-left tile of the top rectangle. |
| /// ### |
| /// @ 0x0000C ref_in_b (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// ### |
| /// * Tile output cropping inner bottom corner coordinate, this pixel should fall into the most top-right tile of the bottom rectangle. |
| /// ### |
| /// @ 0x00010 disp_tr (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// @ 0x00014 disp_bl (P) |
| /// %unsigned 16 x |
| /// %unsigned 16 y |
| /// ### |
| /// * Display ROI region of the top-right and bottom-left location. The unit are in pixel, and x is tile (8-pixel) aligned. Y should be two pixels aligned considering chroma and field output. |
| /// * End of pixFmt_ROI |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 24B, bits: 192b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pixFmt_ROI |
| #define h_pixFmt_ROI (){} |
| |
| #define RA_pixFmt_ROI_ref_tr 0x0000 |
| |
| #define BA_pixFmt_ROI_ref_tr_x 0x0000 |
| #define B16pixFmt_ROI_ref_tr_x 0x0000 |
| #define LSb32pixFmt_ROI_ref_tr_x 0 |
| #define LSb16pixFmt_ROI_ref_tr_x 0 |
| #define bpixFmt_ROI_ref_tr_x 16 |
| #define MSK32pixFmt_ROI_ref_tr_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_ref_tr_y 0x0002 |
| #define B16pixFmt_ROI_ref_tr_y 0x0002 |
| #define LSb32pixFmt_ROI_ref_tr_y 16 |
| #define LSb16pixFmt_ROI_ref_tr_y 0 |
| #define bpixFmt_ROI_ref_tr_y 16 |
| #define MSK32pixFmt_ROI_ref_tr_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_ROI_ref_bl 0x0004 |
| |
| #define BA_pixFmt_ROI_ref_bl_x 0x0004 |
| #define B16pixFmt_ROI_ref_bl_x 0x0004 |
| #define LSb32pixFmt_ROI_ref_bl_x 0 |
| #define LSb16pixFmt_ROI_ref_bl_x 0 |
| #define bpixFmt_ROI_ref_bl_x 16 |
| #define MSK32pixFmt_ROI_ref_bl_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_ref_bl_y 0x0006 |
| #define B16pixFmt_ROI_ref_bl_y 0x0006 |
| #define LSb32pixFmt_ROI_ref_bl_y 16 |
| #define LSb16pixFmt_ROI_ref_bl_y 0 |
| #define bpixFmt_ROI_ref_bl_y 16 |
| #define MSK32pixFmt_ROI_ref_bl_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_ROI_ref_in_t 0x0008 |
| |
| #define BA_pixFmt_ROI_ref_in_t_x 0x0008 |
| #define B16pixFmt_ROI_ref_in_t_x 0x0008 |
| #define LSb32pixFmt_ROI_ref_in_t_x 0 |
| #define LSb16pixFmt_ROI_ref_in_t_x 0 |
| #define bpixFmt_ROI_ref_in_t_x 16 |
| #define MSK32pixFmt_ROI_ref_in_t_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_ref_in_t_y 0x000A |
| #define B16pixFmt_ROI_ref_in_t_y 0x000A |
| #define LSb32pixFmt_ROI_ref_in_t_y 16 |
| #define LSb16pixFmt_ROI_ref_in_t_y 0 |
| #define bpixFmt_ROI_ref_in_t_y 16 |
| #define MSK32pixFmt_ROI_ref_in_t_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_ROI_ref_in_b 0x000C |
| |
| #define BA_pixFmt_ROI_ref_in_b_x 0x000C |
| #define B16pixFmt_ROI_ref_in_b_x 0x000C |
| #define LSb32pixFmt_ROI_ref_in_b_x 0 |
| #define LSb16pixFmt_ROI_ref_in_b_x 0 |
| #define bpixFmt_ROI_ref_in_b_x 16 |
| #define MSK32pixFmt_ROI_ref_in_b_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_ref_in_b_y 0x000E |
| #define B16pixFmt_ROI_ref_in_b_y 0x000E |
| #define LSb32pixFmt_ROI_ref_in_b_y 16 |
| #define LSb16pixFmt_ROI_ref_in_b_y 0 |
| #define bpixFmt_ROI_ref_in_b_y 16 |
| #define MSK32pixFmt_ROI_ref_in_b_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_ROI_disp_tr 0x0010 |
| |
| #define BA_pixFmt_ROI_disp_tr_x 0x0010 |
| #define B16pixFmt_ROI_disp_tr_x 0x0010 |
| #define LSb32pixFmt_ROI_disp_tr_x 0 |
| #define LSb16pixFmt_ROI_disp_tr_x 0 |
| #define bpixFmt_ROI_disp_tr_x 16 |
| #define MSK32pixFmt_ROI_disp_tr_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_disp_tr_y 0x0012 |
| #define B16pixFmt_ROI_disp_tr_y 0x0012 |
| #define LSb32pixFmt_ROI_disp_tr_y 16 |
| #define LSb16pixFmt_ROI_disp_tr_y 0 |
| #define bpixFmt_ROI_disp_tr_y 16 |
| #define MSK32pixFmt_ROI_disp_tr_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmt_ROI_disp_bl 0x0014 |
| |
| #define BA_pixFmt_ROI_disp_bl_x 0x0014 |
| #define B16pixFmt_ROI_disp_bl_x 0x0014 |
| #define LSb32pixFmt_ROI_disp_bl_x 0 |
| #define LSb16pixFmt_ROI_disp_bl_x 0 |
| #define bpixFmt_ROI_disp_bl_x 16 |
| #define MSK32pixFmt_ROI_disp_bl_x 0x0000FFFF |
| |
| #define BA_pixFmt_ROI_disp_bl_y 0x0016 |
| #define B16pixFmt_ROI_disp_bl_y 0x0016 |
| #define LSb32pixFmt_ROI_disp_bl_y 16 |
| #define LSb16pixFmt_ROI_disp_bl_y 0 |
| #define bpixFmt_ROI_disp_bl_y 16 |
| #define MSK32pixFmt_ROI_disp_bl_y 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pixFmt_ROI { |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_ref_tr_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_ref_tr_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_ref_tr_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_tr_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_ref_tr_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_ref_tr_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_ref_tr_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_tr_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_ref_tr {\ |
| UNSG32 uref_tr_x : 16;\ |
| UNSG32 uref_tr_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_ref_tr; |
| struct w32pixFmt_ROI_ref_tr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_ref_bl_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_ref_bl_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_ref_bl_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_bl_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_ref_bl_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_ref_bl_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_ref_bl_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_bl_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_ref_bl {\ |
| UNSG32 uref_bl_x : 16;\ |
| UNSG32 uref_bl_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_ref_bl; |
| struct w32pixFmt_ROI_ref_bl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_ref_in_t_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_ref_in_t_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_ref_in_t_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_in_t_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_ref_in_t_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_ref_in_t_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_ref_in_t_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_in_t_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_ref_in_t {\ |
| UNSG32 uref_in_t_x : 16;\ |
| UNSG32 uref_in_t_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_ref_in_t; |
| struct w32pixFmt_ROI_ref_in_t; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_ref_in_b_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_ref_in_b_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_ref_in_b_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_in_b_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_ref_in_b_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_ref_in_b_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_ref_in_b_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_ref_in_b_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_ref_in_b {\ |
| UNSG32 uref_in_b_x : 16;\ |
| UNSG32 uref_in_b_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_ref_in_b; |
| struct w32pixFmt_ROI_ref_in_b; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_disp_tr_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_disp_tr_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_disp_tr_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_disp_tr_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_disp_tr_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_disp_tr_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_disp_tr_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_disp_tr_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_disp_tr {\ |
| UNSG32 udisp_tr_x : 16;\ |
| UNSG32 udisp_tr_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_disp_tr; |
| struct w32pixFmt_ROI_disp_tr; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmt_ROI_disp_bl_x(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmt_ROI_disp_bl_x(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmt_ROI_disp_bl_x(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_disp_bl_x(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmt_ROI_disp_bl_y(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmt_ROI_disp_bl_y(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmt_ROI_disp_bl_y(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmt_ROI_disp_bl_y(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmt_ROI_disp_bl {\ |
| UNSG32 udisp_bl_x : 16;\ |
| UNSG32 udisp_bl_y : 16;\ |
| } |
| union { UNSG32 u32pixFmt_ROI_disp_bl; |
| struct w32pixFmt_ROI_disp_bl; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pixFmt_ROI; |
| |
| typedef union T32pixFmt_ROI_ref_tr |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_ref_tr; |
| } T32pixFmt_ROI_ref_tr; |
| typedef union T32pixFmt_ROI_ref_bl |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_ref_bl; |
| } T32pixFmt_ROI_ref_bl; |
| typedef union T32pixFmt_ROI_ref_in_t |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_ref_in_t; |
| } T32pixFmt_ROI_ref_in_t; |
| typedef union T32pixFmt_ROI_ref_in_b |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_ref_in_b; |
| } T32pixFmt_ROI_ref_in_b; |
| typedef union T32pixFmt_ROI_disp_tr |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_disp_tr; |
| } T32pixFmt_ROI_disp_tr; |
| typedef union T32pixFmt_ROI_disp_bl |
| { UNSG32 u32; |
| struct w32pixFmt_ROI_disp_bl; |
| } T32pixFmt_ROI_disp_bl; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpixFmt_ROI_ref_tr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_ref_tr; |
| }; |
| } TpixFmt_ROI_ref_tr; |
| typedef union TpixFmt_ROI_ref_bl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_ref_bl; |
| }; |
| } TpixFmt_ROI_ref_bl; |
| typedef union TpixFmt_ROI_ref_in_t |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_ref_in_t; |
| }; |
| } TpixFmt_ROI_ref_in_t; |
| typedef union TpixFmt_ROI_ref_in_b |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_ref_in_b; |
| }; |
| } TpixFmt_ROI_ref_in_b; |
| typedef union TpixFmt_ROI_disp_tr |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_disp_tr; |
| }; |
| } TpixFmt_ROI_disp_tr; |
| typedef union TpixFmt_ROI_disp_bl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmt_ROI_disp_bl; |
| }; |
| } TpixFmt_ROI_disp_bl; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pixFmt_ROI_drvrd(SIE_pixFmt_ROI *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pixFmt_ROI_drvwr(SIE_pixFmt_ROI *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pixFmt_ROI_reset(SIE_pixFmt_ROI *p); |
| SIGN32 pixFmt_ROI_cmp (SIE_pixFmt_ROI *p, SIE_pixFmt_ROI *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pixFmt_ROI_check(p,pie,pfx,hLOG) pixFmt_ROI_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pixFmt_ROI_print(p, pfx,hLOG) pixFmt_ROI_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pixFmt_ROI |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pixFmtReg biu (4,4) |
| /// ### |
| /// * Input descriptor |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 idesc |
| /// $pixFmt_idesc idesc REG [8] |
| /// @ 0x00020 (P) |
| /// # 0x00020 odesc |
| /// $pixFmt_odesc odesc REG [8] |
| /// ### |
| /// * Support upto 8 output desciptor |
| /// ### |
| /// @ 0x000A0 (P) |
| /// # 0x000A0 roi |
| /// $pixFmt_ROI roi REG |
| /// @ 0x000B8 flt (P) |
| /// %unsigned 16 ty 0x0 |
| /// %unsigned 16 by 0x0 |
| /// ### |
| /// * Indicating the top and bottom line for the chroma upsampling. Disabled when both of them are “0”. |
| /// ### |
| /// @ 0x000BC disp (P) |
| /// ### |
| /// * This is used to configure the range reduction or mapping for VC1, it only applied to the pixels for display. |
| /// ### |
| /// %unsigned 1 rangeMapYflag 0x0 |
| /// ### |
| /// * Range mapping is on for Luma of current picture |
| /// ### |
| /// %unsigned 3 rangeMapY 0x0 |
| /// ### |
| /// * Range mapping scaling factor for Luma |
| /// ### |
| /// %unsigned 1 rangeMapUVflag 0x0 |
| /// ### |
| /// * Range mapping is on for Chroma of current picture |
| /// ### |
| /// %unsigned 3 rangeMapUV 0x0 |
| /// ### |
| /// * Range mapping scaling factor for Chroma |
| /// ### |
| /// %unsigned 1 rangeRed 0x0 |
| /// ### |
| /// * range reduction is on for current picture |
| /// ### |
| /// %unsigned 1 ROI 0x0 |
| /// ### |
| /// * This register can be replaced by the ROI |
| /// * 0: output all MB row |
| /// * 1: output ROI only |
| /// ### |
| /// %% 22 # Stuffing bits... |
| /// @ 0x000C0 np_cfg (P) |
| /// %unsigned 32 addr 0x0 |
| /// ### |
| /// * When this address falls into the output burst address range, an non-bufferable write will be issued. |
| /// ### |
| /// @ 0x000C4 start (W-) |
| /// %unsigned 4 oid |
| /// ### |
| /// * Write to this register will kickoff the corresponding output thread. |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x000C8 ST (R-) |
| /// %unsigned 16 oThread |
| /// ### |
| /// * Output thread busy status. 0 : idle, 1: busy. |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x000CC Module (P) |
| /// %unsigned 1 en 0x0 |
| /// ### |
| /// * 1: enable pixFmt |
| /// * 0: enable vFmt |
| /// * End of pixFmt_reg |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 208B, bits: 1103b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pixFmtReg |
| #define h_pixFmtReg (){} |
| |
| #define RA_pixFmtReg_idesc 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_odesc 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_roi 0x00A0 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_flt 0x00B8 |
| |
| #define BA_pixFmtReg_flt_ty 0x00B8 |
| #define B16pixFmtReg_flt_ty 0x00B8 |
| #define LSb32pixFmtReg_flt_ty 0 |
| #define LSb16pixFmtReg_flt_ty 0 |
| #define bpixFmtReg_flt_ty 16 |
| #define MSK32pixFmtReg_flt_ty 0x0000FFFF |
| |
| #define BA_pixFmtReg_flt_by 0x00BA |
| #define B16pixFmtReg_flt_by 0x00BA |
| #define LSb32pixFmtReg_flt_by 16 |
| #define LSb16pixFmtReg_flt_by 0 |
| #define bpixFmtReg_flt_by 16 |
| #define MSK32pixFmtReg_flt_by 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_disp 0x00BC |
| |
| #define BA_pixFmtReg_disp_rangeMapYflag 0x00BC |
| #define B16pixFmtReg_disp_rangeMapYflag 0x00BC |
| #define LSb32pixFmtReg_disp_rangeMapYflag 0 |
| #define LSb16pixFmtReg_disp_rangeMapYflag 0 |
| #define bpixFmtReg_disp_rangeMapYflag 1 |
| #define MSK32pixFmtReg_disp_rangeMapYflag 0x00000001 |
| |
| #define BA_pixFmtReg_disp_rangeMapY 0x00BC |
| #define B16pixFmtReg_disp_rangeMapY 0x00BC |
| #define LSb32pixFmtReg_disp_rangeMapY 1 |
| #define LSb16pixFmtReg_disp_rangeMapY 1 |
| #define bpixFmtReg_disp_rangeMapY 3 |
| #define MSK32pixFmtReg_disp_rangeMapY 0x0000000E |
| |
| #define BA_pixFmtReg_disp_rangeMapUVflag 0x00BC |
| #define B16pixFmtReg_disp_rangeMapUVflag 0x00BC |
| #define LSb32pixFmtReg_disp_rangeMapUVflag 4 |
| #define LSb16pixFmtReg_disp_rangeMapUVflag 4 |
| #define bpixFmtReg_disp_rangeMapUVflag 1 |
| #define MSK32pixFmtReg_disp_rangeMapUVflag 0x00000010 |
| |
| #define BA_pixFmtReg_disp_rangeMapUV 0x00BC |
| #define B16pixFmtReg_disp_rangeMapUV 0x00BC |
| #define LSb32pixFmtReg_disp_rangeMapUV 5 |
| #define LSb16pixFmtReg_disp_rangeMapUV 5 |
| #define bpixFmtReg_disp_rangeMapUV 3 |
| #define MSK32pixFmtReg_disp_rangeMapUV 0x000000E0 |
| |
| #define BA_pixFmtReg_disp_rangeRed 0x00BD |
| #define B16pixFmtReg_disp_rangeRed 0x00BC |
| #define LSb32pixFmtReg_disp_rangeRed 8 |
| #define LSb16pixFmtReg_disp_rangeRed 8 |
| #define bpixFmtReg_disp_rangeRed 1 |
| #define MSK32pixFmtReg_disp_rangeRed 0x00000100 |
| |
| #define BA_pixFmtReg_disp_ROI 0x00BD |
| #define B16pixFmtReg_disp_ROI 0x00BC |
| #define LSb32pixFmtReg_disp_ROI 9 |
| #define LSb16pixFmtReg_disp_ROI 9 |
| #define bpixFmtReg_disp_ROI 1 |
| #define MSK32pixFmtReg_disp_ROI 0x00000200 |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_np_cfg 0x00C0 |
| |
| #define BA_pixFmtReg_np_cfg_addr 0x00C0 |
| #define B16pixFmtReg_np_cfg_addr 0x00C0 |
| #define LSb32pixFmtReg_np_cfg_addr 0 |
| #define LSb16pixFmtReg_np_cfg_addr 0 |
| #define bpixFmtReg_np_cfg_addr 32 |
| #define MSK32pixFmtReg_np_cfg_addr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_start 0x00C4 |
| |
| #define BA_pixFmtReg_start_oid 0x00C4 |
| #define B16pixFmtReg_start_oid 0x00C4 |
| #define LSb32pixFmtReg_start_oid 0 |
| #define LSb16pixFmtReg_start_oid 0 |
| #define bpixFmtReg_start_oid 4 |
| #define MSK32pixFmtReg_start_oid 0x0000000F |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_ST 0x00C8 |
| |
| #define BA_pixFmtReg_ST_oThread 0x00C8 |
| #define B16pixFmtReg_ST_oThread 0x00C8 |
| #define LSb32pixFmtReg_ST_oThread 0 |
| #define LSb16pixFmtReg_ST_oThread 0 |
| #define bpixFmtReg_ST_oThread 16 |
| #define MSK32pixFmtReg_ST_oThread 0x0000FFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_pixFmtReg_Module 0x00CC |
| |
| #define BA_pixFmtReg_Module_en 0x00CC |
| #define B16pixFmtReg_Module_en 0x00CC |
| #define LSb32pixFmtReg_Module_en 0 |
| #define LSb16pixFmtReg_Module_en 0 |
| #define bpixFmtReg_Module_en 1 |
| #define MSK32pixFmtReg_Module_en 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pixFmtReg { |
| /////////////////////////////////////////////////////////// |
| SIE_pixFmt_idesc ie_idesc[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_pixFmt_odesc ie_odesc[8]; |
| /////////////////////////////////////////////////////////// |
| SIE_pixFmt_ROI ie_roi; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_flt_ty(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmtReg_flt_ty(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmtReg_flt_ty(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmtReg_flt_ty(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pixFmtReg_flt_by(r32) _BFGET_(r32,31,16) |
| #define SET32pixFmtReg_flt_by(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16pixFmtReg_flt_by(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmtReg_flt_by(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmtReg_flt {\ |
| UNSG32 uflt_ty : 16;\ |
| UNSG32 uflt_by : 16;\ |
| } |
| union { UNSG32 u32pixFmtReg_flt; |
| struct w32pixFmtReg_flt; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_disp_rangeMapYflag(r32) _BFGET_(r32, 0, 0) |
| #define SET32pixFmtReg_disp_rangeMapYflag(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pixFmtReg_disp_rangeMapYflag(r16) _BFGET_(r16, 0, 0) |
| #define SET16pixFmtReg_disp_rangeMapYflag(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pixFmtReg_disp_rangeMapY(r32) _BFGET_(r32, 3, 1) |
| #define SET32pixFmtReg_disp_rangeMapY(r32,v) _BFSET_(r32, 3, 1,v) |
| #define GET16pixFmtReg_disp_rangeMapY(r16) _BFGET_(r16, 3, 1) |
| #define SET16pixFmtReg_disp_rangeMapY(r16,v) _BFSET_(r16, 3, 1,v) |
| |
| #define GET32pixFmtReg_disp_rangeMapUVflag(r32) _BFGET_(r32, 4, 4) |
| #define SET32pixFmtReg_disp_rangeMapUVflag(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16pixFmtReg_disp_rangeMapUVflag(r16) _BFGET_(r16, 4, 4) |
| #define SET16pixFmtReg_disp_rangeMapUVflag(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32pixFmtReg_disp_rangeMapUV(r32) _BFGET_(r32, 7, 5) |
| #define SET32pixFmtReg_disp_rangeMapUV(r32,v) _BFSET_(r32, 7, 5,v) |
| #define GET16pixFmtReg_disp_rangeMapUV(r16) _BFGET_(r16, 7, 5) |
| #define SET16pixFmtReg_disp_rangeMapUV(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32pixFmtReg_disp_rangeRed(r32) _BFGET_(r32, 8, 8) |
| #define SET32pixFmtReg_disp_rangeRed(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16pixFmtReg_disp_rangeRed(r16) _BFGET_(r16, 8, 8) |
| #define SET16pixFmtReg_disp_rangeRed(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32pixFmtReg_disp_ROI(r32) _BFGET_(r32, 9, 9) |
| #define SET32pixFmtReg_disp_ROI(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16pixFmtReg_disp_ROI(r16) _BFGET_(r16, 9, 9) |
| #define SET16pixFmtReg_disp_ROI(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define w32pixFmtReg_disp {\ |
| UNSG32 udisp_rangeMapYflag : 1;\ |
| UNSG32 udisp_rangeMapY : 3;\ |
| UNSG32 udisp_rangeMapUVflag : 1;\ |
| UNSG32 udisp_rangeMapUV : 3;\ |
| UNSG32 udisp_rangeRed : 1;\ |
| UNSG32 udisp_ROI : 1;\ |
| UNSG32 RSVDxBC_b10 : 22;\ |
| } |
| union { UNSG32 u32pixFmtReg_disp; |
| struct w32pixFmtReg_disp; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_np_cfg_addr(r32) _BFGET_(r32,31, 0) |
| #define SET32pixFmtReg_np_cfg_addr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32pixFmtReg_np_cfg {\ |
| UNSG32 unp_cfg_addr : 32;\ |
| } |
| union { UNSG32 u32pixFmtReg_np_cfg; |
| struct w32pixFmtReg_np_cfg; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_start_oid(r32) _BFGET_(r32, 3, 0) |
| #define SET32pixFmtReg_start_oid(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16pixFmtReg_start_oid(r16) _BFGET_(r16, 3, 0) |
| #define SET16pixFmtReg_start_oid(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define w32pixFmtReg_start {\ |
| UNSG32 ustart_oid : 4;\ |
| UNSG32 RSVDxC4_b4 : 28;\ |
| } |
| union { UNSG32 u32pixFmtReg_start; |
| struct w32pixFmtReg_start; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_ST_oThread(r32) _BFGET_(r32,15, 0) |
| #define SET32pixFmtReg_ST_oThread(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pixFmtReg_ST_oThread(r16) _BFGET_(r16,15, 0) |
| #define SET16pixFmtReg_ST_oThread(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32pixFmtReg_ST {\ |
| UNSG32 uST_oThread : 16;\ |
| UNSG32 RSVDxC8_b16 : 16;\ |
| } |
| union { UNSG32 u32pixFmtReg_ST; |
| struct w32pixFmtReg_ST; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pixFmtReg_Module_en(r32) _BFGET_(r32, 0, 0) |
| #define SET32pixFmtReg_Module_en(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pixFmtReg_Module_en(r16) _BFGET_(r16, 0, 0) |
| #define SET16pixFmtReg_Module_en(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32pixFmtReg_Module {\ |
| UNSG32 uModule_en : 1;\ |
| UNSG32 RSVDxCC_b1 : 31;\ |
| } |
| union { UNSG32 u32pixFmtReg_Module; |
| struct w32pixFmtReg_Module; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pixFmtReg; |
| |
| typedef union T32pixFmtReg_flt |
| { UNSG32 u32; |
| struct w32pixFmtReg_flt; |
| } T32pixFmtReg_flt; |
| typedef union T32pixFmtReg_disp |
| { UNSG32 u32; |
| struct w32pixFmtReg_disp; |
| } T32pixFmtReg_disp; |
| typedef union T32pixFmtReg_np_cfg |
| { UNSG32 u32; |
| struct w32pixFmtReg_np_cfg; |
| } T32pixFmtReg_np_cfg; |
| typedef union T32pixFmtReg_start |
| { UNSG32 u32; |
| struct w32pixFmtReg_start; |
| } T32pixFmtReg_start; |
| typedef union T32pixFmtReg_ST |
| { UNSG32 u32; |
| struct w32pixFmtReg_ST; |
| } T32pixFmtReg_ST; |
| typedef union T32pixFmtReg_Module |
| { UNSG32 u32; |
| struct w32pixFmtReg_Module; |
| } T32pixFmtReg_Module; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpixFmtReg_flt |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_flt; |
| }; |
| } TpixFmtReg_flt; |
| typedef union TpixFmtReg_disp |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_disp; |
| }; |
| } TpixFmtReg_disp; |
| typedef union TpixFmtReg_np_cfg |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_np_cfg; |
| }; |
| } TpixFmtReg_np_cfg; |
| typedef union TpixFmtReg_start |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_start; |
| }; |
| } TpixFmtReg_start; |
| typedef union TpixFmtReg_ST |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_ST; |
| }; |
| } TpixFmtReg_ST; |
| typedef union TpixFmtReg_Module |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pixFmtReg_Module; |
| }; |
| } TpixFmtReg_Module; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pixFmtReg_drvrd(SIE_pixFmtReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pixFmtReg_drvwr(SIE_pixFmtReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pixFmtReg_reset(SIE_pixFmtReg *p); |
| SIGN32 pixFmtReg_cmp (SIE_pixFmtReg *p, SIE_pixFmtReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pixFmtReg_check(p,pie,pfx,hLOG) pixFmtReg_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pixFmtReg_print(p, pfx,hLOG) pixFmtReg_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pixFmtReg |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3DMA biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 4 ufSem |
| /// ### |
| /// * 1~15 for local semaphore consumer-check |
| /// ### |
| /// %unsigned 28 eptr |
| /// ### |
| /// * 32b-word address for read source pointer |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 11 dptr |
| /// ### |
| /// * 128b-word address for read destination pointer |
| /// ### |
| /// %unsigned 5 decSem |
| /// ### |
| /// * !=0 to decrease after DMA read done |
| /// ### |
| /// %unsigned 5 incSem |
| /// ### |
| /// * !=0 to increase after DMA read done |
| /// ### |
| /// %unsigned 11 numTsc |
| /// ### |
| /// * Number of 128b transactions, or |
| /// * ==0 to check semaphores only |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3DMA |
| #define h_P3DMA (){} |
| |
| #define BA_P3DMA_ufSem 0x0000 |
| #define B16P3DMA_ufSem 0x0000 |
| #define LSb32P3DMA_ufSem 0 |
| #define LSb16P3DMA_ufSem 0 |
| #define bP3DMA_ufSem 4 |
| #define MSK32P3DMA_ufSem 0x0000000F |
| |
| #define BA_P3DMA_eptr 0x0000 |
| #define B16P3DMA_eptr 0x0000 |
| #define LSb32P3DMA_eptr 4 |
| #define LSb16P3DMA_eptr 4 |
| #define bP3DMA_eptr 28 |
| #define MSK32P3DMA_eptr 0xFFFFFFF0 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3DMA_dptr 0x0004 |
| #define B16P3DMA_dptr 0x0004 |
| #define LSb32P3DMA_dptr 0 |
| #define LSb16P3DMA_dptr 0 |
| #define bP3DMA_dptr 11 |
| #define MSK32P3DMA_dptr 0x000007FF |
| |
| #define BA_P3DMA_decSem 0x0005 |
| #define B16P3DMA_decSem 0x0004 |
| #define LSb32P3DMA_decSem 11 |
| #define LSb16P3DMA_decSem 11 |
| #define bP3DMA_decSem 5 |
| #define MSK32P3DMA_decSem 0x0000F800 |
| |
| #define BA_P3DMA_incSem 0x0006 |
| #define B16P3DMA_incSem 0x0006 |
| #define LSb32P3DMA_incSem 16 |
| #define LSb16P3DMA_incSem 0 |
| #define bP3DMA_incSem 5 |
| #define MSK32P3DMA_incSem 0x001F0000 |
| |
| #define BA_P3DMA_numTsc 0x0006 |
| #define B16P3DMA_numTsc 0x0006 |
| #define LSb32P3DMA_numTsc 21 |
| #define LSb16P3DMA_numTsc 5 |
| #define bP3DMA_numTsc 11 |
| #define MSK32P3DMA_numTsc 0xFFE00000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3DMA { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3DMA_ufSem(r32) _BFGET_(r32, 3, 0) |
| #define SET32P3DMA_ufSem(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16P3DMA_ufSem(r16) _BFGET_(r16, 3, 0) |
| #define SET16P3DMA_ufSem(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32P3DMA_eptr(r32) _BFGET_(r32,31, 4) |
| #define SET32P3DMA_eptr(r32,v) _BFSET_(r32,31, 4,v) |
| |
| UNSG32 u_ufSem : 4; |
| UNSG32 u_eptr : 28; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3DMA_dptr(r32) _BFGET_(r32,10, 0) |
| #define SET32P3DMA_dptr(r32,v) _BFSET_(r32,10, 0,v) |
| #define GET16P3DMA_dptr(r16) _BFGET_(r16,10, 0) |
| #define SET16P3DMA_dptr(r16,v) _BFSET_(r16,10, 0,v) |
| |
| #define GET32P3DMA_decSem(r32) _BFGET_(r32,15,11) |
| #define SET32P3DMA_decSem(r32,v) _BFSET_(r32,15,11,v) |
| #define GET16P3DMA_decSem(r16) _BFGET_(r16,15,11) |
| #define SET16P3DMA_decSem(r16,v) _BFSET_(r16,15,11,v) |
| |
| #define GET32P3DMA_incSem(r32) _BFGET_(r32,20,16) |
| #define SET32P3DMA_incSem(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16P3DMA_incSem(r16) _BFGET_(r16, 4, 0) |
| #define SET16P3DMA_incSem(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32P3DMA_numTsc(r32) _BFGET_(r32,31,21) |
| #define SET32P3DMA_numTsc(r32,v) _BFSET_(r32,31,21,v) |
| #define GET16P3DMA_numTsc(r16) _BFGET_(r16,15, 5) |
| #define SET16P3DMA_numTsc(r16,v) _BFSET_(r16,15, 5,v) |
| |
| UNSG32 u_dptr : 11; |
| UNSG32 u_decSem : 5; |
| UNSG32 u_incSem : 5; |
| UNSG32 u_numTsc : 11; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3DMA; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3DMA_drvrd(SIE_P3DMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3DMA_drvwr(SIE_P3DMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3DMA_reset(SIE_P3DMA *p); |
| SIGN32 P3DMA_cmp (SIE_P3DMA *p, SIE_P3DMA *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3DMA_check(p,pie,pfx,hLOG) P3DMA_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3DMA_print(p, pfx,hLOG) P3DMA_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3DMA |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3A64SEM biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 ID |
| /// ### |
| /// * ID of the semaphore to check |
| /// ### |
| /// %unsigned 1 type |
| /// : pro 0x0 |
| /// : con 0x1 |
| /// ### |
| /// * Type of semaphore check (producer or consumer) |
| /// ### |
| /// %% 25 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 7b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3A64SEM |
| #define h_P3A64SEM (){} |
| |
| #define BA_P3A64SEM_ID 0x0000 |
| #define B16P3A64SEM_ID 0x0000 |
| #define LSb32P3A64SEM_ID 0 |
| #define LSb16P3A64SEM_ID 0 |
| #define bP3A64SEM_ID 6 |
| #define MSK32P3A64SEM_ID 0x0000003F |
| |
| #define BA_P3A64SEM_type 0x0000 |
| #define B16P3A64SEM_type 0x0000 |
| #define LSb32P3A64SEM_type 6 |
| #define LSb16P3A64SEM_type 6 |
| #define bP3A64SEM_type 1 |
| #define MSK32P3A64SEM_type 0x00000040 |
| #define P3A64SEM_type_pro 0x0 |
| #define P3A64SEM_type_con 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3A64SEM { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3A64SEM_ID(r32) _BFGET_(r32, 5, 0) |
| #define SET32P3A64SEM_ID(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16P3A64SEM_ID(r16) _BFGET_(r16, 5, 0) |
| #define SET16P3A64SEM_ID(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32P3A64SEM_type(r32) _BFGET_(r32, 6, 6) |
| #define SET32P3A64SEM_type(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16P3A64SEM_type(r16) _BFGET_(r16, 6, 6) |
| #define SET16P3A64SEM_type(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| UNSG32 u_ID : 6; |
| UNSG32 u_type : 1; |
| UNSG32 RSVDx0_b7 : 25; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3A64SEM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3A64SEM_drvrd(SIE_P3A64SEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3A64SEM_drvwr(SIE_P3A64SEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3A64SEM_reset(SIE_P3A64SEM *p); |
| SIGN32 P3A64SEM_cmp (SIE_P3A64SEM *p, SIE_P3A64SEM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3A64SEM_check(p,pie,pfx,hLOG) P3A64SEM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3A64SEM_print(p, pfx,hLOG) P3A64SEM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3A64SEM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3A64SP biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 funcIDX |
| /// ### |
| /// * 0~254 for alternative index of function pointer table |
| /// ### |
| /// : void 0xFF |
| /// ### |
| /// * A void function call to be ignored by ALU64 extension |
| /// ### |
| /// : altIDX 0xFC |
| /// ### |
| /// * A64CMD(C, SP, TQ): |
| /// * IDX = (C == altIDX) ? SP.funcIDX : C; |
| /// ### |
| /// : param 0xFD |
| /// ### |
| /// * Bypass only (N/A for alternative IDX): C == param |
| /// * Pass flattened P3CMD.param from TQ[63:0] |
| /// ### |
| /// : func 0xFE |
| /// ### |
| /// * Bypass only (N/A for alternative IDX): C == param |
| /// * Pass flattened P3CMD.func from TQ[31:0] & push to FiFo |
| /// ### |
| /// : push 0xFF |
| /// ### |
| /// * Non-function lookup extension push |
| /// ### |
| /// %unsigned 8 opDlt |
| /// ### |
| /// * Op-code table offset |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3A64SP |
| #define h_P3A64SP (){} |
| |
| #define BA_P3A64SP_funcIDX 0x0000 |
| #define B16P3A64SP_funcIDX 0x0000 |
| #define LSb32P3A64SP_funcIDX 0 |
| #define LSb16P3A64SP_funcIDX 0 |
| #define bP3A64SP_funcIDX 8 |
| #define MSK32P3A64SP_funcIDX 0x000000FF |
| #define P3A64SP_funcIDX_void 0xFF |
| #define P3A64SP_funcIDX_altIDX 0xFC |
| #define P3A64SP_funcIDX_param 0xFD |
| #define P3A64SP_funcIDX_func 0xFE |
| #define P3A64SP_funcIDX_push 0xFF |
| |
| #define BA_P3A64SP_opDlt 0x0001 |
| #define B16P3A64SP_opDlt 0x0000 |
| #define LSb32P3A64SP_opDlt 8 |
| #define LSb16P3A64SP_opDlt 8 |
| #define bP3A64SP_opDlt 8 |
| #define MSK32P3A64SP_opDlt 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3A64SP { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3A64SP_funcIDX(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3A64SP_funcIDX(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3A64SP_funcIDX(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3A64SP_funcIDX(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3A64SP_opDlt(r32) _BFGET_(r32,15, 8) |
| #define SET32P3A64SP_opDlt(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16P3A64SP_opDlt(r16) _BFGET_(r16,15, 8) |
| #define SET16P3A64SP_opDlt(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_funcIDX : 8; |
| UNSG32 u_opDlt : 8; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3A64SP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3A64SP_drvrd(SIE_P3A64SP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3A64SP_drvwr(SIE_P3A64SP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3A64SP_reset(SIE_P3A64SP *p); |
| SIGN32 P3A64SP_cmp (SIE_P3A64SP *p, SIE_P3A64SP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3A64SP_check(p,pie,pfx,hLOG) P3A64SP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3A64SP_print(p, pfx,hLOG) P3A64SP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3A64SP |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3A64TQ biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 rptrDlt |
| /// ### |
| /// * 32b-word offset to read pointer base address |
| /// ### |
| /// %unsigned 8 wptrDlt |
| /// ### |
| /// * 32b-word offset to read pointer base address |
| /// ### |
| /// %unsigned 8 rptrBase |
| /// ### |
| /// * 1024b-tile base address for read pointer |
| /// ### |
| /// %unsigned 8 wptrBase |
| /// ### |
| /// * 1024b-tile base address for write pointer |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 4 rfBase |
| /// ### |
| /// * Alternative RF base pointer |
| /// ### |
| /// %unsigned 28 eptrBase |
| /// ### |
| /// * 32b-word base address for external pointer |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3A64TQ |
| #define h_P3A64TQ (){} |
| |
| #define BA_P3A64TQ_rptrDlt 0x0000 |
| #define B16P3A64TQ_rptrDlt 0x0000 |
| #define LSb32P3A64TQ_rptrDlt 0 |
| #define LSb16P3A64TQ_rptrDlt 0 |
| #define bP3A64TQ_rptrDlt 8 |
| #define MSK32P3A64TQ_rptrDlt 0x000000FF |
| |
| #define BA_P3A64TQ_wptrDlt 0x0001 |
| #define B16P3A64TQ_wptrDlt 0x0000 |
| #define LSb32P3A64TQ_wptrDlt 8 |
| #define LSb16P3A64TQ_wptrDlt 8 |
| #define bP3A64TQ_wptrDlt 8 |
| #define MSK32P3A64TQ_wptrDlt 0x0000FF00 |
| |
| #define BA_P3A64TQ_rptrBase 0x0002 |
| #define B16P3A64TQ_rptrBase 0x0002 |
| #define LSb32P3A64TQ_rptrBase 16 |
| #define LSb16P3A64TQ_rptrBase 0 |
| #define bP3A64TQ_rptrBase 8 |
| #define MSK32P3A64TQ_rptrBase 0x00FF0000 |
| |
| #define BA_P3A64TQ_wptrBase 0x0003 |
| #define B16P3A64TQ_wptrBase 0x0002 |
| #define LSb32P3A64TQ_wptrBase 24 |
| #define LSb16P3A64TQ_wptrBase 8 |
| #define bP3A64TQ_wptrBase 8 |
| #define MSK32P3A64TQ_wptrBase 0xFF000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3A64TQ_rfBase 0x0004 |
| #define B16P3A64TQ_rfBase 0x0004 |
| #define LSb32P3A64TQ_rfBase 0 |
| #define LSb16P3A64TQ_rfBase 0 |
| #define bP3A64TQ_rfBase 4 |
| #define MSK32P3A64TQ_rfBase 0x0000000F |
| |
| #define BA_P3A64TQ_eptrBase 0x0004 |
| #define B16P3A64TQ_eptrBase 0x0004 |
| #define LSb32P3A64TQ_eptrBase 4 |
| #define LSb16P3A64TQ_eptrBase 4 |
| #define bP3A64TQ_eptrBase 28 |
| #define MSK32P3A64TQ_eptrBase 0xFFFFFFF0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3A64TQ { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3A64TQ_rptrDlt(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3A64TQ_rptrDlt(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3A64TQ_rptrDlt(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3A64TQ_rptrDlt(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3A64TQ_wptrDlt(r32) _BFGET_(r32,15, 8) |
| #define SET32P3A64TQ_wptrDlt(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16P3A64TQ_wptrDlt(r16) _BFGET_(r16,15, 8) |
| #define SET16P3A64TQ_wptrDlt(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32P3A64TQ_rptrBase(r32) _BFGET_(r32,23,16) |
| #define SET32P3A64TQ_rptrBase(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16P3A64TQ_rptrBase(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3A64TQ_rptrBase(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3A64TQ_wptrBase(r32) _BFGET_(r32,31,24) |
| #define SET32P3A64TQ_wptrBase(r32,v) _BFSET_(r32,31,24,v) |
| #define GET16P3A64TQ_wptrBase(r16) _BFGET_(r16,15, 8) |
| #define SET16P3A64TQ_wptrBase(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_rptrDlt : 8; |
| UNSG32 u_wptrDlt : 8; |
| UNSG32 u_rptrBase : 8; |
| UNSG32 u_wptrBase : 8; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3A64TQ_rfBase(r32) _BFGET_(r32, 3, 0) |
| #define SET32P3A64TQ_rfBase(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16P3A64TQ_rfBase(r16) _BFGET_(r16, 3, 0) |
| #define SET16P3A64TQ_rfBase(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32P3A64TQ_eptrBase(r32) _BFGET_(r32,31, 4) |
| #define SET32P3A64TQ_eptrBase(r32,v) _BFSET_(r32,31, 4,v) |
| |
| UNSG32 u_rfBase : 4; |
| UNSG32 u_eptrBase : 28; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3A64TQ; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3A64TQ_drvrd(SIE_P3A64TQ *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3A64TQ_drvwr(SIE_P3A64TQ *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3A64TQ_reset(SIE_P3A64TQ *p); |
| SIGN32 P3A64TQ_cmp (SIE_P3A64TQ *p, SIE_P3A64TQ *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3A64TQ_check(p,pie,pfx,hLOG) P3A64TQ_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3A64TQ_print(p, pfx,hLOG) P3A64TQ_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3A64TQ |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3A64PushR16 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 ID |
| /// ### |
| /// * extension ID |
| /// ### |
| /// : semChk 0x0 |
| /// ### |
| /// * Check semaphores with q6==6'b1 |
| /// ### |
| /// %unsigned 8 param |
| /// ### |
| /// * Extension parameter |
| /// * if ID==semChk, param==semaphore ID (in P3A64PushR16 data struction defined before, bit[6] indicates whether it's producer or consumer check) |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3A64PushR16 |
| #define h_P3A64PushR16 (){} |
| |
| #define BA_P3A64PushR16_ID 0x0000 |
| #define B16P3A64PushR16_ID 0x0000 |
| #define LSb32P3A64PushR16_ID 0 |
| #define LSb16P3A64PushR16_ID 0 |
| #define bP3A64PushR16_ID 8 |
| #define MSK32P3A64PushR16_ID 0x000000FF |
| #define P3A64PushR16_ID_semChk 0x0 |
| |
| #define BA_P3A64PushR16_param 0x0001 |
| #define B16P3A64PushR16_param 0x0000 |
| #define LSb32P3A64PushR16_param 8 |
| #define LSb16P3A64PushR16_param 8 |
| #define bP3A64PushR16_param 8 |
| #define MSK32P3A64PushR16_param 0x0000FF00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3A64PushR16 { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3A64PushR16_ID(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3A64PushR16_ID(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3A64PushR16_ID(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3A64PushR16_ID(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3A64PushR16_param(r32) _BFGET_(r32,15, 8) |
| #define SET32P3A64PushR16_param(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16P3A64PushR16_param(r16) _BFGET_(r16,15, 8) |
| #define SET16P3A64PushR16_param(r16,v) _BFSET_(r16,15, 8,v) |
| |
| UNSG32 u_ID : 8; |
| UNSG32 u_param : 8; |
| UNSG32 RSVDx0_b16 : 16; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3A64PushR16; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3A64PushR16_drvrd(SIE_P3A64PushR16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3A64PushR16_drvwr(SIE_P3A64PushR16 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3A64PushR16_reset(SIE_P3A64PushR16 *p); |
| SIGN32 P3A64PushR16_cmp (SIE_P3A64PushR16 *p, SIE_P3A64PushR16 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3A64PushR16_check(p,pie,pfx,hLOG) P3A64PushR16_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3A64PushR16_print(p, pfx,hLOG) P3A64PushR16_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3A64PushR16 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3PARAM biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 rptrBase |
| /// ### |
| /// * 32b-word base address for read pointer: |
| /// * = TQ.rptrBase * 32 + TQ.rptrDlt |
| /// * NOTE: rptrBase should be 64b aligned; I.e. rptrBase[0]=0 |
| /// ### |
| /// %unsigned 16 wptrBase |
| /// ### |
| /// * 32b-word base address for write pointer: |
| /// * = TQ.wptrBase * 32 + TQ.wptrDlt |
| /// ### |
| /// @ 0x00004 (P) |
| /// %unsigned 4 rfBase |
| /// ### |
| /// * RF base pointer: |
| /// * = FNP.altRFP ? TQ.rfBase : 0 |
| /// ### |
| /// %unsigned 28 eptrBase |
| /// ### |
| /// * 32b-word base address for external pointer |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3PARAM |
| #define h_P3PARAM (){} |
| |
| #define BA_P3PARAM_rptrBase 0x0000 |
| #define B16P3PARAM_rptrBase 0x0000 |
| #define LSb32P3PARAM_rptrBase 0 |
| #define LSb16P3PARAM_rptrBase 0 |
| #define bP3PARAM_rptrBase 16 |
| #define MSK32P3PARAM_rptrBase 0x0000FFFF |
| |
| #define BA_P3PARAM_wptrBase 0x0002 |
| #define B16P3PARAM_wptrBase 0x0002 |
| #define LSb32P3PARAM_wptrBase 16 |
| #define LSb16P3PARAM_wptrBase 0 |
| #define bP3PARAM_wptrBase 16 |
| #define MSK32P3PARAM_wptrBase 0xFFFF0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3PARAM_rfBase 0x0004 |
| #define B16P3PARAM_rfBase 0x0004 |
| #define LSb32P3PARAM_rfBase 0 |
| #define LSb16P3PARAM_rfBase 0 |
| #define bP3PARAM_rfBase 4 |
| #define MSK32P3PARAM_rfBase 0x0000000F |
| |
| #define BA_P3PARAM_eptrBase 0x0004 |
| #define B16P3PARAM_eptrBase 0x0004 |
| #define LSb32P3PARAM_eptrBase 4 |
| #define LSb16P3PARAM_eptrBase 4 |
| #define bP3PARAM_eptrBase 28 |
| #define MSK32P3PARAM_eptrBase 0xFFFFFFF0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3PARAM { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3PARAM_rptrBase(r32) _BFGET_(r32,15, 0) |
| #define SET32P3PARAM_rptrBase(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16P3PARAM_rptrBase(r16) _BFGET_(r16,15, 0) |
| #define SET16P3PARAM_rptrBase(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32P3PARAM_wptrBase(r32) _BFGET_(r32,31,16) |
| #define SET32P3PARAM_wptrBase(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16P3PARAM_wptrBase(r16) _BFGET_(r16,15, 0) |
| #define SET16P3PARAM_wptrBase(r16,v) _BFSET_(r16,15, 0,v) |
| |
| UNSG32 u_rptrBase : 16; |
| UNSG32 u_wptrBase : 16; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3PARAM_rfBase(r32) _BFGET_(r32, 3, 0) |
| #define SET32P3PARAM_rfBase(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16P3PARAM_rfBase(r16) _BFGET_(r16, 3, 0) |
| #define SET16P3PARAM_rfBase(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32P3PARAM_eptrBase(r32) _BFGET_(r32,31, 4) |
| #define SET32P3PARAM_eptrBase(r32,v) _BFSET_(r32,31, 4,v) |
| |
| UNSG32 u_rfBase : 4; |
| UNSG32 u_eptrBase : 28; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3PARAM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3PARAM_drvrd(SIE_P3PARAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3PARAM_drvwr(SIE_P3PARAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3PARAM_reset(SIE_P3PARAM *p); |
| SIGN32 P3PARAM_cmp (SIE_P3PARAM *p, SIE_P3PARAM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3PARAM_check(p,pie,pfx,hLOG) P3PARAM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3PARAM_print(p, pfx,hLOG) P3PARAM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3PARAM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FNP biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 9 opBase |
| /// ### |
| /// * Base op-code |
| /// ### |
| /// %unsigned 1 opDlt |
| /// ### |
| /// * if(opDlt) opBase += SP.opDlt |
| /// ### |
| /// %unsigned 6 numIns |
| /// ### |
| /// * Number of instructions to execute |
| /// ### |
| /// %unsigned 12 funcEntry |
| /// ### |
| /// * Function entry in IRAM |
| /// ### |
| /// %unsigned 1 unpack |
| /// ### |
| /// * To unpack source 8b unsigned to 16b signed |
| /// * (A) Unpack = 1 |
| /// * (1) Load 32 bits from DMEM using 32-bit address |
| /// * (2) Each 8-bit unit from 32-bit loaded data is expanded to 20 bits. |
| /// * (B) Unpack = 0 |
| /// * (1) Load 64 bits from DMEM using 64-bit address |
| /// ### |
| /// %unsigned 1 altRFP |
| /// ### |
| /// * If to use alternative RFP from TQ.rfBase |
| /// ### |
| /// %unsigned 2 ID |
| /// ### |
| /// * Datapath selection, 0 as default |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FNP |
| #define h_P3FNP (){} |
| |
| #define BA_P3FNP_opBase 0x0000 |
| #define B16P3FNP_opBase 0x0000 |
| #define LSb32P3FNP_opBase 0 |
| #define LSb16P3FNP_opBase 0 |
| #define bP3FNP_opBase 9 |
| #define MSK32P3FNP_opBase 0x000001FF |
| |
| #define BA_P3FNP_opDlt 0x0001 |
| #define B16P3FNP_opDlt 0x0000 |
| #define LSb32P3FNP_opDlt 9 |
| #define LSb16P3FNP_opDlt 9 |
| #define bP3FNP_opDlt 1 |
| #define MSK32P3FNP_opDlt 0x00000200 |
| |
| #define BA_P3FNP_numIns 0x0001 |
| #define B16P3FNP_numIns 0x0000 |
| #define LSb32P3FNP_numIns 10 |
| #define LSb16P3FNP_numIns 10 |
| #define bP3FNP_numIns 6 |
| #define MSK32P3FNP_numIns 0x0000FC00 |
| |
| #define BA_P3FNP_funcEntry 0x0002 |
| #define B16P3FNP_funcEntry 0x0002 |
| #define LSb32P3FNP_funcEntry 16 |
| #define LSb16P3FNP_funcEntry 0 |
| #define bP3FNP_funcEntry 12 |
| #define MSK32P3FNP_funcEntry 0x0FFF0000 |
| |
| #define BA_P3FNP_unpack 0x0003 |
| #define B16P3FNP_unpack 0x0002 |
| #define LSb32P3FNP_unpack 28 |
| #define LSb16P3FNP_unpack 12 |
| #define bP3FNP_unpack 1 |
| #define MSK32P3FNP_unpack 0x10000000 |
| |
| #define BA_P3FNP_altRFP 0x0003 |
| #define B16P3FNP_altRFP 0x0002 |
| #define LSb32P3FNP_altRFP 29 |
| #define LSb16P3FNP_altRFP 13 |
| #define bP3FNP_altRFP 1 |
| #define MSK32P3FNP_altRFP 0x20000000 |
| |
| #define BA_P3FNP_ID 0x0003 |
| #define B16P3FNP_ID 0x0002 |
| #define LSb32P3FNP_ID 30 |
| #define LSb16P3FNP_ID 14 |
| #define bP3FNP_ID 2 |
| #define MSK32P3FNP_ID 0xC0000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FNP { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FNP_opBase(r32) _BFGET_(r32, 8, 0) |
| #define SET32P3FNP_opBase(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16P3FNP_opBase(r16) _BFGET_(r16, 8, 0) |
| #define SET16P3FNP_opBase(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32P3FNP_opDlt(r32) _BFGET_(r32, 9, 9) |
| #define SET32P3FNP_opDlt(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16P3FNP_opDlt(r16) _BFGET_(r16, 9, 9) |
| #define SET16P3FNP_opDlt(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32P3FNP_numIns(r32) _BFGET_(r32,15,10) |
| #define SET32P3FNP_numIns(r32,v) _BFSET_(r32,15,10,v) |
| #define GET16P3FNP_numIns(r16) _BFGET_(r16,15,10) |
| #define SET16P3FNP_numIns(r16,v) _BFSET_(r16,15,10,v) |
| |
| #define GET32P3FNP_funcEntry(r32) _BFGET_(r32,27,16) |
| #define SET32P3FNP_funcEntry(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16P3FNP_funcEntry(r16) _BFGET_(r16,11, 0) |
| #define SET16P3FNP_funcEntry(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32P3FNP_unpack(r32) _BFGET_(r32,28,28) |
| #define SET32P3FNP_unpack(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16P3FNP_unpack(r16) _BFGET_(r16,12,12) |
| #define SET16P3FNP_unpack(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32P3FNP_altRFP(r32) _BFGET_(r32,29,29) |
| #define SET32P3FNP_altRFP(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16P3FNP_altRFP(r16) _BFGET_(r16,13,13) |
| #define SET16P3FNP_altRFP(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32P3FNP_ID(r32) _BFGET_(r32,31,30) |
| #define SET32P3FNP_ID(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16P3FNP_ID(r16) _BFGET_(r16,15,14) |
| #define SET16P3FNP_ID(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_opBase : 9; |
| UNSG32 u_opDlt : 1; |
| UNSG32 u_numIns : 6; |
| UNSG32 u_funcEntry : 12; |
| UNSG32 u_unpack : 1; |
| UNSG32 u_altRFP : 1; |
| UNSG32 u_ID : 2; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FNP; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FNP_drvrd(SIE_P3FNP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FNP_drvwr(SIE_P3FNP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FNP_reset(SIE_P3FNP *p); |
| SIGN32 P3FNP_cmp (SIE_P3FNP *p, SIE_P3FNP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FNP_check(p,pie,pfx,hLOG) P3FNP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FNP_print(p, pfx,hLOG) P3FNP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FNP |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3CMD biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 func |
| /// $P3FNP func REG |
| /// ### |
| /// * Function pointer |
| /// ### |
| /// @ 0x00004 (P) |
| /// # 0x00004 param |
| /// $P3PARAM param REG |
| /// ### |
| /// * Function parameters |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 12B, bits: 96b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3CMD |
| #define h_P3CMD (){} |
| |
| #define RA_P3CMD_func 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3CMD_param 0x0004 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3CMD { |
| /////////////////////////////////////////////////////////// |
| SIE_P3FNP ie_func; |
| /////////////////////////////////////////////////////////// |
| SIE_P3PARAM ie_param; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3CMD; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3CMD_drvrd(SIE_P3CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3CMD_drvwr(SIE_P3CMD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3CMD_reset(SIE_P3CMD *p); |
| SIGN32 P3CMD_cmp (SIE_P3CMD *p, SIE_P3CMD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3CMD_check(p,pie,pfx,hLOG) P3CMD_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3CMD_print(p, pfx,hLOG) P3CMD_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3CMD |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3INSDMA biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 6 dptrDlt |
| /// ### |
| /// * Source offset to base write pointer, in 128b-entries |
| /// ### |
| /// %unsigned 7 eptrDlt |
| /// ### |
| /// * Destination offset to base external pointer, in 32b |
| /// ### |
| /// %unsigned 6 numTsc |
| /// ### |
| /// * Number of 128b transactions, or |
| /// * ==0 to append semaphores update 'fake transaction' only (no DMA transfer) |
| /// ### |
| /// %unsigned 1 ID_DMAOP |
| /// : INSDMA 0x0 |
| /// ### |
| /// * 0: for P3INSDMA |
| /// * 1: for P3INSOP |
| /// ### |
| /// %unsigned 5 decSem |
| /// ### |
| /// * !=0 to be appended to decrease at transfer end |
| /// ### |
| /// %unsigned 5 incSem |
| /// ### |
| /// * !=0 to be appended to increase at transfer end |
| /// ### |
| /// %unsigned 1 syncOnly |
| /// ### |
| /// * If to update semaphore only |
| /// ### |
| /// %unsigned 1 ID |
| /// : DMA 0x1 |
| /// ### |
| /// * == 1'b1 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3INSDMA |
| #define h_P3INSDMA (){} |
| |
| #define BA_P3INSDMA_dptrDlt 0x0000 |
| #define B16P3INSDMA_dptrDlt 0x0000 |
| #define LSb32P3INSDMA_dptrDlt 0 |
| #define LSb16P3INSDMA_dptrDlt 0 |
| #define bP3INSDMA_dptrDlt 6 |
| #define MSK32P3INSDMA_dptrDlt 0x0000003F |
| |
| #define BA_P3INSDMA_eptrDlt 0x0000 |
| #define B16P3INSDMA_eptrDlt 0x0000 |
| #define LSb32P3INSDMA_eptrDlt 6 |
| #define LSb16P3INSDMA_eptrDlt 6 |
| #define bP3INSDMA_eptrDlt 7 |
| #define MSK32P3INSDMA_eptrDlt 0x00001FC0 |
| |
| #define BA_P3INSDMA_numTsc 0x0001 |
| #define B16P3INSDMA_numTsc 0x0000 |
| #define LSb32P3INSDMA_numTsc 13 |
| #define LSb16P3INSDMA_numTsc 13 |
| #define bP3INSDMA_numTsc 6 |
| #define MSK32P3INSDMA_numTsc 0x0007E000 |
| |
| #define BA_P3INSDMA_ID_DMAOP 0x0002 |
| #define B16P3INSDMA_ID_DMAOP 0x0002 |
| #define LSb32P3INSDMA_ID_DMAOP 19 |
| #define LSb16P3INSDMA_ID_DMAOP 3 |
| #define bP3INSDMA_ID_DMAOP 1 |
| #define MSK32P3INSDMA_ID_DMAOP 0x00080000 |
| #define P3INSDMA_ID_DMAOP_INSDMA 0x0 |
| |
| #define BA_P3INSDMA_decSem 0x0002 |
| #define B16P3INSDMA_decSem 0x0002 |
| #define LSb32P3INSDMA_decSem 20 |
| #define LSb16P3INSDMA_decSem 4 |
| #define bP3INSDMA_decSem 5 |
| #define MSK32P3INSDMA_decSem 0x01F00000 |
| |
| #define BA_P3INSDMA_incSem 0x0003 |
| #define B16P3INSDMA_incSem 0x0002 |
| #define LSb32P3INSDMA_incSem 25 |
| #define LSb16P3INSDMA_incSem 9 |
| #define bP3INSDMA_incSem 5 |
| #define MSK32P3INSDMA_incSem 0x3E000000 |
| |
| #define BA_P3INSDMA_syncOnly 0x0003 |
| #define B16P3INSDMA_syncOnly 0x0002 |
| #define LSb32P3INSDMA_syncOnly 30 |
| #define LSb16P3INSDMA_syncOnly 14 |
| #define bP3INSDMA_syncOnly 1 |
| #define MSK32P3INSDMA_syncOnly 0x40000000 |
| |
| #define BA_P3INSDMA_ID 0x0003 |
| #define B16P3INSDMA_ID 0x0002 |
| #define LSb32P3INSDMA_ID 31 |
| #define LSb16P3INSDMA_ID 15 |
| #define bP3INSDMA_ID 1 |
| #define MSK32P3INSDMA_ID 0x80000000 |
| #define P3INSDMA_ID_DMA 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3INSDMA { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3INSDMA_dptrDlt(r32) _BFGET_(r32, 5, 0) |
| #define SET32P3INSDMA_dptrDlt(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16P3INSDMA_dptrDlt(r16) _BFGET_(r16, 5, 0) |
| #define SET16P3INSDMA_dptrDlt(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32P3INSDMA_eptrDlt(r32) _BFGET_(r32,12, 6) |
| #define SET32P3INSDMA_eptrDlt(r32,v) _BFSET_(r32,12, 6,v) |
| #define GET16P3INSDMA_eptrDlt(r16) _BFGET_(r16,12, 6) |
| #define SET16P3INSDMA_eptrDlt(r16,v) _BFSET_(r16,12, 6,v) |
| |
| #define GET32P3INSDMA_numTsc(r32) _BFGET_(r32,18,13) |
| #define SET32P3INSDMA_numTsc(r32,v) _BFSET_(r32,18,13,v) |
| |
| #define GET32P3INSDMA_ID_DMAOP(r32) _BFGET_(r32,19,19) |
| #define SET32P3INSDMA_ID_DMAOP(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16P3INSDMA_ID_DMAOP(r16) _BFGET_(r16, 3, 3) |
| #define SET16P3INSDMA_ID_DMAOP(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32P3INSDMA_decSem(r32) _BFGET_(r32,24,20) |
| #define SET32P3INSDMA_decSem(r32,v) _BFSET_(r32,24,20,v) |
| #define GET16P3INSDMA_decSem(r16) _BFGET_(r16, 8, 4) |
| #define SET16P3INSDMA_decSem(r16,v) _BFSET_(r16, 8, 4,v) |
| |
| #define GET32P3INSDMA_incSem(r32) _BFGET_(r32,29,25) |
| #define SET32P3INSDMA_incSem(r32,v) _BFSET_(r32,29,25,v) |
| #define GET16P3INSDMA_incSem(r16) _BFGET_(r16,13, 9) |
| #define SET16P3INSDMA_incSem(r16,v) _BFSET_(r16,13, 9,v) |
| |
| #define GET32P3INSDMA_syncOnly(r32) _BFGET_(r32,30,30) |
| #define SET32P3INSDMA_syncOnly(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16P3INSDMA_syncOnly(r16) _BFGET_(r16,14,14) |
| #define SET16P3INSDMA_syncOnly(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32P3INSDMA_ID(r32) _BFGET_(r32,31,31) |
| #define SET32P3INSDMA_ID(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16P3INSDMA_ID(r16) _BFGET_(r16,15,15) |
| #define SET16P3INSDMA_ID(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_dptrDlt : 6; |
| UNSG32 u_eptrDlt : 7; |
| UNSG32 u_numTsc : 6; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 u_decSem : 5; |
| UNSG32 u_incSem : 5; |
| UNSG32 u_syncOnly : 1; |
| UNSG32 u_ID : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3INSDMA; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3INSDMA_drvrd(SIE_P3INSDMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3INSDMA_drvwr(SIE_P3INSDMA *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3INSDMA_reset(SIE_P3INSDMA *p); |
| SIGN32 P3INSDMA_cmp (SIE_P3INSDMA *p, SIE_P3INSDMA *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3INSDMA_check(p,pie,pfx,hLOG) P3INSDMA_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3INSDMA_print(p, pfx,hLOG) P3INSDMA_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3INSDMA |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3INSEXE biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 8 rptrDlt |
| /// ### |
| /// * Relative read pointer, in 64b or 32b (if unpack == 1) |
| /// ### |
| /// %unsigned 2 rd |
| /// : 4x1 0x1 |
| /// : 8x1 0x2 |
| /// : 4x2 0x2 |
| /// : 1x4 0x3 |
| /// : NONE 0x0 |
| /// ### |
| /// * The usage of rd depends on the P3FNP.unpack (the definition of unpack please refer to comments of bit field P3FNP.unpack) |
| /// * (A) P3FNP.unpack = 0 |
| /// * (1) 4x1: read four 16-bit entries from a row. Each 16-bit unit is signed expanded to 20 bits |
| /// * (2) 1x4: read four 16-bit entries from a column. Each 16-bit unit is signed expanded to 20 bits |
| /// * (3) 8x1: read eight 8-bit entries from a row. Each 8-bit unit is unsigned expanded to 10 bits |
| /// * (4) 4x2: read eight 8-bit entries from a region consisting two rows and four columns. Each 8-bit unit is unsigned expanded to 10 bits |
| /// * (B) P3FNP.unpack = 1 |
| /// * (1) 4x1: read four 8-bit entries from a row. Each 8-bit unit is unsigned expanded to 20 bits |
| /// * (2) 1x4: read four 8-bit entries from a column. Each 8-bit unit is unsigned expanded to 20 bits |
| /// * (C)The feasible combination of unpack and read mode |
| /// * unpack | read mode |
| /// * (1) 0 4x1 |
| /// * (2) 0 1x4 |
| /// * (3) 0 8x1 |
| /// * (4) 0 4x2 |
| /// * (5) 1 4x1 |
| /// * (6) 1 1x4 |
| /// ### |
| /// %unsigned 7 wptrDlt |
| /// ### |
| /// * Relative write pointer, in 64b |
| /// ### |
| /// %unsigned 2 wr |
| /// : 2x4 0x0 |
| /// : 4x1 0x1 |
| /// : 8x1 0x1 |
| /// : 4x2 0x1 |
| /// : 4x1L 0x2 |
| /// : 4x1H 0x3 |
| /// : NONE 0x0 |
| /// ### |
| /// * Write mode |
| /// * Please refer to the end of this section for the explanation of write mode |
| /// ### |
| /// %unsigned 4 rfp |
| /// ### |
| /// * Relative offset for rotating access of RF[0~15] |
| /// ### |
| /// %unsigned 8 op |
| /// ### |
| /// * Relative op-code for pipeline |
| /// ### |
| /// : BUBL 0xFF |
| /// ### |
| /// * Force to generate bubbles |
| /// ### |
| /// %unsigned 1 ID |
| /// : EXE 0x0 |
| /// ### |
| /// * == 1'b0 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3INSEXE |
| #define h_P3INSEXE (){} |
| |
| #define BA_P3INSEXE_rptrDlt 0x0000 |
| #define B16P3INSEXE_rptrDlt 0x0000 |
| #define LSb32P3INSEXE_rptrDlt 0 |
| #define LSb16P3INSEXE_rptrDlt 0 |
| #define bP3INSEXE_rptrDlt 8 |
| #define MSK32P3INSEXE_rptrDlt 0x000000FF |
| |
| #define BA_P3INSEXE_rd 0x0001 |
| #define B16P3INSEXE_rd 0x0000 |
| #define LSb32P3INSEXE_rd 8 |
| #define LSb16P3INSEXE_rd 8 |
| #define bP3INSEXE_rd 2 |
| #define MSK32P3INSEXE_rd 0x00000300 |
| #define P3INSEXE_rd_4x1 0x1 |
| #define P3INSEXE_rd_8x1 0x2 |
| #define P3INSEXE_rd_4x2 0x2 |
| #define P3INSEXE_rd_1x4 0x3 |
| #define P3INSEXE_rd_NONE 0x0 |
| |
| #define BA_P3INSEXE_wptrDlt 0x0001 |
| #define B16P3INSEXE_wptrDlt 0x0000 |
| #define LSb32P3INSEXE_wptrDlt 10 |
| #define LSb16P3INSEXE_wptrDlt 10 |
| #define bP3INSEXE_wptrDlt 7 |
| #define MSK32P3INSEXE_wptrDlt 0x0001FC00 |
| |
| #define BA_P3INSEXE_wr 0x0002 |
| #define B16P3INSEXE_wr 0x0002 |
| #define LSb32P3INSEXE_wr 17 |
| #define LSb16P3INSEXE_wr 1 |
| #define bP3INSEXE_wr 2 |
| #define MSK32P3INSEXE_wr 0x00060000 |
| #define P3INSEXE_wr_2x4 0x0 |
| #define P3INSEXE_wr_4x1 0x1 |
| #define P3INSEXE_wr_8x1 0x1 |
| #define P3INSEXE_wr_4x2 0x1 |
| #define P3INSEXE_wr_4x1L 0x2 |
| #define P3INSEXE_wr_4x1H 0x3 |
| #define P3INSEXE_wr_NONE 0x0 |
| |
| #define BA_P3INSEXE_rfp 0x0002 |
| #define B16P3INSEXE_rfp 0x0002 |
| #define LSb32P3INSEXE_rfp 19 |
| #define LSb16P3INSEXE_rfp 3 |
| #define bP3INSEXE_rfp 4 |
| #define MSK32P3INSEXE_rfp 0x00780000 |
| |
| #define BA_P3INSEXE_op 0x0002 |
| #define B16P3INSEXE_op 0x0002 |
| #define LSb32P3INSEXE_op 23 |
| #define LSb16P3INSEXE_op 7 |
| #define bP3INSEXE_op 8 |
| #define MSK32P3INSEXE_op 0x7F800000 |
| #define P3INSEXE_op_BUBL 0xFF |
| |
| #define BA_P3INSEXE_ID 0x0003 |
| #define B16P3INSEXE_ID 0x0002 |
| #define LSb32P3INSEXE_ID 31 |
| #define LSb16P3INSEXE_ID 15 |
| #define bP3INSEXE_ID 1 |
| #define MSK32P3INSEXE_ID 0x80000000 |
| #define P3INSEXE_ID_EXE 0x0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3INSEXE { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3INSEXE_rptrDlt(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3INSEXE_rptrDlt(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3INSEXE_rptrDlt(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3INSEXE_rptrDlt(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3INSEXE_rd(r32) _BFGET_(r32, 9, 8) |
| #define SET32P3INSEXE_rd(r32,v) _BFSET_(r32, 9, 8,v) |
| #define GET16P3INSEXE_rd(r16) _BFGET_(r16, 9, 8) |
| #define SET16P3INSEXE_rd(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32P3INSEXE_wptrDlt(r32) _BFGET_(r32,16,10) |
| #define SET32P3INSEXE_wptrDlt(r32,v) _BFSET_(r32,16,10,v) |
| |
| #define GET32P3INSEXE_wr(r32) _BFGET_(r32,18,17) |
| #define SET32P3INSEXE_wr(r32,v) _BFSET_(r32,18,17,v) |
| #define GET16P3INSEXE_wr(r16) _BFGET_(r16, 2, 1) |
| #define SET16P3INSEXE_wr(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32P3INSEXE_rfp(r32) _BFGET_(r32,22,19) |
| #define SET32P3INSEXE_rfp(r32,v) _BFSET_(r32,22,19,v) |
| #define GET16P3INSEXE_rfp(r16) _BFGET_(r16, 6, 3) |
| #define SET16P3INSEXE_rfp(r16,v) _BFSET_(r16, 6, 3,v) |
| |
| #define GET32P3INSEXE_op(r32) _BFGET_(r32,30,23) |
| #define SET32P3INSEXE_op(r32,v) _BFSET_(r32,30,23,v) |
| #define GET16P3INSEXE_op(r16) _BFGET_(r16,14, 7) |
| #define SET16P3INSEXE_op(r16,v) _BFSET_(r16,14, 7,v) |
| |
| #define GET32P3INSEXE_ID(r32) _BFGET_(r32,31,31) |
| #define SET32P3INSEXE_ID(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16P3INSEXE_ID(r16) _BFGET_(r16,15,15) |
| #define SET16P3INSEXE_ID(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_rptrDlt : 8; |
| UNSG32 u_rd : 2; |
| UNSG32 u_wptrDlt : 7; |
| UNSG32 u_wr : 2; |
| UNSG32 u_rfp : 4; |
| UNSG32 u_op : 8; |
| UNSG32 u_ID : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3INSEXE; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3INSEXE_drvrd(SIE_P3INSEXE *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3INSEXE_drvwr(SIE_P3INSEXE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3INSEXE_reset(SIE_P3INSEXE *p); |
| SIGN32 P3INSEXE_cmp (SIE_P3INSEXE *p, SIE_P3INSEXE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3INSEXE_check(p,pie,pfx,hLOG) P3INSEXE_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3INSEXE_print(p, pfx,hLOG) P3INSEXE_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3INSEXE |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3INSOPWRF biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 rpu |
| /// ### |
| /// * RF read address for u pipe (absolute address) |
| /// ### |
| /// %unsigned 5 rpv |
| /// ### |
| /// * RF read address for v pipe (absolute address) |
| /// ### |
| /// %unsigned 5 wp |
| /// ### |
| /// * RF write address (absolute address) |
| /// * The actual write operation is controlled by wCtl as ENABLE |
| /// ### |
| /// %unsigned 4 RESD0 |
| /// ### |
| /// * reserved |
| /// ### |
| /// %unsigned 1 ID_DMAOP |
| /// : INSOP 0x1 |
| /// ### |
| /// * 0: for P3INSDMA |
| /// * 1: for P3INSOP |
| /// ### |
| /// %unsigned 1 wID |
| /// : RF 0x0 |
| /// ### |
| /// * 0: write to RF |
| /// ### |
| /// %unsigned 1 wCtl |
| /// : DISABLE 0x0 |
| /// : ENABLE 0x1 |
| /// ### |
| /// * DISABLE: no writing back to RF |
| /// * ENABLE: enable writing result to RF |
| /// ### |
| /// %unsigned 1 RESD1 |
| /// ### |
| /// * reserved |
| /// ### |
| /// %unsigned 8 op |
| /// ### |
| /// * Relative op-code for pipeline |
| /// ### |
| /// : BUBL 0xFF |
| /// ### |
| /// * Force to generate bubbles |
| /// ### |
| /// %unsigned 1 ID |
| /// : OP 0x1 |
| /// ### |
| /// * == 1'b1 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3INSOPWRF |
| #define h_P3INSOPWRF (){} |
| |
| #define BA_P3INSOPWRF_rpu 0x0000 |
| #define B16P3INSOPWRF_rpu 0x0000 |
| #define LSb32P3INSOPWRF_rpu 0 |
| #define LSb16P3INSOPWRF_rpu 0 |
| #define bP3INSOPWRF_rpu 5 |
| #define MSK32P3INSOPWRF_rpu 0x0000001F |
| |
| #define BA_P3INSOPWRF_rpv 0x0000 |
| #define B16P3INSOPWRF_rpv 0x0000 |
| #define LSb32P3INSOPWRF_rpv 5 |
| #define LSb16P3INSOPWRF_rpv 5 |
| #define bP3INSOPWRF_rpv 5 |
| #define MSK32P3INSOPWRF_rpv 0x000003E0 |
| |
| #define BA_P3INSOPWRF_wp 0x0001 |
| #define B16P3INSOPWRF_wp 0x0000 |
| #define LSb32P3INSOPWRF_wp 10 |
| #define LSb16P3INSOPWRF_wp 10 |
| #define bP3INSOPWRF_wp 5 |
| #define MSK32P3INSOPWRF_wp 0x00007C00 |
| |
| #define BA_P3INSOPWRF_RESD0 0x0001 |
| #define B16P3INSOPWRF_RESD0 0x0000 |
| #define LSb32P3INSOPWRF_RESD0 15 |
| #define LSb16P3INSOPWRF_RESD0 15 |
| #define bP3INSOPWRF_RESD0 4 |
| #define MSK32P3INSOPWRF_RESD0 0x00078000 |
| |
| #define BA_P3INSOPWRF_ID_DMAOP 0x0002 |
| #define B16P3INSOPWRF_ID_DMAOP 0x0002 |
| #define LSb32P3INSOPWRF_ID_DMAOP 19 |
| #define LSb16P3INSOPWRF_ID_DMAOP 3 |
| #define bP3INSOPWRF_ID_DMAOP 1 |
| #define MSK32P3INSOPWRF_ID_DMAOP 0x00080000 |
| #define P3INSOPWRF_ID_DMAOP_INSOP 0x1 |
| |
| #define BA_P3INSOPWRF_wID 0x0002 |
| #define B16P3INSOPWRF_wID 0x0002 |
| #define LSb32P3INSOPWRF_wID 20 |
| #define LSb16P3INSOPWRF_wID 4 |
| #define bP3INSOPWRF_wID 1 |
| #define MSK32P3INSOPWRF_wID 0x00100000 |
| #define P3INSOPWRF_wID_RF 0x0 |
| |
| #define BA_P3INSOPWRF_wCtl 0x0002 |
| #define B16P3INSOPWRF_wCtl 0x0002 |
| #define LSb32P3INSOPWRF_wCtl 21 |
| #define LSb16P3INSOPWRF_wCtl 5 |
| #define bP3INSOPWRF_wCtl 1 |
| #define MSK32P3INSOPWRF_wCtl 0x00200000 |
| #define P3INSOPWRF_wCtl_DISABLE 0x0 |
| #define P3INSOPWRF_wCtl_ENABLE 0x1 |
| |
| #define BA_P3INSOPWRF_RESD1 0x0002 |
| #define B16P3INSOPWRF_RESD1 0x0002 |
| #define LSb32P3INSOPWRF_RESD1 22 |
| #define LSb16P3INSOPWRF_RESD1 6 |
| #define bP3INSOPWRF_RESD1 1 |
| #define MSK32P3INSOPWRF_RESD1 0x00400000 |
| |
| #define BA_P3INSOPWRF_op 0x0002 |
| #define B16P3INSOPWRF_op 0x0002 |
| #define LSb32P3INSOPWRF_op 23 |
| #define LSb16P3INSOPWRF_op 7 |
| #define bP3INSOPWRF_op 8 |
| #define MSK32P3INSOPWRF_op 0x7F800000 |
| #define P3INSOPWRF_op_BUBL 0xFF |
| |
| #define BA_P3INSOPWRF_ID 0x0003 |
| #define B16P3INSOPWRF_ID 0x0002 |
| #define LSb32P3INSOPWRF_ID 31 |
| #define LSb16P3INSOPWRF_ID 15 |
| #define bP3INSOPWRF_ID 1 |
| #define MSK32P3INSOPWRF_ID 0x80000000 |
| #define P3INSOPWRF_ID_OP 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3INSOPWRF { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3INSOPWRF_rpu(r32) _BFGET_(r32, 4, 0) |
| #define SET32P3INSOPWRF_rpu(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16P3INSOPWRF_rpu(r16) _BFGET_(r16, 4, 0) |
| #define SET16P3INSOPWRF_rpu(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32P3INSOPWRF_rpv(r32) _BFGET_(r32, 9, 5) |
| #define SET32P3INSOPWRF_rpv(r32,v) _BFSET_(r32, 9, 5,v) |
| #define GET16P3INSOPWRF_rpv(r16) _BFGET_(r16, 9, 5) |
| #define SET16P3INSOPWRF_rpv(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32P3INSOPWRF_wp(r32) _BFGET_(r32,14,10) |
| #define SET32P3INSOPWRF_wp(r32,v) _BFSET_(r32,14,10,v) |
| #define GET16P3INSOPWRF_wp(r16) _BFGET_(r16,14,10) |
| #define SET16P3INSOPWRF_wp(r16,v) _BFSET_(r16,14,10,v) |
| |
| #define GET32P3INSOPWRF_RESD0(r32) _BFGET_(r32,18,15) |
| #define SET32P3INSOPWRF_RESD0(r32,v) _BFSET_(r32,18,15,v) |
| |
| #define GET32P3INSOPWRF_ID_DMAOP(r32) _BFGET_(r32,19,19) |
| #define SET32P3INSOPWRF_ID_DMAOP(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16P3INSOPWRF_ID_DMAOP(r16) _BFGET_(r16, 3, 3) |
| #define SET16P3INSOPWRF_ID_DMAOP(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32P3INSOPWRF_wID(r32) _BFGET_(r32,20,20) |
| #define SET32P3INSOPWRF_wID(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16P3INSOPWRF_wID(r16) _BFGET_(r16, 4, 4) |
| #define SET16P3INSOPWRF_wID(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32P3INSOPWRF_wCtl(r32) _BFGET_(r32,21,21) |
| #define SET32P3INSOPWRF_wCtl(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16P3INSOPWRF_wCtl(r16) _BFGET_(r16, 5, 5) |
| #define SET16P3INSOPWRF_wCtl(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32P3INSOPWRF_RESD1(r32) _BFGET_(r32,22,22) |
| #define SET32P3INSOPWRF_RESD1(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16P3INSOPWRF_RESD1(r16) _BFGET_(r16, 6, 6) |
| #define SET16P3INSOPWRF_RESD1(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32P3INSOPWRF_op(r32) _BFGET_(r32,30,23) |
| #define SET32P3INSOPWRF_op(r32,v) _BFSET_(r32,30,23,v) |
| #define GET16P3INSOPWRF_op(r16) _BFGET_(r16,14, 7) |
| #define SET16P3INSOPWRF_op(r16,v) _BFSET_(r16,14, 7,v) |
| |
| #define GET32P3INSOPWRF_ID(r32) _BFGET_(r32,31,31) |
| #define SET32P3INSOPWRF_ID(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16P3INSOPWRF_ID(r16) _BFGET_(r16,15,15) |
| #define SET16P3INSOPWRF_ID(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_rpu : 5; |
| UNSG32 u_rpv : 5; |
| UNSG32 u_wp : 5; |
| UNSG32 u_RESD0 : 4; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 u_wID : 1; |
| UNSG32 u_wCtl : 1; |
| UNSG32 u_RESD1 : 1; |
| UNSG32 u_op : 8; |
| UNSG32 u_ID : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3INSOPWRF; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3INSOPWRF_drvrd(SIE_P3INSOPWRF *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3INSOPWRF_drvwr(SIE_P3INSOPWRF *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3INSOPWRF_reset(SIE_P3INSOPWRF *p); |
| SIGN32 P3INSOPWRF_cmp (SIE_P3INSOPWRF *p, SIE_P3INSOPWRF *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3INSOPWRF_check(p,pie,pfx,hLOG) P3INSOPWRF_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3INSOPWRF_print(p, pfx,hLOG) P3INSOPWRF_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3INSOPWRF |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3INSOPWDMEM biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 5 rpu |
| /// ### |
| /// * RF read address for u pipe (absolute address) |
| /// ### |
| /// %unsigned 5 rpv |
| /// ### |
| /// * RF read address for v pipe (absolute address) |
| /// ### |
| /// %unsigned 7 wptrDlt |
| /// ### |
| /// * Relative write pointer, in 64b |
| /// ### |
| /// %unsigned 2 wr |
| /// : 2x4 0x0 |
| /// : 4x1 0x1 |
| /// : 8x1 0x1 |
| /// : 4x2 0x1 |
| /// : 4x1L 0x2 |
| /// : 4x1H 0x3 |
| /// : NONE 0x0 |
| /// ### |
| /// * Write mode |
| /// * The actual write operation is controlled by wCtl as ENABLE |
| /// ### |
| /// %unsigned 1 ID_DMAOP |
| /// : INSOP 0x1 |
| /// ### |
| /// * 0: for P3INSDMA |
| /// * 1: for P3INSOP |
| /// ### |
| /// %unsigned 1 wID |
| /// : DMEM 0x1 |
| /// ### |
| /// * 1: write to DMEM |
| /// ### |
| /// %unsigned 1 wCtl |
| /// : DISABLE 0x0 |
| /// : ENABLE 0x1 |
| /// ### |
| /// * DISABLE: no writing result to DMEM |
| /// * ENABLE: enable writing result to DMEM |
| /// ### |
| /// %unsigned 1 RESD |
| /// ### |
| /// * reserved |
| /// ### |
| /// %unsigned 8 op |
| /// ### |
| /// * Relative op-code for pipeline |
| /// ### |
| /// : BUBL 0xFF |
| /// ### |
| /// * Force to generate bubbles |
| /// ### |
| /// %unsigned 1 ID |
| /// : OP 0x1 |
| /// ### |
| /// * == 1'b1 |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3INSOPWDMEM |
| #define h_P3INSOPWDMEM (){} |
| |
| #define BA_P3INSOPWDMEM_rpu 0x0000 |
| #define B16P3INSOPWDMEM_rpu 0x0000 |
| #define LSb32P3INSOPWDMEM_rpu 0 |
| #define LSb16P3INSOPWDMEM_rpu 0 |
| #define bP3INSOPWDMEM_rpu 5 |
| #define MSK32P3INSOPWDMEM_rpu 0x0000001F |
| |
| #define BA_P3INSOPWDMEM_rpv 0x0000 |
| #define B16P3INSOPWDMEM_rpv 0x0000 |
| #define LSb32P3INSOPWDMEM_rpv 5 |
| #define LSb16P3INSOPWDMEM_rpv 5 |
| #define bP3INSOPWDMEM_rpv 5 |
| #define MSK32P3INSOPWDMEM_rpv 0x000003E0 |
| |
| #define BA_P3INSOPWDMEM_wptrDlt 0x0001 |
| #define B16P3INSOPWDMEM_wptrDlt 0x0000 |
| #define LSb32P3INSOPWDMEM_wptrDlt 10 |
| #define LSb16P3INSOPWDMEM_wptrDlt 10 |
| #define bP3INSOPWDMEM_wptrDlt 7 |
| #define MSK32P3INSOPWDMEM_wptrDlt 0x0001FC00 |
| |
| #define BA_P3INSOPWDMEM_wr 0x0002 |
| #define B16P3INSOPWDMEM_wr 0x0002 |
| #define LSb32P3INSOPWDMEM_wr 17 |
| #define LSb16P3INSOPWDMEM_wr 1 |
| #define bP3INSOPWDMEM_wr 2 |
| #define MSK32P3INSOPWDMEM_wr 0x00060000 |
| #define P3INSOPWDMEM_wr_2x4 0x0 |
| #define P3INSOPWDMEM_wr_4x1 0x1 |
| #define P3INSOPWDMEM_wr_8x1 0x1 |
| #define P3INSOPWDMEM_wr_4x2 0x1 |
| #define P3INSOPWDMEM_wr_4x1L 0x2 |
| #define P3INSOPWDMEM_wr_4x1H 0x3 |
| #define P3INSOPWDMEM_wr_NONE 0x0 |
| |
| #define BA_P3INSOPWDMEM_ID_DMAOP 0x0002 |
| #define B16P3INSOPWDMEM_ID_DMAOP 0x0002 |
| #define LSb32P3INSOPWDMEM_ID_DMAOP 19 |
| #define LSb16P3INSOPWDMEM_ID_DMAOP 3 |
| #define bP3INSOPWDMEM_ID_DMAOP 1 |
| #define MSK32P3INSOPWDMEM_ID_DMAOP 0x00080000 |
| #define P3INSOPWDMEM_ID_DMAOP_INSOP 0x1 |
| |
| #define BA_P3INSOPWDMEM_wID 0x0002 |
| #define B16P3INSOPWDMEM_wID 0x0002 |
| #define LSb32P3INSOPWDMEM_wID 20 |
| #define LSb16P3INSOPWDMEM_wID 4 |
| #define bP3INSOPWDMEM_wID 1 |
| #define MSK32P3INSOPWDMEM_wID 0x00100000 |
| #define P3INSOPWDMEM_wID_DMEM 0x1 |
| |
| #define BA_P3INSOPWDMEM_wCtl 0x0002 |
| #define B16P3INSOPWDMEM_wCtl 0x0002 |
| #define LSb32P3INSOPWDMEM_wCtl 21 |
| #define LSb16P3INSOPWDMEM_wCtl 5 |
| #define bP3INSOPWDMEM_wCtl 1 |
| #define MSK32P3INSOPWDMEM_wCtl 0x00200000 |
| #define P3INSOPWDMEM_wCtl_DISABLE 0x0 |
| #define P3INSOPWDMEM_wCtl_ENABLE 0x1 |
| |
| #define BA_P3INSOPWDMEM_RESD 0x0002 |
| #define B16P3INSOPWDMEM_RESD 0x0002 |
| #define LSb32P3INSOPWDMEM_RESD 22 |
| #define LSb16P3INSOPWDMEM_RESD 6 |
| #define bP3INSOPWDMEM_RESD 1 |
| #define MSK32P3INSOPWDMEM_RESD 0x00400000 |
| |
| #define BA_P3INSOPWDMEM_op 0x0002 |
| #define B16P3INSOPWDMEM_op 0x0002 |
| #define LSb32P3INSOPWDMEM_op 23 |
| #define LSb16P3INSOPWDMEM_op 7 |
| #define bP3INSOPWDMEM_op 8 |
| #define MSK32P3INSOPWDMEM_op 0x7F800000 |
| #define P3INSOPWDMEM_op_BUBL 0xFF |
| |
| #define BA_P3INSOPWDMEM_ID 0x0003 |
| #define B16P3INSOPWDMEM_ID 0x0002 |
| #define LSb32P3INSOPWDMEM_ID 31 |
| #define LSb16P3INSOPWDMEM_ID 15 |
| #define bP3INSOPWDMEM_ID 1 |
| #define MSK32P3INSOPWDMEM_ID 0x80000000 |
| #define P3INSOPWDMEM_ID_OP 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3INSOPWDMEM { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3INSOPWDMEM_rpu(r32) _BFGET_(r32, 4, 0) |
| #define SET32P3INSOPWDMEM_rpu(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16P3INSOPWDMEM_rpu(r16) _BFGET_(r16, 4, 0) |
| #define SET16P3INSOPWDMEM_rpu(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32P3INSOPWDMEM_rpv(r32) _BFGET_(r32, 9, 5) |
| #define SET32P3INSOPWDMEM_rpv(r32,v) _BFSET_(r32, 9, 5,v) |
| #define GET16P3INSOPWDMEM_rpv(r16) _BFGET_(r16, 9, 5) |
| #define SET16P3INSOPWDMEM_rpv(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32P3INSOPWDMEM_wptrDlt(r32) _BFGET_(r32,16,10) |
| #define SET32P3INSOPWDMEM_wptrDlt(r32,v) _BFSET_(r32,16,10,v) |
| |
| #define GET32P3INSOPWDMEM_wr(r32) _BFGET_(r32,18,17) |
| #define SET32P3INSOPWDMEM_wr(r32,v) _BFSET_(r32,18,17,v) |
| #define GET16P3INSOPWDMEM_wr(r16) _BFGET_(r16, 2, 1) |
| #define SET16P3INSOPWDMEM_wr(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32P3INSOPWDMEM_ID_DMAOP(r32) _BFGET_(r32,19,19) |
| #define SET32P3INSOPWDMEM_ID_DMAOP(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16P3INSOPWDMEM_ID_DMAOP(r16) _BFGET_(r16, 3, 3) |
| #define SET16P3INSOPWDMEM_ID_DMAOP(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32P3INSOPWDMEM_wID(r32) _BFGET_(r32,20,20) |
| #define SET32P3INSOPWDMEM_wID(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16P3INSOPWDMEM_wID(r16) _BFGET_(r16, 4, 4) |
| #define SET16P3INSOPWDMEM_wID(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32P3INSOPWDMEM_wCtl(r32) _BFGET_(r32,21,21) |
| #define SET32P3INSOPWDMEM_wCtl(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16P3INSOPWDMEM_wCtl(r16) _BFGET_(r16, 5, 5) |
| #define SET16P3INSOPWDMEM_wCtl(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32P3INSOPWDMEM_RESD(r32) _BFGET_(r32,22,22) |
| #define SET32P3INSOPWDMEM_RESD(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16P3INSOPWDMEM_RESD(r16) _BFGET_(r16, 6, 6) |
| #define SET16P3INSOPWDMEM_RESD(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32P3INSOPWDMEM_op(r32) _BFGET_(r32,30,23) |
| #define SET32P3INSOPWDMEM_op(r32,v) _BFSET_(r32,30,23,v) |
| #define GET16P3INSOPWDMEM_op(r16) _BFGET_(r16,14, 7) |
| #define SET16P3INSOPWDMEM_op(r16,v) _BFSET_(r16,14, 7,v) |
| |
| #define GET32P3INSOPWDMEM_ID(r32) _BFGET_(r32,31,31) |
| #define SET32P3INSOPWDMEM_ID(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16P3INSOPWDMEM_ID(r16) _BFGET_(r16,15,15) |
| #define SET16P3INSOPWDMEM_ID(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_rpu : 5; |
| UNSG32 u_rpv : 5; |
| UNSG32 u_wptrDlt : 7; |
| UNSG32 u_wr : 2; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 u_wID : 1; |
| UNSG32 u_wCtl : 1; |
| UNSG32 u_RESD : 1; |
| UNSG32 u_op : 8; |
| UNSG32 u_ID : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3INSOPWDMEM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3INSOPWDMEM_drvrd(SIE_P3INSOPWDMEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3INSOPWDMEM_drvwr(SIE_P3INSOPWDMEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3INSOPWDMEM_reset(SIE_P3INSOPWDMEM *p); |
| SIGN32 P3INSOPWDMEM_cmp (SIE_P3INSOPWDMEM *p, SIE_P3INSOPWDMEM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3INSOPWDMEM_check(p,pie,pfx,hLOG) P3INSOPWDMEM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3INSOPWDMEM_print(p, pfx,hLOG) P3INSOPWDMEM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3INSOPWDMEM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3TblEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 word_0i |
| /// %unsigned 32 word_1i |
| /// %unsigned 32 word_2i |
| /// %unsigned 32 word_3i |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 128b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3TblEntry |
| #define h_P3TblEntry (){} |
| |
| #define BA_P3TblEntry_word_0i 0x0000 |
| #define B16P3TblEntry_word_0i 0x0000 |
| #define LSb32P3TblEntry_word_0i 0 |
| #define LSb16P3TblEntry_word_0i 0 |
| #define bP3TblEntry_word_0i 32 |
| #define MSK32P3TblEntry_word_0i 0xFFFFFFFF |
| |
| #define BA_P3TblEntry_word_1i 0x0004 |
| #define B16P3TblEntry_word_1i 0x0004 |
| #define LSb32P3TblEntry_word_1i 0 |
| #define LSb16P3TblEntry_word_1i 0 |
| #define bP3TblEntry_word_1i 32 |
| #define MSK32P3TblEntry_word_1i 0xFFFFFFFF |
| |
| #define BA_P3TblEntry_word_2i 0x0008 |
| #define B16P3TblEntry_word_2i 0x0008 |
| #define LSb32P3TblEntry_word_2i 0 |
| #define LSb16P3TblEntry_word_2i 0 |
| #define bP3TblEntry_word_2i 32 |
| #define MSK32P3TblEntry_word_2i 0xFFFFFFFF |
| |
| #define BA_P3TblEntry_word_3i 0x000C |
| #define B16P3TblEntry_word_3i 0x000C |
| #define LSb32P3TblEntry_word_3i 0 |
| #define LSb16P3TblEntry_word_3i 0 |
| #define bP3TblEntry_word_3i 32 |
| #define MSK32P3TblEntry_word_3i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3TblEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3TblEntry_word_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3TblEntry_word_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32P3TblEntry_word_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3TblEntry_word_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_1i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32P3TblEntry_word_2i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3TblEntry_word_2i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_2i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32P3TblEntry_word_3i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3TblEntry_word_3i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_3i : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3TblEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3TblEntry_drvrd(SIE_P3TblEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3TblEntry_drvwr(SIE_P3TblEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3TblEntry_reset(SIE_P3TblEntry *p); |
| SIGN32 P3TblEntry_cmp (SIE_P3TblEntry *p, SIE_P3TblEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3TblEntry_check(p,pie,pfx,hLOG) P3TblEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3TblEntry_print(p, pfx,hLOG) P3TblEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3TblEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3OpTblEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 word_0i |
| /// %unsigned 32 word_1i |
| /// @ 0x00008 (P) |
| /// %unsigned 14 word2 |
| /// %% 18 # Stuffing bits... |
| /// @ 0x0000C rsvd (RW-) |
| /// %unsigned 32 val |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16B, bits: 110b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3OpTblEntry |
| #define h_P3OpTblEntry (){} |
| |
| #define BA_P3OpTblEntry_word_0i 0x0000 |
| #define B16P3OpTblEntry_word_0i 0x0000 |
| #define LSb32P3OpTblEntry_word_0i 0 |
| #define LSb16P3OpTblEntry_word_0i 0 |
| #define bP3OpTblEntry_word_0i 32 |
| #define MSK32P3OpTblEntry_word_0i 0xFFFFFFFF |
| |
| #define BA_P3OpTblEntry_word_1i 0x0004 |
| #define B16P3OpTblEntry_word_1i 0x0004 |
| #define LSb32P3OpTblEntry_word_1i 0 |
| #define LSb16P3OpTblEntry_word_1i 0 |
| #define bP3OpTblEntry_word_1i 32 |
| #define MSK32P3OpTblEntry_word_1i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3OpTblEntry_word2 0x0008 |
| #define B16P3OpTblEntry_word2 0x0008 |
| #define LSb32P3OpTblEntry_word2 0 |
| #define LSb16P3OpTblEntry_word2 0 |
| #define bP3OpTblEntry_word2 14 |
| #define MSK32P3OpTblEntry_word2 0x00003FFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3OpTblEntry_rsvd 0x000C |
| |
| #define BA_P3OpTblEntry_rsvd_val 0x000C |
| #define B16P3OpTblEntry_rsvd_val 0x000C |
| #define LSb32P3OpTblEntry_rsvd_val 0 |
| #define LSb16P3OpTblEntry_rsvd_val 0 |
| #define bP3OpTblEntry_rsvd_val 32 |
| #define MSK32P3OpTblEntry_rsvd_val 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3OpTblEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3OpTblEntry_word_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3OpTblEntry_word_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32P3OpTblEntry_word_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3OpTblEntry_word_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_1i : 32; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3OpTblEntry_word2(r32) _BFGET_(r32,13, 0) |
| #define SET32P3OpTblEntry_word2(r32,v) _BFSET_(r32,13, 0,v) |
| #define GET16P3OpTblEntry_word2(r16) _BFGET_(r16,13, 0) |
| #define SET16P3OpTblEntry_word2(r16,v) _BFSET_(r16,13, 0,v) |
| |
| UNSG32 u_word2 : 14; |
| UNSG32 RSVDx8_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3OpTblEntry_rsvd_val(r32) _BFGET_(r32,31, 0) |
| #define SET32P3OpTblEntry_rsvd_val(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3OpTblEntry_rsvd {\ |
| UNSG32 ursvd_val : 32;\ |
| } |
| union { UNSG32 u32P3OpTblEntry_rsvd; |
| struct w32P3OpTblEntry_rsvd; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3OpTblEntry; |
| |
| typedef union T32P3OpTblEntry_rsvd |
| { UNSG32 u32; |
| struct w32P3OpTblEntry_rsvd; |
| } T32P3OpTblEntry_rsvd; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TP3OpTblEntry_rsvd |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3OpTblEntry_rsvd; |
| }; |
| } TP3OpTblEntry_rsvd; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3OpTblEntry_drvrd(SIE_P3OpTblEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3OpTblEntry_drvwr(SIE_P3OpTblEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3OpTblEntry_reset(SIE_P3OpTblEntry *p); |
| SIGN32 P3OpTblEntry_cmp (SIE_P3OpTblEntry *p, SIE_P3OpTblEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3OpTblEntry_check(p,pie,pfx,hLOG) P3OpTblEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3OpTblEntry_print(p, pfx,hLOG) P3OpTblEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3OpTblEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3IramEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 word |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3IramEntry |
| #define h_P3IramEntry (){} |
| |
| #define BA_P3IramEntry_word 0x0000 |
| #define B16P3IramEntry_word 0x0000 |
| #define LSb32P3IramEntry_word 0 |
| #define LSb16P3IramEntry_word 0 |
| #define bP3IramEntry_word 32 |
| #define MSK32P3IramEntry_word 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3IramEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3IramEntry_word(r32) _BFGET_(r32,31, 0) |
| #define SET32P3IramEntry_word(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3IramEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3IramEntry_drvrd(SIE_P3IramEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3IramEntry_drvwr(SIE_P3IramEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3IramEntry_reset(SIE_P3IramEntry *p); |
| SIGN32 P3IramEntry_cmp (SIE_P3IramEntry *p, SIE_P3IramEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3IramEntry_check(p,pie,pfx,hLOG) P3IramEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3IramEntry_print(p, pfx,hLOG) P3IramEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3IramEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3CmdEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 32 word_0i |
| /// %unsigned 32 word_1i |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 64b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3CmdEntry |
| #define h_P3CmdEntry (){} |
| |
| #define BA_P3CmdEntry_word_0i 0x0000 |
| #define B16P3CmdEntry_word_0i 0x0000 |
| #define LSb32P3CmdEntry_word_0i 0 |
| #define LSb16P3CmdEntry_word_0i 0 |
| #define bP3CmdEntry_word_0i 32 |
| #define MSK32P3CmdEntry_word_0i 0xFFFFFFFF |
| |
| #define BA_P3CmdEntry_word_1i 0x0004 |
| #define B16P3CmdEntry_word_1i 0x0004 |
| #define LSb32P3CmdEntry_word_1i 0 |
| #define LSb16P3CmdEntry_word_1i 0 |
| #define bP3CmdEntry_word_1i 32 |
| #define MSK32P3CmdEntry_word_1i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3CmdEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3CmdEntry_word_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3CmdEntry_word_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_0i : 32; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32P3CmdEntry_word_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3CmdEntry_word_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| UNSG32 u_word_1i : 32; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3CmdEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3CmdEntry_drvrd(SIE_P3CmdEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3CmdEntry_drvwr(SIE_P3CmdEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3CmdEntry_reset(SIE_P3CmdEntry *p); |
| SIGN32 P3CmdEntry_cmp (SIE_P3CmdEntry *p, SIE_P3CmdEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3CmdEntry_check(p,pie,pfx,hLOG) P3CmdEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3CmdEntry_print(p, pfx,hLOG) P3CmdEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3CmdEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3IRAM (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3IramEntry tbl REG [2048] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8192B, bits: 65536b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3IRAM |
| #define h_P3IRAM (){} |
| |
| #define RA_P3IRAM_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3IRAM { |
| /////////////////////////////////////////////////////////// |
| SIE_P3IramEntry ie_tbl[2048]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3IRAM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3IRAM_drvrd(SIE_P3IRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3IRAM_drvwr(SIE_P3IRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3IRAM_reset(SIE_P3IRAM *p); |
| SIGN32 P3IRAM_cmp (SIE_P3IRAM *p, SIE_P3IRAM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3IRAM_check(p,pie,pfx,hLOG) P3IRAM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3IRAM_print(p, pfx,hLOG) P3IRAM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3IRAM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3CLUT (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3FNP tbl REG [256] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 1024B, bits: 8192b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3CLUT |
| #define h_P3CLUT (){} |
| |
| #define RA_P3CLUT_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3CLUT { |
| /////////////////////////////////////////////////////////// |
| SIE_P3FNP ie_tbl[256]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3CLUT; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3CLUT_drvrd(SIE_P3CLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3CLUT_drvwr(SIE_P3CLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3CLUT_reset(SIE_P3CLUT *p); |
| SIGN32 P3CLUT_cmp (SIE_P3CLUT *p, SIE_P3CLUT *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3CLUT_check(p,pie,pfx,hLOG) P3CLUT_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3CLUT_print(p, pfx,hLOG) P3CLUT_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3CLUT |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3CMDLUT (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3CmdEntry tbl REG [768] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 6144B, bits: 49152b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3CMDLUT |
| #define h_P3CMDLUT (){} |
| |
| #define RA_P3CMDLUT_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3CMDLUT { |
| /////////////////////////////////////////////////////////// |
| SIE_P3CmdEntry ie_tbl[768]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3CMDLUT; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3CMDLUT_drvrd(SIE_P3CMDLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3CMDLUT_drvwr(SIE_P3CMDLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3CMDLUT_reset(SIE_P3CMDLUT *p); |
| SIGN32 P3CMDLUT_cmp (SIE_P3CMDLUT *p, SIE_P3CMDLUT *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3CMDLUT_check(p,pie,pfx,hLOG) P3CMDLUT_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3CMDLUT_print(p, pfx,hLOG) P3CMDLUT_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3CMDLUT |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3DMEM (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3TblEntry tbl REG [1024] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16384B, bits: 131072b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3DMEM |
| #define h_P3DMEM (){} |
| |
| #define RA_P3DMEM_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3DMEM { |
| /////////////////////////////////////////////////////////// |
| SIE_P3TblEntry ie_tbl[1024]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3DMEM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3DMEM_drvrd(SIE_P3DMEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3DMEM_drvwr(SIE_P3DMEM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3DMEM_reset(SIE_P3DMEM *p); |
| SIGN32 P3DMEM_cmp (SIE_P3DMEM *p, SIE_P3DMEM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3DMEM_check(p,pie,pfx,hLOG) P3DMEM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3DMEM_print(p, pfx,hLOG) P3DMEM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3DMEM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FigoEntry (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 24 word |
| /// %% 8 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 24b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FigoEntry |
| #define h_P3FigoEntry (){} |
| |
| #define BA_P3FigoEntry_word 0x0000 |
| #define B16P3FigoEntry_word 0x0000 |
| #define LSb32P3FigoEntry_word 0 |
| #define LSb16P3FigoEntry_word 0 |
| #define bP3FigoEntry_word 24 |
| #define MSK32P3FigoEntry_word 0x00FFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FigoEntry { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FigoEntry_word(r32) _BFGET_(r32,23, 0) |
| #define SET32P3FigoEntry_word(r32,v) _BFSET_(r32,23, 0,v) |
| |
| UNSG32 u_word : 24; |
| UNSG32 RSVDx0_b24 : 8; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FigoEntry; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FigoEntry_drvrd(SIE_P3FigoEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FigoEntry_drvwr(SIE_P3FigoEntry *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FigoEntry_reset(SIE_P3FigoEntry *p); |
| SIGN32 P3FigoEntry_cmp (SIE_P3FigoEntry *p, SIE_P3FigoEntry *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FigoEntry_check(p,pie,pfx,hLOG) P3FigoEntry_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FigoEntry_print(p, pfx,hLOG) P3FigoEntry_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FigoEntry |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FigoITCM (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3FigoEntry tbl REG [4096] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 16384B, bits: 98304b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FigoITCM |
| #define h_P3FigoITCM (){} |
| |
| #define RA_P3FigoITCM_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FigoITCM { |
| /////////////////////////////////////////////////////////// |
| SIE_P3FigoEntry ie_tbl[4096]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FigoITCM; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FigoITCM_drvrd(SIE_P3FigoITCM *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FigoITCM_drvwr(SIE_P3FigoITCM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FigoITCM_reset(SIE_P3FigoITCM *p); |
| SIGN32 P3FigoITCM_cmp (SIE_P3FigoITCM *p, SIE_P3FigoITCM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FigoITCM_check(p,pie,pfx,hLOG) P3FigoITCM_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FigoITCM_print(p, pfx,hLOG) P3FigoITCM_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FigoITCM |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3SReq biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Dat |
| /// $P3TblEntry Dat REG |
| /// @ 0x00010 (P) |
| /// %unsigned 10 Adr |
| /// %unsigned 4 Wmsk |
| /// %unsigned 2 Mode |
| /// : NOP 0x0 |
| /// : RD 0x1 |
| /// : WR 0x2 |
| /// : SEM 0x3 |
| /// %unsigned 2 id |
| /// : DR 0x0 |
| /// : WA 0x1 |
| /// : RA 0x2 |
| /// : CFG 0x3 |
| /// %% 14 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 20B, bits: 146b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3SReq |
| #define h_P3SReq (){} |
| |
| #define RA_P3SReq_Dat 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3SReq_Adr 0x0010 |
| #define B16P3SReq_Adr 0x0010 |
| #define LSb32P3SReq_Adr 0 |
| #define LSb16P3SReq_Adr 0 |
| #define bP3SReq_Adr 10 |
| #define MSK32P3SReq_Adr 0x000003FF |
| |
| #define BA_P3SReq_Wmsk 0x0011 |
| #define B16P3SReq_Wmsk 0x0010 |
| #define LSb32P3SReq_Wmsk 10 |
| #define LSb16P3SReq_Wmsk 10 |
| #define bP3SReq_Wmsk 4 |
| #define MSK32P3SReq_Wmsk 0x00003C00 |
| |
| #define BA_P3SReq_Mode 0x0011 |
| #define B16P3SReq_Mode 0x0010 |
| #define LSb32P3SReq_Mode 14 |
| #define LSb16P3SReq_Mode 14 |
| #define bP3SReq_Mode 2 |
| #define MSK32P3SReq_Mode 0x0000C000 |
| #define P3SReq_Mode_NOP 0x0 |
| #define P3SReq_Mode_RD 0x1 |
| #define P3SReq_Mode_WR 0x2 |
| #define P3SReq_Mode_SEM 0x3 |
| |
| #define BA_P3SReq_id 0x0012 |
| #define B16P3SReq_id 0x0012 |
| #define LSb32P3SReq_id 16 |
| #define LSb16P3SReq_id 0 |
| #define bP3SReq_id 2 |
| #define MSK32P3SReq_id 0x00030000 |
| #define P3SReq_id_DR 0x0 |
| #define P3SReq_id_WA 0x1 |
| #define P3SReq_id_RA 0x2 |
| #define P3SReq_id_CFG 0x3 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3SReq { |
| /////////////////////////////////////////////////////////// |
| SIE_P3TblEntry ie_Dat; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3SReq_Adr(r32) _BFGET_(r32, 9, 0) |
| #define SET32P3SReq_Adr(r32,v) _BFSET_(r32, 9, 0,v) |
| #define GET16P3SReq_Adr(r16) _BFGET_(r16, 9, 0) |
| #define SET16P3SReq_Adr(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| #define GET32P3SReq_Wmsk(r32) _BFGET_(r32,13,10) |
| #define SET32P3SReq_Wmsk(r32,v) _BFSET_(r32,13,10,v) |
| #define GET16P3SReq_Wmsk(r16) _BFGET_(r16,13,10) |
| #define SET16P3SReq_Wmsk(r16,v) _BFSET_(r16,13,10,v) |
| |
| #define GET32P3SReq_Mode(r32) _BFGET_(r32,15,14) |
| #define SET32P3SReq_Mode(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16P3SReq_Mode(r16) _BFGET_(r16,15,14) |
| #define SET16P3SReq_Mode(r16,v) _BFSET_(r16,15,14,v) |
| |
| #define GET32P3SReq_id(r32) _BFGET_(r32,17,16) |
| #define SET32P3SReq_id(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16P3SReq_id(r16) _BFGET_(r16, 1, 0) |
| #define SET16P3SReq_id(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| UNSG32 u_Adr : 10; |
| UNSG32 u_Wmsk : 4; |
| UNSG32 u_Mode : 2; |
| UNSG32 u_id : 2; |
| UNSG32 RSVDx10_b18 : 14; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3SReq; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3SReq_drvrd(SIE_P3SReq *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3SReq_drvwr(SIE_P3SReq *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3SReq_reset(SIE_P3SReq *p); |
| SIGN32 P3SReq_cmp (SIE_P3SReq *p, SIE_P3SReq *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3SReq_check(p,pie,pfx,hLOG) P3SReq_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3SReq_print(p, pfx,hLOG) P3SReq_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3SReq |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3SRsp biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 Dat |
| /// $P3TblEntry Dat REG |
| /// @ 0x00010 (P) |
| /// %unsigned 2 id |
| /// : RSVD 0x0 |
| /// : WA 0x1 |
| /// : SEM 0x2 |
| /// : CFG 0x3 |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 20B, bits: 130b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3SRsp |
| #define h_P3SRsp (){} |
| |
| #define RA_P3SRsp_Dat 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3SRsp_id 0x0010 |
| #define B16P3SRsp_id 0x0010 |
| #define LSb32P3SRsp_id 0 |
| #define LSb16P3SRsp_id 0 |
| #define bP3SRsp_id 2 |
| #define MSK32P3SRsp_id 0x00000003 |
| #define P3SRsp_id_RSVD 0x0 |
| #define P3SRsp_id_WA 0x1 |
| #define P3SRsp_id_SEM 0x2 |
| #define P3SRsp_id_CFG 0x3 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3SRsp { |
| /////////////////////////////////////////////////////////// |
| SIE_P3TblEntry ie_Dat; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3SRsp_id(r32) _BFGET_(r32, 1, 0) |
| #define SET32P3SRsp_id(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16P3SRsp_id(r16) _BFGET_(r16, 1, 0) |
| #define SET16P3SRsp_id(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| UNSG32 u_id : 2; |
| UNSG32 RSVDx10_b2 : 30; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3SRsp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3SRsp_drvrd(SIE_P3SRsp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3SRsp_drvwr(SIE_P3SRsp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3SRsp_reset(SIE_P3SRsp *p); |
| SIGN32 P3SRsp_cmp (SIE_P3SRsp *p, SIE_P3SRsp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3SRsp_check(p,pie,pfx,hLOG) P3SRsp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3SRsp_print(p, pfx,hLOG) P3SRsp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3SRsp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FIE biu (4,4) |
| /// ### |
| /// * Pcube flattened instruction exe , depends on P3INSEXE |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 valid |
| /// : BUBL 0x0 |
| /// : VALID 0x1 |
| /// %unsigned 1 id |
| /// : EXE 0x0 |
| /// : DMA 0x1 |
| /// ### |
| /// * This depends on P3INSEXE |
| /// ### |
| /// %unsigned 12 wPtr |
| /// ### |
| /// * 32-bit word address |
| /// ### |
| /// %unsigned 2 wr |
| /// %unsigned 12 rPtr |
| /// ### |
| /// * 32-bit word address |
| /// ### |
| /// %unsigned 2 rd |
| /// %% 2 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 9 op |
| /// %unsigned 4 rfp |
| /// %unsigned 1 unPack |
| /// %% 18 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 44b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FIE |
| #define h_P3FIE (){} |
| |
| #define BA_P3FIE_valid 0x0000 |
| #define B16P3FIE_valid 0x0000 |
| #define LSb32P3FIE_valid 0 |
| #define LSb16P3FIE_valid 0 |
| #define bP3FIE_valid 1 |
| #define MSK32P3FIE_valid 0x00000001 |
| #define P3FIE_valid_BUBL 0x0 |
| #define P3FIE_valid_VALID 0x1 |
| |
| #define BA_P3FIE_id 0x0000 |
| #define B16P3FIE_id 0x0000 |
| #define LSb32P3FIE_id 1 |
| #define LSb16P3FIE_id 1 |
| #define bP3FIE_id 1 |
| #define MSK32P3FIE_id 0x00000002 |
| #define P3FIE_id_EXE 0x0 |
| #define P3FIE_id_DMA 0x1 |
| |
| #define BA_P3FIE_wPtr 0x0000 |
| #define B16P3FIE_wPtr 0x0000 |
| #define LSb32P3FIE_wPtr 2 |
| #define LSb16P3FIE_wPtr 2 |
| #define bP3FIE_wPtr 12 |
| #define MSK32P3FIE_wPtr 0x00003FFC |
| |
| #define BA_P3FIE_wr 0x0001 |
| #define B16P3FIE_wr 0x0000 |
| #define LSb32P3FIE_wr 14 |
| #define LSb16P3FIE_wr 14 |
| #define bP3FIE_wr 2 |
| #define MSK32P3FIE_wr 0x0000C000 |
| |
| #define BA_P3FIE_rPtr 0x0002 |
| #define B16P3FIE_rPtr 0x0002 |
| #define LSb32P3FIE_rPtr 16 |
| #define LSb16P3FIE_rPtr 0 |
| #define bP3FIE_rPtr 12 |
| #define MSK32P3FIE_rPtr 0x0FFF0000 |
| |
| #define BA_P3FIE_rd 0x0003 |
| #define B16P3FIE_rd 0x0002 |
| #define LSb32P3FIE_rd 28 |
| #define LSb16P3FIE_rd 12 |
| #define bP3FIE_rd 2 |
| #define MSK32P3FIE_rd 0x30000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3FIE_op 0x0004 |
| #define B16P3FIE_op 0x0004 |
| #define LSb32P3FIE_op 0 |
| #define LSb16P3FIE_op 0 |
| #define bP3FIE_op 9 |
| #define MSK32P3FIE_op 0x000001FF |
| |
| #define BA_P3FIE_rfp 0x0005 |
| #define B16P3FIE_rfp 0x0004 |
| #define LSb32P3FIE_rfp 9 |
| #define LSb16P3FIE_rfp 9 |
| #define bP3FIE_rfp 4 |
| #define MSK32P3FIE_rfp 0x00001E00 |
| |
| #define BA_P3FIE_unPack 0x0005 |
| #define B16P3FIE_unPack 0x0004 |
| #define LSb32P3FIE_unPack 13 |
| #define LSb16P3FIE_unPack 13 |
| #define bP3FIE_unPack 1 |
| #define MSK32P3FIE_unPack 0x00002000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FIE { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FIE_valid(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3FIE_valid(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3FIE_valid(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3FIE_valid(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3FIE_id(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3FIE_id(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3FIE_id(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3FIE_id(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3FIE_wPtr(r32) _BFGET_(r32,13, 2) |
| #define SET32P3FIE_wPtr(r32,v) _BFSET_(r32,13, 2,v) |
| #define GET16P3FIE_wPtr(r16) _BFGET_(r16,13, 2) |
| #define SET16P3FIE_wPtr(r16,v) _BFSET_(r16,13, 2,v) |
| |
| #define GET32P3FIE_wr(r32) _BFGET_(r32,15,14) |
| #define SET32P3FIE_wr(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16P3FIE_wr(r16) _BFGET_(r16,15,14) |
| #define SET16P3FIE_wr(r16,v) _BFSET_(r16,15,14,v) |
| |
| #define GET32P3FIE_rPtr(r32) _BFGET_(r32,27,16) |
| #define SET32P3FIE_rPtr(r32,v) _BFSET_(r32,27,16,v) |
| #define GET16P3FIE_rPtr(r16) _BFGET_(r16,11, 0) |
| #define SET16P3FIE_rPtr(r16,v) _BFSET_(r16,11, 0,v) |
| |
| #define GET32P3FIE_rd(r32) _BFGET_(r32,29,28) |
| #define SET32P3FIE_rd(r32,v) _BFSET_(r32,29,28,v) |
| #define GET16P3FIE_rd(r16) _BFGET_(r16,13,12) |
| #define SET16P3FIE_rd(r16,v) _BFSET_(r16,13,12,v) |
| |
| UNSG32 u_valid : 1; |
| UNSG32 u_id : 1; |
| UNSG32 u_wPtr : 12; |
| UNSG32 u_wr : 2; |
| UNSG32 u_rPtr : 12; |
| UNSG32 u_rd : 2; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FIE_op(r32) _BFGET_(r32, 8, 0) |
| #define SET32P3FIE_op(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16P3FIE_op(r16) _BFGET_(r16, 8, 0) |
| #define SET16P3FIE_op(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32P3FIE_rfp(r32) _BFGET_(r32,12, 9) |
| #define SET32P3FIE_rfp(r32,v) _BFSET_(r32,12, 9,v) |
| #define GET16P3FIE_rfp(r16) _BFGET_(r16,12, 9) |
| #define SET16P3FIE_rfp(r16,v) _BFSET_(r16,12, 9,v) |
| |
| #define GET32P3FIE_unPack(r32) _BFGET_(r32,13,13) |
| #define SET32P3FIE_unPack(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16P3FIE_unPack(r16) _BFGET_(r16,13,13) |
| #define SET16P3FIE_unPack(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_op : 9; |
| UNSG32 u_rfp : 4; |
| UNSG32 u_unPack : 1; |
| UNSG32 RSVDx4_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FIE; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FIE_drvrd(SIE_P3FIE *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FIE_drvwr(SIE_P3FIE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FIE_reset(SIE_P3FIE *p); |
| SIGN32 P3FIE_cmp (SIE_P3FIE *p, SIE_P3FIE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FIE_check(p,pie,pfx,hLOG) P3FIE_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FIE_print(p, pfx,hLOG) P3FIE_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FIE |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FIS biu (4,4) |
| /// ### |
| /// * Pcube flattened instruction sync entry, depends on P3INSEXE |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 valid |
| /// : BUBL 0x0 |
| /// : VALID 0x1 |
| /// %unsigned 1 id |
| /// : EXE 0x0 |
| /// : DMA 0x1 |
| /// ### |
| /// * This depends on P3INSEXE |
| /// ### |
| /// %unsigned 1 sync |
| /// %unsigned 5 inc |
| /// %unsigned 5 dec |
| /// %unsigned 13 rsvd |
| /// %unsigned 1 ID_DMAOP |
| /// : INSDMA 0x0 |
| /// %% 5 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 27b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FIS |
| #define h_P3FIS (){} |
| |
| #define BA_P3FIS_valid 0x0000 |
| #define B16P3FIS_valid 0x0000 |
| #define LSb32P3FIS_valid 0 |
| #define LSb16P3FIS_valid 0 |
| #define bP3FIS_valid 1 |
| #define MSK32P3FIS_valid 0x00000001 |
| #define P3FIS_valid_BUBL 0x0 |
| #define P3FIS_valid_VALID 0x1 |
| |
| #define BA_P3FIS_id 0x0000 |
| #define B16P3FIS_id 0x0000 |
| #define LSb32P3FIS_id 1 |
| #define LSb16P3FIS_id 1 |
| #define bP3FIS_id 1 |
| #define MSK32P3FIS_id 0x00000002 |
| #define P3FIS_id_EXE 0x0 |
| #define P3FIS_id_DMA 0x1 |
| |
| #define BA_P3FIS_sync 0x0000 |
| #define B16P3FIS_sync 0x0000 |
| #define LSb32P3FIS_sync 2 |
| #define LSb16P3FIS_sync 2 |
| #define bP3FIS_sync 1 |
| #define MSK32P3FIS_sync 0x00000004 |
| |
| #define BA_P3FIS_inc 0x0000 |
| #define B16P3FIS_inc 0x0000 |
| #define LSb32P3FIS_inc 3 |
| #define LSb16P3FIS_inc 3 |
| #define bP3FIS_inc 5 |
| #define MSK32P3FIS_inc 0x000000F8 |
| |
| #define BA_P3FIS_dec 0x0001 |
| #define B16P3FIS_dec 0x0000 |
| #define LSb32P3FIS_dec 8 |
| #define LSb16P3FIS_dec 8 |
| #define bP3FIS_dec 5 |
| #define MSK32P3FIS_dec 0x00001F00 |
| |
| #define BA_P3FIS_rsvd 0x0001 |
| #define B16P3FIS_rsvd 0x0000 |
| #define LSb32P3FIS_rsvd 13 |
| #define LSb16P3FIS_rsvd 13 |
| #define bP3FIS_rsvd 13 |
| #define MSK32P3FIS_rsvd 0x03FFE000 |
| |
| #define BA_P3FIS_ID_DMAOP 0x0003 |
| #define B16P3FIS_ID_DMAOP 0x0002 |
| #define LSb32P3FIS_ID_DMAOP 26 |
| #define LSb16P3FIS_ID_DMAOP 10 |
| #define bP3FIS_ID_DMAOP 1 |
| #define MSK32P3FIS_ID_DMAOP 0x04000000 |
| #define P3FIS_ID_DMAOP_INSDMA 0x0 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FIS { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FIS_valid(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3FIS_valid(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3FIS_valid(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3FIS_valid(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3FIS_id(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3FIS_id(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3FIS_id(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3FIS_id(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3FIS_sync(r32) _BFGET_(r32, 2, 2) |
| #define SET32P3FIS_sync(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16P3FIS_sync(r16) _BFGET_(r16, 2, 2) |
| #define SET16P3FIS_sync(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32P3FIS_inc(r32) _BFGET_(r32, 7, 3) |
| #define SET32P3FIS_inc(r32,v) _BFSET_(r32, 7, 3,v) |
| #define GET16P3FIS_inc(r16) _BFGET_(r16, 7, 3) |
| #define SET16P3FIS_inc(r16,v) _BFSET_(r16, 7, 3,v) |
| |
| #define GET32P3FIS_dec(r32) _BFGET_(r32,12, 8) |
| #define SET32P3FIS_dec(r32,v) _BFSET_(r32,12, 8,v) |
| #define GET16P3FIS_dec(r16) _BFGET_(r16,12, 8) |
| #define SET16P3FIS_dec(r16,v) _BFSET_(r16,12, 8,v) |
| |
| #define GET32P3FIS_rsvd(r32) _BFGET_(r32,25,13) |
| #define SET32P3FIS_rsvd(r32,v) _BFSET_(r32,25,13,v) |
| |
| #define GET32P3FIS_ID_DMAOP(r32) _BFGET_(r32,26,26) |
| #define SET32P3FIS_ID_DMAOP(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16P3FIS_ID_DMAOP(r16) _BFGET_(r16,10,10) |
| #define SET16P3FIS_ID_DMAOP(r16,v) _BFSET_(r16,10,10,v) |
| |
| UNSG32 u_valid : 1; |
| UNSG32 u_id : 1; |
| UNSG32 u_sync : 1; |
| UNSG32 u_inc : 5; |
| UNSG32 u_dec : 5; |
| UNSG32 u_rsvd : 13; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 RSVDx0_b27 : 5; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FIS; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FIS_drvrd(SIE_P3FIS *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FIS_drvwr(SIE_P3FIS *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FIS_reset(SIE_P3FIS *p); |
| SIGN32 P3FIS_cmp (SIE_P3FIS *p, SIE_P3FIS *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FIS_check(p,pie,pfx,hLOG) P3FIS_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FIS_print(p, pfx,hLOG) P3FIS_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FIS |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FIR biu (4,4) |
| /// ### |
| /// * Pcube flattened instruction OP RF , depends on P3INSOPRF |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 valid |
| /// : BUBL 0x0 |
| /// : VALID 0x1 |
| /// %unsigned 1 id |
| /// : EXE 0x0 |
| /// : OP 0x1 |
| /// ### |
| /// * This depends on P3INSOPRF |
| /// ### |
| /// %unsigned 5 wp |
| /// %unsigned 9 rsvd0 |
| /// %unsigned 5 rpu |
| /// %unsigned 5 rpv |
| /// %unsigned 1 ID_DMAOP |
| /// : INSDMA 0x0 |
| /// : INSOP 0x1 |
| /// %unsigned 1 wCtl |
| /// %unsigned 1 wID |
| /// : RF 0x0 |
| /// : DMEM 0x1 |
| /// %unsigned 1 rsvd1 |
| /// %% 2 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 9 op |
| /// %unsigned 4 rfp |
| /// %% 19 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 43b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FIR |
| #define h_P3FIR (){} |
| |
| #define BA_P3FIR_valid 0x0000 |
| #define B16P3FIR_valid 0x0000 |
| #define LSb32P3FIR_valid 0 |
| #define LSb16P3FIR_valid 0 |
| #define bP3FIR_valid 1 |
| #define MSK32P3FIR_valid 0x00000001 |
| #define P3FIR_valid_BUBL 0x0 |
| #define P3FIR_valid_VALID 0x1 |
| |
| #define BA_P3FIR_id 0x0000 |
| #define B16P3FIR_id 0x0000 |
| #define LSb32P3FIR_id 1 |
| #define LSb16P3FIR_id 1 |
| #define bP3FIR_id 1 |
| #define MSK32P3FIR_id 0x00000002 |
| #define P3FIR_id_EXE 0x0 |
| #define P3FIR_id_OP 0x1 |
| |
| #define BA_P3FIR_wp 0x0000 |
| #define B16P3FIR_wp 0x0000 |
| #define LSb32P3FIR_wp 2 |
| #define LSb16P3FIR_wp 2 |
| #define bP3FIR_wp 5 |
| #define MSK32P3FIR_wp 0x0000007C |
| |
| #define BA_P3FIR_rsvd0 0x0000 |
| #define B16P3FIR_rsvd0 0x0000 |
| #define LSb32P3FIR_rsvd0 7 |
| #define LSb16P3FIR_rsvd0 7 |
| #define bP3FIR_rsvd0 9 |
| #define MSK32P3FIR_rsvd0 0x0000FF80 |
| |
| #define BA_P3FIR_rpu 0x0002 |
| #define B16P3FIR_rpu 0x0002 |
| #define LSb32P3FIR_rpu 16 |
| #define LSb16P3FIR_rpu 0 |
| #define bP3FIR_rpu 5 |
| #define MSK32P3FIR_rpu 0x001F0000 |
| |
| #define BA_P3FIR_rpv 0x0002 |
| #define B16P3FIR_rpv 0x0002 |
| #define LSb32P3FIR_rpv 21 |
| #define LSb16P3FIR_rpv 5 |
| #define bP3FIR_rpv 5 |
| #define MSK32P3FIR_rpv 0x03E00000 |
| |
| #define BA_P3FIR_ID_DMAOP 0x0003 |
| #define B16P3FIR_ID_DMAOP 0x0002 |
| #define LSb32P3FIR_ID_DMAOP 26 |
| #define LSb16P3FIR_ID_DMAOP 10 |
| #define bP3FIR_ID_DMAOP 1 |
| #define MSK32P3FIR_ID_DMAOP 0x04000000 |
| #define P3FIR_ID_DMAOP_INSDMA 0x0 |
| #define P3FIR_ID_DMAOP_INSOP 0x1 |
| |
| #define BA_P3FIR_wCtl 0x0003 |
| #define B16P3FIR_wCtl 0x0002 |
| #define LSb32P3FIR_wCtl 27 |
| #define LSb16P3FIR_wCtl 11 |
| #define bP3FIR_wCtl 1 |
| #define MSK32P3FIR_wCtl 0x08000000 |
| |
| #define BA_P3FIR_wID 0x0003 |
| #define B16P3FIR_wID 0x0002 |
| #define LSb32P3FIR_wID 28 |
| #define LSb16P3FIR_wID 12 |
| #define bP3FIR_wID 1 |
| #define MSK32P3FIR_wID 0x10000000 |
| #define P3FIR_wID_RF 0x0 |
| #define P3FIR_wID_DMEM 0x1 |
| |
| #define BA_P3FIR_rsvd1 0x0003 |
| #define B16P3FIR_rsvd1 0x0002 |
| #define LSb32P3FIR_rsvd1 29 |
| #define LSb16P3FIR_rsvd1 13 |
| #define bP3FIR_rsvd1 1 |
| #define MSK32P3FIR_rsvd1 0x20000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3FIR_op 0x0004 |
| #define B16P3FIR_op 0x0004 |
| #define LSb32P3FIR_op 0 |
| #define LSb16P3FIR_op 0 |
| #define bP3FIR_op 9 |
| #define MSK32P3FIR_op 0x000001FF |
| |
| #define BA_P3FIR_rfp 0x0005 |
| #define B16P3FIR_rfp 0x0004 |
| #define LSb32P3FIR_rfp 9 |
| #define LSb16P3FIR_rfp 9 |
| #define bP3FIR_rfp 4 |
| #define MSK32P3FIR_rfp 0x00001E00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FIR { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FIR_valid(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3FIR_valid(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3FIR_valid(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3FIR_valid(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3FIR_id(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3FIR_id(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3FIR_id(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3FIR_id(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3FIR_wp(r32) _BFGET_(r32, 6, 2) |
| #define SET32P3FIR_wp(r32,v) _BFSET_(r32, 6, 2,v) |
| #define GET16P3FIR_wp(r16) _BFGET_(r16, 6, 2) |
| #define SET16P3FIR_wp(r16,v) _BFSET_(r16, 6, 2,v) |
| |
| #define GET32P3FIR_rsvd0(r32) _BFGET_(r32,15, 7) |
| #define SET32P3FIR_rsvd0(r32,v) _BFSET_(r32,15, 7,v) |
| #define GET16P3FIR_rsvd0(r16) _BFGET_(r16,15, 7) |
| #define SET16P3FIR_rsvd0(r16,v) _BFSET_(r16,15, 7,v) |
| |
| #define GET32P3FIR_rpu(r32) _BFGET_(r32,20,16) |
| #define SET32P3FIR_rpu(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16P3FIR_rpu(r16) _BFGET_(r16, 4, 0) |
| #define SET16P3FIR_rpu(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32P3FIR_rpv(r32) _BFGET_(r32,25,21) |
| #define SET32P3FIR_rpv(r32,v) _BFSET_(r32,25,21,v) |
| #define GET16P3FIR_rpv(r16) _BFGET_(r16, 9, 5) |
| #define SET16P3FIR_rpv(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32P3FIR_ID_DMAOP(r32) _BFGET_(r32,26,26) |
| #define SET32P3FIR_ID_DMAOP(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16P3FIR_ID_DMAOP(r16) _BFGET_(r16,10,10) |
| #define SET16P3FIR_ID_DMAOP(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32P3FIR_wCtl(r32) _BFGET_(r32,27,27) |
| #define SET32P3FIR_wCtl(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16P3FIR_wCtl(r16) _BFGET_(r16,11,11) |
| #define SET16P3FIR_wCtl(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32P3FIR_wID(r32) _BFGET_(r32,28,28) |
| #define SET32P3FIR_wID(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16P3FIR_wID(r16) _BFGET_(r16,12,12) |
| #define SET16P3FIR_wID(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32P3FIR_rsvd1(r32) _BFGET_(r32,29,29) |
| #define SET32P3FIR_rsvd1(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16P3FIR_rsvd1(r16) _BFGET_(r16,13,13) |
| #define SET16P3FIR_rsvd1(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_valid : 1; |
| UNSG32 u_id : 1; |
| UNSG32 u_wp : 5; |
| UNSG32 u_rsvd0 : 9; |
| UNSG32 u_rpu : 5; |
| UNSG32 u_rpv : 5; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 u_wCtl : 1; |
| UNSG32 u_wID : 1; |
| UNSG32 u_rsvd1 : 1; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FIR_op(r32) _BFGET_(r32, 8, 0) |
| #define SET32P3FIR_op(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16P3FIR_op(r16) _BFGET_(r16, 8, 0) |
| #define SET16P3FIR_op(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32P3FIR_rfp(r32) _BFGET_(r32,12, 9) |
| #define SET32P3FIR_rfp(r32,v) _BFSET_(r32,12, 9,v) |
| #define GET16P3FIR_rfp(r16) _BFGET_(r16,12, 9) |
| #define SET16P3FIR_rfp(r16,v) _BFSET_(r16,12, 9,v) |
| |
| UNSG32 u_op : 9; |
| UNSG32 u_rfp : 4; |
| UNSG32 RSVDx4_b13 : 19; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FIR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FIR_drvrd(SIE_P3FIR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FIR_drvwr(SIE_P3FIR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FIR_reset(SIE_P3FIR *p); |
| SIGN32 P3FIR_cmp (SIE_P3FIR *p, SIE_P3FIR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FIR_check(p,pie,pfx,hLOG) P3FIR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FIR_print(p, pfx,hLOG) P3FIR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FIR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3FID biu (4,4) |
| /// ### |
| /// * Pcube flattened instruction OP DMEM , depends on P3INSOPDMEM |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 valid |
| /// : BUBL 0x0 |
| /// : VALID 0x1 |
| /// %unsigned 1 id |
| /// : EXE 0x0 |
| /// : OP 0x1 |
| /// ### |
| /// * This depends on P3INSOPDMEM |
| /// ### |
| /// %unsigned 12 wPtr |
| /// ### |
| /// * 32-bit word address |
| /// ### |
| /// %unsigned 2 wr |
| /// %unsigned 5 rpu |
| /// %unsigned 5 rpv |
| /// %unsigned 1 ID_DMAOP |
| /// : INSDMA 0x0 |
| /// : INSOP 0x1 |
| /// %unsigned 1 wCtl |
| /// %unsigned 1 wID |
| /// : RF 0x0 |
| /// : DMEM 0x1 |
| /// %unsigned 1 rsvd1 |
| /// %% 2 # Stuffing bits... |
| /// @ 0x00004 (P) |
| /// %unsigned 9 op |
| /// %unsigned 4 rfp |
| /// %% 19 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 43b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3FID |
| #define h_P3FID (){} |
| |
| #define BA_P3FID_valid 0x0000 |
| #define B16P3FID_valid 0x0000 |
| #define LSb32P3FID_valid 0 |
| #define LSb16P3FID_valid 0 |
| #define bP3FID_valid 1 |
| #define MSK32P3FID_valid 0x00000001 |
| #define P3FID_valid_BUBL 0x0 |
| #define P3FID_valid_VALID 0x1 |
| |
| #define BA_P3FID_id 0x0000 |
| #define B16P3FID_id 0x0000 |
| #define LSb32P3FID_id 1 |
| #define LSb16P3FID_id 1 |
| #define bP3FID_id 1 |
| #define MSK32P3FID_id 0x00000002 |
| #define P3FID_id_EXE 0x0 |
| #define P3FID_id_OP 0x1 |
| |
| #define BA_P3FID_wPtr 0x0000 |
| #define B16P3FID_wPtr 0x0000 |
| #define LSb32P3FID_wPtr 2 |
| #define LSb16P3FID_wPtr 2 |
| #define bP3FID_wPtr 12 |
| #define MSK32P3FID_wPtr 0x00003FFC |
| |
| #define BA_P3FID_wr 0x0001 |
| #define B16P3FID_wr 0x0000 |
| #define LSb32P3FID_wr 14 |
| #define LSb16P3FID_wr 14 |
| #define bP3FID_wr 2 |
| #define MSK32P3FID_wr 0x0000C000 |
| |
| #define BA_P3FID_rpu 0x0002 |
| #define B16P3FID_rpu 0x0002 |
| #define LSb32P3FID_rpu 16 |
| #define LSb16P3FID_rpu 0 |
| #define bP3FID_rpu 5 |
| #define MSK32P3FID_rpu 0x001F0000 |
| |
| #define BA_P3FID_rpv 0x0002 |
| #define B16P3FID_rpv 0x0002 |
| #define LSb32P3FID_rpv 21 |
| #define LSb16P3FID_rpv 5 |
| #define bP3FID_rpv 5 |
| #define MSK32P3FID_rpv 0x03E00000 |
| |
| #define BA_P3FID_ID_DMAOP 0x0003 |
| #define B16P3FID_ID_DMAOP 0x0002 |
| #define LSb32P3FID_ID_DMAOP 26 |
| #define LSb16P3FID_ID_DMAOP 10 |
| #define bP3FID_ID_DMAOP 1 |
| #define MSK32P3FID_ID_DMAOP 0x04000000 |
| #define P3FID_ID_DMAOP_INSDMA 0x0 |
| #define P3FID_ID_DMAOP_INSOP 0x1 |
| |
| #define BA_P3FID_wCtl 0x0003 |
| #define B16P3FID_wCtl 0x0002 |
| #define LSb32P3FID_wCtl 27 |
| #define LSb16P3FID_wCtl 11 |
| #define bP3FID_wCtl 1 |
| #define MSK32P3FID_wCtl 0x08000000 |
| |
| #define BA_P3FID_wID 0x0003 |
| #define B16P3FID_wID 0x0002 |
| #define LSb32P3FID_wID 28 |
| #define LSb16P3FID_wID 12 |
| #define bP3FID_wID 1 |
| #define MSK32P3FID_wID 0x10000000 |
| #define P3FID_wID_RF 0x0 |
| #define P3FID_wID_DMEM 0x1 |
| |
| #define BA_P3FID_rsvd1 0x0003 |
| #define B16P3FID_rsvd1 0x0002 |
| #define LSb32P3FID_rsvd1 29 |
| #define LSb16P3FID_rsvd1 13 |
| #define bP3FID_rsvd1 1 |
| #define MSK32P3FID_rsvd1 0x20000000 |
| /////////////////////////////////////////////////////////// |
| |
| #define BA_P3FID_op 0x0004 |
| #define B16P3FID_op 0x0004 |
| #define LSb32P3FID_op 0 |
| #define LSb16P3FID_op 0 |
| #define bP3FID_op 9 |
| #define MSK32P3FID_op 0x000001FF |
| |
| #define BA_P3FID_rfp 0x0005 |
| #define B16P3FID_rfp 0x0004 |
| #define LSb32P3FID_rfp 9 |
| #define LSb16P3FID_rfp 9 |
| #define bP3FID_rfp 4 |
| #define MSK32P3FID_rfp 0x00001E00 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3FID { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FID_valid(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3FID_valid(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3FID_valid(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3FID_valid(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3FID_id(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3FID_id(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3FID_id(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3FID_id(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3FID_wPtr(r32) _BFGET_(r32,13, 2) |
| #define SET32P3FID_wPtr(r32,v) _BFSET_(r32,13, 2,v) |
| #define GET16P3FID_wPtr(r16) _BFGET_(r16,13, 2) |
| #define SET16P3FID_wPtr(r16,v) _BFSET_(r16,13, 2,v) |
| |
| #define GET32P3FID_wr(r32) _BFGET_(r32,15,14) |
| #define SET32P3FID_wr(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16P3FID_wr(r16) _BFGET_(r16,15,14) |
| #define SET16P3FID_wr(r16,v) _BFSET_(r16,15,14,v) |
| |
| #define GET32P3FID_rpu(r32) _BFGET_(r32,20,16) |
| #define SET32P3FID_rpu(r32,v) _BFSET_(r32,20,16,v) |
| #define GET16P3FID_rpu(r16) _BFGET_(r16, 4, 0) |
| #define SET16P3FID_rpu(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32P3FID_rpv(r32) _BFGET_(r32,25,21) |
| #define SET32P3FID_rpv(r32,v) _BFSET_(r32,25,21,v) |
| #define GET16P3FID_rpv(r16) _BFGET_(r16, 9, 5) |
| #define SET16P3FID_rpv(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32P3FID_ID_DMAOP(r32) _BFGET_(r32,26,26) |
| #define SET32P3FID_ID_DMAOP(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16P3FID_ID_DMAOP(r16) _BFGET_(r16,10,10) |
| #define SET16P3FID_ID_DMAOP(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32P3FID_wCtl(r32) _BFGET_(r32,27,27) |
| #define SET32P3FID_wCtl(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16P3FID_wCtl(r16) _BFGET_(r16,11,11) |
| #define SET16P3FID_wCtl(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32P3FID_wID(r32) _BFGET_(r32,28,28) |
| #define SET32P3FID_wID(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16P3FID_wID(r16) _BFGET_(r16,12,12) |
| #define SET16P3FID_wID(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32P3FID_rsvd1(r32) _BFGET_(r32,29,29) |
| #define SET32P3FID_rsvd1(r32,v) _BFSET_(r32,29,29,v) |
| #define GET16P3FID_rsvd1(r16) _BFGET_(r16,13,13) |
| #define SET16P3FID_rsvd1(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_valid : 1; |
| UNSG32 u_id : 1; |
| UNSG32 u_wPtr : 12; |
| UNSG32 u_wr : 2; |
| UNSG32 u_rpu : 5; |
| UNSG32 u_rpv : 5; |
| UNSG32 u_ID_DMAOP : 1; |
| UNSG32 u_wCtl : 1; |
| UNSG32 u_wID : 1; |
| UNSG32 u_rsvd1 : 1; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3FID_op(r32) _BFGET_(r32, 8, 0) |
| #define SET32P3FID_op(r32,v) _BFSET_(r32, 8, 0,v) |
| #define GET16P3FID_op(r16) _BFGET_(r16, 8, 0) |
| #define SET16P3FID_op(r16,v) _BFSET_(r16, 8, 0,v) |
| |
| #define GET32P3FID_rfp(r32) _BFGET_(r32,12, 9) |
| #define SET32P3FID_rfp(r32,v) _BFSET_(r32,12, 9,v) |
| #define GET16P3FID_rfp(r16) _BFGET_(r16,12, 9) |
| #define SET16P3FID_rfp(r16,v) _BFSET_(r16,12, 9,v) |
| |
| UNSG32 u_op : 9; |
| UNSG32 u_rfp : 4; |
| UNSG32 RSVDx4_b13 : 19; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3FID; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3FID_drvrd(SIE_P3FID *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3FID_drvwr(SIE_P3FID *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3FID_reset(SIE_P3FID *p); |
| SIGN32 P3FID_cmp (SIE_P3FID *p, SIE_P3FID *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3FID_check(p,pie,pfx,hLOG) P3FID_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3FID_print(p, pfx,hLOG) P3FID_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3FID |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ticOp biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 SIMD |
| /// : x4 0x0 |
| /// : x8 0x1 |
| /// ### |
| /// * SIMD pipeline mode |
| /// ### |
| /// %unsigned 5 in |
| /// ### |
| /// * RF write address for DMEM input |
| /// ### |
| /// %unsigned 5 rp_0i |
| /// %unsigned 5 rp_1i |
| /// ### |
| /// * RF read address of u/v-pipe (related via rtp in instruction) |
| /// * if PINSOP instruction is used, |
| /// * value of rp[0] will be replaced P3INSOPx.rpu |
| /// * value of rp[1] will be replaced P3INSOPx rpv |
| /// ### |
| /// %unsigned 2 mLatch_0i |
| /// %unsigned 2 mLatch_1i |
| /// : disable 0x0 |
| /// : m2rm 0x1 |
| /// : m2em 0x2 |
| /// : m2both 0x3 |
| /// ### |
| /// * Lacth control for multiplication stage of u-pipe. v-pipe is the same as u-pipe |
| /// ### |
| /// %unsigned 4 mCtl_0i |
| /// %unsigned 4 mCtl_1i |
| /// ### |
| /// * SIMDx4: multiplication coefficient for u/v-pipe |
| /// * SIMDx8: input shuffling (specified in mCtl[0]) |
| /// * Elementary modes: N, P, D, Q, X, R |
| /// * Combinations: (N/P/X/Q) – (N/P/D/R) |
| /// * Op-code: 00 (high & low) |
| /// * Op-name: N (no-op) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> 4 5 6 7 |
| /// * A B C D -> A B C D |
| /// * E F G H E F G H |
| /// * Op-code: 01 (high & low) |
| /// * Op-name: P (single-pix muxing): |
| /// * 0 1 2 3 0 A 1 B |
| /// * 4 5 6 7 -> 2 C 3 D |
| /// * A B C D -> 4 E 5 F |
| /// * E F G H 6 G 7 H |
| /// * Op-code: 10 (low) |
| /// * Op-name: D (double-pix muxing) |
| /// * 0 1 2 3 0 1 A B |
| /// * 4 5 6 7 -> 2 3 C D |
| /// * A B C D -> 4 5 E F |
| /// * E F G H 6 7 G H |
| /// * Op-code: 11 (high) |
| /// * Op-name: Q (quad-pix muxing) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> A B C D |
| /// * A B C D -> 4 5 6 7 |
| /// * E F G H E F G H |
| /// * Op-code: 10 (high) |
| /// * Op-name: X (quad-pix exchange): |
| /// * 0 1 2 3 4 5 6 7 |
| /// * 4 5 6 7 -> 0 1 2 3 |
| /// * A B C D -> E F G H |
| /// * E F G H A B C D |
| /// * Op-code: 11 (low) |
| /// * Op-name: R (pix repeating & packing) |
| /// * 0 1 2 3 0 0 A A |
| /// * 4 5 6 7 -> 1 1 B B |
| /// * A B C D -> 2 2 C C |
| /// * E F G H 3 3 D D |
| /// ### |
| /// : bypass 0x0 |
| /// : NN 0x0 |
| /// ### |
| /// * 00-00 (NN): bypass |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> 4 5 6 7 |
| /// * A B C D -> A B C D |
| /// * E F G H E F G H |
| /// ### |
| /// : SPixPac 0xD |
| /// : QP 0xD |
| /// ### |
| /// * 11-01 (QP): single-pix inline packing |
| /// * 0 1 2 3 0 4 1 5 |
| /// * 4 5 6 7 -> 2 6 3 7 |
| /// * A B C D -> A E B F |
| /// * E F G H C G D H |
| /// ### |
| /// : DPixPac 0xE |
| /// : QD 0xE |
| /// ### |
| /// * 11-10 (QD): double-pix inline packing |
| /// * 0 1 2 3 0 1 4 5 |
| /// * 4 5 6 7 -> 2 3 6 7 |
| /// * A B C D -> A B E F |
| /// * E F G H C D G H |
| /// ### |
| /// : SPixMux 0x1 |
| /// : NP 0x1 |
| /// : PN 0x4 |
| /// ### |
| /// * 00-01 (NP): |
| /// * 01-00 (PN): single-pix cross muxing |
| /// * 0 1 2 3 0 A 1 B |
| /// * 4 5 6 7 -> 2 C 3 D |
| /// * A B C D -> 4 E 5 F |
| /// * E F G H 6 G 7 H |
| /// ### |
| /// : DPixMux 0x2 |
| /// : ND 0x2 |
| /// ### |
| /// * 00-10 (ND): double-pix cross muxing |
| /// * 0 1 2 3 0 1 A B |
| /// * 4 5 6 7 -> 2 3 C D |
| /// * A B C D -> 4 5 E F |
| /// * E F G H 6 7 G H |
| /// ### |
| /// : QPixMux 0xC |
| /// : QN 0xC |
| /// ### |
| /// * 11-00 (QN): quad-pix muxing (frame2field) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> A B C D |
| /// * A B C D -> 4 5 6 7 |
| /// * E F G H E F G H |
| /// ### |
| /// : XQPix 0x8 |
| /// : XN 0x8 |
| /// ### |
| /// * 10-00 (XN): quad-pix exchange |
| /// * 0 1 2 3 4 5 6 7 |
| /// * 4 5 6 7 -> 0 1 2 3 |
| /// * A B C D -> E F G H |
| /// * E F G H A B C D |
| /// ### |
| /// : DuMuxL 0x3 |
| /// : NR 0x3 |
| /// ### |
| /// * 00-11 (NR): repeat & mux low |
| /// * 0 1 2 3 0 0 A A |
| /// * 4 5 6 7 -> 1 1 B B |
| /// * A B C D -> 2 2 C C |
| /// * E F G H 3 3 D D |
| /// ### |
| /// : DuMuxH 0xB |
| /// : XR 0xB |
| /// ### |
| /// * 10-11 (XR): repeat & mux high |
| /// * 0 1 2 3 4 4 E E |
| /// * 4 5 6 7 -> 5 5 F F |
| /// * A B C D -> 6 6 G G |
| /// * E F G H 7 7 H H |
| /// ### |
| /// : 4x4T 0x5 |
| /// : PP 0x5 |
| /// ### |
| /// * 01-01 (PP): 4x4 transpose |
| /// * 0 1 2 3 0 4 A E |
| /// * 4 5 6 7 -> 1 5 B F |
| /// * A B C D -> 2 6 C G |
| /// * E F G H 3 7 D H |
| /// ### |
| /// : Qmux4x4T 0x6 |
| /// : PD 0x6 |
| /// ### |
| /// * 01-10 (PD): 4x4 transpose after quad-muxing |
| /// * 0 1 2 3 0 A 4 E |
| /// * 4 5 6 7 -> 1 B 5 F |
| /// * A B C D -> 2 C 6 G |
| /// * E F G H 3 D 7 H |
| /// ### |
| /// : PR 0x7 |
| /// : XP 0x9 |
| /// : XD 0xA |
| /// : QR 0xF |
| /// ### |
| /// * Reserved |
| /// * SIMDx8: de-blocking extension (specified in mCtl[1]) |
| /// * bypass |
| /// * 0 |
| /// ### |
| /// : L0 0x8 |
| /// : L1 0x9 |
| /// : L2 0xA |
| /// : L3 0xB |
| /// ### |
| /// * SIMDx8: load fop[15:0] (BS/tc0 or PQUANT) from x4.rv |
| /// * L0: fop[15:0] = rv[15:0] |
| /// * L1: fop[15:0] = rv[35:20] |
| /// * L2: fop[15:0] = rv[55:40] |
| /// * L3: fop[15:0] = rv[75:60] |
| /// ### |
| /// : H0 0xC |
| /// : H1 0xD |
| /// : H2 0xE |
| /// : H3 0xF |
| /// ### |
| /// * SIMDx8: load fop[28:16] (alpha/beta) from x4.rv |
| /// * H0: fop[28:16] = rv[12:0] |
| /// * H1: fop[28:16] = rv[32:20] |
| /// * H2: fop[28:16] = rv[52:40] |
| /// * H3: fop[28:16] = rv[72:60] |
| /// ### |
| /// : xmul_rv_0 0x0 |
| /// : xmul_rv_1 0x1 |
| /// : xmul_rv_2 0x2 |
| /// : xmul_rv_3 0x3 |
| /// : xmul_rv_dot 0x4 |
| /// ### |
| /// * SIMDx4: rv selection for xmul operations (specified in mCtl[0]) |
| /// * xmul_rv_0 : rmu[i] = ru[i] * rv[0] |
| /// * xmul_rv_1 : rmu[i] = ru[i] * rv[1] |
| /// * xmul_rv_2 : rmu[i] = ru[i] * rv[2] |
| /// * xmul_rv_3 : rmu[i] = ru[i] * rv[3] |
| /// * xmul_rv_dot : rmu[i] = ru[i] * rv[i] |
| /// ### |
| /// %unsigned 2 sLatch_0i |
| /// %unsigned 2 sLatch_1i |
| /// : disable 0x0 |
| /// : s2rs 0x1 |
| /// : s2es 0x2 |
| /// : s2both 0x3 |
| /// ### |
| /// * Latch control for shifting stage of u/v-pipe |
| /// ### |
| /// %unsigned 1 modeShift |
| /// : bits 0x0 |
| /// : words 0x1 |
| /// ### |
| /// * Mode for shifting stage of both pipes |
| /// * bits mode is only supported in SIMD4 |
| /// * words mode are supported by both SIMD4 and SIMD8 |
| /// ### |
| /// %signed 4 sCtl_0i |
| /// %signed 4 sCtl_1i |
| /// ### |
| /// * Shift-bits: -8~7, for SIMDx4 only |
| /// ### |
| /// : bypass 0 |
| /// : Hwsh1 1 |
| /// : Hwsh2 2 |
| /// : Hwsh3 3 |
| /// : Hwsh4 4 |
| /// : Fwpad1 15 |
| /// : Fwpad2 14 |
| /// : Fwpad3 13 |
| /// ### |
| /// * Shift-words: half-word shift 0~4, full-word pad 1~3 |
| /// ### |
| /// %unsigned 3 sum_0i |
| /// %unsigned 3 sum_1i |
| /// : disable 0x0 |
| /// : abs 0x1 |
| /// : equ 0x2 |
| /// : eqv 0x3 |
| /// : add_add 0x4 |
| /// : add_sub 0x5 |
| /// : sub_add 0x6 |
| /// : sub_sub 0x7 |
| /// ### |
| /// * SIMDx4: sum stage control of basic/extra pipeline |
| /// * Usage: |
| /// * sum[0] ; sum[1] |
| /// * abs: | rsu[i]-rsv[i] | ; | esu[i]-esv[i] | |
| /// * equ: rsum[i]=rsu[i] ; esum[i]=esu[i] |
| /// * eqv: rsum[i]=rsv[i] ; esum[i]=esv[i] |
| /// * add_add: rsum[i]=+rsu[i]+rsv[i]; esum[i]=+esu[i]+esv[i] |
| /// * add_sub: rsum[i]=+rsu[i]-rsv[i] ; esum[i]=+esu[i]-esv[i] |
| /// * sub_add: rsum[i]=-rsu[i]+rsv[i] ; esum[i]=-esu[i]+esv[i] |
| /// * sub_sub: rsum[i]=-rsu[i]-rsv[i] ; esum[i]=-esu[i]-esv[i] |
| /// * disable |
| /// * 0 |
| /// * abs |
| /// * 1 |
| /// * 10b |
| /// * equ |
| /// * 2 |
| /// * eqv |
| /// * 3 |
| /// ### |
| /// : equm 0x4 |
| /// : eqvm 0x5 |
| /// : equmEx 0x6 |
| /// : eqvmEx 0x7 |
| /// : db 0x4 |
| /// : luma 0x6 |
| /// : chroma 0x7 |
| /// ### |
| /// * SIMDx8: sum stage control of basic/extra pipeline |
| /// * Usage: |
| /// * sum[0] only supports equ, eqv, equm(Ex), and eqvm(Ex) |
| /// * sum[1] only supports equ, eqv, db, luma, and chroma |
| /// * The following is the legal combination and behavior: |
| /// * (A) when sum[1] != db or luma or chroma |
| /// * sum[0] operations |
| /// * equ: rsum[i]=rsu[i] |
| /// * eqv: rsum[i]=rsv[i] |
| /// * equm(Ex): rsum[i]=rmu[i] |
| /// * eqvm(Ex): rsum[i]=rmv[i] |
| /// * CAUTION: when using equm/eqvm/equmEs/eqvmEx, the mLatch in the next opcode should set to “disable” to avoid mismatches between C-model and RTL.: Strongly suggest to use them in DBLK usage only. |
| /// * (B) when sum[1] = db (for H.264) |
| /// * rsum[i] kept as the one in previous opcode |
| /// * esum[i] has the value from DBLK output |
| /// * (C) when sum[1] = luma (for VC1) |
| /// * set filter selection as 0 |
| /// * rsum[i] and esum[i] kept as the ones in previous opcode |
| /// * (D) when sum[1] = chroma (for VC1) |
| /// * set filter selection as 1 |
| /// * rsum[i] and esum[i] kept as the ones in previous opcode |
| /// ### |
| /// %unsigned 2 accSel_0i |
| /// %unsigned 2 accSel_1i |
| /// : e2r 0x0 |
| /// : r2r 0x1 |
| /// : t2r 0x2 |
| /// : t2t 0x3 |
| /// ### |
| /// * I/O select for accumulation stage of basic pipeline |
| /// ### |
| /// : r2e 0x0 |
| /// : e2e 0x1 |
| /// : t2e 0x2 |
| /// ### |
| /// * t2t |
| /// * 3 |
| /// * t=tacc+esum |
| /// * I/O select for accumulation stage of extra pipeline |
| /// ### |
| /// %unsigned 3 acc_0i |
| /// %unsigned 3 acc_1i |
| /// : disable 0x0 |
| /// ### |
| /// * pack |
| /// * 1 |
| /// ### |
| /// : eqsum 0x3 |
| /// : add_add 0x4 |
| /// : xor 0x5 |
| /// : or 0x6 |
| /// : and 0x7 |
| /// ### |
| /// * SIMDx4: accumulation control of basic/extra pipeline |
| /// * disable |
| /// * 0 |
| /// * pack |
| /// * 1 |
| /// * unpack |
| /// * 2 |
| /// * eqsum |
| /// * 3 |
| /// * add_add |
| /// * 4 |
| /// * xor |
| /// * 5 |
| /// * or |
| /// * 6 |
| /// * and |
| /// * 7 |
| /// * SIMDx8: accumulation control of basic/extra pipeline |
| /// ### |
| /// %unsigned 2 desIn |
| /// : disable 0x0 |
| /// : racc 0x1 |
| /// : tacc 0x2 |
| /// : eacc 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 0 |
| /// ### |
| /// : racc_AND_eacc 0x0 |
| /// : tacc_OR_eacc 0x1 |
| /// : racc_OR_eacc 0x2 |
| /// : racc_OR_tacc 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 1 and under SIMD4 mode |
| /// ### |
| /// %unsigned 4 des |
| /// ### |
| /// * SIMDx4: de-scaling bits 0~14 |
| /// ### |
| /// : bypass 0x0 |
| /// : frm2fld 0xF |
| /// ### |
| /// * SIMDx8: |
| /// * frm2fld (0xF): output shuffling |
| /// * (0b0001~0b0110): unsigned right shift bits 1~6 for descaling |
| /// * (0b1001~0b1110): signed right shift bits 1~6 for descaling |
| /// ### |
| /// %unsigned 1 clip |
| /// ### |
| /// * 0/1 to disable/enable clipping output (16-bit clip for SIMD4 10-bit clip for SIMD8) |
| /// ### |
| /// %unsigned 5 wp |
| /// ### |
| /// * RF write address |
| /// * if P3INSOPWRF instruction is used, |
| /// * value of wp will be replaced P3INSOPWRF.wp |
| /// ### |
| /// %unsigned 3 wCtl |
| /// : disable 0x0 |
| /// : RF 0x1 |
| /// : dmem 0x2 |
| /// : both 0x3 |
| /// : min 0x4 |
| /// : max 0x5 |
| /// ### |
| /// * RF/DMEM & special registers write-back control |
| /// ### |
| /// %unsigned 1 xmul |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * rmu[i] = ru[i] * rv[s][3:0]; |
| /// * rmv[i] = ru[i] * rv[s][8:4]; / using signed multiplication |
| /// * value of s comes from mCtl[0]. |
| /// * The main usage for xmul is to calculate signed 20bits (store d in ru) multiplied by one singed 9b (in rv) . |
| /// ### |
| /// %unsigned 1 xshift |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * (1) su [i]=(signed20b)( rmu[i]<< (signed 4b)rmv[i] ) |
| /// * modeShift[0] and sCtl[0] are ignored |
| /// * (2) sv is controlled via the baseline opcode control bit , namely, modeShift[1] and sCtl[1] |
| /// * sLatch[0] and sLatch[1] still function. |
| /// * When xshift is set to 1 in SIMD8 mode, the function of xshift will be disable. |
| /// * Stage: shift |
| /// ### |
| /// %unsigned 3 xcmp |
| /// : na 0x0 |
| /// ### |
| /// * Use default ops |
| /// ### |
| /// : carry 0x1 |
| /// ### |
| /// * Output carry bit(s) instead of sum result rsum ; will be ignored in SIMD8 mode |
| /// * Carry bit(s) are generated according to sum[0] control bit |
| /// * add_add: rsum[i] = (rsu[i]+rsv[i])[20] ? 1 : 0 |
| /// * add_sub: rsum[i] = (rsu[i]-rsv[i])[20] ? 0 : -1 |
| /// * sub_add: rsum[i] = (-rsu[i]+rsv[i])[20] ? 0 : -1 |
| /// * sub_sub: rsum[i] = (-rsu[i]-rsv[i])[20] ? -1 : -2 |
| /// * Caution: when loading 16 bit data into pipeline, be sure to left shift 4 bits so as to generate carry bit. |
| /// ### |
| /// : EQ 0x2 |
| /// : EQj 0x3 |
| /// : G 0x4 |
| /// : Gj 0x5 |
| /// : L 0x6 |
| /// : Lj 0x7 |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * rsum[i] = (signed 20b)rsu[i] <cmp> (signed 20b)rsv[i] ? 20'hFFFFF : 20'h0 |
| /// * esum[i] = (signed 20b)rsu[i] <cmp> (signed 20b)rsv[i] ? 20'h0 : 20'hFFFFF |
| /// * Main operation is to replace sum[0] and sum[1]. |
| /// * Stage: sum |
| /// ### |
| /// %unsigned 1 xdesInSelMode |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * (1) when xdesInSelMode == 0: |
| /// * desIn selects one acc register and perform descaling or frm2fld on the selected register based on des value. |
| /// * (2) when xdesInSelMode == 1 : |
| /// * (2.a) desIn = 1 ~ 3 selects acc register pair denoted as xacc and yacc; then perform logic operation OR. |
| /// * rout[i] = xacc[i] OR yacc[i]. |
| /// * (2.b) desIn =0 ; acc register pair is selected by default and perform logic operation AND |
| /// * rout[i] = racc[i] AND eacc[i]. |
| /// ### |
| /// %% 18 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 12B, bits: 78b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ticOp |
| #define h_ticOp (){} |
| |
| #define BA_ticOp_SIMD 0x0000 |
| #define B16ticOp_SIMD 0x0000 |
| #define LSb32ticOp_SIMD 0 |
| #define LSb16ticOp_SIMD 0 |
| #define bticOp_SIMD 1 |
| #define MSK32ticOp_SIMD 0x00000001 |
| #define ticOp_SIMD_x4 0x0 |
| #define ticOp_SIMD_x8 0x1 |
| |
| #define BA_ticOp_in 0x0000 |
| #define B16ticOp_in 0x0000 |
| #define LSb32ticOp_in 1 |
| #define LSb16ticOp_in 1 |
| #define bticOp_in 5 |
| #define MSK32ticOp_in 0x0000003E |
| |
| #define BA_ticOp_rp_0i 0x0000 |
| #define B16ticOp_rp_0i 0x0000 |
| #define LSb32ticOp_rp_0i 6 |
| #define LSb16ticOp_rp_0i 6 |
| #define bticOp_rp_0i 5 |
| #define MSK32ticOp_rp_0i 0x000007C0 |
| |
| #define BA_ticOp_rp_1i 0x0001 |
| #define B16ticOp_rp_1i 0x0000 |
| #define LSb32ticOp_rp_1i 11 |
| #define LSb16ticOp_rp_1i 11 |
| #define bticOp_rp_1i 5 |
| #define MSK32ticOp_rp_1i 0x0000F800 |
| |
| #define BA_ticOp_mLatch_0i 0x0002 |
| #define B16ticOp_mLatch_0i 0x0002 |
| #define LSb32ticOp_mLatch_0i 16 |
| #define LSb16ticOp_mLatch_0i 0 |
| #define bticOp_mLatch_0i 2 |
| #define MSK32ticOp_mLatch_0i 0x00030000 |
| |
| #define BA_ticOp_mLatch_1i 0x0002 |
| #define B16ticOp_mLatch_1i 0x0002 |
| #define LSb32ticOp_mLatch_1i 18 |
| #define LSb16ticOp_mLatch_1i 2 |
| #define bticOp_mLatch_1i 2 |
| #define MSK32ticOp_mLatch_1i 0x000C0000 |
| #define ticOp_mLatch_disable 0x0 |
| #define ticOp_mLatch_m2rm 0x1 |
| #define ticOp_mLatch_m2em 0x2 |
| #define ticOp_mLatch_m2both 0x3 |
| |
| #define BA_ticOp_mCtl_0i 0x0002 |
| #define B16ticOp_mCtl_0i 0x0002 |
| #define LSb32ticOp_mCtl_0i 20 |
| #define LSb16ticOp_mCtl_0i 4 |
| #define bticOp_mCtl_0i 4 |
| #define MSK32ticOp_mCtl_0i 0x00F00000 |
| |
| #define BA_ticOp_mCtl_1i 0x0003 |
| #define B16ticOp_mCtl_1i 0x0002 |
| #define LSb32ticOp_mCtl_1i 24 |
| #define LSb16ticOp_mCtl_1i 8 |
| #define bticOp_mCtl_1i 4 |
| #define MSK32ticOp_mCtl_1i 0x0F000000 |
| #define ticOp_mCtl_bypass 0x0 |
| #define ticOp_mCtl_NN 0x0 |
| #define ticOp_mCtl_SPixPac 0xD |
| #define ticOp_mCtl_QP 0xD |
| #define ticOp_mCtl_DPixPac 0xE |
| #define ticOp_mCtl_QD 0xE |
| #define ticOp_mCtl_SPixMux 0x1 |
| #define ticOp_mCtl_NP 0x1 |
| #define ticOp_mCtl_PN 0x4 |
| #define ticOp_mCtl_DPixMux 0x2 |
| #define ticOp_mCtl_ND 0x2 |
| #define ticOp_mCtl_QPixMux 0xC |
| #define ticOp_mCtl_QN 0xC |
| #define ticOp_mCtl_XQPix 0x8 |
| #define ticOp_mCtl_XN 0x8 |
| #define ticOp_mCtl_DuMuxL 0x3 |
| #define ticOp_mCtl_NR 0x3 |
| #define ticOp_mCtl_DuMuxH 0xB |
| #define ticOp_mCtl_XR 0xB |
| #define ticOp_mCtl_4x4T 0x5 |
| #define ticOp_mCtl_PP 0x5 |
| #define ticOp_mCtl_Qmux4x4T 0x6 |
| #define ticOp_mCtl_PD 0x6 |
| #define ticOp_mCtl_PR 0x7 |
| #define ticOp_mCtl_XP 0x9 |
| #define ticOp_mCtl_XD 0xA |
| #define ticOp_mCtl_QR 0xF |
| #define ticOp_mCtl_L0 0x8 |
| #define ticOp_mCtl_L1 0x9 |
| #define ticOp_mCtl_L2 0xA |
| #define ticOp_mCtl_L3 0xB |
| #define ticOp_mCtl_H0 0xC |
| #define ticOp_mCtl_H1 0xD |
| #define ticOp_mCtl_H2 0xE |
| #define ticOp_mCtl_H3 0xF |
| #define ticOp_mCtl_xmul_rv_0 0x0 |
| #define ticOp_mCtl_xmul_rv_1 0x1 |
| #define ticOp_mCtl_xmul_rv_2 0x2 |
| #define ticOp_mCtl_xmul_rv_3 0x3 |
| #define ticOp_mCtl_xmul_rv_dot 0x4 |
| |
| #define BA_ticOp_sLatch_0i 0x0003 |
| #define B16ticOp_sLatch_0i 0x0002 |
| #define LSb32ticOp_sLatch_0i 28 |
| #define LSb16ticOp_sLatch_0i 12 |
| #define bticOp_sLatch_0i 2 |
| #define MSK32ticOp_sLatch_0i 0x30000000 |
| |
| #define BA_ticOp_sLatch_1i 0x0003 |
| #define B16ticOp_sLatch_1i 0x0002 |
| #define LSb32ticOp_sLatch_1i 30 |
| #define LSb16ticOp_sLatch_1i 14 |
| #define bticOp_sLatch_1i 2 |
| #define MSK32ticOp_sLatch_1i 0xC0000000 |
| #define ticOp_sLatch_disable 0x0 |
| #define ticOp_sLatch_s2rs 0x1 |
| #define ticOp_sLatch_s2es 0x2 |
| #define ticOp_sLatch_s2both 0x3 |
| |
| #define BA_ticOp_modeShift 0x0004 |
| #define B16ticOp_modeShift 0x0004 |
| #define LSb32ticOp_modeShift 0 |
| #define LSb16ticOp_modeShift 0 |
| #define bticOp_modeShift 1 |
| #define MSK32ticOp_modeShift 0x00000001 |
| #define ticOp_modeShift_bits 0x0 |
| #define ticOp_modeShift_words 0x1 |
| |
| #define BA_ticOp_sCtl_0i 0x0004 |
| #define B16ticOp_sCtl_0i 0x0004 |
| #define LSb32ticOp_sCtl_0i 1 |
| #define LSb16ticOp_sCtl_0i 1 |
| #define bticOp_sCtl_0i 4 |
| #define MSK32ticOp_sCtl_0i 0x0000001E |
| |
| #define BA_ticOp_sCtl_1i 0x0004 |
| #define B16ticOp_sCtl_1i 0x0004 |
| #define LSb32ticOp_sCtl_1i 5 |
| #define LSb16ticOp_sCtl_1i 5 |
| #define bticOp_sCtl_1i 4 |
| #define MSK32ticOp_sCtl_1i 0x000001E0 |
| #define ticOp_sCtl_bypass 0 |
| #define ticOp_sCtl_Hwsh1 1 |
| #define ticOp_sCtl_Hwsh2 2 |
| #define ticOp_sCtl_Hwsh3 3 |
| #define ticOp_sCtl_Hwsh4 4 |
| #define ticOp_sCtl_Fwpad1 15 |
| #define ticOp_sCtl_Fwpad2 14 |
| #define ticOp_sCtl_Fwpad3 13 |
| |
| #define BA_ticOp_sum_0i 0x0005 |
| #define B16ticOp_sum_0i 0x0004 |
| #define LSb32ticOp_sum_0i 9 |
| #define LSb16ticOp_sum_0i 9 |
| #define bticOp_sum_0i 3 |
| #define MSK32ticOp_sum_0i 0x00000E00 |
| |
| #define BA_ticOp_sum_1i 0x0005 |
| #define B16ticOp_sum_1i 0x0004 |
| #define LSb32ticOp_sum_1i 12 |
| #define LSb16ticOp_sum_1i 12 |
| #define bticOp_sum_1i 3 |
| #define MSK32ticOp_sum_1i 0x00007000 |
| #define ticOp_sum_disable 0x0 |
| #define ticOp_sum_abs 0x1 |
| #define ticOp_sum_equ 0x2 |
| #define ticOp_sum_eqv 0x3 |
| #define ticOp_sum_add_add 0x4 |
| #define ticOp_sum_add_sub 0x5 |
| #define ticOp_sum_sub_add 0x6 |
| #define ticOp_sum_sub_sub 0x7 |
| #define ticOp_sum_equm 0x4 |
| #define ticOp_sum_eqvm 0x5 |
| #define ticOp_sum_equmEx 0x6 |
| #define ticOp_sum_eqvmEx 0x7 |
| #define ticOp_sum_db 0x4 |
| #define ticOp_sum_luma 0x6 |
| #define ticOp_sum_chroma 0x7 |
| |
| #define BA_ticOp_accSel_0i 0x0005 |
| #define B16ticOp_accSel_0i 0x0004 |
| #define LSb32ticOp_accSel_0i 15 |
| #define LSb16ticOp_accSel_0i 15 |
| #define bticOp_accSel_0i 2 |
| #define MSK32ticOp_accSel_0i 0x00018000 |
| |
| #define BA_ticOp_accSel_1i 0x0006 |
| #define B16ticOp_accSel_1i 0x0006 |
| #define LSb32ticOp_accSel_1i 17 |
| #define LSb16ticOp_accSel_1i 1 |
| #define bticOp_accSel_1i 2 |
| #define MSK32ticOp_accSel_1i 0x00060000 |
| #define ticOp_accSel_e2r 0x0 |
| #define ticOp_accSel_r2r 0x1 |
| #define ticOp_accSel_t2r 0x2 |
| #define ticOp_accSel_t2t 0x3 |
| #define ticOp_accSel_r2e 0x0 |
| #define ticOp_accSel_e2e 0x1 |
| #define ticOp_accSel_t2e 0x2 |
| |
| #define BA_ticOp_acc_0i 0x0006 |
| #define B16ticOp_acc_0i 0x0006 |
| #define LSb32ticOp_acc_0i 19 |
| #define LSb16ticOp_acc_0i 3 |
| #define bticOp_acc_0i 3 |
| #define MSK32ticOp_acc_0i 0x00380000 |
| |
| #define BA_ticOp_acc_1i 0x0006 |
| #define B16ticOp_acc_1i 0x0006 |
| #define LSb32ticOp_acc_1i 22 |
| #define LSb16ticOp_acc_1i 6 |
| #define bticOp_acc_1i 3 |
| #define MSK32ticOp_acc_1i 0x01C00000 |
| #define ticOp_acc_disable 0x0 |
| #define ticOp_acc_eqsum 0x3 |
| #define ticOp_acc_add_add 0x4 |
| #define ticOp_acc_xor 0x5 |
| #define ticOp_acc_or 0x6 |
| #define ticOp_acc_and 0x7 |
| |
| #define BA_ticOp_desIn 0x0007 |
| #define B16ticOp_desIn 0x0006 |
| #define LSb32ticOp_desIn 25 |
| #define LSb16ticOp_desIn 9 |
| #define bticOp_desIn 2 |
| #define MSK32ticOp_desIn 0x06000000 |
| #define ticOp_desIn_disable 0x0 |
| #define ticOp_desIn_racc 0x1 |
| #define ticOp_desIn_tacc 0x2 |
| #define ticOp_desIn_eacc 0x3 |
| #define ticOp_desIn_racc_AND_eacc 0x0 |
| #define ticOp_desIn_tacc_OR_eacc 0x1 |
| #define ticOp_desIn_racc_OR_eacc 0x2 |
| #define ticOp_desIn_racc_OR_tacc 0x3 |
| |
| #define BA_ticOp_des 0x0007 |
| #define B16ticOp_des 0x0006 |
| #define LSb32ticOp_des 27 |
| #define LSb16ticOp_des 11 |
| #define bticOp_des 4 |
| #define MSK32ticOp_des 0x78000000 |
| #define ticOp_des_bypass 0x0 |
| #define ticOp_des_frm2fld 0xF |
| |
| #define BA_ticOp_clip 0x0007 |
| #define B16ticOp_clip 0x0006 |
| #define LSb32ticOp_clip 31 |
| #define LSb16ticOp_clip 15 |
| #define bticOp_clip 1 |
| #define MSK32ticOp_clip 0x80000000 |
| |
| #define BA_ticOp_wp 0x0008 |
| #define B16ticOp_wp 0x0008 |
| #define LSb32ticOp_wp 0 |
| #define LSb16ticOp_wp 0 |
| #define bticOp_wp 5 |
| #define MSK32ticOp_wp 0x0000001F |
| |
| #define BA_ticOp_wCtl 0x0008 |
| #define B16ticOp_wCtl 0x0008 |
| #define LSb32ticOp_wCtl 5 |
| #define LSb16ticOp_wCtl 5 |
| #define bticOp_wCtl 3 |
| #define MSK32ticOp_wCtl 0x000000E0 |
| #define ticOp_wCtl_disable 0x0 |
| #define ticOp_wCtl_RF 0x1 |
| #define ticOp_wCtl_dmem 0x2 |
| #define ticOp_wCtl_both 0x3 |
| #define ticOp_wCtl_min 0x4 |
| #define ticOp_wCtl_max 0x5 |
| |
| #define BA_ticOp_xmul 0x0009 |
| #define B16ticOp_xmul 0x0008 |
| #define LSb32ticOp_xmul 8 |
| #define LSb16ticOp_xmul 8 |
| #define bticOp_xmul 1 |
| #define MSK32ticOp_xmul 0x00000100 |
| |
| #define BA_ticOp_xshift 0x0009 |
| #define B16ticOp_xshift 0x0008 |
| #define LSb32ticOp_xshift 9 |
| #define LSb16ticOp_xshift 9 |
| #define bticOp_xshift 1 |
| #define MSK32ticOp_xshift 0x00000200 |
| |
| #define BA_ticOp_xcmp 0x0009 |
| #define B16ticOp_xcmp 0x0008 |
| #define LSb32ticOp_xcmp 10 |
| #define LSb16ticOp_xcmp 10 |
| #define bticOp_xcmp 3 |
| #define MSK32ticOp_xcmp 0x00001C00 |
| #define ticOp_xcmp_na 0x0 |
| #define ticOp_xcmp_carry 0x1 |
| #define ticOp_xcmp_EQ 0x2 |
| #define ticOp_xcmp_EQj 0x3 |
| #define ticOp_xcmp_G 0x4 |
| #define ticOp_xcmp_Gj 0x5 |
| #define ticOp_xcmp_L 0x6 |
| #define ticOp_xcmp_Lj 0x7 |
| |
| #define BA_ticOp_xdesInSelMode 0x0009 |
| #define B16ticOp_xdesInSelMode 0x0008 |
| #define LSb32ticOp_xdesInSelMode 13 |
| #define LSb16ticOp_xdesInSelMode 13 |
| #define bticOp_xdesInSelMode 1 |
| #define MSK32ticOp_xdesInSelMode 0x00002000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ticOp { |
| /////////////////////////////////////////////////////////// |
| #define GET32ticOp_SIMD(r32) _BFGET_(r32, 0, 0) |
| #define SET32ticOp_SIMD(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ticOp_SIMD(r16) _BFGET_(r16, 0, 0) |
| #define SET16ticOp_SIMD(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ticOp_in(r32) _BFGET_(r32, 5, 1) |
| #define SET32ticOp_in(r32,v) _BFSET_(r32, 5, 1,v) |
| #define GET16ticOp_in(r16) _BFGET_(r16, 5, 1) |
| #define SET16ticOp_in(r16,v) _BFSET_(r16, 5, 1,v) |
| |
| #define GET32ticOp_rp_0i(r32) _BFGET_(r32,10, 6) |
| #define SET32ticOp_rp_0i(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16ticOp_rp_0i(r16) _BFGET_(r16,10, 6) |
| #define SET16ticOp_rp_0i(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32ticOp_rp_1i(r32) _BFGET_(r32,15,11) |
| #define SET32ticOp_rp_1i(r32,v) _BFSET_(r32,15,11,v) |
| #define GET16ticOp_rp_1i(r16) _BFGET_(r16,15,11) |
| #define SET16ticOp_rp_1i(r16,v) _BFSET_(r16,15,11,v) |
| |
| #define GET32ticOp_mLatch_0i(r32) _BFGET_(r32,17,16) |
| #define SET32ticOp_mLatch_0i(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16ticOp_mLatch_0i(r16) _BFGET_(r16, 1, 0) |
| #define SET16ticOp_mLatch_0i(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32ticOp_mLatch_1i(r32) _BFGET_(r32,19,18) |
| #define SET32ticOp_mLatch_1i(r32,v) _BFSET_(r32,19,18,v) |
| #define GET16ticOp_mLatch_1i(r16) _BFGET_(r16, 3, 2) |
| #define SET16ticOp_mLatch_1i(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32ticOp_mCtl_0i(r32) _BFGET_(r32,23,20) |
| #define SET32ticOp_mCtl_0i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16ticOp_mCtl_0i(r16) _BFGET_(r16, 7, 4) |
| #define SET16ticOp_mCtl_0i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32ticOp_mCtl_1i(r32) _BFGET_(r32,27,24) |
| #define SET32ticOp_mCtl_1i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16ticOp_mCtl_1i(r16) _BFGET_(r16,11, 8) |
| #define SET16ticOp_mCtl_1i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32ticOp_sLatch_0i(r32) _BFGET_(r32,29,28) |
| #define SET32ticOp_sLatch_0i(r32,v) _BFSET_(r32,29,28,v) |
| #define GET16ticOp_sLatch_0i(r16) _BFGET_(r16,13,12) |
| #define SET16ticOp_sLatch_0i(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32ticOp_sLatch_1i(r32) _BFGET_(r32,31,30) |
| #define SET32ticOp_sLatch_1i(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16ticOp_sLatch_1i(r16) _BFGET_(r16,15,14) |
| #define SET16ticOp_sLatch_1i(r16,v) _BFSET_(r16,15,14,v) |
| |
| UNSG32 u_SIMD : 1; |
| UNSG32 u_in : 5; |
| UNSG32 u_rp_0i : 5; |
| UNSG32 u_rp_1i : 5; |
| UNSG32 u_mLatch_0i : 2; |
| UNSG32 u_mLatch_1i : 2; |
| UNSG32 u_mCtl_0i : 4; |
| UNSG32 u_mCtl_1i : 4; |
| UNSG32 u_sLatch_0i : 2; |
| UNSG32 u_sLatch_1i : 2; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32ticOp_modeShift(r32) _BFGET_(r32, 0, 0) |
| #define SET32ticOp_modeShift(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ticOp_modeShift(r16) _BFGET_(r16, 0, 0) |
| #define SET16ticOp_modeShift(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ticOp_sCtl_0i(r32) _BFGET_(r32, 4, 1) |
| #define SET32ticOp_sCtl_0i(r32,v) _BFSET_(r32, 4, 1,v) |
| #define GET16ticOp_sCtl_0i(r16) _BFGET_(r16, 4, 1) |
| #define SET16ticOp_sCtl_0i(r16,v) _BFSET_(r16, 4, 1,v) |
| |
| #define GET32ticOp_sCtl_1i(r32) _BFGET_(r32, 8, 5) |
| #define SET32ticOp_sCtl_1i(r32,v) _BFSET_(r32, 8, 5,v) |
| #define GET16ticOp_sCtl_1i(r16) _BFGET_(r16, 8, 5) |
| #define SET16ticOp_sCtl_1i(r16,v) _BFSET_(r16, 8, 5,v) |
| |
| #define GET32ticOp_sum_0i(r32) _BFGET_(r32,11, 9) |
| #define SET32ticOp_sum_0i(r32,v) _BFSET_(r32,11, 9,v) |
| #define GET16ticOp_sum_0i(r16) _BFGET_(r16,11, 9) |
| #define SET16ticOp_sum_0i(r16,v) _BFSET_(r16,11, 9,v) |
| |
| #define GET32ticOp_sum_1i(r32) _BFGET_(r32,14,12) |
| #define SET32ticOp_sum_1i(r32,v) _BFSET_(r32,14,12,v) |
| #define GET16ticOp_sum_1i(r16) _BFGET_(r16,14,12) |
| #define SET16ticOp_sum_1i(r16,v) _BFSET_(r16,14,12,v) |
| |
| #define GET32ticOp_accSel_0i(r32) _BFGET_(r32,16,15) |
| #define SET32ticOp_accSel_0i(r32,v) _BFSET_(r32,16,15,v) |
| |
| #define GET32ticOp_accSel_1i(r32) _BFGET_(r32,18,17) |
| #define SET32ticOp_accSel_1i(r32,v) _BFSET_(r32,18,17,v) |
| #define GET16ticOp_accSel_1i(r16) _BFGET_(r16, 2, 1) |
| #define SET16ticOp_accSel_1i(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32ticOp_acc_0i(r32) _BFGET_(r32,21,19) |
| #define SET32ticOp_acc_0i(r32,v) _BFSET_(r32,21,19,v) |
| #define GET16ticOp_acc_0i(r16) _BFGET_(r16, 5, 3) |
| #define SET16ticOp_acc_0i(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32ticOp_acc_1i(r32) _BFGET_(r32,24,22) |
| #define SET32ticOp_acc_1i(r32,v) _BFSET_(r32,24,22,v) |
| #define GET16ticOp_acc_1i(r16) _BFGET_(r16, 8, 6) |
| #define SET16ticOp_acc_1i(r16,v) _BFSET_(r16, 8, 6,v) |
| |
| #define GET32ticOp_desIn(r32) _BFGET_(r32,26,25) |
| #define SET32ticOp_desIn(r32,v) _BFSET_(r32,26,25,v) |
| #define GET16ticOp_desIn(r16) _BFGET_(r16,10, 9) |
| #define SET16ticOp_desIn(r16,v) _BFSET_(r16,10, 9,v) |
| |
| #define GET32ticOp_des(r32) _BFGET_(r32,30,27) |
| #define SET32ticOp_des(r32,v) _BFSET_(r32,30,27,v) |
| #define GET16ticOp_des(r16) _BFGET_(r16,14,11) |
| #define SET16ticOp_des(r16,v) _BFSET_(r16,14,11,v) |
| |
| #define GET32ticOp_clip(r32) _BFGET_(r32,31,31) |
| #define SET32ticOp_clip(r32,v) _BFSET_(r32,31,31,v) |
| #define GET16ticOp_clip(r16) _BFGET_(r16,15,15) |
| #define SET16ticOp_clip(r16,v) _BFSET_(r16,15,15,v) |
| |
| UNSG32 u_modeShift : 1; |
| UNSG32 s_sCtl_0i : 4; |
| UNSG32 s_sCtl_1i : 4; |
| UNSG32 u_sum_0i : 3; |
| UNSG32 u_sum_1i : 3; |
| UNSG32 u_accSel_0i : 2; |
| UNSG32 u_accSel_1i : 2; |
| UNSG32 u_acc_0i : 3; |
| UNSG32 u_acc_1i : 3; |
| UNSG32 u_desIn : 2; |
| UNSG32 u_des : 4; |
| UNSG32 u_clip : 1; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32ticOp_wp(r32) _BFGET_(r32, 4, 0) |
| #define SET32ticOp_wp(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16ticOp_wp(r16) _BFGET_(r16, 4, 0) |
| #define SET16ticOp_wp(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32ticOp_wCtl(r32) _BFGET_(r32, 7, 5) |
| #define SET32ticOp_wCtl(r32,v) _BFSET_(r32, 7, 5,v) |
| #define GET16ticOp_wCtl(r16) _BFGET_(r16, 7, 5) |
| #define SET16ticOp_wCtl(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32ticOp_xmul(r32) _BFGET_(r32, 8, 8) |
| #define SET32ticOp_xmul(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16ticOp_xmul(r16) _BFGET_(r16, 8, 8) |
| #define SET16ticOp_xmul(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32ticOp_xshift(r32) _BFGET_(r32, 9, 9) |
| #define SET32ticOp_xshift(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16ticOp_xshift(r16) _BFGET_(r16, 9, 9) |
| #define SET16ticOp_xshift(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32ticOp_xcmp(r32) _BFGET_(r32,12,10) |
| #define SET32ticOp_xcmp(r32,v) _BFSET_(r32,12,10,v) |
| #define GET16ticOp_xcmp(r16) _BFGET_(r16,12,10) |
| #define SET16ticOp_xcmp(r16,v) _BFSET_(r16,12,10,v) |
| |
| #define GET32ticOp_xdesInSelMode(r32) _BFGET_(r32,13,13) |
| #define SET32ticOp_xdesInSelMode(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16ticOp_xdesInSelMode(r16) _BFGET_(r16,13,13) |
| #define SET16ticOp_xdesInSelMode(r16,v) _BFSET_(r16,13,13,v) |
| |
| UNSG32 u_wp : 5; |
| UNSG32 u_wCtl : 3; |
| UNSG32 u_xmul : 1; |
| UNSG32 u_xshift : 1; |
| UNSG32 u_xcmp : 3; |
| UNSG32 u_xdesInSelMode : 1; |
| UNSG32 RSVDx8_b14 : 18; |
| /////////////////////////////////////////////////////////// |
| } SIE_ticOp; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ticOp_drvrd(SIE_ticOp *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ticOp_drvwr(SIE_ticOp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ticOp_reset(SIE_ticOp *p); |
| SIGN32 ticOp_cmp (SIE_ticOp *p, SIE_ticOp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ticOp_check(p,pie,pfx,hLOG) ticOp_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ticOp_print(p, pfx,hLOG) ticOp_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ticOp |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE ticOp2 biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 1 SIMD |
| /// : x4 0x0 |
| /// : x8 0x1 |
| /// ### |
| /// * SIMD pipeline mode |
| /// ### |
| /// %unsigned 5 in |
| /// ### |
| /// * RF write address for DMEM input |
| /// ### |
| /// %unsigned 5 rp_0i |
| /// %unsigned 5 rp_1i |
| /// ### |
| /// * RF read address of u/v-pipe (related via rtp in instruction) |
| /// * if PINSOP instruction is used, |
| /// * value of rp[0] will be replaced P3INSOPx.rpu |
| /// * value of rp[1] will be replaced P3INSOPx rpv |
| /// ### |
| /// %unsigned 4 mCtl_0i |
| /// %unsigned 4 mCtl_1i |
| /// %unsigned 4 mCtl_2i |
| /// %unsigned 4 mCtl_3i |
| /// ### |
| /// * SIMDx4: multiplication coefficient for u/v-pipe |
| /// * SIMDx8: input shuffling. For rmu and rmv, the shuffling mode is specified in mCtl[0]. For emu and emv, the shuffling mode is specified in mCtl[2]. |
| /// * Elementary modes: N, P, D, Q, X, R |
| /// * Combinations: (N/P/X/Q) – (N/P/D/R) |
| /// * Op-code: 00 (high & low) |
| /// * Op-name: N (no-op) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> 4 5 6 7 |
| /// * A B C D -> A B C D |
| /// * E F G H E F G H |
| /// * Op-code: 01 (high & low) |
| /// * Op-name: P (single-pix muxing): |
| /// * 0 1 2 3 0 A 1 B |
| /// * 4 5 6 7 -> 2 C 3 D |
| /// * A B C D -> 4 E 5 F |
| /// * E F G H 6 G 7 H |
| /// * Op-code: 10 (low) |
| /// * Op-name: D (double-pix muxing) |
| /// * 0 1 2 3 0 1 A B |
| /// * 4 5 6 7 -> 2 3 C D |
| /// * A B C D -> 4 5 E F |
| /// * E F G H 6 7 G H |
| /// * Op-code: 11 (high) |
| /// * Op-name: Q (quad-pix muxing) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> A B C D |
| /// * A B C D -> 4 5 6 7 |
| /// * E F G H E F G H |
| /// * Op-code: 10 (high) |
| /// * Op-name: X (quad-pix exchange): |
| /// * 0 1 2 3 4 5 6 7 |
| /// * 4 5 6 7 -> 0 1 2 3 |
| /// * A B C D -> E F G H |
| /// * E F G H A B C D |
| /// * Op-code: 11 (low) |
| /// * Op-name: R (pix repeating & packing) |
| /// * 0 1 2 3 0 0 A A |
| /// * 4 5 6 7 -> 1 1 B B |
| /// * A B C D -> 2 2 C C |
| /// * E F G H 3 3 D D |
| /// ### |
| /// : bypass 0x0 |
| /// : NN 0x0 |
| /// ### |
| /// * 00-00 (NN): bypass |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> 4 5 6 7 |
| /// * A B C D -> A B C D |
| /// * E F G H E F G H |
| /// ### |
| /// : SPixPac 0xD |
| /// : QP 0xD |
| /// ### |
| /// * 11-01 (QP): single-pix inline packing |
| /// * 0 1 2 3 0 4 1 5 |
| /// * 4 5 6 7 -> 2 6 3 7 |
| /// * A B C D -> A E B F |
| /// * E F G H C G D H |
| /// ### |
| /// : DPixPac 0xE |
| /// : QD 0xE |
| /// ### |
| /// * 11-10 (QD): double-pix inline packing |
| /// * 0 1 2 3 0 1 4 5 |
| /// * 4 5 6 7 -> 2 3 6 7 |
| /// * A B C D -> A B E F |
| /// * E F G H C D G H |
| /// ### |
| /// : SPixMux 0x1 |
| /// : NP 0x1 |
| /// : PN 0x4 |
| /// ### |
| /// * 00-01 (NP): |
| /// * 01-00 (PN): single-pix cross muxing |
| /// * 0 1 2 3 0 A 1 B |
| /// * 4 5 6 7 -> 2 C 3 D |
| /// * A B C D -> 4 E 5 F |
| /// * E F G H 6 G 7 H |
| /// ### |
| /// : DPixMux 0x2 |
| /// : ND 0x2 |
| /// ### |
| /// * 00-10 (ND): double-pix cross muxing |
| /// * 0 1 2 3 0 1 A B |
| /// * 4 5 6 7 -> 2 3 C D |
| /// * A B C D -> 4 5 E F |
| /// * E F G H 6 7 G H |
| /// ### |
| /// : QPixMux 0xC |
| /// : QN 0xC |
| /// ### |
| /// * 11-00 (QN): quad-pix muxing (frame2field) |
| /// * 0 1 2 3 0 1 2 3 |
| /// * 4 5 6 7 -> A B C D |
| /// * A B C D -> 4 5 6 7 |
| /// * E F G H E F G H |
| /// ### |
| /// : XQPix 0x8 |
| /// : XN 0x8 |
| /// ### |
| /// * 10-00 (XN): quad-pix exchange |
| /// * 0 1 2 3 4 5 6 7 |
| /// * 4 5 6 7 -> 0 1 2 3 |
| /// * A B C D -> E F G H |
| /// * E F G H A B C D |
| /// ### |
| /// : DuMuxL 0x3 |
| /// : NR 0x3 |
| /// ### |
| /// * 00-11 (NR): repeat & mux low |
| /// * 0 1 2 3 0 0 A A |
| /// * 4 5 6 7 -> 1 1 B B |
| /// * A B C D -> 2 2 C C |
| /// * E F G H 3 3 D D |
| /// ### |
| /// : DuMuxH 0xB |
| /// : XR 0xB |
| /// ### |
| /// * 10-11 (XR): repeat & mux high |
| /// * 0 1 2 3 4 4 E E |
| /// * 4 5 6 7 -> 5 5 F F |
| /// * A B C D -> 6 6 G G |
| /// * E F G H 7 7 H H |
| /// ### |
| /// : 4x4T 0x5 |
| /// : PP 0x5 |
| /// ### |
| /// * 01-01 (PP): 4x4 transpose |
| /// * 0 1 2 3 0 4 A E |
| /// * 4 5 6 7 -> 1 5 B F |
| /// * A B C D -> 2 6 C G |
| /// * E F G H 3 7 D H |
| /// ### |
| /// : Qmux4x4T 0x6 |
| /// : PD 0x6 |
| /// ### |
| /// * 01-10 (PD): 4x4 transpose after quad-muxing |
| /// * 0 1 2 3 0 A 4 E |
| /// * 4 5 6 7 -> 1 B 5 F |
| /// * A B C D -> 2 C 6 G |
| /// * E F G H 3 D 7 H |
| /// ### |
| /// : PR 0x7 |
| /// : XP 0x9 |
| /// : XD 0xA |
| /// : QR 0xF |
| /// ### |
| /// * Reserved |
| /// * SIMDx8: de-blocking extension (specified in mCtl[1]) |
| /// * bypass |
| /// * 0 |
| /// ### |
| /// : L0 0x8 |
| /// : L1 0x9 |
| /// : L2 0xA |
| /// : L3 0xB |
| /// ### |
| /// * SIMDx8: load fop[15:0] (BS/tc0 or PQUANT) from x4.rv |
| /// * L0: fop[15:0] = rv[15:0] |
| /// * L1: fop[15:0] = rv[35:20] |
| /// * L2: fop[15:0] = rv[55:40] |
| /// * L3: fop[15:0] = rv[75:60] |
| /// ### |
| /// : H0 0xC |
| /// : H1 0xD |
| /// : H2 0xE |
| /// : H3 0xF |
| /// ### |
| /// * SIMDx8: load fop[28:16] (alpha/beta) from x4.rv |
| /// * H0: fop[28:16] = rv[12:0] |
| /// * H1: fop[28:16] = rv[32:20] |
| /// * H2: fop[28:16] = rv[52:40] |
| /// * H3: fop[28:16] = rv[72:60] |
| /// ### |
| /// : xmul_rv_0 0x0 |
| /// : xmul_rv_1 0x1 |
| /// : xmul_rv_2 0x2 |
| /// : xmul_rv_3 0x3 |
| /// : xmul_rv_dot 0x4 |
| /// ### |
| /// * SIMDx4: rv selection for xmul operations (specified in mCtl[0]) |
| /// * xmul_rv_0 : rmu[i] = ru[i] * rv[0] |
| /// * xmul_rv_1 : rmu[i] = ru[i] * rv[1] |
| /// * xmul_rv_2 : rmu[i] = ru[i] * rv[2] |
| /// * xmul_rv_3 : rmu[i] = ru[i] * rv[3] |
| /// * xmul_rv_dot : rmu[i] = ru[i] * rv[i] |
| /// ### |
| /// %unsigned 1 mLatch_0i |
| /// %unsigned 1 mLatch_1i |
| /// : disable 0x0 |
| /// : m2m 0x1 |
| /// ### |
| /// * Latch control for multiplication stage. |
| /// * rmu and emu are controlled by mLatch[0]. rmv and emv are controlled by mLatch[1]. |
| /// ### |
| /// %unsigned 2 xmul |
| /// : disable 0x0 |
| /// : xmul17 0x1 |
| /// : xmul9 0x3 |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * mctl[0:1] still function, meaning mu/mv keep the values in the previous op-code if mctl[0]/mctl[1] is disabled. Otherwise, mu/mv is loaded with the following computation. |
| /// * (1) If xmul == 1 |
| /// * rmu[i] = ru[i] * rv[s][3:0]; |
| /// * rmv[i] = ru[i] * rv[s][7:4]; |
| /// * emu[i] = ru[i] * rv[s][11:8]; |
| /// * emv[i] = ru[i] * rv[s][16:12]; |
| /// * value of s comes from mCtl[0]. |
| /// * The main usage is to calculate signed 20bits (stored in ru) multiplied by one singed 17b (in rv). The complete computation takes 2 op-codes, one for low 16 bits, and a second one for high 20 bits. |
| /// * (2) If xmul == 3 |
| /// * rmu[i] = ru[i] * rv[s][3:0]; |
| /// * rmv[i] = ru[i] * rv[s][8:4]; |
| /// * emu[i] = ru[i] *rv[s][11:8]; |
| /// * emv[i] = ru[i] * rv[s][16:12]; |
| /// * value of s comes from mCtl[0]. |
| /// * The main usage is to calculate signed 20bits (stored in ru) multiplied by one signed 9b (in rv). This can be completed in one op-code, so it is more efficient than xmul9=0 if the multiplicand (rv) is small. |
| /// ### |
| /// %signed 4 sCtl_0i |
| /// %signed 4 sCtl_1i |
| /// %signed 4 sCtl_2i |
| /// %signed 4 sCtl_3i |
| /// ### |
| /// * Shift-bits: -8~7, for SIMDx4 only |
| /// ### |
| /// : bypass 0 |
| /// : Hwsh1 1 |
| /// : Hwsh2 2 |
| /// : Hwsh3 3 |
| /// : Hwsh4 4 |
| /// : Fwpad1 15 |
| /// : Fwpad2 14 |
| /// : Fwpad3 13 |
| /// ### |
| /// * Shift-words: half-word shift 0~4, full-word pad 1~3 |
| /// * rsu = Hwsh(rmu, rmv) or Fwpad(rmu), controlled by sCtl[0] |
| /// * rsv = Hwsh(rmu, rmv) or Fwpad(rmv), controlled by sCtl[1] |
| /// * esu=Hwsh(emu,emv) or Fwpad(emu), controlled by sCtl[2] |
| /// * esv=Hwsh(emu,emv) or Fwpad(emv), controlled by sCtl[3] |
| /// * Note that the functions of Hwsh/Fwpad in u-pipe and v-pipe are asymmetric. |
| /// * sCtl[0:3] are ignored when xshift > 1. |
| /// ### |
| /// %unsigned 2 sLatch_0i |
| /// %unsigned 2 sLatch_1i |
| /// : disable 0x0 |
| /// : r2r_e2e 0x1 |
| /// : r2e_e2r 0x2 |
| /// ### |
| /// * Latch control for shifting stage. |
| /// * rsu and esu are controlled by sLatch[0]. rsv and esv are controlled by sLatch[1]. |
| /// ### |
| /// %unsigned 4 sum_0i |
| /// %unsigned 4 sum_1i |
| /// : disable 0x0 |
| /// : abs 0x1 |
| /// : equ 0x2 |
| /// : eqv 0x3 |
| /// : add_add 0x4 |
| /// : add_sub 0x5 |
| /// : sub_add 0x6 |
| /// : sub_sub 0x7 |
| /// : EQ 0xA |
| /// : EQj 0xB |
| /// : G 0xC |
| /// : Gj 0xD |
| /// : L 0xE |
| /// : Lj 0xF |
| /// ### |
| /// * SIMDx4: sum stage control of basic/extra pipeline |
| /// * Usage: |
| /// * sum[0] ; sum[1] |
| /// * abs: | rsu[i]-rsv[i] | ; | esu[i]-esv[i] | |
| /// * equ: rsum[i]=rsu[i] ; esum[i]=esu[i] |
| /// * eqv: rsum[i]=rsv[i] ; esum[i]=esv[i] |
| /// * add_add: rsum[i]=+rsu[i]+rsv[i]; esum[i]=+esu[i]+esv[i] |
| /// * add_sub: rsum[i]=+rsu[i]-rsv[i] ; esum[i]=+esu[i]-esv[i] |
| /// * sub_add: rsum[i]=-rsu[i]+rsv[i] ; esum[i]=-esu[i]+esv[i] |
| /// * sub_sub: rsum[i]=-rsu[i]-rsv[i] ; esum[i]=-esu[i]-esv[i] |
| /// * EQ, Eqj, G, Gj, L, Lj are comparison modes. They are used only in SIMD4 mode: |
| /// * rsum[i] = (signed 20b)rsu[i] <cmp> (signed 20b)rsv[i] ? 20'hFFFFF : 20'h0. The <cmp> is specified in sum[0]. |
| /// * esum[i] = (signed 20b)esu[i] <cmp> (signed 20b)esv[i] ? 20'hFFFFF : 20'h0. The <cmp> is specified in sum[1]. |
| /// * disable |
| /// * 0 |
| /// * abs |
| /// * 1 |
| /// * 10b |
| /// * equ |
| /// * 2 |
| /// * eqv |
| /// * 3 |
| /// ### |
| /// : equm 0x4 |
| /// : eqvm 0x5 |
| /// : equmEx 0x6 |
| /// : eqvmEx 0x7 |
| /// : db 0x4 |
| /// : luma 0x6 |
| /// : chroma 0x7 |
| /// ### |
| /// * SIMDx8: sum stage control of basic/extra pipeline |
| /// * Usage: |
| /// * sum[0] only supports equ, eqv, equm(Ex), and eqvm(Ex) |
| /// * sum[1] only supports equ, eqv, db, luma, and chroma |
| /// * The following is the legal combination and behavior: |
| /// * (A) when sum[1] != db or luma or chroma |
| /// * sum[0] operations |
| /// * equ: rsum[i]=rsu[i] |
| /// * eqv: rsum[i]=rsv[i] |
| /// * equm(Ex): rsum[i]=rmu[i] |
| /// * eqvm(Ex): rsum[i]=rmv[i] |
| /// * CAUTION: when using equm/eqvm/equmEs/eqvmEx, the mLatch in the next opcode should set to “disable” to avoid mismatches between C-model and RTL.: Strongly suggest to use them in DBLK usage only. |
| /// * (B) when sum[1] = db (for H.264, VC1, AVS, RV) |
| /// * rsum[i] is rsu, rsv, rmu or rmv, determined by sum[0] |
| /// * esum[i] has the value from DBLK output |
| /// * (C) when sum[1] = luma (for H.264, AVS, RV) |
| /// * set filter selection as 0 |
| /// * rsum[i] and esum[i] kept as the ones in previous opcode |
| /// * (D) when sum[1] = chroma (for H.264, AVS, RV) |
| /// * set filter selection as 1 |
| /// * rsum[i] and esum[i] kept as the ones in previous opcode |
| /// ### |
| /// %unsigned 2 accSel_0i |
| /// %unsigned 2 accSel_1i |
| /// : e2r 0x0 |
| /// : r2r 0x1 |
| /// : t2r 0x2 |
| /// : t2t 0x3 |
| /// ### |
| /// * I/O select for accumulation stage of basic pipeline |
| /// ### |
| /// : r2e 0x0 |
| /// : e2e 0x1 |
| /// : t2e 0x2 |
| /// ### |
| /// * t2t |
| /// * 3 |
| /// * t=tacc+esum |
| /// * I/O select for accumulation stage of extra pipeline |
| /// ### |
| /// %unsigned 3 acc_0i |
| /// %unsigned 3 acc_1i |
| /// : disable 0x0 |
| /// ### |
| /// * pack |
| /// * 1 |
| /// ### |
| /// : eqsum 0x3 |
| /// : add_add 0x4 |
| /// : xor 0x5 |
| /// : or 0x6 |
| /// : and 0x7 |
| /// ### |
| /// * SIMDx4: accumulation control of basic/extra pipeline |
| /// * disable |
| /// * 0 |
| /// * pack |
| /// * 1 |
| /// * unpack |
| /// * 2 |
| /// * eqsum |
| /// * 3 |
| /// * add_add |
| /// * 4 |
| /// * xor |
| /// * 5 |
| /// * or |
| /// * 6 |
| /// * and |
| /// * 7 |
| /// * SIMDx8: accumulation control of basic/extra pipeline |
| /// ### |
| /// %unsigned 2 desIn |
| /// : disable 0x0 |
| /// : racc 0x1 |
| /// : tacc 0x2 |
| /// : eacc 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 0 |
| /// ### |
| /// : racc_AND_eacc 0x0 |
| /// : tacc_OR_eacc 0x1 |
| /// : racc_OR_eacc 0x2 |
| /// : racc_OR_tacc 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 1 and under SIMD4 mode. Note racc_AND_eacc is currently not supported. |
| /// ### |
| /// : racc_low16 0x1 |
| /// : tacc_low16 0x2 |
| /// : eacc_low16 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 2 and under SIMD4 mode. Takes one of the following: |
| /// * unsigned racc[15:0] |
| /// * unsigned tacc[15:0] |
| /// * unsigned eacc[15:0] |
| /// ### |
| /// : racc_ADD_tacc_high 0x1 |
| /// : racc_ADD_eacc_high 0x2 |
| /// : eacc_ADD_tacc_high 0x3 |
| /// ### |
| /// * Input select for de-scale stage when xdesInSelMode = 3 and under SIMD4 mode. Computes one of the following: |
| /// * racc+signed tacc[19:16] |
| /// * racc+signed eacc[19:16] |
| /// * eacc+signed tacc[19:16] |
| /// ### |
| /// %unsigned 4 des |
| /// ### |
| /// * SIMDx4: de-scaling bits 0~14 |
| /// ### |
| /// : bypass 0x0 |
| /// : frm2fld 0xF |
| /// ### |
| /// * SIMDx8: |
| /// * frm2fld (0xF): output shuffling |
| /// * (0b0001~0b0110): unsigned right shift bits 1~6 for descaling |
| /// * (0b1001~0b1110): signed right shift bits 1~6 for descaling |
| /// ### |
| /// %unsigned 1 clip |
| /// ### |
| /// * 0/1 to disable/enable clipping output (16-bit clip for SIMD4 10-bit clip for SIMD8) |
| /// ### |
| /// %unsigned 5 wp |
| /// ### |
| /// * RF write address |
| /// * if P3INSOPWRF instruction is used, |
| /// * value of wp will be replaced P3INSOPWRF.wp |
| /// ### |
| /// %unsigned 3 wCtl |
| /// : disable 0x0 |
| /// : RF 0x1 |
| /// : dmem 0x2 |
| /// : both 0x3 |
| /// : min 0x4 |
| /// : max 0x5 |
| /// ### |
| /// * RF/DMEM & special registers write-back control |
| /// ### |
| /// %unsigned 3 xshift |
| /// : const_bits 0x0 |
| /// : const_words 0x1 |
| /// : register_shift 0x2 |
| /// : low_16 0x3 |
| /// : high_20 0x4 |
| /// ### |
| /// * If xshift != 1, it is operated in SIMD4 only, and will be ignored in SIMD8. |
| /// * slatch[0:1] still function, meaning that if slatch[i] is disabled, su/sv keep the values in the previous code. Otherwise, the following computation is loaded to su/sv according to the xshift value: |
| /// * 0: constant bit-shift, controlled by sCtl[0:3]; |
| /// * 1: constant word-shift, controlled by sCtl[0:3]: |
| /// * rsu = Hwsh(rmu, rmv) or Fwpad(rmu), controlled by sCtl[0] |
| /// * rsv = Hwsh(rmu, rmv) or Fwpad(rmv), controlled by sCtl[1] |
| /// * esu=Hwsh(emu,emv) or Fwpad(emu), controlled by sCtl[2] |
| /// * esv=Hwsh(emu,emv) or Fwpad(emv), controlled by sCtl[3] |
| /// * Note that the functions of Hwsh/Fwpad in u-pipe and v-pipe are asymmetric. |
| /// * 2: rsu[i]=rsv[i]=(signed20b)( rmu[i]<< (signed 4b)rmv[i] ) |
| /// * esu[i]=esv[i]=(signed20b)( emu[i]<<(signed 4b)emv[i] ) |
| /// * sCtl[0:3] are ignored |
| /// * 3. Get low 16 bits in SIGN20b*SIGN17b multiplication |
| /// * rsu = unsigned rmu[15:0]; |
| /// * rsv = unsigned rmv[11:0]<<4; |
| /// * esu = unsigned emu[7:0]<<8; |
| /// * esv = unsigned emv[3:0]<<12; |
| /// * sCtl[0:3] are ignored |
| /// * 4. Get high 20 bits in SIGN20b*SIGN17b multiplication |
| /// * rsu = signed rmu[23:16]; |
| /// * rsv = signed rmv[23:12]; |
| /// * esu = signed emu[23:8]; |
| /// * esv = signed emv[23:4]; |
| /// * sCtl[0:3] are ignored |
| /// * Stage: shift |
| /// ### |
| /// %unsigned 2 xdesInSelMode |
| /// : des 0x0 |
| /// : acc_or 0x1 |
| /// : unsg16_des 0x2 |
| /// : addc 0x3 |
| /// ### |
| /// * Operates in SIMD 4 mode; will be ignored in SIMD8 mode |
| /// * (1) when xdesInSelMode == 0: |
| /// * desIn selects one acc register and perform descaling or frm2fld on the selected register based on des value. |
| /// * (2) when xdesInSelMode == 1 : |
| /// * (2.a) desIn = 1 ~ 3 selects acc register pair denoted as xacc and yacc; then perform logic operation OR. |
| /// * rout[i] = xacc[i] OR yacc[i]. |
| /// * (2.b) desIn =0 ; acc register pair is selected by default and perform logic operation AND. Note this mode is currently not supported. |
| /// * rout[i] = racc[i] AND eacc[i]. |
| /// * (3) when xdesInSelMode == 2: |
| /// * desIn = 1~3 selects one acc register and get its (unsigned) low 16 bits and perform descaling based on des value. |
| /// * (4) when xdesInSelMode == 3: |
| /// * desIn = 1~3 selects acc register pair denoted as xacc and yacc, and compute xacc + (signed yacc[19:16]) |
| /// ### |
| /// %unsigned 1 zero_extension |
| /// ### |
| /// * 0: sign extension to 20 bits when read 16 bits from DMEM |
| /// * 1: zero extension to 20 bits when read 16 bits from DMEM |
| /// ### |
| /// %% 1 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 12B, bits: 95b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ticOp2 |
| #define h_ticOp2 (){} |
| |
| #define BA_ticOp2_SIMD 0x0000 |
| #define B16ticOp2_SIMD 0x0000 |
| #define LSb32ticOp2_SIMD 0 |
| #define LSb16ticOp2_SIMD 0 |
| #define bticOp2_SIMD 1 |
| #define MSK32ticOp2_SIMD 0x00000001 |
| #define ticOp2_SIMD_x4 0x0 |
| #define ticOp2_SIMD_x8 0x1 |
| |
| #define BA_ticOp2_in 0x0000 |
| #define B16ticOp2_in 0x0000 |
| #define LSb32ticOp2_in 1 |
| #define LSb16ticOp2_in 1 |
| #define bticOp2_in 5 |
| #define MSK32ticOp2_in 0x0000003E |
| |
| #define BA_ticOp2_rp_0i 0x0000 |
| #define B16ticOp2_rp_0i 0x0000 |
| #define LSb32ticOp2_rp_0i 6 |
| #define LSb16ticOp2_rp_0i 6 |
| #define bticOp2_rp_0i 5 |
| #define MSK32ticOp2_rp_0i 0x000007C0 |
| |
| #define BA_ticOp2_rp_1i 0x0001 |
| #define B16ticOp2_rp_1i 0x0000 |
| #define LSb32ticOp2_rp_1i 11 |
| #define LSb16ticOp2_rp_1i 11 |
| #define bticOp2_rp_1i 5 |
| #define MSK32ticOp2_rp_1i 0x0000F800 |
| |
| #define BA_ticOp2_mCtl_0i 0x0002 |
| #define B16ticOp2_mCtl_0i 0x0002 |
| #define LSb32ticOp2_mCtl_0i 16 |
| #define LSb16ticOp2_mCtl_0i 0 |
| #define bticOp2_mCtl_0i 4 |
| #define MSK32ticOp2_mCtl_0i 0x000F0000 |
| |
| #define BA_ticOp2_mCtl_1i 0x0002 |
| #define B16ticOp2_mCtl_1i 0x0002 |
| #define LSb32ticOp2_mCtl_1i 20 |
| #define LSb16ticOp2_mCtl_1i 4 |
| #define bticOp2_mCtl_1i 4 |
| #define MSK32ticOp2_mCtl_1i 0x00F00000 |
| |
| #define BA_ticOp2_mCtl_2i 0x0003 |
| #define B16ticOp2_mCtl_2i 0x0002 |
| #define LSb32ticOp2_mCtl_2i 24 |
| #define LSb16ticOp2_mCtl_2i 8 |
| #define bticOp2_mCtl_2i 4 |
| #define MSK32ticOp2_mCtl_2i 0x0F000000 |
| |
| #define BA_ticOp2_mCtl_3i 0x0003 |
| #define B16ticOp2_mCtl_3i 0x0002 |
| #define LSb32ticOp2_mCtl_3i 28 |
| #define LSb16ticOp2_mCtl_3i 12 |
| #define bticOp2_mCtl_3i 4 |
| #define MSK32ticOp2_mCtl_3i 0xF0000000 |
| #define ticOp2_mCtl_bypass 0x0 |
| #define ticOp2_mCtl_NN 0x0 |
| #define ticOp2_mCtl_SPixPac 0xD |
| #define ticOp2_mCtl_QP 0xD |
| #define ticOp2_mCtl_DPixPac 0xE |
| #define ticOp2_mCtl_QD 0xE |
| #define ticOp2_mCtl_SPixMux 0x1 |
| #define ticOp2_mCtl_NP 0x1 |
| #define ticOp2_mCtl_PN 0x4 |
| #define ticOp2_mCtl_DPixMux 0x2 |
| #define ticOp2_mCtl_ND 0x2 |
| #define ticOp2_mCtl_QPixMux 0xC |
| #define ticOp2_mCtl_QN 0xC |
| #define ticOp2_mCtl_XQPix 0x8 |
| #define ticOp2_mCtl_XN 0x8 |
| #define ticOp2_mCtl_DuMuxL 0x3 |
| #define ticOp2_mCtl_NR 0x3 |
| #define ticOp2_mCtl_DuMuxH 0xB |
| #define ticOp2_mCtl_XR 0xB |
| #define ticOp2_mCtl_4x4T 0x5 |
| #define ticOp2_mCtl_PP 0x5 |
| #define ticOp2_mCtl_Qmux4x4T 0x6 |
| #define ticOp2_mCtl_PD 0x6 |
| #define ticOp2_mCtl_PR 0x7 |
| #define ticOp2_mCtl_XP 0x9 |
| #define ticOp2_mCtl_XD 0xA |
| #define ticOp2_mCtl_QR 0xF |
| #define ticOp2_mCtl_L0 0x8 |
| #define ticOp2_mCtl_L1 0x9 |
| #define ticOp2_mCtl_L2 0xA |
| #define ticOp2_mCtl_L3 0xB |
| #define ticOp2_mCtl_H0 0xC |
| #define ticOp2_mCtl_H1 0xD |
| #define ticOp2_mCtl_H2 0xE |
| #define ticOp2_mCtl_H3 0xF |
| #define ticOp2_mCtl_xmul_rv_0 0x0 |
| #define ticOp2_mCtl_xmul_rv_1 0x1 |
| #define ticOp2_mCtl_xmul_rv_2 0x2 |
| #define ticOp2_mCtl_xmul_rv_3 0x3 |
| #define ticOp2_mCtl_xmul_rv_dot 0x4 |
| |
| #define BA_ticOp2_mLatch_0i 0x0004 |
| #define B16ticOp2_mLatch_0i 0x0004 |
| #define LSb32ticOp2_mLatch_0i 0 |
| #define LSb16ticOp2_mLatch_0i 0 |
| #define bticOp2_mLatch_0i 1 |
| #define MSK32ticOp2_mLatch_0i 0x00000001 |
| |
| #define BA_ticOp2_mLatch_1i 0x0004 |
| #define B16ticOp2_mLatch_1i 0x0004 |
| #define LSb32ticOp2_mLatch_1i 1 |
| #define LSb16ticOp2_mLatch_1i 1 |
| #define bticOp2_mLatch_1i 1 |
| #define MSK32ticOp2_mLatch_1i 0x00000002 |
| #define ticOp2_mLatch_disable 0x0 |
| #define ticOp2_mLatch_m2m 0x1 |
| |
| #define BA_ticOp2_xmul 0x0004 |
| #define B16ticOp2_xmul 0x0004 |
| #define LSb32ticOp2_xmul 2 |
| #define LSb16ticOp2_xmul 2 |
| #define bticOp2_xmul 2 |
| #define MSK32ticOp2_xmul 0x0000000C |
| #define ticOp2_xmul_disable 0x0 |
| #define ticOp2_xmul_xmul17 0x1 |
| #define ticOp2_xmul_xmul9 0x3 |
| |
| #define BA_ticOp2_sCtl_0i 0x0004 |
| #define B16ticOp2_sCtl_0i 0x0004 |
| #define LSb32ticOp2_sCtl_0i 4 |
| #define LSb16ticOp2_sCtl_0i 4 |
| #define bticOp2_sCtl_0i 4 |
| #define MSK32ticOp2_sCtl_0i 0x000000F0 |
| |
| #define BA_ticOp2_sCtl_1i 0x0005 |
| #define B16ticOp2_sCtl_1i 0x0004 |
| #define LSb32ticOp2_sCtl_1i 8 |
| #define LSb16ticOp2_sCtl_1i 8 |
| #define bticOp2_sCtl_1i 4 |
| #define MSK32ticOp2_sCtl_1i 0x00000F00 |
| |
| #define BA_ticOp2_sCtl_2i 0x0005 |
| #define B16ticOp2_sCtl_2i 0x0004 |
| #define LSb32ticOp2_sCtl_2i 12 |
| #define LSb16ticOp2_sCtl_2i 12 |
| #define bticOp2_sCtl_2i 4 |
| #define MSK32ticOp2_sCtl_2i 0x0000F000 |
| |
| #define BA_ticOp2_sCtl_3i 0x0006 |
| #define B16ticOp2_sCtl_3i 0x0006 |
| #define LSb32ticOp2_sCtl_3i 16 |
| #define LSb16ticOp2_sCtl_3i 0 |
| #define bticOp2_sCtl_3i 4 |
| #define MSK32ticOp2_sCtl_3i 0x000F0000 |
| #define ticOp2_sCtl_bypass 0 |
| #define ticOp2_sCtl_Hwsh1 1 |
| #define ticOp2_sCtl_Hwsh2 2 |
| #define ticOp2_sCtl_Hwsh3 3 |
| #define ticOp2_sCtl_Hwsh4 4 |
| #define ticOp2_sCtl_Fwpad1 15 |
| #define ticOp2_sCtl_Fwpad2 14 |
| #define ticOp2_sCtl_Fwpad3 13 |
| |
| #define BA_ticOp2_sLatch_0i 0x0006 |
| #define B16ticOp2_sLatch_0i 0x0006 |
| #define LSb32ticOp2_sLatch_0i 20 |
| #define LSb16ticOp2_sLatch_0i 4 |
| #define bticOp2_sLatch_0i 2 |
| #define MSK32ticOp2_sLatch_0i 0x00300000 |
| |
| #define BA_ticOp2_sLatch_1i 0x0006 |
| #define B16ticOp2_sLatch_1i 0x0006 |
| #define LSb32ticOp2_sLatch_1i 22 |
| #define LSb16ticOp2_sLatch_1i 6 |
| #define bticOp2_sLatch_1i 2 |
| #define MSK32ticOp2_sLatch_1i 0x00C00000 |
| #define ticOp2_sLatch_disable 0x0 |
| #define ticOp2_sLatch_r2r_e2e 0x1 |
| #define ticOp2_sLatch_r2e_e2r 0x2 |
| |
| #define BA_ticOp2_sum_0i 0x0007 |
| #define B16ticOp2_sum_0i 0x0006 |
| #define LSb32ticOp2_sum_0i 24 |
| #define LSb16ticOp2_sum_0i 8 |
| #define bticOp2_sum_0i 4 |
| #define MSK32ticOp2_sum_0i 0x0F000000 |
| |
| #define BA_ticOp2_sum_1i 0x0007 |
| #define B16ticOp2_sum_1i 0x0006 |
| #define LSb32ticOp2_sum_1i 28 |
| #define LSb16ticOp2_sum_1i 12 |
| #define bticOp2_sum_1i 4 |
| #define MSK32ticOp2_sum_1i 0xF0000000 |
| #define ticOp2_sum_disable 0x0 |
| #define ticOp2_sum_abs 0x1 |
| #define ticOp2_sum_equ 0x2 |
| #define ticOp2_sum_eqv 0x3 |
| #define ticOp2_sum_add_add 0x4 |
| #define ticOp2_sum_add_sub 0x5 |
| #define ticOp2_sum_sub_add 0x6 |
| #define ticOp2_sum_sub_sub 0x7 |
| #define ticOp2_sum_EQ 0xA |
| #define ticOp2_sum_EQj 0xB |
| #define ticOp2_sum_G 0xC |
| #define ticOp2_sum_Gj 0xD |
| #define ticOp2_sum_L 0xE |
| #define ticOp2_sum_Lj 0xF |
| #define ticOp2_sum_equm 0x4 |
| #define ticOp2_sum_eqvm 0x5 |
| #define ticOp2_sum_equmEx 0x6 |
| #define ticOp2_sum_eqvmEx 0x7 |
| #define ticOp2_sum_db 0x4 |
| #define ticOp2_sum_luma 0x6 |
| #define ticOp2_sum_chroma 0x7 |
| |
| #define BA_ticOp2_accSel_0i 0x0008 |
| #define B16ticOp2_accSel_0i 0x0008 |
| #define LSb32ticOp2_accSel_0i 0 |
| #define LSb16ticOp2_accSel_0i 0 |
| #define bticOp2_accSel_0i 2 |
| #define MSK32ticOp2_accSel_0i 0x00000003 |
| |
| #define BA_ticOp2_accSel_1i 0x0008 |
| #define B16ticOp2_accSel_1i 0x0008 |
| #define LSb32ticOp2_accSel_1i 2 |
| #define LSb16ticOp2_accSel_1i 2 |
| #define bticOp2_accSel_1i 2 |
| #define MSK32ticOp2_accSel_1i 0x0000000C |
| #define ticOp2_accSel_e2r 0x0 |
| #define ticOp2_accSel_r2r 0x1 |
| #define ticOp2_accSel_t2r 0x2 |
| #define ticOp2_accSel_t2t 0x3 |
| #define ticOp2_accSel_r2e 0x0 |
| #define ticOp2_accSel_e2e 0x1 |
| #define ticOp2_accSel_t2e 0x2 |
| |
| #define BA_ticOp2_acc_0i 0x0008 |
| #define B16ticOp2_acc_0i 0x0008 |
| #define LSb32ticOp2_acc_0i 4 |
| #define LSb16ticOp2_acc_0i 4 |
| #define bticOp2_acc_0i 3 |
| #define MSK32ticOp2_acc_0i 0x00000070 |
| |
| #define BA_ticOp2_acc_1i 0x0008 |
| #define B16ticOp2_acc_1i 0x0008 |
| #define LSb32ticOp2_acc_1i 7 |
| #define LSb16ticOp2_acc_1i 7 |
| #define bticOp2_acc_1i 3 |
| #define MSK32ticOp2_acc_1i 0x00000380 |
| #define ticOp2_acc_disable 0x0 |
| #define ticOp2_acc_eqsum 0x3 |
| #define ticOp2_acc_add_add 0x4 |
| #define ticOp2_acc_xor 0x5 |
| #define ticOp2_acc_or 0x6 |
| #define ticOp2_acc_and 0x7 |
| |
| #define BA_ticOp2_desIn 0x0009 |
| #define B16ticOp2_desIn 0x0008 |
| #define LSb32ticOp2_desIn 10 |
| #define LSb16ticOp2_desIn 10 |
| #define bticOp2_desIn 2 |
| #define MSK32ticOp2_desIn 0x00000C00 |
| #define ticOp2_desIn_disable 0x0 |
| #define ticOp2_desIn_racc 0x1 |
| #define ticOp2_desIn_tacc 0x2 |
| #define ticOp2_desIn_eacc 0x3 |
| #define ticOp2_desIn_racc_AND_eacc 0x0 |
| #define ticOp2_desIn_tacc_OR_eacc 0x1 |
| #define ticOp2_desIn_racc_OR_eacc 0x2 |
| #define ticOp2_desIn_racc_OR_tacc 0x3 |
| #define ticOp2_desIn_racc_low16 0x1 |
| #define ticOp2_desIn_tacc_low16 0x2 |
| #define ticOp2_desIn_eacc_low16 0x3 |
| #define ticOp2_desIn_racc_ADD_tacc_high 0x1 |
| #define ticOp2_desIn_racc_ADD_eacc_high 0x2 |
| #define ticOp2_desIn_eacc_ADD_tacc_high 0x3 |
| |
| #define BA_ticOp2_des 0x0009 |
| #define B16ticOp2_des 0x0008 |
| #define LSb32ticOp2_des 12 |
| #define LSb16ticOp2_des 12 |
| #define bticOp2_des 4 |
| #define MSK32ticOp2_des 0x0000F000 |
| #define ticOp2_des_bypass 0x0 |
| #define ticOp2_des_frm2fld 0xF |
| |
| #define BA_ticOp2_clip 0x000A |
| #define B16ticOp2_clip 0x000A |
| #define LSb32ticOp2_clip 16 |
| #define LSb16ticOp2_clip 0 |
| #define bticOp2_clip 1 |
| #define MSK32ticOp2_clip 0x00010000 |
| |
| #define BA_ticOp2_wp 0x000A |
| #define B16ticOp2_wp 0x000A |
| #define LSb32ticOp2_wp 17 |
| #define LSb16ticOp2_wp 1 |
| #define bticOp2_wp 5 |
| #define MSK32ticOp2_wp 0x003E0000 |
| |
| #define BA_ticOp2_wCtl 0x000A |
| #define B16ticOp2_wCtl 0x000A |
| #define LSb32ticOp2_wCtl 22 |
| #define LSb16ticOp2_wCtl 6 |
| #define bticOp2_wCtl 3 |
| #define MSK32ticOp2_wCtl 0x01C00000 |
| #define ticOp2_wCtl_disable 0x0 |
| #define ticOp2_wCtl_RF 0x1 |
| #define ticOp2_wCtl_dmem 0x2 |
| #define ticOp2_wCtl_both 0x3 |
| #define ticOp2_wCtl_min 0x4 |
| #define ticOp2_wCtl_max 0x5 |
| |
| #define BA_ticOp2_xshift 0x000B |
| #define B16ticOp2_xshift 0x000A |
| #define LSb32ticOp2_xshift 25 |
| #define LSb16ticOp2_xshift 9 |
| #define bticOp2_xshift 3 |
| #define MSK32ticOp2_xshift 0x0E000000 |
| #define ticOp2_xshift_const_bits 0x0 |
| #define ticOp2_xshift_const_words 0x1 |
| #define ticOp2_xshift_register_shift 0x2 |
| #define ticOp2_xshift_low_16 0x3 |
| #define ticOp2_xshift_high_20 0x4 |
| |
| #define BA_ticOp2_xdesInSelMode 0x000B |
| #define B16ticOp2_xdesInSelMode 0x000A |
| #define LSb32ticOp2_xdesInSelMode 28 |
| #define LSb16ticOp2_xdesInSelMode 12 |
| #define bticOp2_xdesInSelMode 2 |
| #define MSK32ticOp2_xdesInSelMode 0x30000000 |
| #define ticOp2_xdesInSelMode_des 0x0 |
| #define ticOp2_xdesInSelMode_acc_or 0x1 |
| #define ticOp2_xdesInSelMode_unsg16_des 0x2 |
| #define ticOp2_xdesInSelMode_addc 0x3 |
| |
| #define BA_ticOp2_zero_extension 0x000B |
| #define B16ticOp2_zero_extension 0x000A |
| #define LSb32ticOp2_zero_extension 30 |
| #define LSb16ticOp2_zero_extension 14 |
| #define bticOp2_zero_extension 1 |
| #define MSK32ticOp2_zero_extension 0x40000000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ticOp2 { |
| /////////////////////////////////////////////////////////// |
| #define GET32ticOp2_SIMD(r32) _BFGET_(r32, 0, 0) |
| #define SET32ticOp2_SIMD(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ticOp2_SIMD(r16) _BFGET_(r16, 0, 0) |
| #define SET16ticOp2_SIMD(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ticOp2_in(r32) _BFGET_(r32, 5, 1) |
| #define SET32ticOp2_in(r32,v) _BFSET_(r32, 5, 1,v) |
| #define GET16ticOp2_in(r16) _BFGET_(r16, 5, 1) |
| #define SET16ticOp2_in(r16,v) _BFSET_(r16, 5, 1,v) |
| |
| #define GET32ticOp2_rp_0i(r32) _BFGET_(r32,10, 6) |
| #define SET32ticOp2_rp_0i(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16ticOp2_rp_0i(r16) _BFGET_(r16,10, 6) |
| #define SET16ticOp2_rp_0i(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define GET32ticOp2_rp_1i(r32) _BFGET_(r32,15,11) |
| #define SET32ticOp2_rp_1i(r32,v) _BFSET_(r32,15,11,v) |
| #define GET16ticOp2_rp_1i(r16) _BFGET_(r16,15,11) |
| #define SET16ticOp2_rp_1i(r16,v) _BFSET_(r16,15,11,v) |
| |
| #define GET32ticOp2_mCtl_0i(r32) _BFGET_(r32,19,16) |
| #define SET32ticOp2_mCtl_0i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16ticOp2_mCtl_0i(r16) _BFGET_(r16, 3, 0) |
| #define SET16ticOp2_mCtl_0i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32ticOp2_mCtl_1i(r32) _BFGET_(r32,23,20) |
| #define SET32ticOp2_mCtl_1i(r32,v) _BFSET_(r32,23,20,v) |
| #define GET16ticOp2_mCtl_1i(r16) _BFGET_(r16, 7, 4) |
| #define SET16ticOp2_mCtl_1i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32ticOp2_mCtl_2i(r32) _BFGET_(r32,27,24) |
| #define SET32ticOp2_mCtl_2i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16ticOp2_mCtl_2i(r16) _BFGET_(r16,11, 8) |
| #define SET16ticOp2_mCtl_2i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32ticOp2_mCtl_3i(r32) _BFGET_(r32,31,28) |
| #define SET32ticOp2_mCtl_3i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16ticOp2_mCtl_3i(r16) _BFGET_(r16,15,12) |
| #define SET16ticOp2_mCtl_3i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_SIMD : 1; |
| UNSG32 u_in : 5; |
| UNSG32 u_rp_0i : 5; |
| UNSG32 u_rp_1i : 5; |
| UNSG32 u_mCtl_0i : 4; |
| UNSG32 u_mCtl_1i : 4; |
| UNSG32 u_mCtl_2i : 4; |
| UNSG32 u_mCtl_3i : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32ticOp2_mLatch_0i(r32) _BFGET_(r32, 0, 0) |
| #define SET32ticOp2_mLatch_0i(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16ticOp2_mLatch_0i(r16) _BFGET_(r16, 0, 0) |
| #define SET16ticOp2_mLatch_0i(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ticOp2_mLatch_1i(r32) _BFGET_(r32, 1, 1) |
| #define SET32ticOp2_mLatch_1i(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16ticOp2_mLatch_1i(r16) _BFGET_(r16, 1, 1) |
| #define SET16ticOp2_mLatch_1i(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32ticOp2_xmul(r32) _BFGET_(r32, 3, 2) |
| #define SET32ticOp2_xmul(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16ticOp2_xmul(r16) _BFGET_(r16, 3, 2) |
| #define SET16ticOp2_xmul(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32ticOp2_sCtl_0i(r32) _BFGET_(r32, 7, 4) |
| #define SET32ticOp2_sCtl_0i(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16ticOp2_sCtl_0i(r16) _BFGET_(r16, 7, 4) |
| #define SET16ticOp2_sCtl_0i(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32ticOp2_sCtl_1i(r32) _BFGET_(r32,11, 8) |
| #define SET32ticOp2_sCtl_1i(r32,v) _BFSET_(r32,11, 8,v) |
| #define GET16ticOp2_sCtl_1i(r16) _BFGET_(r16,11, 8) |
| #define SET16ticOp2_sCtl_1i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32ticOp2_sCtl_2i(r32) _BFGET_(r32,15,12) |
| #define SET32ticOp2_sCtl_2i(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16ticOp2_sCtl_2i(r16) _BFGET_(r16,15,12) |
| #define SET16ticOp2_sCtl_2i(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32ticOp2_sCtl_3i(r32) _BFGET_(r32,19,16) |
| #define SET32ticOp2_sCtl_3i(r32,v) _BFSET_(r32,19,16,v) |
| #define GET16ticOp2_sCtl_3i(r16) _BFGET_(r16, 3, 0) |
| #define SET16ticOp2_sCtl_3i(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32ticOp2_sLatch_0i(r32) _BFGET_(r32,21,20) |
| #define SET32ticOp2_sLatch_0i(r32,v) _BFSET_(r32,21,20,v) |
| #define GET16ticOp2_sLatch_0i(r16) _BFGET_(r16, 5, 4) |
| #define SET16ticOp2_sLatch_0i(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| #define GET32ticOp2_sLatch_1i(r32) _BFGET_(r32,23,22) |
| #define SET32ticOp2_sLatch_1i(r32,v) _BFSET_(r32,23,22,v) |
| #define GET16ticOp2_sLatch_1i(r16) _BFGET_(r16, 7, 6) |
| #define SET16ticOp2_sLatch_1i(r16,v) _BFSET_(r16, 7, 6,v) |
| |
| #define GET32ticOp2_sum_0i(r32) _BFGET_(r32,27,24) |
| #define SET32ticOp2_sum_0i(r32,v) _BFSET_(r32,27,24,v) |
| #define GET16ticOp2_sum_0i(r16) _BFGET_(r16,11, 8) |
| #define SET16ticOp2_sum_0i(r16,v) _BFSET_(r16,11, 8,v) |
| |
| #define GET32ticOp2_sum_1i(r32) _BFGET_(r32,31,28) |
| #define SET32ticOp2_sum_1i(r32,v) _BFSET_(r32,31,28,v) |
| #define GET16ticOp2_sum_1i(r16) _BFGET_(r16,15,12) |
| #define SET16ticOp2_sum_1i(r16,v) _BFSET_(r16,15,12,v) |
| |
| UNSG32 u_mLatch_0i : 1; |
| UNSG32 u_mLatch_1i : 1; |
| UNSG32 u_xmul : 2; |
| UNSG32 s_sCtl_0i : 4; |
| UNSG32 s_sCtl_1i : 4; |
| UNSG32 s_sCtl_2i : 4; |
| UNSG32 s_sCtl_3i : 4; |
| UNSG32 u_sLatch_0i : 2; |
| UNSG32 u_sLatch_1i : 2; |
| UNSG32 u_sum_0i : 4; |
| UNSG32 u_sum_1i : 4; |
| /////////////////////////////////////////////////////////// |
| |
| #define GET32ticOp2_accSel_0i(r32) _BFGET_(r32, 1, 0) |
| #define SET32ticOp2_accSel_0i(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16ticOp2_accSel_0i(r16) _BFGET_(r16, 1, 0) |
| #define SET16ticOp2_accSel_0i(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32ticOp2_accSel_1i(r32) _BFGET_(r32, 3, 2) |
| #define SET32ticOp2_accSel_1i(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16ticOp2_accSel_1i(r16) _BFGET_(r16, 3, 2) |
| #define SET16ticOp2_accSel_1i(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32ticOp2_acc_0i(r32) _BFGET_(r32, 6, 4) |
| #define SET32ticOp2_acc_0i(r32,v) _BFSET_(r32, 6, 4,v) |
| #define GET16ticOp2_acc_0i(r16) _BFGET_(r16, 6, 4) |
| #define SET16ticOp2_acc_0i(r16,v) _BFSET_(r16, 6, 4,v) |
| |
| #define GET32ticOp2_acc_1i(r32) _BFGET_(r32, 9, 7) |
| #define SET32ticOp2_acc_1i(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16ticOp2_acc_1i(r16) _BFGET_(r16, 9, 7) |
| #define SET16ticOp2_acc_1i(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define GET32ticOp2_desIn(r32) _BFGET_(r32,11,10) |
| #define SET32ticOp2_desIn(r32,v) _BFSET_(r32,11,10,v) |
| #define GET16ticOp2_desIn(r16) _BFGET_(r16,11,10) |
| #define SET16ticOp2_desIn(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32ticOp2_des(r32) _BFGET_(r32,15,12) |
| #define SET32ticOp2_des(r32,v) _BFSET_(r32,15,12,v) |
| #define GET16ticOp2_des(r16) _BFGET_(r16,15,12) |
| #define SET16ticOp2_des(r16,v) _BFSET_(r16,15,12,v) |
| |
| #define GET32ticOp2_clip(r32) _BFGET_(r32,16,16) |
| #define SET32ticOp2_clip(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16ticOp2_clip(r16) _BFGET_(r16, 0, 0) |
| #define SET16ticOp2_clip(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32ticOp2_wp(r32) _BFGET_(r32,21,17) |
| #define SET32ticOp2_wp(r32,v) _BFSET_(r32,21,17,v) |
| #define GET16ticOp2_wp(r16) _BFGET_(r16, 5, 1) |
| #define SET16ticOp2_wp(r16,v) _BFSET_(r16, 5, 1,v) |
| |
| #define GET32ticOp2_wCtl(r32) _BFGET_(r32,24,22) |
| #define SET32ticOp2_wCtl(r32,v) _BFSET_(r32,24,22,v) |
| #define GET16ticOp2_wCtl(r16) _BFGET_(r16, 8, 6) |
| #define SET16ticOp2_wCtl(r16,v) _BFSET_(r16, 8, 6,v) |
| |
| #define GET32ticOp2_xshift(r32) _BFGET_(r32,27,25) |
| #define SET32ticOp2_xshift(r32,v) _BFSET_(r32,27,25,v) |
| #define GET16ticOp2_xshift(r16) _BFGET_(r16,11, 9) |
| #define SET16ticOp2_xshift(r16,v) _BFSET_(r16,11, 9,v) |
| |
| #define GET32ticOp2_xdesInSelMode(r32) _BFGET_(r32,29,28) |
| #define SET32ticOp2_xdesInSelMode(r32,v) _BFSET_(r32,29,28,v) |
| #define GET16ticOp2_xdesInSelMode(r16) _BFGET_(r16,13,12) |
| #define SET16ticOp2_xdesInSelMode(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32ticOp2_zero_extension(r32) _BFGET_(r32,30,30) |
| #define SET32ticOp2_zero_extension(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16ticOp2_zero_extension(r16) _BFGET_(r16,14,14) |
| #define SET16ticOp2_zero_extension(r16,v) _BFSET_(r16,14,14,v) |
| |
| UNSG32 u_accSel_0i : 2; |
| UNSG32 u_accSel_1i : 2; |
| UNSG32 u_acc_0i : 3; |
| UNSG32 u_acc_1i : 3; |
| UNSG32 u_desIn : 2; |
| UNSG32 u_des : 4; |
| UNSG32 u_clip : 1; |
| UNSG32 u_wp : 5; |
| UNSG32 u_wCtl : 3; |
| UNSG32 u_xshift : 3; |
| UNSG32 u_xdesInSelMode : 2; |
| UNSG32 u_zero_extension : 1; |
| UNSG32 RSVDx8_b31 : 1; |
| /////////////////////////////////////////////////////////// |
| } SIE_ticOp2; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ticOp2_drvrd(SIE_ticOp2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ticOp2_drvwr(SIE_ticOp2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ticOp2_reset(SIE_ticOp2 *p); |
| SIGN32 ticOp2_cmp (SIE_ticOp2 *p, SIE_ticOp2 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ticOp2_check(p,pie,pfx,hLOG) ticOp2_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ticOp2_print(p, pfx,hLOG) ticOp2_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ticOp2 |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3OpTbl (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 tbl |
| /// $P3OpTblEntry tbl REG [512] |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8192B, bits: 56320b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3OpTbl |
| #define h_P3OpTbl (){} |
| |
| #define RA_P3OpTbl_tbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3OpTbl { |
| /////////////////////////////////////////////////////////// |
| SIE_P3OpTblEntry ie_tbl[512]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3OpTbl; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3OpTbl_drvrd(SIE_P3OpTbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3OpTbl_drvwr(SIE_P3OpTbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3OpTbl_reset(SIE_P3OpTbl *p); |
| SIGN32 P3OpTbl_cmp (SIE_P3OpTbl *p, SIE_P3OpTbl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3OpTbl_check(p,pie,pfx,hLOG) P3OpTbl_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3OpTbl_print(p, pfx,hLOG) P3OpTbl_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3OpTbl |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3ticEx (4,4) |
| /// # # ---------------------------------------------------------- |
| /// : RegBase 0x6000 |
| /// @ 0x00000 OPTBL (P) |
| /// # 0x00000 optbl |
| /// $P3OpTbl optbl MEM |
| /// @ 0x02000 (W-) |
| /// # # Stuffing bytes... |
| /// %% 131072 |
| /// @ 0x06000 DBLK (P) |
| /// ### |
| /// * DBLK extension configuration |
| /// ### |
| /// %unsigned 4 fmt 0x0 |
| /// : na 0x0 |
| /// : h264 0x1 |
| /// : v9 0x2 |
| /// : avs 0x3 |
| /// : rv9 0x4 |
| /// : vp8 0x5 |
| /// ### |
| /// * DBLK format |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x06004 (W-) |
| /// # # Stuffing bytes... |
| /// %% 65504 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 32768B, bits: 36b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3ticEx |
| #define h_P3ticEx (){} |
| |
| #define P3ticEx_RegBase 0x6000 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3ticEx_OPTBL 0x0000 |
| #define RA_P3ticEx_optbl 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3ticEx_DBLK 0x6000 |
| |
| #define BA_P3ticEx_DBLK_fmt 0x6000 |
| #define B16P3ticEx_DBLK_fmt 0x6000 |
| #define LSb32P3ticEx_DBLK_fmt 0 |
| #define LSb16P3ticEx_DBLK_fmt 0 |
| #define bP3ticEx_DBLK_fmt 4 |
| #define MSK32P3ticEx_DBLK_fmt 0x0000000F |
| #define P3ticEx_DBLK_fmt_na 0x0 |
| #define P3ticEx_DBLK_fmt_h264 0x1 |
| #define P3ticEx_DBLK_fmt_v9 0x2 |
| #define P3ticEx_DBLK_fmt_avs 0x3 |
| #define P3ticEx_DBLK_fmt_rv9 0x4 |
| #define P3ticEx_DBLK_fmt_vp8 0x5 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3ticEx { |
| /////////////////////////////////////////////////////////// |
| SIE_P3OpTbl ie_optbl; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx2000 [16384]; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3ticEx_DBLK_fmt(r32) _BFGET_(r32, 3, 0) |
| #define SET32P3ticEx_DBLK_fmt(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16P3ticEx_DBLK_fmt(r16) _BFGET_(r16, 3, 0) |
| #define SET16P3ticEx_DBLK_fmt(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define w32P3ticEx_DBLK {\ |
| UNSG32 uDBLK_fmt : 4;\ |
| UNSG32 RSVDx6000_b4 : 28;\ |
| } |
| union { UNSG32 u32P3ticEx_DBLK; |
| struct w32P3ticEx_DBLK; |
| }; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx6004 [8188]; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3ticEx; |
| |
| typedef union T32P3ticEx_DBLK |
| { UNSG32 u32; |
| struct w32P3ticEx_DBLK; |
| } T32P3ticEx_DBLK; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TP3ticEx_DBLK |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3ticEx_DBLK; |
| }; |
| } TP3ticEx_DBLK; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3ticEx_drvrd(SIE_P3ticEx *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3ticEx_drvwr(SIE_P3ticEx *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3ticEx_reset(SIE_P3ticEx *p); |
| SIGN32 P3ticEx_cmp (SIE_P3ticEx *p, SIE_P3ticEx *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3ticEx_check(p,pie,pfx,hLOG) P3ticEx_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3ticEx_print(p, pfx,hLOG) P3ticEx_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3ticEx |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3EPTRMap (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 16 byte |
| /// ### |
| /// * Each channel has 64KByte space. |
| /// ### |
| /// %unsigned 11 CH |
| /// : DMEM 0x0 |
| /// ### |
| /// * Global Channel ID under a particular device. Refer the definition from GaloisDmaMap.sxw.txt.txt. |
| /// ### |
| /// %unsigned 3 DEV |
| /// : DEV 0x0 |
| /// : FUN 0x1 |
| /// ### |
| /// * Used to select a particular device. |
| /// * 000: DMA/HBO/ |
| /// * 001: Functional address. |
| /// * 01x: video formatter |
| /// * 1xx: DDR |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 30b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3EPTRMap |
| #define h_P3EPTRMap (){} |
| |
| #define BA_P3EPTRMap_byte 0x0000 |
| #define B16P3EPTRMap_byte 0x0000 |
| #define LSb32P3EPTRMap_byte 0 |
| #define LSb16P3EPTRMap_byte 0 |
| #define bP3EPTRMap_byte 16 |
| #define MSK32P3EPTRMap_byte 0x0000FFFF |
| |
| #define BA_P3EPTRMap_CH 0x0002 |
| #define B16P3EPTRMap_CH 0x0002 |
| #define LSb32P3EPTRMap_CH 16 |
| #define LSb16P3EPTRMap_CH 0 |
| #define bP3EPTRMap_CH 11 |
| #define MSK32P3EPTRMap_CH 0x07FF0000 |
| #define P3EPTRMap_CH_DMEM 0x0 |
| |
| #define BA_P3EPTRMap_DEV 0x0003 |
| #define B16P3EPTRMap_DEV 0x0002 |
| #define LSb32P3EPTRMap_DEV 27 |
| #define LSb16P3EPTRMap_DEV 11 |
| #define bP3EPTRMap_DEV 3 |
| #define MSK32P3EPTRMap_DEV 0x38000000 |
| #define P3EPTRMap_DEV_DEV 0x0 |
| #define P3EPTRMap_DEV_FUN 0x1 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3EPTRMap { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3EPTRMap_byte(r32) _BFGET_(r32,15, 0) |
| #define SET32P3EPTRMap_byte(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16P3EPTRMap_byte(r16) _BFGET_(r16,15, 0) |
| #define SET16P3EPTRMap_byte(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32P3EPTRMap_CH(r32) _BFGET_(r32,26,16) |
| #define SET32P3EPTRMap_CH(r32,v) _BFSET_(r32,26,16,v) |
| #define GET16P3EPTRMap_CH(r16) _BFGET_(r16,10, 0) |
| #define SET16P3EPTRMap_CH(r16,v) _BFSET_(r16,10, 0,v) |
| |
| #define GET32P3EPTRMap_DEV(r32) _BFGET_(r32,29,27) |
| #define SET32P3EPTRMap_DEV(r32,v) _BFSET_(r32,29,27,v) |
| #define GET16P3EPTRMap_DEV(r16) _BFGET_(r16,13,11) |
| #define SET16P3EPTRMap_DEV(r16,v) _BFSET_(r16,13,11,v) |
| |
| UNSG32 u_byte : 16; |
| UNSG32 u_CH : 11; |
| UNSG32 u_DEV : 3; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3EPTRMap; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3EPTRMap_drvrd(SIE_P3EPTRMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3EPTRMap_drvwr(SIE_P3EPTRMap *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3EPTRMap_reset(SIE_P3EPTRMap *p); |
| SIGN32 P3EPTRMap_cmp (SIE_P3EPTRMap *p, SIE_P3EPTRMap *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3EPTRMap_check(p,pie,pfx,hLOG) P3EPTRMap_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3EPTRMap_print(p, pfx,hLOG) P3EPTRMap_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3EPTRMap |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3vFmtADDR (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// %unsigned 2 byte |
| /// ### |
| /// * Byte address in a word |
| /// ### |
| /// %unsigned 2 word |
| /// : dsample 0x0 |
| /// : uyvy 0x1 |
| /// : luma 0x2 |
| /// : chroma 0x3 |
| /// ### |
| /// * Word address in a 16B DMEM entry |
| /// ### |
| /// %unsigned 8 x16B |
| /// ### |
| /// * DMEM quad-word (16B) address offset |
| /// ### |
| /// %unsigned 8 xLocMB |
| /// ### |
| /// * Base horizontal MB location |
| /// ### |
| /// %unsigned 8 yLocMB |
| /// ### |
| /// * Base vertical MB location |
| /// ### |
| /// %unsigned 2 mode |
| /// : device 0x0 |
| /// : vfmt 0x1 |
| /// : bypass 0x2 |
| /// : np_vfmt 0x3 |
| /// : vfmt_1 0x3 |
| /// ### |
| /// * LSb used to indicate device or vfmt mode |
| /// * Otherwise (MSB=1) bypass mode |
| /// * Non-posted mode is replaced by NP_CFG. When output address is in the range of NP_CFG, it will generate an interrupt. |
| /// * When mode is set to vfmt_1, the address/stride register set with suffix “_1” should be used. |
| /// ### |
| /// %% 2 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 30b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3vFmtADDR |
| #define h_P3vFmtADDR (){} |
| |
| #define BA_P3vFmtADDR_byte 0x0000 |
| #define B16P3vFmtADDR_byte 0x0000 |
| #define LSb32P3vFmtADDR_byte 0 |
| #define LSb16P3vFmtADDR_byte 0 |
| #define bP3vFmtADDR_byte 2 |
| #define MSK32P3vFmtADDR_byte 0x00000003 |
| |
| #define BA_P3vFmtADDR_word 0x0000 |
| #define B16P3vFmtADDR_word 0x0000 |
| #define LSb32P3vFmtADDR_word 2 |
| #define LSb16P3vFmtADDR_word 2 |
| #define bP3vFmtADDR_word 2 |
| #define MSK32P3vFmtADDR_word 0x0000000C |
| #define P3vFmtADDR_word_dsample 0x0 |
| #define P3vFmtADDR_word_uyvy 0x1 |
| #define P3vFmtADDR_word_luma 0x2 |
| #define P3vFmtADDR_word_chroma 0x3 |
| |
| #define BA_P3vFmtADDR_x16B 0x0000 |
| #define B16P3vFmtADDR_x16B 0x0000 |
| #define LSb32P3vFmtADDR_x16B 4 |
| #define LSb16P3vFmtADDR_x16B 4 |
| #define bP3vFmtADDR_x16B 8 |
| #define MSK32P3vFmtADDR_x16B 0x00000FF0 |
| |
| #define BA_P3vFmtADDR_xLocMB 0x0001 |
| #define B16P3vFmtADDR_xLocMB 0x0000 |
| #define LSb32P3vFmtADDR_xLocMB 12 |
| #define LSb16P3vFmtADDR_xLocMB 12 |
| #define bP3vFmtADDR_xLocMB 8 |
| #define MSK32P3vFmtADDR_xLocMB 0x000FF000 |
| |
| #define BA_P3vFmtADDR_yLocMB 0x0002 |
| #define B16P3vFmtADDR_yLocMB 0x0002 |
| #define LSb32P3vFmtADDR_yLocMB 20 |
| #define LSb16P3vFmtADDR_yLocMB 4 |
| #define bP3vFmtADDR_yLocMB 8 |
| #define MSK32P3vFmtADDR_yLocMB 0x0FF00000 |
| |
| #define BA_P3vFmtADDR_mode 0x0003 |
| #define B16P3vFmtADDR_mode 0x0002 |
| #define LSb32P3vFmtADDR_mode 28 |
| #define LSb16P3vFmtADDR_mode 12 |
| #define bP3vFmtADDR_mode 2 |
| #define MSK32P3vFmtADDR_mode 0x30000000 |
| #define P3vFmtADDR_mode_device 0x0 |
| #define P3vFmtADDR_mode_vfmt 0x1 |
| #define P3vFmtADDR_mode_bypass 0x2 |
| #define P3vFmtADDR_mode_np_vfmt 0x3 |
| #define P3vFmtADDR_mode_vfmt_1 0x3 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3vFmtADDR { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmtADDR_byte(r32) _BFGET_(r32, 1, 0) |
| #define SET32P3vFmtADDR_byte(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16P3vFmtADDR_byte(r16) _BFGET_(r16, 1, 0) |
| #define SET16P3vFmtADDR_byte(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32P3vFmtADDR_word(r32) _BFGET_(r32, 3, 2) |
| #define SET32P3vFmtADDR_word(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16P3vFmtADDR_word(r16) _BFGET_(r16, 3, 2) |
| #define SET16P3vFmtADDR_word(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32P3vFmtADDR_x16B(r32) _BFGET_(r32,11, 4) |
| #define SET32P3vFmtADDR_x16B(r32,v) _BFSET_(r32,11, 4,v) |
| #define GET16P3vFmtADDR_x16B(r16) _BFGET_(r16,11, 4) |
| #define SET16P3vFmtADDR_x16B(r16,v) _BFSET_(r16,11, 4,v) |
| |
| #define GET32P3vFmtADDR_xLocMB(r32) _BFGET_(r32,19,12) |
| #define SET32P3vFmtADDR_xLocMB(r32,v) _BFSET_(r32,19,12,v) |
| |
| #define GET32P3vFmtADDR_yLocMB(r32) _BFGET_(r32,27,20) |
| #define SET32P3vFmtADDR_yLocMB(r32,v) _BFSET_(r32,27,20,v) |
| #define GET16P3vFmtADDR_yLocMB(r16) _BFGET_(r16,11, 4) |
| #define SET16P3vFmtADDR_yLocMB(r16,v) _BFSET_(r16,11, 4,v) |
| |
| #define GET32P3vFmtADDR_mode(r32) _BFGET_(r32,29,28) |
| #define SET32P3vFmtADDR_mode(r32,v) _BFSET_(r32,29,28,v) |
| #define GET16P3vFmtADDR_mode(r16) _BFGET_(r16,13,12) |
| #define SET16P3vFmtADDR_mode(r16,v) _BFSET_(r16,13,12,v) |
| |
| UNSG32 u_byte : 2; |
| UNSG32 u_word : 2; |
| UNSG32 u_x16B : 8; |
| UNSG32 u_xLocMB : 8; |
| UNSG32 u_yLocMB : 8; |
| UNSG32 u_mode : 2; |
| UNSG32 RSVDx0_b30 : 2; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3vFmtADDR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3vFmtADDR_drvrd(SIE_P3vFmtADDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3vFmtADDR_drvwr(SIE_P3vFmtADDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3vFmtADDR_reset(SIE_P3vFmtADDR *p); |
| SIGN32 P3vFmtADDR_cmp (SIE_P3vFmtADDR *p, SIE_P3vFmtADDR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3vFmtADDR_check(p,pie,pfx,hLOG) P3vFmtADDR_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3vFmtADDR_print(p, pfx,hLOG) P3vFmtADDR_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3vFmtADDR |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3vFmt biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CFG (P) |
| /// %unsigned 2 scan |
| /// : Prog 0x0 |
| /// : Top 0x1 |
| /// : Bottom 0x2 |
| /// : WeavedFrm 0x3 |
| /// ### |
| /// * Picture scan mode |
| /// ### |
| /// %unsigned 1 rangeMapYflag 0x0 |
| /// ### |
| /// * Range mapping is on for Luma of current picture |
| /// ### |
| /// %unsigned 3 rangeMapY 0x0 |
| /// ### |
| /// * Range mapping scaling factor for Luma |
| /// ### |
| /// %unsigned 1 rangeMapUVflag 0x0 |
| /// ### |
| /// * Range mapping is on for Chroma of current picture |
| /// ### |
| /// %unsigned 3 rangeMapUV 0x0 |
| /// ### |
| /// * Range mapping scaling factor for Chroma |
| /// ### |
| /// %unsigned 1 rangeRed 0x0 |
| /// ### |
| /// * range reduction is on for current picture |
| /// ### |
| /// %unsigned 1 tileMode |
| /// : TBTB 0x0 |
| /// : TTBB2TBTB 0x1 |
| /// ### |
| /// * Tile conversion modes for luma & chroma |
| /// ### |
| /// %% 20 # Stuffing bits... |
| /// @ 0x00004 UYVY (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt mode DDR base address for 422 output |
| /// ### |
| /// @ 0x00008 LUMA (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt mode DDR base address for tiled luma output |
| /// ### |
| /// @ 0x0000C CHROMA (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt mode DDR base address for tiled chroma output |
| /// ### |
| /// @ 0x00010 DSAMPLE (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * DDR base address for tiled down-sampled output |
| /// ### |
| /// @ 0x00014 BYPASS (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt mode DDR base address for bypass mode |
| /// ### |
| /// @ 0x00018 STRIDE (P) |
| /// %unsigned 8 tiledPage |
| /// ### |
| /// * vfmt mode 4KB page count of luma/chorma buffer stride |
| /// ### |
| /// %unsigned 8 tiledDSPage |
| /// ### |
| /// * vfmt mode 4KB page count of down sampled buffer stride |
| /// ### |
| /// %unsigned 10 422Line |
| /// ### |
| /// * vfmt mode 32-byte word count of 422 output line stride. |
| /// ### |
| /// %% 6 # Stuffing bits... |
| /// @ 0x0001C UYVY_1 (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt_1 mode DDR base address for 422 output |
| /// ### |
| /// @ 0x00020 LUMA_1 (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt_1 mode DDR base address for tiled luma output |
| /// ### |
| /// @ 0x00024 CHROMA_1 (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt_1 mode DDR base address for tiled chroma output |
| /// ### |
| /// @ 0x00028 DSAMPLE_1 (P) |
| /// %unsigned 32 base |
| /// ### |
| /// * vfmt_1 mode DDR base address for tiled down-sampled output |
| /// ### |
| /// @ 0x0002C STRIDE_1 (P) |
| /// %unsigned 8 422Line |
| /// ### |
| /// * vfmt_1 mode 32-byte word count of 422 output line stride |
| /// ### |
| /// %unsigned 8 tiledPage |
| /// ### |
| /// * vfmt_1 mode 4KB page count of luma/chorma buffer stride |
| /// ### |
| /// %unsigned 8 tiledDSPage |
| /// ### |
| /// * vfmt_1 mode 4KB page count of down sampled buffer stride |
| /// ### |
| /// %% 8 # Stuffing bits... |
| /// @ 0x00030 NP_CFG (P) |
| /// %unsigned 32 minAddr 0x0 |
| /// # 0x00034 NP_CFG1 |
| /// %unsigned 32 maxAddr 0x0 |
| /// ### |
| /// * When the output address is in this range (>= minAddr and < maxAddr), the transaction should generate an interrupt. |
| /// ### |
| /// @ 0x00038 ADDR (R-) |
| /// %unsigned 32 sum |
| /// ### |
| /// * Vfmt outupt address check sum |
| /// ### |
| /// @ 0x0003C DAT (R-) |
| /// %unsigned 32 sum_0i |
| /// # 0x00040 DAT1 |
| /// %unsigned 32 sum_1i |
| /// # 0x00044 DAT2 |
| /// %unsigned 32 sum_2i |
| /// # 0x00048 DAT3 |
| /// %unsigned 32 sum_3i |
| /// # 0x0004C DAT4 |
| /// %unsigned 32 sum_4i |
| /// # 0x00050 DAT5 |
| /// %unsigned 32 sum_5i |
| /// # 0x00054 DAT6 |
| /// %unsigned 32 sum_6i |
| /// # 0x00058 DAT7 |
| /// %unsigned 32 sum_7i |
| /// ### |
| /// * Vfmt outupt data check sum, each 8-bit stream has 32-bit checksum. |
| /// ### |
| /// @ 0x0005C CHKEN (P) |
| /// %unsigned 1 bypass 0x0 |
| /// ### |
| /// * Write 1 to enable VFMT bypass mode check sum. |
| /// ### |
| /// %unsigned 1 display 0x0 |
| /// %unsigned 1 ref 0x0 |
| /// ### |
| /// * Write 1 to enable VFMT reference data check sum. |
| /// ### |
| /// %% 29 # Stuffing bits... |
| /// @ 0x00060 CLR (W-) |
| /// %unsigned 1 sumAddr |
| /// %unsigned 1 sumDat |
| /// ### |
| /// * Write '1' to the bit field to clear the corresponding checksum to 0. Only the write pulse take effect, the register value is not used to do anything. |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 100B, bits: 707b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3vFmt |
| #define h_P3vFmt (){} |
| |
| #define RA_P3vFmt_CFG 0x0000 |
| |
| #define BA_P3vFmt_CFG_scan 0x0000 |
| #define B16P3vFmt_CFG_scan 0x0000 |
| #define LSb32P3vFmt_CFG_scan 0 |
| #define LSb16P3vFmt_CFG_scan 0 |
| #define bP3vFmt_CFG_scan 2 |
| #define MSK32P3vFmt_CFG_scan 0x00000003 |
| #define P3vFmt_CFG_scan_Prog 0x0 |
| #define P3vFmt_CFG_scan_Top 0x1 |
| #define P3vFmt_CFG_scan_Bottom 0x2 |
| #define P3vFmt_CFG_scan_WeavedFrm 0x3 |
| |
| #define BA_P3vFmt_CFG_rangeMapYflag 0x0000 |
| #define B16P3vFmt_CFG_rangeMapYflag 0x0000 |
| #define LSb32P3vFmt_CFG_rangeMapYflag 2 |
| #define LSb16P3vFmt_CFG_rangeMapYflag 2 |
| #define bP3vFmt_CFG_rangeMapYflag 1 |
| #define MSK32P3vFmt_CFG_rangeMapYflag 0x00000004 |
| |
| #define BA_P3vFmt_CFG_rangeMapY 0x0000 |
| #define B16P3vFmt_CFG_rangeMapY 0x0000 |
| #define LSb32P3vFmt_CFG_rangeMapY 3 |
| #define LSb16P3vFmt_CFG_rangeMapY 3 |
| #define bP3vFmt_CFG_rangeMapY 3 |
| #define MSK32P3vFmt_CFG_rangeMapY 0x00000038 |
| |
| #define BA_P3vFmt_CFG_rangeMapUVflag 0x0000 |
| #define B16P3vFmt_CFG_rangeMapUVflag 0x0000 |
| #define LSb32P3vFmt_CFG_rangeMapUVflag 6 |
| #define LSb16P3vFmt_CFG_rangeMapUVflag 6 |
| #define bP3vFmt_CFG_rangeMapUVflag 1 |
| #define MSK32P3vFmt_CFG_rangeMapUVflag 0x00000040 |
| |
| #define BA_P3vFmt_CFG_rangeMapUV 0x0000 |
| #define B16P3vFmt_CFG_rangeMapUV 0x0000 |
| #define LSb32P3vFmt_CFG_rangeMapUV 7 |
| #define LSb16P3vFmt_CFG_rangeMapUV 7 |
| #define bP3vFmt_CFG_rangeMapUV 3 |
| #define MSK32P3vFmt_CFG_rangeMapUV 0x00000380 |
| |
| #define BA_P3vFmt_CFG_rangeRed 0x0001 |
| #define B16P3vFmt_CFG_rangeRed 0x0000 |
| #define LSb32P3vFmt_CFG_rangeRed 10 |
| #define LSb16P3vFmt_CFG_rangeRed 10 |
| #define bP3vFmt_CFG_rangeRed 1 |
| #define MSK32P3vFmt_CFG_rangeRed 0x00000400 |
| |
| #define BA_P3vFmt_CFG_tileMode 0x0001 |
| #define B16P3vFmt_CFG_tileMode 0x0000 |
| #define LSb32P3vFmt_CFG_tileMode 11 |
| #define LSb16P3vFmt_CFG_tileMode 11 |
| #define bP3vFmt_CFG_tileMode 1 |
| #define MSK32P3vFmt_CFG_tileMode 0x00000800 |
| #define P3vFmt_CFG_tileMode_TBTB 0x0 |
| #define P3vFmt_CFG_tileMode_TTBB2TBTB 0x1 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_UYVY 0x0004 |
| |
| #define BA_P3vFmt_UYVY_base 0x0004 |
| #define B16P3vFmt_UYVY_base 0x0004 |
| #define LSb32P3vFmt_UYVY_base 0 |
| #define LSb16P3vFmt_UYVY_base 0 |
| #define bP3vFmt_UYVY_base 32 |
| #define MSK32P3vFmt_UYVY_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_LUMA 0x0008 |
| |
| #define BA_P3vFmt_LUMA_base 0x0008 |
| #define B16P3vFmt_LUMA_base 0x0008 |
| #define LSb32P3vFmt_LUMA_base 0 |
| #define LSb16P3vFmt_LUMA_base 0 |
| #define bP3vFmt_LUMA_base 32 |
| #define MSK32P3vFmt_LUMA_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_CHROMA 0x000C |
| |
| #define BA_P3vFmt_CHROMA_base 0x000C |
| #define B16P3vFmt_CHROMA_base 0x000C |
| #define LSb32P3vFmt_CHROMA_base 0 |
| #define LSb16P3vFmt_CHROMA_base 0 |
| #define bP3vFmt_CHROMA_base 32 |
| #define MSK32P3vFmt_CHROMA_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_DSAMPLE 0x0010 |
| |
| #define BA_P3vFmt_DSAMPLE_base 0x0010 |
| #define B16P3vFmt_DSAMPLE_base 0x0010 |
| #define LSb32P3vFmt_DSAMPLE_base 0 |
| #define LSb16P3vFmt_DSAMPLE_base 0 |
| #define bP3vFmt_DSAMPLE_base 32 |
| #define MSK32P3vFmt_DSAMPLE_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_BYPASS 0x0014 |
| |
| #define BA_P3vFmt_BYPASS_base 0x0014 |
| #define B16P3vFmt_BYPASS_base 0x0014 |
| #define LSb32P3vFmt_BYPASS_base 0 |
| #define LSb16P3vFmt_BYPASS_base 0 |
| #define bP3vFmt_BYPASS_base 32 |
| #define MSK32P3vFmt_BYPASS_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_STRIDE 0x0018 |
| |
| #define BA_P3vFmt_STRIDE_tiledPage 0x0018 |
| #define B16P3vFmt_STRIDE_tiledPage 0x0018 |
| #define LSb32P3vFmt_STRIDE_tiledPage 0 |
| #define LSb16P3vFmt_STRIDE_tiledPage 0 |
| #define bP3vFmt_STRIDE_tiledPage 8 |
| #define MSK32P3vFmt_STRIDE_tiledPage 0x000000FF |
| |
| #define BA_P3vFmt_STRIDE_tiledDSPage 0x0019 |
| #define B16P3vFmt_STRIDE_tiledDSPage 0x0018 |
| #define LSb32P3vFmt_STRIDE_tiledDSPage 8 |
| #define LSb16P3vFmt_STRIDE_tiledDSPage 8 |
| #define bP3vFmt_STRIDE_tiledDSPage 8 |
| #define MSK32P3vFmt_STRIDE_tiledDSPage 0x0000FF00 |
| |
| #define BA_P3vFmt_STRIDE_422Line 0x001A |
| #define B16P3vFmt_STRIDE_422Line 0x001A |
| #define LSb32P3vFmt_STRIDE_422Line 16 |
| #define LSb16P3vFmt_STRIDE_422Line 0 |
| #define bP3vFmt_STRIDE_422Line 10 |
| #define MSK32P3vFmt_STRIDE_422Line 0x03FF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_UYVY_1 0x001C |
| |
| #define BA_P3vFmt_UYVY_1_base 0x001C |
| #define B16P3vFmt_UYVY_1_base 0x001C |
| #define LSb32P3vFmt_UYVY_1_base 0 |
| #define LSb16P3vFmt_UYVY_1_base 0 |
| #define bP3vFmt_UYVY_1_base 32 |
| #define MSK32P3vFmt_UYVY_1_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_LUMA_1 0x0020 |
| |
| #define BA_P3vFmt_LUMA_1_base 0x0020 |
| #define B16P3vFmt_LUMA_1_base 0x0020 |
| #define LSb32P3vFmt_LUMA_1_base 0 |
| #define LSb16P3vFmt_LUMA_1_base 0 |
| #define bP3vFmt_LUMA_1_base 32 |
| #define MSK32P3vFmt_LUMA_1_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_CHROMA_1 0x0024 |
| |
| #define BA_P3vFmt_CHROMA_1_base 0x0024 |
| #define B16P3vFmt_CHROMA_1_base 0x0024 |
| #define LSb32P3vFmt_CHROMA_1_base 0 |
| #define LSb16P3vFmt_CHROMA_1_base 0 |
| #define bP3vFmt_CHROMA_1_base 32 |
| #define MSK32P3vFmt_CHROMA_1_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_DSAMPLE_1 0x0028 |
| |
| #define BA_P3vFmt_DSAMPLE_1_base 0x0028 |
| #define B16P3vFmt_DSAMPLE_1_base 0x0028 |
| #define LSb32P3vFmt_DSAMPLE_1_base 0 |
| #define LSb16P3vFmt_DSAMPLE_1_base 0 |
| #define bP3vFmt_DSAMPLE_1_base 32 |
| #define MSK32P3vFmt_DSAMPLE_1_base 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_STRIDE_1 0x002C |
| |
| #define BA_P3vFmt_STRIDE_1_422Line 0x002C |
| #define B16P3vFmt_STRIDE_1_422Line 0x002C |
| #define LSb32P3vFmt_STRIDE_1_422Line 0 |
| #define LSb16P3vFmt_STRIDE_1_422Line 0 |
| #define bP3vFmt_STRIDE_1_422Line 8 |
| #define MSK32P3vFmt_STRIDE_1_422Line 0x000000FF |
| |
| #define BA_P3vFmt_STRIDE_1_tiledPage 0x002D |
| #define B16P3vFmt_STRIDE_1_tiledPage 0x002C |
| #define LSb32P3vFmt_STRIDE_1_tiledPage 8 |
| #define LSb16P3vFmt_STRIDE_1_tiledPage 8 |
| #define bP3vFmt_STRIDE_1_tiledPage 8 |
| #define MSK32P3vFmt_STRIDE_1_tiledPage 0x0000FF00 |
| |
| #define BA_P3vFmt_STRIDE_1_tiledDSPage 0x002E |
| #define B16P3vFmt_STRIDE_1_tiledDSPage 0x002E |
| #define LSb32P3vFmt_STRIDE_1_tiledDSPage 16 |
| #define LSb16P3vFmt_STRIDE_1_tiledDSPage 0 |
| #define bP3vFmt_STRIDE_1_tiledDSPage 8 |
| #define MSK32P3vFmt_STRIDE_1_tiledDSPage 0x00FF0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_NP_CFG 0x0030 |
| |
| #define BA_P3vFmt_NP_CFG_minAddr 0x0030 |
| #define B16P3vFmt_NP_CFG_minAddr 0x0030 |
| #define LSb32P3vFmt_NP_CFG_minAddr 0 |
| #define LSb16P3vFmt_NP_CFG_minAddr 0 |
| #define bP3vFmt_NP_CFG_minAddr 32 |
| #define MSK32P3vFmt_NP_CFG_minAddr 0xFFFFFFFF |
| |
| #define RA_P3vFmt_NP_CFG1 0x0034 |
| |
| #define BA_P3vFmt_NP_CFG_maxAddr 0x0034 |
| #define B16P3vFmt_NP_CFG_maxAddr 0x0034 |
| #define LSb32P3vFmt_NP_CFG_maxAddr 0 |
| #define LSb16P3vFmt_NP_CFG_maxAddr 0 |
| #define bP3vFmt_NP_CFG_maxAddr 32 |
| #define MSK32P3vFmt_NP_CFG_maxAddr 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_ADDR 0x0038 |
| |
| #define BA_P3vFmt_ADDR_sum 0x0038 |
| #define B16P3vFmt_ADDR_sum 0x0038 |
| #define LSb32P3vFmt_ADDR_sum 0 |
| #define LSb16P3vFmt_ADDR_sum 0 |
| #define bP3vFmt_ADDR_sum 32 |
| #define MSK32P3vFmt_ADDR_sum 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_DAT 0x003C |
| |
| #define BA_P3vFmt_DAT_sum_0i 0x003C |
| #define B16P3vFmt_DAT_sum_0i 0x003C |
| #define LSb32P3vFmt_DAT_sum_0i 0 |
| #define LSb16P3vFmt_DAT_sum_0i 0 |
| #define bP3vFmt_DAT_sum_0i 32 |
| #define MSK32P3vFmt_DAT_sum_0i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT1 0x0040 |
| |
| #define BA_P3vFmt_DAT_sum_1i 0x0040 |
| #define B16P3vFmt_DAT_sum_1i 0x0040 |
| #define LSb32P3vFmt_DAT_sum_1i 0 |
| #define LSb16P3vFmt_DAT_sum_1i 0 |
| #define bP3vFmt_DAT_sum_1i 32 |
| #define MSK32P3vFmt_DAT_sum_1i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT2 0x0044 |
| |
| #define BA_P3vFmt_DAT_sum_2i 0x0044 |
| #define B16P3vFmt_DAT_sum_2i 0x0044 |
| #define LSb32P3vFmt_DAT_sum_2i 0 |
| #define LSb16P3vFmt_DAT_sum_2i 0 |
| #define bP3vFmt_DAT_sum_2i 32 |
| #define MSK32P3vFmt_DAT_sum_2i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT3 0x0048 |
| |
| #define BA_P3vFmt_DAT_sum_3i 0x0048 |
| #define B16P3vFmt_DAT_sum_3i 0x0048 |
| #define LSb32P3vFmt_DAT_sum_3i 0 |
| #define LSb16P3vFmt_DAT_sum_3i 0 |
| #define bP3vFmt_DAT_sum_3i 32 |
| #define MSK32P3vFmt_DAT_sum_3i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT4 0x004C |
| |
| #define BA_P3vFmt_DAT_sum_4i 0x004C |
| #define B16P3vFmt_DAT_sum_4i 0x004C |
| #define LSb32P3vFmt_DAT_sum_4i 0 |
| #define LSb16P3vFmt_DAT_sum_4i 0 |
| #define bP3vFmt_DAT_sum_4i 32 |
| #define MSK32P3vFmt_DAT_sum_4i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT5 0x0050 |
| |
| #define BA_P3vFmt_DAT_sum_5i 0x0050 |
| #define B16P3vFmt_DAT_sum_5i 0x0050 |
| #define LSb32P3vFmt_DAT_sum_5i 0 |
| #define LSb16P3vFmt_DAT_sum_5i 0 |
| #define bP3vFmt_DAT_sum_5i 32 |
| #define MSK32P3vFmt_DAT_sum_5i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT6 0x0054 |
| |
| #define BA_P3vFmt_DAT_sum_6i 0x0054 |
| #define B16P3vFmt_DAT_sum_6i 0x0054 |
| #define LSb32P3vFmt_DAT_sum_6i 0 |
| #define LSb16P3vFmt_DAT_sum_6i 0 |
| #define bP3vFmt_DAT_sum_6i 32 |
| #define MSK32P3vFmt_DAT_sum_6i 0xFFFFFFFF |
| |
| #define RA_P3vFmt_DAT7 0x0058 |
| |
| #define BA_P3vFmt_DAT_sum_7i 0x0058 |
| #define B16P3vFmt_DAT_sum_7i 0x0058 |
| #define LSb32P3vFmt_DAT_sum_7i 0 |
| #define LSb16P3vFmt_DAT_sum_7i 0 |
| #define bP3vFmt_DAT_sum_7i 32 |
| #define MSK32P3vFmt_DAT_sum_7i 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_CHKEN 0x005C |
| |
| #define BA_P3vFmt_CHKEN_bypass 0x005C |
| #define B16P3vFmt_CHKEN_bypass 0x005C |
| #define LSb32P3vFmt_CHKEN_bypass 0 |
| #define LSb16P3vFmt_CHKEN_bypass 0 |
| #define bP3vFmt_CHKEN_bypass 1 |
| #define MSK32P3vFmt_CHKEN_bypass 0x00000001 |
| |
| #define BA_P3vFmt_CHKEN_display 0x005C |
| #define B16P3vFmt_CHKEN_display 0x005C |
| #define LSb32P3vFmt_CHKEN_display 1 |
| #define LSb16P3vFmt_CHKEN_display 1 |
| #define bP3vFmt_CHKEN_display 1 |
| #define MSK32P3vFmt_CHKEN_display 0x00000002 |
| |
| #define BA_P3vFmt_CHKEN_ref 0x005C |
| #define B16P3vFmt_CHKEN_ref 0x005C |
| #define LSb32P3vFmt_CHKEN_ref 2 |
| #define LSb16P3vFmt_CHKEN_ref 2 |
| #define bP3vFmt_CHKEN_ref 1 |
| #define MSK32P3vFmt_CHKEN_ref 0x00000004 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3vFmt_CLR 0x0060 |
| |
| #define BA_P3vFmt_CLR_sumAddr 0x0060 |
| #define B16P3vFmt_CLR_sumAddr 0x0060 |
| #define LSb32P3vFmt_CLR_sumAddr 0 |
| #define LSb16P3vFmt_CLR_sumAddr 0 |
| #define bP3vFmt_CLR_sumAddr 1 |
| #define MSK32P3vFmt_CLR_sumAddr 0x00000001 |
| |
| #define BA_P3vFmt_CLR_sumDat 0x0060 |
| #define B16P3vFmt_CLR_sumDat 0x0060 |
| #define LSb32P3vFmt_CLR_sumDat 1 |
| #define LSb16P3vFmt_CLR_sumDat 1 |
| #define bP3vFmt_CLR_sumDat 1 |
| #define MSK32P3vFmt_CLR_sumDat 0x00000002 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3vFmt { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_CFG_scan(r32) _BFGET_(r32, 1, 0) |
| #define SET32P3vFmt_CFG_scan(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16P3vFmt_CFG_scan(r16) _BFGET_(r16, 1, 0) |
| #define SET16P3vFmt_CFG_scan(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32P3vFmt_CFG_rangeMapYflag(r32) _BFGET_(r32, 2, 2) |
| #define SET32P3vFmt_CFG_rangeMapYflag(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16P3vFmt_CFG_rangeMapYflag(r16) _BFGET_(r16, 2, 2) |
| #define SET16P3vFmt_CFG_rangeMapYflag(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32P3vFmt_CFG_rangeMapY(r32) _BFGET_(r32, 5, 3) |
| #define SET32P3vFmt_CFG_rangeMapY(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16P3vFmt_CFG_rangeMapY(r16) _BFGET_(r16, 5, 3) |
| #define SET16P3vFmt_CFG_rangeMapY(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32P3vFmt_CFG_rangeMapUVflag(r32) _BFGET_(r32, 6, 6) |
| #define SET32P3vFmt_CFG_rangeMapUVflag(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16P3vFmt_CFG_rangeMapUVflag(r16) _BFGET_(r16, 6, 6) |
| #define SET16P3vFmt_CFG_rangeMapUVflag(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32P3vFmt_CFG_rangeMapUV(r32) _BFGET_(r32, 9, 7) |
| #define SET32P3vFmt_CFG_rangeMapUV(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16P3vFmt_CFG_rangeMapUV(r16) _BFGET_(r16, 9, 7) |
| #define SET16P3vFmt_CFG_rangeMapUV(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define GET32P3vFmt_CFG_rangeRed(r32) _BFGET_(r32,10,10) |
| #define SET32P3vFmt_CFG_rangeRed(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16P3vFmt_CFG_rangeRed(r16) _BFGET_(r16,10,10) |
| #define SET16P3vFmt_CFG_rangeRed(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32P3vFmt_CFG_tileMode(r32) _BFGET_(r32,11,11) |
| #define SET32P3vFmt_CFG_tileMode(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16P3vFmt_CFG_tileMode(r16) _BFGET_(r16,11,11) |
| #define SET16P3vFmt_CFG_tileMode(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define w32P3vFmt_CFG {\ |
| UNSG32 uCFG_scan : 2;\ |
| UNSG32 uCFG_rangeMapYflag : 1;\ |
| UNSG32 uCFG_rangeMapY : 3;\ |
| UNSG32 uCFG_rangeMapUVflag : 1;\ |
| UNSG32 uCFG_rangeMapUV : 3;\ |
| UNSG32 uCFG_rangeRed : 1;\ |
| UNSG32 uCFG_tileMode : 1;\ |
| UNSG32 RSVDx0_b12 : 20;\ |
| } |
| union { UNSG32 u32P3vFmt_CFG; |
| struct w32P3vFmt_CFG; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_UYVY_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_UYVY_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_UYVY {\ |
| UNSG32 uUYVY_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_UYVY; |
| struct w32P3vFmt_UYVY; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_LUMA_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_LUMA_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_LUMA {\ |
| UNSG32 uLUMA_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_LUMA; |
| struct w32P3vFmt_LUMA; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_CHROMA_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_CHROMA_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_CHROMA {\ |
| UNSG32 uCHROMA_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_CHROMA; |
| struct w32P3vFmt_CHROMA; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_DSAMPLE_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DSAMPLE_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DSAMPLE {\ |
| UNSG32 uDSAMPLE_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DSAMPLE; |
| struct w32P3vFmt_DSAMPLE; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_BYPASS_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_BYPASS_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_BYPASS {\ |
| UNSG32 uBYPASS_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_BYPASS; |
| struct w32P3vFmt_BYPASS; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_STRIDE_tiledPage(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3vFmt_STRIDE_tiledPage(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3vFmt_STRIDE_tiledPage(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3vFmt_STRIDE_tiledPage(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3vFmt_STRIDE_tiledDSPage(r32) _BFGET_(r32,15, 8) |
| #define SET32P3vFmt_STRIDE_tiledDSPage(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16P3vFmt_STRIDE_tiledDSPage(r16) _BFGET_(r16,15, 8) |
| #define SET16P3vFmt_STRIDE_tiledDSPage(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32P3vFmt_STRIDE_422Line(r32) _BFGET_(r32,25,16) |
| #define SET32P3vFmt_STRIDE_422Line(r32,v) _BFSET_(r32,25,16,v) |
| #define GET16P3vFmt_STRIDE_422Line(r16) _BFGET_(r16, 9, 0) |
| #define SET16P3vFmt_STRIDE_422Line(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| #define w32P3vFmt_STRIDE {\ |
| UNSG32 uSTRIDE_tiledPage : 8;\ |
| UNSG32 uSTRIDE_tiledDSPage : 8;\ |
| UNSG32 uSTRIDE_422Line : 10;\ |
| UNSG32 RSVDx18_b26 : 6;\ |
| } |
| union { UNSG32 u32P3vFmt_STRIDE; |
| struct w32P3vFmt_STRIDE; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_UYVY_1_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_UYVY_1_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_UYVY_1 {\ |
| UNSG32 uUYVY_1_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_UYVY_1; |
| struct w32P3vFmt_UYVY_1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_LUMA_1_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_LUMA_1_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_LUMA_1 {\ |
| UNSG32 uLUMA_1_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_LUMA_1; |
| struct w32P3vFmt_LUMA_1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_CHROMA_1_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_CHROMA_1_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_CHROMA_1 {\ |
| UNSG32 uCHROMA_1_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_CHROMA_1; |
| struct w32P3vFmt_CHROMA_1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_DSAMPLE_1_base(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DSAMPLE_1_base(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DSAMPLE_1 {\ |
| UNSG32 uDSAMPLE_1_base : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DSAMPLE_1; |
| struct w32P3vFmt_DSAMPLE_1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_STRIDE_1_422Line(r32) _BFGET_(r32, 7, 0) |
| #define SET32P3vFmt_STRIDE_1_422Line(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16P3vFmt_STRIDE_1_422Line(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3vFmt_STRIDE_1_422Line(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32P3vFmt_STRIDE_1_tiledPage(r32) _BFGET_(r32,15, 8) |
| #define SET32P3vFmt_STRIDE_1_tiledPage(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16P3vFmt_STRIDE_1_tiledPage(r16) _BFGET_(r16,15, 8) |
| #define SET16P3vFmt_STRIDE_1_tiledPage(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define GET32P3vFmt_STRIDE_1_tiledDSPage(r32) _BFGET_(r32,23,16) |
| #define SET32P3vFmt_STRIDE_1_tiledDSPage(r32,v) _BFSET_(r32,23,16,v) |
| #define GET16P3vFmt_STRIDE_1_tiledDSPage(r16) _BFGET_(r16, 7, 0) |
| #define SET16P3vFmt_STRIDE_1_tiledDSPage(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define w32P3vFmt_STRIDE_1 {\ |
| UNSG32 uSTRIDE_1_422Line : 8;\ |
| UNSG32 uSTRIDE_1_tiledPage : 8;\ |
| UNSG32 uSTRIDE_1_tiledDSPage : 8;\ |
| UNSG32 RSVDx2C_b24 : 8;\ |
| } |
| union { UNSG32 u32P3vFmt_STRIDE_1; |
| struct w32P3vFmt_STRIDE_1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_NP_CFG_minAddr(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_NP_CFG_minAddr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_NP_CFG {\ |
| UNSG32 uNP_CFG_minAddr : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_NP_CFG; |
| struct w32P3vFmt_NP_CFG; |
| }; |
| #define GET32P3vFmt_NP_CFG_maxAddr(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_NP_CFG_maxAddr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_NP_CFG1 {\ |
| UNSG32 uNP_CFG_maxAddr : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_NP_CFG1; |
| struct w32P3vFmt_NP_CFG1; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_ADDR_sum(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_ADDR_sum(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_ADDR {\ |
| UNSG32 uADDR_sum : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_ADDR; |
| struct w32P3vFmt_ADDR; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_DAT_sum_0i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_0i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT {\ |
| UNSG32 uDAT_sum_0i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT; |
| struct w32P3vFmt_DAT; |
| }; |
| #define GET32P3vFmt_DAT_sum_1i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_1i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT1 {\ |
| UNSG32 uDAT_sum_1i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT1; |
| struct w32P3vFmt_DAT1; |
| }; |
| #define GET32P3vFmt_DAT_sum_2i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_2i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT2 {\ |
| UNSG32 uDAT_sum_2i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT2; |
| struct w32P3vFmt_DAT2; |
| }; |
| #define GET32P3vFmt_DAT_sum_3i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_3i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT3 {\ |
| UNSG32 uDAT_sum_3i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT3; |
| struct w32P3vFmt_DAT3; |
| }; |
| #define GET32P3vFmt_DAT_sum_4i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_4i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT4 {\ |
| UNSG32 uDAT_sum_4i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT4; |
| struct w32P3vFmt_DAT4; |
| }; |
| #define GET32P3vFmt_DAT_sum_5i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_5i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT5 {\ |
| UNSG32 uDAT_sum_5i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT5; |
| struct w32P3vFmt_DAT5; |
| }; |
| #define GET32P3vFmt_DAT_sum_6i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_6i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT6 {\ |
| UNSG32 uDAT_sum_6i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT6; |
| struct w32P3vFmt_DAT6; |
| }; |
| #define GET32P3vFmt_DAT_sum_7i(r32) _BFGET_(r32,31, 0) |
| #define SET32P3vFmt_DAT_sum_7i(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3vFmt_DAT7 {\ |
| UNSG32 uDAT_sum_7i : 32;\ |
| } |
| union { UNSG32 u32P3vFmt_DAT7; |
| struct w32P3vFmt_DAT7; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_CHKEN_bypass(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3vFmt_CHKEN_bypass(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3vFmt_CHKEN_bypass(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3vFmt_CHKEN_bypass(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3vFmt_CHKEN_display(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3vFmt_CHKEN_display(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3vFmt_CHKEN_display(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3vFmt_CHKEN_display(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3vFmt_CHKEN_ref(r32) _BFGET_(r32, 2, 2) |
| #define SET32P3vFmt_CHKEN_ref(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16P3vFmt_CHKEN_ref(r16) _BFGET_(r16, 2, 2) |
| #define SET16P3vFmt_CHKEN_ref(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define w32P3vFmt_CHKEN {\ |
| UNSG32 uCHKEN_bypass : 1;\ |
| UNSG32 uCHKEN_display : 1;\ |
| UNSG32 uCHKEN_ref : 1;\ |
| UNSG32 RSVDx5C_b3 : 29;\ |
| } |
| union { UNSG32 u32P3vFmt_CHKEN; |
| struct w32P3vFmt_CHKEN; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3vFmt_CLR_sumAddr(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3vFmt_CLR_sumAddr(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3vFmt_CLR_sumAddr(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3vFmt_CLR_sumAddr(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3vFmt_CLR_sumDat(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3vFmt_CLR_sumDat(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3vFmt_CLR_sumDat(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3vFmt_CLR_sumDat(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32P3vFmt_CLR {\ |
| UNSG32 uCLR_sumAddr : 1;\ |
| UNSG32 uCLR_sumDat : 1;\ |
| UNSG32 RSVDx60_b2 : 30;\ |
| } |
| union { UNSG32 u32P3vFmt_CLR; |
| struct w32P3vFmt_CLR; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3vFmt; |
| |
| typedef union T32P3vFmt_CFG |
| { UNSG32 u32; |
| struct w32P3vFmt_CFG; |
| } T32P3vFmt_CFG; |
| typedef union T32P3vFmt_UYVY |
| { UNSG32 u32; |
| struct w32P3vFmt_UYVY; |
| } T32P3vFmt_UYVY; |
| typedef union T32P3vFmt_LUMA |
| { UNSG32 u32; |
| struct w32P3vFmt_LUMA; |
| } T32P3vFmt_LUMA; |
| typedef union T32P3vFmt_CHROMA |
| { UNSG32 u32; |
| struct w32P3vFmt_CHROMA; |
| } T32P3vFmt_CHROMA; |
| typedef union T32P3vFmt_DSAMPLE |
| { UNSG32 u32; |
| struct w32P3vFmt_DSAMPLE; |
| } T32P3vFmt_DSAMPLE; |
| typedef union T32P3vFmt_BYPASS |
| { UNSG32 u32; |
| struct w32P3vFmt_BYPASS; |
| } T32P3vFmt_BYPASS; |
| typedef union T32P3vFmt_STRIDE |
| { UNSG32 u32; |
| struct w32P3vFmt_STRIDE; |
| } T32P3vFmt_STRIDE; |
| typedef union T32P3vFmt_UYVY_1 |
| { UNSG32 u32; |
| struct w32P3vFmt_UYVY_1; |
| } T32P3vFmt_UYVY_1; |
| typedef union T32P3vFmt_LUMA_1 |
| { UNSG32 u32; |
| struct w32P3vFmt_LUMA_1; |
| } T32P3vFmt_LUMA_1; |
| typedef union T32P3vFmt_CHROMA_1 |
| { UNSG32 u32; |
| struct w32P3vFmt_CHROMA_1; |
| } T32P3vFmt_CHROMA_1; |
| typedef union T32P3vFmt_DSAMPLE_1 |
| { UNSG32 u32; |
| struct w32P3vFmt_DSAMPLE_1; |
| } T32P3vFmt_DSAMPLE_1; |
| typedef union T32P3vFmt_STRIDE_1 |
| { UNSG32 u32; |
| struct w32P3vFmt_STRIDE_1; |
| } T32P3vFmt_STRIDE_1; |
| typedef union T32P3vFmt_NP_CFG |
| { UNSG32 u32; |
| struct w32P3vFmt_NP_CFG; |
| } T32P3vFmt_NP_CFG; |
| typedef union T32P3vFmt_NP_CFG1 |
| { UNSG32 u32; |
| struct w32P3vFmt_NP_CFG1; |
| } T32P3vFmt_NP_CFG1; |
| typedef union T32P3vFmt_ADDR |
| { UNSG32 u32; |
| struct w32P3vFmt_ADDR; |
| } T32P3vFmt_ADDR; |
| typedef union T32P3vFmt_DAT |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT; |
| } T32P3vFmt_DAT; |
| typedef union T32P3vFmt_DAT1 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT1; |
| } T32P3vFmt_DAT1; |
| typedef union T32P3vFmt_DAT2 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT2; |
| } T32P3vFmt_DAT2; |
| typedef union T32P3vFmt_DAT3 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT3; |
| } T32P3vFmt_DAT3; |
| typedef union T32P3vFmt_DAT4 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT4; |
| } T32P3vFmt_DAT4; |
| typedef union T32P3vFmt_DAT5 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT5; |
| } T32P3vFmt_DAT5; |
| typedef union T32P3vFmt_DAT6 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT6; |
| } T32P3vFmt_DAT6; |
| typedef union T32P3vFmt_DAT7 |
| { UNSG32 u32; |
| struct w32P3vFmt_DAT7; |
| } T32P3vFmt_DAT7; |
| typedef union T32P3vFmt_CHKEN |
| { UNSG32 u32; |
| struct w32P3vFmt_CHKEN; |
| } T32P3vFmt_CHKEN; |
| typedef union T32P3vFmt_CLR |
| { UNSG32 u32; |
| struct w32P3vFmt_CLR; |
| } T32P3vFmt_CLR; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TP3vFmt_CFG |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_CFG; |
| }; |
| } TP3vFmt_CFG; |
| typedef union TP3vFmt_UYVY |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_UYVY; |
| }; |
| } TP3vFmt_UYVY; |
| typedef union TP3vFmt_LUMA |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_LUMA; |
| }; |
| } TP3vFmt_LUMA; |
| typedef union TP3vFmt_CHROMA |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_CHROMA; |
| }; |
| } TP3vFmt_CHROMA; |
| typedef union TP3vFmt_DSAMPLE |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_DSAMPLE; |
| }; |
| } TP3vFmt_DSAMPLE; |
| typedef union TP3vFmt_BYPASS |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_BYPASS; |
| }; |
| } TP3vFmt_BYPASS; |
| typedef union TP3vFmt_STRIDE |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_STRIDE; |
| }; |
| } TP3vFmt_STRIDE; |
| typedef union TP3vFmt_UYVY_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_UYVY_1; |
| }; |
| } TP3vFmt_UYVY_1; |
| typedef union TP3vFmt_LUMA_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_LUMA_1; |
| }; |
| } TP3vFmt_LUMA_1; |
| typedef union TP3vFmt_CHROMA_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_CHROMA_1; |
| }; |
| } TP3vFmt_CHROMA_1; |
| typedef union TP3vFmt_DSAMPLE_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_DSAMPLE_1; |
| }; |
| } TP3vFmt_DSAMPLE_1; |
| typedef union TP3vFmt_STRIDE_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_STRIDE_1; |
| }; |
| } TP3vFmt_STRIDE_1; |
| typedef union TP3vFmt_NP_CFG |
| { UNSG32 u32[2]; |
| struct { |
| struct w32P3vFmt_NP_CFG; |
| struct w32P3vFmt_NP_CFG1; |
| }; |
| } TP3vFmt_NP_CFG; |
| typedef union TP3vFmt_ADDR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_ADDR; |
| }; |
| } TP3vFmt_ADDR; |
| typedef union TP3vFmt_DAT |
| { UNSG32 u32[8]; |
| struct { |
| struct w32P3vFmt_DAT; |
| struct w32P3vFmt_DAT1; |
| struct w32P3vFmt_DAT2; |
| struct w32P3vFmt_DAT3; |
| struct w32P3vFmt_DAT4; |
| struct w32P3vFmt_DAT5; |
| struct w32P3vFmt_DAT6; |
| struct w32P3vFmt_DAT7; |
| }; |
| } TP3vFmt_DAT; |
| typedef union TP3vFmt_CHKEN |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_CHKEN; |
| }; |
| } TP3vFmt_CHKEN; |
| typedef union TP3vFmt_CLR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3vFmt_CLR; |
| }; |
| } TP3vFmt_CLR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3vFmt_drvrd(SIE_P3vFmt *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3vFmt_drvwr(SIE_P3vFmt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3vFmt_reset(SIE_P3vFmt *p); |
| SIGN32 P3vFmt_cmp (SIE_P3vFmt *p, SIE_P3vFmt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3vFmt_check(p,pie,pfx,hLOG) P3vFmt_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3vFmt_print(p, pfx,hLOG) P3vFmt_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3vFmt |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3pCnt biu (4,4) |
| /// ### |
| /// * pCube performance Counters. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 CLK (R-) |
| /// %unsigned 32 CNT |
| /// ### |
| /// * Free run counter used to count the number of p3Clk. |
| /// ### |
| /// @ 0x00004 INS (R-) |
| /// %unsigned 32 CNT |
| /// ### |
| /// * Total instruction counter provided by p3Ctl. |
| /// ### |
| /// @ 0x00008 BUBL (R-) |
| /// %unsigned 32 CNT |
| /// ### |
| /// * Total bubble counter inserted by HW. |
| /// ### |
| /// @ 0x0000C STAL (R-) |
| /// %unsigned 32 CNT |
| /// ### |
| /// * Total stall counter. |
| /// ### |
| /// @ 0x00010 SEMA (R-) |
| /// %unsigned 32 CNT |
| /// ### |
| /// * Counter for total # of cycles spent waiting for SEM check. Not gated by CNTR_CTRL.Enable. Write 0 to clear. |
| /// ### |
| /// @ 0x00014 FREE_RUN (W-) |
| /// %unsigned 1 EN 0x0 |
| /// ### |
| /// * 0: disable free run |
| /// * 1: enable free run, bubble instruction will be inserted by HW when no more instructions are available after one sync-only instruction. |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00018 CLR (W-) |
| /// %unsigned 1 CLK |
| /// %unsigned 1 INS |
| /// %unsigned 1 BUBL |
| /// %unsigned 1 STAL |
| /// %unsigned 1 SEMA |
| /// ### |
| /// * Write “1” to clear the corresponding counters |
| /// * End Of P3pCnt |
| /// ### |
| /// %% 27 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 28B, bits: 166b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3pCnt |
| #define h_P3pCnt (){} |
| |
| #define RA_P3pCnt_CLK 0x0000 |
| |
| #define BA_P3pCnt_CLK_CNT 0x0000 |
| #define B16P3pCnt_CLK_CNT 0x0000 |
| #define LSb32P3pCnt_CLK_CNT 0 |
| #define LSb16P3pCnt_CLK_CNT 0 |
| #define bP3pCnt_CLK_CNT 32 |
| #define MSK32P3pCnt_CLK_CNT 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_INS 0x0004 |
| |
| #define BA_P3pCnt_INS_CNT 0x0004 |
| #define B16P3pCnt_INS_CNT 0x0004 |
| #define LSb32P3pCnt_INS_CNT 0 |
| #define LSb16P3pCnt_INS_CNT 0 |
| #define bP3pCnt_INS_CNT 32 |
| #define MSK32P3pCnt_INS_CNT 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_BUBL 0x0008 |
| |
| #define BA_P3pCnt_BUBL_CNT 0x0008 |
| #define B16P3pCnt_BUBL_CNT 0x0008 |
| #define LSb32P3pCnt_BUBL_CNT 0 |
| #define LSb16P3pCnt_BUBL_CNT 0 |
| #define bP3pCnt_BUBL_CNT 32 |
| #define MSK32P3pCnt_BUBL_CNT 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_STAL 0x000C |
| |
| #define BA_P3pCnt_STAL_CNT 0x000C |
| #define B16P3pCnt_STAL_CNT 0x000C |
| #define LSb32P3pCnt_STAL_CNT 0 |
| #define LSb16P3pCnt_STAL_CNT 0 |
| #define bP3pCnt_STAL_CNT 32 |
| #define MSK32P3pCnt_STAL_CNT 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_SEMA 0x0010 |
| |
| #define BA_P3pCnt_SEMA_CNT 0x0010 |
| #define B16P3pCnt_SEMA_CNT 0x0010 |
| #define LSb32P3pCnt_SEMA_CNT 0 |
| #define LSb16P3pCnt_SEMA_CNT 0 |
| #define bP3pCnt_SEMA_CNT 32 |
| #define MSK32P3pCnt_SEMA_CNT 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_FREE_RUN 0x0014 |
| |
| #define BA_P3pCnt_FREE_RUN_EN 0x0014 |
| #define B16P3pCnt_FREE_RUN_EN 0x0014 |
| #define LSb32P3pCnt_FREE_RUN_EN 0 |
| #define LSb16P3pCnt_FREE_RUN_EN 0 |
| #define bP3pCnt_FREE_RUN_EN 1 |
| #define MSK32P3pCnt_FREE_RUN_EN 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3pCnt_CLR 0x0018 |
| |
| #define BA_P3pCnt_CLR_CLK 0x0018 |
| #define B16P3pCnt_CLR_CLK 0x0018 |
| #define LSb32P3pCnt_CLR_CLK 0 |
| #define LSb16P3pCnt_CLR_CLK 0 |
| #define bP3pCnt_CLR_CLK 1 |
| #define MSK32P3pCnt_CLR_CLK 0x00000001 |
| |
| #define BA_P3pCnt_CLR_INS 0x0018 |
| #define B16P3pCnt_CLR_INS 0x0018 |
| #define LSb32P3pCnt_CLR_INS 1 |
| #define LSb16P3pCnt_CLR_INS 1 |
| #define bP3pCnt_CLR_INS 1 |
| #define MSK32P3pCnt_CLR_INS 0x00000002 |
| |
| #define BA_P3pCnt_CLR_BUBL 0x0018 |
| #define B16P3pCnt_CLR_BUBL 0x0018 |
| #define LSb32P3pCnt_CLR_BUBL 2 |
| #define LSb16P3pCnt_CLR_BUBL 2 |
| #define bP3pCnt_CLR_BUBL 1 |
| #define MSK32P3pCnt_CLR_BUBL 0x00000004 |
| |
| #define BA_P3pCnt_CLR_STAL 0x0018 |
| #define B16P3pCnt_CLR_STAL 0x0018 |
| #define LSb32P3pCnt_CLR_STAL 3 |
| #define LSb16P3pCnt_CLR_STAL 3 |
| #define bP3pCnt_CLR_STAL 1 |
| #define MSK32P3pCnt_CLR_STAL 0x00000008 |
| |
| #define BA_P3pCnt_CLR_SEMA 0x0018 |
| #define B16P3pCnt_CLR_SEMA 0x0018 |
| #define LSb32P3pCnt_CLR_SEMA 4 |
| #define LSb16P3pCnt_CLR_SEMA 4 |
| #define bP3pCnt_CLR_SEMA 1 |
| #define MSK32P3pCnt_CLR_SEMA 0x00000010 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3pCnt { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_CLK_CNT(r32) _BFGET_(r32,31, 0) |
| #define SET32P3pCnt_CLK_CNT(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3pCnt_CLK {\ |
| UNSG32 uCLK_CNT : 32;\ |
| } |
| union { UNSG32 u32P3pCnt_CLK; |
| struct w32P3pCnt_CLK; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_INS_CNT(r32) _BFGET_(r32,31, 0) |
| #define SET32P3pCnt_INS_CNT(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3pCnt_INS {\ |
| UNSG32 uINS_CNT : 32;\ |
| } |
| union { UNSG32 u32P3pCnt_INS; |
| struct w32P3pCnt_INS; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_BUBL_CNT(r32) _BFGET_(r32,31, 0) |
| #define SET32P3pCnt_BUBL_CNT(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3pCnt_BUBL {\ |
| UNSG32 uBUBL_CNT : 32;\ |
| } |
| union { UNSG32 u32P3pCnt_BUBL; |
| struct w32P3pCnt_BUBL; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_STAL_CNT(r32) _BFGET_(r32,31, 0) |
| #define SET32P3pCnt_STAL_CNT(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3pCnt_STAL {\ |
| UNSG32 uSTAL_CNT : 32;\ |
| } |
| union { UNSG32 u32P3pCnt_STAL; |
| struct w32P3pCnt_STAL; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_SEMA_CNT(r32) _BFGET_(r32,31, 0) |
| #define SET32P3pCnt_SEMA_CNT(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32P3pCnt_SEMA {\ |
| UNSG32 uSEMA_CNT : 32;\ |
| } |
| union { UNSG32 u32P3pCnt_SEMA; |
| struct w32P3pCnt_SEMA; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_FREE_RUN_EN(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3pCnt_FREE_RUN_EN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3pCnt_FREE_RUN_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3pCnt_FREE_RUN_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32P3pCnt_FREE_RUN {\ |
| UNSG32 uFREE_RUN_EN : 1;\ |
| UNSG32 RSVDx14_b1 : 31;\ |
| } |
| union { UNSG32 u32P3pCnt_FREE_RUN; |
| struct w32P3pCnt_FREE_RUN; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32P3pCnt_CLR_CLK(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3pCnt_CLR_CLK(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3pCnt_CLR_CLK(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3pCnt_CLR_CLK(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32P3pCnt_CLR_INS(r32) _BFGET_(r32, 1, 1) |
| #define SET32P3pCnt_CLR_INS(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16P3pCnt_CLR_INS(r16) _BFGET_(r16, 1, 1) |
| #define SET16P3pCnt_CLR_INS(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32P3pCnt_CLR_BUBL(r32) _BFGET_(r32, 2, 2) |
| #define SET32P3pCnt_CLR_BUBL(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16P3pCnt_CLR_BUBL(r16) _BFGET_(r16, 2, 2) |
| #define SET16P3pCnt_CLR_BUBL(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32P3pCnt_CLR_STAL(r32) _BFGET_(r32, 3, 3) |
| #define SET32P3pCnt_CLR_STAL(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16P3pCnt_CLR_STAL(r16) _BFGET_(r16, 3, 3) |
| #define SET16P3pCnt_CLR_STAL(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32P3pCnt_CLR_SEMA(r32) _BFGET_(r32, 4, 4) |
| #define SET32P3pCnt_CLR_SEMA(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16P3pCnt_CLR_SEMA(r16) _BFGET_(r16, 4, 4) |
| #define SET16P3pCnt_CLR_SEMA(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32P3pCnt_CLR {\ |
| UNSG32 uCLR_CLK : 1;\ |
| UNSG32 uCLR_INS : 1;\ |
| UNSG32 uCLR_BUBL : 1;\ |
| UNSG32 uCLR_STAL : 1;\ |
| UNSG32 uCLR_SEMA : 1;\ |
| UNSG32 RSVDx18_b5 : 27;\ |
| } |
| union { UNSG32 u32P3pCnt_CLR; |
| struct w32P3pCnt_CLR; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3pCnt; |
| |
| typedef union T32P3pCnt_CLK |
| { UNSG32 u32; |
| struct w32P3pCnt_CLK; |
| } T32P3pCnt_CLK; |
| typedef union T32P3pCnt_INS |
| { UNSG32 u32; |
| struct w32P3pCnt_INS; |
| } T32P3pCnt_INS; |
| typedef union T32P3pCnt_BUBL |
| { UNSG32 u32; |
| struct w32P3pCnt_BUBL; |
| } T32P3pCnt_BUBL; |
| typedef union T32P3pCnt_STAL |
| { UNSG32 u32; |
| struct w32P3pCnt_STAL; |
| } T32P3pCnt_STAL; |
| typedef union T32P3pCnt_SEMA |
| { UNSG32 u32; |
| struct w32P3pCnt_SEMA; |
| } T32P3pCnt_SEMA; |
| typedef union T32P3pCnt_FREE_RUN |
| { UNSG32 u32; |
| struct w32P3pCnt_FREE_RUN; |
| } T32P3pCnt_FREE_RUN; |
| typedef union T32P3pCnt_CLR |
| { UNSG32 u32; |
| struct w32P3pCnt_CLR; |
| } T32P3pCnt_CLR; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TP3pCnt_CLK |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_CLK; |
| }; |
| } TP3pCnt_CLK; |
| typedef union TP3pCnt_INS |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_INS; |
| }; |
| } TP3pCnt_INS; |
| typedef union TP3pCnt_BUBL |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_BUBL; |
| }; |
| } TP3pCnt_BUBL; |
| typedef union TP3pCnt_STAL |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_STAL; |
| }; |
| } TP3pCnt_STAL; |
| typedef union TP3pCnt_SEMA |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_SEMA; |
| }; |
| } TP3pCnt_SEMA; |
| typedef union TP3pCnt_FREE_RUN |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_FREE_RUN; |
| }; |
| } TP3pCnt_FREE_RUN; |
| typedef union TP3pCnt_CLR |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3pCnt_CLR; |
| }; |
| } TP3pCnt_CLR; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3pCnt_drvrd(SIE_P3pCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3pCnt_drvwr(SIE_P3pCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3pCnt_reset(SIE_P3pCnt *p); |
| SIGN32 P3pCnt_cmp (SIE_P3pCnt *p, SIE_P3pCnt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3pCnt_check(p,pie,pfx,hLOG) P3pCnt_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3pCnt_print(p, pfx,hLOG) P3pCnt_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3pCnt |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE PCUBE biu (4,4) |
| /// ### |
| /// * Dtcm size for different pCube configurations |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// : DEC_DCTM0_SIZE 0x1000 |
| /// : DEC_DCTM1_SIZE 0x800 |
| /// : ENC_DTCM0_SIZE 0x1800 |
| /// : ENC_DTCM1_SIZE 0x800 |
| /// : DEC_ITCM0_SIZE 0x1000 |
| /// : DEC_ITCM1_SIZE 0x800 |
| /// : ENC_ITCM0_SIZE 0x1000 |
| /// : ENC_ITCM1_SIZE 0x800 |
| /// : NUL 0x0 |
| /// : LUT 0xFC |
| /// : INS 0xF8 |
| /// : OPO 0xF4 |
| /// : END 0xF2 |
| /// : CLR 0xF1 |
| /// : BIU 0xF0 |
| /// : CSH 0xE0 |
| /// : RegBase 0xC000 |
| /// : RegSize 0x4000 |
| /// : F2A64_QdeQ 0x0 |
| /// : F2A64_IPRO 0x2 |
| /// : F2A64_FLUSH 0x1 |
| /// : F2A64_IPLUS 0x3 |
| /// : F2A64_IPLUS_QMAT 0x4 |
| /// : F2A64_SemChk 0x7 |
| /// : F2A64_SemUpdf 0x8 |
| /// : F2A64_BitOp0 0x20 |
| /// : F2A64_BitOp1 0x21 |
| /// : F2A64_BitOp2 0x22 |
| /// : F2A64_BitOp3 0x23 |
| /// ### |
| /// * PCube FIGO extension IDs; FIGO3 == new FIGO for encoder |
| /// ### |
| /// : F3A64_Fop 0x0 |
| /// : F3A64_FLUSH 0x1 |
| /// ### |
| /// * To be replaced soon by F3A64_IME and F3A64_FME |
| /// ### |
| /// : F3A64_neighbor 0x2 |
| /// : F3A64_neighborAB 0x3 |
| /// : F3A64_neighborCD 0x4 |
| /// : F3A64_BwPmv 0x5 |
| /// : F3A64_FwPmv 0x6 |
| /// : F3A64_SemChk 0x7 |
| /// : F3A64_SemUpd 0x8 |
| /// : F3A64_IME 0x9 |
| /// ### |
| /// * MEE extension ID for IME thread |
| /// ### |
| /// : F3A64_FME 0xA |
| /// ### |
| /// * MEE extension ID for FME thread |
| /// ### |
| /// : F3A64_WME 0xB |
| /// ### |
| /// * MEE extension ID for WBO thread |
| /// ### |
| /// : F3A64_BitOp0 0x20 |
| /// : F3A64_BitOp1 0x21 |
| /// : F3A64_BitOp2 0x22 |
| /// : F3A64_BitOp3 0x23 |
| /// @ 0x00000 TCM (P) |
| /// # 0x00000 tcm |
| /// $FigoData tcm MEM [1024] |
| /// ### |
| /// * For decoder, 4KB + 2KB |
| /// ### |
| /// @ 0x02000 (W-) |
| /// # # Stuffing bytes... |
| /// %% 196608 |
| /// @ 0x08000 FIGO (P) |
| /// # 0x08000 figo |
| /// $FigoReg figo REG |
| /// @ 0x0A000 FIGO_CTLR (P) |
| /// # 0x0A000 figoCtlr |
| /// $FigoReg figoCtlr REG |
| /// @ 0x0C000 HBO (P) |
| /// # 0x0C000 hbo |
| /// $HBO hbo REG |
| /// @ 0x0C700 SEMA (P) |
| /// # 0x0C700 semaHub |
| /// $SemaHub semaHub REG |
| /// @ 0x0CB00 CFG (P) |
| /// ### |
| /// * Basic configuration |
| /// ### |
| /// %unsigned 2 SelDP 0x0 |
| /// ### |
| /// * 0~3 to select active data processing pipeline |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// @ 0x0CB04 clkGateEn (P) |
| /// %unsigned 1 meeSysClk 0x1 |
| /// %unsigned 1 meeClk 0x1 |
| /// %unsigned 1 iProSysClk 0x1 |
| /// %unsigned 1 iProClk 0x1 |
| /// %unsigned 1 pipe1Clk 0x1 |
| /// ### |
| /// * 0~3 to select active data processing pipeline |
| /// ### |
| /// %% 27 # Stuffing bits... |
| /// @ 0x0CB08 BASE (RW) |
| /// ### |
| /// * Base addresses |
| /// ### |
| /// %unsigned 10 CmdLUT 0x0 |
| /// ### |
| /// * CmdLUT base pointer b[9:0] |
| /// * CmdLUT addressing: cp' = BASE_CmdLUT + cp |
| /// ### |
| /// %unsigned 13 IRAM 0x0 |
| /// ### |
| /// * IRAM base pointer b[12:0] |
| /// * IRAM addressing: ip' = BASE_IRAM + ip |
| /// ### |
| /// %unsigned 9 OPO 0x0 |
| /// ### |
| /// * Opcode offset b[8:0] |
| /// * Opcode table addressing: op' = BASE_OPO + op |
| /// ### |
| /// @ 0x0CB0C RESET (WOC-) |
| /// ### |
| /// * Software reset |
| /// ### |
| /// %unsigned 1 Enb |
| /// ### |
| /// * Trigger software reset |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0CB10 START (WOC-) |
| /// ### |
| /// * PCube kick off |
| /// ### |
| /// %unsigned 1 Enb |
| /// ### |
| /// * Start PCube command loader |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x0CB14 STATUS (R-) |
| /// ### |
| /// * PCube internal status of all threads |
| /// ### |
| /// %unsigned 1 p3Clr 0x1 |
| /// %unsigned 1 p3Clr1 0x1 |
| /// ### |
| /// * If pCube pipeline is in clear state |
| /// ### |
| /// %unsigned 1 PendingCmd 0x0 |
| /// ### |
| /// * If there're pending commands in look-up stage |
| /// ### |
| /// %unsigned 5 SemID 0x0 |
| /// ### |
| /// * If there is semaphore check op in cmdParser. 0 indicate no semaphore check. |
| /// ### |
| /// %unsigned 1 semOp 0x0 |
| /// ### |
| /// * Indicate the sem operation mode,0-OF check, 1-UF check. |
| /// ### |
| /// %unsigned 1 PendingRdQ 0x0 |
| /// ### |
| /// * If there're pending DMA read in Read Agent Queue |
| /// ### |
| /// %unsigned 1 PendingIns 0x0 |
| /// ### |
| /// * If there're pending instructions in look-up stage |
| /// ### |
| /// %unsigned 1 PendingInsQ 0x0 |
| /// ### |
| /// * If there're pending ins in instruction Queue |
| /// ### |
| /// %unsigned 1 PendingWrQ 0x0 |
| /// ### |
| /// * If there're pending DMA write in Write Agent Queue |
| /// ### |
| /// %unsigned 1 PendingSyncQ 0x0 |
| /// ### |
| /// * If there're pending DMA write in sync Queue |
| /// ### |
| /// %unsigned 2 RABusy 0x0 |
| /// ### |
| /// * Bit[0] indicate the status between RA and DMEM. |
| /// * Bit[1] indicate the status between RA and OCPf. |
| /// ### |
| /// %unsigned 2 WABusy 0x0 |
| /// ### |
| /// * Bit[0] indicate the status between WA and DMEM. |
| /// * Bit[1] indicate the status between WA and OCPf. |
| /// ### |
| /// %unsigned 1 DataRcvBusy 0x0 |
| /// ### |
| /// * Indicate the status between DR and DMEM. |
| /// ### |
| /// %unsigned 1 VFMTBusy 0x0 |
| /// ### |
| /// * Indicate the status video formatter |
| /// ### |
| /// %% 12 # Stuffing bits... |
| /// @ 0x0CB18 VFMT (P) |
| /// # 0x0CB18 vFmt |
| /// $P3vFmt vFmt REG |
| /// @ 0x0CB7C PCNT (P) |
| /// # 0x0CB7C pCnt |
| /// $P3pCnt pCnt REG |
| /// @ 0x0CB98 PCNT1 (P) |
| /// # 0x0CB98 pCnt1 |
| /// $P3pCnt pCnt1 REG |
| /// @ 0x0CBB4 (W-) |
| /// # # Stuffing bytes... |
| /// %% 107104 |
| /// @ 0x10000 DP0 (P) |
| /// # 0x10000 ticEx |
| /// $P3ticEx ticEx REG |
| /// @ 0x18000 DP1 (P) |
| /// # 0x18000 ticEx1 |
| /// $P3ticEx ticEx1 REG |
| /// ### |
| /// * env 0x00000003=CODEC prepASIC vprodoc; or |
| /// * env XOPTS='-D 1' prepASIC vprodoc |
| /// ### |
| /// @ 0x20000 (W-) |
| /// # # Stuffing bytes... |
| /// %% 524288 |
| /// @ 0x30000 IRAM (P) |
| /// # 0x30000 iram |
| /// $P3IRAM iram MEM |
| /// @ 0x32000 (W-) |
| /// # # Stuffing bytes... |
| /// %% 458752 |
| /// @ 0x40000 DMEM (P) |
| /// # 0x40000 dmem |
| /// $P3DMEM dmem MEM |
| /// @ 0x44000 (W-) |
| /// # # Stuffing bytes... |
| /// %% 131072 |
| /// @ 0x48000 CmdLUT (P) |
| /// # 0x48000 cmdlut |
| /// $P3CLUT cmdlut MEM |
| /// @ 0x48400 (W-) |
| /// # # Stuffing bytes... |
| /// %% 24576 |
| /// @ 0x49000 CmdLUT1 (P) |
| /// # 0x49000 cmdlut1 |
| /// $P3CLUT cmdlut1 MEM |
| /// @ 0x49400 (W-) |
| /// # # Stuffing bytes... |
| /// %% 221184 |
| /// @ 0x50000 ITCM (P) |
| /// # 0x50000 itcm |
| /// $P3FigoITCM itcm MEM |
| /// @ 0x54000 ITCM1 (P) |
| /// # 0x54000 itcm1 |
| /// $ITCM itcm1 MEM |
| /// @ 0x56000 QMTX (-) |
| /// # 0x56000 qmtx |
| /// $QMatrix qmtx MEM |
| /// @ 0x56200 DQMTX (-) |
| /// # 0x56200 dqmtx |
| /// $deQMatrix dqmtx MEM |
| /// @ 0x56400 (W-) |
| /// # # Stuffing bytes... |
| /// %% 8192 |
| /// @ 0x56800 RNDMTX (-) |
| /// # 0x56800 rndmtx |
| /// $RoundMatrix rndmtx MEM |
| /// @ 0x57000 SSDMTX (-) |
| /// # 0x57000 ssdmtx |
| /// $ScaleMatrix ssdmtx MEM |
| /// @ 0x57400 (W-) |
| /// # # Stuffing bytes... |
| /// %% 24576 |
| /// @ 0x58000 IPRO (-) |
| /// # 0x58000 iprobiu |
| /// $IPROBIU iprobiu REG |
| /// @ 0x5C000 PFMT (P) |
| /// # 0x5C000 pixFmt |
| /// $pixFmtReg pixFmt REG |
| /// @ 0x5C0D0 (W-) |
| /// # # Stuffing bytes... |
| /// %% 129408 |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 393216B, bits: 7206b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_PCUBE |
| #define h_PCUBE (){} |
| |
| #define PCUBE_DEC_DCTM0_SIZE 0x1000 |
| #define PCUBE_DEC_DCTM1_SIZE 0x800 |
| #define PCUBE_ENC_DTCM0_SIZE 0x1800 |
| #define PCUBE_ENC_DTCM1_SIZE 0x800 |
| #define PCUBE_DEC_ITCM0_SIZE 0x1000 |
| #define PCUBE_DEC_ITCM1_SIZE 0x800 |
| #define PCUBE_ENC_ITCM0_SIZE 0x1000 |
| #define PCUBE_ENC_ITCM1_SIZE 0x800 |
| #define PCUBE_NUL 0x0 |
| #define PCUBE_LUT 0xFC |
| #define PCUBE_INS 0xF8 |
| #define PCUBE_OPO 0xF4 |
| #define PCUBE_END 0xF2 |
| #define PCUBE_CLR 0xF1 |
| #define PCUBE_BIU 0xF0 |
| #define PCUBE_CSH 0xE0 |
| #define PCUBE_RegBase 0xC000 |
| #define PCUBE_RegSize 0x4000 |
| #define PCUBE_F2A64_QdeQ 0x0 |
| #define PCUBE_F2A64_IPRO 0x2 |
| #define PCUBE_F2A64_FLUSH 0x1 |
| #define PCUBE_F2A64_IPLUS 0x3 |
| #define PCUBE_F2A64_IPLUS_QMAT 0x4 |
| #define PCUBE_F2A64_SemChk 0x7 |
| #define PCUBE_F2A64_SemUpdf 0x8 |
| #define PCUBE_F2A64_BitOp0 0x20 |
| #define PCUBE_F2A64_BitOp1 0x21 |
| #define PCUBE_F2A64_BitOp2 0x22 |
| #define PCUBE_F2A64_BitOp3 0x23 |
| #define PCUBE_F3A64_Fop 0x0 |
| #define PCUBE_F3A64_FLUSH 0x1 |
| #define PCUBE_F3A64_neighbor 0x2 |
| #define PCUBE_F3A64_neighborAB 0x3 |
| #define PCUBE_F3A64_neighborCD 0x4 |
| #define PCUBE_F3A64_BwPmv 0x5 |
| #define PCUBE_F3A64_FwPmv 0x6 |
| #define PCUBE_F3A64_SemChk 0x7 |
| #define PCUBE_F3A64_SemUpd 0x8 |
| #define PCUBE_F3A64_IME 0x9 |
| #define PCUBE_F3A64_FME 0xA |
| #define PCUBE_F3A64_WME 0xB |
| #define PCUBE_F3A64_BitOp0 0x20 |
| #define PCUBE_F3A64_BitOp1 0x21 |
| #define PCUBE_F3A64_BitOp2 0x22 |
| #define PCUBE_F3A64_BitOp3 0x23 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_TCM 0x0000 |
| #define RA_PCUBE_tcm 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_FIGO 0x8000 |
| #define RA_PCUBE_figo 0x8000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_FIGO_CTLR 0xA000 |
| #define RA_PCUBE_figoCtlr 0xA000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_HBO 0xC000 |
| #define RA_PCUBE_hbo 0xC000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_SEMA 0xC700 |
| #define RA_PCUBE_semaHub 0xC700 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_CFG 0xCB00 |
| |
| #define BA_PCUBE_CFG_SelDP 0xCB00 |
| #define B16PCUBE_CFG_SelDP 0xCB00 |
| #define LSb32PCUBE_CFG_SelDP 0 |
| #define LSb16PCUBE_CFG_SelDP 0 |
| #define bPCUBE_CFG_SelDP 2 |
| #define MSK32PCUBE_CFG_SelDP 0x00000003 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_clkGateEn 0xCB04 |
| |
| #define BA_PCUBE_clkGateEn_meeSysClk 0xCB04 |
| #define B16PCUBE_clkGateEn_meeSysClk 0xCB04 |
| #define LSb32PCUBE_clkGateEn_meeSysClk 0 |
| #define LSb16PCUBE_clkGateEn_meeSysClk 0 |
| #define bPCUBE_clkGateEn_meeSysClk 1 |
| #define MSK32PCUBE_clkGateEn_meeSysClk 0x00000001 |
| |
| #define BA_PCUBE_clkGateEn_meeClk 0xCB04 |
| #define B16PCUBE_clkGateEn_meeClk 0xCB04 |
| #define LSb32PCUBE_clkGateEn_meeClk 1 |
| #define LSb16PCUBE_clkGateEn_meeClk 1 |
| #define bPCUBE_clkGateEn_meeClk 1 |
| #define MSK32PCUBE_clkGateEn_meeClk 0x00000002 |
| |
| #define BA_PCUBE_clkGateEn_iProSysClk 0xCB04 |
| #define B16PCUBE_clkGateEn_iProSysClk 0xCB04 |
| #define LSb32PCUBE_clkGateEn_iProSysClk 2 |
| #define LSb16PCUBE_clkGateEn_iProSysClk 2 |
| #define bPCUBE_clkGateEn_iProSysClk 1 |
| #define MSK32PCUBE_clkGateEn_iProSysClk 0x00000004 |
| |
| #define BA_PCUBE_clkGateEn_iProClk 0xCB04 |
| #define B16PCUBE_clkGateEn_iProClk 0xCB04 |
| #define LSb32PCUBE_clkGateEn_iProClk 3 |
| #define LSb16PCUBE_clkGateEn_iProClk 3 |
| #define bPCUBE_clkGateEn_iProClk 1 |
| #define MSK32PCUBE_clkGateEn_iProClk 0x00000008 |
| |
| #define BA_PCUBE_clkGateEn_pipe1Clk 0xCB04 |
| #define B16PCUBE_clkGateEn_pipe1Clk 0xCB04 |
| #define LSb32PCUBE_clkGateEn_pipe1Clk 4 |
| #define LSb16PCUBE_clkGateEn_pipe1Clk 4 |
| #define bPCUBE_clkGateEn_pipe1Clk 1 |
| #define MSK32PCUBE_clkGateEn_pipe1Clk 0x00000010 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_BASE 0xCB08 |
| |
| #define BA_PCUBE_BASE_CmdLUT 0xCB08 |
| #define B16PCUBE_BASE_CmdLUT 0xCB08 |
| #define LSb32PCUBE_BASE_CmdLUT 0 |
| #define LSb16PCUBE_BASE_CmdLUT 0 |
| #define bPCUBE_BASE_CmdLUT 10 |
| #define MSK32PCUBE_BASE_CmdLUT 0x000003FF |
| |
| #define BA_PCUBE_BASE_IRAM 0xCB09 |
| #define B16PCUBE_BASE_IRAM 0xCB08 |
| #define LSb32PCUBE_BASE_IRAM 10 |
| #define LSb16PCUBE_BASE_IRAM 10 |
| #define bPCUBE_BASE_IRAM 13 |
| #define MSK32PCUBE_BASE_IRAM 0x007FFC00 |
| |
| #define BA_PCUBE_BASE_OPO 0xCB0A |
| #define B16PCUBE_BASE_OPO 0xCB0A |
| #define LSb32PCUBE_BASE_OPO 23 |
| #define LSb16PCUBE_BASE_OPO 7 |
| #define bPCUBE_BASE_OPO 9 |
| #define MSK32PCUBE_BASE_OPO 0xFF800000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_RESET 0xCB0C |
| |
| #define BA_PCUBE_RESET_Enb 0xCB0C |
| #define B16PCUBE_RESET_Enb 0xCB0C |
| #define LSb32PCUBE_RESET_Enb 0 |
| #define LSb16PCUBE_RESET_Enb 0 |
| #define bPCUBE_RESET_Enb 1 |
| #define MSK32PCUBE_RESET_Enb 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_START 0xCB10 |
| |
| #define BA_PCUBE_START_Enb 0xCB10 |
| #define B16PCUBE_START_Enb 0xCB10 |
| #define LSb32PCUBE_START_Enb 0 |
| #define LSb16PCUBE_START_Enb 0 |
| #define bPCUBE_START_Enb 1 |
| #define MSK32PCUBE_START_Enb 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_STATUS 0xCB14 |
| |
| #define BA_PCUBE_STATUS_p3Clr 0xCB14 |
| #define B16PCUBE_STATUS_p3Clr 0xCB14 |
| #define LSb32PCUBE_STATUS_p3Clr 0 |
| #define LSb16PCUBE_STATUS_p3Clr 0 |
| #define bPCUBE_STATUS_p3Clr 1 |
| #define MSK32PCUBE_STATUS_p3Clr 0x00000001 |
| |
| #define BA_PCUBE_STATUS_p3Clr1 0xCB14 |
| #define B16PCUBE_STATUS_p3Clr1 0xCB14 |
| #define LSb32PCUBE_STATUS_p3Clr1 1 |
| #define LSb16PCUBE_STATUS_p3Clr1 1 |
| #define bPCUBE_STATUS_p3Clr1 1 |
| #define MSK32PCUBE_STATUS_p3Clr1 0x00000002 |
| |
| #define BA_PCUBE_STATUS_PendingCmd 0xCB14 |
| #define B16PCUBE_STATUS_PendingCmd 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingCmd 2 |
| #define LSb16PCUBE_STATUS_PendingCmd 2 |
| #define bPCUBE_STATUS_PendingCmd 1 |
| #define MSK32PCUBE_STATUS_PendingCmd 0x00000004 |
| |
| #define BA_PCUBE_STATUS_SemID 0xCB14 |
| #define B16PCUBE_STATUS_SemID 0xCB14 |
| #define LSb32PCUBE_STATUS_SemID 3 |
| #define LSb16PCUBE_STATUS_SemID 3 |
| #define bPCUBE_STATUS_SemID 5 |
| #define MSK32PCUBE_STATUS_SemID 0x000000F8 |
| |
| #define BA_PCUBE_STATUS_semOp 0xCB15 |
| #define B16PCUBE_STATUS_semOp 0xCB14 |
| #define LSb32PCUBE_STATUS_semOp 8 |
| #define LSb16PCUBE_STATUS_semOp 8 |
| #define bPCUBE_STATUS_semOp 1 |
| #define MSK32PCUBE_STATUS_semOp 0x00000100 |
| |
| #define BA_PCUBE_STATUS_PendingRdQ 0xCB15 |
| #define B16PCUBE_STATUS_PendingRdQ 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingRdQ 9 |
| #define LSb16PCUBE_STATUS_PendingRdQ 9 |
| #define bPCUBE_STATUS_PendingRdQ 1 |
| #define MSK32PCUBE_STATUS_PendingRdQ 0x00000200 |
| |
| #define BA_PCUBE_STATUS_PendingIns 0xCB15 |
| #define B16PCUBE_STATUS_PendingIns 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingIns 10 |
| #define LSb16PCUBE_STATUS_PendingIns 10 |
| #define bPCUBE_STATUS_PendingIns 1 |
| #define MSK32PCUBE_STATUS_PendingIns 0x00000400 |
| |
| #define BA_PCUBE_STATUS_PendingInsQ 0xCB15 |
| #define B16PCUBE_STATUS_PendingInsQ 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingInsQ 11 |
| #define LSb16PCUBE_STATUS_PendingInsQ 11 |
| #define bPCUBE_STATUS_PendingInsQ 1 |
| #define MSK32PCUBE_STATUS_PendingInsQ 0x00000800 |
| |
| #define BA_PCUBE_STATUS_PendingWrQ 0xCB15 |
| #define B16PCUBE_STATUS_PendingWrQ 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingWrQ 12 |
| #define LSb16PCUBE_STATUS_PendingWrQ 12 |
| #define bPCUBE_STATUS_PendingWrQ 1 |
| #define MSK32PCUBE_STATUS_PendingWrQ 0x00001000 |
| |
| #define BA_PCUBE_STATUS_PendingSyncQ 0xCB15 |
| #define B16PCUBE_STATUS_PendingSyncQ 0xCB14 |
| #define LSb32PCUBE_STATUS_PendingSyncQ 13 |
| #define LSb16PCUBE_STATUS_PendingSyncQ 13 |
| #define bPCUBE_STATUS_PendingSyncQ 1 |
| #define MSK32PCUBE_STATUS_PendingSyncQ 0x00002000 |
| |
| #define BA_PCUBE_STATUS_RABusy 0xCB15 |
| #define B16PCUBE_STATUS_RABusy 0xCB14 |
| #define LSb32PCUBE_STATUS_RABusy 14 |
| #define LSb16PCUBE_STATUS_RABusy 14 |
| #define bPCUBE_STATUS_RABusy 2 |
| #define MSK32PCUBE_STATUS_RABusy 0x0000C000 |
| |
| #define BA_PCUBE_STATUS_WABusy 0xCB16 |
| #define B16PCUBE_STATUS_WABusy 0xCB16 |
| #define LSb32PCUBE_STATUS_WABusy 16 |
| #define LSb16PCUBE_STATUS_WABusy 0 |
| #define bPCUBE_STATUS_WABusy 2 |
| #define MSK32PCUBE_STATUS_WABusy 0x00030000 |
| |
| #define BA_PCUBE_STATUS_DataRcvBusy 0xCB16 |
| #define B16PCUBE_STATUS_DataRcvBusy 0xCB16 |
| #define LSb32PCUBE_STATUS_DataRcvBusy 18 |
| #define LSb16PCUBE_STATUS_DataRcvBusy 2 |
| #define bPCUBE_STATUS_DataRcvBusy 1 |
| #define MSK32PCUBE_STATUS_DataRcvBusy 0x00040000 |
| |
| #define BA_PCUBE_STATUS_VFMTBusy 0xCB16 |
| #define B16PCUBE_STATUS_VFMTBusy 0xCB16 |
| #define LSb32PCUBE_STATUS_VFMTBusy 19 |
| #define LSb16PCUBE_STATUS_VFMTBusy 3 |
| #define bPCUBE_STATUS_VFMTBusy 1 |
| #define MSK32PCUBE_STATUS_VFMTBusy 0x00080000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_VFMT 0xCB18 |
| #define RA_PCUBE_vFmt 0xCB18 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_PCNT 0xCB7C |
| #define RA_PCUBE_pCnt 0xCB7C |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_PCNT1 0xCB98 |
| #define RA_PCUBE_pCnt1 0xCB98 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_DP0 0x10000 |
| #define RA_PCUBE_ticEx 0x10000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_DP1 0x18000 |
| #define RA_PCUBE_ticEx1 0x18000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_IRAM 0x30000 |
| #define RA_PCUBE_iram 0x30000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_DMEM 0x40000 |
| #define RA_PCUBE_dmem 0x40000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_CmdLUT 0x48000 |
| #define RA_PCUBE_cmdlut 0x48000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_CmdLUT1 0x49000 |
| #define RA_PCUBE_cmdlut1 0x49000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_ITCM 0x50000 |
| #define RA_PCUBE_itcm 0x50000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_ITCM1 0x54000 |
| #define RA_PCUBE_itcm1 0x54000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_QMTX 0x56000 |
| #define RA_PCUBE_qmtx 0x56000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_DQMTX 0x56200 |
| #define RA_PCUBE_dqmtx 0x56200 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_RNDMTX 0x56800 |
| #define RA_PCUBE_rndmtx 0x56800 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_SSDMTX 0x57000 |
| #define RA_PCUBE_ssdmtx 0x57000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_IPRO 0x58000 |
| #define RA_PCUBE_iprobiu 0x58000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCUBE_PFMT 0x5C000 |
| #define RA_PCUBE_pixFmt 0x5C000 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_PCUBE { |
| /////////////////////////////////////////////////////////// |
| SIE_FigoData ie_tcm[1024]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx2000 [24576]; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg ie_figo; |
| /////////////////////////////////////////////////////////// |
| SIE_FigoReg ie_figoCtlr; |
| /////////////////////////////////////////////////////////// |
| SIE_HBO ie_hbo; |
| /////////////////////////////////////////////////////////// |
| SIE_SemaHub ie_semaHub; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_CFG_SelDP(r32) _BFGET_(r32, 1, 0) |
| #define SET32PCUBE_CFG_SelDP(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16PCUBE_CFG_SelDP(r16) _BFGET_(r16, 1, 0) |
| #define SET16PCUBE_CFG_SelDP(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define w32PCUBE_CFG {\ |
| UNSG32 uCFG_SelDP : 2;\ |
| UNSG32 RSVDxCB00_b2 : 30;\ |
| } |
| union { UNSG32 u32PCUBE_CFG; |
| struct w32PCUBE_CFG; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_clkGateEn_meeSysClk(r32) _BFGET_(r32, 0, 0) |
| #define SET32PCUBE_clkGateEn_meeSysClk(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16PCUBE_clkGateEn_meeSysClk(r16) _BFGET_(r16, 0, 0) |
| #define SET16PCUBE_clkGateEn_meeSysClk(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32PCUBE_clkGateEn_meeClk(r32) _BFGET_(r32, 1, 1) |
| #define SET32PCUBE_clkGateEn_meeClk(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16PCUBE_clkGateEn_meeClk(r16) _BFGET_(r16, 1, 1) |
| #define SET16PCUBE_clkGateEn_meeClk(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32PCUBE_clkGateEn_iProSysClk(r32) _BFGET_(r32, 2, 2) |
| #define SET32PCUBE_clkGateEn_iProSysClk(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16PCUBE_clkGateEn_iProSysClk(r16) _BFGET_(r16, 2, 2) |
| #define SET16PCUBE_clkGateEn_iProSysClk(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32PCUBE_clkGateEn_iProClk(r32) _BFGET_(r32, 3, 3) |
| #define SET32PCUBE_clkGateEn_iProClk(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16PCUBE_clkGateEn_iProClk(r16) _BFGET_(r16, 3, 3) |
| #define SET16PCUBE_clkGateEn_iProClk(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32PCUBE_clkGateEn_pipe1Clk(r32) _BFGET_(r32, 4, 4) |
| #define SET32PCUBE_clkGateEn_pipe1Clk(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16PCUBE_clkGateEn_pipe1Clk(r16) _BFGET_(r16, 4, 4) |
| #define SET16PCUBE_clkGateEn_pipe1Clk(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32PCUBE_clkGateEn {\ |
| UNSG32 uclkGateEn_meeSysClk : 1;\ |
| UNSG32 uclkGateEn_meeClk : 1;\ |
| UNSG32 uclkGateEn_iProSysClk : 1;\ |
| UNSG32 uclkGateEn_iProClk : 1;\ |
| UNSG32 uclkGateEn_pipe1Clk : 1;\ |
| UNSG32 RSVDxCB04_b5 : 27;\ |
| } |
| union { UNSG32 u32PCUBE_clkGateEn; |
| struct w32PCUBE_clkGateEn; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_BASE_CmdLUT(r32) _BFGET_(r32, 9, 0) |
| #define SET32PCUBE_BASE_CmdLUT(r32,v) _BFSET_(r32, 9, 0,v) |
| #define GET16PCUBE_BASE_CmdLUT(r16) _BFGET_(r16, 9, 0) |
| #define SET16PCUBE_BASE_CmdLUT(r16,v) _BFSET_(r16, 9, 0,v) |
| |
| #define GET32PCUBE_BASE_IRAM(r32) _BFGET_(r32,22,10) |
| #define SET32PCUBE_BASE_IRAM(r32,v) _BFSET_(r32,22,10,v) |
| |
| #define GET32PCUBE_BASE_OPO(r32) _BFGET_(r32,31,23) |
| #define SET32PCUBE_BASE_OPO(r32,v) _BFSET_(r32,31,23,v) |
| #define GET16PCUBE_BASE_OPO(r16) _BFGET_(r16,15, 7) |
| #define SET16PCUBE_BASE_OPO(r16,v) _BFSET_(r16,15, 7,v) |
| |
| #define w32PCUBE_BASE {\ |
| UNSG32 uBASE_CmdLUT : 10;\ |
| UNSG32 uBASE_IRAM : 13;\ |
| UNSG32 uBASE_OPO : 9;\ |
| } |
| union { UNSG32 u32PCUBE_BASE; |
| struct w32PCUBE_BASE; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_RESET_Enb(r32) _BFGET_(r32, 0, 0) |
| #define SET32PCUBE_RESET_Enb(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16PCUBE_RESET_Enb(r16) _BFGET_(r16, 0, 0) |
| #define SET16PCUBE_RESET_Enb(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32PCUBE_RESET {\ |
| UNSG32 uRESET_Enb : 1;\ |
| UNSG32 RSVDxCB0C_b1 : 31;\ |
| } |
| union { UNSG32 u32PCUBE_RESET; |
| struct w32PCUBE_RESET; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_START_Enb(r32) _BFGET_(r32, 0, 0) |
| #define SET32PCUBE_START_Enb(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16PCUBE_START_Enb(r16) _BFGET_(r16, 0, 0) |
| #define SET16PCUBE_START_Enb(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32PCUBE_START {\ |
| UNSG32 uSTART_Enb : 1;\ |
| UNSG32 RSVDxCB10_b1 : 31;\ |
| } |
| union { UNSG32 u32PCUBE_START; |
| struct w32PCUBE_START; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32PCUBE_STATUS_p3Clr(r32) _BFGET_(r32, 0, 0) |
| #define SET32PCUBE_STATUS_p3Clr(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16PCUBE_STATUS_p3Clr(r16) _BFGET_(r16, 0, 0) |
| #define SET16PCUBE_STATUS_p3Clr(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32PCUBE_STATUS_p3Clr1(r32) _BFGET_(r32, 1, 1) |
| #define SET32PCUBE_STATUS_p3Clr1(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16PCUBE_STATUS_p3Clr1(r16) _BFGET_(r16, 1, 1) |
| #define SET16PCUBE_STATUS_p3Clr1(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32PCUBE_STATUS_PendingCmd(r32) _BFGET_(r32, 2, 2) |
| #define SET32PCUBE_STATUS_PendingCmd(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16PCUBE_STATUS_PendingCmd(r16) _BFGET_(r16, 2, 2) |
| #define SET16PCUBE_STATUS_PendingCmd(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32PCUBE_STATUS_SemID(r32) _BFGET_(r32, 7, 3) |
| #define SET32PCUBE_STATUS_SemID(r32,v) _BFSET_(r32, 7, 3,v) |
| #define GET16PCUBE_STATUS_SemID(r16) _BFGET_(r16, 7, 3) |
| #define SET16PCUBE_STATUS_SemID(r16,v) _BFSET_(r16, 7, 3,v) |
| |
| #define GET32PCUBE_STATUS_semOp(r32) _BFGET_(r32, 8, 8) |
| #define SET32PCUBE_STATUS_semOp(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16PCUBE_STATUS_semOp(r16) _BFGET_(r16, 8, 8) |
| #define SET16PCUBE_STATUS_semOp(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32PCUBE_STATUS_PendingRdQ(r32) _BFGET_(r32, 9, 9) |
| #define SET32PCUBE_STATUS_PendingRdQ(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16PCUBE_STATUS_PendingRdQ(r16) _BFGET_(r16, 9, 9) |
| #define SET16PCUBE_STATUS_PendingRdQ(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32PCUBE_STATUS_PendingIns(r32) _BFGET_(r32,10,10) |
| #define SET32PCUBE_STATUS_PendingIns(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16PCUBE_STATUS_PendingIns(r16) _BFGET_(r16,10,10) |
| #define SET16PCUBE_STATUS_PendingIns(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32PCUBE_STATUS_PendingInsQ(r32) _BFGET_(r32,11,11) |
| #define SET32PCUBE_STATUS_PendingInsQ(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16PCUBE_STATUS_PendingInsQ(r16) _BFGET_(r16,11,11) |
| #define SET16PCUBE_STATUS_PendingInsQ(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32PCUBE_STATUS_PendingWrQ(r32) _BFGET_(r32,12,12) |
| #define SET32PCUBE_STATUS_PendingWrQ(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16PCUBE_STATUS_PendingWrQ(r16) _BFGET_(r16,12,12) |
| #define SET16PCUBE_STATUS_PendingWrQ(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32PCUBE_STATUS_PendingSyncQ(r32) _BFGET_(r32,13,13) |
| #define SET32PCUBE_STATUS_PendingSyncQ(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16PCUBE_STATUS_PendingSyncQ(r16) _BFGET_(r16,13,13) |
| #define SET16PCUBE_STATUS_PendingSyncQ(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32PCUBE_STATUS_RABusy(r32) _BFGET_(r32,15,14) |
| #define SET32PCUBE_STATUS_RABusy(r32,v) _BFSET_(r32,15,14,v) |
| #define GET16PCUBE_STATUS_RABusy(r16) _BFGET_(r16,15,14) |
| #define SET16PCUBE_STATUS_RABusy(r16,v) _BFSET_(r16,15,14,v) |
| |
| #define GET32PCUBE_STATUS_WABusy(r32) _BFGET_(r32,17,16) |
| #define SET32PCUBE_STATUS_WABusy(r32,v) _BFSET_(r32,17,16,v) |
| #define GET16PCUBE_STATUS_WABusy(r16) _BFGET_(r16, 1, 0) |
| #define SET16PCUBE_STATUS_WABusy(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define GET32PCUBE_STATUS_DataRcvBusy(r32) _BFGET_(r32,18,18) |
| #define SET32PCUBE_STATUS_DataRcvBusy(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16PCUBE_STATUS_DataRcvBusy(r16) _BFGET_(r16, 2, 2) |
| #define SET16PCUBE_STATUS_DataRcvBusy(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32PCUBE_STATUS_VFMTBusy(r32) _BFGET_(r32,19,19) |
| #define SET32PCUBE_STATUS_VFMTBusy(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16PCUBE_STATUS_VFMTBusy(r16) _BFGET_(r16, 3, 3) |
| #define SET16PCUBE_STATUS_VFMTBusy(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32PCUBE_STATUS {\ |
| UNSG32 uSTATUS_p3Clr : 1;\ |
| UNSG32 uSTATUS_p3Clr1 : 1;\ |
| UNSG32 uSTATUS_PendingCmd : 1;\ |
| UNSG32 uSTATUS_SemID : 5;\ |
| UNSG32 uSTATUS_semOp : 1;\ |
| UNSG32 uSTATUS_PendingRdQ : 1;\ |
| UNSG32 uSTATUS_PendingIns : 1;\ |
| UNSG32 uSTATUS_PendingInsQ : 1;\ |
| UNSG32 uSTATUS_PendingWrQ : 1;\ |
| UNSG32 uSTATUS_PendingSyncQ : 1;\ |
| UNSG32 uSTATUS_RABusy : 2;\ |
| UNSG32 uSTATUS_WABusy : 2;\ |
| UNSG32 uSTATUS_DataRcvBusy : 1;\ |
| UNSG32 uSTATUS_VFMTBusy : 1;\ |
| UNSG32 RSVDxCB14_b20 : 12;\ |
| } |
| union { UNSG32 u32PCUBE_STATUS; |
| struct w32PCUBE_STATUS; |
| }; |
| /////////////////////////////////////////////////////////// |
| SIE_P3vFmt ie_vFmt; |
| /////////////////////////////////////////////////////////// |
| SIE_P3pCnt ie_pCnt; |
| /////////////////////////////////////////////////////////// |
| SIE_P3pCnt ie_pCnt1; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDxCBB4 [13388]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3ticEx ie_ticEx; |
| /////////////////////////////////////////////////////////// |
| SIE_P3ticEx ie_ticEx1; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx20000 [65536]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3IRAM ie_iram; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx32000 [57344]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3DMEM ie_dmem; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx44000 [16384]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3CLUT ie_cmdlut; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx48400 [3072]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3CLUT ie_cmdlut1; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx49400 [27648]; |
| /////////////////////////////////////////////////////////// |
| SIE_P3FigoITCM ie_itcm; |
| /////////////////////////////////////////////////////////// |
| SIE_ITCM ie_itcm1; |
| /////////////////////////////////////////////////////////// |
| SIE_QMatrix ie_qmtx; |
| /////////////////////////////////////////////////////////// |
| SIE_deQMatrix ie_dqmtx; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx56400 [1024]; |
| /////////////////////////////////////////////////////////// |
| SIE_RoundMatrix ie_rndmtx; |
| /////////////////////////////////////////////////////////// |
| SIE_ScaleMatrix ie_ssdmtx; |
| UNSG8 RSVD_ssdmtx [256]; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx57400 [3072]; |
| /////////////////////////////////////////////////////////// |
| SIE_IPROBIU ie_iprobiu; |
| /////////////////////////////////////////////////////////// |
| SIE_pixFmtReg ie_pixFmt; |
| /////////////////////////////////////////////////////////// |
| UNSG8 RSVDx5C0D0 [16176]; |
| /////////////////////////////////////////////////////////// |
| } SIE_PCUBE; |
| |
| typedef union T32PCUBE_CFG |
| { UNSG32 u32; |
| struct w32PCUBE_CFG; |
| } T32PCUBE_CFG; |
| typedef union T32PCUBE_clkGateEn |
| { UNSG32 u32; |
| struct w32PCUBE_clkGateEn; |
| } T32PCUBE_clkGateEn; |
| typedef union T32PCUBE_BASE |
| { UNSG32 u32; |
| struct w32PCUBE_BASE; |
| } T32PCUBE_BASE; |
| typedef union T32PCUBE_RESET |
| { UNSG32 u32; |
| struct w32PCUBE_RESET; |
| } T32PCUBE_RESET; |
| typedef union T32PCUBE_START |
| { UNSG32 u32; |
| struct w32PCUBE_START; |
| } T32PCUBE_START; |
| typedef union T32PCUBE_STATUS |
| { UNSG32 u32; |
| struct w32PCUBE_STATUS; |
| } T32PCUBE_STATUS; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TPCUBE_CFG |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_CFG; |
| }; |
| } TPCUBE_CFG; |
| typedef union TPCUBE_clkGateEn |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_clkGateEn; |
| }; |
| } TPCUBE_clkGateEn; |
| typedef union TPCUBE_BASE |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_BASE; |
| }; |
| } TPCUBE_BASE; |
| typedef union TPCUBE_RESET |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_RESET; |
| }; |
| } TPCUBE_RESET; |
| typedef union TPCUBE_START |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_START; |
| }; |
| } TPCUBE_START; |
| typedef union TPCUBE_STATUS |
| { UNSG32 u32[1]; |
| struct { |
| struct w32PCUBE_STATUS; |
| }; |
| } TPCUBE_STATUS; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 PCUBE_drvrd(SIE_PCUBE *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 PCUBE_drvwr(SIE_PCUBE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void PCUBE_reset(SIE_PCUBE *p); |
| SIGN32 PCUBE_cmp (SIE_PCUBE *p, SIE_PCUBE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define PCUBE_check(p,pie,pfx,hLOG) PCUBE_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define PCUBE_print(p, pfx,hLOG) PCUBE_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: PCUBE |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE p3ClkRst biu (4,4) |
| /// ### |
| /// * Pcube level clock reset control unit |
| /// * For all reset control bit, 0-- reset, 1-- release. After chip power on reset, all these registers are 0 which means the vPro subsystem is in reset state and should be kicked-off by CPU. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 (P) |
| /// # 0x00000 global |
| /// $ClkRstBiu global REG |
| /// @ 0x00004 (P) |
| /// # 0x00004 p3Pipe_0 |
| /// $ClkRstBiu p3Pipe_0 REG |
| /// @ 0x00008 (P) |
| /// # 0x00008 p3Pipe_1 |
| /// $ClkRstBiu p3Pipe_1 REG |
| /// @ 0x0000C (P) |
| /// # 0x0000C iPro |
| /// $ClkRstBiu iPro REG |
| /// @ 0x00010 (P) |
| /// # 0x00010 mee |
| /// $ClkRstBiu mee REG |
| /// @ 0x00014 (P) |
| /// # 0x00014 nlTop |
| /// $ClkRstBiu nlTop REG |
| /// @ 0x00018 (P) |
| /// # 0x00018 fop |
| /// $ClkRstBiu fop REG |
| /// @ 0x0001C (P) |
| /// # 0x0001C pmv |
| /// $ClkRstBiu pmv REG |
| /// @ 0x00020 (P) |
| /// # 0x00020 bitOp_0 |
| /// $ClkRstBiu bitOp_0 REG |
| /// @ 0x00024 (P) |
| /// # 0x00024 bitOp_1 |
| /// $ClkRstBiu bitOp_1 REG |
| /// @ 0x00028 (P) |
| /// # 0x00028 semaExt_0 |
| /// $ClkRstBiu semaExt_0 REG |
| /// @ 0x0002C (P) |
| /// # 0x0002C semaExt_1 |
| /// $ClkRstBiu semaExt_1 REG |
| /// @ 0x00030 (P) |
| /// # 0x00030 p3Figo0 |
| /// $ClkRstBiu p3Figo0 REG |
| /// @ 0x00034 (P) |
| /// # 0x00034 p3Figo1 |
| /// $ClkRstBiu p3Figo1 REG |
| /// @ 0x00038 (P) |
| /// # 0x00038 p3Alu64_0 |
| /// $ClkRstBiu p3Alu64_0 REG |
| /// @ 0x0003C (P) |
| /// # 0x0003C p3Alu64_1 |
| /// $ClkRstBiu p3Alu64_1 REG |
| /// @ 0x00040 (P) |
| /// # 0x00040 p3RF64_0 |
| /// $ClkRstBiu p3RF64_0 REG |
| /// @ 0x00044 (P) |
| /// # 0x00044 p3RF64_1 |
| /// $ClkRstBiu p3RF64_1 REG |
| /// @ 0x00048 (P) |
| /// # 0x00048 p3Biu |
| /// $ClkRstBiu p3Biu REG |
| /// @ 0x0004C (P) |
| /// # 0x0004C p3F0Itcm |
| /// $ClkRstBiu p3F0Itcm REG |
| /// @ 0x00050 (P) |
| /// # 0x00050 p3F1Itcm |
| /// $ClkRstBiu p3F1Itcm REG |
| /// @ 0x00054 (P) |
| /// # 0x00054 p3Dtcm |
| /// $ClkRstBiu p3Dtcm REG |
| /// @ 0x00058 (P) |
| /// # 0x00058 misc |
| /// $ClkRstBiu misc REG |
| /// ### |
| /// * For p3Figo0/1, only sw clock enable is used and dynamic clock control will not be applied,. |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 92B, bits: 69b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_p3ClkRst |
| #define h_p3ClkRst (){} |
| |
| #define RA_p3ClkRst_global 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Pipe_0 0x0004 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Pipe_1 0x0008 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_iPro 0x000C |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_mee 0x0010 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_nlTop 0x0014 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_fop 0x0018 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_pmv 0x001C |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_bitOp_0 0x0020 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_bitOp_1 0x0024 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_semaExt_0 0x0028 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_semaExt_1 0x002C |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Figo0 0x0030 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Figo1 0x0034 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Alu64_0 0x0038 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Alu64_1 0x003C |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3RF64_0 0x0040 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3RF64_1 0x0044 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Biu 0x0048 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3F0Itcm 0x004C |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3F1Itcm 0x0050 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_p3Dtcm 0x0054 |
| /////////////////////////////////////////////////////////// |
| #define RA_p3ClkRst_misc 0x0058 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_p3ClkRst { |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_global; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Pipe_0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Pipe_1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_iPro; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_mee; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_nlTop; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_fop; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_pmv; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_bitOp_0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_bitOp_1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_semaExt_0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_semaExt_1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Figo0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Figo1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Alu64_0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Alu64_1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3RF64_0; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3RF64_1; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Biu; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3F0Itcm; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3F1Itcm; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_p3Dtcm; |
| /////////////////////////////////////////////////////////// |
| SIE_ClkRstBiu ie_misc; |
| /////////////////////////////////////////////////////////// |
| } SIE_p3ClkRst; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 p3ClkRst_drvrd(SIE_p3ClkRst *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 p3ClkRst_drvwr(SIE_p3ClkRst *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void p3ClkRst_reset(SIE_p3ClkRst *p); |
| SIGN32 p3ClkRst_cmp (SIE_p3ClkRst *p, SIE_p3ClkRst *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define p3ClkRst_check(p,pie,pfx,hLOG) p3ClkRst_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define p3ClkRst_print(p, pfx,hLOG) p3ClkRst_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: p3ClkRst |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE P3BIU (4,4) |
| /// ### |
| /// * Constants for vScope submodule hSel decoding |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// : SIZE 0x100000 |
| /// : DEC_BIT 0x14 |
| /// ### |
| /// * PCUBE |
| /// ### |
| /// : P3_OFST 0x0 |
| /// : P3_SIZE 0xF0000 |
| /// : P3_DEC_BIT 0x10 |
| /// ### |
| /// * P3CR |
| /// ### |
| /// : P3CR_OFST 0xF0000 |
| /// : P3CR_SIZE 0x10000 |
| /// : P3CR_DEC_BIT 0x10 |
| /// @ 0x00000 Dummy (P) |
| /// %unsigned 1 xxx 0x0 |
| /// %% 31 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 1b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_P3BIU |
| #define h_P3BIU (){} |
| |
| #define P3BIU_SIZE 0x100000 |
| #define P3BIU_DEC_BIT 0x14 |
| #define P3BIU_P3_OFST 0x0 |
| #define P3BIU_P3_SIZE 0xF0000 |
| #define P3BIU_P3_DEC_BIT 0x10 |
| #define P3BIU_P3CR_OFST 0xF0000 |
| #define P3BIU_P3CR_SIZE 0x10000 |
| #define P3BIU_P3CR_DEC_BIT 0x10 |
| /////////////////////////////////////////////////////////// |
| #define RA_P3BIU_Dummy 0x0000 |
| |
| #define BA_P3BIU_Dummy_xxx 0x0000 |
| #define B16P3BIU_Dummy_xxx 0x0000 |
| #define LSb32P3BIU_Dummy_xxx 0 |
| #define LSb16P3BIU_Dummy_xxx 0 |
| #define bP3BIU_Dummy_xxx 1 |
| #define MSK32P3BIU_Dummy_xxx 0x00000001 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_P3BIU { |
| /////////////////////////////////////////////////////////// |
| #define GET32P3BIU_Dummy_xxx(r32) _BFGET_(r32, 0, 0) |
| #define SET32P3BIU_Dummy_xxx(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16P3BIU_Dummy_xxx(r16) _BFGET_(r16, 0, 0) |
| #define SET16P3BIU_Dummy_xxx(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32P3BIU_Dummy {\ |
| UNSG32 uDummy_xxx : 1;\ |
| UNSG32 RSVDx0_b1 : 31;\ |
| } |
| union { UNSG32 u32P3BIU_Dummy; |
| struct w32P3BIU_Dummy; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_P3BIU; |
| |
| typedef union T32P3BIU_Dummy |
| { UNSG32 u32; |
| struct w32P3BIU_Dummy; |
| } T32P3BIU_Dummy; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TP3BIU_Dummy |
| { UNSG32 u32[1]; |
| struct { |
| struct w32P3BIU_Dummy; |
| }; |
| } TP3BIU_Dummy; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 P3BIU_drvrd(SIE_P3BIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 P3BIU_drvwr(SIE_P3BIU *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void P3BIU_reset(SIE_P3BIU *p); |
| SIGN32 P3BIU_cmp (SIE_P3BIU *p, SIE_P3BIU *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define P3BIU_check(p,pie,pfx,hLOG) P3BIU_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define P3BIU_print(p, pfx,hLOG) P3BIU_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: P3BIU |
| //////////////////////////////////////////////////////////// |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
| ////// |
| /// ENDOFFILE: pcube_spec.h |
| //////////////////////////////////////////////////////////// |
| |