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nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP / global.h
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/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: global.h
////////////////////////////////////////////////////////////
#ifndef global_h
#define global_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE pll (4,4)
/// ###
/// * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
/// * adding in a fixed frequency offset in about 1 ppm/step resolution.
/// * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
/// * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
/// * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
/// * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
/// * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
/// * M: Reference Divider: 1 to 511.
/// * N: Feedback Divider: 1 to 511.
/// * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
/// * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
/// * Divider value = 1 1,2,3,4….128.
/// * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
/// * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
/// * applicable only in the low power mode and cannot be used with the SSC function. In order to
/// * use the SSC function VCO must be operated above 1.5GHz.
/// * .. Cycle to Cycle Jitter (max): <30 ps.
/// * .. Programmable Reference and Feedback Divider.
/// * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
/// * Divider setting.
/// * .. SSC frequency range: 30 KHz ~ 100 KHz
/// * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
/// * .. Supporting both down-spread and center-spread modes.
/// * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
/// * .. Locking time: < 50 us
/// * .. Process Node: 28 nm LP
/// * .. Analog Power Supply: 1.8 V (+10%, -5%)
/// * .. Digital Power Supply: 1.05 V (±10%)
/// * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
/// * .. Output Duty Cycle: 45% - 55% for any post divider ratio
/// * .. Built-in Bandgap circuit.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * PLL Control register
/// ###
/// %unsigned 1 PU 0x1
/// ###
/// * PLL Power-Up
/// * 1: power up.
/// * 0: power down.
/// ###
/// %unsigned 1 RESET 0x0
/// ###
/// * Power On Reset. Active high, reset PLL and all logic.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 AVDD1815_SEL 0x1
/// ###
/// * AVDD Select.
/// * Selects whether AVDD is 1.8V
/// * or 1.5V.
/// * 1: 1.8V
/// * 0: 1.5V
/// ###
/// %unsigned 9 REFDIV 0x2
/// ###
/// * Reference Clock Divider
/// * Select.
/// * Divider = REFDIV[8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * REFDIV[8:0] range is 1~250
/// ###
/// %unsigned 9 FBDIV 0x20
/// ###
/// * Feedback Clock Divider Select.
/// * Divider= FBDIV [8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * FBDIV range is 9 to 94
/// ###
/// %unsigned 2 VDDM 0x1
/// ###
/// * VCO Supply Control.
/// * 11: 1.3 V
/// * 10: 1.25 V
/// * 01: 1.2 V
/// * 00: 1.15 V.
/// ###
/// %unsigned 3 VDDL 0x4
/// ###
/// * Internal VDD Supply
/// * Control.
/// * 000:0.9V
/// * 001:0.95V
/// * 010:1V
/// * 011:1.05V
/// * 100:1.1V
/// * 101:1.15V
/// * 110:1.2V
/// * 111:1.2V.
/// ###
/// %unsigned 4 ICP 0x1
/// ###
/// * Charge-pump Current Control Bits.
/// * 0000: 3 uA
/// * 0001: 3.75 uA
/// * 0010: 4.5 uA
/// * 0011: 5.25 uA
/// * 0100: 6 uA
/// * 0101: 7.5 uA
/// * 0110: 9 uA
/// * 0111: 10.5 uA
/// * 1000: 12 uA
/// * 1001: 15 uA
/// * 1010: 18 uA
/// * 1011: 21 uA
/// * 1100: 24 uA
/// * 1101: 30 uA
/// * 1110: 36 uA
/// * 1111: 42 uA.
/// * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
/// * If PU_BW_SEL = 1, then increase ICP value by 2x
/// ###
/// %unsigned 1 PLL_BW_SEL 0x0
/// ###
/// * PLL Bandwidth Select.
/// * 1: BW x 2
/// * 0: Normal PLL bandwidth.
/// * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
/// * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 4 KVCO 0xA
/// ###
/// * KVCO Frequency Range
/// * Select.
/// * 0000~0111: Reserved.
/// * 1000:1.2GHz ~ 1.35GHz
/// * 1001:1.35GHz ~ 1.5GHz
/// * 1010:1.5GHz ~ 1.75GHz
/// * 1011:1.75GHz ~ 2.00GHz
/// * 1100: 2GHz ~ 2.2GHz
/// * 1101: 2.2GHz ~ 2.4GHz
/// * 1110: 2.4GHz ~ 2.6GHz
/// * 1111: 2.6GHz ~ 3GHz
/// * SSC mode is only supported for frequency >=2 GHz
/// * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
/// ###
/// %unsigned 2 CTUNE 0x1
/// ###
/// * VCO Capacitor Select.
/// * 00: No Cap Loading
/// * 01: One Unit Cap Loading
/// * 10: Two Unit Cap Loading
/// * 11: Three Unit Cap Loading.
/// ###
/// %unsigned 3 CLKOUT_DIFF_DIV_SEL 0x2
/// ###
/// * Post Divider For Differential
/// * Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 3 CLKOUT_SE_DIV_SEL 0x2
/// ###
/// * Post Divider For
/// * Single-ended Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 1 CLKOUT_SOURCE_SEL 0x1
/// ###
/// * Differential Clock And
/// * Single-ended Clock Source Control.
/// * 0: from the phase interpolator.
/// * 1: from VCO directly.
/// * Note: This is used in test mode only. Select ‘1’ for normal operation.
/// ###
/// %unsigned 1 CLKOUT_DIFF_EN 0x1
/// ###
/// * Differential Clock Enable.
/// * 0:Disable differential clock
/// * 1:Enable differential clock
/// ###
/// %unsigned 1 BYPASS_EN 0x0
/// ###
/// * PLL Clock Bypass Enable.
/// * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
/// * 0: CLKOUT is derived from the PLL clock.
/// * NOTE: Bypass only works for the single ended clock.
/// * If BYPASS_EN==1. CLKOUT= REFCLK.
/// * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
/// ###
/// %unsigned 1 CLKOUT_SE_GATING_EN 0x0
/// ###
/// * Clock Output Gating Control.
/// * Selection for using the PLL lock signal to gate the output clock.
/// * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
/// * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
/// ###
/// %unsigned 1 FBCLK_EXT_SEL 0x0
/// ###
/// * External Or Internal Feedback
/// * Clock Select.
/// * 0: select internal feedback clock
/// * 1: select external feedback clock.
/// * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
/// ###
/// %unsigned 6 FBCDLY 0x0
/// ###
/// * Fine Tune Delay Select
/// * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
/// * FBCDLY[5] is the sign bit.
/// * 1 = FBCLK_EXT will lag REFCLK.
/// * 0 = FBCLK_EXT will lead REFCLK.
/// * FBCDLY[4:0] decides the actual amount of delay.
/// * 00000: No delay.
/// * Each additional step has these
/// * delays:
/// * 00h = No delay
/// * 01h = 15 - 50 ps phase difference
/// * 02h = 30 - 100 ps phase difference
/// * 03h = 45 - 150 ps phase difference
/// * ...
/// * 3Fh = 945 ps - 3150 ps phase difference.
/// * Note: Used in DSPLL application, do not use in regular PLL application.
/// ###
/// %unsigned 3 FD 0x4
/// ###
/// * Tune Frequency Detector Precision
/// * FD[0]: Reserved.
/// * FD[2:1] FD precision
/// * 00 +/- 0.1%
/// * 01 +/- 0.2%
/// * 10 +/- 0.4%
/// * 11 +/- 0.8%.
/// ###
/// %unsigned 4 INTPI 0x6
/// ###
/// * Phase Interpolator Bias Current Select.
/// * 1.2 ~ 1.5 GHz NOT SUPPORTED
/// * 0101: (VCO:1.5 ~ 2 GHz)
/// * 0110: (VCO:2 ~ 2.5 GHz)
/// * 1000: (VCO:2.5 ~ 3GHz).
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 3 INTPR 0x4
/// ###
/// * Phase Interpolator Resistor Select.
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %unsigned 1 PI_EN 0x0
/// ###
/// * Phase Interpolator Enable.
/// * 1: Enable phase interpolator
/// * 0: Disable phase interpolator.
/// ###
/// %unsigned 1 PI_LOOP_MODE 0x0
/// ###
/// * Phase Interpolator Loop Control.
/// * 1: PI is in the PLL loop.
/// * 0: PI is out of the PLL loop
/// ###
/// %unsigned 1 CLK_DET_EN 0x1
/// ###
/// * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
/// ###
/// %unsigned 1 RESET_PI 0x0
/// ###
/// * External Interpolator Reset.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 RESET_SSC 0x0
/// ###
/// * SSC reset
/// * 0 : No reset
/// * 1 : Reset
/// ###
/// %unsigned 1 FREQ_OFFSET_EN 0x0
/// ###
/// * Frequency Offset Enable.
/// * 0: Disable
/// * 1: Enable.
/// ###
/// %unsigned 17 FREQ_OFFSET 0x0
/// ###
/// * Frequency Offset Value
/// * Control.
/// * [16]: Sign-Bit.
/// * 0: Frequency down
/// * 1: Frequency up
/// * [15:0] : 1 LSB 1 ppm, upto 5%
/// * 1LSB=10e6/(4*128 *2048) ppm
/// * [16]=0--->Sign= 1
/// * [16]=1--->Sign= -1
/// * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
/// ###
/// %unsigned 1 FREQ_OFFSET_MODE_SELECTION 0x0
/// ###
/// * Frequency Offset Mode Select.
/// * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
/// * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
/// * (It has to be valid at the rising edge of CK_DIV64_OUT).
/// * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
/// ###
/// %unsigned 1 FREQ_OFFSET_VALID 0x0
/// ###
/// * Frequency Offset Value Valid.
/// * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
/// * Note:
/// * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
/// * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
/// ###
/// %unsigned 1 SSC_CLK_EN 0x0
/// ###
/// * SSC Clock Enable.
/// * This selection enables the PI output clock for SSC digital logic.
/// ###
/// %unsigned 1 SSC_MODE 0x1
/// ###
/// * SSC Mode Select.
/// * 0: center spread
/// * 1: down spread.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 16 SSC_FREQ_DIV 0x0
/// ###
/// * SSC Frequency Select.
/// ###
/// %unsigned 11 SSC_RNGE 0x0
/// ###
/// * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
/// * Rounding to integer required.
/// ###
/// %unsigned 4 TEST_ANA 0x0
/// ###
/// * Analog test point
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00010 ctrl4
/// %unsigned 8 RESERVE_IN 0x0
/// ###
/// * Reserved input pins
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00014 status (R-)
/// ###
/// * PLL status register
/// ###
/// %unsigned 1 PLL_LOCK
/// ###
/// * PLL Lock Detect.
/// * 1: PLL locked.
/// * 0: PLL not locked.
/// * Note:
/// * After PLL is powered up, wait for 50 us to check for the lock status.
/// * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
/// * This signal is for testing purpose only, do not use it for any functional use.
/// ###
/// %unsigned 1 CLK_CFMOD
/// ###
/// * Clock Mode Output.
/// * • For down spread and
/// * PI_LOOP_MODE = 0, output
/// * is 0.
/// * • For down spread and
/// * PI_LOOP_MODE = 1, output
/// * is 1.
/// * • For center spread, output a
/// * clock with SSC modulation
/// * frequency.
/// ###
/// %unsigned 1 CLK_FMOD
/// ###
/// * Clock Output And Modulation
/// * Frequency.
/// * For down spread, output a clock
/// * with SSC modulation frequency.
/// * For center spread, output a clock
/// * with double SSC modulation
/// * frequency.
/// ###
/// %unsigned 8 RESERVE_OUT
/// ###
/// * Reserve Output Register pins.
/// ###
/// %% 21 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 24B, bits: 141b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}
#define RA_pll_ctrl 0x0000
#define BA_pll_ctrl_PU 0x0000
#define B16pll_ctrl_PU 0x0000
#define LSb32pll_ctrl_PU 0
#define LSb16pll_ctrl_PU 0
#define bpll_ctrl_PU 1
#define MSK32pll_ctrl_PU 0x00000001
#define BA_pll_ctrl_RESET 0x0000
#define B16pll_ctrl_RESET 0x0000
#define LSb32pll_ctrl_RESET 1
#define LSb16pll_ctrl_RESET 1
#define bpll_ctrl_RESET 1
#define MSK32pll_ctrl_RESET 0x00000002
#define BA_pll_ctrl_AVDD1815_SEL 0x0000
#define B16pll_ctrl_AVDD1815_SEL 0x0000
#define LSb32pll_ctrl_AVDD1815_SEL 2
#define LSb16pll_ctrl_AVDD1815_SEL 2
#define bpll_ctrl_AVDD1815_SEL 1
#define MSK32pll_ctrl_AVDD1815_SEL 0x00000004
#define BA_pll_ctrl_REFDIV 0x0000
#define B16pll_ctrl_REFDIV 0x0000
#define LSb32pll_ctrl_REFDIV 3
#define LSb16pll_ctrl_REFDIV 3
#define bpll_ctrl_REFDIV 9
#define MSK32pll_ctrl_REFDIV 0x00000FF8
#define BA_pll_ctrl_FBDIV 0x0001
#define B16pll_ctrl_FBDIV 0x0000
#define LSb32pll_ctrl_FBDIV 12
#define LSb16pll_ctrl_FBDIV 12
#define bpll_ctrl_FBDIV 9
#define MSK32pll_ctrl_FBDIV 0x001FF000
#define BA_pll_ctrl_VDDM 0x0002
#define B16pll_ctrl_VDDM 0x0002
#define LSb32pll_ctrl_VDDM 21
#define LSb16pll_ctrl_VDDM 5
#define bpll_ctrl_VDDM 2
#define MSK32pll_ctrl_VDDM 0x00600000
#define BA_pll_ctrl_VDDL 0x0002
#define B16pll_ctrl_VDDL 0x0002
#define LSb32pll_ctrl_VDDL 23
#define LSb16pll_ctrl_VDDL 7
#define bpll_ctrl_VDDL 3
#define MSK32pll_ctrl_VDDL 0x03800000
#define BA_pll_ctrl_ICP 0x0003
#define B16pll_ctrl_ICP 0x0002
#define LSb32pll_ctrl_ICP 26
#define LSb16pll_ctrl_ICP 10
#define bpll_ctrl_ICP 4
#define MSK32pll_ctrl_ICP 0x3C000000
#define BA_pll_ctrl_PLL_BW_SEL 0x0003
#define B16pll_ctrl_PLL_BW_SEL 0x0002
#define LSb32pll_ctrl_PLL_BW_SEL 30
#define LSb16pll_ctrl_PLL_BW_SEL 14
#define bpll_ctrl_PLL_BW_SEL 1
#define MSK32pll_ctrl_PLL_BW_SEL 0x40000000
#define RA_pll_ctrl1 0x0004
#define BA_pll_ctrl_KVCO 0x0004
#define B16pll_ctrl_KVCO 0x0004
#define LSb32pll_ctrl_KVCO 0
#define LSb16pll_ctrl_KVCO 0
#define bpll_ctrl_KVCO 4
#define MSK32pll_ctrl_KVCO 0x0000000F
#define BA_pll_ctrl_CTUNE 0x0004
#define B16pll_ctrl_CTUNE 0x0004
#define LSb32pll_ctrl_CTUNE 4
#define LSb16pll_ctrl_CTUNE 4
#define bpll_ctrl_CTUNE 2
#define MSK32pll_ctrl_CTUNE 0x00000030
#define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x000001C0
#define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define bpll_ctrl_CLKOUT_SE_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00000E00
#define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 12
#define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 12
#define bpll_ctrl_CLKOUT_SOURCE_SEL 1
#define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x00001000
#define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0005
#define B16pll_ctrl_CLKOUT_DIFF_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_EN 13
#define LSb16pll_ctrl_CLKOUT_DIFF_EN 13
#define bpll_ctrl_CLKOUT_DIFF_EN 1
#define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x00002000
#define BA_pll_ctrl_BYPASS_EN 0x0005
#define B16pll_ctrl_BYPASS_EN 0x0004
#define LSb32pll_ctrl_BYPASS_EN 14
#define LSb16pll_ctrl_BYPASS_EN 14
#define bpll_ctrl_BYPASS_EN 1
#define MSK32pll_ctrl_BYPASS_EN 0x00004000
#define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0005
#define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 15
#define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 15
#define bpll_ctrl_CLKOUT_SE_GATING_EN 1
#define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x00008000
#define BA_pll_ctrl_FBCLK_EXT_SEL 0x0006
#define B16pll_ctrl_FBCLK_EXT_SEL 0x0006
#define LSb32pll_ctrl_FBCLK_EXT_SEL 16
#define LSb16pll_ctrl_FBCLK_EXT_SEL 0
#define bpll_ctrl_FBCLK_EXT_SEL 1
#define MSK32pll_ctrl_FBCLK_EXT_SEL 0x00010000
#define BA_pll_ctrl_FBCDLY 0x0006
#define B16pll_ctrl_FBCDLY 0x0006
#define LSb32pll_ctrl_FBCDLY 17
#define LSb16pll_ctrl_FBCDLY 1
#define bpll_ctrl_FBCDLY 6
#define MSK32pll_ctrl_FBCDLY 0x007E0000
#define BA_pll_ctrl_FD 0x0006
#define B16pll_ctrl_FD 0x0006
#define LSb32pll_ctrl_FD 23
#define LSb16pll_ctrl_FD 7
#define bpll_ctrl_FD 3
#define MSK32pll_ctrl_FD 0x03800000
#define BA_pll_ctrl_INTPI 0x0007
#define B16pll_ctrl_INTPI 0x0006
#define LSb32pll_ctrl_INTPI 26
#define LSb16pll_ctrl_INTPI 10
#define bpll_ctrl_INTPI 4
#define MSK32pll_ctrl_INTPI 0x3C000000
#define RA_pll_ctrl2 0x0008
#define BA_pll_ctrl_INTPR 0x0008
#define B16pll_ctrl_INTPR 0x0008
#define LSb32pll_ctrl_INTPR 0
#define LSb16pll_ctrl_INTPR 0
#define bpll_ctrl_INTPR 3
#define MSK32pll_ctrl_INTPR 0x00000007
#define BA_pll_ctrl_PI_EN 0x0008
#define B16pll_ctrl_PI_EN 0x0008
#define LSb32pll_ctrl_PI_EN 3
#define LSb16pll_ctrl_PI_EN 3
#define bpll_ctrl_PI_EN 1
#define MSK32pll_ctrl_PI_EN 0x00000008
#define BA_pll_ctrl_PI_LOOP_MODE 0x0008
#define B16pll_ctrl_PI_LOOP_MODE 0x0008
#define LSb32pll_ctrl_PI_LOOP_MODE 4
#define LSb16pll_ctrl_PI_LOOP_MODE 4
#define bpll_ctrl_PI_LOOP_MODE 1
#define MSK32pll_ctrl_PI_LOOP_MODE 0x00000010
#define BA_pll_ctrl_CLK_DET_EN 0x0008
#define B16pll_ctrl_CLK_DET_EN 0x0008
#define LSb32pll_ctrl_CLK_DET_EN 5
#define LSb16pll_ctrl_CLK_DET_EN 5
#define bpll_ctrl_CLK_DET_EN 1
#define MSK32pll_ctrl_CLK_DET_EN 0x00000020
#define BA_pll_ctrl_RESET_PI 0x0008
#define B16pll_ctrl_RESET_PI 0x0008
#define LSb32pll_ctrl_RESET_PI 6
#define LSb16pll_ctrl_RESET_PI 6
#define bpll_ctrl_RESET_PI 1
#define MSK32pll_ctrl_RESET_PI 0x00000040
#define BA_pll_ctrl_RESET_SSC 0x0008
#define B16pll_ctrl_RESET_SSC 0x0008
#define LSb32pll_ctrl_RESET_SSC 7
#define LSb16pll_ctrl_RESET_SSC 7
#define bpll_ctrl_RESET_SSC 1
#define MSK32pll_ctrl_RESET_SSC 0x00000080
#define BA_pll_ctrl_FREQ_OFFSET_EN 0x0009
#define B16pll_ctrl_FREQ_OFFSET_EN 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET_EN 8
#define LSb16pll_ctrl_FREQ_OFFSET_EN 8
#define bpll_ctrl_FREQ_OFFSET_EN 1
#define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00000100
#define BA_pll_ctrl_FREQ_OFFSET 0x0009
#define B16pll_ctrl_FREQ_OFFSET 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET 9
#define LSb16pll_ctrl_FREQ_OFFSET 9
#define bpll_ctrl_FREQ_OFFSET 17
#define MSK32pll_ctrl_FREQ_OFFSET 0x03FFFE00
#define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000B
#define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 26
#define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 10
#define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1
#define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x04000000
#define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000B
#define B16pll_ctrl_FREQ_OFFSET_VALID 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_VALID 27
#define LSb16pll_ctrl_FREQ_OFFSET_VALID 11
#define bpll_ctrl_FREQ_OFFSET_VALID 1
#define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x08000000
#define BA_pll_ctrl_SSC_CLK_EN 0x000B
#define B16pll_ctrl_SSC_CLK_EN 0x000A
#define LSb32pll_ctrl_SSC_CLK_EN 28
#define LSb16pll_ctrl_SSC_CLK_EN 12
#define bpll_ctrl_SSC_CLK_EN 1
#define MSK32pll_ctrl_SSC_CLK_EN 0x10000000
#define BA_pll_ctrl_SSC_MODE 0x000B
#define B16pll_ctrl_SSC_MODE 0x000A
#define LSb32pll_ctrl_SSC_MODE 29
#define LSb16pll_ctrl_SSC_MODE 13
#define bpll_ctrl_SSC_MODE 1
#define MSK32pll_ctrl_SSC_MODE 0x20000000
#define RA_pll_ctrl3 0x000C
#define BA_pll_ctrl_SSC_FREQ_DIV 0x000C
#define B16pll_ctrl_SSC_FREQ_DIV 0x000C
#define LSb32pll_ctrl_SSC_FREQ_DIV 0
#define LSb16pll_ctrl_SSC_FREQ_DIV 0
#define bpll_ctrl_SSC_FREQ_DIV 16
#define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF
#define BA_pll_ctrl_SSC_RNGE 0x000E
#define B16pll_ctrl_SSC_RNGE 0x000E
#define LSb32pll_ctrl_SSC_RNGE 16
#define LSb16pll_ctrl_SSC_RNGE 0
#define bpll_ctrl_SSC_RNGE 11
#define MSK32pll_ctrl_SSC_RNGE 0x07FF0000
#define BA_pll_ctrl_TEST_ANA 0x000F
#define B16pll_ctrl_TEST_ANA 0x000E
#define LSb32pll_ctrl_TEST_ANA 27
#define LSb16pll_ctrl_TEST_ANA 11
#define bpll_ctrl_TEST_ANA 4
#define MSK32pll_ctrl_TEST_ANA 0x78000000
#define RA_pll_ctrl4 0x0010
#define BA_pll_ctrl_RESERVE_IN 0x0010
#define B16pll_ctrl_RESERVE_IN 0x0010
#define LSb32pll_ctrl_RESERVE_IN 0
#define LSb16pll_ctrl_RESERVE_IN 0
#define bpll_ctrl_RESERVE_IN 8
#define MSK32pll_ctrl_RESERVE_IN 0x000000FF
///////////////////////////////////////////////////////////
#define RA_pll_status 0x0014
#define BA_pll_status_PLL_LOCK 0x0014
#define B16pll_status_PLL_LOCK 0x0014
#define LSb32pll_status_PLL_LOCK 0
#define LSb16pll_status_PLL_LOCK 0
#define bpll_status_PLL_LOCK 1
#define MSK32pll_status_PLL_LOCK 0x00000001
#define BA_pll_status_CLK_CFMOD 0x0014
#define B16pll_status_CLK_CFMOD 0x0014
#define LSb32pll_status_CLK_CFMOD 1
#define LSb16pll_status_CLK_CFMOD 1
#define bpll_status_CLK_CFMOD 1
#define MSK32pll_status_CLK_CFMOD 0x00000002
#define BA_pll_status_CLK_FMOD 0x0014
#define B16pll_status_CLK_FMOD 0x0014
#define LSb32pll_status_CLK_FMOD 2
#define LSb16pll_status_CLK_FMOD 2
#define bpll_status_CLK_FMOD 1
#define MSK32pll_status_CLK_FMOD 0x00000004
#define BA_pll_status_RESERVE_OUT 0x0014
#define B16pll_status_RESERVE_OUT 0x0014
#define LSb32pll_status_RESERVE_OUT 3
#define LSb16pll_status_RESERVE_OUT 3
#define bpll_status_RESERVE_OUT 8
#define MSK32pll_status_RESERVE_OUT 0x000007F8
///////////////////////////////////////////////////////////
typedef struct SIE_pll {
///////////////////////////////////////////////////////////
#define GET32pll_ctrl_PU(r32) _BFGET_(r32, 0, 0)
#define SET32pll_ctrl_PU(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_ctrl_PU(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_PU(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_RESET(r32) _BFGET_(r32, 1, 1)
#define SET32pll_ctrl_RESET(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_ctrl_RESET(r16) _BFGET_(r16, 1, 1)
#define SET16pll_ctrl_RESET(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_ctrl_AVDD1815_SEL(r32) _BFGET_(r32, 2, 2)
#define SET32pll_ctrl_AVDD1815_SEL(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_ctrl_AVDD1815_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16pll_ctrl_AVDD1815_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_ctrl_REFDIV(r32) _BFGET_(r32,11, 3)
#define SET32pll_ctrl_REFDIV(r32,v) _BFSET_(r32,11, 3,v)
#define GET16pll_ctrl_REFDIV(r16) _BFGET_(r16,11, 3)
#define SET16pll_ctrl_REFDIV(r16,v) _BFSET_(r16,11, 3,v)
#define GET32pll_ctrl_FBDIV(r32) _BFGET_(r32,20,12)
#define SET32pll_ctrl_FBDIV(r32,v) _BFSET_(r32,20,12,v)
#define GET32pll_ctrl_VDDM(r32) _BFGET_(r32,22,21)
#define SET32pll_ctrl_VDDM(r32,v) _BFSET_(r32,22,21,v)
#define GET16pll_ctrl_VDDM(r16) _BFGET_(r16, 6, 5)
#define SET16pll_ctrl_VDDM(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32pll_ctrl_VDDL(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_VDDL(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_VDDL(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_VDDL(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_ICP(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_ICP(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_ICP(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_ICP(r16,v) _BFSET_(r16,13,10,v)
#define GET32pll_ctrl_PLL_BW_SEL(r32) _BFGET_(r32,30,30)
#define SET32pll_ctrl_PLL_BW_SEL(r32,v) _BFSET_(r32,30,30,v)
#define GET16pll_ctrl_PLL_BW_SEL(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_PLL_BW_SEL(r16,v) _BFSET_(r16,14,14,v)
#define w32pll_ctrl {\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_AVDD1815_SEL : 1;\
UNSG32 uctrl_REFDIV : 9;\
UNSG32 uctrl_FBDIV : 9;\
UNSG32 uctrl_VDDM : 2;\
UNSG32 uctrl_VDDL : 3;\
UNSG32 uctrl_ICP : 4;\
UNSG32 uctrl_PLL_BW_SEL : 1;\
UNSG32 RSVDx0_b31 : 1;\
}
union { UNSG32 u32pll_ctrl;
struct w32pll_ctrl;
};
#define GET32pll_ctrl_KVCO(r32) _BFGET_(r32, 3, 0)
#define SET32pll_ctrl_KVCO(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16pll_ctrl_KVCO(r16) _BFGET_(r16, 3, 0)
#define SET16pll_ctrl_KVCO(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32pll_ctrl_CTUNE(r32) _BFGET_(r32, 5, 4)
#define SET32pll_ctrl_CTUNE(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16pll_ctrl_CTUNE(r16) _BFGET_(r16, 5, 4)
#define SET16pll_ctrl_CTUNE(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32) _BFGET_(r32, 8, 6)
#define SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16) _BFGET_(r16, 8, 6)
#define SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32) _BFGET_(r32,11, 9)
#define SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v) _BFSET_(r32,11, 9,v)
#define GET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16) _BFGET_(r16,11, 9)
#define SET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16,v) _BFSET_(r16,11, 9,v)
#define GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32) _BFGET_(r32,12,12)
#define SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v) _BFSET_(r32,12,12,v)
#define GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_CLKOUT_DIFF_EN(r32) _BFGET_(r32,13,13)
#define SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v) _BFSET_(r32,13,13,v)
#define GET16pll_ctrl_CLKOUT_DIFF_EN(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32pll_ctrl_BYPASS_EN(r32) _BFGET_(r32,14,14)
#define SET32pll_ctrl_BYPASS_EN(r32,v) _BFSET_(r32,14,14,v)
#define GET16pll_ctrl_BYPASS_EN(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_BYPASS_EN(r16,v) _BFSET_(r16,14,14,v)
#define GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32) _BFGET_(r32,15,15)
#define SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v) _BFSET_(r32,15,15,v)
#define GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16) _BFGET_(r16,15,15)
#define SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v) _BFSET_(r16,15,15,v)
#define GET32pll_ctrl_FBCLK_EXT_SEL(r32) _BFGET_(r32,16,16)
#define SET32pll_ctrl_FBCLK_EXT_SEL(r32,v) _BFSET_(r32,16,16,v)
#define GET16pll_ctrl_FBCLK_EXT_SEL(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_FBCLK_EXT_SEL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_FBCDLY(r32) _BFGET_(r32,22,17)
#define SET32pll_ctrl_FBCDLY(r32,v) _BFSET_(r32,22,17,v)
#define GET16pll_ctrl_FBCDLY(r16) _BFGET_(r16, 6, 1)
#define SET16pll_ctrl_FBCDLY(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32pll_ctrl_FD(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_FD(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_FD(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_FD(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_INTPI(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_INTPI(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_INTPI(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_INTPI(r16,v) _BFSET_(r16,13,10,v)
#define w32pll_ctrl1 {\
UNSG32 uctrl_KVCO : 4;\
UNSG32 uctrl_CTUNE : 2;\
UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SE_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SOURCE_SEL : 1;\
UNSG32 uctrl_CLKOUT_DIFF_EN : 1;\
UNSG32 uctrl_BYPASS_EN : 1;\
UNSG32 uctrl_CLKOUT_SE_GATING_EN : 1;\
UNSG32 uctrl_FBCLK_EXT_SEL : 1;\
UNSG32 uctrl_FBCDLY : 6;\
UNSG32 uctrl_FD : 3;\
UNSG32 uctrl_INTPI : 4;\
UNSG32 RSVDx4_b30 : 2;\
}
union { UNSG32 u32pll_ctrl1;
struct w32pll_ctrl1;
};
#define GET32pll_ctrl_INTPR(r32) _BFGET_(r32, 2, 0)
#define SET32pll_ctrl_INTPR(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16pll_ctrl_INTPR(r16) _BFGET_(r16, 2, 0)
#define SET16pll_ctrl_INTPR(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32pll_ctrl_PI_EN(r32) _BFGET_(r32, 3, 3)
#define SET32pll_ctrl_PI_EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pll_ctrl_PI_EN(r16) _BFGET_(r16, 3, 3)
#define SET16pll_ctrl_PI_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32pll_ctrl_PI_LOOP_MODE(r32) _BFGET_(r32, 4, 4)
#define SET32pll_ctrl_PI_LOOP_MODE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16pll_ctrl_PI_LOOP_MODE(r16) _BFGET_(r16, 4, 4)
#define SET16pll_ctrl_PI_LOOP_MODE(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32pll_ctrl_CLK_DET_EN(r32) _BFGET_(r32, 5, 5)
#define SET32pll_ctrl_CLK_DET_EN(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16pll_ctrl_CLK_DET_EN(r16) _BFGET_(r16, 5, 5)
#define SET16pll_ctrl_CLK_DET_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32pll_ctrl_RESET_PI(r32) _BFGET_(r32, 6, 6)
#define SET32pll_ctrl_RESET_PI(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16pll_ctrl_RESET_PI(r16) _BFGET_(r16, 6, 6)
#define SET16pll_ctrl_RESET_PI(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32pll_ctrl_RESET_SSC(r32) _BFGET_(r32, 7, 7)
#define SET32pll_ctrl_RESET_SSC(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16pll_ctrl_RESET_SSC(r16) _BFGET_(r16, 7, 7)
#define SET16pll_ctrl_RESET_SSC(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32pll_ctrl_FREQ_OFFSET_EN(r32) _BFGET_(r32, 8, 8)
#define SET32pll_ctrl_FREQ_OFFSET_EN(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16pll_ctrl_FREQ_OFFSET_EN(r16) _BFGET_(r16, 8, 8)
#define SET16pll_ctrl_FREQ_OFFSET_EN(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32pll_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,25, 9)
#define SET32pll_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,25, 9,v)
#define GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32) _BFGET_(r32,26,26)
#define SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v) _BFSET_(r32,26,26,v)
#define GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16) _BFGET_(r16,10,10)
#define SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v) _BFSET_(r16,10,10,v)
#define GET32pll_ctrl_FREQ_OFFSET_VALID(r32) _BFGET_(r32,27,27)
#define SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v) _BFSET_(r32,27,27,v)
#define GET16pll_ctrl_FREQ_OFFSET_VALID(r16) _BFGET_(r16,11,11)
#define SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v) _BFSET_(r16,11,11,v)
#define GET32pll_ctrl_SSC_CLK_EN(r32) _BFGET_(r32,28,28)
#define SET32pll_ctrl_SSC_CLK_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16pll_ctrl_SSC_CLK_EN(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_SSC_CLK_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_SSC_MODE(r32) _BFGET_(r32,29,29)
#define SET32pll_ctrl_SSC_MODE(r32,v) _BFSET_(r32,29,29,v)
#define GET16pll_ctrl_SSC_MODE(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_SSC_MODE(r16,v) _BFSET_(r16,13,13,v)
#define w32pll_ctrl2 {\
UNSG32 uctrl_INTPR : 3;\
UNSG32 uctrl_PI_EN : 1;\
UNSG32 uctrl_PI_LOOP_MODE : 1;\
UNSG32 uctrl_CLK_DET_EN : 1;\
UNSG32 uctrl_RESET_PI : 1;\
UNSG32 uctrl_RESET_SSC : 1;\
UNSG32 uctrl_FREQ_OFFSET_EN : 1;\
UNSG32 uctrl_FREQ_OFFSET : 17;\
UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION : 1;\
UNSG32 uctrl_FREQ_OFFSET_VALID : 1;\
UNSG32 uctrl_SSC_CLK_EN : 1;\
UNSG32 uctrl_SSC_MODE : 1;\
UNSG32 RSVDx8_b30 : 2;\
}
union { UNSG32 u32pll_ctrl2;
struct w32pll_ctrl2;
};
#define GET32pll_ctrl_SSC_FREQ_DIV(r32) _BFGET_(r32,15, 0)
#define SET32pll_ctrl_SSC_FREQ_DIV(r32,v) _BFSET_(r32,15, 0,v)
#define GET16pll_ctrl_SSC_FREQ_DIV(r16) _BFGET_(r16,15, 0)
#define SET16pll_ctrl_SSC_FREQ_DIV(r16,v) _BFSET_(r16,15, 0,v)
#define GET32pll_ctrl_SSC_RNGE(r32) _BFGET_(r32,26,16)
#define SET32pll_ctrl_SSC_RNGE(r32,v) _BFSET_(r32,26,16,v)
#define GET16pll_ctrl_SSC_RNGE(r16) _BFGET_(r16,10, 0)
#define SET16pll_ctrl_SSC_RNGE(r16,v) _BFSET_(r16,10, 0,v)
#define GET32pll_ctrl_TEST_ANA(r32) _BFGET_(r32,30,27)
#define SET32pll_ctrl_TEST_ANA(r32,v) _BFSET_(r32,30,27,v)
#define GET16pll_ctrl_TEST_ANA(r16) _BFGET_(r16,14,11)
#define SET16pll_ctrl_TEST_ANA(r16,v) _BFSET_(r16,14,11,v)
#define w32pll_ctrl3 {\
UNSG32 uctrl_SSC_FREQ_DIV : 16;\
UNSG32 uctrl_SSC_RNGE : 11;\
UNSG32 uctrl_TEST_ANA : 4;\
UNSG32 RSVDxC_b31 : 1;\
}
union { UNSG32 u32pll_ctrl3;
struct w32pll_ctrl3;
};
#define GET32pll_ctrl_RESERVE_IN(r32) _BFGET_(r32, 7, 0)
#define SET32pll_ctrl_RESERVE_IN(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16pll_ctrl_RESERVE_IN(r16) _BFGET_(r16, 7, 0)
#define SET16pll_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 7, 0,v)
#define w32pll_ctrl4 {\
UNSG32 uctrl_RESERVE_IN : 8;\
UNSG32 RSVDx10_b8 : 24;\
}
union { UNSG32 u32pll_ctrl4;
struct w32pll_ctrl4;
};
///////////////////////////////////////////////////////////
#define GET32pll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32pll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16pll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_status_CLK_CFMOD(r32) _BFGET_(r32, 1, 1)
#define SET32pll_status_CLK_CFMOD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_status_CLK_CFMOD(r16) _BFGET_(r16, 1, 1)
#define SET16pll_status_CLK_CFMOD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_status_CLK_FMOD(r32) _BFGET_(r32, 2, 2)
#define SET32pll_status_CLK_FMOD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_status_CLK_FMOD(r16) _BFGET_(r16, 2, 2)
#define SET16pll_status_CLK_FMOD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_status_RESERVE_OUT(r32) _BFGET_(r32,10, 3)
#define SET32pll_status_RESERVE_OUT(r32,v) _BFSET_(r32,10, 3,v)
#define GET16pll_status_RESERVE_OUT(r16) _BFGET_(r16,10, 3)
#define SET16pll_status_RESERVE_OUT(r16,v) _BFSET_(r16,10, 3,v)
#define w32pll_status {\
UNSG32 ustatus_PLL_LOCK : 1;\
UNSG32 ustatus_CLK_CFMOD : 1;\
UNSG32 ustatus_CLK_FMOD : 1;\
UNSG32 ustatus_RESERVE_OUT : 8;\
UNSG32 RSVDx14_b11 : 21;\
}
union { UNSG32 u32pll_status;
struct w32pll_status;
};
///////////////////////////////////////////////////////////
} SIE_pll;
typedef union T32pll_ctrl
{ UNSG32 u32;
struct w32pll_ctrl;
} T32pll_ctrl;
typedef union T32pll_ctrl1
{ UNSG32 u32;
struct w32pll_ctrl1;
} T32pll_ctrl1;
typedef union T32pll_ctrl2
{ UNSG32 u32;
struct w32pll_ctrl2;
} T32pll_ctrl2;
typedef union T32pll_ctrl3
{ UNSG32 u32;
struct w32pll_ctrl3;
} T32pll_ctrl3;
typedef union T32pll_ctrl4
{ UNSG32 u32;
struct w32pll_ctrl4;
} T32pll_ctrl4;
typedef union T32pll_status
{ UNSG32 u32;
struct w32pll_status;
} T32pll_status;
///////////////////////////////////////////////////////////
typedef union Tpll_ctrl
{ UNSG32 u32[5];
struct {
struct w32pll_ctrl;
struct w32pll_ctrl1;
struct w32pll_ctrl2;
struct w32pll_ctrl3;
struct w32pll_ctrl4;
};
} Tpll_ctrl;
typedef union Tpll_status
{ UNSG32 u32[1];
struct {
struct w32pll_status;
};
} Tpll_status;
///////////////////////////////////////////////////////////
SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pll_reset(SIE_pll *p);
SIGN32 pll_cmp (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pll_print(p, pfx,hLOG) pll_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE avpllCh biu (4,4)
/// ###
/// * AVPLL control signals for one channel
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 13 POSTDIV 0x0
/// %unsigned 1 POSTDIV_0P5 0x0
/// ###
/// * Audio clock divider program
/// * 1, When POSTDIV_CX[12:0]=
/// * 0 0000 0000 0000, then disable post divider
/// * 2, When POSTDIV_CX[12:0]>0:
/// * if POSTDIV_0P5_CX=0:
/// * Divider=POSTDIV_CX[12:0],
/// * if POSTDIV_0P5_CX=1:
/// * Divider=POSTDIV_CX[12:0]+0.5
/// * For C1-C7 only
/// ###
/// %unsigned 1 EN_DPLL 0x0
/// ###
/// * 0: disable channel CX's DPLL
/// * 1: enable channel CX's DPLL
/// ###
/// %unsigned 2 EN_LP 0x0
/// ###
/// * EN_LP_CX[1:0] FREQ_OFFSET CK_INTG
/// * 00 X CK_SSC
/// * 01 X*2 CK_SSC/2
/// * 10 X CK_SSC
/// * 11 X*4 CK_SSC/4
/// ###
/// %% 15 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 19 FREQ_OFFSET 0x0
/// ###
/// * [18] is sign bit
/// * 0: PI's Frequency down
/// * 1: PI's Frequency up
/// * [17:0]: 1 LSB -> 0.25ppm,
/// * up to 5%
/// ###
/// %unsigned 1 FREQ_OFFSET_READY 0x0
/// ###
/// * Frequency offset value readiness
/// * indicator for FREQ_OFFSET_CX [18:0],
/// * the pulse need to be longer
/// * than 320/Fvco. For Fvco=3GHz,
/// * the pulse with should > 172ns;
/// * For Fvco=1.5GHz, pulse width >344ns
/// ###
/// %unsigned 1 PU 0x0
/// ###
/// * 0: power down channel CX
/// * 1: power up channel CX
/// ###
/// %unsigned 1 PU_OFST_CTRL 0x1
/// ###
/// * 0: power down FREQ_OFFS
/// * 1: power up FREQ_OFFSET
/// ###
/// %% 10 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 20 P_SYNC1 0x10
/// ###
/// * Set DPLL's reference divider
/// * Divider= P_SYNC1_CX[19:0]
/// * It is forbidden when N<16
/// ###
/// %% 12 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 20 P_SYNC2 0x10
/// ###
/// * Set DPLL's feedback divider
/// * Divider= P_SYNC2_CX[19:0]
/// * It is forbidden when N<16
/// ###
/// %unsigned 1 RESET 0x1
/// ###
/// * Reset channel CX logic:
/// * 0: not reset
/// * 1: active reset
/// ###
/// %unsigned 2 RESERVE_IN 0x0
/// %% 9 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 82b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_avpllCh
#define h_avpllCh (){}
#define RA_avpllCh_ctrl 0x0000
#define BA_avpllCh_ctrl_POSTDIV 0x0000
#define B16avpllCh_ctrl_POSTDIV 0x0000
#define LSb32avpllCh_ctrl_POSTDIV 0
#define LSb16avpllCh_ctrl_POSTDIV 0
#define bavpllCh_ctrl_POSTDIV 13
#define MSK32avpllCh_ctrl_POSTDIV 0x00001FFF
#define BA_avpllCh_ctrl_POSTDIV_0P5 0x0001
#define B16avpllCh_ctrl_POSTDIV_0P5 0x0000
#define LSb32avpllCh_ctrl_POSTDIV_0P5 13
#define LSb16avpllCh_ctrl_POSTDIV_0P5 13
#define bavpllCh_ctrl_POSTDIV_0P5 1
#define MSK32avpllCh_ctrl_POSTDIV_0P5 0x00002000
#define BA_avpllCh_ctrl_EN_DPLL 0x0001
#define B16avpllCh_ctrl_EN_DPLL 0x0000
#define LSb32avpllCh_ctrl_EN_DPLL 14
#define LSb16avpllCh_ctrl_EN_DPLL 14
#define bavpllCh_ctrl_EN_DPLL 1
#define MSK32avpllCh_ctrl_EN_DPLL 0x00004000
#define BA_avpllCh_ctrl_EN_LP 0x0001
#define B16avpllCh_ctrl_EN_LP 0x0000
#define LSb32avpllCh_ctrl_EN_LP 15
#define LSb16avpllCh_ctrl_EN_LP 15
#define bavpllCh_ctrl_EN_LP 2
#define MSK32avpllCh_ctrl_EN_LP 0x00018000
#define RA_avpllCh_ctrl1 0x0004
#define BA_avpllCh_ctrl_FREQ_OFFSET 0x0004
#define B16avpllCh_ctrl_FREQ_OFFSET 0x0004
#define LSb32avpllCh_ctrl_FREQ_OFFSET 0
#define LSb16avpllCh_ctrl_FREQ_OFFSET 0
#define bavpllCh_ctrl_FREQ_OFFSET 19
#define MSK32avpllCh_ctrl_FREQ_OFFSET 0x0007FFFF
#define BA_avpllCh_ctrl_FREQ_OFFSET_READY 0x0006
#define B16avpllCh_ctrl_FREQ_OFFSET_READY 0x0006
#define LSb32avpllCh_ctrl_FREQ_OFFSET_READY 19
#define LSb16avpllCh_ctrl_FREQ_OFFSET_READY 3
#define bavpllCh_ctrl_FREQ_OFFSET_READY 1
#define MSK32avpllCh_ctrl_FREQ_OFFSET_READY 0x00080000
#define BA_avpllCh_ctrl_PU 0x0006
#define B16avpllCh_ctrl_PU 0x0006
#define LSb32avpllCh_ctrl_PU 20
#define LSb16avpllCh_ctrl_PU 4
#define bavpllCh_ctrl_PU 1
#define MSK32avpllCh_ctrl_PU 0x00100000
#define BA_avpllCh_ctrl_PU_OFST_CTRL 0x0006
#define B16avpllCh_ctrl_PU_OFST_CTRL 0x0006
#define LSb32avpllCh_ctrl_PU_OFST_CTRL 21
#define LSb16avpllCh_ctrl_PU_OFST_CTRL 5
#define bavpllCh_ctrl_PU_OFST_CTRL 1
#define MSK32avpllCh_ctrl_PU_OFST_CTRL 0x00200000
#define RA_avpllCh_ctrl2 0x0008
#define BA_avpllCh_ctrl_P_SYNC1 0x0008
#define B16avpllCh_ctrl_P_SYNC1 0x0008
#define LSb32avpllCh_ctrl_P_SYNC1 0
#define LSb16avpllCh_ctrl_P_SYNC1 0
#define bavpllCh_ctrl_P_SYNC1 20
#define MSK32avpllCh_ctrl_P_SYNC1 0x000FFFFF
#define RA_avpllCh_ctrl3 0x000C
#define BA_avpllCh_ctrl_P_SYNC2 0x000C
#define B16avpllCh_ctrl_P_SYNC2 0x000C
#define LSb32avpllCh_ctrl_P_SYNC2 0
#define LSb16avpllCh_ctrl_P_SYNC2 0
#define bavpllCh_ctrl_P_SYNC2 20
#define MSK32avpllCh_ctrl_P_SYNC2 0x000FFFFF
#define BA_avpllCh_ctrl_RESET 0x000E
#define B16avpllCh_ctrl_RESET 0x000E
#define LSb32avpllCh_ctrl_RESET 20
#define LSb16avpllCh_ctrl_RESET 4
#define bavpllCh_ctrl_RESET 1
#define MSK32avpllCh_ctrl_RESET 0x00100000
#define BA_avpllCh_ctrl_RESERVE_IN 0x000E
#define B16avpllCh_ctrl_RESERVE_IN 0x000E
#define LSb32avpllCh_ctrl_RESERVE_IN 21
#define LSb16avpllCh_ctrl_RESERVE_IN 5
#define bavpllCh_ctrl_RESERVE_IN 2
#define MSK32avpllCh_ctrl_RESERVE_IN 0x00600000
///////////////////////////////////////////////////////////
typedef struct SIE_avpllCh {
///////////////////////////////////////////////////////////
#define GET32avpllCh_ctrl_POSTDIV(r32) _BFGET_(r32,12, 0)
#define SET32avpllCh_ctrl_POSTDIV(r32,v) _BFSET_(r32,12, 0,v)
#define GET16avpllCh_ctrl_POSTDIV(r16) _BFGET_(r16,12, 0)
#define SET16avpllCh_ctrl_POSTDIV(r16,v) _BFSET_(r16,12, 0,v)
#define GET32avpllCh_ctrl_POSTDIV_0P5(r32) _BFGET_(r32,13,13)
#define SET32avpllCh_ctrl_POSTDIV_0P5(r32,v) _BFSET_(r32,13,13,v)
#define GET16avpllCh_ctrl_POSTDIV_0P5(r16) _BFGET_(r16,13,13)
#define SET16avpllCh_ctrl_POSTDIV_0P5(r16,v) _BFSET_(r16,13,13,v)
#define GET32avpllCh_ctrl_EN_DPLL(r32) _BFGET_(r32,14,14)
#define SET32avpllCh_ctrl_EN_DPLL(r32,v) _BFSET_(r32,14,14,v)
#define GET16avpllCh_ctrl_EN_DPLL(r16) _BFGET_(r16,14,14)
#define SET16avpllCh_ctrl_EN_DPLL(r16,v) _BFSET_(r16,14,14,v)
#define GET32avpllCh_ctrl_EN_LP(r32) _BFGET_(r32,16,15)
#define SET32avpllCh_ctrl_EN_LP(r32,v) _BFSET_(r32,16,15,v)
#define w32avpllCh_ctrl {\
UNSG32 uctrl_POSTDIV : 13;\
UNSG32 uctrl_POSTDIV_0P5 : 1;\
UNSG32 uctrl_EN_DPLL : 1;\
UNSG32 uctrl_EN_LP : 2;\
UNSG32 RSVDx0_b17 : 15;\
}
union { UNSG32 u32avpllCh_ctrl;
struct w32avpllCh_ctrl;
};
#define GET32avpllCh_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,18, 0)
#define SET32avpllCh_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,18, 0,v)
#define GET32avpllCh_ctrl_FREQ_OFFSET_READY(r32) _BFGET_(r32,19,19)
#define SET32avpllCh_ctrl_FREQ_OFFSET_READY(r32,v) _BFSET_(r32,19,19,v)
#define GET16avpllCh_ctrl_FREQ_OFFSET_READY(r16) _BFGET_(r16, 3, 3)
#define SET16avpllCh_ctrl_FREQ_OFFSET_READY(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32avpllCh_ctrl_PU(r32) _BFGET_(r32,20,20)
#define SET32avpllCh_ctrl_PU(r32,v) _BFSET_(r32,20,20,v)
#define GET16avpllCh_ctrl_PU(r16) _BFGET_(r16, 4, 4)
#define SET16avpllCh_ctrl_PU(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32avpllCh_ctrl_PU_OFST_CTRL(r32) _BFGET_(r32,21,21)
#define SET32avpllCh_ctrl_PU_OFST_CTRL(r32,v) _BFSET_(r32,21,21,v)
#define GET16avpllCh_ctrl_PU_OFST_CTRL(r16) _BFGET_(r16, 5, 5)
#define SET16avpllCh_ctrl_PU_OFST_CTRL(r16,v) _BFSET_(r16, 5, 5,v)
#define w32avpllCh_ctrl1 {\
UNSG32 uctrl_FREQ_OFFSET : 19;\
UNSG32 uctrl_FREQ_OFFSET_READY : 1;\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_PU_OFST_CTRL : 1;\
UNSG32 RSVDx4_b22 : 10;\
}
union { UNSG32 u32avpllCh_ctrl1;
struct w32avpllCh_ctrl1;
};
#define GET32avpllCh_ctrl_P_SYNC1(r32) _BFGET_(r32,19, 0)
#define SET32avpllCh_ctrl_P_SYNC1(r32,v) _BFSET_(r32,19, 0,v)
#define w32avpllCh_ctrl2 {\
UNSG32 uctrl_P_SYNC1 : 20;\
UNSG32 RSVDx8_b20 : 12;\
}
union { UNSG32 u32avpllCh_ctrl2;
struct w32avpllCh_ctrl2;
};
#define GET32avpllCh_ctrl_P_SYNC2(r32) _BFGET_(r32,19, 0)
#define SET32avpllCh_ctrl_P_SYNC2(r32,v) _BFSET_(r32,19, 0,v)
#define GET32avpllCh_ctrl_RESET(r32) _BFGET_(r32,20,20)
#define SET32avpllCh_ctrl_RESET(r32,v) _BFSET_(r32,20,20,v)
#define GET16avpllCh_ctrl_RESET(r16) _BFGET_(r16, 4, 4)
#define SET16avpllCh_ctrl_RESET(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32avpllCh_ctrl_RESERVE_IN(r32) _BFGET_(r32,22,21)
#define SET32avpllCh_ctrl_RESERVE_IN(r32,v) _BFSET_(r32,22,21,v)
#define GET16avpllCh_ctrl_RESERVE_IN(r16) _BFGET_(r16, 6, 5)
#define SET16avpllCh_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 6, 5,v)
#define w32avpllCh_ctrl3 {\
UNSG32 uctrl_P_SYNC2 : 20;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_RESERVE_IN : 2;\
UNSG32 RSVDxC_b23 : 9;\
}
union { UNSG32 u32avpllCh_ctrl3;
struct w32avpllCh_ctrl3;
};
///////////////////////////////////////////////////////////
} SIE_avpllCh;
typedef union T32avpllCh_ctrl
{ UNSG32 u32;
struct w32avpllCh_ctrl;
} T32avpllCh_ctrl;
typedef union T32avpllCh_ctrl1
{ UNSG32 u32;
struct w32avpllCh_ctrl1;
} T32avpllCh_ctrl1;
typedef union T32avpllCh_ctrl2
{ UNSG32 u32;
struct w32avpllCh_ctrl2;
} T32avpllCh_ctrl2;
typedef union T32avpllCh_ctrl3
{ UNSG32 u32;
struct w32avpllCh_ctrl3;
} T32avpllCh_ctrl3;
///////////////////////////////////////////////////////////
typedef union TavpllCh_ctrl
{ UNSG32 u32[4];
struct {
struct w32avpllCh_ctrl;
struct w32avpllCh_ctrl1;
struct w32avpllCh_ctrl2;
struct w32avpllCh_ctrl3;
};
} TavpllCh_ctrl;
///////////////////////////////////////////////////////////
SIGN32 avpllCh_drvrd(SIE_avpllCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 avpllCh_drvwr(SIE_avpllCh *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void avpllCh_reset(SIE_avpllCh *p);
SIGN32 avpllCh_cmp (SIE_avpllCh *p, SIE_avpllCh *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define avpllCh_check(p,pie,pfx,hLOG) avpllCh_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define avpllCh_print(p, pfx,hLOG) avpllCh_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: avpllCh
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE avpllCh8 biu (4,4)
/// ###
/// * AVPLL control signals for channel 8 (Channel inside PLL)
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 13 POSTDIV 0x0
/// %unsigned 1 POSTDIV_0P5 0x0
/// ###
/// * Audio clock divider program
/// * 1, When POSTDIV_CX[12:0]=
/// * 0 0000 0000 0000, then disable post divider
/// * 2, When POSTDIV_CX[12:0]>0:
/// * if POSTDIV_0P5_CX=0:
/// * Divider=POSTDIV_CX[12:0],
/// * if POSTDIV_0P5_CX=1:
/// * Divider=POSTDIV_CX[12:0]+0.5
/// * For C1-C7 only
/// ###
/// %unsigned 1 EN_DPLL 0x0
/// ###
/// * 0: disable channel CX's DPLL
/// * 1: enable channel CX's DPLL
/// ###
/// %unsigned 2 EN_LP 0x0
/// ###
/// * EN_LP_CX[1:0] FREQ_OFFSET CK_INTG
/// * 00 X CK_SSC
/// * 01 X*2 CK_SSC/2
/// * 10 X CK_SSC
/// * 11 X*4 CK_SSC/4
/// ###
/// %% 15 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 19 FREQ_OFFSET 0x0
/// ###
/// * [18] is sign bit
/// * 0: PI's Frequency down
/// * 1: PI's Frequency up
/// * [17:0]: 1 LSB -> 0.25ppm,
/// * up to 5%
/// ###
/// %unsigned 1 FREQ_OFFSET_READY 0x0
/// ###
/// * Frequency offset value readiness
/// * indicator for FREQ_OFFSET_CX [18:0],
/// * the pulse need to be longer
/// * than 320/Fvco. For Fvco=3GHz,
/// * the pulse with should > 172ns;
/// * For Fvco=1.5GHz, pulse width >344ns
/// ###
/// %unsigned 1 PU 0x0
/// ###
/// * 0: power down channel CX
/// * 1: power up channel CX
/// ###
/// %unsigned 1 PU_OFST_CTRL 0x1
/// ###
/// * 0: power down FREQ_OFFS
/// * 1: power up FREQ_OFFSET
/// ###
/// %% 10 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 20 P_SYNC1 0x10
/// ###
/// * Set DPLL's reference divider
/// * Divider= P_SYNC1_CX[19:0]
/// * It is forbidden when N<16
/// ###
/// %% 12 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 20 P_SYNC2 0x10
/// ###
/// * Set DPLL's feedback divider
/// * Divider= P_SYNC2_CX[19:0]
/// * It is forbidden when N<16
/// ###
/// %unsigned 1 RESET 0x0
/// ###
/// * Reset channel CX logic:
/// * 0: not reset
/// * 1: active reset
/// ###
/// %unsigned 2 RESERVE_IN 0x1
/// %% 9 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 82b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_avpllCh8
#define h_avpllCh8 (){}
#define RA_avpllCh8_ctrl 0x0000
#define BA_avpllCh8_ctrl_POSTDIV 0x0000
#define B16avpllCh8_ctrl_POSTDIV 0x0000
#define LSb32avpllCh8_ctrl_POSTDIV 0
#define LSb16avpllCh8_ctrl_POSTDIV 0
#define bavpllCh8_ctrl_POSTDIV 13
#define MSK32avpllCh8_ctrl_POSTDIV 0x00001FFF
#define BA_avpllCh8_ctrl_POSTDIV_0P5 0x0001
#define B16avpllCh8_ctrl_POSTDIV_0P5 0x0000
#define LSb32avpllCh8_ctrl_POSTDIV_0P5 13
#define LSb16avpllCh8_ctrl_POSTDIV_0P5 13
#define bavpllCh8_ctrl_POSTDIV_0P5 1
#define MSK32avpllCh8_ctrl_POSTDIV_0P5 0x00002000
#define BA_avpllCh8_ctrl_EN_DPLL 0x0001
#define B16avpllCh8_ctrl_EN_DPLL 0x0000
#define LSb32avpllCh8_ctrl_EN_DPLL 14
#define LSb16avpllCh8_ctrl_EN_DPLL 14
#define bavpllCh8_ctrl_EN_DPLL 1
#define MSK32avpllCh8_ctrl_EN_DPLL 0x00004000
#define BA_avpllCh8_ctrl_EN_LP 0x0001
#define B16avpllCh8_ctrl_EN_LP 0x0000
#define LSb32avpllCh8_ctrl_EN_LP 15
#define LSb16avpllCh8_ctrl_EN_LP 15
#define bavpllCh8_ctrl_EN_LP 2
#define MSK32avpllCh8_ctrl_EN_LP 0x00018000
#define RA_avpllCh8_ctrl1 0x0004
#define BA_avpllCh8_ctrl_FREQ_OFFSET 0x0004
#define B16avpllCh8_ctrl_FREQ_OFFSET 0x0004
#define LSb32avpllCh8_ctrl_FREQ_OFFSET 0
#define LSb16avpllCh8_ctrl_FREQ_OFFSET 0
#define bavpllCh8_ctrl_FREQ_OFFSET 19
#define MSK32avpllCh8_ctrl_FREQ_OFFSET 0x0007FFFF
#define BA_avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006
#define B16avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006
#define LSb32avpllCh8_ctrl_FREQ_OFFSET_READY 19
#define LSb16avpllCh8_ctrl_FREQ_OFFSET_READY 3
#define bavpllCh8_ctrl_FREQ_OFFSET_READY 1
#define MSK32avpllCh8_ctrl_FREQ_OFFSET_READY 0x00080000
#define BA_avpllCh8_ctrl_PU 0x0006
#define B16avpllCh8_ctrl_PU 0x0006
#define LSb32avpllCh8_ctrl_PU 20
#define LSb16avpllCh8_ctrl_PU 4
#define bavpllCh8_ctrl_PU 1
#define MSK32avpllCh8_ctrl_PU 0x00100000
#define BA_avpllCh8_ctrl_PU_OFST_CTRL 0x0006
#define B16avpllCh8_ctrl_PU_OFST_CTRL 0x0006
#define LSb32avpllCh8_ctrl_PU_OFST_CTRL 21
#define LSb16avpllCh8_ctrl_PU_OFST_CTRL 5
#define bavpllCh8_ctrl_PU_OFST_CTRL 1
#define MSK32avpllCh8_ctrl_PU_OFST_CTRL 0x00200000
#define RA_avpllCh8_ctrl2 0x0008
#define BA_avpllCh8_ctrl_P_SYNC1 0x0008
#define B16avpllCh8_ctrl_P_SYNC1 0x0008
#define LSb32avpllCh8_ctrl_P_SYNC1 0
#define LSb16avpllCh8_ctrl_P_SYNC1 0
#define bavpllCh8_ctrl_P_SYNC1 20
#define MSK32avpllCh8_ctrl_P_SYNC1 0x000FFFFF
#define RA_avpllCh8_ctrl3 0x000C
#define BA_avpllCh8_ctrl_P_SYNC2 0x000C
#define B16avpllCh8_ctrl_P_SYNC2 0x000C
#define LSb32avpllCh8_ctrl_P_SYNC2 0
#define LSb16avpllCh8_ctrl_P_SYNC2 0
#define bavpllCh8_ctrl_P_SYNC2 20
#define MSK32avpllCh8_ctrl_P_SYNC2 0x000FFFFF
#define BA_avpllCh8_ctrl_RESET 0x000E
#define B16avpllCh8_ctrl_RESET 0x000E
#define LSb32avpllCh8_ctrl_RESET 20
#define LSb16avpllCh8_ctrl_RESET 4
#define bavpllCh8_ctrl_RESET 1
#define MSK32avpllCh8_ctrl_RESET 0x00100000
#define BA_avpllCh8_ctrl_RESERVE_IN 0x000E
#define B16avpllCh8_ctrl_RESERVE_IN 0x000E
#define LSb32avpllCh8_ctrl_RESERVE_IN 21
#define LSb16avpllCh8_ctrl_RESERVE_IN 5
#define bavpllCh8_ctrl_RESERVE_IN 2
#define MSK32avpllCh8_ctrl_RESERVE_IN 0x00600000
///////////////////////////////////////////////////////////
typedef struct SIE_avpllCh8 {
///////////////////////////////////////////////////////////
#define GET32avpllCh8_ctrl_POSTDIV(r32) _BFGET_(r32,12, 0)
#define SET32avpllCh8_ctrl_POSTDIV(r32,v) _BFSET_(r32,12, 0,v)
#define GET16avpllCh8_ctrl_POSTDIV(r16) _BFGET_(r16,12, 0)
#define SET16avpllCh8_ctrl_POSTDIV(r16,v) _BFSET_(r16,12, 0,v)
#define GET32avpllCh8_ctrl_POSTDIV_0P5(r32) _BFGET_(r32,13,13)
#define SET32avpllCh8_ctrl_POSTDIV_0P5(r32,v) _BFSET_(r32,13,13,v)
#define GET16avpllCh8_ctrl_POSTDIV_0P5(r16) _BFGET_(r16,13,13)
#define SET16avpllCh8_ctrl_POSTDIV_0P5(r16,v) _BFSET_(r16,13,13,v)
#define GET32avpllCh8_ctrl_EN_DPLL(r32) _BFGET_(r32,14,14)
#define SET32avpllCh8_ctrl_EN_DPLL(r32,v) _BFSET_(r32,14,14,v)
#define GET16avpllCh8_ctrl_EN_DPLL(r16) _BFGET_(r16,14,14)
#define SET16avpllCh8_ctrl_EN_DPLL(r16,v) _BFSET_(r16,14,14,v)
#define GET32avpllCh8_ctrl_EN_LP(r32) _BFGET_(r32,16,15)
#define SET32avpllCh8_ctrl_EN_LP(r32,v) _BFSET_(r32,16,15,v)
#define w32avpllCh8_ctrl {\
UNSG32 uctrl_POSTDIV : 13;\
UNSG32 uctrl_POSTDIV_0P5 : 1;\
UNSG32 uctrl_EN_DPLL : 1;\
UNSG32 uctrl_EN_LP : 2;\
UNSG32 RSVDx0_b17 : 15;\
}
union { UNSG32 u32avpllCh8_ctrl;
struct w32avpllCh8_ctrl;
};
#define GET32avpllCh8_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,18, 0)
#define SET32avpllCh8_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,18, 0,v)
#define GET32avpllCh8_ctrl_FREQ_OFFSET_READY(r32) _BFGET_(r32,19,19)
#define SET32avpllCh8_ctrl_FREQ_OFFSET_READY(r32,v) _BFSET_(r32,19,19,v)
#define GET16avpllCh8_ctrl_FREQ_OFFSET_READY(r16) _BFGET_(r16, 3, 3)
#define SET16avpllCh8_ctrl_FREQ_OFFSET_READY(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32avpllCh8_ctrl_PU(r32) _BFGET_(r32,20,20)
#define SET32avpllCh8_ctrl_PU(r32,v) _BFSET_(r32,20,20,v)
#define GET16avpllCh8_ctrl_PU(r16) _BFGET_(r16, 4, 4)
#define SET16avpllCh8_ctrl_PU(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32avpllCh8_ctrl_PU_OFST_CTRL(r32) _BFGET_(r32,21,21)
#define SET32avpllCh8_ctrl_PU_OFST_CTRL(r32,v) _BFSET_(r32,21,21,v)
#define GET16avpllCh8_ctrl_PU_OFST_CTRL(r16) _BFGET_(r16, 5, 5)
#define SET16avpllCh8_ctrl_PU_OFST_CTRL(r16,v) _BFSET_(r16, 5, 5,v)
#define w32avpllCh8_ctrl1 {\
UNSG32 uctrl_FREQ_OFFSET : 19;\
UNSG32 uctrl_FREQ_OFFSET_READY : 1;\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_PU_OFST_CTRL : 1;\
UNSG32 RSVDx4_b22 : 10;\
}
union { UNSG32 u32avpllCh8_ctrl1;
struct w32avpllCh8_ctrl1;
};
#define GET32avpllCh8_ctrl_P_SYNC1(r32) _BFGET_(r32,19, 0)
#define SET32avpllCh8_ctrl_P_SYNC1(r32,v) _BFSET_(r32,19, 0,v)
#define w32avpllCh8_ctrl2 {\
UNSG32 uctrl_P_SYNC1 : 20;\
UNSG32 RSVDx8_b20 : 12;\
}
union { UNSG32 u32avpllCh8_ctrl2;
struct w32avpllCh8_ctrl2;
};
#define GET32avpllCh8_ctrl_P_SYNC2(r32) _BFGET_(r32,19, 0)
#define SET32avpllCh8_ctrl_P_SYNC2(r32,v) _BFSET_(r32,19, 0,v)
#define GET32avpllCh8_ctrl_RESET(r32) _BFGET_(r32,20,20)
#define SET32avpllCh8_ctrl_RESET(r32,v) _BFSET_(r32,20,20,v)
#define GET16avpllCh8_ctrl_RESET(r16) _BFGET_(r16, 4, 4)
#define SET16avpllCh8_ctrl_RESET(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32avpllCh8_ctrl_RESERVE_IN(r32) _BFGET_(r32,22,21)
#define SET32avpllCh8_ctrl_RESERVE_IN(r32,v) _BFSET_(r32,22,21,v)
#define GET16avpllCh8_ctrl_RESERVE_IN(r16) _BFGET_(r16, 6, 5)
#define SET16avpllCh8_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 6, 5,v)
#define w32avpllCh8_ctrl3 {\
UNSG32 uctrl_P_SYNC2 : 20;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_RESERVE_IN : 2;\
UNSG32 RSVDxC_b23 : 9;\
}
union { UNSG32 u32avpllCh8_ctrl3;
struct w32avpllCh8_ctrl3;
};
///////////////////////////////////////////////////////////
} SIE_avpllCh8;
typedef union T32avpllCh8_ctrl
{ UNSG32 u32;
struct w32avpllCh8_ctrl;
} T32avpllCh8_ctrl;
typedef union T32avpllCh8_ctrl1
{ UNSG32 u32;
struct w32avpllCh8_ctrl1;
} T32avpllCh8_ctrl1;
typedef union T32avpllCh8_ctrl2
{ UNSG32 u32;
struct w32avpllCh8_ctrl2;
} T32avpllCh8_ctrl2;
typedef union T32avpllCh8_ctrl3
{ UNSG32 u32;
struct w32avpllCh8_ctrl3;
} T32avpllCh8_ctrl3;
///////////////////////////////////////////////////////////
typedef union TavpllCh8_ctrl
{ UNSG32 u32[4];
struct {
struct w32avpllCh8_ctrl;
struct w32avpllCh8_ctrl1;
struct w32avpllCh8_ctrl2;
struct w32avpllCh8_ctrl3;
};
} TavpllCh8_ctrl;
///////////////////////////////////////////////////////////
SIGN32 avpllCh8_drvrd(SIE_avpllCh8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 avpllCh8_drvwr(SIE_avpllCh8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void avpllCh8_reset(SIE_avpllCh8 *p);
SIGN32 avpllCh8_cmp (SIE_avpllCh8 *p, SIE_avpllCh8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define avpllCh8_check(p,pie,pfx,hLOG) avpllCh8_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define avpllCh8_print(p, pfx,hLOG) avpllCh8_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: avpllCh8
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE avPll biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrlPLL (P-)
/// ###
/// * AVPLL Control Registers
/// * The AVPLL is designed to generate clocks for digital Audio and Video applications. It consists of only one core PLL which generates clock outputs covering the frequency range from 1.5GHz to 2.97GHz. There are totally 8 PIs, with 1 PI used inside PLL, 7 PIs used in output clock channels. The PI used inside PLL is referred to C8.
/// * Other PIs in each channel provides 7 channels output clock signal:
/// * a), The other five channels (C1..C5) can be programmed as audio/video clock. They are single end output clock.
/// * b), In contrast with C1..C5, CHANNEL6 provide clock of lower jitter. They are proposed to be programmed as video DAC or other higher performance clock (Of course, they also can be programmed as audio clock). C6 are differential output clock.
/// * c), CHANNEL7 (C7) is dedicated HDMI clock. C7 is differential output clock.
/// ###
/// %unsigned 1 RESET 0x1
/// ###
/// * 0
/// * De-asserted
/// * 1
/// * Asserted
/// * Reset PLL
/// * Must be de-asserted after 10us from the time when PU is set to 1.
/// * Note: Firmware should first set PU then de-assert PLL reset after 10us and then enable the video and audio clocks using the clk enable register.
/// ###
/// %unsigned 1 PU 0x0
/// ###
/// * Power up signal for AVPLL
/// * 0=power down
/// * 1=active
/// * When PU=0, all circuits including IVREF, INTP, REGULATOR and PLL are POWERED OFF
/// ###
/// %unsigned 3 PLL_VDDRA_SEL 0x3
/// ###
/// * Select gate voltage for
/// * VDDBUF
/// * 000 1,16v
/// * 001 1.18v
/// * 010 1.20v
/// * 011 1.22v
/// * 100 1.24v
/// * 101 1.26v
/// * 110 1.28v
/// * 111 1.30v
/// * VGATE=1.22V,
/// * range from 1.16-1.3,
/// * 20mv/step
/// ###
/// %unsigned 1 REG_RING_EXTRA_I_EN 0x0
/// ###
/// * "1" : turn on extra current for
/// * the oscillator of vdda23 charge pump
/// ###
/// %unsigned 2 VCO_REF1P45_SEL 0x1
/// ###
/// * Select VREF1P0V_VCO1P45
/// * 00 0.975v
/// * 01 1.0v
/// * 10 1.025v
/// * 11 1.05v
/// ###
/// %unsigned 2 VDDA23_PUMP_SEL 0x1
/// ###
/// * Select VREF0P96_VDDA23PUMP
/// * 00 0.925v
/// * 01 0.95v
/// * 10 1.0v
/// * 11 1.05v
/// ###
/// %unsigned 3 VDDBUF_ADJ 0x0
/// ###
/// * Adjust for VDDVDOFBUF
/// * VDDBUF_ADJ[2:1] are reserved
/// * VDDBUF[0]:
/// * 0: vddvcofbuf=vddvco
/// * 1: vddvcofbuf=1.08*vddvco
/// ###
/// %unsigned 4 VDDL 0xC
/// ###
/// * Internal regulated VDD supply
/// * 0001: 0.88v
/// * 0010: 0.90v
/// * 0011: 0.92v
/// * 0100: 0.94 v
/// * 0101: 0.96 v
/// * 0110: 0.98 v
/// * 0111: 1.00 v
/// * 1000: 1.02 v
/// * 1001: 1.04 v
/// * 1010: 1.06 v
/// * 1011: 1.08 v
/// * 1100: 1.10v
/// * 1101: 1.12v
/// * 1110: 1.14v
/// * 1111: 1.16v
/// ###
/// %unsigned 9 FBDIV 0x10
/// ###
/// * Feedback clock divider select
/// * Divider= FBDIV [8:0], start from 16.
/// ###
/// %unsigned 4 ICP 0x5
/// ###
/// * Charge-pump current con
/// * 0000 30uA
/// * 0001 37.5uA
/// * 0010 45uA
/// * 0011 52.5uA
/// * 0100 60uA
/// * 0101 75uA
/// * 0110 90uA
/// * 0111 105uA
/// * 1000 120uA
/// * 1001 150uA
/// * 1010 180uA
/// * 1011 210uA
/// * 1100 240uA
/// * 1101 300uA
/// * 1110 360uA
/// * 1111 420uA
/// ###
/// %unsigned 1 PLL_LPFC2_LESS 0x0
/// ###
/// * PLL_LPFC1=1, C2=1.2pf
/// * PLL_LPFC1=0, C2=1.4pf
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00004 ctrlPLL1
/// %unsigned 7 REFDIV 0x1
/// ###
/// * Reference clock divider select
/// * [5:0]
/// * 0000000: not used.
/// * 0000001: div1.
/// * 0000010: div2
/// * 0000011: div3
/// * 0000100: div4
/// * .
/// * .
/// * Divider=REFDIV[5:0], for N>=2
/// ###
/// %unsigned 6 RESERVE_PLL_IN 0x0
/// %unsigned 4 EXT_SPEED 0x0
/// ###
/// * External VCO speed control for
/// * different VCO frequencies. The following table is for simulation purpose, it matches the verilog model. The actual VCO speed setting is coming from the calibration result.
/// * SPEED[3:0]: typical freq range
/// * 0000 reserved
/// * 0001 reserved
/// * 0010 1.5G~1.7GHz
/// * 0011 1.7G~1.9GHz
/// * 0100 1.9G~2.1GHz
/// * 0101 2.1G~2.3GHz
/// * 0110 2.3G~2.45GHz
/// * 0111 2.45G~2.6GHz
/// * 1000 2.6G~2.75GHz
/// * 1001 2.75G~2.9GHz
/// * 1010 2.9G~3.0GHz
/// * 1011 reserved
/// * 1100 reserved
/// * 1101 reserved
/// * 1110 reserved
/// ###
/// %unsigned 4 SPEED_FBRES 0x0
/// ###
/// * External feedback resistor (VCO ring) set up bits
/// ###
/// %unsigned 1 UPDATE_SEL 0x0
/// ###
/// * Select the PLL update_rate:
/// * 0: 19M~26MHz
/// * for refclk 19.2M, 38.4M 2
/// * 1: 13MHz for refclk 13MHz
/// ###
/// %% 10 # Stuffing bits...
/// @ 0x00008 ctrlCAL (P-)
/// %unsigned 9 CAL_FBDIV 0x64
/// ###
/// * During calibration, count Fvco/CAL_FBDIV cycles in 1us, and compare it with SPEED_THRESH[5:0] to decide fvco is higher or lower than the expected frequency, set to dec100.
/// ###
/// %unsigned 1 EXT_SLLP_DAC_EN 0x0
/// ###
/// * 0: use the calibrated code SLLP_DAC_RD[6:0]
/// * 1: use the external input EXT_SLLP_DAC[6:0]
/// ###
/// %unsigned 1 EXT_SPEED_EN 0x0
/// ###
/// * 0: use the calibrated code SPEED_RD[3:0]
/// * 1: use the external input SPEED[3:0]
/// ###
/// %unsigned 1 EXT_SP_FBRES_EN 0x0
/// ###
/// * External speed enable pin
/// * 0: take SPEED_RD[3:0] for feedback resistor
/// * 1: take SPEED_FBRES[3:0]
/// ###
/// %unsigned 5 PLL_CALCLK_DIV 0x19
/// ###
/// * Divider to generate around 1MHz calibration clock from the internal update clock:
/// * 00000: not used.
/// * 00001: div1.
/// * 00010: div2
/// * 00011: div3
/// * 00100: div4
/// * .. .
/// * Divider=PLL_CALCLK_DIV[4:0], for N>=2
/// * D13 for refclk 13MHz
/// * D19 for refclk 19.2MHz/38.4MHz
/// * D25 for refclk 25MHz
/// * D26 for refclk 26MHz
/// ###
/// %unsigned 1 PLL_CAL_START 0x0
/// ###
/// * Rising edge to start PLL calibration
/// ###
/// %unsigned 4 REG_SETTLE_LIMIT 0x8
/// ###
/// * Select waiting time before calibration logic start to take action after PLL_CAL_START is issued, default is 8us
/// ###
/// %unsigned 1 SEL_VTHVCOCONT 0x1
/// ###
/// * Select the source of threshold
/// * 0: select IPP+IPTAT generated threshold voltage
/// * 1: select IPP generated threshold voltage
/// ###
/// %unsigned 6 SPEED_THRESH 0x1E
/// ###
/// * Digital counter threshold for VCO speed setting calibration loop, threshold value varies with the target VCO frequency.
/// * if CAL_FBDIV=dec100,
/// * speed_thresh[5:0] VCO_frequency
/// * dec15 1.5GHz
/// * dec20 2.0GHz
/// * dec30 3.0GHz
/// ###
/// %unsigned 2 VCON_SEL 0x2
/// ###
/// * Used to set VCON value during PLL Open loop calibration
/// * 00: 0.6
/// * 01: 0.65
/// * 10: 0.7
/// * 11: 0.75
/// ###
/// %% 1 # Stuffing bits...
/// # 0x0000C ctrlCAL1
/// %unsigned 7 EXT_SLLP_DAC 0x32
/// ###
/// * External input used to set VDDVCO value. Used to set Vcon reference value during PLL normal calibration.
/// * Vcon: 0.35 + 0.01125*VSET_SLLP_DAC[6:0] default: 01,1011 -------- Vcon=0.697V
/// ###
/// %unsigned 2 VTH_VCO_CAL 0x2
/// ###
/// * 2 bits to select the threshold for calibrated VDDVCO voltage
/// * When SEL_VTHVCOCON=1, select IPP generated threshold:
/// * 00 1.05v
/// * 01 1.075v
/// * 10 1.1v
/// * 11 1.125v
/// * When SEL_VTHVCOCON=0, select IPP portion for IPP+IPTAT generated threshold:
/// * 00: 31uA
/// * 01: 33uA
/// * 10: 35uA
/// * 11: 37uA
/// ###
/// %unsigned 2 VTH_VCO_PTAT 0x1
/// ###
/// * 2 bits to select IPTAT curren
/// * IPTAT current
/// * 00 0uA
/// * 01 2uA
/// * 10 4uA
/// * 11 6uA
/// ###
/// %% 21 # Stuffing bits...
/// @ 0x00010 ctrlSlowLoop (P-)
/// %unsigned 3 PW_SLLP 0x3
/// ###
/// * This set of signals define PLL
/// * 000: 2T_vco
/// * 001: 4T_vco
/// * 010: 8T_vco
/// * 011: 16T_vco
/// * 100: 32T_vco
/// * 101: 64T_vco
/// * 110:128T_vco
/// * 111:256T_vco
/// ###
/// %unsigned 1 SLLP_CLK_DIV5EN 0x0
/// ###
/// * Enable slow loop
/// * clock=200KHz, default is 100KHz
/// * SLLP_CLK_DIV5EN=0,
/// * slow loop clock is 100KHz;
/// * SLLP_CLK_DIV5EN=1,
/// * slow loop clock is 200KHz
/// ###
/// %unsigned 1 SLLP_EN_DIS 0x0
/// ###
/// * 0: Enable slow loop
/// * 1: Disable slow loop
/// ###
/// %unsigned 3 SLLP_PSF_LEVEL 0x1
/// ###
/// * IPP current control to genera
/// * SLLP_PSF_LEVEL[2] is re
/// * [1:0] IPP current
/// * 00 2uA
/// * 01 4uA
/// * 10 6uA
/// * 11 8uA
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00014 ctrlINTP (P-)
/// %unsigned 1 CLK_DET_EN 0x1
/// ###
/// * Enables PI output clock for internal reset circuit.
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 2 DPHER_DLY_SEL 0x2
/// ###
/// * Tuning DPHERCK delay
/// * 00: smallest
/// * 01
/// * 10
/// * 11: largest
/// ###
/// %unsigned 4 INTPI 0xB
/// ###
/// * Select PI bias current:
/// * INTPI[3:0] CURRENT VCO's Freq
/// * 0000 20uA
/// * 0001 22.5uA
/// * 0010 25uA 1.5GHz
/// * 0011 27.5uA
/// * 0100 30uA
/// * 0101 32.5uA 2.0GHz
/// * 0110 35uA
/// * 0111 37.5uA 2.3Ghz
/// * 1000 40uA
/// * 1001 42.5uA 2.65GHz
/// * 1010 45uA
/// * 1011 47.5uA 3GHz
/// * 1100 50uA
/// * 1101 52.5uA 3.3GHz
/// * 1110 55uA
/// * 1111 57.5uA 3.6GHz
/// * Use high frequency band on boarder
/// * Default setting is for 3.0GHz
/// ###
/// %unsigned 3 INTPR 0x2
/// ###
/// * Used for PI Rload resistor se
/// * INTPR[2:0] RES VCO's Freq
/// * 000 650
/// * 001 750 3.3~4GHz
/// * 010 900 2.65~3.3GHz
/// * 011 1150 2.0~2.65GHz
/// * 100 1500 1.5~2GHz
/// * 101 2300 1~1.5GHz
/// * 110 4600
/// * 111 RESERVED
/// * Use high frequency band on boarder
/// * Default setting is for 3.0GHz
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00018 ctrlC8AddOn (P-)
/// %unsigned 1 MASTER_SLAVEB 0x1
/// ###
/// * Used to sync frequencies
/// * if using 2 PLLs.
/// * 1 ' Master PLL
/// * 0 ' Slave PLL
/// ###
/// %unsigned 2 MODE 0x0
/// ###
/// * Mode[1:0] cali_done fbclk
/// * 0x 0 fb_vco
/// * 0x 1 fb_pi
/// * 10 x fb_vco
/// * 11 x fb_pi
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x0001C (P)
/// # 0x0001C C1
/// $avpllCh C1 REG
/// @ 0x0002C (P)
/// # 0x0002C C2
/// $avpllCh C2 REG
/// @ 0x0003C (P)
/// # 0x0003C C3
/// $avpllCh C3 REG
/// @ 0x0004C (P)
/// # 0x0004C C4
/// $avpllCh C4 REG
/// @ 0x0005C (P)
/// # 0x0005C C5
/// $avpllCh C5 REG
/// @ 0x0006C (P)
/// # 0x0006C C6
/// $avpllCh C6 REG
/// @ 0x0007C (P)
/// # 0x0007C C7
/// $avpllCh C7 REG
/// @ 0x0008C (P)
/// # 0x0008C C8
/// $avpllCh8 C8 REG
/// @ 0x0009C ctrlTest (P-)
/// %unsigned 1 CLKOUT_TST_EN 0x0
/// ###
/// * 0: CLKOUT_TST=0
/// * 1: Enable CLKOUT_TST output
/// ###
/// %unsigned 6 TEST_MON 0x0
/// ###
/// * TEST_MON[5]:
/// * 0: TP = high Z
/// * 1: enable test point
/// * If TEST_MON[5]=1 :
/// * TEST_MON[4:0] TP
/// * 0 0000 DVSS
/// * 0 0001 AVDD
/// * 0 0010 AVSS
/// * 0 0011~0 1001 AVSS
/// * 0 1010 TP_V0P7
/// * 0 1011 TP_VCOVTH
/// * 0 1100 VDDR_VCOFBUF
/// * 0 1101 TP_CHGPMP_
/// * 0 1110 TP_CHGPMP_
/// * 0 1111 VDDR_REFDIV
/// * 1 0000 VDDR_FBDIV
/// * 1 0001 VDDR_INTP_LA
/// * 1 0010 VDDR_INTP_LA
/// * 1 0011 TP_NBIAS_INTP
/// * 1 0100 DVDD
/// * 1 0101 PLL_LOCK
/// * 1 0110 PLL_CAL_EN
/// * 1 0111 PLL_CAL_DONE
/// * 1 1000 TP_VCTL_SLOW
/// * 1 1001 TP_VDAC_OUT
/// * 1 1010 TP_VDDVCO
/// * 1 1011 TP_VCON
/// * 1 1100~1 1111 AVSS
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x000A0 status (R-)
/// ###
/// * PLL status register
/// ###
/// %unsigned 1 PLL_LOCK
/// ###
/// * PLL Lock
/// * 1: PLL locked.
/// * 0: PLL not locked.
/// ###
/// %unsigned 6 RESERVE_PLL_OUT
/// %unsigned 9 FBDIV_RD
/// ###
/// * Output register bits for calibrated FBDIV[8:0]
/// ###
/// %unsigned 1 PLL_CAL_DONE
/// ###
/// * Rising edge indicate the end of PLL calibration
/// ###
/// %unsigned 6 SPEED_CNT
/// ###
/// * Output register bits for speed counter in calibration
/// ###
/// %unsigned 4 SPEED_RD
/// ###
/// * Output register bits for calibrated SPEED[3:0]
/// ###
/// %% 5 # Stuffing bits...
/// # 0x000A4 status1
/// %unsigned 7 SLLP_DAC_RD
/// ###
/// * Output register bits for calibrated SLLP_DAC[6:0]
/// ###
/// %% 25 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 168B, bits: 813b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_avPll
#define h_avPll (){}
#define RA_avPll_ctrlPLL 0x0000
#define BA_avPll_ctrlPLL_RESET 0x0000
#define B16avPll_ctrlPLL_RESET 0x0000
#define LSb32avPll_ctrlPLL_RESET 0
#define LSb16avPll_ctrlPLL_RESET 0
#define bavPll_ctrlPLL_RESET 1
#define MSK32avPll_ctrlPLL_RESET 0x00000001
#define BA_avPll_ctrlPLL_PU 0x0000
#define B16avPll_ctrlPLL_PU 0x0000
#define LSb32avPll_ctrlPLL_PU 1
#define LSb16avPll_ctrlPLL_PU 1
#define bavPll_ctrlPLL_PU 1
#define MSK32avPll_ctrlPLL_PU 0x00000002
#define BA_avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000
#define B16avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000
#define LSb32avPll_ctrlPLL_PLL_VDDRA_SEL 2
#define LSb16avPll_ctrlPLL_PLL_VDDRA_SEL 2
#define bavPll_ctrlPLL_PLL_VDDRA_SEL 3
#define MSK32avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000001C
#define BA_avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000
#define B16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000
#define LSb32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5
#define LSb16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5
#define bavPll_ctrlPLL_REG_RING_EXTRA_I_EN 1
#define MSK32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x00000020
#define BA_avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000
#define B16avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000
#define LSb32avPll_ctrlPLL_VCO_REF1P45_SEL 6
#define LSb16avPll_ctrlPLL_VCO_REF1P45_SEL 6
#define bavPll_ctrlPLL_VCO_REF1P45_SEL 2
#define MSK32avPll_ctrlPLL_VCO_REF1P45_SEL 0x000000C0
#define BA_avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0001
#define B16avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0000
#define LSb32avPll_ctrlPLL_VDDA23_PUMP_SEL 8
#define LSb16avPll_ctrlPLL_VDDA23_PUMP_SEL 8
#define bavPll_ctrlPLL_VDDA23_PUMP_SEL 2
#define MSK32avPll_ctrlPLL_VDDA23_PUMP_SEL 0x00000300
#define BA_avPll_ctrlPLL_VDDBUF_ADJ 0x0001
#define B16avPll_ctrlPLL_VDDBUF_ADJ 0x0000
#define LSb32avPll_ctrlPLL_VDDBUF_ADJ 10
#define LSb16avPll_ctrlPLL_VDDBUF_ADJ 10
#define bavPll_ctrlPLL_VDDBUF_ADJ 3
#define MSK32avPll_ctrlPLL_VDDBUF_ADJ 0x00001C00
#define BA_avPll_ctrlPLL_VDDL 0x0001
#define B16avPll_ctrlPLL_VDDL 0x0000
#define LSb32avPll_ctrlPLL_VDDL 13
#define LSb16avPll_ctrlPLL_VDDL 13
#define bavPll_ctrlPLL_VDDL 4
#define MSK32avPll_ctrlPLL_VDDL 0x0001E000
#define BA_avPll_ctrlPLL_FBDIV 0x0002
#define B16avPll_ctrlPLL_FBDIV 0x0002
#define LSb32avPll_ctrlPLL_FBDIV 17
#define LSb16avPll_ctrlPLL_FBDIV 1
#define bavPll_ctrlPLL_FBDIV 9
#define MSK32avPll_ctrlPLL_FBDIV 0x03FE0000
#define BA_avPll_ctrlPLL_ICP 0x0003
#define B16avPll_ctrlPLL_ICP 0x0002
#define LSb32avPll_ctrlPLL_ICP 26
#define LSb16avPll_ctrlPLL_ICP 10
#define bavPll_ctrlPLL_ICP 4
#define MSK32avPll_ctrlPLL_ICP 0x3C000000
#define BA_avPll_ctrlPLL_PLL_LPFC2_LESS 0x0003
#define B16avPll_ctrlPLL_PLL_LPFC2_LESS 0x0002
#define LSb32avPll_ctrlPLL_PLL_LPFC2_LESS 30
#define LSb16avPll_ctrlPLL_PLL_LPFC2_LESS 14
#define bavPll_ctrlPLL_PLL_LPFC2_LESS 1
#define MSK32avPll_ctrlPLL_PLL_LPFC2_LESS 0x40000000
#define RA_avPll_ctrlPLL1 0x0004
#define BA_avPll_ctrlPLL_REFDIV 0x0004
#define B16avPll_ctrlPLL_REFDIV 0x0004
#define LSb32avPll_ctrlPLL_REFDIV 0
#define LSb16avPll_ctrlPLL_REFDIV 0
#define bavPll_ctrlPLL_REFDIV 7
#define MSK32avPll_ctrlPLL_REFDIV 0x0000007F
#define BA_avPll_ctrlPLL_RESERVE_PLL_IN 0x0004
#define B16avPll_ctrlPLL_RESERVE_PLL_IN 0x0004
#define LSb32avPll_ctrlPLL_RESERVE_PLL_IN 7
#define LSb16avPll_ctrlPLL_RESERVE_PLL_IN 7
#define bavPll_ctrlPLL_RESERVE_PLL_IN 6
#define MSK32avPll_ctrlPLL_RESERVE_PLL_IN 0x00001F80
#define BA_avPll_ctrlPLL_EXT_SPEED 0x0005
#define B16avPll_ctrlPLL_EXT_SPEED 0x0004
#define LSb32avPll_ctrlPLL_EXT_SPEED 13
#define LSb16avPll_ctrlPLL_EXT_SPEED 13
#define bavPll_ctrlPLL_EXT_SPEED 4
#define MSK32avPll_ctrlPLL_EXT_SPEED 0x0001E000
#define BA_avPll_ctrlPLL_SPEED_FBRES 0x0006
#define B16avPll_ctrlPLL_SPEED_FBRES 0x0006
#define LSb32avPll_ctrlPLL_SPEED_FBRES 17
#define LSb16avPll_ctrlPLL_SPEED_FBRES 1
#define bavPll_ctrlPLL_SPEED_FBRES 4
#define MSK32avPll_ctrlPLL_SPEED_FBRES 0x001E0000
#define BA_avPll_ctrlPLL_UPDATE_SEL 0x0006
#define B16avPll_ctrlPLL_UPDATE_SEL 0x0006
#define LSb32avPll_ctrlPLL_UPDATE_SEL 21
#define LSb16avPll_ctrlPLL_UPDATE_SEL 5
#define bavPll_ctrlPLL_UPDATE_SEL 1
#define MSK32avPll_ctrlPLL_UPDATE_SEL 0x00200000
///////////////////////////////////////////////////////////
#define RA_avPll_ctrlCAL 0x0008
#define BA_avPll_ctrlCAL_CAL_FBDIV 0x0008
#define B16avPll_ctrlCAL_CAL_FBDIV 0x0008
#define LSb32avPll_ctrlCAL_CAL_FBDIV 0
#define LSb16avPll_ctrlCAL_CAL_FBDIV 0
#define bavPll_ctrlCAL_CAL_FBDIV 9
#define MSK32avPll_ctrlCAL_CAL_FBDIV 0x000001FF
#define BA_avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0009
#define B16avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0008
#define LSb32avPll_ctrlCAL_EXT_SLLP_DAC_EN 9
#define LSb16avPll_ctrlCAL_EXT_SLLP_DAC_EN 9
#define bavPll_ctrlCAL_EXT_SLLP_DAC_EN 1
#define MSK32avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x00000200
#define BA_avPll_ctrlCAL_EXT_SPEED_EN 0x0009
#define B16avPll_ctrlCAL_EXT_SPEED_EN 0x0008
#define LSb32avPll_ctrlCAL_EXT_SPEED_EN 10
#define LSb16avPll_ctrlCAL_EXT_SPEED_EN 10
#define bavPll_ctrlCAL_EXT_SPEED_EN 1
#define MSK32avPll_ctrlCAL_EXT_SPEED_EN 0x00000400
#define BA_avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0009
#define B16avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0008
#define LSb32avPll_ctrlCAL_EXT_SP_FBRES_EN 11
#define LSb16avPll_ctrlCAL_EXT_SP_FBRES_EN 11
#define bavPll_ctrlCAL_EXT_SP_FBRES_EN 1
#define MSK32avPll_ctrlCAL_EXT_SP_FBRES_EN 0x00000800
#define BA_avPll_ctrlCAL_PLL_CALCLK_DIV 0x0009
#define B16avPll_ctrlCAL_PLL_CALCLK_DIV 0x0008
#define LSb32avPll_ctrlCAL_PLL_CALCLK_DIV 12
#define LSb16avPll_ctrlCAL_PLL_CALCLK_DIV 12
#define bavPll_ctrlCAL_PLL_CALCLK_DIV 5
#define MSK32avPll_ctrlCAL_PLL_CALCLK_DIV 0x0001F000
#define BA_avPll_ctrlCAL_PLL_CAL_START 0x000A
#define B16avPll_ctrlCAL_PLL_CAL_START 0x000A
#define LSb32avPll_ctrlCAL_PLL_CAL_START 17
#define LSb16avPll_ctrlCAL_PLL_CAL_START 1
#define bavPll_ctrlCAL_PLL_CAL_START 1
#define MSK32avPll_ctrlCAL_PLL_CAL_START 0x00020000
#define BA_avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A
#define B16avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A
#define LSb32avPll_ctrlCAL_REG_SETTLE_LIMIT 18
#define LSb16avPll_ctrlCAL_REG_SETTLE_LIMIT 2
#define bavPll_ctrlCAL_REG_SETTLE_LIMIT 4
#define MSK32avPll_ctrlCAL_REG_SETTLE_LIMIT 0x003C0000
#define BA_avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A
#define B16avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A
#define LSb32avPll_ctrlCAL_SEL_VTHVCOCONT 22
#define LSb16avPll_ctrlCAL_SEL_VTHVCOCONT 6
#define bavPll_ctrlCAL_SEL_VTHVCOCONT 1
#define MSK32avPll_ctrlCAL_SEL_VTHVCOCONT 0x00400000
#define BA_avPll_ctrlCAL_SPEED_THRESH 0x000A
#define B16avPll_ctrlCAL_SPEED_THRESH 0x000A
#define LSb32avPll_ctrlCAL_SPEED_THRESH 23
#define LSb16avPll_ctrlCAL_SPEED_THRESH 7
#define bavPll_ctrlCAL_SPEED_THRESH 6
#define MSK32avPll_ctrlCAL_SPEED_THRESH 0x1F800000
#define BA_avPll_ctrlCAL_VCON_SEL 0x000B
#define B16avPll_ctrlCAL_VCON_SEL 0x000A
#define LSb32avPll_ctrlCAL_VCON_SEL 29
#define LSb16avPll_ctrlCAL_VCON_SEL 13
#define bavPll_ctrlCAL_VCON_SEL 2
#define MSK32avPll_ctrlCAL_VCON_SEL 0x60000000
#define RA_avPll_ctrlCAL1 0x000C
#define BA_avPll_ctrlCAL_EXT_SLLP_DAC 0x000C
#define B16avPll_ctrlCAL_EXT_SLLP_DAC 0x000C
#define LSb32avPll_ctrlCAL_EXT_SLLP_DAC 0
#define LSb16avPll_ctrlCAL_EXT_SLLP_DAC 0
#define bavPll_ctrlCAL_EXT_SLLP_DAC 7
#define MSK32avPll_ctrlCAL_EXT_SLLP_DAC 0x0000007F
#define BA_avPll_ctrlCAL_VTH_VCO_CAL 0x000C
#define B16avPll_ctrlCAL_VTH_VCO_CAL 0x000C
#define LSb32avPll_ctrlCAL_VTH_VCO_CAL 7
#define LSb16avPll_ctrlCAL_VTH_VCO_CAL 7
#define bavPll_ctrlCAL_VTH_VCO_CAL 2
#define MSK32avPll_ctrlCAL_VTH_VCO_CAL 0x00000180
#define BA_avPll_ctrlCAL_VTH_VCO_PTAT 0x000D
#define B16avPll_ctrlCAL_VTH_VCO_PTAT 0x000C
#define LSb32avPll_ctrlCAL_VTH_VCO_PTAT 9
#define LSb16avPll_ctrlCAL_VTH_VCO_PTAT 9
#define bavPll_ctrlCAL_VTH_VCO_PTAT 2
#define MSK32avPll_ctrlCAL_VTH_VCO_PTAT 0x00000600
///////////////////////////////////////////////////////////
#define RA_avPll_ctrlSlowLoop 0x0010
#define BA_avPll_ctrlSlowLoop_PW_SLLP 0x0010
#define B16avPll_ctrlSlowLoop_PW_SLLP 0x0010
#define LSb32avPll_ctrlSlowLoop_PW_SLLP 0
#define LSb16avPll_ctrlSlowLoop_PW_SLLP 0
#define bavPll_ctrlSlowLoop_PW_SLLP 3
#define MSK32avPll_ctrlSlowLoop_PW_SLLP 0x00000007
#define BA_avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010
#define B16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010
#define LSb32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3
#define LSb16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3
#define bavPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 1
#define MSK32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x00000008
#define BA_avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010
#define B16avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010
#define LSb32avPll_ctrlSlowLoop_SLLP_EN_DIS 4
#define LSb16avPll_ctrlSlowLoop_SLLP_EN_DIS 4
#define bavPll_ctrlSlowLoop_SLLP_EN_DIS 1
#define MSK32avPll_ctrlSlowLoop_SLLP_EN_DIS 0x00000010
#define BA_avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010
#define B16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010
#define LSb32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5
#define LSb16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5
#define bavPll_ctrlSlowLoop_SLLP_PSF_LEVEL 3
#define MSK32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x000000E0
///////////////////////////////////////////////////////////
#define RA_avPll_ctrlINTP 0x0014
#define BA_avPll_ctrlINTP_CLK_DET_EN 0x0014
#define B16avPll_ctrlINTP_CLK_DET_EN 0x0014
#define LSb32avPll_ctrlINTP_CLK_DET_EN 0
#define LSb16avPll_ctrlINTP_CLK_DET_EN 0
#define bavPll_ctrlINTP_CLK_DET_EN 1
#define MSK32avPll_ctrlINTP_CLK_DET_EN 0x00000001
#define BA_avPll_ctrlINTP_DPHER_DLY_SEL 0x0014
#define B16avPll_ctrlINTP_DPHER_DLY_SEL 0x0014
#define LSb32avPll_ctrlINTP_DPHER_DLY_SEL 1
#define LSb16avPll_ctrlINTP_DPHER_DLY_SEL 1
#define bavPll_ctrlINTP_DPHER_DLY_SEL 2
#define MSK32avPll_ctrlINTP_DPHER_DLY_SEL 0x00000006
#define BA_avPll_ctrlINTP_INTPI 0x0014
#define B16avPll_ctrlINTP_INTPI 0x0014
#define LSb32avPll_ctrlINTP_INTPI 3
#define LSb16avPll_ctrlINTP_INTPI 3
#define bavPll_ctrlINTP_INTPI 4
#define MSK32avPll_ctrlINTP_INTPI 0x00000078
#define BA_avPll_ctrlINTP_INTPR 0x0014
#define B16avPll_ctrlINTP_INTPR 0x0014
#define LSb32avPll_ctrlINTP_INTPR 7
#define LSb16avPll_ctrlINTP_INTPR 7
#define bavPll_ctrlINTP_INTPR 3
#define MSK32avPll_ctrlINTP_INTPR 0x00000380
///////////////////////////////////////////////////////////
#define RA_avPll_ctrlC8AddOn 0x0018
#define BA_avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018
#define B16avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018
#define LSb32avPll_ctrlC8AddOn_MASTER_SLAVEB 0
#define LSb16avPll_ctrlC8AddOn_MASTER_SLAVEB 0
#define bavPll_ctrlC8AddOn_MASTER_SLAVEB 1
#define MSK32avPll_ctrlC8AddOn_MASTER_SLAVEB 0x00000001
#define BA_avPll_ctrlC8AddOn_MODE 0x0018
#define B16avPll_ctrlC8AddOn_MODE 0x0018
#define LSb32avPll_ctrlC8AddOn_MODE 1
#define LSb16avPll_ctrlC8AddOn_MODE 1
#define bavPll_ctrlC8AddOn_MODE 2
#define MSK32avPll_ctrlC8AddOn_MODE 0x00000006
///////////////////////////////////////////////////////////
#define RA_avPll_C1 0x001C
///////////////////////////////////////////////////////////
#define RA_avPll_C2 0x002C
///////////////////////////////////////////////////////////
#define RA_avPll_C3 0x003C
///////////////////////////////////////////////////////////
#define RA_avPll_C4 0x004C
///////////////////////////////////////////////////////////
#define RA_avPll_C5 0x005C
///////////////////////////////////////////////////////////
#define RA_avPll_C6 0x006C
///////////////////////////////////////////////////////////
#define RA_avPll_C7 0x007C
///////////////////////////////////////////////////////////
#define RA_avPll_C8 0x008C
///////////////////////////////////////////////////////////
#define RA_avPll_ctrlTest 0x009C
#define BA_avPll_ctrlTest_CLKOUT_TST_EN 0x009C
#define B16avPll_ctrlTest_CLKOUT_TST_EN 0x009C
#define LSb32avPll_ctrlTest_CLKOUT_TST_EN 0
#define LSb16avPll_ctrlTest_CLKOUT_TST_EN 0
#define bavPll_ctrlTest_CLKOUT_TST_EN 1
#define MSK32avPll_ctrlTest_CLKOUT_TST_EN 0x00000001
#define BA_avPll_ctrlTest_TEST_MON 0x009C
#define B16avPll_ctrlTest_TEST_MON 0x009C
#define LSb32avPll_ctrlTest_TEST_MON 1
#define LSb16avPll_ctrlTest_TEST_MON 1
#define bavPll_ctrlTest_TEST_MON 6
#define MSK32avPll_ctrlTest_TEST_MON 0x0000007E
///////////////////////////////////////////////////////////
#define RA_avPll_status 0x00A0
#define BA_avPll_status_PLL_LOCK 0x00A0
#define B16avPll_status_PLL_LOCK 0x00A0
#define LSb32avPll_status_PLL_LOCK 0
#define LSb16avPll_status_PLL_LOCK 0
#define bavPll_status_PLL_LOCK 1
#define MSK32avPll_status_PLL_LOCK 0x00000001
#define BA_avPll_status_RESERVE_PLL_OUT 0x00A0
#define B16avPll_status_RESERVE_PLL_OUT 0x00A0
#define LSb32avPll_status_RESERVE_PLL_OUT 1
#define LSb16avPll_status_RESERVE_PLL_OUT 1
#define bavPll_status_RESERVE_PLL_OUT 6
#define MSK32avPll_status_RESERVE_PLL_OUT 0x0000007E
#define BA_avPll_status_FBDIV_RD 0x00A0
#define B16avPll_status_FBDIV_RD 0x00A0
#define LSb32avPll_status_FBDIV_RD 7
#define LSb16avPll_status_FBDIV_RD 7
#define bavPll_status_FBDIV_RD 9
#define MSK32avPll_status_FBDIV_RD 0x0000FF80
#define BA_avPll_status_PLL_CAL_DONE 0x00A2
#define B16avPll_status_PLL_CAL_DONE 0x00A2
#define LSb32avPll_status_PLL_CAL_DONE 16
#define LSb16avPll_status_PLL_CAL_DONE 0
#define bavPll_status_PLL_CAL_DONE 1
#define MSK32avPll_status_PLL_CAL_DONE 0x00010000
#define BA_avPll_status_SPEED_CNT 0x00A2
#define B16avPll_status_SPEED_CNT 0x00A2
#define LSb32avPll_status_SPEED_CNT 17
#define LSb16avPll_status_SPEED_CNT 1
#define bavPll_status_SPEED_CNT 6
#define MSK32avPll_status_SPEED_CNT 0x007E0000
#define BA_avPll_status_SPEED_RD 0x00A2
#define B16avPll_status_SPEED_RD 0x00A2
#define LSb32avPll_status_SPEED_RD 23
#define LSb16avPll_status_SPEED_RD 7
#define bavPll_status_SPEED_RD 4
#define MSK32avPll_status_SPEED_RD 0x07800000
#define RA_avPll_status1 0x00A4
#define BA_avPll_status_SLLP_DAC_RD 0x00A4
#define B16avPll_status_SLLP_DAC_RD 0x00A4
#define LSb32avPll_status_SLLP_DAC_RD 0
#define LSb16avPll_status_SLLP_DAC_RD 0
#define bavPll_status_SLLP_DAC_RD 7
#define MSK32avPll_status_SLLP_DAC_RD 0x0000007F
///////////////////////////////////////////////////////////
typedef struct SIE_avPll {
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlPLL_RESET(r32) _BFGET_(r32, 0, 0)
#define SET32avPll_ctrlPLL_RESET(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16avPll_ctrlPLL_RESET(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_ctrlPLL_RESET(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_ctrlPLL_PU(r32) _BFGET_(r32, 1, 1)
#define SET32avPll_ctrlPLL_PU(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16avPll_ctrlPLL_PU(r16) _BFGET_(r16, 1, 1)
#define SET16avPll_ctrlPLL_PU(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32avPll_ctrlPLL_PLL_VDDRA_SEL(r32) _BFGET_(r32, 4, 2)
#define SET32avPll_ctrlPLL_PLL_VDDRA_SEL(r32,v) _BFSET_(r32, 4, 2,v)
#define GET16avPll_ctrlPLL_PLL_VDDRA_SEL(r16) _BFGET_(r16, 4, 2)
#define SET16avPll_ctrlPLL_PLL_VDDRA_SEL(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r32) _BFGET_(r32, 5, 5)
#define SET32avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r16) _BFGET_(r16, 5, 5)
#define SET16avPll_ctrlPLL_REG_RING_EXTRA_I_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32avPll_ctrlPLL_VCO_REF1P45_SEL(r32) _BFGET_(r32, 7, 6)
#define SET32avPll_ctrlPLL_VCO_REF1P45_SEL(r32,v) _BFSET_(r32, 7, 6,v)
#define GET16avPll_ctrlPLL_VCO_REF1P45_SEL(r16) _BFGET_(r16, 7, 6)
#define SET16avPll_ctrlPLL_VCO_REF1P45_SEL(r16,v) _BFSET_(r16, 7, 6,v)
#define GET32avPll_ctrlPLL_VDDA23_PUMP_SEL(r32) _BFGET_(r32, 9, 8)
#define SET32avPll_ctrlPLL_VDDA23_PUMP_SEL(r32,v) _BFSET_(r32, 9, 8,v)
#define GET16avPll_ctrlPLL_VDDA23_PUMP_SEL(r16) _BFGET_(r16, 9, 8)
#define SET16avPll_ctrlPLL_VDDA23_PUMP_SEL(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32avPll_ctrlPLL_VDDBUF_ADJ(r32) _BFGET_(r32,12,10)
#define SET32avPll_ctrlPLL_VDDBUF_ADJ(r32,v) _BFSET_(r32,12,10,v)
#define GET16avPll_ctrlPLL_VDDBUF_ADJ(r16) _BFGET_(r16,12,10)
#define SET16avPll_ctrlPLL_VDDBUF_ADJ(r16,v) _BFSET_(r16,12,10,v)
#define GET32avPll_ctrlPLL_VDDL(r32) _BFGET_(r32,16,13)
#define SET32avPll_ctrlPLL_VDDL(r32,v) _BFSET_(r32,16,13,v)
#define GET32avPll_ctrlPLL_FBDIV(r32) _BFGET_(r32,25,17)
#define SET32avPll_ctrlPLL_FBDIV(r32,v) _BFSET_(r32,25,17,v)
#define GET16avPll_ctrlPLL_FBDIV(r16) _BFGET_(r16, 9, 1)
#define SET16avPll_ctrlPLL_FBDIV(r16,v) _BFSET_(r16, 9, 1,v)
#define GET32avPll_ctrlPLL_ICP(r32) _BFGET_(r32,29,26)
#define SET32avPll_ctrlPLL_ICP(r32,v) _BFSET_(r32,29,26,v)
#define GET16avPll_ctrlPLL_ICP(r16) _BFGET_(r16,13,10)
#define SET16avPll_ctrlPLL_ICP(r16,v) _BFSET_(r16,13,10,v)
#define GET32avPll_ctrlPLL_PLL_LPFC2_LESS(r32) _BFGET_(r32,30,30)
#define SET32avPll_ctrlPLL_PLL_LPFC2_LESS(r32,v) _BFSET_(r32,30,30,v)
#define GET16avPll_ctrlPLL_PLL_LPFC2_LESS(r16) _BFGET_(r16,14,14)
#define SET16avPll_ctrlPLL_PLL_LPFC2_LESS(r16,v) _BFSET_(r16,14,14,v)
#define w32avPll_ctrlPLL {\
UNSG32 uctrlPLL_RESET : 1;\
UNSG32 uctrlPLL_PU : 1;\
UNSG32 uctrlPLL_PLL_VDDRA_SEL : 3;\
UNSG32 uctrlPLL_REG_RING_EXTRA_I_EN : 1;\
UNSG32 uctrlPLL_VCO_REF1P45_SEL : 2;\
UNSG32 uctrlPLL_VDDA23_PUMP_SEL : 2;\
UNSG32 uctrlPLL_VDDBUF_ADJ : 3;\
UNSG32 uctrlPLL_VDDL : 4;\
UNSG32 uctrlPLL_FBDIV : 9;\
UNSG32 uctrlPLL_ICP : 4;\
UNSG32 uctrlPLL_PLL_LPFC2_LESS : 1;\
UNSG32 RSVDx0_b31 : 1;\
}
union { UNSG32 u32avPll_ctrlPLL;
struct w32avPll_ctrlPLL;
};
#define GET32avPll_ctrlPLL_REFDIV(r32) _BFGET_(r32, 6, 0)
#define SET32avPll_ctrlPLL_REFDIV(r32,v) _BFSET_(r32, 6, 0,v)
#define GET16avPll_ctrlPLL_REFDIV(r16) _BFGET_(r16, 6, 0)
#define SET16avPll_ctrlPLL_REFDIV(r16,v) _BFSET_(r16, 6, 0,v)
#define GET32avPll_ctrlPLL_RESERVE_PLL_IN(r32) _BFGET_(r32,12, 7)
#define SET32avPll_ctrlPLL_RESERVE_PLL_IN(r32,v) _BFSET_(r32,12, 7,v)
#define GET16avPll_ctrlPLL_RESERVE_PLL_IN(r16) _BFGET_(r16,12, 7)
#define SET16avPll_ctrlPLL_RESERVE_PLL_IN(r16,v) _BFSET_(r16,12, 7,v)
#define GET32avPll_ctrlPLL_EXT_SPEED(r32) _BFGET_(r32,16,13)
#define SET32avPll_ctrlPLL_EXT_SPEED(r32,v) _BFSET_(r32,16,13,v)
#define GET32avPll_ctrlPLL_SPEED_FBRES(r32) _BFGET_(r32,20,17)
#define SET32avPll_ctrlPLL_SPEED_FBRES(r32,v) _BFSET_(r32,20,17,v)
#define GET16avPll_ctrlPLL_SPEED_FBRES(r16) _BFGET_(r16, 4, 1)
#define SET16avPll_ctrlPLL_SPEED_FBRES(r16,v) _BFSET_(r16, 4, 1,v)
#define GET32avPll_ctrlPLL_UPDATE_SEL(r32) _BFGET_(r32,21,21)
#define SET32avPll_ctrlPLL_UPDATE_SEL(r32,v) _BFSET_(r32,21,21,v)
#define GET16avPll_ctrlPLL_UPDATE_SEL(r16) _BFGET_(r16, 5, 5)
#define SET16avPll_ctrlPLL_UPDATE_SEL(r16,v) _BFSET_(r16, 5, 5,v)
#define w32avPll_ctrlPLL1 {\
UNSG32 uctrlPLL_REFDIV : 7;\
UNSG32 uctrlPLL_RESERVE_PLL_IN : 6;\
UNSG32 uctrlPLL_EXT_SPEED : 4;\
UNSG32 uctrlPLL_SPEED_FBRES : 4;\
UNSG32 uctrlPLL_UPDATE_SEL : 1;\
UNSG32 RSVDx4_b22 : 10;\
}
union { UNSG32 u32avPll_ctrlPLL1;
struct w32avPll_ctrlPLL1;
};
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlCAL_CAL_FBDIV(r32) _BFGET_(r32, 8, 0)
#define SET32avPll_ctrlCAL_CAL_FBDIV(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16avPll_ctrlCAL_CAL_FBDIV(r16) _BFGET_(r16, 8, 0)
#define SET16avPll_ctrlCAL_CAL_FBDIV(r16,v) _BFSET_(r16, 8, 0,v)
#define GET32avPll_ctrlCAL_EXT_SLLP_DAC_EN(r32) _BFGET_(r32, 9, 9)
#define SET32avPll_ctrlCAL_EXT_SLLP_DAC_EN(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16avPll_ctrlCAL_EXT_SLLP_DAC_EN(r16) _BFGET_(r16, 9, 9)
#define SET16avPll_ctrlCAL_EXT_SLLP_DAC_EN(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32avPll_ctrlCAL_EXT_SPEED_EN(r32) _BFGET_(r32,10,10)
#define SET32avPll_ctrlCAL_EXT_SPEED_EN(r32,v) _BFSET_(r32,10,10,v)
#define GET16avPll_ctrlCAL_EXT_SPEED_EN(r16) _BFGET_(r16,10,10)
#define SET16avPll_ctrlCAL_EXT_SPEED_EN(r16,v) _BFSET_(r16,10,10,v)
#define GET32avPll_ctrlCAL_EXT_SP_FBRES_EN(r32) _BFGET_(r32,11,11)
#define SET32avPll_ctrlCAL_EXT_SP_FBRES_EN(r32,v) _BFSET_(r32,11,11,v)
#define GET16avPll_ctrlCAL_EXT_SP_FBRES_EN(r16) _BFGET_(r16,11,11)
#define SET16avPll_ctrlCAL_EXT_SP_FBRES_EN(r16,v) _BFSET_(r16,11,11,v)
#define GET32avPll_ctrlCAL_PLL_CALCLK_DIV(r32) _BFGET_(r32,16,12)
#define SET32avPll_ctrlCAL_PLL_CALCLK_DIV(r32,v) _BFSET_(r32,16,12,v)
#define GET32avPll_ctrlCAL_PLL_CAL_START(r32) _BFGET_(r32,17,17)
#define SET32avPll_ctrlCAL_PLL_CAL_START(r32,v) _BFSET_(r32,17,17,v)
#define GET16avPll_ctrlCAL_PLL_CAL_START(r16) _BFGET_(r16, 1, 1)
#define SET16avPll_ctrlCAL_PLL_CAL_START(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32avPll_ctrlCAL_REG_SETTLE_LIMIT(r32) _BFGET_(r32,21,18)
#define SET32avPll_ctrlCAL_REG_SETTLE_LIMIT(r32,v) _BFSET_(r32,21,18,v)
#define GET16avPll_ctrlCAL_REG_SETTLE_LIMIT(r16) _BFGET_(r16, 5, 2)
#define SET16avPll_ctrlCAL_REG_SETTLE_LIMIT(r16,v) _BFSET_(r16, 5, 2,v)
#define GET32avPll_ctrlCAL_SEL_VTHVCOCONT(r32) _BFGET_(r32,22,22)
#define SET32avPll_ctrlCAL_SEL_VTHVCOCONT(r32,v) _BFSET_(r32,22,22,v)
#define GET16avPll_ctrlCAL_SEL_VTHVCOCONT(r16) _BFGET_(r16, 6, 6)
#define SET16avPll_ctrlCAL_SEL_VTHVCOCONT(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32avPll_ctrlCAL_SPEED_THRESH(r32) _BFGET_(r32,28,23)
#define SET32avPll_ctrlCAL_SPEED_THRESH(r32,v) _BFSET_(r32,28,23,v)
#define GET16avPll_ctrlCAL_SPEED_THRESH(r16) _BFGET_(r16,12, 7)
#define SET16avPll_ctrlCAL_SPEED_THRESH(r16,v) _BFSET_(r16,12, 7,v)
#define GET32avPll_ctrlCAL_VCON_SEL(r32) _BFGET_(r32,30,29)
#define SET32avPll_ctrlCAL_VCON_SEL(r32,v) _BFSET_(r32,30,29,v)
#define GET16avPll_ctrlCAL_VCON_SEL(r16) _BFGET_(r16,14,13)
#define SET16avPll_ctrlCAL_VCON_SEL(r16,v) _BFSET_(r16,14,13,v)
#define w32avPll_ctrlCAL {\
UNSG32 uctrlCAL_CAL_FBDIV : 9;\
UNSG32 uctrlCAL_EXT_SLLP_DAC_EN : 1;\
UNSG32 uctrlCAL_EXT_SPEED_EN : 1;\
UNSG32 uctrlCAL_EXT_SP_FBRES_EN : 1;\
UNSG32 uctrlCAL_PLL_CALCLK_DIV : 5;\
UNSG32 uctrlCAL_PLL_CAL_START : 1;\
UNSG32 uctrlCAL_REG_SETTLE_LIMIT : 4;\
UNSG32 uctrlCAL_SEL_VTHVCOCONT : 1;\
UNSG32 uctrlCAL_SPEED_THRESH : 6;\
UNSG32 uctrlCAL_VCON_SEL : 2;\
UNSG32 RSVDx8_b31 : 1;\
}
union { UNSG32 u32avPll_ctrlCAL;
struct w32avPll_ctrlCAL;
};
#define GET32avPll_ctrlCAL_EXT_SLLP_DAC(r32) _BFGET_(r32, 6, 0)
#define SET32avPll_ctrlCAL_EXT_SLLP_DAC(r32,v) _BFSET_(r32, 6, 0,v)
#define GET16avPll_ctrlCAL_EXT_SLLP_DAC(r16) _BFGET_(r16, 6, 0)
#define SET16avPll_ctrlCAL_EXT_SLLP_DAC(r16,v) _BFSET_(r16, 6, 0,v)
#define GET32avPll_ctrlCAL_VTH_VCO_CAL(r32) _BFGET_(r32, 8, 7)
#define SET32avPll_ctrlCAL_VTH_VCO_CAL(r32,v) _BFSET_(r32, 8, 7,v)
#define GET16avPll_ctrlCAL_VTH_VCO_CAL(r16) _BFGET_(r16, 8, 7)
#define SET16avPll_ctrlCAL_VTH_VCO_CAL(r16,v) _BFSET_(r16, 8, 7,v)
#define GET32avPll_ctrlCAL_VTH_VCO_PTAT(r32) _BFGET_(r32,10, 9)
#define SET32avPll_ctrlCAL_VTH_VCO_PTAT(r32,v) _BFSET_(r32,10, 9,v)
#define GET16avPll_ctrlCAL_VTH_VCO_PTAT(r16) _BFGET_(r16,10, 9)
#define SET16avPll_ctrlCAL_VTH_VCO_PTAT(r16,v) _BFSET_(r16,10, 9,v)
#define w32avPll_ctrlCAL1 {\
UNSG32 uctrlCAL_EXT_SLLP_DAC : 7;\
UNSG32 uctrlCAL_VTH_VCO_CAL : 2;\
UNSG32 uctrlCAL_VTH_VCO_PTAT : 2;\
UNSG32 RSVDxC_b11 : 21;\
}
union { UNSG32 u32avPll_ctrlCAL1;
struct w32avPll_ctrlCAL1;
};
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlSlowLoop_PW_SLLP(r32) _BFGET_(r32, 2, 0)
#define SET32avPll_ctrlSlowLoop_PW_SLLP(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16avPll_ctrlSlowLoop_PW_SLLP(r16) _BFGET_(r16, 2, 0)
#define SET16avPll_ctrlSlowLoop_PW_SLLP(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r32) _BFGET_(r32, 3, 3)
#define SET32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r16) _BFGET_(r16, 3, 3)
#define SET16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32avPll_ctrlSlowLoop_SLLP_EN_DIS(r32) _BFGET_(r32, 4, 4)
#define SET32avPll_ctrlSlowLoop_SLLP_EN_DIS(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16avPll_ctrlSlowLoop_SLLP_EN_DIS(r16) _BFGET_(r16, 4, 4)
#define SET16avPll_ctrlSlowLoop_SLLP_EN_DIS(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r32) _BFGET_(r32, 7, 5)
#define SET32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r32,v) _BFSET_(r32, 7, 5,v)
#define GET16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r16) _BFGET_(r16, 7, 5)
#define SET16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL(r16,v) _BFSET_(r16, 7, 5,v)
#define w32avPll_ctrlSlowLoop {\
UNSG32 uctrlSlowLoop_PW_SLLP : 3;\
UNSG32 uctrlSlowLoop_SLLP_CLK_DIV5EN : 1;\
UNSG32 uctrlSlowLoop_SLLP_EN_DIS : 1;\
UNSG32 uctrlSlowLoop_SLLP_PSF_LEVEL : 3;\
UNSG32 RSVDx10_b8 : 24;\
}
union { UNSG32 u32avPll_ctrlSlowLoop;
struct w32avPll_ctrlSlowLoop;
};
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlINTP_CLK_DET_EN(r32) _BFGET_(r32, 0, 0)
#define SET32avPll_ctrlINTP_CLK_DET_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16avPll_ctrlINTP_CLK_DET_EN(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_ctrlINTP_CLK_DET_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_ctrlINTP_DPHER_DLY_SEL(r32) _BFGET_(r32, 2, 1)
#define SET32avPll_ctrlINTP_DPHER_DLY_SEL(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16avPll_ctrlINTP_DPHER_DLY_SEL(r16) _BFGET_(r16, 2, 1)
#define SET16avPll_ctrlINTP_DPHER_DLY_SEL(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32avPll_ctrlINTP_INTPI(r32) _BFGET_(r32, 6, 3)
#define SET32avPll_ctrlINTP_INTPI(r32,v) _BFSET_(r32, 6, 3,v)
#define GET16avPll_ctrlINTP_INTPI(r16) _BFGET_(r16, 6, 3)
#define SET16avPll_ctrlINTP_INTPI(r16,v) _BFSET_(r16, 6, 3,v)
#define GET32avPll_ctrlINTP_INTPR(r32) _BFGET_(r32, 9, 7)
#define SET32avPll_ctrlINTP_INTPR(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16avPll_ctrlINTP_INTPR(r16) _BFGET_(r16, 9, 7)
#define SET16avPll_ctrlINTP_INTPR(r16,v) _BFSET_(r16, 9, 7,v)
#define w32avPll_ctrlINTP {\
UNSG32 uctrlINTP_CLK_DET_EN : 1;\
UNSG32 uctrlINTP_DPHER_DLY_SEL : 2;\
UNSG32 uctrlINTP_INTPI : 4;\
UNSG32 uctrlINTP_INTPR : 3;\
UNSG32 RSVDx14_b10 : 22;\
}
union { UNSG32 u32avPll_ctrlINTP;
struct w32avPll_ctrlINTP;
};
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlC8AddOn_MASTER_SLAVEB(r32) _BFGET_(r32, 0, 0)
#define SET32avPll_ctrlC8AddOn_MASTER_SLAVEB(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16avPll_ctrlC8AddOn_MASTER_SLAVEB(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_ctrlC8AddOn_MASTER_SLAVEB(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_ctrlC8AddOn_MODE(r32) _BFGET_(r32, 2, 1)
#define SET32avPll_ctrlC8AddOn_MODE(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16avPll_ctrlC8AddOn_MODE(r16) _BFGET_(r16, 2, 1)
#define SET16avPll_ctrlC8AddOn_MODE(r16,v) _BFSET_(r16, 2, 1,v)
#define w32avPll_ctrlC8AddOn {\
UNSG32 uctrlC8AddOn_MASTER_SLAVEB : 1;\
UNSG32 uctrlC8AddOn_MODE : 2;\
UNSG32 RSVDx18_b3 : 29;\
}
union { UNSG32 u32avPll_ctrlC8AddOn;
struct w32avPll_ctrlC8AddOn;
};
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C1;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C2;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C3;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C4;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C5;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C6;
///////////////////////////////////////////////////////////
SIE_avpllCh ie_C7;
///////////////////////////////////////////////////////////
SIE_avpllCh8 ie_C8;
///////////////////////////////////////////////////////////
#define GET32avPll_ctrlTest_CLKOUT_TST_EN(r32) _BFGET_(r32, 0, 0)
#define SET32avPll_ctrlTest_CLKOUT_TST_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16avPll_ctrlTest_CLKOUT_TST_EN(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_ctrlTest_CLKOUT_TST_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_ctrlTest_TEST_MON(r32) _BFGET_(r32, 6, 1)
#define SET32avPll_ctrlTest_TEST_MON(r32,v) _BFSET_(r32, 6, 1,v)
#define GET16avPll_ctrlTest_TEST_MON(r16) _BFGET_(r16, 6, 1)
#define SET16avPll_ctrlTest_TEST_MON(r16,v) _BFSET_(r16, 6, 1,v)
#define w32avPll_ctrlTest {\
UNSG32 uctrlTest_CLKOUT_TST_EN : 1;\
UNSG32 uctrlTest_TEST_MON : 6;\
UNSG32 RSVDx9C_b7 : 25;\
}
union { UNSG32 u32avPll_ctrlTest;
struct w32avPll_ctrlTest;
};
///////////////////////////////////////////////////////////
#define GET32avPll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32avPll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16avPll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_status_RESERVE_PLL_OUT(r32) _BFGET_(r32, 6, 1)
#define SET32avPll_status_RESERVE_PLL_OUT(r32,v) _BFSET_(r32, 6, 1,v)
#define GET16avPll_status_RESERVE_PLL_OUT(r16) _BFGET_(r16, 6, 1)
#define SET16avPll_status_RESERVE_PLL_OUT(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32avPll_status_FBDIV_RD(r32) _BFGET_(r32,15, 7)
#define SET32avPll_status_FBDIV_RD(r32,v) _BFSET_(r32,15, 7,v)
#define GET16avPll_status_FBDIV_RD(r16) _BFGET_(r16,15, 7)
#define SET16avPll_status_FBDIV_RD(r16,v) _BFSET_(r16,15, 7,v)
#define GET32avPll_status_PLL_CAL_DONE(r32) _BFGET_(r32,16,16)
#define SET32avPll_status_PLL_CAL_DONE(r32,v) _BFSET_(r32,16,16,v)
#define GET16avPll_status_PLL_CAL_DONE(r16) _BFGET_(r16, 0, 0)
#define SET16avPll_status_PLL_CAL_DONE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32avPll_status_SPEED_CNT(r32) _BFGET_(r32,22,17)
#define SET32avPll_status_SPEED_CNT(r32,v) _BFSET_(r32,22,17,v)
#define GET16avPll_status_SPEED_CNT(r16) _BFGET_(r16, 6, 1)
#define SET16avPll_status_SPEED_CNT(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32avPll_status_SPEED_RD(r32) _BFGET_(r32,26,23)
#define SET32avPll_status_SPEED_RD(r32,v) _BFSET_(r32,26,23,v)
#define GET16avPll_status_SPEED_RD(r16) _BFGET_(r16,10, 7)
#define SET16avPll_status_SPEED_RD(r16,v) _BFSET_(r16,10, 7,v)
#define w32avPll_status {\
UNSG32 ustatus_PLL_LOCK : 1;\
UNSG32 ustatus_RESERVE_PLL_OUT : 6;\
UNSG32 ustatus_FBDIV_RD : 9;\
UNSG32 ustatus_PLL_CAL_DONE : 1;\
UNSG32 ustatus_SPEED_CNT : 6;\
UNSG32 ustatus_SPEED_RD : 4;\
UNSG32 RSVDxA0_b27 : 5;\
}
union { UNSG32 u32avPll_status;
struct w32avPll_status;
};
#define GET32avPll_status_SLLP_DAC_RD(r32) _BFGET_(r32, 6, 0)
#define SET32avPll_status_SLLP_DAC_RD(r32,v) _BFSET_(r32, 6, 0,v)
#define GET16avPll_status_SLLP_DAC_RD(r16) _BFGET_(r16, 6, 0)
#define SET16avPll_status_SLLP_DAC_RD(r16,v) _BFSET_(r16, 6, 0,v)
#define w32avPll_status1 {\
UNSG32 ustatus_SLLP_DAC_RD : 7;\
UNSG32 RSVDxA4_b7 : 25;\
}
union { UNSG32 u32avPll_status1;
struct w32avPll_status1;
};
///////////////////////////////////////////////////////////
} SIE_avPll;
typedef union T32avPll_ctrlPLL
{ UNSG32 u32;
struct w32avPll_ctrlPLL;
} T32avPll_ctrlPLL;
typedef union T32avPll_ctrlPLL1
{ UNSG32 u32;
struct w32avPll_ctrlPLL1;
} T32avPll_ctrlPLL1;
typedef union T32avPll_ctrlCAL
{ UNSG32 u32;
struct w32avPll_ctrlCAL;
} T32avPll_ctrlCAL;
typedef union T32avPll_ctrlCAL1
{ UNSG32 u32;
struct w32avPll_ctrlCAL1;
} T32avPll_ctrlCAL1;
typedef union T32avPll_ctrlSlowLoop
{ UNSG32 u32;
struct w32avPll_ctrlSlowLoop;
} T32avPll_ctrlSlowLoop;
typedef union T32avPll_ctrlINTP
{ UNSG32 u32;
struct w32avPll_ctrlINTP;
} T32avPll_ctrlINTP;
typedef union T32avPll_ctrlC8AddOn
{ UNSG32 u32;
struct w32avPll_ctrlC8AddOn;
} T32avPll_ctrlC8AddOn;
typedef union T32avPll_ctrlTest
{ UNSG32 u32;
struct w32avPll_ctrlTest;
} T32avPll_ctrlTest;
typedef union T32avPll_status
{ UNSG32 u32;
struct w32avPll_status;
} T32avPll_status;
typedef union T32avPll_status1
{ UNSG32 u32;
struct w32avPll_status1;
} T32avPll_status1;
///////////////////////////////////////////////////////////
typedef union TavPll_ctrlPLL
{ UNSG32 u32[2];
struct {
struct w32avPll_ctrlPLL;
struct w32avPll_ctrlPLL1;
};
} TavPll_ctrlPLL;
typedef union TavPll_ctrlCAL
{ UNSG32 u32[2];
struct {
struct w32avPll_ctrlCAL;
struct w32avPll_ctrlCAL1;
};
} TavPll_ctrlCAL;
typedef union TavPll_ctrlSlowLoop
{ UNSG32 u32[1];
struct {
struct w32avPll_ctrlSlowLoop;
};
} TavPll_ctrlSlowLoop;
typedef union TavPll_ctrlINTP
{ UNSG32 u32[1];
struct {
struct w32avPll_ctrlINTP;
};
} TavPll_ctrlINTP;
typedef union TavPll_ctrlC8AddOn
{ UNSG32 u32[1];
struct {
struct w32avPll_ctrlC8AddOn;
};
} TavPll_ctrlC8AddOn;
typedef union TavPll_ctrlTest
{ UNSG32 u32[1];
struct {
struct w32avPll_ctrlTest;
};
} TavPll_ctrlTest;
typedef union TavPll_status
{ UNSG32 u32[2];
struct {
struct w32avPll_status;
struct w32avPll_status1;
};
} TavPll_status;
///////////////////////////////////////////////////////////
SIGN32 avPll_drvrd(SIE_avPll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 avPll_drvwr(SIE_avPll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void avPll_reset(SIE_avPll *p);
SIGN32 avPll_cmp (SIE_avPll *p, SIE_avPll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define avPll_check(p,pie,pfx,hLOG) avPll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define avPll_print(p, pfx,hLOG) avPll_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: avPll
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pwrOff (4,4)
/// ###
/// * Register for the Power domain which is OFF by default
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (RW-)
/// ###
/// * Power Domain Control Register
/// ###
/// %unsigned 1 iso_eN 0x0
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Isolation control bit. Active low
/// * 0 : Isolation is enabled
/// * 1 : Isolation is disabled (default)
/// ###
/// %unsigned 2 pwrSwitchCtrl 0x0
/// : PWROFF 0x0
/// : PWRON 0x3
/// ###
/// * Power Switch control
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %unsigned 1 pwrDomainRstN 0x0
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Power Domain Reset. Active low.
/// * 0 : Reset the power domain
/// * 1: De-assert the reset for the power domain
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 2 pwrStatus
/// ###
/// * Power domain Status output from the power domain module
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOff
#define h_pwrOff (){}
#define RA_pwrOff_ctrl 0x0000
#define BA_pwrOff_ctrl_iso_eN 0x0000
#define B16pwrOff_ctrl_iso_eN 0x0000
#define LSb32pwrOff_ctrl_iso_eN 0
#define LSb16pwrOff_ctrl_iso_eN 0
#define bpwrOff_ctrl_iso_eN 1
#define MSK32pwrOff_ctrl_iso_eN 0x00000001
#define pwrOff_ctrl_iso_eN_enable 0x0
#define pwrOff_ctrl_iso_eN_disable 0x1
#define BA_pwrOff_ctrl_pwrSwitchCtrl 0x0000
#define B16pwrOff_ctrl_pwrSwitchCtrl 0x0000
#define LSb32pwrOff_ctrl_pwrSwitchCtrl 1
#define LSb16pwrOff_ctrl_pwrSwitchCtrl 1
#define bpwrOff_ctrl_pwrSwitchCtrl 2
#define MSK32pwrOff_ctrl_pwrSwitchCtrl 0x00000006
#define pwrOff_ctrl_pwrSwitchCtrl_PWROFF 0x0
#define pwrOff_ctrl_pwrSwitchCtrl_PWRON 0x3
#define BA_pwrOff_ctrl_pwrDomainRstN 0x0000
#define B16pwrOff_ctrl_pwrDomainRstN 0x0000
#define LSb32pwrOff_ctrl_pwrDomainRstN 3
#define LSb16pwrOff_ctrl_pwrDomainRstN 3
#define bpwrOff_ctrl_pwrDomainRstN 1
#define MSK32pwrOff_ctrl_pwrDomainRstN 0x00000008
#define pwrOff_ctrl_pwrDomainRstN_enable 0x0
#define pwrOff_ctrl_pwrDomainRstN_disable 0x1
///////////////////////////////////////////////////////////
#define RA_pwrOff_status 0x0004
#define BA_pwrOff_status_pwrStatus 0x0004
#define B16pwrOff_status_pwrStatus 0x0004
#define LSb32pwrOff_status_pwrStatus 0
#define LSb16pwrOff_status_pwrStatus 0
#define bpwrOff_status_pwrStatus 2
#define MSK32pwrOff_status_pwrStatus 0x00000003
///////////////////////////////////////////////////////////
typedef struct SIE_pwrOff {
///////////////////////////////////////////////////////////
#define GET32pwrOff_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0)
#define SET32pwrOff_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pwrOff_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0)
#define SET16pwrOff_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pwrOff_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1)
#define SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16pwrOff_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1)
#define SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32pwrOff_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3)
#define SET32pwrOff_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pwrOff_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3)
#define SET16pwrOff_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v)
#define w32pwrOff_ctrl {\
UNSG32 uctrl_iso_eN : 1;\
UNSG32 uctrl_pwrSwitchCtrl : 2;\
UNSG32 uctrl_pwrDomainRstN : 1;\
UNSG32 RSVDx0_b4 : 28;\
}
union { UNSG32 u32pwrOff_ctrl;
struct w32pwrOff_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32pwrOff_status_pwrStatus(r32) _BFGET_(r32, 1, 0)
#define SET32pwrOff_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16pwrOff_status_pwrStatus(r16) _BFGET_(r16, 1, 0)
#define SET16pwrOff_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v)
#define w32pwrOff_status {\
UNSG32 ustatus_pwrStatus : 2;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32pwrOff_status;
struct w32pwrOff_status;
};
///////////////////////////////////////////////////////////
} SIE_pwrOff;
typedef union T32pwrOff_ctrl
{ UNSG32 u32;
struct w32pwrOff_ctrl;
} T32pwrOff_ctrl;
typedef union T32pwrOff_status
{ UNSG32 u32;
struct w32pwrOff_status;
} T32pwrOff_status;
///////////////////////////////////////////////////////////
typedef union TpwrOff_ctrl
{ UNSG32 u32[1];
struct {
struct w32pwrOff_ctrl;
};
} TpwrOff_ctrl;
typedef union TpwrOff_status
{ UNSG32 u32[1];
struct {
struct w32pwrOff_status;
};
} TpwrOff_status;
///////////////////////////////////////////////////////////
SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pwrOff_reset(SIE_pwrOff *p);
SIGN32 pwrOff_cmp (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pwrOff_print(p, pfx,hLOG) pwrOff_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pwrOff
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pwrOn (4,4)
/// ###
/// * Register for the Power domain which is ON by default
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (RW-)
/// ###
/// * Power Domain Control Register
/// ###
/// %unsigned 1 iso_eN 0x1
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Isolation control bit. Active low
/// * 0 : Isolation is enabled
/// * 1 : Isolation is disabled (default)
/// ###
/// %unsigned 2 pwrSwitchCtrl 0x3
/// ###
/// * Power Switch control
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %unsigned 1 pwrDomainRstN 0x1
/// ###
/// * Power Domain Reset. Active low.
/// * 0 : Reset the power domain
/// * 1: De-assert the reset for the power domain
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 2 pwrStatus
/// ###
/// * Power domain Status output from the power domain module
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn
#define h_pwrOn (){}
#define RA_pwrOn_ctrl 0x0000
#define BA_pwrOn_ctrl_iso_eN 0x0000
#define B16pwrOn_ctrl_iso_eN 0x0000
#define LSb32pwrOn_ctrl_iso_eN 0
#define LSb16pwrOn_ctrl_iso_eN 0
#define bpwrOn_ctrl_iso_eN 1
#define MSK32pwrOn_ctrl_iso_eN 0x00000001
#define pwrOn_ctrl_iso_eN_enable 0x0
#define pwrOn_ctrl_iso_eN_disable 0x1
#define BA_pwrOn_ctrl_pwrSwitchCtrl 0x0000
#define B16pwrOn_ctrl_pwrSwitchCtrl 0x0000
#define LSb32pwrOn_ctrl_pwrSwitchCtrl 1
#define LSb16pwrOn_ctrl_pwrSwitchCtrl 1
#define bpwrOn_ctrl_pwrSwitchCtrl 2
#define MSK32pwrOn_ctrl_pwrSwitchCtrl 0x00000006
#define BA_pwrOn_ctrl_pwrDomainRstN 0x0000
#define B16pwrOn_ctrl_pwrDomainRstN 0x0000
#define LSb32pwrOn_ctrl_pwrDomainRstN 3
#define LSb16pwrOn_ctrl_pwrDomainRstN 3
#define bpwrOn_ctrl_pwrDomainRstN 1
#define MSK32pwrOn_ctrl_pwrDomainRstN 0x00000008
///////////////////////////////////////////////////////////
#define RA_pwrOn_status 0x0004
#define BA_pwrOn_status_pwrStatus 0x0004
#define B16pwrOn_status_pwrStatus 0x0004
#define LSb32pwrOn_status_pwrStatus 0
#define LSb16pwrOn_status_pwrStatus 0
#define bpwrOn_status_pwrStatus 2
#define MSK32pwrOn_status_pwrStatus 0x00000003
///////////////////////////////////////////////////////////
typedef struct SIE_pwrOn {
///////////////////////////////////////////////////////////
#define GET32pwrOn_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0)
#define SET32pwrOn_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pwrOn_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0)
#define SET16pwrOn_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pwrOn_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1)
#define SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16pwrOn_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1)
#define SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32pwrOn_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3)
#define SET32pwrOn_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pwrOn_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3)
#define SET16pwrOn_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v)
#define w32pwrOn_ctrl {\
UNSG32 uctrl_iso_eN : 1;\
UNSG32 uctrl_pwrSwitchCtrl : 2;\
UNSG32 uctrl_pwrDomainRstN : 1;\
UNSG32 RSVDx0_b4 : 28;\
}
union { UNSG32 u32pwrOn_ctrl;
struct w32pwrOn_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32pwrOn_status_pwrStatus(r32) _BFGET_(r32, 1, 0)
#define SET32pwrOn_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16pwrOn_status_pwrStatus(r16) _BFGET_(r16, 1, 0)
#define SET16pwrOn_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v)
#define w32pwrOn_status {\
UNSG32 ustatus_pwrStatus : 2;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32pwrOn_status;
struct w32pwrOn_status;
};
///////////////////////////////////////////////////////////
} SIE_pwrOn;
typedef union T32pwrOn_ctrl
{ UNSG32 u32;
struct w32pwrOn_ctrl;
} T32pwrOn_ctrl;
typedef union T32pwrOn_status
{ UNSG32 u32;
struct w32pwrOn_status;
} T32pwrOn_status;
///////////////////////////////////////////////////////////
typedef union TpwrOn_ctrl
{ UNSG32 u32[1];
struct {
struct w32pwrOn_ctrl;
};
} TpwrOn_ctrl;
typedef union TpwrOn_status
{ UNSG32 u32[1];
struct {
struct w32pwrOn_status;
};
} TpwrOn_status;
///////////////////////////////////////////////////////////
SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pwrOn_reset(SIE_pwrOn *p);
SIGN32 pwrOn_cmp (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pwrOn_print(p, pfx,hLOG) pwrOn_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pwrOn
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD1 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x0
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider (default) for Divide by 1
/// * 1: Use Divider
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x1
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// * Note: Not used for Divide by 1
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD1
#define h_clkD1 (){}
#define RA_clkD1_ctrl 0x0000
#define BA_clkD1_ctrl_ClkEn 0x0000
#define B16clkD1_ctrl_ClkEn 0x0000
#define LSb32clkD1_ctrl_ClkEn 0
#define LSb16clkD1_ctrl_ClkEn 0
#define bclkD1_ctrl_ClkEn 1
#define MSK32clkD1_ctrl_ClkEn 0x00000001
#define clkD1_ctrl_ClkEn_enable 0x1
#define clkD1_ctrl_ClkEn_disable 0x0
#define BA_clkD1_ctrl_ClkPllSel 0x0000
#define B16clkD1_ctrl_ClkPllSel 0x0000
#define LSb32clkD1_ctrl_ClkPllSel 1
#define LSb16clkD1_ctrl_ClkPllSel 1
#define bclkD1_ctrl_ClkPllSel 3
#define MSK32clkD1_ctrl_ClkPllSel 0x0000000E
#define clkD1_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD1_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD1_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD1_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD1_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD1_ctrl_ClkPllSwitch 0x0000
#define B16clkD1_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD1_ctrl_ClkPllSwitch 4
#define LSb16clkD1_ctrl_ClkPllSwitch 4
#define bclkD1_ctrl_ClkPllSwitch 1
#define MSK32clkD1_ctrl_ClkPllSwitch 0x00000010
#define clkD1_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD1_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD1_ctrl_ClkSwitch 0x0000
#define B16clkD1_ctrl_ClkSwitch 0x0000
#define LSb32clkD1_ctrl_ClkSwitch 5
#define LSb16clkD1_ctrl_ClkSwitch 5
#define bclkD1_ctrl_ClkSwitch 1
#define MSK32clkD1_ctrl_ClkSwitch 0x00000020
#define clkD1_ctrl_ClkSwitch_SrcClk 0x0
#define clkD1_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD1_ctrl_ClkD3Switch 0x0000
#define B16clkD1_ctrl_ClkD3Switch 0x0000
#define LSb32clkD1_ctrl_ClkD3Switch 6
#define LSb16clkD1_ctrl_ClkD3Switch 6
#define bclkD1_ctrl_ClkD3Switch 1
#define MSK32clkD1_ctrl_ClkD3Switch 0x00000040
#define clkD1_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD1_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD1_ctrl_ClkSel 0x0000
#define B16clkD1_ctrl_ClkSel 0x0000
#define LSb32clkD1_ctrl_ClkSel 7
#define LSb16clkD1_ctrl_ClkSel 7
#define bclkD1_ctrl_ClkSel 3
#define MSK32clkD1_ctrl_ClkSel 0x00000380
#define clkD1_ctrl_ClkSel_d2 0x1
#define clkD1_ctrl_ClkSel_d4 0x2
#define clkD1_ctrl_ClkSel_d6 0x3
#define clkD1_ctrl_ClkSel_d8 0x4
#define clkD1_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD1 {
///////////////////////////////////////////////////////////
#define GET32clkD1_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD1_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD1_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD1_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD1_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD1_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD1_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD1_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD1_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD1_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD1_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD1_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD1_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD1_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD1_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD1_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD1_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD1_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD1_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD1_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD1_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD1_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD1_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD1_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD1_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD1_ctrl;
struct w32clkD1_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD1;
typedef union T32clkD1_ctrl
{ UNSG32 u32;
struct w32clkD1_ctrl;
} T32clkD1_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD1_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD1_ctrl;
};
} TclkD1_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD1_drvrd(SIE_clkD1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD1_drvwr(SIE_clkD1 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD1_reset(SIE_clkD1 *p);
SIGN32 clkD1_cmp (SIE_clkD1 *p, SIE_clkD1 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD1_check(p,pie,pfx,hLOG) clkD1_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD1_print(p, pfx,hLOG) clkD1_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD1
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD2 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider
/// * 1: Use Divider (default)
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x1
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD2
#define h_clkD2 (){}
#define RA_clkD2_ctrl 0x0000
#define BA_clkD2_ctrl_ClkEn 0x0000
#define B16clkD2_ctrl_ClkEn 0x0000
#define LSb32clkD2_ctrl_ClkEn 0
#define LSb16clkD2_ctrl_ClkEn 0
#define bclkD2_ctrl_ClkEn 1
#define MSK32clkD2_ctrl_ClkEn 0x00000001
#define clkD2_ctrl_ClkEn_enable 0x1
#define clkD2_ctrl_ClkEn_disable 0x0
#define BA_clkD2_ctrl_ClkPllSel 0x0000
#define B16clkD2_ctrl_ClkPllSel 0x0000
#define LSb32clkD2_ctrl_ClkPllSel 1
#define LSb16clkD2_ctrl_ClkPllSel 1
#define bclkD2_ctrl_ClkPllSel 3
#define MSK32clkD2_ctrl_ClkPllSel 0x0000000E
#define clkD2_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD2_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD2_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD2_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD2_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD2_ctrl_ClkPllSwitch 0x0000
#define B16clkD2_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD2_ctrl_ClkPllSwitch 4
#define LSb16clkD2_ctrl_ClkPllSwitch 4
#define bclkD2_ctrl_ClkPllSwitch 1
#define MSK32clkD2_ctrl_ClkPllSwitch 0x00000010
#define clkD2_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD2_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD2_ctrl_ClkSwitch 0x0000
#define B16clkD2_ctrl_ClkSwitch 0x0000
#define LSb32clkD2_ctrl_ClkSwitch 5
#define LSb16clkD2_ctrl_ClkSwitch 5
#define bclkD2_ctrl_ClkSwitch 1
#define MSK32clkD2_ctrl_ClkSwitch 0x00000020
#define clkD2_ctrl_ClkSwitch_SrcClk 0x0
#define clkD2_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD2_ctrl_ClkD3Switch 0x0000
#define B16clkD2_ctrl_ClkD3Switch 0x0000
#define LSb32clkD2_ctrl_ClkD3Switch 6
#define LSb16clkD2_ctrl_ClkD3Switch 6
#define bclkD2_ctrl_ClkD3Switch 1
#define MSK32clkD2_ctrl_ClkD3Switch 0x00000040
#define clkD2_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD2_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD2_ctrl_ClkSel 0x0000
#define B16clkD2_ctrl_ClkSel 0x0000
#define LSb32clkD2_ctrl_ClkSel 7
#define LSb16clkD2_ctrl_ClkSel 7
#define bclkD2_ctrl_ClkSel 3
#define MSK32clkD2_ctrl_ClkSel 0x00000380
#define clkD2_ctrl_ClkSel_d2 0x1
#define clkD2_ctrl_ClkSel_d4 0x2
#define clkD2_ctrl_ClkSel_d6 0x3
#define clkD2_ctrl_ClkSel_d8 0x4
#define clkD2_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD2 {
///////////////////////////////////////////////////////////
#define GET32clkD2_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD2_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD2_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD2_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD2_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD2_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD2_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD2_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD2_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD2_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD2_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD2_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD2_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD2_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD2_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD2_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD2_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD2_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD2_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD2_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD2_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD2_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD2_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD2_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD2_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD2_ctrl;
struct w32clkD2_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD2;
typedef union T32clkD2_ctrl
{ UNSG32 u32;
struct w32clkD2_ctrl;
} T32clkD2_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD2_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD2_ctrl;
};
} TclkD2_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD2_drvrd(SIE_clkD2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD2_drvwr(SIE_clkD2 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD2_reset(SIE_clkD2 *p);
SIGN32 clkD2_cmp (SIE_clkD2 *p, SIE_clkD2 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD2_check(p,pie,pfx,hLOG) clkD2_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD2_print(p, pfx,hLOG) clkD2_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD2
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD4 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider
/// * 1: Use Divider (default)
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x2
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD4
#define h_clkD4 (){}
#define RA_clkD4_ctrl 0x0000
#define BA_clkD4_ctrl_ClkEn 0x0000
#define B16clkD4_ctrl_ClkEn 0x0000
#define LSb32clkD4_ctrl_ClkEn 0
#define LSb16clkD4_ctrl_ClkEn 0
#define bclkD4_ctrl_ClkEn 1
#define MSK32clkD4_ctrl_ClkEn 0x00000001
#define clkD4_ctrl_ClkEn_enable 0x1
#define clkD4_ctrl_ClkEn_disable 0x0
#define BA_clkD4_ctrl_ClkPllSel 0x0000
#define B16clkD4_ctrl_ClkPllSel 0x0000
#define LSb32clkD4_ctrl_ClkPllSel 1
#define LSb16clkD4_ctrl_ClkPllSel 1
#define bclkD4_ctrl_ClkPllSel 3
#define MSK32clkD4_ctrl_ClkPllSel 0x0000000E
#define clkD4_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD4_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD4_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD4_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD4_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD4_ctrl_ClkPllSwitch 0x0000
#define B16clkD4_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD4_ctrl_ClkPllSwitch 4
#define LSb16clkD4_ctrl_ClkPllSwitch 4
#define bclkD4_ctrl_ClkPllSwitch 1
#define MSK32clkD4_ctrl_ClkPllSwitch 0x00000010
#define clkD4_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD4_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD4_ctrl_ClkSwitch 0x0000
#define B16clkD4_ctrl_ClkSwitch 0x0000
#define LSb32clkD4_ctrl_ClkSwitch 5
#define LSb16clkD4_ctrl_ClkSwitch 5
#define bclkD4_ctrl_ClkSwitch 1
#define MSK32clkD4_ctrl_ClkSwitch 0x00000020
#define clkD4_ctrl_ClkSwitch_SrcClk 0x0
#define clkD4_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD4_ctrl_ClkD3Switch 0x0000
#define B16clkD4_ctrl_ClkD3Switch 0x0000
#define LSb32clkD4_ctrl_ClkD3Switch 6
#define LSb16clkD4_ctrl_ClkD3Switch 6
#define bclkD4_ctrl_ClkD3Switch 1
#define MSK32clkD4_ctrl_ClkD3Switch 0x00000040
#define clkD4_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD4_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD4_ctrl_ClkSel 0x0000
#define B16clkD4_ctrl_ClkSel 0x0000
#define LSb32clkD4_ctrl_ClkSel 7
#define LSb16clkD4_ctrl_ClkSel 7
#define bclkD4_ctrl_ClkSel 3
#define MSK32clkD4_ctrl_ClkSel 0x00000380
#define clkD4_ctrl_ClkSel_d2 0x1
#define clkD4_ctrl_ClkSel_d4 0x2
#define clkD4_ctrl_ClkSel_d6 0x3
#define clkD4_ctrl_ClkSel_d8 0x4
#define clkD4_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD4 {
///////////////////////////////////////////////////////////
#define GET32clkD4_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD4_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD4_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD4_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD4_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD4_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD4_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD4_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD4_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD4_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD4_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD4_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD4_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD4_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD4_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD4_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD4_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD4_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD4_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD4_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD4_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD4_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD4_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD4_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD4_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD4_ctrl;
struct w32clkD4_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD4;
typedef union T32clkD4_ctrl
{ UNSG32 u32;
struct w32clkD4_ctrl;
} T32clkD4_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD4_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD4_ctrl;
};
} TclkD4_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD4_drvrd(SIE_clkD4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD4_drvwr(SIE_clkD4 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD4_reset(SIE_clkD4 *p);
SIGN32 clkD4_cmp (SIE_clkD4 *p, SIE_clkD4 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD4_check(p,pie,pfx,hLOG) clkD4_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD4_print(p, pfx,hLOG) clkD4_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD4
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD6 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider
/// * 1: Use Divider (default)
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x3
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD6
#define h_clkD6 (){}
#define RA_clkD6_ctrl 0x0000
#define BA_clkD6_ctrl_ClkEn 0x0000
#define B16clkD6_ctrl_ClkEn 0x0000
#define LSb32clkD6_ctrl_ClkEn 0
#define LSb16clkD6_ctrl_ClkEn 0
#define bclkD6_ctrl_ClkEn 1
#define MSK32clkD6_ctrl_ClkEn 0x00000001
#define clkD6_ctrl_ClkEn_enable 0x1
#define clkD6_ctrl_ClkEn_disable 0x0
#define BA_clkD6_ctrl_ClkPllSel 0x0000
#define B16clkD6_ctrl_ClkPllSel 0x0000
#define LSb32clkD6_ctrl_ClkPllSel 1
#define LSb16clkD6_ctrl_ClkPllSel 1
#define bclkD6_ctrl_ClkPllSel 3
#define MSK32clkD6_ctrl_ClkPllSel 0x0000000E
#define clkD6_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD6_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD6_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD6_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD6_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD6_ctrl_ClkPllSwitch 0x0000
#define B16clkD6_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD6_ctrl_ClkPllSwitch 4
#define LSb16clkD6_ctrl_ClkPllSwitch 4
#define bclkD6_ctrl_ClkPllSwitch 1
#define MSK32clkD6_ctrl_ClkPllSwitch 0x00000010
#define clkD6_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD6_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD6_ctrl_ClkSwitch 0x0000
#define B16clkD6_ctrl_ClkSwitch 0x0000
#define LSb32clkD6_ctrl_ClkSwitch 5
#define LSb16clkD6_ctrl_ClkSwitch 5
#define bclkD6_ctrl_ClkSwitch 1
#define MSK32clkD6_ctrl_ClkSwitch 0x00000020
#define clkD6_ctrl_ClkSwitch_SrcClk 0x0
#define clkD6_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD6_ctrl_ClkD3Switch 0x0000
#define B16clkD6_ctrl_ClkD3Switch 0x0000
#define LSb32clkD6_ctrl_ClkD3Switch 6
#define LSb16clkD6_ctrl_ClkD3Switch 6
#define bclkD6_ctrl_ClkD3Switch 1
#define MSK32clkD6_ctrl_ClkD3Switch 0x00000040
#define clkD6_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD6_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD6_ctrl_ClkSel 0x0000
#define B16clkD6_ctrl_ClkSel 0x0000
#define LSb32clkD6_ctrl_ClkSel 7
#define LSb16clkD6_ctrl_ClkSel 7
#define bclkD6_ctrl_ClkSel 3
#define MSK32clkD6_ctrl_ClkSel 0x00000380
#define clkD6_ctrl_ClkSel_d2 0x1
#define clkD6_ctrl_ClkSel_d4 0x2
#define clkD6_ctrl_ClkSel_d6 0x3
#define clkD6_ctrl_ClkSel_d8 0x4
#define clkD6_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD6 {
///////////////////////////////////////////////////////////
#define GET32clkD6_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD6_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD6_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD6_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD6_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD6_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD6_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD6_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD6_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD6_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD6_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD6_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD6_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD6_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD6_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD6_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD6_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD6_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD6_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD6_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD6_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD6_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD6_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD6_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD6_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD6_ctrl;
struct w32clkD6_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD6;
typedef union T32clkD6_ctrl
{ UNSG32 u32;
struct w32clkD6_ctrl;
} T32clkD6_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD6_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD6_ctrl;
};
} TclkD6_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD6_drvrd(SIE_clkD6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD6_drvwr(SIE_clkD6 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD6_reset(SIE_clkD6 *p);
SIGN32 clkD6_cmp (SIE_clkD6 *p, SIE_clkD6 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD6_check(p,pie,pfx,hLOG) clkD6_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD6_print(p, pfx,hLOG) clkD6_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD6
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD8 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider
/// * 1: Use Divider (default)
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x4
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD8
#define h_clkD8 (){}
#define RA_clkD8_ctrl 0x0000
#define BA_clkD8_ctrl_ClkEn 0x0000
#define B16clkD8_ctrl_ClkEn 0x0000
#define LSb32clkD8_ctrl_ClkEn 0
#define LSb16clkD8_ctrl_ClkEn 0
#define bclkD8_ctrl_ClkEn 1
#define MSK32clkD8_ctrl_ClkEn 0x00000001
#define clkD8_ctrl_ClkEn_enable 0x1
#define clkD8_ctrl_ClkEn_disable 0x0
#define BA_clkD8_ctrl_ClkPllSel 0x0000
#define B16clkD8_ctrl_ClkPllSel 0x0000
#define LSb32clkD8_ctrl_ClkPllSel 1
#define LSb16clkD8_ctrl_ClkPllSel 1
#define bclkD8_ctrl_ClkPllSel 3
#define MSK32clkD8_ctrl_ClkPllSel 0x0000000E
#define clkD8_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD8_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD8_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD8_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD8_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD8_ctrl_ClkPllSwitch 0x0000
#define B16clkD8_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD8_ctrl_ClkPllSwitch 4
#define LSb16clkD8_ctrl_ClkPllSwitch 4
#define bclkD8_ctrl_ClkPllSwitch 1
#define MSK32clkD8_ctrl_ClkPllSwitch 0x00000010
#define clkD8_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD8_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD8_ctrl_ClkSwitch 0x0000
#define B16clkD8_ctrl_ClkSwitch 0x0000
#define LSb32clkD8_ctrl_ClkSwitch 5
#define LSb16clkD8_ctrl_ClkSwitch 5
#define bclkD8_ctrl_ClkSwitch 1
#define MSK32clkD8_ctrl_ClkSwitch 0x00000020
#define clkD8_ctrl_ClkSwitch_SrcClk 0x0
#define clkD8_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD8_ctrl_ClkD3Switch 0x0000
#define B16clkD8_ctrl_ClkD3Switch 0x0000
#define LSb32clkD8_ctrl_ClkD3Switch 6
#define LSb16clkD8_ctrl_ClkD3Switch 6
#define bclkD8_ctrl_ClkD3Switch 1
#define MSK32clkD8_ctrl_ClkD3Switch 0x00000040
#define clkD8_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD8_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD8_ctrl_ClkSel 0x0000
#define B16clkD8_ctrl_ClkSel 0x0000
#define LSb32clkD8_ctrl_ClkSel 7
#define LSb16clkD8_ctrl_ClkSel 7
#define bclkD8_ctrl_ClkSel 3
#define MSK32clkD8_ctrl_ClkSel 0x00000380
#define clkD8_ctrl_ClkSel_d2 0x1
#define clkD8_ctrl_ClkSel_d4 0x2
#define clkD8_ctrl_ClkSel_d6 0x3
#define clkD8_ctrl_ClkSel_d8 0x4
#define clkD8_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD8 {
///////////////////////////////////////////////////////////
#define GET32clkD8_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD8_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD8_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD8_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD8_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD8_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD8_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD8_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD8_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD8_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD8_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD8_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD8_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD8_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD8_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD8_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD8_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD8_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD8_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD8_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD8_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD8_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD8_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD8_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD8_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD8_ctrl;
struct w32clkD8_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD8;
typedef union T32clkD8_ctrl
{ UNSG32 u32;
struct w32clkD8_ctrl;
} T32clkD8_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD8_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD8_ctrl;
};
} TclkD8_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD8_drvrd(SIE_clkD8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD8_drvwr(SIE_clkD8 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD8_reset(SIE_clkD8 *p);
SIGN32 clkD8_cmp (SIE_clkD8 *p, SIE_clkD8 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD8_check(p,pie,pfx,hLOG) clkD8_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD8_print(p, pfx,hLOG) clkD8_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD8
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkD12 (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * Control register
/// ###
/// %unsigned 1 ClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Clock enable register
/// * 0: Disable
/// * 1: Enable (default)
/// ###
/// %unsigned 3 ClkPllSel 0x4
/// : AVPllB4 0x0
/// : AVPllB5 0x1
/// : AVPllB6 0x2
/// : AVPllB7 0x3
/// : SYSPLL 0x4
/// ###
/// * Clock source selection
/// * 0: AVPLL B[4]
/// * 1: AVPLL B[5]
/// * 2: AVPLL B[6]
/// * 3: AVPLL B[7]
/// * 4: SYSPLL (default)
/// * 5-7: Reserved
/// ###
/// %unsigned 1 ClkPllSwitch 0x0
/// : SYSPLL 0x0
/// : AVPLL 0x1
/// ###
/// * Switch to select between SYSPLL or AVPLL as a clock source
/// * 0: SYSPLL (default)
/// * 1: AVPLL
/// ###
/// %unsigned 1 ClkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Clock divider switch select
/// * 0: No divider
/// * 1: Use Divider (default)
/// ###
/// %unsigned 1 ClkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Divide by 3 clock switch
/// * 0: No Divide by 3 (default)
/// * 1: Use Divide by 3
/// ###
/// %unsigned 3 ClkSel 0x5
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * Clock divider Selection
/// * 0: Reserved
/// * 1: Divide by 2 ( default)
/// * 2: Divide by 4
/// * 3: Divide by 6
/// * 4: Divide by 8
/// * 5: Divide by 12
/// * 6-7: Reserved
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkD12
#define h_clkD12 (){}
#define RA_clkD12_ctrl 0x0000
#define BA_clkD12_ctrl_ClkEn 0x0000
#define B16clkD12_ctrl_ClkEn 0x0000
#define LSb32clkD12_ctrl_ClkEn 0
#define LSb16clkD12_ctrl_ClkEn 0
#define bclkD12_ctrl_ClkEn 1
#define MSK32clkD12_ctrl_ClkEn 0x00000001
#define clkD12_ctrl_ClkEn_enable 0x1
#define clkD12_ctrl_ClkEn_disable 0x0
#define BA_clkD12_ctrl_ClkPllSel 0x0000
#define B16clkD12_ctrl_ClkPllSel 0x0000
#define LSb32clkD12_ctrl_ClkPllSel 1
#define LSb16clkD12_ctrl_ClkPllSel 1
#define bclkD12_ctrl_ClkPllSel 3
#define MSK32clkD12_ctrl_ClkPllSel 0x0000000E
#define clkD12_ctrl_ClkPllSel_AVPllB4 0x0
#define clkD12_ctrl_ClkPllSel_AVPllB5 0x1
#define clkD12_ctrl_ClkPllSel_AVPllB6 0x2
#define clkD12_ctrl_ClkPllSel_AVPllB7 0x3
#define clkD12_ctrl_ClkPllSel_SYSPLL 0x4
#define BA_clkD12_ctrl_ClkPllSwitch 0x0000
#define B16clkD12_ctrl_ClkPllSwitch 0x0000
#define LSb32clkD12_ctrl_ClkPllSwitch 4
#define LSb16clkD12_ctrl_ClkPllSwitch 4
#define bclkD12_ctrl_ClkPllSwitch 1
#define MSK32clkD12_ctrl_ClkPllSwitch 0x00000010
#define clkD12_ctrl_ClkPllSwitch_SYSPLL 0x0
#define clkD12_ctrl_ClkPllSwitch_AVPLL 0x1
#define BA_clkD12_ctrl_ClkSwitch 0x0000
#define B16clkD12_ctrl_ClkSwitch 0x0000
#define LSb32clkD12_ctrl_ClkSwitch 5
#define LSb16clkD12_ctrl_ClkSwitch 5
#define bclkD12_ctrl_ClkSwitch 1
#define MSK32clkD12_ctrl_ClkSwitch 0x00000020
#define clkD12_ctrl_ClkSwitch_SrcClk 0x0
#define clkD12_ctrl_ClkSwitch_DivClk 0x1
#define BA_clkD12_ctrl_ClkD3Switch 0x0000
#define B16clkD12_ctrl_ClkD3Switch 0x0000
#define LSb32clkD12_ctrl_ClkD3Switch 6
#define LSb16clkD12_ctrl_ClkD3Switch 6
#define bclkD12_ctrl_ClkD3Switch 1
#define MSK32clkD12_ctrl_ClkD3Switch 0x00000040
#define clkD12_ctrl_ClkD3Switch_NonDiv3Clk 0x0
#define clkD12_ctrl_ClkD3Switch_Div3Clk 0x1
#define BA_clkD12_ctrl_ClkSel 0x0000
#define B16clkD12_ctrl_ClkSel 0x0000
#define LSb32clkD12_ctrl_ClkSel 7
#define LSb16clkD12_ctrl_ClkSel 7
#define bclkD12_ctrl_ClkSel 3
#define MSK32clkD12_ctrl_ClkSel 0x00000380
#define clkD12_ctrl_ClkSel_d2 0x1
#define clkD12_ctrl_ClkSel_d4 0x2
#define clkD12_ctrl_ClkSel_d6 0x3
#define clkD12_ctrl_ClkSel_d8 0x4
#define clkD12_ctrl_ClkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_clkD12 {
///////////////////////////////////////////////////////////
#define GET32clkD12_ctrl_ClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32clkD12_ctrl_ClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkD12_ctrl_ClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16clkD12_ctrl_ClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkD12_ctrl_ClkPllSel(r32) _BFGET_(r32, 3, 1)
#define SET32clkD12_ctrl_ClkPllSel(r32,v) _BFSET_(r32, 3, 1,v)
#define GET16clkD12_ctrl_ClkPllSel(r16) _BFGET_(r16, 3, 1)
#define SET16clkD12_ctrl_ClkPllSel(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32clkD12_ctrl_ClkPllSwitch(r32) _BFGET_(r32, 4, 4)
#define SET32clkD12_ctrl_ClkPllSwitch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16clkD12_ctrl_ClkPllSwitch(r16) _BFGET_(r16, 4, 4)
#define SET16clkD12_ctrl_ClkPllSwitch(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32clkD12_ctrl_ClkSwitch(r32) _BFGET_(r32, 5, 5)
#define SET32clkD12_ctrl_ClkSwitch(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16clkD12_ctrl_ClkSwitch(r16) _BFGET_(r16, 5, 5)
#define SET16clkD12_ctrl_ClkSwitch(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32clkD12_ctrl_ClkD3Switch(r32) _BFGET_(r32, 6, 6)
#define SET32clkD12_ctrl_ClkD3Switch(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16clkD12_ctrl_ClkD3Switch(r16) _BFGET_(r16, 6, 6)
#define SET16clkD12_ctrl_ClkD3Switch(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32clkD12_ctrl_ClkSel(r32) _BFGET_(r32, 9, 7)
#define SET32clkD12_ctrl_ClkSel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16clkD12_ctrl_ClkSel(r16) _BFGET_(r16, 9, 7)
#define SET16clkD12_ctrl_ClkSel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32clkD12_ctrl {\
UNSG32 uctrl_ClkEn : 1;\
UNSG32 uctrl_ClkPllSel : 3;\
UNSG32 uctrl_ClkPllSwitch : 1;\
UNSG32 uctrl_ClkSwitch : 1;\
UNSG32 uctrl_ClkD3Switch : 1;\
UNSG32 uctrl_ClkSel : 3;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32clkD12_ctrl;
struct w32clkD12_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_clkD12;
typedef union T32clkD12_ctrl
{ UNSG32 u32;
struct w32clkD12_ctrl;
} T32clkD12_ctrl;
///////////////////////////////////////////////////////////
typedef union TclkD12_ctrl
{ UNSG32 u32[1];
struct {
struct w32clkD12_ctrl;
};
} TclkD12_ctrl;
///////////////////////////////////////////////////////////
SIGN32 clkD12_drvrd(SIE_clkD12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkD12_drvwr(SIE_clkD12 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkD12_reset(SIE_clkD12 *p);
SIGN32 clkD12_cmp (SIE_clkD12 *p, SIE_clkD12 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkD12_check(p,pie,pfx,hLOG) clkD12_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkD12_print(p, pfx,hLOG) clkD12_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkD12
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE efuse (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (RW)
/// ###
/// * EFUSE Control register
/// ###
/// %unsigned 1 PROG_SEQ_CODE 0x0
/// ###
/// * Program code
/// ###
/// %unsigned 1 PROG_SEQ_CODE_CLK 0x0
/// ###
/// * Clock needed to latch in the 10/60bit serial code on the rising edge prior to programming.
/// ###
/// %unsigned 1 SCLK 0x0
/// ###
/// * Serial Clock. High period for program. Falling edge clocks out data to Dout
/// ###
/// %unsigned 1 PRDT 0x1
/// ###
/// * Parallel read trigger. For alternative read protocol. Performs parallel read at rising edge. This parallel read operation is required prior to programming .
/// ###
/// %unsigned 1 POR_B 0x1
/// ###
/// * Power-On-Reset. Active LOW.
/// ###
/// %unsigned 1 CSB 0x1
/// ###
/// * Macro select
/// ###
/// %unsigned 1 PGM 0x0
/// ###
/// * Programming mode control and selective bit program control.
/// ###
/// %unsigned 1 WPROT 0x1
/// ###
/// * Programming protection signal.
/// * Must remain level in program/read state. For id_efuse_msb_sfb, if the number of match code bits is 60 bits, WPROT LOW enables the loading of PROG_SEQ_CODE into the match code register, WPROT HIGH resets the match code register. For id_efuse_lsb, if the number of match code bits is 60 bits, WPROT LOW enables the loading of PROG_SEQ_CODE into the match code register, WPROT HIGH keeps the old value of the match code register.
/// ###
/// %unsigned 4 TEST 0xA
/// ###
/// * These control internal circuit settings for optimum VDD min/ VHV min performance. They are similar to RTC settings in SRAM. TEST[3:0] should be registered and modifiable by firmware or software.
/// * Default settings: GSVT 0101, GHVT 1101, LPSVT1010, LPHVT 1010, LPMSVT 1010, LPMHVT 1010.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00004 status_match (R-)
/// ###
/// * EFUSE status0 register
/// ###
/// %unsigned 1 MATCH_VALUE
/// ###
/// * MATCH signal is available when the number of match code bits is 60 bits. MATCH=HIGH indicates that the input code is matched. MATCH=LOW indicates that the input code is not matched.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00008 status_qout (R-)
/// ###
/// * EFUSE status1 register: 257-bits Parallel Data out register
/// ###
/// %unsigned 32 QOUT_31_0
/// # 0x0000C status_qout1
/// %unsigned 32 QOUT_63_32
/// # 0x00010 status_qout2
/// %unsigned 32 QOUT_95_64
/// # 0x00014 status_qout3
/// %unsigned 32 QOUT_127_96
/// # 0x00018 status_qout4
/// %unsigned 32 QOUT_159_128
/// # 0x0001C status_qout5
/// %unsigned 32 QOUT_191_160
/// # 0x00020 status_qout6
/// %unsigned 32 QOUT_223_192
/// # 0x00024 status_qout7
/// %unsigned 32 QOUT_255_224
/// # 0x00028 status_qout8
/// %unsigned 17 QOUT_272_256
/// %% 15 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 44B, bits: 286b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_efuse
#define h_efuse (){}
#define RA_efuse_ctrl 0x0000
#define BA_efuse_ctrl_PROG_SEQ_CODE 0x0000
#define B16efuse_ctrl_PROG_SEQ_CODE 0x0000
#define LSb32efuse_ctrl_PROG_SEQ_CODE 0
#define LSb16efuse_ctrl_PROG_SEQ_CODE 0
#define befuse_ctrl_PROG_SEQ_CODE 1
#define MSK32efuse_ctrl_PROG_SEQ_CODE 0x00000001
#define BA_efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000
#define B16efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000
#define LSb32efuse_ctrl_PROG_SEQ_CODE_CLK 1
#define LSb16efuse_ctrl_PROG_SEQ_CODE_CLK 1
#define befuse_ctrl_PROG_SEQ_CODE_CLK 1
#define MSK32efuse_ctrl_PROG_SEQ_CODE_CLK 0x00000002
#define BA_efuse_ctrl_SCLK 0x0000
#define B16efuse_ctrl_SCLK 0x0000
#define LSb32efuse_ctrl_SCLK 2
#define LSb16efuse_ctrl_SCLK 2
#define befuse_ctrl_SCLK 1
#define MSK32efuse_ctrl_SCLK 0x00000004
#define BA_efuse_ctrl_PRDT 0x0000
#define B16efuse_ctrl_PRDT 0x0000
#define LSb32efuse_ctrl_PRDT 3
#define LSb16efuse_ctrl_PRDT 3
#define befuse_ctrl_PRDT 1
#define MSK32efuse_ctrl_PRDT 0x00000008
#define BA_efuse_ctrl_POR_B 0x0000
#define B16efuse_ctrl_POR_B 0x0000
#define LSb32efuse_ctrl_POR_B 4
#define LSb16efuse_ctrl_POR_B 4
#define befuse_ctrl_POR_B 1
#define MSK32efuse_ctrl_POR_B 0x00000010
#define BA_efuse_ctrl_CSB 0x0000
#define B16efuse_ctrl_CSB 0x0000
#define LSb32efuse_ctrl_CSB 5
#define LSb16efuse_ctrl_CSB 5
#define befuse_ctrl_CSB 1
#define MSK32efuse_ctrl_CSB 0x00000020
#define BA_efuse_ctrl_PGM 0x0000
#define B16efuse_ctrl_PGM 0x0000
#define LSb32efuse_ctrl_PGM 6
#define LSb16efuse_ctrl_PGM 6
#define befuse_ctrl_PGM 1
#define MSK32efuse_ctrl_PGM 0x00000040
#define BA_efuse_ctrl_WPROT 0x0000
#define B16efuse_ctrl_WPROT 0x0000
#define LSb32efuse_ctrl_WPROT 7
#define LSb16efuse_ctrl_WPROT 7
#define befuse_ctrl_WPROT 1
#define MSK32efuse_ctrl_WPROT 0x00000080
#define BA_efuse_ctrl_TEST 0x0001
#define B16efuse_ctrl_TEST 0x0000
#define LSb32efuse_ctrl_TEST 8
#define LSb16efuse_ctrl_TEST 8
#define befuse_ctrl_TEST 4
#define MSK32efuse_ctrl_TEST 0x00000F00
///////////////////////////////////////////////////////////
#define RA_efuse_status_match 0x0004
#define BA_efuse_status_match_MATCH_VALUE 0x0004
#define B16efuse_status_match_MATCH_VALUE 0x0004
#define LSb32efuse_status_match_MATCH_VALUE 0
#define LSb16efuse_status_match_MATCH_VALUE 0
#define befuse_status_match_MATCH_VALUE 1
#define MSK32efuse_status_match_MATCH_VALUE 0x00000001
///////////////////////////////////////////////////////////
#define RA_efuse_status_qout 0x0008
#define BA_efuse_status_qout_QOUT_31_0 0x0008
#define B16efuse_status_qout_QOUT_31_0 0x0008
#define LSb32efuse_status_qout_QOUT_31_0 0
#define LSb16efuse_status_qout_QOUT_31_0 0
#define befuse_status_qout_QOUT_31_0 32
#define MSK32efuse_status_qout_QOUT_31_0 0xFFFFFFFF
#define RA_efuse_status_qout1 0x000C
#define BA_efuse_status_qout_QOUT_63_32 0x000C
#define B16efuse_status_qout_QOUT_63_32 0x000C
#define LSb32efuse_status_qout_QOUT_63_32 0
#define LSb16efuse_status_qout_QOUT_63_32 0
#define befuse_status_qout_QOUT_63_32 32
#define MSK32efuse_status_qout_QOUT_63_32 0xFFFFFFFF
#define RA_efuse_status_qout2 0x0010
#define BA_efuse_status_qout_QOUT_95_64 0x0010
#define B16efuse_status_qout_QOUT_95_64 0x0010
#define LSb32efuse_status_qout_QOUT_95_64 0
#define LSb16efuse_status_qout_QOUT_95_64 0
#define befuse_status_qout_QOUT_95_64 32
#define MSK32efuse_status_qout_QOUT_95_64 0xFFFFFFFF
#define RA_efuse_status_qout3 0x0014
#define BA_efuse_status_qout_QOUT_127_96 0x0014
#define B16efuse_status_qout_QOUT_127_96 0x0014
#define LSb32efuse_status_qout_QOUT_127_96 0
#define LSb16efuse_status_qout_QOUT_127_96 0
#define befuse_status_qout_QOUT_127_96 32
#define MSK32efuse_status_qout_QOUT_127_96 0xFFFFFFFF
#define RA_efuse_status_qout4 0x0018
#define BA_efuse_status_qout_QOUT_159_128 0x0018
#define B16efuse_status_qout_QOUT_159_128 0x0018
#define LSb32efuse_status_qout_QOUT_159_128 0
#define LSb16efuse_status_qout_QOUT_159_128 0
#define befuse_status_qout_QOUT_159_128 32
#define MSK32efuse_status_qout_QOUT_159_128 0xFFFFFFFF
#define RA_efuse_status_qout5 0x001C
#define BA_efuse_status_qout_QOUT_191_160 0x001C
#define B16efuse_status_qout_QOUT_191_160 0x001C
#define LSb32efuse_status_qout_QOUT_191_160 0
#define LSb16efuse_status_qout_QOUT_191_160 0
#define befuse_status_qout_QOUT_191_160 32
#define MSK32efuse_status_qout_QOUT_191_160 0xFFFFFFFF
#define RA_efuse_status_qout6 0x0020
#define BA_efuse_status_qout_QOUT_223_192 0x0020
#define B16efuse_status_qout_QOUT_223_192 0x0020
#define LSb32efuse_status_qout_QOUT_223_192 0
#define LSb16efuse_status_qout_QOUT_223_192 0
#define befuse_status_qout_QOUT_223_192 32
#define MSK32efuse_status_qout_QOUT_223_192 0xFFFFFFFF
#define RA_efuse_status_qout7 0x0024
#define BA_efuse_status_qout_QOUT_255_224 0x0024
#define B16efuse_status_qout_QOUT_255_224 0x0024
#define LSb32efuse_status_qout_QOUT_255_224 0
#define LSb16efuse_status_qout_QOUT_255_224 0
#define befuse_status_qout_QOUT_255_224 32
#define MSK32efuse_status_qout_QOUT_255_224 0xFFFFFFFF
#define RA_efuse_status_qout8 0x0028
#define BA_efuse_status_qout_QOUT_272_256 0x0028
#define B16efuse_status_qout_QOUT_272_256 0x0028
#define LSb32efuse_status_qout_QOUT_272_256 0
#define LSb16efuse_status_qout_QOUT_272_256 0
#define befuse_status_qout_QOUT_272_256 17
#define MSK32efuse_status_qout_QOUT_272_256 0x0001FFFF
///////////////////////////////////////////////////////////
typedef struct SIE_efuse {
///////////////////////////////////////////////////////////
#define GET32efuse_ctrl_PROG_SEQ_CODE(r32) _BFGET_(r32, 0, 0)
#define SET32efuse_ctrl_PROG_SEQ_CODE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16efuse_ctrl_PROG_SEQ_CODE(r16) _BFGET_(r16, 0, 0)
#define SET16efuse_ctrl_PROG_SEQ_CODE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32efuse_ctrl_PROG_SEQ_CODE_CLK(r32) _BFGET_(r32, 1, 1)
#define SET32efuse_ctrl_PROG_SEQ_CODE_CLK(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16efuse_ctrl_PROG_SEQ_CODE_CLK(r16) _BFGET_(r16, 1, 1)
#define SET16efuse_ctrl_PROG_SEQ_CODE_CLK(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32efuse_ctrl_SCLK(r32) _BFGET_(r32, 2, 2)
#define SET32efuse_ctrl_SCLK(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16efuse_ctrl_SCLK(r16) _BFGET_(r16, 2, 2)
#define SET16efuse_ctrl_SCLK(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32efuse_ctrl_PRDT(r32) _BFGET_(r32, 3, 3)
#define SET32efuse_ctrl_PRDT(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16efuse_ctrl_PRDT(r16) _BFGET_(r16, 3, 3)
#define SET16efuse_ctrl_PRDT(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32efuse_ctrl_POR_B(r32) _BFGET_(r32, 4, 4)
#define SET32efuse_ctrl_POR_B(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16efuse_ctrl_POR_B(r16) _BFGET_(r16, 4, 4)
#define SET16efuse_ctrl_POR_B(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32efuse_ctrl_CSB(r32) _BFGET_(r32, 5, 5)
#define SET32efuse_ctrl_CSB(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16efuse_ctrl_CSB(r16) _BFGET_(r16, 5, 5)
#define SET16efuse_ctrl_CSB(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32efuse_ctrl_PGM(r32) _BFGET_(r32, 6, 6)
#define SET32efuse_ctrl_PGM(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16efuse_ctrl_PGM(r16) _BFGET_(r16, 6, 6)
#define SET16efuse_ctrl_PGM(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32efuse_ctrl_WPROT(r32) _BFGET_(r32, 7, 7)
#define SET32efuse_ctrl_WPROT(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16efuse_ctrl_WPROT(r16) _BFGET_(r16, 7, 7)
#define SET16efuse_ctrl_WPROT(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32efuse_ctrl_TEST(r32) _BFGET_(r32,11, 8)
#define SET32efuse_ctrl_TEST(r32,v) _BFSET_(r32,11, 8,v)
#define GET16efuse_ctrl_TEST(r16) _BFGET_(r16,11, 8)
#define SET16efuse_ctrl_TEST(r16,v) _BFSET_(r16,11, 8,v)
#define w32efuse_ctrl {\
UNSG32 uctrl_PROG_SEQ_CODE : 1;\
UNSG32 uctrl_PROG_SEQ_CODE_CLK : 1;\
UNSG32 uctrl_SCLK : 1;\
UNSG32 uctrl_PRDT : 1;\
UNSG32 uctrl_POR_B : 1;\
UNSG32 uctrl_CSB : 1;\
UNSG32 uctrl_PGM : 1;\
UNSG32 uctrl_WPROT : 1;\
UNSG32 uctrl_TEST : 4;\
UNSG32 RSVDx0_b12 : 20;\
}
union { UNSG32 u32efuse_ctrl;
struct w32efuse_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32efuse_status_match_MATCH_VALUE(r32) _BFGET_(r32, 0, 0)
#define SET32efuse_status_match_MATCH_VALUE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16efuse_status_match_MATCH_VALUE(r16) _BFGET_(r16, 0, 0)
#define SET16efuse_status_match_MATCH_VALUE(r16,v) _BFSET_(r16, 0, 0,v)
#define w32efuse_status_match {\
UNSG32 ustatus_match_MATCH_VALUE : 1;\
UNSG32 RSVDx4_b1 : 31;\
}
union { UNSG32 u32efuse_status_match;
struct w32efuse_status_match;
};
///////////////////////////////////////////////////////////
#define GET32efuse_status_qout_QOUT_31_0(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_31_0(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout {\
UNSG32 ustatus_qout_QOUT_31_0 : 32;\
}
union { UNSG32 u32efuse_status_qout;
struct w32efuse_status_qout;
};
#define GET32efuse_status_qout_QOUT_63_32(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_63_32(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout1 {\
UNSG32 ustatus_qout_QOUT_63_32 : 32;\
}
union { UNSG32 u32efuse_status_qout1;
struct w32efuse_status_qout1;
};
#define GET32efuse_status_qout_QOUT_95_64(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_95_64(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout2 {\
UNSG32 ustatus_qout_QOUT_95_64 : 32;\
}
union { UNSG32 u32efuse_status_qout2;
struct w32efuse_status_qout2;
};
#define GET32efuse_status_qout_QOUT_127_96(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_127_96(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout3 {\
UNSG32 ustatus_qout_QOUT_127_96 : 32;\
}
union { UNSG32 u32efuse_status_qout3;
struct w32efuse_status_qout3;
};
#define GET32efuse_status_qout_QOUT_159_128(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_159_128(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout4 {\
UNSG32 ustatus_qout_QOUT_159_128 : 32;\
}
union { UNSG32 u32efuse_status_qout4;
struct w32efuse_status_qout4;
};
#define GET32efuse_status_qout_QOUT_191_160(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_191_160(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout5 {\
UNSG32 ustatus_qout_QOUT_191_160 : 32;\
}
union { UNSG32 u32efuse_status_qout5;
struct w32efuse_status_qout5;
};
#define GET32efuse_status_qout_QOUT_223_192(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_223_192(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout6 {\
UNSG32 ustatus_qout_QOUT_223_192 : 32;\
}
union { UNSG32 u32efuse_status_qout6;
struct w32efuse_status_qout6;
};
#define GET32efuse_status_qout_QOUT_255_224(r32) _BFGET_(r32,31, 0)
#define SET32efuse_status_qout_QOUT_255_224(r32,v) _BFSET_(r32,31, 0,v)
#define w32efuse_status_qout7 {\
UNSG32 ustatus_qout_QOUT_255_224 : 32;\
}
union { UNSG32 u32efuse_status_qout7;
struct w32efuse_status_qout7;
};
#define GET32efuse_status_qout_QOUT_272_256(r32) _BFGET_(r32,16, 0)
#define SET32efuse_status_qout_QOUT_272_256(r32,v) _BFSET_(r32,16, 0,v)
#define w32efuse_status_qout8 {\
UNSG32 ustatus_qout_QOUT_272_256 : 17;\
UNSG32 RSVDx28_b17 : 15;\
}
union { UNSG32 u32efuse_status_qout8;
struct w32efuse_status_qout8;
};
///////////////////////////////////////////////////////////
} SIE_efuse;
typedef union T32efuse_ctrl
{ UNSG32 u32;
struct w32efuse_ctrl;
} T32efuse_ctrl;
typedef union T32efuse_status_match
{ UNSG32 u32;
struct w32efuse_status_match;
} T32efuse_status_match;
typedef union T32efuse_status_qout
{ UNSG32 u32;
struct w32efuse_status_qout;
} T32efuse_status_qout;
typedef union T32efuse_status_qout1
{ UNSG32 u32;
struct w32efuse_status_qout1;
} T32efuse_status_qout1;
typedef union T32efuse_status_qout2
{ UNSG32 u32;
struct w32efuse_status_qout2;
} T32efuse_status_qout2;
typedef union T32efuse_status_qout3
{ UNSG32 u32;
struct w32efuse_status_qout3;
} T32efuse_status_qout3;
typedef union T32efuse_status_qout4
{ UNSG32 u32;
struct w32efuse_status_qout4;
} T32efuse_status_qout4;
typedef union T32efuse_status_qout5
{ UNSG32 u32;
struct w32efuse_status_qout5;
} T32efuse_status_qout5;
typedef union T32efuse_status_qout6
{ UNSG32 u32;
struct w32efuse_status_qout6;
} T32efuse_status_qout6;
typedef union T32efuse_status_qout7
{ UNSG32 u32;
struct w32efuse_status_qout7;
} T32efuse_status_qout7;
typedef union T32efuse_status_qout8
{ UNSG32 u32;
struct w32efuse_status_qout8;
} T32efuse_status_qout8;
///////////////////////////////////////////////////////////
typedef union Tefuse_ctrl
{ UNSG32 u32[1];
struct {
struct w32efuse_ctrl;
};
} Tefuse_ctrl;
typedef union Tefuse_status_match
{ UNSG32 u32[1];
struct {
struct w32efuse_status_match;
};
} Tefuse_status_match;
typedef union Tefuse_status_qout
{ UNSG32 u32[9];
struct {
struct w32efuse_status_qout;
struct w32efuse_status_qout1;
struct w32efuse_status_qout2;
struct w32efuse_status_qout3;
struct w32efuse_status_qout4;
struct w32efuse_status_qout5;
struct w32efuse_status_qout6;
struct w32efuse_status_qout7;
struct w32efuse_status_qout8;
};
} Tefuse_status_qout;
///////////////////////////////////////////////////////////
SIGN32 efuse_drvrd(SIE_efuse *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 efuse_drvwr(SIE_efuse *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void efuse_reset(SIE_efuse *p);
SIGN32 efuse_cmp (SIE_efuse *p, SIE_efuse *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define efuse_check(p,pie,pfx,hLOG) efuse_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define efuse_print(p, pfx,hLOG) efuse_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: efuse
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE PERIF biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 PHY_DBG_CTRL (P)
/// %unsigned 1 USB0_SATA_PHY_DBG 0x0
/// ###
/// * 0 : USB0 PHY MON selected
/// * 1: COMPHY PHY_DBG_TEST_BUS [9:0] selected for SATA/PCIE
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00004 USB_CTRL (P)
/// %unsigned 1 DISABLE_EL16 0x0
/// ###
/// * 0: Not disable EL16 compliance
/// * 1: Disable EL 16 compliance
/// ###
/// %unsigned 2 CTRL_MODE 0x0
/// ###
/// * 00 : For OTG mode
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00008 RSERVED_CTRL0 (P)
/// ###
/// * Not used, may be used for ECOs
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 ctrl 0x0
/// ###
/// * Not used.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 12B, bits: 36b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_PERIF
#define h_PERIF (){}
#define RA_PERIF_PHY_DBG_CTRL 0x0000
#define BA_PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x0000
#define B16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x0000
#define LSb32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0
#define LSb16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0
#define bPERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 1
#define MSK32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x00000001
///////////////////////////////////////////////////////////
#define RA_PERIF_USB_CTRL 0x0004
#define BA_PERIF_USB_CTRL_DISABLE_EL16 0x0004
#define B16PERIF_USB_CTRL_DISABLE_EL16 0x0004
#define LSb32PERIF_USB_CTRL_DISABLE_EL16 0
#define LSb16PERIF_USB_CTRL_DISABLE_EL16 0
#define bPERIF_USB_CTRL_DISABLE_EL16 1
#define MSK32PERIF_USB_CTRL_DISABLE_EL16 0x00000001
#define BA_PERIF_USB_CTRL_CTRL_MODE 0x0004
#define B16PERIF_USB_CTRL_CTRL_MODE 0x0004
#define LSb32PERIF_USB_CTRL_CTRL_MODE 1
#define LSb16PERIF_USB_CTRL_CTRL_MODE 1
#define bPERIF_USB_CTRL_CTRL_MODE 2
#define MSK32PERIF_USB_CTRL_CTRL_MODE 0x00000006
///////////////////////////////////////////////////////////
#define RA_PERIF_RSERVED_CTRL0 0x0008
#define BA_PERIF_RSERVED_CTRL0_ctrl 0x0008
#define B16PERIF_RSERVED_CTRL0_ctrl 0x0008
#define LSb32PERIF_RSERVED_CTRL0_ctrl 0
#define LSb16PERIF_RSERVED_CTRL0_ctrl 0
#define bPERIF_RSERVED_CTRL0_ctrl 32
#define MSK32PERIF_RSERVED_CTRL0_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_PERIF {
///////////////////////////////////////////////////////////
#define GET32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG(r32) _BFGET_(r32, 0, 0)
#define SET32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG(r16) _BFGET_(r16, 0, 0)
#define SET16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG(r16,v) _BFSET_(r16, 0, 0,v)
#define w32PERIF_PHY_DBG_CTRL {\
UNSG32 uPHY_DBG_CTRL_USB0_SATA_PHY_DBG : 1;\
UNSG32 RSVDx0_b1 : 31;\
}
union { UNSG32 u32PERIF_PHY_DBG_CTRL;
struct w32PERIF_PHY_DBG_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32PERIF_USB_CTRL_DISABLE_EL16(r32) _BFGET_(r32, 0, 0)
#define SET32PERIF_USB_CTRL_DISABLE_EL16(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16PERIF_USB_CTRL_DISABLE_EL16(r16) _BFGET_(r16, 0, 0)
#define SET16PERIF_USB_CTRL_DISABLE_EL16(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32PERIF_USB_CTRL_CTRL_MODE(r32) _BFGET_(r32, 2, 1)
#define SET32PERIF_USB_CTRL_CTRL_MODE(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16PERIF_USB_CTRL_CTRL_MODE(r16) _BFGET_(r16, 2, 1)
#define SET16PERIF_USB_CTRL_CTRL_MODE(r16,v) _BFSET_(r16, 2, 1,v)
#define w32PERIF_USB_CTRL {\
UNSG32 uUSB_CTRL_DISABLE_EL16 : 1;\
UNSG32 uUSB_CTRL_CTRL_MODE : 2;\
UNSG32 RSVDx4_b3 : 29;\
}
union { UNSG32 u32PERIF_USB_CTRL;
struct w32PERIF_USB_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32PERIF_RSERVED_CTRL0_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32PERIF_RSERVED_CTRL0_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32PERIF_RSERVED_CTRL0 {\
UNSG32 uRSERVED_CTRL0_ctrl : 32;\
}
union { UNSG32 u32PERIF_RSERVED_CTRL0;
struct w32PERIF_RSERVED_CTRL0;
};
///////////////////////////////////////////////////////////
} SIE_PERIF;
typedef union T32PERIF_PHY_DBG_CTRL
{ UNSG32 u32;
struct w32PERIF_PHY_DBG_CTRL;
} T32PERIF_PHY_DBG_CTRL;
typedef union T32PERIF_USB_CTRL
{ UNSG32 u32;
struct w32PERIF_USB_CTRL;
} T32PERIF_USB_CTRL;
typedef union T32PERIF_RSERVED_CTRL0
{ UNSG32 u32;
struct w32PERIF_RSERVED_CTRL0;
} T32PERIF_RSERVED_CTRL0;
///////////////////////////////////////////////////////////
typedef union TPERIF_PHY_DBG_CTRL
{ UNSG32 u32[1];
struct {
struct w32PERIF_PHY_DBG_CTRL;
};
} TPERIF_PHY_DBG_CTRL;
typedef union TPERIF_USB_CTRL
{ UNSG32 u32[1];
struct {
struct w32PERIF_USB_CTRL;
};
} TPERIF_USB_CTRL;
typedef union TPERIF_RSERVED_CTRL0
{ UNSG32 u32[1];
struct {
struct w32PERIF_RSERVED_CTRL0;
};
} TPERIF_RSERVED_CTRL0;
///////////////////////////////////////////////////////////
SIGN32 PERIF_drvrd(SIE_PERIF *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 PERIF_drvwr(SIE_PERIF *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void PERIF_reset(SIE_PERIF *p);
SIGN32 PERIF_cmp (SIE_PERIF *p, SIE_PERIF *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define PERIF_check(p,pie,pfx,hLOG) PERIF_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define PERIF_print(p, pfx,hLOG) PERIF_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: PERIF
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE padRing (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 REG_PDB_CORE 0x1
/// : NORMAL 0x1
/// : PWRDN 0x0
/// ###
/// * When REG_PDB_CORE is logic '1', the regulator works in normal mode and consumes ~60uA current at typical 25degC. When REG_PDB_CORE is logic '0', the regulator works in power-down mode and consumes ~6uA current at typical 25degC.
/// ###
/// %unsigned 1 REF_INT_EN 0x1
/// : NORMAL 0x1
/// : REF_DOWN 0x0
/// ###
/// * When REF_INT_EN='1', REF/REF_FT is generated internally. When REF_INT_EN='0', the internal REF circuit is powered down and the REF signal is brought down to 0.
/// * Since we do not use HSIN pads in bg2dtv, we do not use this setting.
/// ###
/// %unsigned 1 V18EN_CORE 0x0
/// %unsigned 1 V25EN_CORE 0x0
/// ###
/// * V18EN_CORE and V25EN_CORE are settings for different IO supply level
/// * V18EN_CORE=0,V25EN_CORE=0 : 3.3V
/// * V18EN_CORE=0,V25EN_CORE=1 : 2.5V
/// * V18EN_CORE=1,V25EN_CORE=X : 1.5V, 1.5V or 1.8V
/// ###
/// %unsigned 4 ZP 0x0
/// ###
/// * ZP[3:0] is used to program PMOS output driver strength for PADXDC_HSIOB. ZP[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 ZN 0x0
/// ###
/// * ZN[3:0] is used to program NMOS output driver strength for PADXDC_HSIOB. ZN[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 CAL_ZP 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 4 CAL_ZN 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 1 CAL_P_EN 0x0
/// ###
/// * CAL_P_EN is active high core signal. Needs to be asserted high to start the PMOS driver calibration
/// ###
/// %unsigned 1 CAL_N_EN 0x0
/// ###
/// * CAL_N_EN is active high core signal. Needs to be asserted high to start the NMOS driver calibration. PMOS driver has to be calibrated first, and ZP_AFT_CAL[3:0] need to be set to the calibrated PMOS settings before CAL_N_EN is asserted high
/// ###
/// %unsigned 1 ODR_EN 0x1
/// ###
/// * When off-chip resistor is used, please set ODR_EN=0. When internal resistor is used for calibration, please set ODR_EN=1 and choose a proper ODR[2:0] setting to achieve desired driver strength.
/// ###
/// %unsigned 3 ODR 0x0
/// ###
/// * ODR[2:0] is used to adjust the internal reference resistor value for calibration without external resistor. ODR_EN need to be set to '1' to enable internal resistor.
/// ###
/// %unsigned 4 ZP_AFT_CAL 0x0
/// ###
/// * ZP_AFT_CAL[3:0] are active high signals at the core signal level. They should be fed in by the registers that stores the settings after the PMOS driver calibration
/// ###
/// %% 2 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 1 CAL_P_INC
/// ###
/// * CAL_P_INC is the output of the comparator. When the pad voltage is lower than the internal reference voltage, CAL_P_INC is high (i.e. the output impedance of PMOS is higher than the desired impedance).
/// * In a calibration loop, CAL_P_INC high can be interpreted as a signal to increment ZP[3:0].
/// ###
/// %unsigned 1 CAL_N_INC
/// ###
/// * CAL_N_INC is the output of the comparator. When the pad voltage is higher than the internal reference voltage, CAL_N_INC is high (i.e. the output impedance of NMOS is higher than the desired impedance). In a calibration loop, CAL_N_INC high can be interpreted as a signal to increment ZN[3:0].
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_padRing
#define h_padRing (){}
#define RA_padRing_ctrl 0x0000
#define BA_padRing_ctrl_REG_PDB_CORE 0x0000
#define B16padRing_ctrl_REG_PDB_CORE 0x0000
#define LSb32padRing_ctrl_REG_PDB_CORE 0
#define LSb16padRing_ctrl_REG_PDB_CORE 0
#define bpadRing_ctrl_REG_PDB_CORE 1
#define MSK32padRing_ctrl_REG_PDB_CORE 0x00000001
#define padRing_ctrl_REG_PDB_CORE_NORMAL 0x1
#define padRing_ctrl_REG_PDB_CORE_PWRDN 0x0
#define BA_padRing_ctrl_REF_INT_EN 0x0000
#define B16padRing_ctrl_REF_INT_EN 0x0000
#define LSb32padRing_ctrl_REF_INT_EN 1
#define LSb16padRing_ctrl_REF_INT_EN 1
#define bpadRing_ctrl_REF_INT_EN 1
#define MSK32padRing_ctrl_REF_INT_EN 0x00000002
#define padRing_ctrl_REF_INT_EN_NORMAL 0x1
#define padRing_ctrl_REF_INT_EN_REF_DOWN 0x0
#define BA_padRing_ctrl_V18EN_CORE 0x0000
#define B16padRing_ctrl_V18EN_CORE 0x0000
#define LSb32padRing_ctrl_V18EN_CORE 2
#define LSb16padRing_ctrl_V18EN_CORE 2
#define bpadRing_ctrl_V18EN_CORE 1
#define MSK32padRing_ctrl_V18EN_CORE 0x00000004
#define BA_padRing_ctrl_V25EN_CORE 0x0000
#define B16padRing_ctrl_V25EN_CORE 0x0000
#define LSb32padRing_ctrl_V25EN_CORE 3
#define LSb16padRing_ctrl_V25EN_CORE 3
#define bpadRing_ctrl_V25EN_CORE 1
#define MSK32padRing_ctrl_V25EN_CORE 0x00000008
#define BA_padRing_ctrl_ZP 0x0000
#define B16padRing_ctrl_ZP 0x0000
#define LSb32padRing_ctrl_ZP 4
#define LSb16padRing_ctrl_ZP 4
#define bpadRing_ctrl_ZP 4
#define MSK32padRing_ctrl_ZP 0x000000F0
#define BA_padRing_ctrl_ZN 0x0001
#define B16padRing_ctrl_ZN 0x0000
#define LSb32padRing_ctrl_ZN 8
#define LSb16padRing_ctrl_ZN 8
#define bpadRing_ctrl_ZN 4
#define MSK32padRing_ctrl_ZN 0x00000F00
#define BA_padRing_ctrl_CAL_ZP 0x0001
#define B16padRing_ctrl_CAL_ZP 0x0000
#define LSb32padRing_ctrl_CAL_ZP 12
#define LSb16padRing_ctrl_CAL_ZP 12
#define bpadRing_ctrl_CAL_ZP 4
#define MSK32padRing_ctrl_CAL_ZP 0x0000F000
#define BA_padRing_ctrl_CAL_ZN 0x0002
#define B16padRing_ctrl_CAL_ZN 0x0002
#define LSb32padRing_ctrl_CAL_ZN 16
#define LSb16padRing_ctrl_CAL_ZN 0
#define bpadRing_ctrl_CAL_ZN 4
#define MSK32padRing_ctrl_CAL_ZN 0x000F0000
#define BA_padRing_ctrl_CAL_P_EN 0x0002
#define B16padRing_ctrl_CAL_P_EN 0x0002
#define LSb32padRing_ctrl_CAL_P_EN 20
#define LSb16padRing_ctrl_CAL_P_EN 4
#define bpadRing_ctrl_CAL_P_EN 1
#define MSK32padRing_ctrl_CAL_P_EN 0x00100000
#define BA_padRing_ctrl_CAL_N_EN 0x0002
#define B16padRing_ctrl_CAL_N_EN 0x0002
#define LSb32padRing_ctrl_CAL_N_EN 21
#define LSb16padRing_ctrl_CAL_N_EN 5
#define bpadRing_ctrl_CAL_N_EN 1
#define MSK32padRing_ctrl_CAL_N_EN 0x00200000
#define BA_padRing_ctrl_ODR_EN 0x0002
#define B16padRing_ctrl_ODR_EN 0x0002
#define LSb32padRing_ctrl_ODR_EN 22
#define LSb16padRing_ctrl_ODR_EN 6
#define bpadRing_ctrl_ODR_EN 1
#define MSK32padRing_ctrl_ODR_EN 0x00400000
#define BA_padRing_ctrl_ODR 0x0002
#define B16padRing_ctrl_ODR 0x0002
#define LSb32padRing_ctrl_ODR 23
#define LSb16padRing_ctrl_ODR 7
#define bpadRing_ctrl_ODR 3
#define MSK32padRing_ctrl_ODR 0x03800000
#define BA_padRing_ctrl_ZP_AFT_CAL 0x0003
#define B16padRing_ctrl_ZP_AFT_CAL 0x0002
#define LSb32padRing_ctrl_ZP_AFT_CAL 26
#define LSb16padRing_ctrl_ZP_AFT_CAL 10
#define bpadRing_ctrl_ZP_AFT_CAL 4
#define MSK32padRing_ctrl_ZP_AFT_CAL 0x3C000000
///////////////////////////////////////////////////////////
#define RA_padRing_status 0x0004
#define BA_padRing_status_CAL_P_INC 0x0004
#define B16padRing_status_CAL_P_INC 0x0004
#define LSb32padRing_status_CAL_P_INC 0
#define LSb16padRing_status_CAL_P_INC 0
#define bpadRing_status_CAL_P_INC 1
#define MSK32padRing_status_CAL_P_INC 0x00000001
#define BA_padRing_status_CAL_N_INC 0x0004
#define B16padRing_status_CAL_N_INC 0x0004
#define LSb32padRing_status_CAL_N_INC 1
#define LSb16padRing_status_CAL_N_INC 1
#define bpadRing_status_CAL_N_INC 1
#define MSK32padRing_status_CAL_N_INC 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_padRing {
///////////////////////////////////////////////////////////
#define GET32padRing_ctrl_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32padRing_ctrl_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRing_ctrl_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16padRing_ctrl_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRing_ctrl_REF_INT_EN(r32) _BFGET_(r32, 1, 1)
#define SET32padRing_ctrl_REF_INT_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRing_ctrl_REF_INT_EN(r16) _BFGET_(r16, 1, 1)
#define SET16padRing_ctrl_REF_INT_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32padRing_ctrl_V18EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32padRing_ctrl_V18EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16padRing_ctrl_V18EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16padRing_ctrl_V18EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32padRing_ctrl_V25EN_CORE(r32) _BFGET_(r32, 3, 3)
#define SET32padRing_ctrl_V25EN_CORE(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16padRing_ctrl_V25EN_CORE(r16) _BFGET_(r16, 3, 3)
#define SET16padRing_ctrl_V25EN_CORE(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32padRing_ctrl_ZP(r32) _BFGET_(r32, 7, 4)
#define SET32padRing_ctrl_ZP(r32,v) _BFSET_(r32, 7, 4,v)
#define GET16padRing_ctrl_ZP(r16) _BFGET_(r16, 7, 4)
#define SET16padRing_ctrl_ZP(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32padRing_ctrl_ZN(r32) _BFGET_(r32,11, 8)
#define SET32padRing_ctrl_ZN(r32,v) _BFSET_(r32,11, 8,v)
#define GET16padRing_ctrl_ZN(r16) _BFGET_(r16,11, 8)
#define SET16padRing_ctrl_ZN(r16,v) _BFSET_(r16,11, 8,v)
#define GET32padRing_ctrl_CAL_ZP(r32) _BFGET_(r32,15,12)
#define SET32padRing_ctrl_CAL_ZP(r32,v) _BFSET_(r32,15,12,v)
#define GET16padRing_ctrl_CAL_ZP(r16) _BFGET_(r16,15,12)
#define SET16padRing_ctrl_CAL_ZP(r16,v) _BFSET_(r16,15,12,v)
#define GET32padRing_ctrl_CAL_ZN(r32) _BFGET_(r32,19,16)
#define SET32padRing_ctrl_CAL_ZN(r32,v) _BFSET_(r32,19,16,v)
#define GET16padRing_ctrl_CAL_ZN(r16) _BFGET_(r16, 3, 0)
#define SET16padRing_ctrl_CAL_ZN(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32padRing_ctrl_CAL_P_EN(r32) _BFGET_(r32,20,20)
#define SET32padRing_ctrl_CAL_P_EN(r32,v) _BFSET_(r32,20,20,v)
#define GET16padRing_ctrl_CAL_P_EN(r16) _BFGET_(r16, 4, 4)
#define SET16padRing_ctrl_CAL_P_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32padRing_ctrl_CAL_N_EN(r32) _BFGET_(r32,21,21)
#define SET32padRing_ctrl_CAL_N_EN(r32,v) _BFSET_(r32,21,21,v)
#define GET16padRing_ctrl_CAL_N_EN(r16) _BFGET_(r16, 5, 5)
#define SET16padRing_ctrl_CAL_N_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32padRing_ctrl_ODR_EN(r32) _BFGET_(r32,22,22)
#define SET32padRing_ctrl_ODR_EN(r32,v) _BFSET_(r32,22,22,v)
#define GET16padRing_ctrl_ODR_EN(r16) _BFGET_(r16, 6, 6)
#define SET16padRing_ctrl_ODR_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32padRing_ctrl_ODR(r32) _BFGET_(r32,25,23)
#define SET32padRing_ctrl_ODR(r32,v) _BFSET_(r32,25,23,v)
#define GET16padRing_ctrl_ODR(r16) _BFGET_(r16, 9, 7)
#define SET16padRing_ctrl_ODR(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32padRing_ctrl_ZP_AFT_CAL(r32) _BFGET_(r32,29,26)
#define SET32padRing_ctrl_ZP_AFT_CAL(r32,v) _BFSET_(r32,29,26,v)
#define GET16padRing_ctrl_ZP_AFT_CAL(r16) _BFGET_(r16,13,10)
#define SET16padRing_ctrl_ZP_AFT_CAL(r16,v) _BFSET_(r16,13,10,v)
#define w32padRing_ctrl {\
UNSG32 uctrl_REG_PDB_CORE : 1;\
UNSG32 uctrl_REF_INT_EN : 1;\
UNSG32 uctrl_V18EN_CORE : 1;\
UNSG32 uctrl_V25EN_CORE : 1;\
UNSG32 uctrl_ZP : 4;\
UNSG32 uctrl_ZN : 4;\
UNSG32 uctrl_CAL_ZP : 4;\
UNSG32 uctrl_CAL_ZN : 4;\
UNSG32 uctrl_CAL_P_EN : 1;\
UNSG32 uctrl_CAL_N_EN : 1;\
UNSG32 uctrl_ODR_EN : 1;\
UNSG32 uctrl_ODR : 3;\
UNSG32 uctrl_ZP_AFT_CAL : 4;\
UNSG32 RSVDx0_b30 : 2;\
}
union { UNSG32 u32padRing_ctrl;
struct w32padRing_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32padRing_status_CAL_P_INC(r32) _BFGET_(r32, 0, 0)
#define SET32padRing_status_CAL_P_INC(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRing_status_CAL_P_INC(r16) _BFGET_(r16, 0, 0)
#define SET16padRing_status_CAL_P_INC(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRing_status_CAL_N_INC(r32) _BFGET_(r32, 1, 1)
#define SET32padRing_status_CAL_N_INC(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRing_status_CAL_N_INC(r16) _BFGET_(r16, 1, 1)
#define SET16padRing_status_CAL_N_INC(r16,v) _BFSET_(r16, 1, 1,v)
#define w32padRing_status {\
UNSG32 ustatus_CAL_P_INC : 1;\
UNSG32 ustatus_CAL_N_INC : 1;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32padRing_status;
struct w32padRing_status;
};
///////////////////////////////////////////////////////////
} SIE_padRing;
typedef union T32padRing_ctrl
{ UNSG32 u32;
struct w32padRing_ctrl;
} T32padRing_ctrl;
typedef union T32padRing_status
{ UNSG32 u32;
struct w32padRing_status;
} T32padRing_status;
///////////////////////////////////////////////////////////
typedef union TpadRing_ctrl
{ UNSG32 u32[1];
struct {
struct w32padRing_ctrl;
};
} TpadRing_ctrl;
typedef union TpadRing_status
{ UNSG32 u32[1];
struct {
struct w32padRing_status;
};
} TpadRing_status;
///////////////////////////////////////////////////////////
SIGN32 padRing_drvrd(SIE_padRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 padRing_drvwr(SIE_padRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void padRing_reset(SIE_padRing *p);
SIGN32 padRing_cmp (SIE_padRing *p, SIE_padRing *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define padRing_check(p,pie,pfx,hLOG) padRing_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define padRing_print(p, pfx,hLOG) padRing_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: padRing
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE padRingHS (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 PDB_LV 0x1
/// : NORMAL 0x1
/// : PWRDN 0x0
/// %unsigned 1 V18EN_CORE 0x0
/// %unsigned 1 V25EN_CORE 0x0
/// ###
/// * V18EN_CORE and V25EN_CORE are settings for different IO supply level
/// * V18EN_CORE=0,V25EN_CORE=0 : 3.3V
/// * V18EN_CORE=0,V25EN_CORE=1 : 2.5V
/// * V18EN_CORE=1,V25EN_CORE=X : 1.5V, 1.5V or 1.8V
/// ###
/// %unsigned 3 ZP 0x0
/// %unsigned 3 ZN 0x0
/// %unsigned 3 CAL_ZP 0x0
/// %unsigned 3 CAL_ZN 0x0
/// %unsigned 3 CAL_RON_ADJ 0x0
/// %unsigned 1 CAL_EN 0x0
/// %unsigned 1 CAL_DO 0x0
/// %% 12 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 1 CAL_INC
/// %% 31 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 21b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_padRingHS
#define h_padRingHS (){}
#define RA_padRingHS_ctrl 0x0000
#define BA_padRingHS_ctrl_PDB_LV 0x0000
#define B16padRingHS_ctrl_PDB_LV 0x0000
#define LSb32padRingHS_ctrl_PDB_LV 0
#define LSb16padRingHS_ctrl_PDB_LV 0
#define bpadRingHS_ctrl_PDB_LV 1
#define MSK32padRingHS_ctrl_PDB_LV 0x00000001
#define padRingHS_ctrl_PDB_LV_NORMAL 0x1
#define padRingHS_ctrl_PDB_LV_PWRDN 0x0
#define BA_padRingHS_ctrl_V18EN_CORE 0x0000
#define B16padRingHS_ctrl_V18EN_CORE 0x0000
#define LSb32padRingHS_ctrl_V18EN_CORE 1
#define LSb16padRingHS_ctrl_V18EN_CORE 1
#define bpadRingHS_ctrl_V18EN_CORE 1
#define MSK32padRingHS_ctrl_V18EN_CORE 0x00000002
#define BA_padRingHS_ctrl_V25EN_CORE 0x0000
#define B16padRingHS_ctrl_V25EN_CORE 0x0000
#define LSb32padRingHS_ctrl_V25EN_CORE 2
#define LSb16padRingHS_ctrl_V25EN_CORE 2
#define bpadRingHS_ctrl_V25EN_CORE 1
#define MSK32padRingHS_ctrl_V25EN_CORE 0x00000004
#define BA_padRingHS_ctrl_ZP 0x0000
#define B16padRingHS_ctrl_ZP 0x0000
#define LSb32padRingHS_ctrl_ZP 3
#define LSb16padRingHS_ctrl_ZP 3
#define bpadRingHS_ctrl_ZP 3
#define MSK32padRingHS_ctrl_ZP 0x00000038
#define BA_padRingHS_ctrl_ZN 0x0000
#define B16padRingHS_ctrl_ZN 0x0000
#define LSb32padRingHS_ctrl_ZN 6
#define LSb16padRingHS_ctrl_ZN 6
#define bpadRingHS_ctrl_ZN 3
#define MSK32padRingHS_ctrl_ZN 0x000001C0
#define BA_padRingHS_ctrl_CAL_ZP 0x0001
#define B16padRingHS_ctrl_CAL_ZP 0x0000
#define LSb32padRingHS_ctrl_CAL_ZP 9
#define LSb16padRingHS_ctrl_CAL_ZP 9
#define bpadRingHS_ctrl_CAL_ZP 3
#define MSK32padRingHS_ctrl_CAL_ZP 0x00000E00
#define BA_padRingHS_ctrl_CAL_ZN 0x0001
#define B16padRingHS_ctrl_CAL_ZN 0x0000
#define LSb32padRingHS_ctrl_CAL_ZN 12
#define LSb16padRingHS_ctrl_CAL_ZN 12
#define bpadRingHS_ctrl_CAL_ZN 3
#define MSK32padRingHS_ctrl_CAL_ZN 0x00007000
#define BA_padRingHS_ctrl_CAL_RON_ADJ 0x0001
#define B16padRingHS_ctrl_CAL_RON_ADJ 0x0000
#define LSb32padRingHS_ctrl_CAL_RON_ADJ 15
#define LSb16padRingHS_ctrl_CAL_RON_ADJ 15
#define bpadRingHS_ctrl_CAL_RON_ADJ 3
#define MSK32padRingHS_ctrl_CAL_RON_ADJ 0x00038000
#define BA_padRingHS_ctrl_CAL_EN 0x0002
#define B16padRingHS_ctrl_CAL_EN 0x0002
#define LSb32padRingHS_ctrl_CAL_EN 18
#define LSb16padRingHS_ctrl_CAL_EN 2
#define bpadRingHS_ctrl_CAL_EN 1
#define MSK32padRingHS_ctrl_CAL_EN 0x00040000
#define BA_padRingHS_ctrl_CAL_DO 0x0002
#define B16padRingHS_ctrl_CAL_DO 0x0002
#define LSb32padRingHS_ctrl_CAL_DO 19
#define LSb16padRingHS_ctrl_CAL_DO 3
#define bpadRingHS_ctrl_CAL_DO 1
#define MSK32padRingHS_ctrl_CAL_DO 0x00080000
///////////////////////////////////////////////////////////
#define RA_padRingHS_status 0x0004
#define BA_padRingHS_status_CAL_INC 0x0004
#define B16padRingHS_status_CAL_INC 0x0004
#define LSb32padRingHS_status_CAL_INC 0
#define LSb16padRingHS_status_CAL_INC 0
#define bpadRingHS_status_CAL_INC 1
#define MSK32padRingHS_status_CAL_INC 0x00000001
///////////////////////////////////////////////////////////
typedef struct SIE_padRingHS {
///////////////////////////////////////////////////////////
#define GET32padRingHS_ctrl_PDB_LV(r32) _BFGET_(r32, 0, 0)
#define SET32padRingHS_ctrl_PDB_LV(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRingHS_ctrl_PDB_LV(r16) _BFGET_(r16, 0, 0)
#define SET16padRingHS_ctrl_PDB_LV(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRingHS_ctrl_V18EN_CORE(r32) _BFGET_(r32, 1, 1)
#define SET32padRingHS_ctrl_V18EN_CORE(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRingHS_ctrl_V18EN_CORE(r16) _BFGET_(r16, 1, 1)
#define SET16padRingHS_ctrl_V18EN_CORE(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32padRingHS_ctrl_V25EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32padRingHS_ctrl_V25EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16padRingHS_ctrl_V25EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16padRingHS_ctrl_V25EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32padRingHS_ctrl_ZP(r32) _BFGET_(r32, 5, 3)
#define SET32padRingHS_ctrl_ZP(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16padRingHS_ctrl_ZP(r16) _BFGET_(r16, 5, 3)
#define SET16padRingHS_ctrl_ZP(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32padRingHS_ctrl_ZN(r32) _BFGET_(r32, 8, 6)
#define SET32padRingHS_ctrl_ZN(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16padRingHS_ctrl_ZN(r16) _BFGET_(r16, 8, 6)
#define SET16padRingHS_ctrl_ZN(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32padRingHS_ctrl_CAL_ZP(r32) _BFGET_(r32,11, 9)
#define SET32padRingHS_ctrl_CAL_ZP(r32,v) _BFSET_(r32,11, 9,v)
#define GET16padRingHS_ctrl_CAL_ZP(r16) _BFGET_(r16,11, 9)
#define SET16padRingHS_ctrl_CAL_ZP(r16,v) _BFSET_(r16,11, 9,v)
#define GET32padRingHS_ctrl_CAL_ZN(r32) _BFGET_(r32,14,12)
#define SET32padRingHS_ctrl_CAL_ZN(r32,v) _BFSET_(r32,14,12,v)
#define GET16padRingHS_ctrl_CAL_ZN(r16) _BFGET_(r16,14,12)
#define SET16padRingHS_ctrl_CAL_ZN(r16,v) _BFSET_(r16,14,12,v)
#define GET32padRingHS_ctrl_CAL_RON_ADJ(r32) _BFGET_(r32,17,15)
#define SET32padRingHS_ctrl_CAL_RON_ADJ(r32,v) _BFSET_(r32,17,15,v)
#define GET32padRingHS_ctrl_CAL_EN(r32) _BFGET_(r32,18,18)
#define SET32padRingHS_ctrl_CAL_EN(r32,v) _BFSET_(r32,18,18,v)
#define GET16padRingHS_ctrl_CAL_EN(r16) _BFGET_(r16, 2, 2)
#define SET16padRingHS_ctrl_CAL_EN(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32padRingHS_ctrl_CAL_DO(r32) _BFGET_(r32,19,19)
#define SET32padRingHS_ctrl_CAL_DO(r32,v) _BFSET_(r32,19,19,v)
#define GET16padRingHS_ctrl_CAL_DO(r16) _BFGET_(r16, 3, 3)
#define SET16padRingHS_ctrl_CAL_DO(r16,v) _BFSET_(r16, 3, 3,v)
#define w32padRingHS_ctrl {\
UNSG32 uctrl_PDB_LV : 1;\
UNSG32 uctrl_V18EN_CORE : 1;\
UNSG32 uctrl_V25EN_CORE : 1;\
UNSG32 uctrl_ZP : 3;\
UNSG32 uctrl_ZN : 3;\
UNSG32 uctrl_CAL_ZP : 3;\
UNSG32 uctrl_CAL_ZN : 3;\
UNSG32 uctrl_CAL_RON_ADJ : 3;\
UNSG32 uctrl_CAL_EN : 1;\
UNSG32 uctrl_CAL_DO : 1;\
UNSG32 RSVDx0_b20 : 12;\
}
union { UNSG32 u32padRingHS_ctrl;
struct w32padRingHS_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32padRingHS_status_CAL_INC(r32) _BFGET_(r32, 0, 0)
#define SET32padRingHS_status_CAL_INC(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRingHS_status_CAL_INC(r16) _BFGET_(r16, 0, 0)
#define SET16padRingHS_status_CAL_INC(r16,v) _BFSET_(r16, 0, 0,v)
#define w32padRingHS_status {\
UNSG32 ustatus_CAL_INC : 1;\
UNSG32 RSVDx4_b1 : 31;\
}
union { UNSG32 u32padRingHS_status;
struct w32padRingHS_status;
};
///////////////////////////////////////////////////////////
} SIE_padRingHS;
typedef union T32padRingHS_ctrl
{ UNSG32 u32;
struct w32padRingHS_ctrl;
} T32padRingHS_ctrl;
typedef union T32padRingHS_status
{ UNSG32 u32;
struct w32padRingHS_status;
} T32padRingHS_status;
///////////////////////////////////////////////////////////
typedef union TpadRingHS_ctrl
{ UNSG32 u32[1];
struct {
struct w32padRingHS_ctrl;
};
} TpadRingHS_ctrl;
typedef union TpadRingHS_status
{ UNSG32 u32[1];
struct {
struct w32padRingHS_status;
};
} TpadRingHS_status;
///////////////////////////////////////////////////////////
SIGN32 padRingHS_drvrd(SIE_padRingHS *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 padRingHS_drvwr(SIE_padRingHS *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void padRingHS_reset(SIE_padRingHS *p);
SIGN32 padRingHS_cmp (SIE_padRingHS *p, SIE_padRingHS *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define padRingHS_check(p,pie,pfx,hLOG) padRingHS_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define padRingHS_print(p, pfx,hLOG) padRingHS_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: padRingHS
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE vtr (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 SWITCH_ON 0x0
/// : TRISTATE 0x0
/// : ENABLE 0x1
/// ###
/// * Enables or tristates VHV_OUT
/// ###
/// %unsigned 2 VOLT_SEL 0x0
/// ###
/// * if SV[1:0] = 2'b00, VHV_OUT steps down to 1.8v
/// * if SV[1:0] = 2'b01, VHV_OUT steps down to 2.0v
/// * if SV[1:0] = 2'b10, VHV_OUT steps down to 2.2v
/// * if SV[1:0] = 2'b11, VHV_OUT steps down to 2.3v
/// ###
/// %unsigned 1 PROG_SEQ_CODE 0x0
/// ###
/// * 60 bit serial code, 1011000110 1011000110 1011000110 1011000110 1011000110 1011000110,
/// * is required prior to programming.
/// * Clock cycle 0 = 1, cycle 1 = 0, cycle 2 = 1, ... cycle 9 = 0.
/// * Clock cycle 10 = 1, cycle 11 = 0, cycle 12 = 1, ... cycle 19 = 0.
/// * Clock cycle 20 = 1, cycle 21 = 0, cycle 22 = 1, ... cycle 29 = 0.
/// * Clock cycle 30 = 1, cycle 31 = 0, cycle 32 = 1, ... cycle 39 = 0.
/// * Clock cycle 40 = 1, cycle 41 = 0, cycle 42 = 1, ... cycle 49 = 0.
/// * Clock cycle 50 = 1, cycle 51 = 0, cycle 52 = 1, ... cycle 59 = 0.
/// ###
/// %unsigned 1 PROG_SEQ_CODE_CLK 0x0
/// ###
/// * Clock needed to latch in the 60bit serial code on the rising edge prior to programming.
/// * After latching in the last bit, this clock must not provide any additional rising edges while programming.
/// * It is gated by SWITCH_ON. SWITCH_ON MUST be 1 before PROG* signals are latched into VTR.
/// * If SWITCH_ON = 0, it will not allow PROG_SEQ_CODE to be loaded into internal flops and force MATCH to be 0.
/// * Min clock period = 20nS, min clock HIGH time = 2ns, min clock LOW time = 2ns
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 1 MATCH 0x0
/// ###
/// * MATCH = 1 indicates the current values of code matches the 60bit code specified above.
/// ###
/// %% 31 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_vtr
#define h_vtr (){}
#define RA_vtr_ctrl 0x0000
#define BA_vtr_ctrl_SWITCH_ON 0x0000
#define B16vtr_ctrl_SWITCH_ON 0x0000
#define LSb32vtr_ctrl_SWITCH_ON 0
#define LSb16vtr_ctrl_SWITCH_ON 0
#define bvtr_ctrl_SWITCH_ON 1
#define MSK32vtr_ctrl_SWITCH_ON 0x00000001
#define vtr_ctrl_SWITCH_ON_TRISTATE 0x0
#define vtr_ctrl_SWITCH_ON_ENABLE 0x1
#define BA_vtr_ctrl_VOLT_SEL 0x0000
#define B16vtr_ctrl_VOLT_SEL 0x0000
#define LSb32vtr_ctrl_VOLT_SEL 1
#define LSb16vtr_ctrl_VOLT_SEL 1
#define bvtr_ctrl_VOLT_SEL 2
#define MSK32vtr_ctrl_VOLT_SEL 0x00000006
#define BA_vtr_ctrl_PROG_SEQ_CODE 0x0000
#define B16vtr_ctrl_PROG_SEQ_CODE 0x0000
#define LSb32vtr_ctrl_PROG_SEQ_CODE 3
#define LSb16vtr_ctrl_PROG_SEQ_CODE 3
#define bvtr_ctrl_PROG_SEQ_CODE 1
#define MSK32vtr_ctrl_PROG_SEQ_CODE 0x00000008
#define BA_vtr_ctrl_PROG_SEQ_CODE_CLK 0x0000
#define B16vtr_ctrl_PROG_SEQ_CODE_CLK 0x0000
#define LSb32vtr_ctrl_PROG_SEQ_CODE_CLK 4
#define LSb16vtr_ctrl_PROG_SEQ_CODE_CLK 4
#define bvtr_ctrl_PROG_SEQ_CODE_CLK 1
#define MSK32vtr_ctrl_PROG_SEQ_CODE_CLK 0x00000010
///////////////////////////////////////////////////////////
#define RA_vtr_status 0x0004
#define BA_vtr_status_MATCH 0x0004
#define B16vtr_status_MATCH 0x0004
#define LSb32vtr_status_MATCH 0
#define LSb16vtr_status_MATCH 0
#define bvtr_status_MATCH 1
#define MSK32vtr_status_MATCH 0x00000001
///////////////////////////////////////////////////////////
typedef struct SIE_vtr {
///////////////////////////////////////////////////////////
#define GET32vtr_ctrl_SWITCH_ON(r32) _BFGET_(r32, 0, 0)
#define SET32vtr_ctrl_SWITCH_ON(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16vtr_ctrl_SWITCH_ON(r16) _BFGET_(r16, 0, 0)
#define SET16vtr_ctrl_SWITCH_ON(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32vtr_ctrl_VOLT_SEL(r32) _BFGET_(r32, 2, 1)
#define SET32vtr_ctrl_VOLT_SEL(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16vtr_ctrl_VOLT_SEL(r16) _BFGET_(r16, 2, 1)
#define SET16vtr_ctrl_VOLT_SEL(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32vtr_ctrl_PROG_SEQ_CODE(r32) _BFGET_(r32, 3, 3)
#define SET32vtr_ctrl_PROG_SEQ_CODE(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16vtr_ctrl_PROG_SEQ_CODE(r16) _BFGET_(r16, 3, 3)
#define SET16vtr_ctrl_PROG_SEQ_CODE(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32vtr_ctrl_PROG_SEQ_CODE_CLK(r32) _BFGET_(r32, 4, 4)
#define SET32vtr_ctrl_PROG_SEQ_CODE_CLK(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16vtr_ctrl_PROG_SEQ_CODE_CLK(r16) _BFGET_(r16, 4, 4)
#define SET16vtr_ctrl_PROG_SEQ_CODE_CLK(r16,v) _BFSET_(r16, 4, 4,v)
#define w32vtr_ctrl {\
UNSG32 uctrl_SWITCH_ON : 1;\
UNSG32 uctrl_VOLT_SEL : 2;\
UNSG32 uctrl_PROG_SEQ_CODE : 1;\
UNSG32 uctrl_PROG_SEQ_CODE_CLK : 1;\
UNSG32 RSVDx0_b5 : 27;\
}
union { UNSG32 u32vtr_ctrl;
struct w32vtr_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32vtr_status_MATCH(r32) _BFGET_(r32, 0, 0)
#define SET32vtr_status_MATCH(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16vtr_status_MATCH(r16) _BFGET_(r16, 0, 0)
#define SET16vtr_status_MATCH(r16,v) _BFSET_(r16, 0, 0,v)
#define w32vtr_status {\
UNSG32 ustatus_MATCH : 1;\
UNSG32 RSVDx4_b1 : 31;\
}
union { UNSG32 u32vtr_status;
struct w32vtr_status;
};
///////////////////////////////////////////////////////////
} SIE_vtr;
typedef union T32vtr_ctrl
{ UNSG32 u32;
struct w32vtr_ctrl;
} T32vtr_ctrl;
typedef union T32vtr_status
{ UNSG32 u32;
struct w32vtr_status;
} T32vtr_status;
///////////////////////////////////////////////////////////
typedef union Tvtr_ctrl
{ UNSG32 u32[1];
struct {
struct w32vtr_ctrl;
};
} Tvtr_ctrl;
typedef union Tvtr_status
{ UNSG32 u32[1];
struct {
struct w32vtr_status;
};
} Tvtr_status;
///////////////////////////////////////////////////////////
SIGN32 vtr_drvrd(SIE_vtr *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 vtr_drvwr(SIE_vtr *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void vtr_reset(SIE_vtr *p);
SIGN32 vtr_cmp (SIE_vtr *p, SIE_vtr *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define vtr_check(p,pie,pfx,hLOG) vtr_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define vtr_print(p, pfx,hLOG) vtr_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: vtr
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE Gbl biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ProductId (R-)
/// ###
/// * Product ID register
/// ###
/// %unsigned 32 Id
/// ###
/// * Product ID:
/// * [31:28] : Revision Id (0x0)/P
/// * [27:12] : Part Number (0x3108)
/// * [11:1] : Manufacture Id (0x588)
/// * [0] : Reserved (0x1)
/// ###
/// @ 0x00004 ProductId_ext (R-)
/// ###
/// * Product ID Extension
/// ###
/// %unsigned 8 ID_EXT
/// ###
/// * ID extension value
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00008 INT_ID (R-)
/// ###
/// * **INTERNAL_ONLY**
/// * Internal ID register
/// ###
/// %unsigned 8 VALUE
/// ###
/// * Internal ID
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0000C bootStrap (R-)
/// ###
/// * Boot Strap Register (Read Only). Boot straps are latched on Power On and stored in this register.
/// * This register can be reset only by PAD reset.
/// ###
/// %unsigned 2 softwareStrap 0x0
/// ###
/// * Straps for software usage
/// ###
/// %unsigned 2 bootSrc 0x0
/// : ROM_SPI_BOOT 0x0
/// : ROM_NAND_BOOT 0x1
/// : ROM_EMMC_BOOT 0x2
/// : ROM_SPI_DIRECT_BOOT 0x3
/// ###
/// * CPU boot source
/// * 00: ROM boot from SPI
/// * 01: ROM boot from NAND
/// * 10: ROM boot from EMMC
/// * 11: Direct boot from SPI (Only available when ENG_EN=1)
/// * Note: When direct boot from SPI (SPI clear boot), pwrCntlByps and cpuRstByps should be set to 1
/// ###
/// %unsigned 1 cpuRstByps 0x1
/// : CPU_INT_RST_BYPS 0x1
/// : CPU_INT_RST_EN 0x0
/// ###
/// * CPU reset bypass strap
/// * 1: Bypass reset logic inside CPU partition
/// * 0: Enable reset logic inside CPU partition
/// ###
/// %unsigned 1 pwrCntlByps 0x0
/// : PWR_SWITCH_ON 0x1
/// : PWR_SWITCH_OFF 0x0
/// ###
/// * Power domain Power Switch control
/// * 1: Power Switch ON. Turn on all power domains during boot up
/// * 0: Power Switch OFF . Only turn on top-module (including BCM) during boot up. All other modules are OFF (AVIO, CPU,MC5, GFX3D, V2G, G1)
/// ###
/// %unsigned 1 pllPwrDown 0x1
/// : PWR_DOWN 0x1
/// : PWR_UP 0x0
/// ###
/// * PLL Power Down
/// * SYS/MEM/CPU PLL Power Down
/// * 1: Power Down
/// * 0: Power UP
/// ###
/// %unsigned 1 sysPllByps 0x0
/// : PLL_OUT 0x0
/// : BYPS 0x1
/// ###
/// * SYSPLL Bypass
/// * 0: No Bypass
/// * 1: System PLL Bypassed
/// ###
/// %unsigned 1 memPllByps 0x0
/// : PLL_OUT 0x0
/// : BYPS 0x1
/// ###
/// * MEMPLL Bypass indicator
/// * 0: No Bypass
/// * 1: Memory PLL Bypassed
/// ###
/// %unsigned 1 cpuPllByps 0x0
/// : PLL_OUT 0x0
/// : BYPS 0x1
/// ###
/// * CPUPLL Bypass indicator
/// * 0: No Bypass
/// * 1: CPUPLL Bypassed
/// ###
/// %unsigned 1 nandV18Enable 0x0
/// : V1R8 0x0
/// : V3R3 0x1
/// ###
/// * NAND pads power selection
/// * 0: NAND pad ring is 3.3V
/// * 1: NAND pad ring is 1.8V
/// ###
/// %unsigned 1 dftStrap 0x0
/// ###
/// * DFT Strap
/// ###
/// %unsigned 1 ENG_EN 0x0
/// : PRODUCTION_MODE 0x0
/// : DEVELOPE_MODE 0x1
/// ###
/// * Production or development mode. This is not a boot strap bit. It's a bonding option and only read by AHB.
/// * *INTERNAL_ONLY**
/// ###
/// %% 19 # Stuffing bits...
/// @ 0x00010 bootStrapEn (RW)
/// ###
/// * Boot Strap Enable register
/// * This register provides the option to over write the Bootstraps using CPU register write
/// ###
/// %unsigned 1 cpuRstBypsEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * CPU Reset Bypass Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %unsigned 1 pwrCntlBypsEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * Power Switch Control Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %unsigned 1 pllPwrDownEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * PLL Power Down Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %unsigned 1 sysPLLBypsEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * System PLL Bypass Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %unsigned 1 memPLLBypsEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * Memory PLL Bypass Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %unsigned 1 cpuPLLBypsEn 0x1
/// : ENABLE 0x1
/// : DISABLE 0x0
/// ###
/// * CPU PLL Bypass Strap Enable
/// * 1 : Allow bootstrap
/// * 0 : Disable bootstrap
/// ###
/// %% 26 # Stuffing bits...
/// @ 0x00014 chipCntl (P-)
/// ###
/// * Misc Chip Control bits
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 1 SD0_CLK_LPBK_EN 0x1
/// ###
/// * SD0 CLK Loop Back enable bit
/// ###
/// %unsigned 1 EMMC_CLK_LPBK_EN 0x1
/// ###
/// * EMMC CLK Loop Back enable bit
/// ###
/// %unsigned 1 FE_MDIO_SEL 0x0
/// ###
/// * Select FE_PHY MDIO control source
/// * 0: eth1
/// * 1: FE_MDC/FE_MDIO pinMux
/// ###
/// %unsigned 1 eth1_PHY_SEL 0x0
/// ###
/// * Select eth1 PHY
/// * 0: use FE_PHY in SM
/// * 1: use external PHY through MII pinMux(ET_*)
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00018 sw_generic0 (P-)
/// ###
/// * Generic software register.
/// ###
/// %unsigned 32 swReg0 0x0
/// @ 0x0001C sw_generic1 (P-)
/// ###
/// * Generic software register.
/// ###
/// %unsigned 32 swReg1 0x0
/// @ 0x00020 sw_generic2 (P-)
/// ###
/// * Generic software register.
/// ###
/// %unsigned 32 swReg2 0x0
/// @ 0x00024 sw_generic3 (P-)
/// ###
/// * Generic software register. This register can be reset only by PAD reset.
/// ###
/// %unsigned 32 swReg3 0x0
/// @ 0x00028 RWTC_gfx3D31to0 (P)
/// %unsigned 32 value 0xAAAA99AA
/// ###
/// * RTWC [31:0] value for Perif
/// * *INTERNAL_ONLY**
/// ###
/// @ 0x0002C RWTC_gfx3D57to32 (P)
/// %unsigned 26 value 0x2A95B5A
/// ###
/// * RWTC [57:32] value for Perif
/// * *INTERNAL_ONLY**
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x00030 RWTC_top31to0 (P)
/// %unsigned 32 value 0xAAAA99AA
/// ###
/// * RTWC [31:0] value for TOP level
/// * *INTERNAL_ONLY**
/// ###
/// @ 0x00034 RWTC_top57to32 (P)
/// %unsigned 26 value 0x2A95B5A
/// ###
/// * RTWC [57:32] value for Top level
/// * *INTERNAL_ONLY**
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x00038 RWTC_vPro31to0 (P)
/// %unsigned 32 value 0xAAAA99AA
/// ###
/// * RTWC [31:0] value for v2gZsp
/// * *INTERNAL_ONLY**
/// ###
/// @ 0x0003C RWTC_vPro57to32 (P)
/// %unsigned 26 value 0x2A95B5A
/// ###
/// * RTWC [57:32] value for v2gZsp
/// * *INTERNAL_ONLY**
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x00040 RWTC_g1Wrap31to0 (P)
/// %unsigned 32 value 0xAAAA99AA
/// ###
/// * RTWC [31:0] value for g1Wrap
/// * *INTERNAL_ONLY**
/// ###
/// @ 0x00044 RWTC_g1Wrap57to32 (P)
/// %unsigned 26 value 0x2A95B5A
/// ###
/// * RTWC [57:32] value for g1Wrap
/// * *INTERNAL_ONLY**
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x00048 RWTC_mr7to0 (P)
/// %unsigned 8 value 0xAA
/// ###
/// * RTWC [7:0] value for mbist repair
/// * *INTERNAL_ONLY**
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0004C FPGAR (R-)
/// ###
/// * FPGA Revision ID Read only register
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 FPGAR 0xB3A9FA72
/// ###
/// * FPGA Revision ID register
/// ###
/// @ 0x00050 FPGARW (RW)
/// ###
/// * FPGA General Purpose RW register
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 FPGARW 0x0
/// ###
/// * FPGA General purpose RW register
/// * PLL Control Region
/// ###
/// @ 0x00054 (W-)
/// # # Stuffing bytes...
/// %% 3424
/// @ 0x00200 (P)
/// # 0x00200 sysPll
/// $pll sysPll REG
/// @ 0x00218 (W-)
/// # # Stuffing bytes...
/// %% 1856
/// @ 0x00300 (P)
/// # 0x00300 AVPLLB
/// $avPll AVPLLB REG
/// ###
/// * Clock and Reset Control Region
/// ###
/// @ 0x003A8 (W-)
/// # # Stuffing bytes...
/// %% 4800
/// @ 0x00600 ResetTrigger (RW-)
/// ###
/// * Software reset trigger register. Using this register software can reset particular module of the chip. Writing 1 to this register will trigger 16 reference clock (640ns) reset to the corresponding module (except for PCIe for PCIe user has all the reset duration control so writing 1 will trigger the reset and writing 0 will de-assert the reset).
/// * In the following register:
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 chipReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset all registers in the chip.
/// * Note: When this bit is set then there is no reset sequence followed to de-assert the reset to CPU in the end as done in case of boot-up. So using this bit is not suggested as CPU will come out of the reset earlier than modules which are running on slow clocks as compared to CPU.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 1 socDdrSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset memory controller
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 avioSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset whole AVIO unit
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 zspSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset Audio DSP
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 perifSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset whole Peripheral unit
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 ethSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset Peripheral Ethernet module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 ahbApbSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset Peripheral AHB-APB module (includes GPIO, Two wire Serial interface, Interrupt controller, Timers and SPI)
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 nanfSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset Peripheral NAND Flash module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 usb0SyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset peripheral USB0 module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 pBridgeSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset peripheral pBridge module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 sdioSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset peripheral SDIO module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 tspSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset TSP module
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 v2gSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset V2G
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 g1SyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset Hantro
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 bcmSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset BCM
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %unsigned 1 atbSyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset CoreSight
/// * 0 : No Reset
/// * 1 : Reset
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00604 ResetStatus (RW-)
/// ###
/// * Reset Status register indicates whether reset is triggered or not to the corresponding module.
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// * Note: Software need to write 0 to clear this register.
/// ###
/// %unsigned 1 ChipResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * **INTERNAL_ONLY**
/// ###
/// %unsigned 1 wd0Status 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Watch dog timer 0 reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 wd1Status 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Watch dog timer 1 reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 wd2Status 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Watch dog timer 2 reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 socDdrSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Memory controller reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 avioSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * AVIO unit reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 zspSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Audio DSP reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 perifSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral unit reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 ethSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral Ethernet module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 ahbApbSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral AHB-APB module (includes GPIO, Two wire Serial interface, Interrupt controller, Timers and SPI) reset status:
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 nanfSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral NAND Flash module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 usb0SyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral USB0 module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 pBridgeSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral pBridge module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 sdioSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Peripheral SDIO module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 tspSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * TSP module reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 v2gSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * V2G reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 g1SyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * Hantro reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 bcmSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * BCM reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %unsigned 1 atbSyncResetStatus 0x0
/// : asserted 0x1
/// : deasserted 0x0
/// ###
/// * ATB (CoreSight) reset status
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %% 13 # Stuffing bits...
/// @ 0x00608 gfx3DReset (RW-)
/// ###
/// * Graphics 3D reset register
/// ###
/// %unsigned 1 SyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset all registers in Graphics 3D module
/// * 0: No Reset
/// * 1: Reset
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0060C gfx3DResetStatus (RW-)
/// %unsigned 1 SyncReset 0x0
/// : assert 0x1
/// : deassert 0x0
/// ###
/// * Reset status of Graphics 3D
/// * 0 : Reset not issued
/// * 1 : Reset issued
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00610 (P)
/// # 0x00610 avioPwrCtrl
/// $pwrOff avioPwrCtrl REG
/// @ 0x00618 (P)
/// # 0x00618 gfx3DPwrCtrl
/// $pwrOff gfx3DPwrCtrl REG
/// @ 0x00620 (P)
/// # 0x00620 g1PwrCtrl
/// $pwrOff g1PwrCtrl REG
/// @ 0x00628 (P)
/// # 0x00628 v2gPwrCtrl
/// $pwrOff v2gPwrCtrl REG
/// @ 0x00630 clkEnable (P-)
/// ###
/// * Clock enable register provides the option to switch clocks OFF for power saving.
/// ###
/// %unsigned 1 ethCoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Ethernet Core Clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %unsigned 1 ahbApbCoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * *INTERNAL_ONLY**
/// * AHB-APB module (includes GPIO, Two wire Serial interface, Interrupt controller, Timers and SPI) Clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %unsigned 1 usb0CoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * USB0 Core Clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %unsigned 1 pBridgeCoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * PBridge module Clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %unsigned 1 sdioCoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * SDIO Core Clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %unsigned 1 nfcCoreClkEn 0x1
/// : enable 0x1
/// : disable 0x0
/// ###
/// * Nand Flash Controller core clock enable register
/// * 0 : disable
/// * 1 : enable
/// ###
/// %% 26 # Stuffing bits...
/// @ 0x00634 ClkSwitch (P-)
/// ###
/// * Clock Switch register. This register is used to select clock between:
/// * PLL clock or reference clock (PLL Bypass option)
/// ###
/// %unsigned 1 sysPLLSWBypass 0x0
/// : refClk 0x1
/// : pllClk 0x0
/// ###
/// * System PLL Bypass switch
/// * 0: Use PLL
/// * 1: Bypass PLL
/// ###
/// %unsigned 1 memPLLSWBypass 0x0
/// : refClk 0x1
/// : pllClk 0x0
/// ###
/// * Memory PLL Bypass switch
/// * 0: Use PLL
/// * 1: Bypass PLL
/// ###
/// %unsigned 1 cpuPLLSWBypass 0x0
/// : refClk 0x1
/// : pllClk 0x0
/// ###
/// * CPU PLL Bypass switch
/// * 0: Use PLL
/// * 1: Bypass PLL
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00638 (P)
/// # 0x00638 cpufastRefClk
/// $clkD2 cpufastRefClk REG
/// ###
/// * Fast backup clock for cpu when cpupll is bypass
/// ###
/// @ 0x0063C (P)
/// # 0x0063C memfastRefClk
/// $clkD2 memfastRefClk REG
/// ###
/// * Fast backup clock for mc5 when mempll is bypass
/// ###
/// @ 0x00640 (P)
/// # 0x00640 cfgClk
/// $clkD8 cfgClk REG
/// ###
/// * System AHB Clock
/// ###
/// @ 0x00644 (P)
/// # 0x00644 sysClk
/// $clkD2 sysClk REG
/// ###
/// * System AXI Clock
/// ###
/// @ 0x00648 (P)
/// # 0x00648 v2gClk
/// $clkD4 v2gClk REG
/// ###
/// * V2G Clock
/// ###
/// @ 0x0064C (P)
/// # 0x0064C v2gM3Clk
/// $clkD4 v2gM3Clk REG
/// ###
/// * V2GM3 clock
/// ###
/// @ 0x00650 (P)
/// # 0x00650 g1CoreClk
/// $clkD4 g1CoreClk REG
/// ###
/// * G1 (Hantro) Core Clock
/// ###
/// @ 0x00654 (P)
/// # 0x00654 gfx3DCoreClk
/// $clkD2 gfx3DCoreClk REG
/// ###
/// * GFX3D Core Clk
/// ###
/// @ 0x00658 (P)
/// # 0x00658 gfx3DSysClk
/// $clkD2 gfx3DSysClk REG
/// ###
/// * GFX3D AXI Clock
/// ###
/// @ 0x0065C (P)
/// # 0x0065C avioSysClk
/// $clkD2 avioSysClk REG
/// ###
/// * AVIO AXI Clock
/// ###
/// @ 0x00660 (P)
/// # 0x00660 appClk
/// $clkD1 appClk REG
/// ###
/// * AVIO APP Clock
/// ###
/// @ 0x00664 (P)
/// # 0x00664 vppSysClk
/// $clkD2 vppSysClk REG
/// ###
/// * AVIO VPP Clock
/// ###
/// @ 0x00668 (P)
/// # 0x00668 arcRefClk
/// $clkD2 arcRefClk REG
/// ###
/// * AVI ARC Ref Clock
/// ###
/// @ 0x0066C (P)
/// # 0x0066C hdmirxMClk
/// $clkD8 hdmirxMClk REG
/// ###
/// * HDMI RX M CLOCK
/// ###
/// @ 0x00670 (P)
/// # 0x00670 perifClk
/// $clkD4 perifClk REG
/// ###
/// * Perif System Clock
/// ###
/// @ 0x00674 (P)
/// # 0x00674 zspClk
/// $clkD2 zspClk REG
/// ###
/// * ZSP Clock
/// ###
/// @ 0x00678 (P)
/// # 0x00678 tspClk
/// $clkD2 tspClk REG
/// ###
/// * TSP Clock
/// ###
/// @ 0x0067C (P)
/// # 0x0067C tspRefClk
/// $clkD4 tspRefClk REG
/// ###
/// * TSP Reference Clock
/// ###
/// @ 0x00680 (P)
/// # 0x00680 atbClk
/// $clkD4 atbClk REG
/// ###
/// * ATB (CoreSight) Clock
/// ###
/// @ 0x00684 (P)
/// # 0x00684 bcmClk
/// $clkD4 bcmClk REG
/// ###
/// * BCM Clock
/// ###
/// @ 0x00688 (P)
/// # 0x00688 nfcEccClk
/// $clkD2 nfcEccClk REG
/// ###
/// * NFC ECC Clock
/// ###
/// @ 0x0068C (P)
/// # 0x0068C sd0Clk
/// $clkD8 sd0Clk REG
/// ###
/// * SDIO0 Clock
/// ###
/// @ 0x00690 (P)
/// # 0x00690 usb2TestClk
/// $clkD12 usb2TestClk REG
/// ###
/// * Test Mode clock for USB2 (60Mhz Max)
/// ###
/// @ 0x00694 (P)
/// # 0x00694 sdio3DllMstRefClk
/// $clkD4 sdio3DllMstRefClk REG
/// ###
/// * SDIO DLL Master Ref Clock
/// * MISC Register Control Region
/// ###
/// @ 0x00698 (W-)
/// # # Stuffing bytes...
/// %% 4928
/// @ 0x00900 SECURE_SCAN_EN (RW)
/// ###
/// * Enable secure scan, should write 1 to it immediately during boot up to disable scan
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 1 SET 0x0
/// ###
/// * 1: scan is disabled
/// * 0: scan is enabled
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00904 NandCtrl (RW)
/// ###
/// * NAND Write Protect pin control register.
/// ###
/// %unsigned 1 NAND_WPn_Sel 0x1
/// ###
/// * 0 : Write protected
/// * 1: Not Write Protected
/// ###
/// %unsigned 1 NAND_CLE_OE 0x1
/// ###
/// * 0 : Output Disabled (drive Zero)
/// * 1: Output Enabled
/// ###
/// %unsigned 1 NAND_ALE_OE 0x1
/// ###
/// * 0 : Output Disabled (drive Zero)
/// * 1: Output Enabled
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00908 sdioDllMstCtrl (RW-)
/// ###
/// * SDIO DLL Master Control register
/// ###
/// %unsigned 6 PH_SEL1 0x1F
/// ###
/// * Channel 1 Delay Phase Selections. Default setting is 90 degree phase shift.
/// ###
/// %unsigned 6 PH_SEL2 0x1F
/// ###
/// * Channel 2 Delay Phase Selections. Default setting is 90 degree phase shift.
/// ###
/// %unsigned 6 PH_SEL3 0x1F
/// ###
/// * Channel 3 Delay Phase Selections. Default setting is 90 degree phase shift.
/// ###
/// %unsigned 6 PH_SEL4 0x1F
/// ###
/// * Channel 4 Delay Phase Selections. Default setting is 90 degree phase shift.
/// ###
/// %unsigned 1 RESET 0x1
/// ###
/// * DLL reset signal. Active high.
/// ###
/// %unsigned 1 GAIN2X 0x1
/// ###
/// * 1: 55~ 300Mhz and 0 > 300-480 Mhz
/// * This bit controls frequency range.
/// * Note that GAIN2X=1, the frequency range is lower.
/// ###
/// %unsigned 1 TEST_EN 0x0
/// ###
/// * DLL test mode enable signal. When=1 disable Master. When=0 normal operation
/// ###
/// %unsigned 5 RESERVE 0x0
/// ###
/// * Reserve debug bits
/// ###
/// # 0x0090C sdioDllMstCtrl1
/// %unsigned 1 FAST_LOCK 0x1
/// ###
/// * When=1 Master lock faster, counter skips 16 counts before comparison. When=0 counter goes 1 count at a time.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00910 sdioDllMstStatus (R-)
/// ###
/// * SDIO DLL Master Status register
/// ###
/// %unsigned 10 DELAY_CTRL1
/// ###
/// * Control bits for channel 1 slave block
/// ###
/// %unsigned 10 DELAY_CTRL2
/// ###
/// * Control bits for channel 2 slave block
/// ###
/// %unsigned 10 DELAY_CTRL3
/// ###
/// * Control bits for channel 3 slave block
/// ###
/// %% 2 # Stuffing bits...
/// # 0x00914 sdioDllMstStatus1
/// %unsigned 10 DELAY_CTRL4
/// ###
/// * Control bits for channel 4 slave block
/// ###
/// %unsigned 1 DLL_LOCK
/// ###
/// * DLL ready when DLL_LOCK is high. Maximum DLL lock time is 4096 reference clock cycles.
/// ###
/// %unsigned 10 DELAY_OUT
/// ###
/// * Delay information from the DLL
/// ###
/// %% 11 # Stuffing bits...
/// @ 0x00918 gfx3DDisRamClkGate (P-)
/// ###
/// * **INTERNAL_ONLY**
/// ###
/// %unsigned 1 drcg 0x0
/// : drcgActive 0x1
/// : drcgInactive 0x0
/// ###
/// * Disable RAM clock gating in Graphics 3D when in BIST mode.
/// * Graphics 3D disable RAM CG register bit
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0091C DroEn (P-)
/// %unsigned 1 Start 0x0
/// : dro_en_start 0x1
/// ###
/// * Write 1 to this bit will generate a pulse which start the dro_ctl to assert dro_en
/// ###
/// %unsigned 16 CountVal 0x10
/// ###
/// * DRO EN counter value
/// ###
/// %% 15 # Stuffing bits...
/// # 0x00920 DroEn1
/// %unsigned 16 WaitVal 0x20
/// ###
/// * Dro_en keep 0 for WaitVal cycles after dro_clk start
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00924 DroShift (P-)
/// %unsigned 1 Start 0x0
/// : dro_shift_start 0x1
/// ###
/// * Write 1 to this bit will generate a pulse which start the dro_ctl to shift out data from dro cells
/// ###
/// %unsigned 16 CountVal 0x20
/// ###
/// * DRO Shift counter value
/// ###
/// %% 15 # Stuffing bits...
/// @ 0x00928 DroStatus (R-)
/// %unsigned 1 En 0x0
/// ###
/// * dro_en_out of the last dro cell
/// ###
/// %unsigned 1 Shift_Done 0x0
/// ###
/// * Shift Done signal from dro_ctl
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x0092C DroCounter (R-)
/// %unsigned 32 Out 0x0
/// @ 0x00930 (P)
/// # 0x00930 vtr
/// $vtr vtr REG
/// @ 0x00938 gic400_ctrl (RW-)
/// %unsigned 1 cgfsdisable 0x0
/// ###
/// * GIC400 secure disable control
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0093C SPARE_CTRL_0 (P-)
/// ###
/// * Not used. May be used for any ECOs.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 ctrl 0x0
/// @ 0x00940 SPARE_CTRL_1 (P-)
/// ###
/// * Not used. May be used for any ECOs.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 ctrl 0x0
/// @ 0x00944 SPARE_CTRL_2 (P-)
/// ###
/// * Not used. May be used for any ECOs.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 ctrl 0x0
/// @ 0x00948 SPARE_CTRL_3 (P-)
/// ###
/// * Not used. May be used for any ECOs.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 32 ctrl 0x0
/// @ 0x0094C (P)
/// # 0x0094C efuse0
/// $efuse efuse0 REG
/// ###
/// * EFUSE for ATE inside Global module
/// ###
/// @ 0x00978 (P)
/// # 0x00978 efuse1
/// $efuse efuse1 REG
/// ###
/// * EFUSE for Memory Repair in MBIST Repair module in Top
/// ###
/// @ 0x009A4 (P)
/// # 0x009A4 PERIF
/// $PERIF PERIF REG
/// ###
/// * PAD Control Region
/// ###
/// @ 0x009B0 (W-)
/// # # Stuffing bytes...
/// %% 111232
/// @ 0x04000 PadSelect (P-)
/// ###
/// * IO Pad Selection
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 1 DVIO_OEN 0x0
/// : Enable 0x1
/// : Disable 0x0
/// ###
/// * For DVIO output enable; Active high
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x04004 (P)
/// # 0x04004 I2C_PADRING
/// $padRing I2C_PADRING REG
/// ###
/// * padRing2 NO CALP pad for HSIOB pad voltage fixed at 3.3V
/// ###
/// @ 0x0400C (P)
/// # 0x0400C SD0_PADRING
/// $padRing SD0_PADRING REG
/// ###
/// * padRing5
/// ###
/// @ 0x04014 (P)
/// # 0x04014 TSI_PADRING
/// $padRing TSI_PADRING REG
/// ###
/// * padRing6
/// ###
/// @ 0x0401C (P)
/// # 0x0401C SPI_PADRING
/// $padRing SPI_PADRING REG
/// ###
/// * padRing7 NO CALP pad for HSIOB pad voltage fixed at 3.3V
/// ###
/// @ 0x04024 (P)
/// # 0x04024 NAND_PADRING
/// $padRing NAND_PADRING REG
/// ###
/// * padRing8 pad voltage select by boot strap
/// ###
/// @ 0x0402C DDC_PAD_CTRL (P-)
/// %unsigned 3 ZN_TW1_SCL 0x0
/// ###
/// * slew rate control for TW1_SCL
/// ###
/// %unsigned 3 ZN_TW1_SDA 0x0
/// ###
/// * slew rate control for TW1_SDA
/// * The below are the Pad Control Registers starting at 32KB boundary. Please do not change this offset and add any register that is needed before this.
/// ###
/// %% 26 # Stuffing bits...
/// @ 0x04030 (W-)
/// # # Stuffing bytes...
/// %% 130688
/// @ 0x08000 pinMuxCntlBus (P-)
/// %unsigned 3 URT0_RXD 0x0
/// ###
/// * pinMuxCntlBus[0*3+2:0*3] pinMux Control for URT0_RXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 URT0_TXD 0x0
/// ###
/// * pinMuxCntlBus[1*3+2:1*3] pinMux Control for URT0_TXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SPI1_SS0n 0x0
/// ###
/// * pinMuxCntlBus[2*3+2:2*3] pinMux Control for SPI1_SS0n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SPI1_SS1n 0x0
/// ###
/// * pinMuxCntlBus[3*3+2:3*3] pinMux Control for SPI1_SS1n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// %unsigned 3 SPI1_SS2n 0x0
/// ###
/// * pinMuxCntlBus[4*3+2:4*3] pinMux Control for SPI1_SS2n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// %unsigned 3 SPI1_SCLK 0x0
/// ###
/// * pinMuxCntlBus[5*3+2:5*3] pinMux Control for SPI1_SCLK
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SPI1_SDO 0x0
/// ###
/// * pinMuxCntlBus[6*3+2:6*3] pinMux Control for SPI1_SDO
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SPI1_SDI 0x0
/// ###
/// * pinMuxCntlBus[7*3+2:7*3] pinMux Control for SPI1_SDI
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 USB1_DRV_VBUS 0x0
/// ###
/// * pinMuxCntlBus[8*3+2:8*3] pinMux Control for USB1_DRV_VBUS
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 TW1_SCL 0x0
/// ###
/// * pinMuxCntlBus[9*3+2:9*3] pinMux Control for TW1_SCL
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %% 2 # Stuffing bits...
/// # 0x08004 pinMuxCntlBus1
/// %unsigned 3 TW1_SDA 0x0
/// ###
/// * pinMuxCntlBus[10*3+2:10*3] pinMux Control for TW1_SDA
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 HDMI_CEC 0x0
/// ###
/// * pinMuxCntlBus[11*3+2:11*3] pinMux Control for HDMI_CEC
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 HDMI_HPD 0x0
/// ###
/// * pinMuxCntlBus[12*3+2:12*3] pinMux Control for HDMI_HPD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 NAND_IO0 0x0
/// ###
/// * pinMuxCntlBus[13*3+2:13*3] pinMux Control for NAND_IO[0]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO1 0x0
/// ###
/// * pinMuxCntlBus[14*3+2:14*3] pinMux Control for NAND_IO[1]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO2 0x0
/// ###
/// * pinMuxCntlBus[15*3+2:15*3] pinMux Control for NAND_IO[2]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO3 0x0
/// ###
/// * pinMuxCntlBus[16*3+2:16*3] pinMux Control for NAND_IO[3]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO4 0x0
/// ###
/// * pinMuxCntlBus[17*3+2:17*3] pinMux Control for NAND_IO[4]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO5 0x0
/// ###
/// * pinMuxCntlBus[18*3+2:18*3] pinMux Control for NAND_IO[5]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_IO6 0x0
/// ###
/// * pinMuxCntlBus[19*3+2:19*3] pinMux Control for NAND_IO[6]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %% 2 # Stuffing bits...
/// # 0x08008 pinMuxCntlBus2
/// %unsigned 3 NAND_IO7 0x0
/// ###
/// * pinMuxCntlBus[20*3+2:20*3] pinMux Control for NAND_IO[7]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_ALE 0x0
/// ###
/// * pinMuxCntlBus[21*3+2:21*3] pinMux Control for NAND_ALE
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// %unsigned 3 NAND_CLE 0x0
/// ###
/// * pinMuxCntlBus[22*3+2:22*3] pinMux Control for NAND_CLE
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// %unsigned 3 NAND_WEn 0x0
/// ###
/// * pinMuxCntlBus[23*3+2:23*3] pinMux Control for NAND_WEn
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// %unsigned 3 NAND_REn 0x0
/// ###
/// * pinMuxCntlBus[24*3+2:24*3] pinMux Control for NAND_REn
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// %unsigned 3 NAND_WPn 0x0
/// ###
/// * pinMuxCntlBus[25*3+2:25*3] pinMux Control for NAND_WPn
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// %unsigned 3 NAND_CEn 0x0
/// ###
/// * pinMuxCntlBus[26*3+2:26*3] pinMux Control for NAND_CEn
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// %unsigned 3 NAND_RDY 0x0
/// ###
/// * pinMuxCntlBus[27*3+2:27*3] pinMux Control for NAND_RDY
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// %unsigned 3 SD0_CLK 0x0
/// ###
/// * pinMuxCntlBus[28*3+2:28*3] pinMux Control for SD0_CLK
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_7 0x7
/// %unsigned 3 SD0_DAT0 0x0
/// ###
/// * pinMuxCntlBus[29*3+2:29*3] pinMux Control for SD0_DAT0
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %% 2 # Stuffing bits...
/// # 0x0800C pinMuxCntlBus3
/// %unsigned 3 SD0_DAT1 0x0
/// ###
/// * pinMuxCntlBus[30*3+2:30*3] pinMux Control for SD0_DAT1
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %unsigned 3 SD0_DAT2 0x0
/// ###
/// * pinMuxCntlBus[31*3+2:31*3] pinMux Control for SD0_DAT2
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %unsigned 3 SD0_DAT3 0x0
/// ###
/// * pinMuxCntlBus[32*3+2:32*3] pinMux Control for SD0_DAT3
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %unsigned 3 SD0_CDn 0x0
/// ###
/// * pinMuxCntlBus[33*3+2:33*3] pinMux Control for SD0_CDn
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %unsigned 3 SD0_CMD 0x0
/// ###
/// * pinMuxCntlBus[34*3+2:34*3] pinMux Control for SD0_CMD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_7 0x7
/// %unsigned 3 SD0_WP 0x0
/// ###
/// * pinMuxCntlBus[35*3+2:35*3] pinMux Control for SD0_WP
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_7 0x7
/// %unsigned 3 STS0_CLK 0x0
/// ###
/// * pinMuxCntlBus[36*3+2:36*3] pinMux Control for STS0_CLK
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_4 0x4
/// %unsigned 3 STS0_SOP 0x0
/// ###
/// * pinMuxCntlBus[37*3+2:37*3] pinMux Control for STS0_SOP
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 STS0_VALD 0x0
/// ###
/// * pinMuxCntlBus[38*3+2:38*3] pinMux Control for STS0_VALD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// %unsigned 3 STS0_SD 0x0
/// ###
/// * pinMuxCntlBus[39*3+2:39*3] pinMux Control for STS0_SD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// %% 2 # Stuffing bits...
/// @ 0x08010 URT0_RXDCntl (P-)
/// ###
/// * Pad Control for URT0_RXD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08014 URT0_TXDCntl (P-)
/// ###
/// * Pad Control for URT0_TXD
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08018 SPI1_SS0nCntl (P-)
/// ###
/// * Pad Control for SPI1_SS0n
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0801C SPI1_SS1nCntl (P-)
/// ###
/// * Pad Control for SPI1_SS1n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08020 SPI1_SS2nCntl (P-)
/// ###
/// * Pad Control for SPI1_SS2n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08024 SPI1_SCLKCntl (P-)
/// ###
/// * Pad Control for SPI1_SCLK
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08028 SPI1_SDOCntl (P-)
/// ###
/// * Pad Control for SPI1_SDO
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0802C SPI1_SDICntl (P-)
/// ###
/// * Pad Control for SPI1_SDI
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08030 USB1_DRV_VBUSCntl (P-)
/// ###
/// * Pad Control for USB1_DRV_VBUS
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08034 NAND_IO0Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[0]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08038 NAND_IO1Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[1]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0803C NAND_IO2Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[2]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08040 NAND_IO3Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[3]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08044 NAND_IO4Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[4]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08048 NAND_IO5Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[5]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0804C NAND_IO6Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[6]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08050 NAND_IO7Cntl (P-)
/// ###
/// * Pad Control for NAND_IO[7]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08054 NAND_ALECntl (P-)
/// ###
/// * Pad Control for NAND_ALE
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08058 NAND_CLECntl (P-)
/// ###
/// * Pad Control for NAND_CLE
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x1
/// %% 30 # Stuffing bits...
/// @ 0x0805C NAND_WEnCntl (P-)
/// ###
/// * Pad Control for NAND_WEn
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08060 NAND_REnCntl (P-)
/// ###
/// * Pad Control for NAND_REn
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08064 NAND_WPnCntl (P-)
/// ###
/// * Pad Control for NAND_WPn
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x1
/// %% 30 # Stuffing bits...
/// @ 0x08068 NAND_CEnCntl (P-)
/// ###
/// * Pad Control for NAND_CEn
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x1
/// %% 30 # Stuffing bits...
/// @ 0x0806C NAND_RDYCntl (P-)
/// ###
/// * Pad Control for NAND_RDY
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x1
/// %% 30 # Stuffing bits...
/// @ 0x08070 SD0_CLKCntl (P-)
/// ###
/// * Pad Control for SD0_CLK
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08074 SD0_DAT0Cntl (P-)
/// ###
/// * Pad Control for SD0_DAT0
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08078 SD0_DAT1Cntl (P-)
/// ###
/// * Pad Control for SD0_DAT1
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0807C SD0_DAT2Cntl (P-)
/// ###
/// * Pad Control for SD0_DAT2
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08080 SD0_DAT3Cntl (P-)
/// ###
/// * Pad Control for SD0_DAT3
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08084 SD0_CDnCntl (P-)
/// ###
/// * Pad Control for SD0_CDn
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08088 SD0_CMDCntl (P-)
/// ###
/// * Pad Control for SD0_CMD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0808C SD0_WPCntl (P-)
/// ###
/// * Pad Control for SD0_WP
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08090 STS0_CLKCntl (P-)
/// ###
/// * Pad Control for STS0_CLK
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08094 STS0_SOPCntl (P-)
/// ###
/// * Pad Control for STS0_SOP
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x08098 STS0_VALDCntl (P-)
/// ###
/// * Pad Control for STS0_VALD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x0809C STS0_SDCntl (P-)
/// ###
/// * Pad Control for STS0_SD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 32928B, bits: 3042b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_Gbl
#define h_Gbl (){}
#define RA_Gbl_ProductId 0x0000
#define BA_Gbl_ProductId_Id 0x0000
#define B16Gbl_ProductId_Id 0x0000
#define LSb32Gbl_ProductId_Id 0
#define LSb16Gbl_ProductId_Id 0
#define bGbl_ProductId_Id 32
#define MSK32Gbl_ProductId_Id 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_ProductId_ext 0x0004
#define BA_Gbl_ProductId_ext_ID_EXT 0x0004
#define B16Gbl_ProductId_ext_ID_EXT 0x0004
#define LSb32Gbl_ProductId_ext_ID_EXT 0
#define LSb16Gbl_ProductId_ext_ID_EXT 0
#define bGbl_ProductId_ext_ID_EXT 8
#define MSK32Gbl_ProductId_ext_ID_EXT 0x000000FF
///////////////////////////////////////////////////////////
#define RA_Gbl_INT_ID 0x0008
#define BA_Gbl_INT_ID_VALUE 0x0008
#define B16Gbl_INT_ID_VALUE 0x0008
#define LSb32Gbl_INT_ID_VALUE 0
#define LSb16Gbl_INT_ID_VALUE 0
#define bGbl_INT_ID_VALUE 8
#define MSK32Gbl_INT_ID_VALUE 0x000000FF
///////////////////////////////////////////////////////////
#define RA_Gbl_bootStrap 0x000C
#define BA_Gbl_bootStrap_softwareStrap 0x000C
#define B16Gbl_bootStrap_softwareStrap 0x000C
#define LSb32Gbl_bootStrap_softwareStrap 0
#define LSb16Gbl_bootStrap_softwareStrap 0
#define bGbl_bootStrap_softwareStrap 2
#define MSK32Gbl_bootStrap_softwareStrap 0x00000003
#define BA_Gbl_bootStrap_bootSrc 0x000C
#define B16Gbl_bootStrap_bootSrc 0x000C
#define LSb32Gbl_bootStrap_bootSrc 2
#define LSb16Gbl_bootStrap_bootSrc 2
#define bGbl_bootStrap_bootSrc 2
#define MSK32Gbl_bootStrap_bootSrc 0x0000000C
#define Gbl_bootStrap_bootSrc_ROM_SPI_BOOT 0x0
#define Gbl_bootStrap_bootSrc_ROM_NAND_BOOT 0x1
#define Gbl_bootStrap_bootSrc_ROM_EMMC_BOOT 0x2
#define Gbl_bootStrap_bootSrc_ROM_SPI_DIRECT_BOOT 0x3
#define BA_Gbl_bootStrap_cpuRstByps 0x000C
#define B16Gbl_bootStrap_cpuRstByps 0x000C
#define LSb32Gbl_bootStrap_cpuRstByps 4
#define LSb16Gbl_bootStrap_cpuRstByps 4
#define bGbl_bootStrap_cpuRstByps 1
#define MSK32Gbl_bootStrap_cpuRstByps 0x00000010
#define Gbl_bootStrap_cpuRstByps_CPU_INT_RST_BYPS 0x1
#define Gbl_bootStrap_cpuRstByps_CPU_INT_RST_EN 0x0
#define BA_Gbl_bootStrap_pwrCntlByps 0x000C
#define B16Gbl_bootStrap_pwrCntlByps 0x000C
#define LSb32Gbl_bootStrap_pwrCntlByps 5
#define LSb16Gbl_bootStrap_pwrCntlByps 5
#define bGbl_bootStrap_pwrCntlByps 1
#define MSK32Gbl_bootStrap_pwrCntlByps 0x00000020
#define Gbl_bootStrap_pwrCntlByps_PWR_SWITCH_ON 0x1
#define Gbl_bootStrap_pwrCntlByps_PWR_SWITCH_OFF 0x0
#define BA_Gbl_bootStrap_pllPwrDown 0x000C
#define B16Gbl_bootStrap_pllPwrDown 0x000C
#define LSb32Gbl_bootStrap_pllPwrDown 6
#define LSb16Gbl_bootStrap_pllPwrDown 6
#define bGbl_bootStrap_pllPwrDown 1
#define MSK32Gbl_bootStrap_pllPwrDown 0x00000040
#define Gbl_bootStrap_pllPwrDown_PWR_DOWN 0x1
#define Gbl_bootStrap_pllPwrDown_PWR_UP 0x0
#define BA_Gbl_bootStrap_sysPllByps 0x000C
#define B16Gbl_bootStrap_sysPllByps 0x000C
#define LSb32Gbl_bootStrap_sysPllByps 7
#define LSb16Gbl_bootStrap_sysPllByps 7
#define bGbl_bootStrap_sysPllByps 1
#define MSK32Gbl_bootStrap_sysPllByps 0x00000080
#define Gbl_bootStrap_sysPllByps_PLL_OUT 0x0
#define Gbl_bootStrap_sysPllByps_BYPS 0x1
#define BA_Gbl_bootStrap_memPllByps 0x000D
#define B16Gbl_bootStrap_memPllByps 0x000C
#define LSb32Gbl_bootStrap_memPllByps 8
#define LSb16Gbl_bootStrap_memPllByps 8
#define bGbl_bootStrap_memPllByps 1
#define MSK32Gbl_bootStrap_memPllByps 0x00000100
#define Gbl_bootStrap_memPllByps_PLL_OUT 0x0
#define Gbl_bootStrap_memPllByps_BYPS 0x1
#define BA_Gbl_bootStrap_cpuPllByps 0x000D
#define B16Gbl_bootStrap_cpuPllByps 0x000C
#define LSb32Gbl_bootStrap_cpuPllByps 9
#define LSb16Gbl_bootStrap_cpuPllByps 9
#define bGbl_bootStrap_cpuPllByps 1
#define MSK32Gbl_bootStrap_cpuPllByps 0x00000200
#define Gbl_bootStrap_cpuPllByps_PLL_OUT 0x0
#define Gbl_bootStrap_cpuPllByps_BYPS 0x1
#define BA_Gbl_bootStrap_nandV18Enable 0x000D
#define B16Gbl_bootStrap_nandV18Enable 0x000C
#define LSb32Gbl_bootStrap_nandV18Enable 10
#define LSb16Gbl_bootStrap_nandV18Enable 10
#define bGbl_bootStrap_nandV18Enable 1
#define MSK32Gbl_bootStrap_nandV18Enable 0x00000400
#define Gbl_bootStrap_nandV18Enable_V1R8 0x0
#define Gbl_bootStrap_nandV18Enable_V3R3 0x1
#define BA_Gbl_bootStrap_dftStrap 0x000D
#define B16Gbl_bootStrap_dftStrap 0x000C
#define LSb32Gbl_bootStrap_dftStrap 11
#define LSb16Gbl_bootStrap_dftStrap 11
#define bGbl_bootStrap_dftStrap 1
#define MSK32Gbl_bootStrap_dftStrap 0x00000800
#define BA_Gbl_bootStrap_ENG_EN 0x000D
#define B16Gbl_bootStrap_ENG_EN 0x000C
#define LSb32Gbl_bootStrap_ENG_EN 12
#define LSb16Gbl_bootStrap_ENG_EN 12
#define bGbl_bootStrap_ENG_EN 1
#define MSK32Gbl_bootStrap_ENG_EN 0x00001000
#define Gbl_bootStrap_ENG_EN_PRODUCTION_MODE 0x0
#define Gbl_bootStrap_ENG_EN_DEVELOPE_MODE 0x1
///////////////////////////////////////////////////////////
#define RA_Gbl_bootStrapEn 0x0010
#define BA_Gbl_bootStrapEn_cpuRstBypsEn 0x0010
#define B16Gbl_bootStrapEn_cpuRstBypsEn 0x0010
#define LSb32Gbl_bootStrapEn_cpuRstBypsEn 0
#define LSb16Gbl_bootStrapEn_cpuRstBypsEn 0
#define bGbl_bootStrapEn_cpuRstBypsEn 1
#define MSK32Gbl_bootStrapEn_cpuRstBypsEn 0x00000001
#define Gbl_bootStrapEn_cpuRstBypsEn_ENABLE 0x1
#define Gbl_bootStrapEn_cpuRstBypsEn_DISABLE 0x0
#define BA_Gbl_bootStrapEn_pwrCntlBypsEn 0x0010
#define B16Gbl_bootStrapEn_pwrCntlBypsEn 0x0010
#define LSb32Gbl_bootStrapEn_pwrCntlBypsEn 1
#define LSb16Gbl_bootStrapEn_pwrCntlBypsEn 1
#define bGbl_bootStrapEn_pwrCntlBypsEn 1
#define MSK32Gbl_bootStrapEn_pwrCntlBypsEn 0x00000002
#define Gbl_bootStrapEn_pwrCntlBypsEn_ENABLE 0x1
#define Gbl_bootStrapEn_pwrCntlBypsEn_DISABLE 0x0
#define BA_Gbl_bootStrapEn_pllPwrDownEn 0x0010
#define B16Gbl_bootStrapEn_pllPwrDownEn 0x0010
#define LSb32Gbl_bootStrapEn_pllPwrDownEn 2
#define LSb16Gbl_bootStrapEn_pllPwrDownEn 2
#define bGbl_bootStrapEn_pllPwrDownEn 1
#define MSK32Gbl_bootStrapEn_pllPwrDownEn 0x00000004
#define Gbl_bootStrapEn_pllPwrDownEn_ENABLE 0x1
#define Gbl_bootStrapEn_pllPwrDownEn_DISABLE 0x0
#define BA_Gbl_bootStrapEn_sysPLLBypsEn 0x0010
#define B16Gbl_bootStrapEn_sysPLLBypsEn 0x0010
#define LSb32Gbl_bootStrapEn_sysPLLBypsEn 3
#define LSb16Gbl_bootStrapEn_sysPLLBypsEn 3
#define bGbl_bootStrapEn_sysPLLBypsEn 1
#define MSK32Gbl_bootStrapEn_sysPLLBypsEn 0x00000008
#define Gbl_bootStrapEn_sysPLLBypsEn_ENABLE 0x1
#define Gbl_bootStrapEn_sysPLLBypsEn_DISABLE 0x0
#define BA_Gbl_bootStrapEn_memPLLBypsEn 0x0010
#define B16Gbl_bootStrapEn_memPLLBypsEn 0x0010
#define LSb32Gbl_bootStrapEn_memPLLBypsEn 4
#define LSb16Gbl_bootStrapEn_memPLLBypsEn 4
#define bGbl_bootStrapEn_memPLLBypsEn 1
#define MSK32Gbl_bootStrapEn_memPLLBypsEn 0x00000010
#define Gbl_bootStrapEn_memPLLBypsEn_ENABLE 0x1
#define Gbl_bootStrapEn_memPLLBypsEn_DISABLE 0x0
#define BA_Gbl_bootStrapEn_cpuPLLBypsEn 0x0010
#define B16Gbl_bootStrapEn_cpuPLLBypsEn 0x0010
#define LSb32Gbl_bootStrapEn_cpuPLLBypsEn 5
#define LSb16Gbl_bootStrapEn_cpuPLLBypsEn 5
#define bGbl_bootStrapEn_cpuPLLBypsEn 1
#define MSK32Gbl_bootStrapEn_cpuPLLBypsEn 0x00000020
#define Gbl_bootStrapEn_cpuPLLBypsEn_ENABLE 0x1
#define Gbl_bootStrapEn_cpuPLLBypsEn_DISABLE 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_chipCntl 0x0014
#define BA_Gbl_chipCntl_SD0_CLK_LPBK_EN 0x0014
#define B16Gbl_chipCntl_SD0_CLK_LPBK_EN 0x0014
#define LSb32Gbl_chipCntl_SD0_CLK_LPBK_EN 0
#define LSb16Gbl_chipCntl_SD0_CLK_LPBK_EN 0
#define bGbl_chipCntl_SD0_CLK_LPBK_EN 1
#define MSK32Gbl_chipCntl_SD0_CLK_LPBK_EN 0x00000001
#define BA_Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x0014
#define B16Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x0014
#define LSb32Gbl_chipCntl_EMMC_CLK_LPBK_EN 1
#define LSb16Gbl_chipCntl_EMMC_CLK_LPBK_EN 1
#define bGbl_chipCntl_EMMC_CLK_LPBK_EN 1
#define MSK32Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x00000002
#define BA_Gbl_chipCntl_FE_MDIO_SEL 0x0014
#define B16Gbl_chipCntl_FE_MDIO_SEL 0x0014
#define LSb32Gbl_chipCntl_FE_MDIO_SEL 2
#define LSb16Gbl_chipCntl_FE_MDIO_SEL 2
#define bGbl_chipCntl_FE_MDIO_SEL 1
#define MSK32Gbl_chipCntl_FE_MDIO_SEL 0x00000004
#define BA_Gbl_chipCntl_eth1_PHY_SEL 0x0014
#define B16Gbl_chipCntl_eth1_PHY_SEL 0x0014
#define LSb32Gbl_chipCntl_eth1_PHY_SEL 3
#define LSb16Gbl_chipCntl_eth1_PHY_SEL 3
#define bGbl_chipCntl_eth1_PHY_SEL 1
#define MSK32Gbl_chipCntl_eth1_PHY_SEL 0x00000008
///////////////////////////////////////////////////////////
#define RA_Gbl_sw_generic0 0x0018
#define BA_Gbl_sw_generic0_swReg0 0x0018
#define B16Gbl_sw_generic0_swReg0 0x0018
#define LSb32Gbl_sw_generic0_swReg0 0
#define LSb16Gbl_sw_generic0_swReg0 0
#define bGbl_sw_generic0_swReg0 32
#define MSK32Gbl_sw_generic0_swReg0 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_sw_generic1 0x001C
#define BA_Gbl_sw_generic1_swReg1 0x001C
#define B16Gbl_sw_generic1_swReg1 0x001C
#define LSb32Gbl_sw_generic1_swReg1 0
#define LSb16Gbl_sw_generic1_swReg1 0
#define bGbl_sw_generic1_swReg1 32
#define MSK32Gbl_sw_generic1_swReg1 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_sw_generic2 0x0020
#define BA_Gbl_sw_generic2_swReg2 0x0020
#define B16Gbl_sw_generic2_swReg2 0x0020
#define LSb32Gbl_sw_generic2_swReg2 0
#define LSb16Gbl_sw_generic2_swReg2 0
#define bGbl_sw_generic2_swReg2 32
#define MSK32Gbl_sw_generic2_swReg2 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_sw_generic3 0x0024
#define BA_Gbl_sw_generic3_swReg3 0x0024
#define B16Gbl_sw_generic3_swReg3 0x0024
#define LSb32Gbl_sw_generic3_swReg3 0
#define LSb16Gbl_sw_generic3_swReg3 0
#define bGbl_sw_generic3_swReg3 32
#define MSK32Gbl_sw_generic3_swReg3 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_gfx3D31to0 0x0028
#define BA_Gbl_RWTC_gfx3D31to0_value 0x0028
#define B16Gbl_RWTC_gfx3D31to0_value 0x0028
#define LSb32Gbl_RWTC_gfx3D31to0_value 0
#define LSb16Gbl_RWTC_gfx3D31to0_value 0
#define bGbl_RWTC_gfx3D31to0_value 32
#define MSK32Gbl_RWTC_gfx3D31to0_value 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_gfx3D57to32 0x002C
#define BA_Gbl_RWTC_gfx3D57to32_value 0x002C
#define B16Gbl_RWTC_gfx3D57to32_value 0x002C
#define LSb32Gbl_RWTC_gfx3D57to32_value 0
#define LSb16Gbl_RWTC_gfx3D57to32_value 0
#define bGbl_RWTC_gfx3D57to32_value 26
#define MSK32Gbl_RWTC_gfx3D57to32_value 0x03FFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_top31to0 0x0030
#define BA_Gbl_RWTC_top31to0_value 0x0030
#define B16Gbl_RWTC_top31to0_value 0x0030
#define LSb32Gbl_RWTC_top31to0_value 0
#define LSb16Gbl_RWTC_top31to0_value 0
#define bGbl_RWTC_top31to0_value 32
#define MSK32Gbl_RWTC_top31to0_value 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_top57to32 0x0034
#define BA_Gbl_RWTC_top57to32_value 0x0034
#define B16Gbl_RWTC_top57to32_value 0x0034
#define LSb32Gbl_RWTC_top57to32_value 0
#define LSb16Gbl_RWTC_top57to32_value 0
#define bGbl_RWTC_top57to32_value 26
#define MSK32Gbl_RWTC_top57to32_value 0x03FFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_vPro31to0 0x0038
#define BA_Gbl_RWTC_vPro31to0_value 0x0038
#define B16Gbl_RWTC_vPro31to0_value 0x0038
#define LSb32Gbl_RWTC_vPro31to0_value 0
#define LSb16Gbl_RWTC_vPro31to0_value 0
#define bGbl_RWTC_vPro31to0_value 32
#define MSK32Gbl_RWTC_vPro31to0_value 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_vPro57to32 0x003C
#define BA_Gbl_RWTC_vPro57to32_value 0x003C
#define B16Gbl_RWTC_vPro57to32_value 0x003C
#define LSb32Gbl_RWTC_vPro57to32_value 0
#define LSb16Gbl_RWTC_vPro57to32_value 0
#define bGbl_RWTC_vPro57to32_value 26
#define MSK32Gbl_RWTC_vPro57to32_value 0x03FFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_g1Wrap31to0 0x0040
#define BA_Gbl_RWTC_g1Wrap31to0_value 0x0040
#define B16Gbl_RWTC_g1Wrap31to0_value 0x0040
#define LSb32Gbl_RWTC_g1Wrap31to0_value 0
#define LSb16Gbl_RWTC_g1Wrap31to0_value 0
#define bGbl_RWTC_g1Wrap31to0_value 32
#define MSK32Gbl_RWTC_g1Wrap31to0_value 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_g1Wrap57to32 0x0044
#define BA_Gbl_RWTC_g1Wrap57to32_value 0x0044
#define B16Gbl_RWTC_g1Wrap57to32_value 0x0044
#define LSb32Gbl_RWTC_g1Wrap57to32_value 0
#define LSb16Gbl_RWTC_g1Wrap57to32_value 0
#define bGbl_RWTC_g1Wrap57to32_value 26
#define MSK32Gbl_RWTC_g1Wrap57to32_value 0x03FFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_RWTC_mr7to0 0x0048
#define BA_Gbl_RWTC_mr7to0_value 0x0048
#define B16Gbl_RWTC_mr7to0_value 0x0048
#define LSb32Gbl_RWTC_mr7to0_value 0
#define LSb16Gbl_RWTC_mr7to0_value 0
#define bGbl_RWTC_mr7to0_value 8
#define MSK32Gbl_RWTC_mr7to0_value 0x000000FF
///////////////////////////////////////////////////////////
#define RA_Gbl_FPGAR 0x004C
#define BA_Gbl_FPGAR_FPGAR 0x004C
#define B16Gbl_FPGAR_FPGAR 0x004C
#define LSb32Gbl_FPGAR_FPGAR 0
#define LSb16Gbl_FPGAR_FPGAR 0
#define bGbl_FPGAR_FPGAR 32
#define MSK32Gbl_FPGAR_FPGAR 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_FPGARW 0x0050
#define BA_Gbl_FPGARW_FPGARW 0x0050
#define B16Gbl_FPGARW_FPGARW 0x0050
#define LSb32Gbl_FPGARW_FPGARW 0
#define LSb16Gbl_FPGARW_FPGARW 0
#define bGbl_FPGARW_FPGARW 32
#define MSK32Gbl_FPGARW_FPGARW 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_sysPll 0x0200
///////////////////////////////////////////////////////////
#define RA_Gbl_AVPLLB 0x0300
///////////////////////////////////////////////////////////
#define RA_Gbl_ResetTrigger 0x0600
#define BA_Gbl_ResetTrigger_chipReset 0x0600
#define B16Gbl_ResetTrigger_chipReset 0x0600
#define LSb32Gbl_ResetTrigger_chipReset 0
#define LSb16Gbl_ResetTrigger_chipReset 0
#define bGbl_ResetTrigger_chipReset 1
#define MSK32Gbl_ResetTrigger_chipReset 0x00000001
#define Gbl_ResetTrigger_chipReset_assert 0x1
#define Gbl_ResetTrigger_chipReset_deassert 0x0
#define BA_Gbl_ResetTrigger_socDdrSyncReset 0x0600
#define B16Gbl_ResetTrigger_socDdrSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_socDdrSyncReset 1
#define LSb16Gbl_ResetTrigger_socDdrSyncReset 1
#define bGbl_ResetTrigger_socDdrSyncReset 1
#define MSK32Gbl_ResetTrigger_socDdrSyncReset 0x00000002
#define Gbl_ResetTrigger_socDdrSyncReset_assert 0x1
#define Gbl_ResetTrigger_socDdrSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_avioSyncReset 0x0600
#define B16Gbl_ResetTrigger_avioSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_avioSyncReset 2
#define LSb16Gbl_ResetTrigger_avioSyncReset 2
#define bGbl_ResetTrigger_avioSyncReset 1
#define MSK32Gbl_ResetTrigger_avioSyncReset 0x00000004
#define Gbl_ResetTrigger_avioSyncReset_assert 0x1
#define Gbl_ResetTrigger_avioSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_zspSyncReset 0x0600
#define B16Gbl_ResetTrigger_zspSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_zspSyncReset 3
#define LSb16Gbl_ResetTrigger_zspSyncReset 3
#define bGbl_ResetTrigger_zspSyncReset 1
#define MSK32Gbl_ResetTrigger_zspSyncReset 0x00000008
#define Gbl_ResetTrigger_zspSyncReset_assert 0x1
#define Gbl_ResetTrigger_zspSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_perifSyncReset 0x0600
#define B16Gbl_ResetTrigger_perifSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_perifSyncReset 4
#define LSb16Gbl_ResetTrigger_perifSyncReset 4
#define bGbl_ResetTrigger_perifSyncReset 1
#define MSK32Gbl_ResetTrigger_perifSyncReset 0x00000010
#define Gbl_ResetTrigger_perifSyncReset_assert 0x1
#define Gbl_ResetTrigger_perifSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_ethSyncReset 0x0600
#define B16Gbl_ResetTrigger_ethSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_ethSyncReset 5
#define LSb16Gbl_ResetTrigger_ethSyncReset 5
#define bGbl_ResetTrigger_ethSyncReset 1
#define MSK32Gbl_ResetTrigger_ethSyncReset 0x00000020
#define Gbl_ResetTrigger_ethSyncReset_assert 0x1
#define Gbl_ResetTrigger_ethSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_ahbApbSyncReset 0x0600
#define B16Gbl_ResetTrigger_ahbApbSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_ahbApbSyncReset 6
#define LSb16Gbl_ResetTrigger_ahbApbSyncReset 6
#define bGbl_ResetTrigger_ahbApbSyncReset 1
#define MSK32Gbl_ResetTrigger_ahbApbSyncReset 0x00000040
#define Gbl_ResetTrigger_ahbApbSyncReset_assert 0x1
#define Gbl_ResetTrigger_ahbApbSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_nanfSyncReset 0x0600
#define B16Gbl_ResetTrigger_nanfSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_nanfSyncReset 7
#define LSb16Gbl_ResetTrigger_nanfSyncReset 7
#define bGbl_ResetTrigger_nanfSyncReset 1
#define MSK32Gbl_ResetTrigger_nanfSyncReset 0x00000080
#define Gbl_ResetTrigger_nanfSyncReset_assert 0x1
#define Gbl_ResetTrigger_nanfSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_usb0SyncReset 0x0601
#define B16Gbl_ResetTrigger_usb0SyncReset 0x0600
#define LSb32Gbl_ResetTrigger_usb0SyncReset 8
#define LSb16Gbl_ResetTrigger_usb0SyncReset 8
#define bGbl_ResetTrigger_usb0SyncReset 1
#define MSK32Gbl_ResetTrigger_usb0SyncReset 0x00000100
#define Gbl_ResetTrigger_usb0SyncReset_assert 0x1
#define Gbl_ResetTrigger_usb0SyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_pBridgeSyncReset 0x0601
#define B16Gbl_ResetTrigger_pBridgeSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_pBridgeSyncReset 9
#define LSb16Gbl_ResetTrigger_pBridgeSyncReset 9
#define bGbl_ResetTrigger_pBridgeSyncReset 1
#define MSK32Gbl_ResetTrigger_pBridgeSyncReset 0x00000200
#define Gbl_ResetTrigger_pBridgeSyncReset_assert 0x1
#define Gbl_ResetTrigger_pBridgeSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_sdioSyncReset 0x0601
#define B16Gbl_ResetTrigger_sdioSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_sdioSyncReset 10
#define LSb16Gbl_ResetTrigger_sdioSyncReset 10
#define bGbl_ResetTrigger_sdioSyncReset 1
#define MSK32Gbl_ResetTrigger_sdioSyncReset 0x00000400
#define Gbl_ResetTrigger_sdioSyncReset_assert 0x1
#define Gbl_ResetTrigger_sdioSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_tspSyncReset 0x0601
#define B16Gbl_ResetTrigger_tspSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_tspSyncReset 11
#define LSb16Gbl_ResetTrigger_tspSyncReset 11
#define bGbl_ResetTrigger_tspSyncReset 1
#define MSK32Gbl_ResetTrigger_tspSyncReset 0x00000800
#define Gbl_ResetTrigger_tspSyncReset_assert 0x1
#define Gbl_ResetTrigger_tspSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_v2gSyncReset 0x0601
#define B16Gbl_ResetTrigger_v2gSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_v2gSyncReset 12
#define LSb16Gbl_ResetTrigger_v2gSyncReset 12
#define bGbl_ResetTrigger_v2gSyncReset 1
#define MSK32Gbl_ResetTrigger_v2gSyncReset 0x00001000
#define Gbl_ResetTrigger_v2gSyncReset_assert 0x1
#define Gbl_ResetTrigger_v2gSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_g1SyncReset 0x0601
#define B16Gbl_ResetTrigger_g1SyncReset 0x0600
#define LSb32Gbl_ResetTrigger_g1SyncReset 13
#define LSb16Gbl_ResetTrigger_g1SyncReset 13
#define bGbl_ResetTrigger_g1SyncReset 1
#define MSK32Gbl_ResetTrigger_g1SyncReset 0x00002000
#define Gbl_ResetTrigger_g1SyncReset_assert 0x1
#define Gbl_ResetTrigger_g1SyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_bcmSyncReset 0x0601
#define B16Gbl_ResetTrigger_bcmSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_bcmSyncReset 14
#define LSb16Gbl_ResetTrigger_bcmSyncReset 14
#define bGbl_ResetTrigger_bcmSyncReset 1
#define MSK32Gbl_ResetTrigger_bcmSyncReset 0x00004000
#define Gbl_ResetTrigger_bcmSyncReset_assert 0x1
#define Gbl_ResetTrigger_bcmSyncReset_deassert 0x0
#define BA_Gbl_ResetTrigger_atbSyncReset 0x0601
#define B16Gbl_ResetTrigger_atbSyncReset 0x0600
#define LSb32Gbl_ResetTrigger_atbSyncReset 15
#define LSb16Gbl_ResetTrigger_atbSyncReset 15
#define bGbl_ResetTrigger_atbSyncReset 1
#define MSK32Gbl_ResetTrigger_atbSyncReset 0x00008000
#define Gbl_ResetTrigger_atbSyncReset_assert 0x1
#define Gbl_ResetTrigger_atbSyncReset_deassert 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_ResetStatus 0x0604
#define BA_Gbl_ResetStatus_ChipResetStatus 0x0604
#define B16Gbl_ResetStatus_ChipResetStatus 0x0604
#define LSb32Gbl_ResetStatus_ChipResetStatus 0
#define LSb16Gbl_ResetStatus_ChipResetStatus 0
#define bGbl_ResetStatus_ChipResetStatus 1
#define MSK32Gbl_ResetStatus_ChipResetStatus 0x00000001
#define Gbl_ResetStatus_ChipResetStatus_asserted 0x1
#define Gbl_ResetStatus_ChipResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_wd0Status 0x0604
#define B16Gbl_ResetStatus_wd0Status 0x0604
#define LSb32Gbl_ResetStatus_wd0Status 1
#define LSb16Gbl_ResetStatus_wd0Status 1
#define bGbl_ResetStatus_wd0Status 1
#define MSK32Gbl_ResetStatus_wd0Status 0x00000002
#define Gbl_ResetStatus_wd0Status_asserted 0x1
#define Gbl_ResetStatus_wd0Status_deasserted 0x0
#define BA_Gbl_ResetStatus_wd1Status 0x0604
#define B16Gbl_ResetStatus_wd1Status 0x0604
#define LSb32Gbl_ResetStatus_wd1Status 2
#define LSb16Gbl_ResetStatus_wd1Status 2
#define bGbl_ResetStatus_wd1Status 1
#define MSK32Gbl_ResetStatus_wd1Status 0x00000004
#define Gbl_ResetStatus_wd1Status_asserted 0x1
#define Gbl_ResetStatus_wd1Status_deasserted 0x0
#define BA_Gbl_ResetStatus_wd2Status 0x0604
#define B16Gbl_ResetStatus_wd2Status 0x0604
#define LSb32Gbl_ResetStatus_wd2Status 3
#define LSb16Gbl_ResetStatus_wd2Status 3
#define bGbl_ResetStatus_wd2Status 1
#define MSK32Gbl_ResetStatus_wd2Status 0x00000008
#define Gbl_ResetStatus_wd2Status_asserted 0x1
#define Gbl_ResetStatus_wd2Status_deasserted 0x0
#define BA_Gbl_ResetStatus_socDdrSyncResetStatus 0x0604
#define B16Gbl_ResetStatus_socDdrSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_socDdrSyncResetStatus 4
#define LSb16Gbl_ResetStatus_socDdrSyncResetStatus 4
#define bGbl_ResetStatus_socDdrSyncResetStatus 1
#define MSK32Gbl_ResetStatus_socDdrSyncResetStatus 0x00000010
#define Gbl_ResetStatus_socDdrSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_socDdrSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_avioSyncResetStatus 0x0604
#define B16Gbl_ResetStatus_avioSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_avioSyncResetStatus 5
#define LSb16Gbl_ResetStatus_avioSyncResetStatus 5
#define bGbl_ResetStatus_avioSyncResetStatus 1
#define MSK32Gbl_ResetStatus_avioSyncResetStatus 0x00000020
#define Gbl_ResetStatus_avioSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_avioSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_zspSyncResetStatus 0x0604
#define B16Gbl_ResetStatus_zspSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_zspSyncResetStatus 6
#define LSb16Gbl_ResetStatus_zspSyncResetStatus 6
#define bGbl_ResetStatus_zspSyncResetStatus 1
#define MSK32Gbl_ResetStatus_zspSyncResetStatus 0x00000040
#define Gbl_ResetStatus_zspSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_zspSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_perifSyncResetStatus 0x0604
#define B16Gbl_ResetStatus_perifSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_perifSyncResetStatus 7
#define LSb16Gbl_ResetStatus_perifSyncResetStatus 7
#define bGbl_ResetStatus_perifSyncResetStatus 1
#define MSK32Gbl_ResetStatus_perifSyncResetStatus 0x00000080
#define Gbl_ResetStatus_perifSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_perifSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_ethSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_ethSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_ethSyncResetStatus 8
#define LSb16Gbl_ResetStatus_ethSyncResetStatus 8
#define bGbl_ResetStatus_ethSyncResetStatus 1
#define MSK32Gbl_ResetStatus_ethSyncResetStatus 0x00000100
#define Gbl_ResetStatus_ethSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_ethSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_ahbApbSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_ahbApbSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_ahbApbSyncResetStatus 9
#define LSb16Gbl_ResetStatus_ahbApbSyncResetStatus 9
#define bGbl_ResetStatus_ahbApbSyncResetStatus 1
#define MSK32Gbl_ResetStatus_ahbApbSyncResetStatus 0x00000200
#define Gbl_ResetStatus_ahbApbSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_ahbApbSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_nanfSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_nanfSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_nanfSyncResetStatus 10
#define LSb16Gbl_ResetStatus_nanfSyncResetStatus 10
#define bGbl_ResetStatus_nanfSyncResetStatus 1
#define MSK32Gbl_ResetStatus_nanfSyncResetStatus 0x00000400
#define Gbl_ResetStatus_nanfSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_nanfSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_usb0SyncResetStatus 0x0605
#define B16Gbl_ResetStatus_usb0SyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_usb0SyncResetStatus 11
#define LSb16Gbl_ResetStatus_usb0SyncResetStatus 11
#define bGbl_ResetStatus_usb0SyncResetStatus 1
#define MSK32Gbl_ResetStatus_usb0SyncResetStatus 0x00000800
#define Gbl_ResetStatus_usb0SyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_usb0SyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_pBridgeSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_pBridgeSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_pBridgeSyncResetStatus 12
#define LSb16Gbl_ResetStatus_pBridgeSyncResetStatus 12
#define bGbl_ResetStatus_pBridgeSyncResetStatus 1
#define MSK32Gbl_ResetStatus_pBridgeSyncResetStatus 0x00001000
#define Gbl_ResetStatus_pBridgeSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_pBridgeSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_sdioSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_sdioSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_sdioSyncResetStatus 13
#define LSb16Gbl_ResetStatus_sdioSyncResetStatus 13
#define bGbl_ResetStatus_sdioSyncResetStatus 1
#define MSK32Gbl_ResetStatus_sdioSyncResetStatus 0x00002000
#define Gbl_ResetStatus_sdioSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_sdioSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_tspSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_tspSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_tspSyncResetStatus 14
#define LSb16Gbl_ResetStatus_tspSyncResetStatus 14
#define bGbl_ResetStatus_tspSyncResetStatus 1
#define MSK32Gbl_ResetStatus_tspSyncResetStatus 0x00004000
#define Gbl_ResetStatus_tspSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_tspSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_v2gSyncResetStatus 0x0605
#define B16Gbl_ResetStatus_v2gSyncResetStatus 0x0604
#define LSb32Gbl_ResetStatus_v2gSyncResetStatus 15
#define LSb16Gbl_ResetStatus_v2gSyncResetStatus 15
#define bGbl_ResetStatus_v2gSyncResetStatus 1
#define MSK32Gbl_ResetStatus_v2gSyncResetStatus 0x00008000
#define Gbl_ResetStatus_v2gSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_v2gSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_g1SyncResetStatus 0x0606
#define B16Gbl_ResetStatus_g1SyncResetStatus 0x0606
#define LSb32Gbl_ResetStatus_g1SyncResetStatus 16
#define LSb16Gbl_ResetStatus_g1SyncResetStatus 0
#define bGbl_ResetStatus_g1SyncResetStatus 1
#define MSK32Gbl_ResetStatus_g1SyncResetStatus 0x00010000
#define Gbl_ResetStatus_g1SyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_g1SyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_bcmSyncResetStatus 0x0606
#define B16Gbl_ResetStatus_bcmSyncResetStatus 0x0606
#define LSb32Gbl_ResetStatus_bcmSyncResetStatus 17
#define LSb16Gbl_ResetStatus_bcmSyncResetStatus 1
#define bGbl_ResetStatus_bcmSyncResetStatus 1
#define MSK32Gbl_ResetStatus_bcmSyncResetStatus 0x00020000
#define Gbl_ResetStatus_bcmSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_bcmSyncResetStatus_deasserted 0x0
#define BA_Gbl_ResetStatus_atbSyncResetStatus 0x0606
#define B16Gbl_ResetStatus_atbSyncResetStatus 0x0606
#define LSb32Gbl_ResetStatus_atbSyncResetStatus 18
#define LSb16Gbl_ResetStatus_atbSyncResetStatus 2
#define bGbl_ResetStatus_atbSyncResetStatus 1
#define MSK32Gbl_ResetStatus_atbSyncResetStatus 0x00040000
#define Gbl_ResetStatus_atbSyncResetStatus_asserted 0x1
#define Gbl_ResetStatus_atbSyncResetStatus_deasserted 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DReset 0x0608
#define BA_Gbl_gfx3DReset_SyncReset 0x0608
#define B16Gbl_gfx3DReset_SyncReset 0x0608
#define LSb32Gbl_gfx3DReset_SyncReset 0
#define LSb16Gbl_gfx3DReset_SyncReset 0
#define bGbl_gfx3DReset_SyncReset 1
#define MSK32Gbl_gfx3DReset_SyncReset 0x00000001
#define Gbl_gfx3DReset_SyncReset_assert 0x1
#define Gbl_gfx3DReset_SyncReset_deassert 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DResetStatus 0x060C
#define BA_Gbl_gfx3DResetStatus_SyncReset 0x060C
#define B16Gbl_gfx3DResetStatus_SyncReset 0x060C
#define LSb32Gbl_gfx3DResetStatus_SyncReset 0
#define LSb16Gbl_gfx3DResetStatus_SyncReset 0
#define bGbl_gfx3DResetStatus_SyncReset 1
#define MSK32Gbl_gfx3DResetStatus_SyncReset 0x00000001
#define Gbl_gfx3DResetStatus_SyncReset_assert 0x1
#define Gbl_gfx3DResetStatus_SyncReset_deassert 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_avioPwrCtrl 0x0610
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DPwrCtrl 0x0618
///////////////////////////////////////////////////////////
#define RA_Gbl_g1PwrCtrl 0x0620
///////////////////////////////////////////////////////////
#define RA_Gbl_v2gPwrCtrl 0x0628
///////////////////////////////////////////////////////////
#define RA_Gbl_clkEnable 0x0630
#define BA_Gbl_clkEnable_ethCoreClkEn 0x0630
#define B16Gbl_clkEnable_ethCoreClkEn 0x0630
#define LSb32Gbl_clkEnable_ethCoreClkEn 0
#define LSb16Gbl_clkEnable_ethCoreClkEn 0
#define bGbl_clkEnable_ethCoreClkEn 1
#define MSK32Gbl_clkEnable_ethCoreClkEn 0x00000001
#define Gbl_clkEnable_ethCoreClkEn_enable 0x1
#define Gbl_clkEnable_ethCoreClkEn_disable 0x0
#define BA_Gbl_clkEnable_ahbApbCoreClkEn 0x0630
#define B16Gbl_clkEnable_ahbApbCoreClkEn 0x0630
#define LSb32Gbl_clkEnable_ahbApbCoreClkEn 1
#define LSb16Gbl_clkEnable_ahbApbCoreClkEn 1
#define bGbl_clkEnable_ahbApbCoreClkEn 1
#define MSK32Gbl_clkEnable_ahbApbCoreClkEn 0x00000002
#define Gbl_clkEnable_ahbApbCoreClkEn_enable 0x1
#define Gbl_clkEnable_ahbApbCoreClkEn_disable 0x0
#define BA_Gbl_clkEnable_usb0CoreClkEn 0x0630
#define B16Gbl_clkEnable_usb0CoreClkEn 0x0630
#define LSb32Gbl_clkEnable_usb0CoreClkEn 2
#define LSb16Gbl_clkEnable_usb0CoreClkEn 2
#define bGbl_clkEnable_usb0CoreClkEn 1
#define MSK32Gbl_clkEnable_usb0CoreClkEn 0x00000004
#define Gbl_clkEnable_usb0CoreClkEn_enable 0x1
#define Gbl_clkEnable_usb0CoreClkEn_disable 0x0
#define BA_Gbl_clkEnable_pBridgeCoreClkEn 0x0630
#define B16Gbl_clkEnable_pBridgeCoreClkEn 0x0630
#define LSb32Gbl_clkEnable_pBridgeCoreClkEn 3
#define LSb16Gbl_clkEnable_pBridgeCoreClkEn 3
#define bGbl_clkEnable_pBridgeCoreClkEn 1
#define MSK32Gbl_clkEnable_pBridgeCoreClkEn 0x00000008
#define Gbl_clkEnable_pBridgeCoreClkEn_enable 0x1
#define Gbl_clkEnable_pBridgeCoreClkEn_disable 0x0
#define BA_Gbl_clkEnable_sdioCoreClkEn 0x0630
#define B16Gbl_clkEnable_sdioCoreClkEn 0x0630
#define LSb32Gbl_clkEnable_sdioCoreClkEn 4
#define LSb16Gbl_clkEnable_sdioCoreClkEn 4
#define bGbl_clkEnable_sdioCoreClkEn 1
#define MSK32Gbl_clkEnable_sdioCoreClkEn 0x00000010
#define Gbl_clkEnable_sdioCoreClkEn_enable 0x1
#define Gbl_clkEnable_sdioCoreClkEn_disable 0x0
#define BA_Gbl_clkEnable_nfcCoreClkEn 0x0630
#define B16Gbl_clkEnable_nfcCoreClkEn 0x0630
#define LSb32Gbl_clkEnable_nfcCoreClkEn 5
#define LSb16Gbl_clkEnable_nfcCoreClkEn 5
#define bGbl_clkEnable_nfcCoreClkEn 1
#define MSK32Gbl_clkEnable_nfcCoreClkEn 0x00000020
#define Gbl_clkEnable_nfcCoreClkEn_enable 0x1
#define Gbl_clkEnable_nfcCoreClkEn_disable 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_ClkSwitch 0x0634
#define BA_Gbl_ClkSwitch_sysPLLSWBypass 0x0634
#define B16Gbl_ClkSwitch_sysPLLSWBypass 0x0634
#define LSb32Gbl_ClkSwitch_sysPLLSWBypass 0
#define LSb16Gbl_ClkSwitch_sysPLLSWBypass 0
#define bGbl_ClkSwitch_sysPLLSWBypass 1
#define MSK32Gbl_ClkSwitch_sysPLLSWBypass 0x00000001
#define Gbl_ClkSwitch_sysPLLSWBypass_refClk 0x1
#define Gbl_ClkSwitch_sysPLLSWBypass_pllClk 0x0
#define BA_Gbl_ClkSwitch_memPLLSWBypass 0x0634
#define B16Gbl_ClkSwitch_memPLLSWBypass 0x0634
#define LSb32Gbl_ClkSwitch_memPLLSWBypass 1
#define LSb16Gbl_ClkSwitch_memPLLSWBypass 1
#define bGbl_ClkSwitch_memPLLSWBypass 1
#define MSK32Gbl_ClkSwitch_memPLLSWBypass 0x00000002
#define Gbl_ClkSwitch_memPLLSWBypass_refClk 0x1
#define Gbl_ClkSwitch_memPLLSWBypass_pllClk 0x0
#define BA_Gbl_ClkSwitch_cpuPLLSWBypass 0x0634
#define B16Gbl_ClkSwitch_cpuPLLSWBypass 0x0634
#define LSb32Gbl_ClkSwitch_cpuPLLSWBypass 2
#define LSb16Gbl_ClkSwitch_cpuPLLSWBypass 2
#define bGbl_ClkSwitch_cpuPLLSWBypass 1
#define MSK32Gbl_ClkSwitch_cpuPLLSWBypass 0x00000004
#define Gbl_ClkSwitch_cpuPLLSWBypass_refClk 0x1
#define Gbl_ClkSwitch_cpuPLLSWBypass_pllClk 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_cpufastRefClk 0x0638
///////////////////////////////////////////////////////////
#define RA_Gbl_memfastRefClk 0x063C
///////////////////////////////////////////////////////////
#define RA_Gbl_cfgClk 0x0640
///////////////////////////////////////////////////////////
#define RA_Gbl_sysClk 0x0644
///////////////////////////////////////////////////////////
#define RA_Gbl_v2gClk 0x0648
///////////////////////////////////////////////////////////
#define RA_Gbl_v2gM3Clk 0x064C
///////////////////////////////////////////////////////////
#define RA_Gbl_g1CoreClk 0x0650
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DCoreClk 0x0654
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DSysClk 0x0658
///////////////////////////////////////////////////////////
#define RA_Gbl_avioSysClk 0x065C
///////////////////////////////////////////////////////////
#define RA_Gbl_appClk 0x0660
///////////////////////////////////////////////////////////
#define RA_Gbl_vppSysClk 0x0664
///////////////////////////////////////////////////////////
#define RA_Gbl_arcRefClk 0x0668
///////////////////////////////////////////////////////////
#define RA_Gbl_hdmirxMClk 0x066C
///////////////////////////////////////////////////////////
#define RA_Gbl_perifClk 0x0670
///////////////////////////////////////////////////////////
#define RA_Gbl_zspClk 0x0674
///////////////////////////////////////////////////////////
#define RA_Gbl_tspClk 0x0678
///////////////////////////////////////////////////////////
#define RA_Gbl_tspRefClk 0x067C
///////////////////////////////////////////////////////////
#define RA_Gbl_atbClk 0x0680
///////////////////////////////////////////////////////////
#define RA_Gbl_bcmClk 0x0684
///////////////////////////////////////////////////////////
#define RA_Gbl_nfcEccClk 0x0688
///////////////////////////////////////////////////////////
#define RA_Gbl_sd0Clk 0x068C
///////////////////////////////////////////////////////////
#define RA_Gbl_usb2TestClk 0x0690
///////////////////////////////////////////////////////////
#define RA_Gbl_sdio3DllMstRefClk 0x0694
///////////////////////////////////////////////////////////
#define RA_Gbl_SECURE_SCAN_EN 0x0900
#define BA_Gbl_SECURE_SCAN_EN_SET 0x0900
#define B16Gbl_SECURE_SCAN_EN_SET 0x0900
#define LSb32Gbl_SECURE_SCAN_EN_SET 0
#define LSb16Gbl_SECURE_SCAN_EN_SET 0
#define bGbl_SECURE_SCAN_EN_SET 1
#define MSK32Gbl_SECURE_SCAN_EN_SET 0x00000001
///////////////////////////////////////////////////////////
#define RA_Gbl_NandCtrl 0x0904
#define BA_Gbl_NandCtrl_NAND_WPn_Sel 0x0904
#define B16Gbl_NandCtrl_NAND_WPn_Sel 0x0904
#define LSb32Gbl_NandCtrl_NAND_WPn_Sel 0
#define LSb16Gbl_NandCtrl_NAND_WPn_Sel 0
#define bGbl_NandCtrl_NAND_WPn_Sel 1
#define MSK32Gbl_NandCtrl_NAND_WPn_Sel 0x00000001
#define BA_Gbl_NandCtrl_NAND_CLE_OE 0x0904
#define B16Gbl_NandCtrl_NAND_CLE_OE 0x0904
#define LSb32Gbl_NandCtrl_NAND_CLE_OE 1
#define LSb16Gbl_NandCtrl_NAND_CLE_OE 1
#define bGbl_NandCtrl_NAND_CLE_OE 1
#define MSK32Gbl_NandCtrl_NAND_CLE_OE 0x00000002
#define BA_Gbl_NandCtrl_NAND_ALE_OE 0x0904
#define B16Gbl_NandCtrl_NAND_ALE_OE 0x0904
#define LSb32Gbl_NandCtrl_NAND_ALE_OE 2
#define LSb16Gbl_NandCtrl_NAND_ALE_OE 2
#define bGbl_NandCtrl_NAND_ALE_OE 1
#define MSK32Gbl_NandCtrl_NAND_ALE_OE 0x00000004
///////////////////////////////////////////////////////////
#define RA_Gbl_sdioDllMstCtrl 0x0908
#define BA_Gbl_sdioDllMstCtrl_PH_SEL1 0x0908
#define B16Gbl_sdioDllMstCtrl_PH_SEL1 0x0908
#define LSb32Gbl_sdioDllMstCtrl_PH_SEL1 0
#define LSb16Gbl_sdioDllMstCtrl_PH_SEL1 0
#define bGbl_sdioDllMstCtrl_PH_SEL1 6
#define MSK32Gbl_sdioDllMstCtrl_PH_SEL1 0x0000003F
#define BA_Gbl_sdioDllMstCtrl_PH_SEL2 0x0908
#define B16Gbl_sdioDllMstCtrl_PH_SEL2 0x0908
#define LSb32Gbl_sdioDllMstCtrl_PH_SEL2 6
#define LSb16Gbl_sdioDllMstCtrl_PH_SEL2 6
#define bGbl_sdioDllMstCtrl_PH_SEL2 6
#define MSK32Gbl_sdioDllMstCtrl_PH_SEL2 0x00000FC0
#define BA_Gbl_sdioDllMstCtrl_PH_SEL3 0x0909
#define B16Gbl_sdioDllMstCtrl_PH_SEL3 0x0908
#define LSb32Gbl_sdioDllMstCtrl_PH_SEL3 12
#define LSb16Gbl_sdioDllMstCtrl_PH_SEL3 12
#define bGbl_sdioDllMstCtrl_PH_SEL3 6
#define MSK32Gbl_sdioDllMstCtrl_PH_SEL3 0x0003F000
#define BA_Gbl_sdioDllMstCtrl_PH_SEL4 0x090A
#define B16Gbl_sdioDllMstCtrl_PH_SEL4 0x090A
#define LSb32Gbl_sdioDllMstCtrl_PH_SEL4 18
#define LSb16Gbl_sdioDllMstCtrl_PH_SEL4 2
#define bGbl_sdioDllMstCtrl_PH_SEL4 6
#define MSK32Gbl_sdioDllMstCtrl_PH_SEL4 0x00FC0000
#define BA_Gbl_sdioDllMstCtrl_RESET 0x090B
#define B16Gbl_sdioDllMstCtrl_RESET 0x090A
#define LSb32Gbl_sdioDllMstCtrl_RESET 24
#define LSb16Gbl_sdioDllMstCtrl_RESET 8
#define bGbl_sdioDllMstCtrl_RESET 1
#define MSK32Gbl_sdioDllMstCtrl_RESET 0x01000000
#define BA_Gbl_sdioDllMstCtrl_GAIN2X 0x090B
#define B16Gbl_sdioDllMstCtrl_GAIN2X 0x090A
#define LSb32Gbl_sdioDllMstCtrl_GAIN2X 25
#define LSb16Gbl_sdioDllMstCtrl_GAIN2X 9
#define bGbl_sdioDllMstCtrl_GAIN2X 1
#define MSK32Gbl_sdioDllMstCtrl_GAIN2X 0x02000000
#define BA_Gbl_sdioDllMstCtrl_TEST_EN 0x090B
#define B16Gbl_sdioDllMstCtrl_TEST_EN 0x090A
#define LSb32Gbl_sdioDllMstCtrl_TEST_EN 26
#define LSb16Gbl_sdioDllMstCtrl_TEST_EN 10
#define bGbl_sdioDllMstCtrl_TEST_EN 1
#define MSK32Gbl_sdioDllMstCtrl_TEST_EN 0x04000000
#define BA_Gbl_sdioDllMstCtrl_RESERVE 0x090B
#define B16Gbl_sdioDllMstCtrl_RESERVE 0x090A
#define LSb32Gbl_sdioDllMstCtrl_RESERVE 27
#define LSb16Gbl_sdioDllMstCtrl_RESERVE 11
#define bGbl_sdioDllMstCtrl_RESERVE 5
#define MSK32Gbl_sdioDllMstCtrl_RESERVE 0xF8000000
#define RA_Gbl_sdioDllMstCtrl1 0x090C
#define BA_Gbl_sdioDllMstCtrl_FAST_LOCK 0x090C
#define B16Gbl_sdioDllMstCtrl_FAST_LOCK 0x090C
#define LSb32Gbl_sdioDllMstCtrl_FAST_LOCK 0
#define LSb16Gbl_sdioDllMstCtrl_FAST_LOCK 0
#define bGbl_sdioDllMstCtrl_FAST_LOCK 1
#define MSK32Gbl_sdioDllMstCtrl_FAST_LOCK 0x00000001
///////////////////////////////////////////////////////////
#define RA_Gbl_sdioDllMstStatus 0x0910
#define BA_Gbl_sdioDllMstStatus_DELAY_CTRL1 0x0910
#define B16Gbl_sdioDllMstStatus_DELAY_CTRL1 0x0910
#define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL1 0
#define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL1 0
#define bGbl_sdioDllMstStatus_DELAY_CTRL1 10
#define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL1 0x000003FF
#define BA_Gbl_sdioDllMstStatus_DELAY_CTRL2 0x0911
#define B16Gbl_sdioDllMstStatus_DELAY_CTRL2 0x0910
#define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL2 10
#define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL2 10
#define bGbl_sdioDllMstStatus_DELAY_CTRL2 10
#define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL2 0x000FFC00
#define BA_Gbl_sdioDllMstStatus_DELAY_CTRL3 0x0912
#define B16Gbl_sdioDllMstStatus_DELAY_CTRL3 0x0912
#define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL3 20
#define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL3 4
#define bGbl_sdioDllMstStatus_DELAY_CTRL3 10
#define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL3 0x3FF00000
#define RA_Gbl_sdioDllMstStatus1 0x0914
#define BA_Gbl_sdioDllMstStatus_DELAY_CTRL4 0x0914
#define B16Gbl_sdioDllMstStatus_DELAY_CTRL4 0x0914
#define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL4 0
#define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL4 0
#define bGbl_sdioDllMstStatus_DELAY_CTRL4 10
#define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL4 0x000003FF
#define BA_Gbl_sdioDllMstStatus_DLL_LOCK 0x0915
#define B16Gbl_sdioDllMstStatus_DLL_LOCK 0x0914
#define LSb32Gbl_sdioDllMstStatus_DLL_LOCK 10
#define LSb16Gbl_sdioDllMstStatus_DLL_LOCK 10
#define bGbl_sdioDllMstStatus_DLL_LOCK 1
#define MSK32Gbl_sdioDllMstStatus_DLL_LOCK 0x00000400
#define BA_Gbl_sdioDllMstStatus_DELAY_OUT 0x0915
#define B16Gbl_sdioDllMstStatus_DELAY_OUT 0x0914
#define LSb32Gbl_sdioDllMstStatus_DELAY_OUT 11
#define LSb16Gbl_sdioDllMstStatus_DELAY_OUT 11
#define bGbl_sdioDllMstStatus_DELAY_OUT 10
#define MSK32Gbl_sdioDllMstStatus_DELAY_OUT 0x001FF800
///////////////////////////////////////////////////////////
#define RA_Gbl_gfx3DDisRamClkGate 0x0918
#define BA_Gbl_gfx3DDisRamClkGate_drcg 0x0918
#define B16Gbl_gfx3DDisRamClkGate_drcg 0x0918
#define LSb32Gbl_gfx3DDisRamClkGate_drcg 0
#define LSb16Gbl_gfx3DDisRamClkGate_drcg 0
#define bGbl_gfx3DDisRamClkGate_drcg 1
#define MSK32Gbl_gfx3DDisRamClkGate_drcg 0x00000001
#define Gbl_gfx3DDisRamClkGate_drcg_drcgActive 0x1
#define Gbl_gfx3DDisRamClkGate_drcg_drcgInactive 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_DroEn 0x091C
#define BA_Gbl_DroEn_Start 0x091C
#define B16Gbl_DroEn_Start 0x091C
#define LSb32Gbl_DroEn_Start 0
#define LSb16Gbl_DroEn_Start 0
#define bGbl_DroEn_Start 1
#define MSK32Gbl_DroEn_Start 0x00000001
#define Gbl_DroEn_Start_dro_en_start 0x1
#define BA_Gbl_DroEn_CountVal 0x091C
#define B16Gbl_DroEn_CountVal 0x091C
#define LSb32Gbl_DroEn_CountVal 1
#define LSb16Gbl_DroEn_CountVal 1
#define bGbl_DroEn_CountVal 16
#define MSK32Gbl_DroEn_CountVal 0x0001FFFE
#define RA_Gbl_DroEn1 0x0920
#define BA_Gbl_DroEn_WaitVal 0x0920
#define B16Gbl_DroEn_WaitVal 0x0920
#define LSb32Gbl_DroEn_WaitVal 0
#define LSb16Gbl_DroEn_WaitVal 0
#define bGbl_DroEn_WaitVal 16
#define MSK32Gbl_DroEn_WaitVal 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_DroShift 0x0924
#define BA_Gbl_DroShift_Start 0x0924
#define B16Gbl_DroShift_Start 0x0924
#define LSb32Gbl_DroShift_Start 0
#define LSb16Gbl_DroShift_Start 0
#define bGbl_DroShift_Start 1
#define MSK32Gbl_DroShift_Start 0x00000001
#define Gbl_DroShift_Start_dro_shift_start 0x1
#define BA_Gbl_DroShift_CountVal 0x0924
#define B16Gbl_DroShift_CountVal 0x0924
#define LSb32Gbl_DroShift_CountVal 1
#define LSb16Gbl_DroShift_CountVal 1
#define bGbl_DroShift_CountVal 16
#define MSK32Gbl_DroShift_CountVal 0x0001FFFE
///////////////////////////////////////////////////////////
#define RA_Gbl_DroStatus 0x0928
#define BA_Gbl_DroStatus_En 0x0928
#define B16Gbl_DroStatus_En 0x0928
#define LSb32Gbl_DroStatus_En 0
#define LSb16Gbl_DroStatus_En 0
#define bGbl_DroStatus_En 1
#define MSK32Gbl_DroStatus_En 0x00000001
#define BA_Gbl_DroStatus_Shift_Done 0x0928
#define B16Gbl_DroStatus_Shift_Done 0x0928
#define LSb32Gbl_DroStatus_Shift_Done 1
#define LSb16Gbl_DroStatus_Shift_Done 1
#define bGbl_DroStatus_Shift_Done 1
#define MSK32Gbl_DroStatus_Shift_Done 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_DroCounter 0x092C
#define BA_Gbl_DroCounter_Out 0x092C
#define B16Gbl_DroCounter_Out 0x092C
#define LSb32Gbl_DroCounter_Out 0
#define LSb16Gbl_DroCounter_Out 0
#define bGbl_DroCounter_Out 32
#define MSK32Gbl_DroCounter_Out 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_vtr 0x0930
///////////////////////////////////////////////////////////
#define RA_Gbl_gic400_ctrl 0x0938
#define BA_Gbl_gic400_ctrl_cgfsdisable 0x0938
#define B16Gbl_gic400_ctrl_cgfsdisable 0x0938
#define LSb32Gbl_gic400_ctrl_cgfsdisable 0
#define LSb16Gbl_gic400_ctrl_cgfsdisable 0
#define bGbl_gic400_ctrl_cgfsdisable 1
#define MSK32Gbl_gic400_ctrl_cgfsdisable 0x00000001
///////////////////////////////////////////////////////////
#define RA_Gbl_SPARE_CTRL_0 0x093C
#define BA_Gbl_SPARE_CTRL_0_ctrl 0x093C
#define B16Gbl_SPARE_CTRL_0_ctrl 0x093C
#define LSb32Gbl_SPARE_CTRL_0_ctrl 0
#define LSb16Gbl_SPARE_CTRL_0_ctrl 0
#define bGbl_SPARE_CTRL_0_ctrl 32
#define MSK32Gbl_SPARE_CTRL_0_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_SPARE_CTRL_1 0x0940
#define BA_Gbl_SPARE_CTRL_1_ctrl 0x0940
#define B16Gbl_SPARE_CTRL_1_ctrl 0x0940
#define LSb32Gbl_SPARE_CTRL_1_ctrl 0
#define LSb16Gbl_SPARE_CTRL_1_ctrl 0
#define bGbl_SPARE_CTRL_1_ctrl 32
#define MSK32Gbl_SPARE_CTRL_1_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_SPARE_CTRL_2 0x0944
#define BA_Gbl_SPARE_CTRL_2_ctrl 0x0944
#define B16Gbl_SPARE_CTRL_2_ctrl 0x0944
#define LSb32Gbl_SPARE_CTRL_2_ctrl 0
#define LSb16Gbl_SPARE_CTRL_2_ctrl 0
#define bGbl_SPARE_CTRL_2_ctrl 32
#define MSK32Gbl_SPARE_CTRL_2_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_SPARE_CTRL_3 0x0948
#define BA_Gbl_SPARE_CTRL_3_ctrl 0x0948
#define B16Gbl_SPARE_CTRL_3_ctrl 0x0948
#define LSb32Gbl_SPARE_CTRL_3_ctrl 0
#define LSb16Gbl_SPARE_CTRL_3_ctrl 0
#define bGbl_SPARE_CTRL_3_ctrl 32
#define MSK32Gbl_SPARE_CTRL_3_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Gbl_efuse0 0x094C
///////////////////////////////////////////////////////////
#define RA_Gbl_efuse1 0x0978
///////////////////////////////////////////////////////////
#define RA_Gbl_PERIF 0x09A4
///////////////////////////////////////////////////////////
#define RA_Gbl_PadSelect 0x4000
#define BA_Gbl_PadSelect_DVIO_OEN 0x4000
#define B16Gbl_PadSelect_DVIO_OEN 0x4000
#define LSb32Gbl_PadSelect_DVIO_OEN 0
#define LSb16Gbl_PadSelect_DVIO_OEN 0
#define bGbl_PadSelect_DVIO_OEN 1
#define MSK32Gbl_PadSelect_DVIO_OEN 0x00000001
#define Gbl_PadSelect_DVIO_OEN_Enable 0x1
#define Gbl_PadSelect_DVIO_OEN_Disable 0x0
///////////////////////////////////////////////////////////
#define RA_Gbl_I2C_PADRING 0x4004
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_PADRING 0x400C
///////////////////////////////////////////////////////////
#define RA_Gbl_TSI_PADRING 0x4014
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI_PADRING 0x401C
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_PADRING 0x4024
///////////////////////////////////////////////////////////
#define RA_Gbl_DDC_PAD_CTRL 0x402C
#define BA_Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x402C
#define B16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x402C
#define LSb32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0
#define LSb16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0
#define bGbl_DDC_PAD_CTRL_ZN_TW1_SCL 3
#define MSK32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x00000007
#define BA_Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x402C
#define B16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x402C
#define LSb32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 3
#define LSb16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 3
#define bGbl_DDC_PAD_CTRL_ZN_TW1_SDA 3
#define MSK32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x00000038
///////////////////////////////////////////////////////////
#define RA_Gbl_pinMuxCntlBus 0x8000
#define BA_Gbl_pinMuxCntlBus_URT0_RXD 0x8000
#define B16Gbl_pinMuxCntlBus_URT0_RXD 0x8000
#define LSb32Gbl_pinMuxCntlBus_URT0_RXD 0
#define LSb16Gbl_pinMuxCntlBus_URT0_RXD 0
#define bGbl_pinMuxCntlBus_URT0_RXD 3
#define MSK32Gbl_pinMuxCntlBus_URT0_RXD 0x00000007
#define Gbl_pinMuxCntlBus_URT0_RXD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_URT0_RXD_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_URT0_TXD 0x8000
#define B16Gbl_pinMuxCntlBus_URT0_TXD 0x8000
#define LSb32Gbl_pinMuxCntlBus_URT0_TXD 3
#define LSb16Gbl_pinMuxCntlBus_URT0_TXD 3
#define bGbl_pinMuxCntlBus_URT0_TXD 3
#define MSK32Gbl_pinMuxCntlBus_URT0_TXD 0x00000038
#define Gbl_pinMuxCntlBus_URT0_TXD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_URT0_TXD_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_SPI1_SS0n 0x8000
#define B16Gbl_pinMuxCntlBus_SPI1_SS0n 0x8000
#define LSb32Gbl_pinMuxCntlBus_SPI1_SS0n 6
#define LSb16Gbl_pinMuxCntlBus_SPI1_SS0n 6
#define bGbl_pinMuxCntlBus_SPI1_SS0n 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SS0n 0x000001C0
#define Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_SPI1_SS1n 0x8001
#define B16Gbl_pinMuxCntlBus_SPI1_SS1n 0x8000
#define LSb32Gbl_pinMuxCntlBus_SPI1_SS1n 9
#define LSb16Gbl_pinMuxCntlBus_SPI1_SS1n 9
#define bGbl_pinMuxCntlBus_SPI1_SS1n 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SS1n 0x00000E00
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_5 0x5
#define BA_Gbl_pinMuxCntlBus_SPI1_SS2n 0x8001
#define B16Gbl_pinMuxCntlBus_SPI1_SS2n 0x8000
#define LSb32Gbl_pinMuxCntlBus_SPI1_SS2n 12
#define LSb16Gbl_pinMuxCntlBus_SPI1_SS2n 12
#define bGbl_pinMuxCntlBus_SPI1_SS2n 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SS2n 0x00007000
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_5 0x5
#define BA_Gbl_pinMuxCntlBus_SPI1_SCLK 0x8001
#define B16Gbl_pinMuxCntlBus_SPI1_SCLK 0x8000
#define LSb32Gbl_pinMuxCntlBus_SPI1_SCLK 15
#define LSb16Gbl_pinMuxCntlBus_SPI1_SCLK 15
#define bGbl_pinMuxCntlBus_SPI1_SCLK 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SCLK 0x00038000
#define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_2 0x2
#define BA_Gbl_pinMuxCntlBus_SPI1_SDO 0x8002
#define B16Gbl_pinMuxCntlBus_SPI1_SDO 0x8002
#define LSb32Gbl_pinMuxCntlBus_SPI1_SDO 18
#define LSb16Gbl_pinMuxCntlBus_SPI1_SDO 2
#define bGbl_pinMuxCntlBus_SPI1_SDO 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SDO 0x001C0000
#define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_2 0x2
#define BA_Gbl_pinMuxCntlBus_SPI1_SDI 0x8002
#define B16Gbl_pinMuxCntlBus_SPI1_SDI 0x8002
#define LSb32Gbl_pinMuxCntlBus_SPI1_SDI 21
#define LSb16Gbl_pinMuxCntlBus_SPI1_SDI 5
#define bGbl_pinMuxCntlBus_SPI1_SDI 3
#define MSK32Gbl_pinMuxCntlBus_SPI1_SDI 0x00E00000
#define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_2 0x2
#define BA_Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x8003
#define B16Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x8002
#define LSb32Gbl_pinMuxCntlBus_USB1_DRV_VBUS 24
#define LSb16Gbl_pinMuxCntlBus_USB1_DRV_VBUS 8
#define bGbl_pinMuxCntlBus_USB1_DRV_VBUS 3
#define MSK32Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x07000000
#define Gbl_pinMuxCntlBus_USB1_DRV_VBUS_MODE_0 0x0
#define Gbl_pinMuxCntlBus_USB1_DRV_VBUS_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_TW1_SCL 0x8003
#define B16Gbl_pinMuxCntlBus_TW1_SCL 0x8002
#define LSb32Gbl_pinMuxCntlBus_TW1_SCL 27
#define LSb16Gbl_pinMuxCntlBus_TW1_SCL 11
#define bGbl_pinMuxCntlBus_TW1_SCL 3
#define MSK32Gbl_pinMuxCntlBus_TW1_SCL 0x38000000
#define Gbl_pinMuxCntlBus_TW1_SCL_MODE_0 0x0
#define Gbl_pinMuxCntlBus_TW1_SCL_MODE_1 0x1
#define Gbl_pinMuxCntlBus_TW1_SCL_MODE_2 0x2
#define RA_Gbl_pinMuxCntlBus1 0x8004
#define BA_Gbl_pinMuxCntlBus_TW1_SDA 0x8004
#define B16Gbl_pinMuxCntlBus_TW1_SDA 0x8004
#define LSb32Gbl_pinMuxCntlBus_TW1_SDA 0
#define LSb16Gbl_pinMuxCntlBus_TW1_SDA 0
#define bGbl_pinMuxCntlBus_TW1_SDA 3
#define MSK32Gbl_pinMuxCntlBus_TW1_SDA 0x00000007
#define Gbl_pinMuxCntlBus_TW1_SDA_MODE_0 0x0
#define Gbl_pinMuxCntlBus_TW1_SDA_MODE_1 0x1
#define Gbl_pinMuxCntlBus_TW1_SDA_MODE_2 0x2
#define BA_Gbl_pinMuxCntlBus_HDMI_CEC 0x8004
#define B16Gbl_pinMuxCntlBus_HDMI_CEC 0x8004
#define LSb32Gbl_pinMuxCntlBus_HDMI_CEC 3
#define LSb16Gbl_pinMuxCntlBus_HDMI_CEC 3
#define bGbl_pinMuxCntlBus_HDMI_CEC 3
#define MSK32Gbl_pinMuxCntlBus_HDMI_CEC 0x00000038
#define Gbl_pinMuxCntlBus_HDMI_CEC_MODE_0 0x0
#define Gbl_pinMuxCntlBus_HDMI_CEC_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_HDMI_HPD 0x8004
#define B16Gbl_pinMuxCntlBus_HDMI_HPD 0x8004
#define LSb32Gbl_pinMuxCntlBus_HDMI_HPD 6
#define LSb16Gbl_pinMuxCntlBus_HDMI_HPD 6
#define bGbl_pinMuxCntlBus_HDMI_HPD 3
#define MSK32Gbl_pinMuxCntlBus_HDMI_HPD 0x000001C0
#define Gbl_pinMuxCntlBus_HDMI_HPD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_HDMI_HPD_MODE_1 0x1
#define BA_Gbl_pinMuxCntlBus_NAND_IO0 0x8005
#define B16Gbl_pinMuxCntlBus_NAND_IO0 0x8004
#define LSb32Gbl_pinMuxCntlBus_NAND_IO0 9
#define LSb16Gbl_pinMuxCntlBus_NAND_IO0 9
#define bGbl_pinMuxCntlBus_NAND_IO0 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO0 0x00000E00
#define Gbl_pinMuxCntlBus_NAND_IO0_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO0_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO0_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO0_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO0_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO1 0x8005
#define B16Gbl_pinMuxCntlBus_NAND_IO1 0x8004
#define LSb32Gbl_pinMuxCntlBus_NAND_IO1 12
#define LSb16Gbl_pinMuxCntlBus_NAND_IO1 12
#define bGbl_pinMuxCntlBus_NAND_IO1 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO1 0x00007000
#define Gbl_pinMuxCntlBus_NAND_IO1_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO1_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO1_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO1_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO1_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO2 0x8005
#define B16Gbl_pinMuxCntlBus_NAND_IO2 0x8004
#define LSb32Gbl_pinMuxCntlBus_NAND_IO2 15
#define LSb16Gbl_pinMuxCntlBus_NAND_IO2 15
#define bGbl_pinMuxCntlBus_NAND_IO2 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO2 0x00038000
#define Gbl_pinMuxCntlBus_NAND_IO2_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO2_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO2_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO2_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO2_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO3 0x8006
#define B16Gbl_pinMuxCntlBus_NAND_IO3 0x8006
#define LSb32Gbl_pinMuxCntlBus_NAND_IO3 18
#define LSb16Gbl_pinMuxCntlBus_NAND_IO3 2
#define bGbl_pinMuxCntlBus_NAND_IO3 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO3 0x001C0000
#define Gbl_pinMuxCntlBus_NAND_IO3_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO3_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO3_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO3_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO3_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO4 0x8006
#define B16Gbl_pinMuxCntlBus_NAND_IO4 0x8006
#define LSb32Gbl_pinMuxCntlBus_NAND_IO4 21
#define LSb16Gbl_pinMuxCntlBus_NAND_IO4 5
#define bGbl_pinMuxCntlBus_NAND_IO4 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO4 0x00E00000
#define Gbl_pinMuxCntlBus_NAND_IO4_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO4_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO4_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO4_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO4_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO5 0x8007
#define B16Gbl_pinMuxCntlBus_NAND_IO5 0x8006
#define LSb32Gbl_pinMuxCntlBus_NAND_IO5 24
#define LSb16Gbl_pinMuxCntlBus_NAND_IO5 8
#define bGbl_pinMuxCntlBus_NAND_IO5 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO5 0x07000000
#define Gbl_pinMuxCntlBus_NAND_IO5_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO5_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO5_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO5_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO5_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_IO6 0x8007
#define B16Gbl_pinMuxCntlBus_NAND_IO6 0x8006
#define LSb32Gbl_pinMuxCntlBus_NAND_IO6 27
#define LSb16Gbl_pinMuxCntlBus_NAND_IO6 11
#define bGbl_pinMuxCntlBus_NAND_IO6 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO6 0x38000000
#define Gbl_pinMuxCntlBus_NAND_IO6_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO6_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO6_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO6_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO6_MODE_4 0x4
#define RA_Gbl_pinMuxCntlBus2 0x8008
#define BA_Gbl_pinMuxCntlBus_NAND_IO7 0x8008
#define B16Gbl_pinMuxCntlBus_NAND_IO7 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_IO7 0
#define LSb16Gbl_pinMuxCntlBus_NAND_IO7 0
#define bGbl_pinMuxCntlBus_NAND_IO7 3
#define MSK32Gbl_pinMuxCntlBus_NAND_IO7 0x00000007
#define Gbl_pinMuxCntlBus_NAND_IO7_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_IO7_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_IO7_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_IO7_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_IO7_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_ALE 0x8008
#define B16Gbl_pinMuxCntlBus_NAND_ALE 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_ALE 3
#define LSb16Gbl_pinMuxCntlBus_NAND_ALE 3
#define bGbl_pinMuxCntlBus_NAND_ALE 3
#define MSK32Gbl_pinMuxCntlBus_NAND_ALE 0x00000038
#define Gbl_pinMuxCntlBus_NAND_ALE_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_ALE_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_ALE_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_ALE_MODE_3 0x3
#define Gbl_pinMuxCntlBus_NAND_ALE_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_NAND_CLE 0x8008
#define B16Gbl_pinMuxCntlBus_NAND_CLE 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_CLE 6
#define LSb16Gbl_pinMuxCntlBus_NAND_CLE 6
#define bGbl_pinMuxCntlBus_NAND_CLE 3
#define MSK32Gbl_pinMuxCntlBus_NAND_CLE 0x000001C0
#define Gbl_pinMuxCntlBus_NAND_CLE_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_CLE_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_CLE_MODE_2 0x2
#define Gbl_pinMuxCntlBus_NAND_CLE_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_NAND_WEn 0x8009
#define B16Gbl_pinMuxCntlBus_NAND_WEn 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_WEn 9
#define LSb16Gbl_pinMuxCntlBus_NAND_WEn 9
#define bGbl_pinMuxCntlBus_NAND_WEn 3
#define MSK32Gbl_pinMuxCntlBus_NAND_WEn 0x00000E00
#define Gbl_pinMuxCntlBus_NAND_WEn_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_WEn_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_WEn_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_NAND_REn 0x8009
#define B16Gbl_pinMuxCntlBus_NAND_REn 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_REn 12
#define LSb16Gbl_pinMuxCntlBus_NAND_REn 12
#define bGbl_pinMuxCntlBus_NAND_REn 3
#define MSK32Gbl_pinMuxCntlBus_NAND_REn 0x00007000
#define Gbl_pinMuxCntlBus_NAND_REn_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_REn_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_REn_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_NAND_WPn 0x8009
#define B16Gbl_pinMuxCntlBus_NAND_WPn 0x8008
#define LSb32Gbl_pinMuxCntlBus_NAND_WPn 15
#define LSb16Gbl_pinMuxCntlBus_NAND_WPn 15
#define bGbl_pinMuxCntlBus_NAND_WPn 3
#define MSK32Gbl_pinMuxCntlBus_NAND_WPn 0x00038000
#define Gbl_pinMuxCntlBus_NAND_WPn_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_WPn_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_WPn_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_NAND_CEn 0x800A
#define B16Gbl_pinMuxCntlBus_NAND_CEn 0x800A
#define LSb32Gbl_pinMuxCntlBus_NAND_CEn 18
#define LSb16Gbl_pinMuxCntlBus_NAND_CEn 2
#define bGbl_pinMuxCntlBus_NAND_CEn 3
#define MSK32Gbl_pinMuxCntlBus_NAND_CEn 0x001C0000
#define Gbl_pinMuxCntlBus_NAND_CEn_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_CEn_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_CEn_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_NAND_RDY 0x800A
#define B16Gbl_pinMuxCntlBus_NAND_RDY 0x800A
#define LSb32Gbl_pinMuxCntlBus_NAND_RDY 21
#define LSb16Gbl_pinMuxCntlBus_NAND_RDY 5
#define bGbl_pinMuxCntlBus_NAND_RDY 3
#define MSK32Gbl_pinMuxCntlBus_NAND_RDY 0x00E00000
#define Gbl_pinMuxCntlBus_NAND_RDY_MODE_0 0x0
#define Gbl_pinMuxCntlBus_NAND_RDY_MODE_1 0x1
#define Gbl_pinMuxCntlBus_NAND_RDY_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_SD0_CLK 0x800B
#define B16Gbl_pinMuxCntlBus_SD0_CLK 0x800A
#define LSb32Gbl_pinMuxCntlBus_SD0_CLK 24
#define LSb16Gbl_pinMuxCntlBus_SD0_CLK 8
#define bGbl_pinMuxCntlBus_SD0_CLK 3
#define MSK32Gbl_pinMuxCntlBus_SD0_CLK 0x07000000
#define Gbl_pinMuxCntlBus_SD0_CLK_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_CLK_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_CLK_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_CLK_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_DAT0 0x800B
#define B16Gbl_pinMuxCntlBus_SD0_DAT0 0x800A
#define LSb32Gbl_pinMuxCntlBus_SD0_DAT0 27
#define LSb16Gbl_pinMuxCntlBus_SD0_DAT0 11
#define bGbl_pinMuxCntlBus_SD0_DAT0 3
#define MSK32Gbl_pinMuxCntlBus_SD0_DAT0 0x38000000
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_7 0x7
#define RA_Gbl_pinMuxCntlBus3 0x800C
#define BA_Gbl_pinMuxCntlBus_SD0_DAT1 0x800C
#define B16Gbl_pinMuxCntlBus_SD0_DAT1 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_DAT1 0
#define LSb16Gbl_pinMuxCntlBus_SD0_DAT1 0
#define bGbl_pinMuxCntlBus_SD0_DAT1 3
#define MSK32Gbl_pinMuxCntlBus_SD0_DAT1 0x00000007
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_DAT2 0x800C
#define B16Gbl_pinMuxCntlBus_SD0_DAT2 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_DAT2 3
#define LSb16Gbl_pinMuxCntlBus_SD0_DAT2 3
#define bGbl_pinMuxCntlBus_SD0_DAT2 3
#define MSK32Gbl_pinMuxCntlBus_SD0_DAT2 0x00000038
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_DAT3 0x800C
#define B16Gbl_pinMuxCntlBus_SD0_DAT3 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_DAT3 6
#define LSb16Gbl_pinMuxCntlBus_SD0_DAT3 6
#define bGbl_pinMuxCntlBus_SD0_DAT3 3
#define MSK32Gbl_pinMuxCntlBus_SD0_DAT3 0x000001C0
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_CDn 0x800D
#define B16Gbl_pinMuxCntlBus_SD0_CDn 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_CDn 9
#define LSb16Gbl_pinMuxCntlBus_SD0_CDn 9
#define bGbl_pinMuxCntlBus_SD0_CDn 3
#define MSK32Gbl_pinMuxCntlBus_SD0_CDn 0x00000E00
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_CDn_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_CMD 0x800D
#define B16Gbl_pinMuxCntlBus_SD0_CMD 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_CMD 12
#define LSb16Gbl_pinMuxCntlBus_SD0_CMD 12
#define bGbl_pinMuxCntlBus_SD0_CMD 3
#define MSK32Gbl_pinMuxCntlBus_SD0_CMD 0x00007000
#define Gbl_pinMuxCntlBus_SD0_CMD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_CMD_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_CMD_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_CMD_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_SD0_WP 0x800D
#define B16Gbl_pinMuxCntlBus_SD0_WP 0x800C
#define LSb32Gbl_pinMuxCntlBus_SD0_WP 15
#define LSb16Gbl_pinMuxCntlBus_SD0_WP 15
#define bGbl_pinMuxCntlBus_SD0_WP 3
#define MSK32Gbl_pinMuxCntlBus_SD0_WP 0x00038000
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_0 0x0
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_1 0x1
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_2 0x2
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_3 0x3
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_4 0x4
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_5 0x5
#define Gbl_pinMuxCntlBus_SD0_WP_MODE_7 0x7
#define BA_Gbl_pinMuxCntlBus_STS0_CLK 0x800E
#define B16Gbl_pinMuxCntlBus_STS0_CLK 0x800E
#define LSb32Gbl_pinMuxCntlBus_STS0_CLK 18
#define LSb16Gbl_pinMuxCntlBus_STS0_CLK 2
#define bGbl_pinMuxCntlBus_STS0_CLK 3
#define MSK32Gbl_pinMuxCntlBus_STS0_CLK 0x001C0000
#define Gbl_pinMuxCntlBus_STS0_CLK_MODE_0 0x0
#define Gbl_pinMuxCntlBus_STS0_CLK_MODE_1 0x1
#define Gbl_pinMuxCntlBus_STS0_CLK_MODE_2 0x2
#define Gbl_pinMuxCntlBus_STS0_CLK_MODE_4 0x4
#define BA_Gbl_pinMuxCntlBus_STS0_SOP 0x800E
#define B16Gbl_pinMuxCntlBus_STS0_SOP 0x800E
#define LSb32Gbl_pinMuxCntlBus_STS0_SOP 21
#define LSb16Gbl_pinMuxCntlBus_STS0_SOP 5
#define bGbl_pinMuxCntlBus_STS0_SOP 3
#define MSK32Gbl_pinMuxCntlBus_STS0_SOP 0x00E00000
#define Gbl_pinMuxCntlBus_STS0_SOP_MODE_0 0x0
#define Gbl_pinMuxCntlBus_STS0_SOP_MODE_1 0x1
#define Gbl_pinMuxCntlBus_STS0_SOP_MODE_2 0x2
#define BA_Gbl_pinMuxCntlBus_STS0_VALD 0x800F
#define B16Gbl_pinMuxCntlBus_STS0_VALD 0x800E
#define LSb32Gbl_pinMuxCntlBus_STS0_VALD 24
#define LSb16Gbl_pinMuxCntlBus_STS0_VALD 8
#define bGbl_pinMuxCntlBus_STS0_VALD 3
#define MSK32Gbl_pinMuxCntlBus_STS0_VALD 0x07000000
#define Gbl_pinMuxCntlBus_STS0_VALD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_STS0_VALD_MODE_1 0x1
#define Gbl_pinMuxCntlBus_STS0_VALD_MODE_2 0x2
#define Gbl_pinMuxCntlBus_STS0_VALD_MODE_3 0x3
#define BA_Gbl_pinMuxCntlBus_STS0_SD 0x800F
#define B16Gbl_pinMuxCntlBus_STS0_SD 0x800E
#define LSb32Gbl_pinMuxCntlBus_STS0_SD 27
#define LSb16Gbl_pinMuxCntlBus_STS0_SD 11
#define bGbl_pinMuxCntlBus_STS0_SD 3
#define MSK32Gbl_pinMuxCntlBus_STS0_SD 0x38000000
#define Gbl_pinMuxCntlBus_STS0_SD_MODE_0 0x0
#define Gbl_pinMuxCntlBus_STS0_SD_MODE_1 0x1
#define Gbl_pinMuxCntlBus_STS0_SD_MODE_2 0x2
#define Gbl_pinMuxCntlBus_STS0_SD_MODE_3 0x3
///////////////////////////////////////////////////////////
#define RA_Gbl_URT0_RXDCntl 0x8010
#define BA_Gbl_URT0_RXDCntl_PD_EN 0x8010
#define B16Gbl_URT0_RXDCntl_PD_EN 0x8010
#define LSb32Gbl_URT0_RXDCntl_PD_EN 0
#define LSb16Gbl_URT0_RXDCntl_PD_EN 0
#define bGbl_URT0_RXDCntl_PD_EN 1
#define MSK32Gbl_URT0_RXDCntl_PD_EN 0x00000001
#define BA_Gbl_URT0_RXDCntl_PU_EN 0x8010
#define B16Gbl_URT0_RXDCntl_PU_EN 0x8010
#define LSb32Gbl_URT0_RXDCntl_PU_EN 1
#define LSb16Gbl_URT0_RXDCntl_PU_EN 1
#define bGbl_URT0_RXDCntl_PU_EN 1
#define MSK32Gbl_URT0_RXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_URT0_TXDCntl 0x8014
#define BA_Gbl_URT0_TXDCntl_PD_EN 0x8014
#define B16Gbl_URT0_TXDCntl_PD_EN 0x8014
#define LSb32Gbl_URT0_TXDCntl_PD_EN 0
#define LSb16Gbl_URT0_TXDCntl_PD_EN 0
#define bGbl_URT0_TXDCntl_PD_EN 1
#define MSK32Gbl_URT0_TXDCntl_PD_EN 0x00000001
#define BA_Gbl_URT0_TXDCntl_PU_EN 0x8014
#define B16Gbl_URT0_TXDCntl_PU_EN 0x8014
#define LSb32Gbl_URT0_TXDCntl_PU_EN 1
#define LSb16Gbl_URT0_TXDCntl_PU_EN 1
#define bGbl_URT0_TXDCntl_PU_EN 1
#define MSK32Gbl_URT0_TXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SS0nCntl 0x8018
#define BA_Gbl_SPI1_SS0nCntl_PD_EN 0x8018
#define B16Gbl_SPI1_SS0nCntl_PD_EN 0x8018
#define LSb32Gbl_SPI1_SS0nCntl_PD_EN 0
#define LSb16Gbl_SPI1_SS0nCntl_PD_EN 0
#define bGbl_SPI1_SS0nCntl_PD_EN 1
#define MSK32Gbl_SPI1_SS0nCntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SS0nCntl_PU_EN 0x8018
#define B16Gbl_SPI1_SS0nCntl_PU_EN 0x8018
#define LSb32Gbl_SPI1_SS0nCntl_PU_EN 1
#define LSb16Gbl_SPI1_SS0nCntl_PU_EN 1
#define bGbl_SPI1_SS0nCntl_PU_EN 1
#define MSK32Gbl_SPI1_SS0nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SS1nCntl 0x801C
#define BA_Gbl_SPI1_SS1nCntl_PD_EN 0x801C
#define B16Gbl_SPI1_SS1nCntl_PD_EN 0x801C
#define LSb32Gbl_SPI1_SS1nCntl_PD_EN 0
#define LSb16Gbl_SPI1_SS1nCntl_PD_EN 0
#define bGbl_SPI1_SS1nCntl_PD_EN 1
#define MSK32Gbl_SPI1_SS1nCntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SS1nCntl_PU_EN 0x801C
#define B16Gbl_SPI1_SS1nCntl_PU_EN 0x801C
#define LSb32Gbl_SPI1_SS1nCntl_PU_EN 1
#define LSb16Gbl_SPI1_SS1nCntl_PU_EN 1
#define bGbl_SPI1_SS1nCntl_PU_EN 1
#define MSK32Gbl_SPI1_SS1nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SS2nCntl 0x8020
#define BA_Gbl_SPI1_SS2nCntl_PD_EN 0x8020
#define B16Gbl_SPI1_SS2nCntl_PD_EN 0x8020
#define LSb32Gbl_SPI1_SS2nCntl_PD_EN 0
#define LSb16Gbl_SPI1_SS2nCntl_PD_EN 0
#define bGbl_SPI1_SS2nCntl_PD_EN 1
#define MSK32Gbl_SPI1_SS2nCntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SS2nCntl_PU_EN 0x8020
#define B16Gbl_SPI1_SS2nCntl_PU_EN 0x8020
#define LSb32Gbl_SPI1_SS2nCntl_PU_EN 1
#define LSb16Gbl_SPI1_SS2nCntl_PU_EN 1
#define bGbl_SPI1_SS2nCntl_PU_EN 1
#define MSK32Gbl_SPI1_SS2nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SCLKCntl 0x8024
#define BA_Gbl_SPI1_SCLKCntl_PD_EN 0x8024
#define B16Gbl_SPI1_SCLKCntl_PD_EN 0x8024
#define LSb32Gbl_SPI1_SCLKCntl_PD_EN 0
#define LSb16Gbl_SPI1_SCLKCntl_PD_EN 0
#define bGbl_SPI1_SCLKCntl_PD_EN 1
#define MSK32Gbl_SPI1_SCLKCntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SCLKCntl_PU_EN 0x8024
#define B16Gbl_SPI1_SCLKCntl_PU_EN 0x8024
#define LSb32Gbl_SPI1_SCLKCntl_PU_EN 1
#define LSb16Gbl_SPI1_SCLKCntl_PU_EN 1
#define bGbl_SPI1_SCLKCntl_PU_EN 1
#define MSK32Gbl_SPI1_SCLKCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SDOCntl 0x8028
#define BA_Gbl_SPI1_SDOCntl_PD_EN 0x8028
#define B16Gbl_SPI1_SDOCntl_PD_EN 0x8028
#define LSb32Gbl_SPI1_SDOCntl_PD_EN 0
#define LSb16Gbl_SPI1_SDOCntl_PD_EN 0
#define bGbl_SPI1_SDOCntl_PD_EN 1
#define MSK32Gbl_SPI1_SDOCntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SDOCntl_PU_EN 0x8028
#define B16Gbl_SPI1_SDOCntl_PU_EN 0x8028
#define LSb32Gbl_SPI1_SDOCntl_PU_EN 1
#define LSb16Gbl_SPI1_SDOCntl_PU_EN 1
#define bGbl_SPI1_SDOCntl_PU_EN 1
#define MSK32Gbl_SPI1_SDOCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SPI1_SDICntl 0x802C
#define BA_Gbl_SPI1_SDICntl_PD_EN 0x802C
#define B16Gbl_SPI1_SDICntl_PD_EN 0x802C
#define LSb32Gbl_SPI1_SDICntl_PD_EN 0
#define LSb16Gbl_SPI1_SDICntl_PD_EN 0
#define bGbl_SPI1_SDICntl_PD_EN 1
#define MSK32Gbl_SPI1_SDICntl_PD_EN 0x00000001
#define BA_Gbl_SPI1_SDICntl_PU_EN 0x802C
#define B16Gbl_SPI1_SDICntl_PU_EN 0x802C
#define LSb32Gbl_SPI1_SDICntl_PU_EN 1
#define LSb16Gbl_SPI1_SDICntl_PU_EN 1
#define bGbl_SPI1_SDICntl_PU_EN 1
#define MSK32Gbl_SPI1_SDICntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_USB1_DRV_VBUSCntl 0x8030
#define BA_Gbl_USB1_DRV_VBUSCntl_PD_EN 0x8030
#define B16Gbl_USB1_DRV_VBUSCntl_PD_EN 0x8030
#define LSb32Gbl_USB1_DRV_VBUSCntl_PD_EN 0
#define LSb16Gbl_USB1_DRV_VBUSCntl_PD_EN 0
#define bGbl_USB1_DRV_VBUSCntl_PD_EN 1
#define MSK32Gbl_USB1_DRV_VBUSCntl_PD_EN 0x00000001
#define BA_Gbl_USB1_DRV_VBUSCntl_PU_EN 0x8030
#define B16Gbl_USB1_DRV_VBUSCntl_PU_EN 0x8030
#define LSb32Gbl_USB1_DRV_VBUSCntl_PU_EN 1
#define LSb16Gbl_USB1_DRV_VBUSCntl_PU_EN 1
#define bGbl_USB1_DRV_VBUSCntl_PU_EN 1
#define MSK32Gbl_USB1_DRV_VBUSCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO0Cntl 0x8034
#define BA_Gbl_NAND_IO0Cntl_PD_EN 0x8034
#define B16Gbl_NAND_IO0Cntl_PD_EN 0x8034
#define LSb32Gbl_NAND_IO0Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO0Cntl_PD_EN 0
#define bGbl_NAND_IO0Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO0Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO0Cntl_PU_EN 0x8034
#define B16Gbl_NAND_IO0Cntl_PU_EN 0x8034
#define LSb32Gbl_NAND_IO0Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO0Cntl_PU_EN 1
#define bGbl_NAND_IO0Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO0Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO1Cntl 0x8038
#define BA_Gbl_NAND_IO1Cntl_PD_EN 0x8038
#define B16Gbl_NAND_IO1Cntl_PD_EN 0x8038
#define LSb32Gbl_NAND_IO1Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO1Cntl_PD_EN 0
#define bGbl_NAND_IO1Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO1Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO1Cntl_PU_EN 0x8038
#define B16Gbl_NAND_IO1Cntl_PU_EN 0x8038
#define LSb32Gbl_NAND_IO1Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO1Cntl_PU_EN 1
#define bGbl_NAND_IO1Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO1Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO2Cntl 0x803C
#define BA_Gbl_NAND_IO2Cntl_PD_EN 0x803C
#define B16Gbl_NAND_IO2Cntl_PD_EN 0x803C
#define LSb32Gbl_NAND_IO2Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO2Cntl_PD_EN 0
#define bGbl_NAND_IO2Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO2Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO2Cntl_PU_EN 0x803C
#define B16Gbl_NAND_IO2Cntl_PU_EN 0x803C
#define LSb32Gbl_NAND_IO2Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO2Cntl_PU_EN 1
#define bGbl_NAND_IO2Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO2Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO3Cntl 0x8040
#define BA_Gbl_NAND_IO3Cntl_PD_EN 0x8040
#define B16Gbl_NAND_IO3Cntl_PD_EN 0x8040
#define LSb32Gbl_NAND_IO3Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO3Cntl_PD_EN 0
#define bGbl_NAND_IO3Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO3Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO3Cntl_PU_EN 0x8040
#define B16Gbl_NAND_IO3Cntl_PU_EN 0x8040
#define LSb32Gbl_NAND_IO3Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO3Cntl_PU_EN 1
#define bGbl_NAND_IO3Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO3Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO4Cntl 0x8044
#define BA_Gbl_NAND_IO4Cntl_PD_EN 0x8044
#define B16Gbl_NAND_IO4Cntl_PD_EN 0x8044
#define LSb32Gbl_NAND_IO4Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO4Cntl_PD_EN 0
#define bGbl_NAND_IO4Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO4Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO4Cntl_PU_EN 0x8044
#define B16Gbl_NAND_IO4Cntl_PU_EN 0x8044
#define LSb32Gbl_NAND_IO4Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO4Cntl_PU_EN 1
#define bGbl_NAND_IO4Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO4Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO5Cntl 0x8048
#define BA_Gbl_NAND_IO5Cntl_PD_EN 0x8048
#define B16Gbl_NAND_IO5Cntl_PD_EN 0x8048
#define LSb32Gbl_NAND_IO5Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO5Cntl_PD_EN 0
#define bGbl_NAND_IO5Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO5Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO5Cntl_PU_EN 0x8048
#define B16Gbl_NAND_IO5Cntl_PU_EN 0x8048
#define LSb32Gbl_NAND_IO5Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO5Cntl_PU_EN 1
#define bGbl_NAND_IO5Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO5Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO6Cntl 0x804C
#define BA_Gbl_NAND_IO6Cntl_PD_EN 0x804C
#define B16Gbl_NAND_IO6Cntl_PD_EN 0x804C
#define LSb32Gbl_NAND_IO6Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO6Cntl_PD_EN 0
#define bGbl_NAND_IO6Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO6Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO6Cntl_PU_EN 0x804C
#define B16Gbl_NAND_IO6Cntl_PU_EN 0x804C
#define LSb32Gbl_NAND_IO6Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO6Cntl_PU_EN 1
#define bGbl_NAND_IO6Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO6Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_IO7Cntl 0x8050
#define BA_Gbl_NAND_IO7Cntl_PD_EN 0x8050
#define B16Gbl_NAND_IO7Cntl_PD_EN 0x8050
#define LSb32Gbl_NAND_IO7Cntl_PD_EN 0
#define LSb16Gbl_NAND_IO7Cntl_PD_EN 0
#define bGbl_NAND_IO7Cntl_PD_EN 1
#define MSK32Gbl_NAND_IO7Cntl_PD_EN 0x00000001
#define BA_Gbl_NAND_IO7Cntl_PU_EN 0x8050
#define B16Gbl_NAND_IO7Cntl_PU_EN 0x8050
#define LSb32Gbl_NAND_IO7Cntl_PU_EN 1
#define LSb16Gbl_NAND_IO7Cntl_PU_EN 1
#define bGbl_NAND_IO7Cntl_PU_EN 1
#define MSK32Gbl_NAND_IO7Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_ALECntl 0x8054
#define BA_Gbl_NAND_ALECntl_PD_EN 0x8054
#define B16Gbl_NAND_ALECntl_PD_EN 0x8054
#define LSb32Gbl_NAND_ALECntl_PD_EN 0
#define LSb16Gbl_NAND_ALECntl_PD_EN 0
#define bGbl_NAND_ALECntl_PD_EN 1
#define MSK32Gbl_NAND_ALECntl_PD_EN 0x00000001
#define BA_Gbl_NAND_ALECntl_PU_EN 0x8054
#define B16Gbl_NAND_ALECntl_PU_EN 0x8054
#define LSb32Gbl_NAND_ALECntl_PU_EN 1
#define LSb16Gbl_NAND_ALECntl_PU_EN 1
#define bGbl_NAND_ALECntl_PU_EN 1
#define MSK32Gbl_NAND_ALECntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_CLECntl 0x8058
#define BA_Gbl_NAND_CLECntl_PD_EN 0x8058
#define B16Gbl_NAND_CLECntl_PD_EN 0x8058
#define LSb32Gbl_NAND_CLECntl_PD_EN 0
#define LSb16Gbl_NAND_CLECntl_PD_EN 0
#define bGbl_NAND_CLECntl_PD_EN 1
#define MSK32Gbl_NAND_CLECntl_PD_EN 0x00000001
#define BA_Gbl_NAND_CLECntl_PU_EN 0x8058
#define B16Gbl_NAND_CLECntl_PU_EN 0x8058
#define LSb32Gbl_NAND_CLECntl_PU_EN 1
#define LSb16Gbl_NAND_CLECntl_PU_EN 1
#define bGbl_NAND_CLECntl_PU_EN 1
#define MSK32Gbl_NAND_CLECntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_WEnCntl 0x805C
#define BA_Gbl_NAND_WEnCntl_PD_EN 0x805C
#define B16Gbl_NAND_WEnCntl_PD_EN 0x805C
#define LSb32Gbl_NAND_WEnCntl_PD_EN 0
#define LSb16Gbl_NAND_WEnCntl_PD_EN 0
#define bGbl_NAND_WEnCntl_PD_EN 1
#define MSK32Gbl_NAND_WEnCntl_PD_EN 0x00000001
#define BA_Gbl_NAND_WEnCntl_PU_EN 0x805C
#define B16Gbl_NAND_WEnCntl_PU_EN 0x805C
#define LSb32Gbl_NAND_WEnCntl_PU_EN 1
#define LSb16Gbl_NAND_WEnCntl_PU_EN 1
#define bGbl_NAND_WEnCntl_PU_EN 1
#define MSK32Gbl_NAND_WEnCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_REnCntl 0x8060
#define BA_Gbl_NAND_REnCntl_PD_EN 0x8060
#define B16Gbl_NAND_REnCntl_PD_EN 0x8060
#define LSb32Gbl_NAND_REnCntl_PD_EN 0
#define LSb16Gbl_NAND_REnCntl_PD_EN 0
#define bGbl_NAND_REnCntl_PD_EN 1
#define MSK32Gbl_NAND_REnCntl_PD_EN 0x00000001
#define BA_Gbl_NAND_REnCntl_PU_EN 0x8060
#define B16Gbl_NAND_REnCntl_PU_EN 0x8060
#define LSb32Gbl_NAND_REnCntl_PU_EN 1
#define LSb16Gbl_NAND_REnCntl_PU_EN 1
#define bGbl_NAND_REnCntl_PU_EN 1
#define MSK32Gbl_NAND_REnCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_WPnCntl 0x8064
#define BA_Gbl_NAND_WPnCntl_PD_EN 0x8064
#define B16Gbl_NAND_WPnCntl_PD_EN 0x8064
#define LSb32Gbl_NAND_WPnCntl_PD_EN 0
#define LSb16Gbl_NAND_WPnCntl_PD_EN 0
#define bGbl_NAND_WPnCntl_PD_EN 1
#define MSK32Gbl_NAND_WPnCntl_PD_EN 0x00000001
#define BA_Gbl_NAND_WPnCntl_PU_EN 0x8064
#define B16Gbl_NAND_WPnCntl_PU_EN 0x8064
#define LSb32Gbl_NAND_WPnCntl_PU_EN 1
#define LSb16Gbl_NAND_WPnCntl_PU_EN 1
#define bGbl_NAND_WPnCntl_PU_EN 1
#define MSK32Gbl_NAND_WPnCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_CEnCntl 0x8068
#define BA_Gbl_NAND_CEnCntl_PD_EN 0x8068
#define B16Gbl_NAND_CEnCntl_PD_EN 0x8068
#define LSb32Gbl_NAND_CEnCntl_PD_EN 0
#define LSb16Gbl_NAND_CEnCntl_PD_EN 0
#define bGbl_NAND_CEnCntl_PD_EN 1
#define MSK32Gbl_NAND_CEnCntl_PD_EN 0x00000001
#define BA_Gbl_NAND_CEnCntl_PU_EN 0x8068
#define B16Gbl_NAND_CEnCntl_PU_EN 0x8068
#define LSb32Gbl_NAND_CEnCntl_PU_EN 1
#define LSb16Gbl_NAND_CEnCntl_PU_EN 1
#define bGbl_NAND_CEnCntl_PU_EN 1
#define MSK32Gbl_NAND_CEnCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_NAND_RDYCntl 0x806C
#define BA_Gbl_NAND_RDYCntl_PD_EN 0x806C
#define B16Gbl_NAND_RDYCntl_PD_EN 0x806C
#define LSb32Gbl_NAND_RDYCntl_PD_EN 0
#define LSb16Gbl_NAND_RDYCntl_PD_EN 0
#define bGbl_NAND_RDYCntl_PD_EN 1
#define MSK32Gbl_NAND_RDYCntl_PD_EN 0x00000001
#define BA_Gbl_NAND_RDYCntl_PU_EN 0x806C
#define B16Gbl_NAND_RDYCntl_PU_EN 0x806C
#define LSb32Gbl_NAND_RDYCntl_PU_EN 1
#define LSb16Gbl_NAND_RDYCntl_PU_EN 1
#define bGbl_NAND_RDYCntl_PU_EN 1
#define MSK32Gbl_NAND_RDYCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_CLKCntl 0x8070
#define BA_Gbl_SD0_CLKCntl_PD_EN 0x8070
#define B16Gbl_SD0_CLKCntl_PD_EN 0x8070
#define LSb32Gbl_SD0_CLKCntl_PD_EN 0
#define LSb16Gbl_SD0_CLKCntl_PD_EN 0
#define bGbl_SD0_CLKCntl_PD_EN 1
#define MSK32Gbl_SD0_CLKCntl_PD_EN 0x00000001
#define BA_Gbl_SD0_CLKCntl_PU_EN 0x8070
#define B16Gbl_SD0_CLKCntl_PU_EN 0x8070
#define LSb32Gbl_SD0_CLKCntl_PU_EN 1
#define LSb16Gbl_SD0_CLKCntl_PU_EN 1
#define bGbl_SD0_CLKCntl_PU_EN 1
#define MSK32Gbl_SD0_CLKCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_DAT0Cntl 0x8074
#define BA_Gbl_SD0_DAT0Cntl_PD_EN 0x8074
#define B16Gbl_SD0_DAT0Cntl_PD_EN 0x8074
#define LSb32Gbl_SD0_DAT0Cntl_PD_EN 0
#define LSb16Gbl_SD0_DAT0Cntl_PD_EN 0
#define bGbl_SD0_DAT0Cntl_PD_EN 1
#define MSK32Gbl_SD0_DAT0Cntl_PD_EN 0x00000001
#define BA_Gbl_SD0_DAT0Cntl_PU_EN 0x8074
#define B16Gbl_SD0_DAT0Cntl_PU_EN 0x8074
#define LSb32Gbl_SD0_DAT0Cntl_PU_EN 1
#define LSb16Gbl_SD0_DAT0Cntl_PU_EN 1
#define bGbl_SD0_DAT0Cntl_PU_EN 1
#define MSK32Gbl_SD0_DAT0Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_DAT1Cntl 0x8078
#define BA_Gbl_SD0_DAT1Cntl_PD_EN 0x8078
#define B16Gbl_SD0_DAT1Cntl_PD_EN 0x8078
#define LSb32Gbl_SD0_DAT1Cntl_PD_EN 0
#define LSb16Gbl_SD0_DAT1Cntl_PD_EN 0
#define bGbl_SD0_DAT1Cntl_PD_EN 1
#define MSK32Gbl_SD0_DAT1Cntl_PD_EN 0x00000001
#define BA_Gbl_SD0_DAT1Cntl_PU_EN 0x8078
#define B16Gbl_SD0_DAT1Cntl_PU_EN 0x8078
#define LSb32Gbl_SD0_DAT1Cntl_PU_EN 1
#define LSb16Gbl_SD0_DAT1Cntl_PU_EN 1
#define bGbl_SD0_DAT1Cntl_PU_EN 1
#define MSK32Gbl_SD0_DAT1Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_DAT2Cntl 0x807C
#define BA_Gbl_SD0_DAT2Cntl_PD_EN 0x807C
#define B16Gbl_SD0_DAT2Cntl_PD_EN 0x807C
#define LSb32Gbl_SD0_DAT2Cntl_PD_EN 0
#define LSb16Gbl_SD0_DAT2Cntl_PD_EN 0
#define bGbl_SD0_DAT2Cntl_PD_EN 1
#define MSK32Gbl_SD0_DAT2Cntl_PD_EN 0x00000001
#define BA_Gbl_SD0_DAT2Cntl_PU_EN 0x807C
#define B16Gbl_SD0_DAT2Cntl_PU_EN 0x807C
#define LSb32Gbl_SD0_DAT2Cntl_PU_EN 1
#define LSb16Gbl_SD0_DAT2Cntl_PU_EN 1
#define bGbl_SD0_DAT2Cntl_PU_EN 1
#define MSK32Gbl_SD0_DAT2Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_DAT3Cntl 0x8080
#define BA_Gbl_SD0_DAT3Cntl_PD_EN 0x8080
#define B16Gbl_SD0_DAT3Cntl_PD_EN 0x8080
#define LSb32Gbl_SD0_DAT3Cntl_PD_EN 0
#define LSb16Gbl_SD0_DAT3Cntl_PD_EN 0
#define bGbl_SD0_DAT3Cntl_PD_EN 1
#define MSK32Gbl_SD0_DAT3Cntl_PD_EN 0x00000001
#define BA_Gbl_SD0_DAT3Cntl_PU_EN 0x8080
#define B16Gbl_SD0_DAT3Cntl_PU_EN 0x8080
#define LSb32Gbl_SD0_DAT3Cntl_PU_EN 1
#define LSb16Gbl_SD0_DAT3Cntl_PU_EN 1
#define bGbl_SD0_DAT3Cntl_PU_EN 1
#define MSK32Gbl_SD0_DAT3Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_CDnCntl 0x8084
#define BA_Gbl_SD0_CDnCntl_PD_EN 0x8084
#define B16Gbl_SD0_CDnCntl_PD_EN 0x8084
#define LSb32Gbl_SD0_CDnCntl_PD_EN 0
#define LSb16Gbl_SD0_CDnCntl_PD_EN 0
#define bGbl_SD0_CDnCntl_PD_EN 1
#define MSK32Gbl_SD0_CDnCntl_PD_EN 0x00000001
#define BA_Gbl_SD0_CDnCntl_PU_EN 0x8084
#define B16Gbl_SD0_CDnCntl_PU_EN 0x8084
#define LSb32Gbl_SD0_CDnCntl_PU_EN 1
#define LSb16Gbl_SD0_CDnCntl_PU_EN 1
#define bGbl_SD0_CDnCntl_PU_EN 1
#define MSK32Gbl_SD0_CDnCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_CMDCntl 0x8088
#define BA_Gbl_SD0_CMDCntl_PD_EN 0x8088
#define B16Gbl_SD0_CMDCntl_PD_EN 0x8088
#define LSb32Gbl_SD0_CMDCntl_PD_EN 0
#define LSb16Gbl_SD0_CMDCntl_PD_EN 0
#define bGbl_SD0_CMDCntl_PD_EN 1
#define MSK32Gbl_SD0_CMDCntl_PD_EN 0x00000001
#define BA_Gbl_SD0_CMDCntl_PU_EN 0x8088
#define B16Gbl_SD0_CMDCntl_PU_EN 0x8088
#define LSb32Gbl_SD0_CMDCntl_PU_EN 1
#define LSb16Gbl_SD0_CMDCntl_PU_EN 1
#define bGbl_SD0_CMDCntl_PU_EN 1
#define MSK32Gbl_SD0_CMDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_SD0_WPCntl 0x808C
#define BA_Gbl_SD0_WPCntl_PD_EN 0x808C
#define B16Gbl_SD0_WPCntl_PD_EN 0x808C
#define LSb32Gbl_SD0_WPCntl_PD_EN 0
#define LSb16Gbl_SD0_WPCntl_PD_EN 0
#define bGbl_SD0_WPCntl_PD_EN 1
#define MSK32Gbl_SD0_WPCntl_PD_EN 0x00000001
#define BA_Gbl_SD0_WPCntl_PU_EN 0x808C
#define B16Gbl_SD0_WPCntl_PU_EN 0x808C
#define LSb32Gbl_SD0_WPCntl_PU_EN 1
#define LSb16Gbl_SD0_WPCntl_PU_EN 1
#define bGbl_SD0_WPCntl_PU_EN 1
#define MSK32Gbl_SD0_WPCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_STS0_CLKCntl 0x8090
#define BA_Gbl_STS0_CLKCntl_PD_EN 0x8090
#define B16Gbl_STS0_CLKCntl_PD_EN 0x8090
#define LSb32Gbl_STS0_CLKCntl_PD_EN 0
#define LSb16Gbl_STS0_CLKCntl_PD_EN 0
#define bGbl_STS0_CLKCntl_PD_EN 1
#define MSK32Gbl_STS0_CLKCntl_PD_EN 0x00000001
#define BA_Gbl_STS0_CLKCntl_PU_EN 0x8090
#define B16Gbl_STS0_CLKCntl_PU_EN 0x8090
#define LSb32Gbl_STS0_CLKCntl_PU_EN 1
#define LSb16Gbl_STS0_CLKCntl_PU_EN 1
#define bGbl_STS0_CLKCntl_PU_EN 1
#define MSK32Gbl_STS0_CLKCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_STS0_SOPCntl 0x8094
#define BA_Gbl_STS0_SOPCntl_PD_EN 0x8094
#define B16Gbl_STS0_SOPCntl_PD_EN 0x8094
#define LSb32Gbl_STS0_SOPCntl_PD_EN 0
#define LSb16Gbl_STS0_SOPCntl_PD_EN 0
#define bGbl_STS0_SOPCntl_PD_EN 1
#define MSK32Gbl_STS0_SOPCntl_PD_EN 0x00000001
#define BA_Gbl_STS0_SOPCntl_PU_EN 0x8094
#define B16Gbl_STS0_SOPCntl_PU_EN 0x8094
#define LSb32Gbl_STS0_SOPCntl_PU_EN 1
#define LSb16Gbl_STS0_SOPCntl_PU_EN 1
#define bGbl_STS0_SOPCntl_PU_EN 1
#define MSK32Gbl_STS0_SOPCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_STS0_VALDCntl 0x8098
#define BA_Gbl_STS0_VALDCntl_PD_EN 0x8098
#define B16Gbl_STS0_VALDCntl_PD_EN 0x8098
#define LSb32Gbl_STS0_VALDCntl_PD_EN 0
#define LSb16Gbl_STS0_VALDCntl_PD_EN 0
#define bGbl_STS0_VALDCntl_PD_EN 1
#define MSK32Gbl_STS0_VALDCntl_PD_EN 0x00000001
#define BA_Gbl_STS0_VALDCntl_PU_EN 0x8098
#define B16Gbl_STS0_VALDCntl_PU_EN 0x8098
#define LSb32Gbl_STS0_VALDCntl_PU_EN 1
#define LSb16Gbl_STS0_VALDCntl_PU_EN 1
#define bGbl_STS0_VALDCntl_PU_EN 1
#define MSK32Gbl_STS0_VALDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_Gbl_STS0_SDCntl 0x809C
#define BA_Gbl_STS0_SDCntl_PD_EN 0x809C
#define B16Gbl_STS0_SDCntl_PD_EN 0x809C
#define LSb32Gbl_STS0_SDCntl_PD_EN 0
#define LSb16Gbl_STS0_SDCntl_PD_EN 0
#define bGbl_STS0_SDCntl_PD_EN 1
#define MSK32Gbl_STS0_SDCntl_PD_EN 0x00000001
#define BA_Gbl_STS0_SDCntl_PU_EN 0x809C
#define B16Gbl_STS0_SDCntl_PU_EN 0x809C
#define LSb32Gbl_STS0_SDCntl_PU_EN 1
#define LSb16Gbl_STS0_SDCntl_PU_EN 1
#define bGbl_STS0_SDCntl_PU_EN 1
#define MSK32Gbl_STS0_SDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_Gbl {
///////////////////////////////////////////////////////////
#define GET32Gbl_ProductId_Id(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_ProductId_Id(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_ProductId {\
UNSG32 uProductId_Id : 32;\
}
union { UNSG32 u32Gbl_ProductId;
struct w32Gbl_ProductId;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_ProductId_ext_ID_EXT(r32) _BFGET_(r32, 7, 0)
#define SET32Gbl_ProductId_ext_ID_EXT(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Gbl_ProductId_ext_ID_EXT(r16) _BFGET_(r16, 7, 0)
#define SET16Gbl_ProductId_ext_ID_EXT(r16,v) _BFSET_(r16, 7, 0,v)
#define w32Gbl_ProductId_ext {\
UNSG32 uProductId_ext_ID_EXT : 8;\
UNSG32 RSVDx4_b8 : 24;\
}
union { UNSG32 u32Gbl_ProductId_ext;
struct w32Gbl_ProductId_ext;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_INT_ID_VALUE(r32) _BFGET_(r32, 7, 0)
#define SET32Gbl_INT_ID_VALUE(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Gbl_INT_ID_VALUE(r16) _BFGET_(r16, 7, 0)
#define SET16Gbl_INT_ID_VALUE(r16,v) _BFSET_(r16, 7, 0,v)
#define w32Gbl_INT_ID {\
UNSG32 uINT_ID_VALUE : 8;\
UNSG32 RSVDx8_b8 : 24;\
}
union { UNSG32 u32Gbl_INT_ID;
struct w32Gbl_INT_ID;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_bootStrap_softwareStrap(r32) _BFGET_(r32, 1, 0)
#define SET32Gbl_bootStrap_softwareStrap(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16Gbl_bootStrap_softwareStrap(r16) _BFGET_(r16, 1, 0)
#define SET16Gbl_bootStrap_softwareStrap(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32Gbl_bootStrap_bootSrc(r32) _BFGET_(r32, 3, 2)
#define SET32Gbl_bootStrap_bootSrc(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16Gbl_bootStrap_bootSrc(r16) _BFGET_(r16, 3, 2)
#define SET16Gbl_bootStrap_bootSrc(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32Gbl_bootStrap_cpuRstByps(r32) _BFGET_(r32, 4, 4)
#define SET32Gbl_bootStrap_cpuRstByps(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Gbl_bootStrap_cpuRstByps(r16) _BFGET_(r16, 4, 4)
#define SET16Gbl_bootStrap_cpuRstByps(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Gbl_bootStrap_pwrCntlByps(r32) _BFGET_(r32, 5, 5)
#define SET32Gbl_bootStrap_pwrCntlByps(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Gbl_bootStrap_pwrCntlByps(r16) _BFGET_(r16, 5, 5)
#define SET16Gbl_bootStrap_pwrCntlByps(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Gbl_bootStrap_pllPwrDown(r32) _BFGET_(r32, 6, 6)
#define SET32Gbl_bootStrap_pllPwrDown(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Gbl_bootStrap_pllPwrDown(r16) _BFGET_(r16, 6, 6)
#define SET16Gbl_bootStrap_pllPwrDown(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32Gbl_bootStrap_sysPllByps(r32) _BFGET_(r32, 7, 7)
#define SET32Gbl_bootStrap_sysPllByps(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16Gbl_bootStrap_sysPllByps(r16) _BFGET_(r16, 7, 7)
#define SET16Gbl_bootStrap_sysPllByps(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32Gbl_bootStrap_memPllByps(r32) _BFGET_(r32, 8, 8)
#define SET32Gbl_bootStrap_memPllByps(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Gbl_bootStrap_memPllByps(r16) _BFGET_(r16, 8, 8)
#define SET16Gbl_bootStrap_memPllByps(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Gbl_bootStrap_cpuPllByps(r32) _BFGET_(r32, 9, 9)
#define SET32Gbl_bootStrap_cpuPllByps(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Gbl_bootStrap_cpuPllByps(r16) _BFGET_(r16, 9, 9)
#define SET16Gbl_bootStrap_cpuPllByps(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Gbl_bootStrap_nandV18Enable(r32) _BFGET_(r32,10,10)
#define SET32Gbl_bootStrap_nandV18Enable(r32,v) _BFSET_(r32,10,10,v)
#define GET16Gbl_bootStrap_nandV18Enable(r16) _BFGET_(r16,10,10)
#define SET16Gbl_bootStrap_nandV18Enable(r16,v) _BFSET_(r16,10,10,v)
#define GET32Gbl_bootStrap_dftStrap(r32) _BFGET_(r32,11,11)
#define SET32Gbl_bootStrap_dftStrap(r32,v) _BFSET_(r32,11,11,v)
#define GET16Gbl_bootStrap_dftStrap(r16) _BFGET_(r16,11,11)
#define SET16Gbl_bootStrap_dftStrap(r16,v) _BFSET_(r16,11,11,v)
#define GET32Gbl_bootStrap_ENG_EN(r32) _BFGET_(r32,12,12)
#define SET32Gbl_bootStrap_ENG_EN(r32,v) _BFSET_(r32,12,12,v)
#define GET16Gbl_bootStrap_ENG_EN(r16) _BFGET_(r16,12,12)
#define SET16Gbl_bootStrap_ENG_EN(r16,v) _BFSET_(r16,12,12,v)
#define w32Gbl_bootStrap {\
UNSG32 ubootStrap_softwareStrap : 2;\
UNSG32 ubootStrap_bootSrc : 2;\
UNSG32 ubootStrap_cpuRstByps : 1;\
UNSG32 ubootStrap_pwrCntlByps : 1;\
UNSG32 ubootStrap_pllPwrDown : 1;\
UNSG32 ubootStrap_sysPllByps : 1;\
UNSG32 ubootStrap_memPllByps : 1;\
UNSG32 ubootStrap_cpuPllByps : 1;\
UNSG32 ubootStrap_nandV18Enable : 1;\
UNSG32 ubootStrap_dftStrap : 1;\
UNSG32 ubootStrap_ENG_EN : 1;\
UNSG32 RSVDxC_b13 : 19;\
}
union { UNSG32 u32Gbl_bootStrap;
struct w32Gbl_bootStrap;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_bootStrapEn_cpuRstBypsEn(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_bootStrapEn_cpuRstBypsEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_bootStrapEn_cpuRstBypsEn(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_bootStrapEn_cpuRstBypsEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_bootStrapEn_pwrCntlBypsEn(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_bootStrapEn_pwrCntlBypsEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_bootStrapEn_pwrCntlBypsEn(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_bootStrapEn_pwrCntlBypsEn(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_bootStrapEn_pllPwrDownEn(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_bootStrapEn_pllPwrDownEn(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_bootStrapEn_pllPwrDownEn(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_bootStrapEn_pllPwrDownEn(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Gbl_bootStrapEn_sysPLLBypsEn(r32) _BFGET_(r32, 3, 3)
#define SET32Gbl_bootStrapEn_sysPLLBypsEn(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Gbl_bootStrapEn_sysPLLBypsEn(r16) _BFGET_(r16, 3, 3)
#define SET16Gbl_bootStrapEn_sysPLLBypsEn(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Gbl_bootStrapEn_memPLLBypsEn(r32) _BFGET_(r32, 4, 4)
#define SET32Gbl_bootStrapEn_memPLLBypsEn(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Gbl_bootStrapEn_memPLLBypsEn(r16) _BFGET_(r16, 4, 4)
#define SET16Gbl_bootStrapEn_memPLLBypsEn(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Gbl_bootStrapEn_cpuPLLBypsEn(r32) _BFGET_(r32, 5, 5)
#define SET32Gbl_bootStrapEn_cpuPLLBypsEn(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Gbl_bootStrapEn_cpuPLLBypsEn(r16) _BFGET_(r16, 5, 5)
#define SET16Gbl_bootStrapEn_cpuPLLBypsEn(r16,v) _BFSET_(r16, 5, 5,v)
#define w32Gbl_bootStrapEn {\
UNSG32 ubootStrapEn_cpuRstBypsEn : 1;\
UNSG32 ubootStrapEn_pwrCntlBypsEn : 1;\
UNSG32 ubootStrapEn_pllPwrDownEn : 1;\
UNSG32 ubootStrapEn_sysPLLBypsEn : 1;\
UNSG32 ubootStrapEn_memPLLBypsEn : 1;\
UNSG32 ubootStrapEn_cpuPLLBypsEn : 1;\
UNSG32 RSVDx10_b6 : 26;\
}
union { UNSG32 u32Gbl_bootStrapEn;
struct w32Gbl_bootStrapEn;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_chipCntl_SD0_CLK_LPBK_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_chipCntl_SD0_CLK_LPBK_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_chipCntl_SD0_CLK_LPBK_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_chipCntl_SD0_CLK_LPBK_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_chipCntl_EMMC_CLK_LPBK_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_chipCntl_EMMC_CLK_LPBK_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_chipCntl_EMMC_CLK_LPBK_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_chipCntl_EMMC_CLK_LPBK_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_chipCntl_FE_MDIO_SEL(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_chipCntl_FE_MDIO_SEL(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_chipCntl_FE_MDIO_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_chipCntl_FE_MDIO_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Gbl_chipCntl_eth1_PHY_SEL(r32) _BFGET_(r32, 3, 3)
#define SET32Gbl_chipCntl_eth1_PHY_SEL(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Gbl_chipCntl_eth1_PHY_SEL(r16) _BFGET_(r16, 3, 3)
#define SET16Gbl_chipCntl_eth1_PHY_SEL(r16,v) _BFSET_(r16, 3, 3,v)
#define w32Gbl_chipCntl {\
UNSG32 uchipCntl_SD0_CLK_LPBK_EN : 1;\
UNSG32 uchipCntl_EMMC_CLK_LPBK_EN : 1;\
UNSG32 uchipCntl_FE_MDIO_SEL : 1;\
UNSG32 uchipCntl_eth1_PHY_SEL : 1;\
UNSG32 RSVDx14_b4 : 28;\
}
union { UNSG32 u32Gbl_chipCntl;
struct w32Gbl_chipCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sw_generic0_swReg0(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_sw_generic0_swReg0(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_sw_generic0 {\
UNSG32 usw_generic0_swReg0 : 32;\
}
union { UNSG32 u32Gbl_sw_generic0;
struct w32Gbl_sw_generic0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sw_generic1_swReg1(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_sw_generic1_swReg1(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_sw_generic1 {\
UNSG32 usw_generic1_swReg1 : 32;\
}
union { UNSG32 u32Gbl_sw_generic1;
struct w32Gbl_sw_generic1;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sw_generic2_swReg2(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_sw_generic2_swReg2(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_sw_generic2 {\
UNSG32 usw_generic2_swReg2 : 32;\
}
union { UNSG32 u32Gbl_sw_generic2;
struct w32Gbl_sw_generic2;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sw_generic3_swReg3(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_sw_generic3_swReg3(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_sw_generic3 {\
UNSG32 usw_generic3_swReg3 : 32;\
}
union { UNSG32 u32Gbl_sw_generic3;
struct w32Gbl_sw_generic3;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_gfx3D31to0_value(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_RWTC_gfx3D31to0_value(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_RWTC_gfx3D31to0 {\
UNSG32 uRWTC_gfx3D31to0_value : 32;\
}
union { UNSG32 u32Gbl_RWTC_gfx3D31to0;
struct w32Gbl_RWTC_gfx3D31to0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_gfx3D57to32_value(r32) _BFGET_(r32,25, 0)
#define SET32Gbl_RWTC_gfx3D57to32_value(r32,v) _BFSET_(r32,25, 0,v)
#define w32Gbl_RWTC_gfx3D57to32 {\
UNSG32 uRWTC_gfx3D57to32_value : 26;\
UNSG32 RSVDx2C_b26 : 6;\
}
union { UNSG32 u32Gbl_RWTC_gfx3D57to32;
struct w32Gbl_RWTC_gfx3D57to32;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_top31to0_value(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_RWTC_top31to0_value(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_RWTC_top31to0 {\
UNSG32 uRWTC_top31to0_value : 32;\
}
union { UNSG32 u32Gbl_RWTC_top31to0;
struct w32Gbl_RWTC_top31to0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_top57to32_value(r32) _BFGET_(r32,25, 0)
#define SET32Gbl_RWTC_top57to32_value(r32,v) _BFSET_(r32,25, 0,v)
#define w32Gbl_RWTC_top57to32 {\
UNSG32 uRWTC_top57to32_value : 26;\
UNSG32 RSVDx34_b26 : 6;\
}
union { UNSG32 u32Gbl_RWTC_top57to32;
struct w32Gbl_RWTC_top57to32;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_vPro31to0_value(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_RWTC_vPro31to0_value(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_RWTC_vPro31to0 {\
UNSG32 uRWTC_vPro31to0_value : 32;\
}
union { UNSG32 u32Gbl_RWTC_vPro31to0;
struct w32Gbl_RWTC_vPro31to0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_vPro57to32_value(r32) _BFGET_(r32,25, 0)
#define SET32Gbl_RWTC_vPro57to32_value(r32,v) _BFSET_(r32,25, 0,v)
#define w32Gbl_RWTC_vPro57to32 {\
UNSG32 uRWTC_vPro57to32_value : 26;\
UNSG32 RSVDx3C_b26 : 6;\
}
union { UNSG32 u32Gbl_RWTC_vPro57to32;
struct w32Gbl_RWTC_vPro57to32;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_g1Wrap31to0_value(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_RWTC_g1Wrap31to0_value(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_RWTC_g1Wrap31to0 {\
UNSG32 uRWTC_g1Wrap31to0_value : 32;\
}
union { UNSG32 u32Gbl_RWTC_g1Wrap31to0;
struct w32Gbl_RWTC_g1Wrap31to0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_g1Wrap57to32_value(r32) _BFGET_(r32,25, 0)
#define SET32Gbl_RWTC_g1Wrap57to32_value(r32,v) _BFSET_(r32,25, 0,v)
#define w32Gbl_RWTC_g1Wrap57to32 {\
UNSG32 uRWTC_g1Wrap57to32_value : 26;\
UNSG32 RSVDx44_b26 : 6;\
}
union { UNSG32 u32Gbl_RWTC_g1Wrap57to32;
struct w32Gbl_RWTC_g1Wrap57to32;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_RWTC_mr7to0_value(r32) _BFGET_(r32, 7, 0)
#define SET32Gbl_RWTC_mr7to0_value(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Gbl_RWTC_mr7to0_value(r16) _BFGET_(r16, 7, 0)
#define SET16Gbl_RWTC_mr7to0_value(r16,v) _BFSET_(r16, 7, 0,v)
#define w32Gbl_RWTC_mr7to0 {\
UNSG32 uRWTC_mr7to0_value : 8;\
UNSG32 RSVDx48_b8 : 24;\
}
union { UNSG32 u32Gbl_RWTC_mr7to0;
struct w32Gbl_RWTC_mr7to0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_FPGAR_FPGAR(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_FPGAR_FPGAR(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_FPGAR {\
UNSG32 uFPGAR_FPGAR : 32;\
}
union { UNSG32 u32Gbl_FPGAR;
struct w32Gbl_FPGAR;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_FPGARW_FPGARW(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_FPGARW_FPGARW(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_FPGARW {\
UNSG32 uFPGARW_FPGARW : 32;\
}
union { UNSG32 u32Gbl_FPGARW;
struct w32Gbl_FPGARW;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDx54 [428];
///////////////////////////////////////////////////////////
SIE_pll ie_sysPll;
///////////////////////////////////////////////////////////
UNSG8 RSVDx218 [232];
///////////////////////////////////////////////////////////
SIE_avPll ie_AVPLLB;
///////////////////////////////////////////////////////////
UNSG8 RSVDx3A8 [600];
///////////////////////////////////////////////////////////
#define GET32Gbl_ResetTrigger_chipReset(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_ResetTrigger_chipReset(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_ResetTrigger_chipReset(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_ResetTrigger_chipReset(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_ResetTrigger_socDdrSyncReset(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_ResetTrigger_socDdrSyncReset(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_ResetTrigger_socDdrSyncReset(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_ResetTrigger_socDdrSyncReset(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_ResetTrigger_avioSyncReset(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_ResetTrigger_avioSyncReset(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_ResetTrigger_avioSyncReset(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_ResetTrigger_avioSyncReset(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Gbl_ResetTrigger_zspSyncReset(r32) _BFGET_(r32, 3, 3)
#define SET32Gbl_ResetTrigger_zspSyncReset(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Gbl_ResetTrigger_zspSyncReset(r16) _BFGET_(r16, 3, 3)
#define SET16Gbl_ResetTrigger_zspSyncReset(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Gbl_ResetTrigger_perifSyncReset(r32) _BFGET_(r32, 4, 4)
#define SET32Gbl_ResetTrigger_perifSyncReset(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Gbl_ResetTrigger_perifSyncReset(r16) _BFGET_(r16, 4, 4)
#define SET16Gbl_ResetTrigger_perifSyncReset(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Gbl_ResetTrigger_ethSyncReset(r32) _BFGET_(r32, 5, 5)
#define SET32Gbl_ResetTrigger_ethSyncReset(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Gbl_ResetTrigger_ethSyncReset(r16) _BFGET_(r16, 5, 5)
#define SET16Gbl_ResetTrigger_ethSyncReset(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Gbl_ResetTrigger_ahbApbSyncReset(r32) _BFGET_(r32, 6, 6)
#define SET32Gbl_ResetTrigger_ahbApbSyncReset(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Gbl_ResetTrigger_ahbApbSyncReset(r16) _BFGET_(r16, 6, 6)
#define SET16Gbl_ResetTrigger_ahbApbSyncReset(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32Gbl_ResetTrigger_nanfSyncReset(r32) _BFGET_(r32, 7, 7)
#define SET32Gbl_ResetTrigger_nanfSyncReset(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16Gbl_ResetTrigger_nanfSyncReset(r16) _BFGET_(r16, 7, 7)
#define SET16Gbl_ResetTrigger_nanfSyncReset(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32Gbl_ResetTrigger_usb0SyncReset(r32) _BFGET_(r32, 8, 8)
#define SET32Gbl_ResetTrigger_usb0SyncReset(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Gbl_ResetTrigger_usb0SyncReset(r16) _BFGET_(r16, 8, 8)
#define SET16Gbl_ResetTrigger_usb0SyncReset(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Gbl_ResetTrigger_pBridgeSyncReset(r32) _BFGET_(r32, 9, 9)
#define SET32Gbl_ResetTrigger_pBridgeSyncReset(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Gbl_ResetTrigger_pBridgeSyncReset(r16) _BFGET_(r16, 9, 9)
#define SET16Gbl_ResetTrigger_pBridgeSyncReset(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Gbl_ResetTrigger_sdioSyncReset(r32) _BFGET_(r32,10,10)
#define SET32Gbl_ResetTrigger_sdioSyncReset(r32,v) _BFSET_(r32,10,10,v)
#define GET16Gbl_ResetTrigger_sdioSyncReset(r16) _BFGET_(r16,10,10)
#define SET16Gbl_ResetTrigger_sdioSyncReset(r16,v) _BFSET_(r16,10,10,v)
#define GET32Gbl_ResetTrigger_tspSyncReset(r32) _BFGET_(r32,11,11)
#define SET32Gbl_ResetTrigger_tspSyncReset(r32,v) _BFSET_(r32,11,11,v)
#define GET16Gbl_ResetTrigger_tspSyncReset(r16) _BFGET_(r16,11,11)
#define SET16Gbl_ResetTrigger_tspSyncReset(r16,v) _BFSET_(r16,11,11,v)
#define GET32Gbl_ResetTrigger_v2gSyncReset(r32) _BFGET_(r32,12,12)
#define SET32Gbl_ResetTrigger_v2gSyncReset(r32,v) _BFSET_(r32,12,12,v)
#define GET16Gbl_ResetTrigger_v2gSyncReset(r16) _BFGET_(r16,12,12)
#define SET16Gbl_ResetTrigger_v2gSyncReset(r16,v) _BFSET_(r16,12,12,v)
#define GET32Gbl_ResetTrigger_g1SyncReset(r32) _BFGET_(r32,13,13)
#define SET32Gbl_ResetTrigger_g1SyncReset(r32,v) _BFSET_(r32,13,13,v)
#define GET16Gbl_ResetTrigger_g1SyncReset(r16) _BFGET_(r16,13,13)
#define SET16Gbl_ResetTrigger_g1SyncReset(r16,v) _BFSET_(r16,13,13,v)
#define GET32Gbl_ResetTrigger_bcmSyncReset(r32) _BFGET_(r32,14,14)
#define SET32Gbl_ResetTrigger_bcmSyncReset(r32,v) _BFSET_(r32,14,14,v)
#define GET16Gbl_ResetTrigger_bcmSyncReset(r16) _BFGET_(r16,14,14)
#define SET16Gbl_ResetTrigger_bcmSyncReset(r16,v) _BFSET_(r16,14,14,v)
#define GET32Gbl_ResetTrigger_atbSyncReset(r32) _BFGET_(r32,15,15)
#define SET32Gbl_ResetTrigger_atbSyncReset(r32,v) _BFSET_(r32,15,15,v)
#define GET16Gbl_ResetTrigger_atbSyncReset(r16) _BFGET_(r16,15,15)
#define SET16Gbl_ResetTrigger_atbSyncReset(r16,v) _BFSET_(r16,15,15,v)
#define w32Gbl_ResetTrigger {\
UNSG32 uResetTrigger_chipReset : 1;\
UNSG32 uResetTrigger_socDdrSyncReset : 1;\
UNSG32 uResetTrigger_avioSyncReset : 1;\
UNSG32 uResetTrigger_zspSyncReset : 1;\
UNSG32 uResetTrigger_perifSyncReset : 1;\
UNSG32 uResetTrigger_ethSyncReset : 1;\
UNSG32 uResetTrigger_ahbApbSyncReset : 1;\
UNSG32 uResetTrigger_nanfSyncReset : 1;\
UNSG32 uResetTrigger_usb0SyncReset : 1;\
UNSG32 uResetTrigger_pBridgeSyncReset : 1;\
UNSG32 uResetTrigger_sdioSyncReset : 1;\
UNSG32 uResetTrigger_tspSyncReset : 1;\
UNSG32 uResetTrigger_v2gSyncReset : 1;\
UNSG32 uResetTrigger_g1SyncReset : 1;\
UNSG32 uResetTrigger_bcmSyncReset : 1;\
UNSG32 uResetTrigger_atbSyncReset : 1;\
UNSG32 RSVDx600_b16 : 16;\
}
union { UNSG32 u32Gbl_ResetTrigger;
struct w32Gbl_ResetTrigger;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_ResetStatus_ChipResetStatus(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_ResetStatus_ChipResetStatus(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_ResetStatus_ChipResetStatus(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_ResetStatus_ChipResetStatus(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_ResetStatus_wd0Status(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_ResetStatus_wd0Status(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_ResetStatus_wd0Status(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_ResetStatus_wd0Status(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_ResetStatus_wd1Status(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_ResetStatus_wd1Status(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_ResetStatus_wd1Status(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_ResetStatus_wd1Status(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Gbl_ResetStatus_wd2Status(r32) _BFGET_(r32, 3, 3)
#define SET32Gbl_ResetStatus_wd2Status(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Gbl_ResetStatus_wd2Status(r16) _BFGET_(r16, 3, 3)
#define SET16Gbl_ResetStatus_wd2Status(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Gbl_ResetStatus_socDdrSyncResetStatus(r32) _BFGET_(r32, 4, 4)
#define SET32Gbl_ResetStatus_socDdrSyncResetStatus(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Gbl_ResetStatus_socDdrSyncResetStatus(r16) _BFGET_(r16, 4, 4)
#define SET16Gbl_ResetStatus_socDdrSyncResetStatus(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Gbl_ResetStatus_avioSyncResetStatus(r32) _BFGET_(r32, 5, 5)
#define SET32Gbl_ResetStatus_avioSyncResetStatus(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Gbl_ResetStatus_avioSyncResetStatus(r16) _BFGET_(r16, 5, 5)
#define SET16Gbl_ResetStatus_avioSyncResetStatus(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Gbl_ResetStatus_zspSyncResetStatus(r32) _BFGET_(r32, 6, 6)
#define SET32Gbl_ResetStatus_zspSyncResetStatus(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Gbl_ResetStatus_zspSyncResetStatus(r16) _BFGET_(r16, 6, 6)
#define SET16Gbl_ResetStatus_zspSyncResetStatus(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32Gbl_ResetStatus_perifSyncResetStatus(r32) _BFGET_(r32, 7, 7)
#define SET32Gbl_ResetStatus_perifSyncResetStatus(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16Gbl_ResetStatus_perifSyncResetStatus(r16) _BFGET_(r16, 7, 7)
#define SET16Gbl_ResetStatus_perifSyncResetStatus(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32Gbl_ResetStatus_ethSyncResetStatus(r32) _BFGET_(r32, 8, 8)
#define SET32Gbl_ResetStatus_ethSyncResetStatus(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Gbl_ResetStatus_ethSyncResetStatus(r16) _BFGET_(r16, 8, 8)
#define SET16Gbl_ResetStatus_ethSyncResetStatus(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Gbl_ResetStatus_ahbApbSyncResetStatus(r32) _BFGET_(r32, 9, 9)
#define SET32Gbl_ResetStatus_ahbApbSyncResetStatus(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Gbl_ResetStatus_ahbApbSyncResetStatus(r16) _BFGET_(r16, 9, 9)
#define SET16Gbl_ResetStatus_ahbApbSyncResetStatus(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Gbl_ResetStatus_nanfSyncResetStatus(r32) _BFGET_(r32,10,10)
#define SET32Gbl_ResetStatus_nanfSyncResetStatus(r32,v) _BFSET_(r32,10,10,v)
#define GET16Gbl_ResetStatus_nanfSyncResetStatus(r16) _BFGET_(r16,10,10)
#define SET16Gbl_ResetStatus_nanfSyncResetStatus(r16,v) _BFSET_(r16,10,10,v)
#define GET32Gbl_ResetStatus_usb0SyncResetStatus(r32) _BFGET_(r32,11,11)
#define SET32Gbl_ResetStatus_usb0SyncResetStatus(r32,v) _BFSET_(r32,11,11,v)
#define GET16Gbl_ResetStatus_usb0SyncResetStatus(r16) _BFGET_(r16,11,11)
#define SET16Gbl_ResetStatus_usb0SyncResetStatus(r16,v) _BFSET_(r16,11,11,v)
#define GET32Gbl_ResetStatus_pBridgeSyncResetStatus(r32) _BFGET_(r32,12,12)
#define SET32Gbl_ResetStatus_pBridgeSyncResetStatus(r32,v) _BFSET_(r32,12,12,v)
#define GET16Gbl_ResetStatus_pBridgeSyncResetStatus(r16) _BFGET_(r16,12,12)
#define SET16Gbl_ResetStatus_pBridgeSyncResetStatus(r16,v) _BFSET_(r16,12,12,v)
#define GET32Gbl_ResetStatus_sdioSyncResetStatus(r32) _BFGET_(r32,13,13)
#define SET32Gbl_ResetStatus_sdioSyncResetStatus(r32,v) _BFSET_(r32,13,13,v)
#define GET16Gbl_ResetStatus_sdioSyncResetStatus(r16) _BFGET_(r16,13,13)
#define SET16Gbl_ResetStatus_sdioSyncResetStatus(r16,v) _BFSET_(r16,13,13,v)
#define GET32Gbl_ResetStatus_tspSyncResetStatus(r32) _BFGET_(r32,14,14)
#define SET32Gbl_ResetStatus_tspSyncResetStatus(r32,v) _BFSET_(r32,14,14,v)
#define GET16Gbl_ResetStatus_tspSyncResetStatus(r16) _BFGET_(r16,14,14)
#define SET16Gbl_ResetStatus_tspSyncResetStatus(r16,v) _BFSET_(r16,14,14,v)
#define GET32Gbl_ResetStatus_v2gSyncResetStatus(r32) _BFGET_(r32,15,15)
#define SET32Gbl_ResetStatus_v2gSyncResetStatus(r32,v) _BFSET_(r32,15,15,v)
#define GET16Gbl_ResetStatus_v2gSyncResetStatus(r16) _BFGET_(r16,15,15)
#define SET16Gbl_ResetStatus_v2gSyncResetStatus(r16,v) _BFSET_(r16,15,15,v)
#define GET32Gbl_ResetStatus_g1SyncResetStatus(r32) _BFGET_(r32,16,16)
#define SET32Gbl_ResetStatus_g1SyncResetStatus(r32,v) _BFSET_(r32,16,16,v)
#define GET16Gbl_ResetStatus_g1SyncResetStatus(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_ResetStatus_g1SyncResetStatus(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_ResetStatus_bcmSyncResetStatus(r32) _BFGET_(r32,17,17)
#define SET32Gbl_ResetStatus_bcmSyncResetStatus(r32,v) _BFSET_(r32,17,17,v)
#define GET16Gbl_ResetStatus_bcmSyncResetStatus(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_ResetStatus_bcmSyncResetStatus(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_ResetStatus_atbSyncResetStatus(r32) _BFGET_(r32,18,18)
#define SET32Gbl_ResetStatus_atbSyncResetStatus(r32,v) _BFSET_(r32,18,18,v)
#define GET16Gbl_ResetStatus_atbSyncResetStatus(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_ResetStatus_atbSyncResetStatus(r16,v) _BFSET_(r16, 2, 2,v)
#define w32Gbl_ResetStatus {\
UNSG32 uResetStatus_ChipResetStatus : 1;\
UNSG32 uResetStatus_wd0Status : 1;\
UNSG32 uResetStatus_wd1Status : 1;\
UNSG32 uResetStatus_wd2Status : 1;\
UNSG32 uResetStatus_socDdrSyncResetStatus : 1;\
UNSG32 uResetStatus_avioSyncResetStatus : 1;\
UNSG32 uResetStatus_zspSyncResetStatus : 1;\
UNSG32 uResetStatus_perifSyncResetStatus : 1;\
UNSG32 uResetStatus_ethSyncResetStatus : 1;\
UNSG32 uResetStatus_ahbApbSyncResetStatus : 1;\
UNSG32 uResetStatus_nanfSyncResetStatus : 1;\
UNSG32 uResetStatus_usb0SyncResetStatus : 1;\
UNSG32 uResetStatus_pBridgeSyncResetStatus : 1;\
UNSG32 uResetStatus_sdioSyncResetStatus : 1;\
UNSG32 uResetStatus_tspSyncResetStatus : 1;\
UNSG32 uResetStatus_v2gSyncResetStatus : 1;\
UNSG32 uResetStatus_g1SyncResetStatus : 1;\
UNSG32 uResetStatus_bcmSyncResetStatus : 1;\
UNSG32 uResetStatus_atbSyncResetStatus : 1;\
UNSG32 RSVDx604_b19 : 13;\
}
union { UNSG32 u32Gbl_ResetStatus;
struct w32Gbl_ResetStatus;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_gfx3DReset_SyncReset(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_gfx3DReset_SyncReset(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_gfx3DReset_SyncReset(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_gfx3DReset_SyncReset(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_gfx3DReset {\
UNSG32 ugfx3DReset_SyncReset : 1;\
UNSG32 RSVDx608_b1 : 31;\
}
union { UNSG32 u32Gbl_gfx3DReset;
struct w32Gbl_gfx3DReset;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_gfx3DResetStatus_SyncReset(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_gfx3DResetStatus_SyncReset(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_gfx3DResetStatus_SyncReset(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_gfx3DResetStatus_SyncReset(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_gfx3DResetStatus {\
UNSG32 ugfx3DResetStatus_SyncReset : 1;\
UNSG32 RSVDx60C_b1 : 31;\
}
union { UNSG32 u32Gbl_gfx3DResetStatus;
struct w32Gbl_gfx3DResetStatus;
};
///////////////////////////////////////////////////////////
SIE_pwrOff ie_avioPwrCtrl;
///////////////////////////////////////////////////////////
SIE_pwrOff ie_gfx3DPwrCtrl;
///////////////////////////////////////////////////////////
SIE_pwrOff ie_g1PwrCtrl;
///////////////////////////////////////////////////////////
SIE_pwrOff ie_v2gPwrCtrl;
///////////////////////////////////////////////////////////
#define GET32Gbl_clkEnable_ethCoreClkEn(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_clkEnable_ethCoreClkEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_clkEnable_ethCoreClkEn(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_clkEnable_ethCoreClkEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_clkEnable_ahbApbCoreClkEn(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_clkEnable_ahbApbCoreClkEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_clkEnable_ahbApbCoreClkEn(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_clkEnable_ahbApbCoreClkEn(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_clkEnable_usb0CoreClkEn(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_clkEnable_usb0CoreClkEn(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_clkEnable_usb0CoreClkEn(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_clkEnable_usb0CoreClkEn(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Gbl_clkEnable_pBridgeCoreClkEn(r32) _BFGET_(r32, 3, 3)
#define SET32Gbl_clkEnable_pBridgeCoreClkEn(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Gbl_clkEnable_pBridgeCoreClkEn(r16) _BFGET_(r16, 3, 3)
#define SET16Gbl_clkEnable_pBridgeCoreClkEn(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Gbl_clkEnable_sdioCoreClkEn(r32) _BFGET_(r32, 4, 4)
#define SET32Gbl_clkEnable_sdioCoreClkEn(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Gbl_clkEnable_sdioCoreClkEn(r16) _BFGET_(r16, 4, 4)
#define SET16Gbl_clkEnable_sdioCoreClkEn(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Gbl_clkEnable_nfcCoreClkEn(r32) _BFGET_(r32, 5, 5)
#define SET32Gbl_clkEnable_nfcCoreClkEn(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Gbl_clkEnable_nfcCoreClkEn(r16) _BFGET_(r16, 5, 5)
#define SET16Gbl_clkEnable_nfcCoreClkEn(r16,v) _BFSET_(r16, 5, 5,v)
#define w32Gbl_clkEnable {\
UNSG32 uclkEnable_ethCoreClkEn : 1;\
UNSG32 uclkEnable_ahbApbCoreClkEn : 1;\
UNSG32 uclkEnable_usb0CoreClkEn : 1;\
UNSG32 uclkEnable_pBridgeCoreClkEn : 1;\
UNSG32 uclkEnable_sdioCoreClkEn : 1;\
UNSG32 uclkEnable_nfcCoreClkEn : 1;\
UNSG32 RSVDx630_b6 : 26;\
}
union { UNSG32 u32Gbl_clkEnable;
struct w32Gbl_clkEnable;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_ClkSwitch_sysPLLSWBypass(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_ClkSwitch_sysPLLSWBypass(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_ClkSwitch_sysPLLSWBypass(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_ClkSwitch_sysPLLSWBypass(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_ClkSwitch_memPLLSWBypass(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_ClkSwitch_memPLLSWBypass(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_ClkSwitch_memPLLSWBypass(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_ClkSwitch_memPLLSWBypass(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_ClkSwitch_cpuPLLSWBypass(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_ClkSwitch_cpuPLLSWBypass(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_ClkSwitch_cpuPLLSWBypass(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_ClkSwitch_cpuPLLSWBypass(r16,v) _BFSET_(r16, 2, 2,v)
#define w32Gbl_ClkSwitch {\
UNSG32 uClkSwitch_sysPLLSWBypass : 1;\
UNSG32 uClkSwitch_memPLLSWBypass : 1;\
UNSG32 uClkSwitch_cpuPLLSWBypass : 1;\
UNSG32 RSVDx634_b3 : 29;\
}
union { UNSG32 u32Gbl_ClkSwitch;
struct w32Gbl_ClkSwitch;
};
///////////////////////////////////////////////////////////
SIE_clkD2 ie_cpufastRefClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_memfastRefClk;
///////////////////////////////////////////////////////////
SIE_clkD8 ie_cfgClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_sysClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_v2gClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_v2gM3Clk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_g1CoreClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_gfx3DCoreClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_gfx3DSysClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_avioSysClk;
///////////////////////////////////////////////////////////
SIE_clkD1 ie_appClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_vppSysClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_arcRefClk;
///////////////////////////////////////////////////////////
SIE_clkD8 ie_hdmirxMClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_perifClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_zspClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_tspClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_tspRefClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_atbClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_bcmClk;
///////////////////////////////////////////////////////////
SIE_clkD2 ie_nfcEccClk;
///////////////////////////////////////////////////////////
SIE_clkD8 ie_sd0Clk;
///////////////////////////////////////////////////////////
SIE_clkD12 ie_usb2TestClk;
///////////////////////////////////////////////////////////
SIE_clkD4 ie_sdio3DllMstRefClk;
///////////////////////////////////////////////////////////
UNSG8 RSVDx698 [616];
///////////////////////////////////////////////////////////
#define GET32Gbl_SECURE_SCAN_EN_SET(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SECURE_SCAN_EN_SET(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SECURE_SCAN_EN_SET(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SECURE_SCAN_EN_SET(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_SECURE_SCAN_EN {\
UNSG32 uSECURE_SCAN_EN_SET : 1;\
UNSG32 RSVDx900_b1 : 31;\
}
union { UNSG32 u32Gbl_SECURE_SCAN_EN;
struct w32Gbl_SECURE_SCAN_EN;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NandCtrl_NAND_WPn_Sel(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NandCtrl_NAND_WPn_Sel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NandCtrl_NAND_WPn_Sel(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NandCtrl_NAND_WPn_Sel(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NandCtrl_NAND_CLE_OE(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NandCtrl_NAND_CLE_OE(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NandCtrl_NAND_CLE_OE(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NandCtrl_NAND_CLE_OE(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Gbl_NandCtrl_NAND_ALE_OE(r32) _BFGET_(r32, 2, 2)
#define SET32Gbl_NandCtrl_NAND_ALE_OE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Gbl_NandCtrl_NAND_ALE_OE(r16) _BFGET_(r16, 2, 2)
#define SET16Gbl_NandCtrl_NAND_ALE_OE(r16,v) _BFSET_(r16, 2, 2,v)
#define w32Gbl_NandCtrl {\
UNSG32 uNandCtrl_NAND_WPn_Sel : 1;\
UNSG32 uNandCtrl_NAND_CLE_OE : 1;\
UNSG32 uNandCtrl_NAND_ALE_OE : 1;\
UNSG32 RSVDx904_b3 : 29;\
}
union { UNSG32 u32Gbl_NandCtrl;
struct w32Gbl_NandCtrl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sdioDllMstCtrl_PH_SEL1(r32) _BFGET_(r32, 5, 0)
#define SET32Gbl_sdioDllMstCtrl_PH_SEL1(r32,v) _BFSET_(r32, 5, 0,v)
#define GET16Gbl_sdioDllMstCtrl_PH_SEL1(r16) _BFGET_(r16, 5, 0)
#define SET16Gbl_sdioDllMstCtrl_PH_SEL1(r16,v) _BFSET_(r16, 5, 0,v)
#define GET32Gbl_sdioDllMstCtrl_PH_SEL2(r32) _BFGET_(r32,11, 6)
#define SET32Gbl_sdioDllMstCtrl_PH_SEL2(r32,v) _BFSET_(r32,11, 6,v)
#define GET16Gbl_sdioDllMstCtrl_PH_SEL2(r16) _BFGET_(r16,11, 6)
#define SET16Gbl_sdioDllMstCtrl_PH_SEL2(r16,v) _BFSET_(r16,11, 6,v)
#define GET32Gbl_sdioDllMstCtrl_PH_SEL3(r32) _BFGET_(r32,17,12)
#define SET32Gbl_sdioDllMstCtrl_PH_SEL3(r32,v) _BFSET_(r32,17,12,v)
#define GET32Gbl_sdioDllMstCtrl_PH_SEL4(r32) _BFGET_(r32,23,18)
#define SET32Gbl_sdioDllMstCtrl_PH_SEL4(r32,v) _BFSET_(r32,23,18,v)
#define GET16Gbl_sdioDllMstCtrl_PH_SEL4(r16) _BFGET_(r16, 7, 2)
#define SET16Gbl_sdioDllMstCtrl_PH_SEL4(r16,v) _BFSET_(r16, 7, 2,v)
#define GET32Gbl_sdioDllMstCtrl_RESET(r32) _BFGET_(r32,24,24)
#define SET32Gbl_sdioDllMstCtrl_RESET(r32,v) _BFSET_(r32,24,24,v)
#define GET16Gbl_sdioDllMstCtrl_RESET(r16) _BFGET_(r16, 8, 8)
#define SET16Gbl_sdioDllMstCtrl_RESET(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Gbl_sdioDllMstCtrl_GAIN2X(r32) _BFGET_(r32,25,25)
#define SET32Gbl_sdioDllMstCtrl_GAIN2X(r32,v) _BFSET_(r32,25,25,v)
#define GET16Gbl_sdioDllMstCtrl_GAIN2X(r16) _BFGET_(r16, 9, 9)
#define SET16Gbl_sdioDllMstCtrl_GAIN2X(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Gbl_sdioDllMstCtrl_TEST_EN(r32) _BFGET_(r32,26,26)
#define SET32Gbl_sdioDllMstCtrl_TEST_EN(r32,v) _BFSET_(r32,26,26,v)
#define GET16Gbl_sdioDllMstCtrl_TEST_EN(r16) _BFGET_(r16,10,10)
#define SET16Gbl_sdioDllMstCtrl_TEST_EN(r16,v) _BFSET_(r16,10,10,v)
#define GET32Gbl_sdioDllMstCtrl_RESERVE(r32) _BFGET_(r32,31,27)
#define SET32Gbl_sdioDllMstCtrl_RESERVE(r32,v) _BFSET_(r32,31,27,v)
#define GET16Gbl_sdioDllMstCtrl_RESERVE(r16) _BFGET_(r16,15,11)
#define SET16Gbl_sdioDllMstCtrl_RESERVE(r16,v) _BFSET_(r16,15,11,v)
#define w32Gbl_sdioDllMstCtrl {\
UNSG32 usdioDllMstCtrl_PH_SEL1 : 6;\
UNSG32 usdioDllMstCtrl_PH_SEL2 : 6;\
UNSG32 usdioDllMstCtrl_PH_SEL3 : 6;\
UNSG32 usdioDllMstCtrl_PH_SEL4 : 6;\
UNSG32 usdioDllMstCtrl_RESET : 1;\
UNSG32 usdioDllMstCtrl_GAIN2X : 1;\
UNSG32 usdioDllMstCtrl_TEST_EN : 1;\
UNSG32 usdioDllMstCtrl_RESERVE : 5;\
}
union { UNSG32 u32Gbl_sdioDllMstCtrl;
struct w32Gbl_sdioDllMstCtrl;
};
#define GET32Gbl_sdioDllMstCtrl_FAST_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_sdioDllMstCtrl_FAST_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_sdioDllMstCtrl_FAST_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_sdioDllMstCtrl_FAST_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_sdioDllMstCtrl1 {\
UNSG32 usdioDllMstCtrl_FAST_LOCK : 1;\
UNSG32 RSVDx90C_b1 : 31;\
}
union { UNSG32 u32Gbl_sdioDllMstCtrl1;
struct w32Gbl_sdioDllMstCtrl1;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_sdioDllMstStatus_DELAY_CTRL1(r32) _BFGET_(r32, 9, 0)
#define SET32Gbl_sdioDllMstStatus_DELAY_CTRL1(r32,v) _BFSET_(r32, 9, 0,v)
#define GET16Gbl_sdioDllMstStatus_DELAY_CTRL1(r16) _BFGET_(r16, 9, 0)
#define SET16Gbl_sdioDllMstStatus_DELAY_CTRL1(r16,v) _BFSET_(r16, 9, 0,v)
#define GET32Gbl_sdioDllMstStatus_DELAY_CTRL2(r32) _BFGET_(r32,19,10)
#define SET32Gbl_sdioDllMstStatus_DELAY_CTRL2(r32,v) _BFSET_(r32,19,10,v)
#define GET32Gbl_sdioDllMstStatus_DELAY_CTRL3(r32) _BFGET_(r32,29,20)
#define SET32Gbl_sdioDllMstStatus_DELAY_CTRL3(r32,v) _BFSET_(r32,29,20,v)
#define GET16Gbl_sdioDllMstStatus_DELAY_CTRL3(r16) _BFGET_(r16,13, 4)
#define SET16Gbl_sdioDllMstStatus_DELAY_CTRL3(r16,v) _BFSET_(r16,13, 4,v)
#define w32Gbl_sdioDllMstStatus {\
UNSG32 usdioDllMstStatus_DELAY_CTRL1 : 10;\
UNSG32 usdioDllMstStatus_DELAY_CTRL2 : 10;\
UNSG32 usdioDllMstStatus_DELAY_CTRL3 : 10;\
UNSG32 RSVDx910_b30 : 2;\
}
union { UNSG32 u32Gbl_sdioDllMstStatus;
struct w32Gbl_sdioDllMstStatus;
};
#define GET32Gbl_sdioDllMstStatus_DELAY_CTRL4(r32) _BFGET_(r32, 9, 0)
#define SET32Gbl_sdioDllMstStatus_DELAY_CTRL4(r32,v) _BFSET_(r32, 9, 0,v)
#define GET16Gbl_sdioDllMstStatus_DELAY_CTRL4(r16) _BFGET_(r16, 9, 0)
#define SET16Gbl_sdioDllMstStatus_DELAY_CTRL4(r16,v) _BFSET_(r16, 9, 0,v)
#define GET32Gbl_sdioDllMstStatus_DLL_LOCK(r32) _BFGET_(r32,10,10)
#define SET32Gbl_sdioDllMstStatus_DLL_LOCK(r32,v) _BFSET_(r32,10,10,v)
#define GET16Gbl_sdioDllMstStatus_DLL_LOCK(r16) _BFGET_(r16,10,10)
#define SET16Gbl_sdioDllMstStatus_DLL_LOCK(r16,v) _BFSET_(r16,10,10,v)
#define GET32Gbl_sdioDllMstStatus_DELAY_OUT(r32) _BFGET_(r32,20,11)
#define SET32Gbl_sdioDllMstStatus_DELAY_OUT(r32,v) _BFSET_(r32,20,11,v)
#define w32Gbl_sdioDllMstStatus1 {\
UNSG32 usdioDllMstStatus_DELAY_CTRL4 : 10;\
UNSG32 usdioDllMstStatus_DLL_LOCK : 1;\
UNSG32 usdioDllMstStatus_DELAY_OUT : 10;\
UNSG32 RSVDx914_b21 : 11;\
}
union { UNSG32 u32Gbl_sdioDllMstStatus1;
struct w32Gbl_sdioDllMstStatus1;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_gfx3DDisRamClkGate_drcg(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_gfx3DDisRamClkGate_drcg(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_gfx3DDisRamClkGate_drcg(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_gfx3DDisRamClkGate_drcg(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_gfx3DDisRamClkGate {\
UNSG32 ugfx3DDisRamClkGate_drcg : 1;\
UNSG32 RSVDx918_b1 : 31;\
}
union { UNSG32 u32Gbl_gfx3DDisRamClkGate;
struct w32Gbl_gfx3DDisRamClkGate;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_DroEn_Start(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_DroEn_Start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_DroEn_Start(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_DroEn_Start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_DroEn_CountVal(r32) _BFGET_(r32,16, 1)
#define SET32Gbl_DroEn_CountVal(r32,v) _BFSET_(r32,16, 1,v)
#define w32Gbl_DroEn {\
UNSG32 uDroEn_Start : 1;\
UNSG32 uDroEn_CountVal : 16;\
UNSG32 RSVDx91C_b17 : 15;\
}
union { UNSG32 u32Gbl_DroEn;
struct w32Gbl_DroEn;
};
#define GET32Gbl_DroEn_WaitVal(r32) _BFGET_(r32,15, 0)
#define SET32Gbl_DroEn_WaitVal(r32,v) _BFSET_(r32,15, 0,v)
#define GET16Gbl_DroEn_WaitVal(r16) _BFGET_(r16,15, 0)
#define SET16Gbl_DroEn_WaitVal(r16,v) _BFSET_(r16,15, 0,v)
#define w32Gbl_DroEn1 {\
UNSG32 uDroEn_WaitVal : 16;\
UNSG32 RSVDx920_b16 : 16;\
}
union { UNSG32 u32Gbl_DroEn1;
struct w32Gbl_DroEn1;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_DroShift_Start(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_DroShift_Start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_DroShift_Start(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_DroShift_Start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_DroShift_CountVal(r32) _BFGET_(r32,16, 1)
#define SET32Gbl_DroShift_CountVal(r32,v) _BFSET_(r32,16, 1,v)
#define w32Gbl_DroShift {\
UNSG32 uDroShift_Start : 1;\
UNSG32 uDroShift_CountVal : 16;\
UNSG32 RSVDx924_b17 : 15;\
}
union { UNSG32 u32Gbl_DroShift;
struct w32Gbl_DroShift;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_DroStatus_En(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_DroStatus_En(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_DroStatus_En(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_DroStatus_En(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_DroStatus_Shift_Done(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_DroStatus_Shift_Done(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_DroStatus_Shift_Done(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_DroStatus_Shift_Done(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_DroStatus {\
UNSG32 uDroStatus_En : 1;\
UNSG32 uDroStatus_Shift_Done : 1;\
UNSG32 RSVDx928_b2 : 30;\
}
union { UNSG32 u32Gbl_DroStatus;
struct w32Gbl_DroStatus;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_DroCounter_Out(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_DroCounter_Out(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_DroCounter {\
UNSG32 uDroCounter_Out : 32;\
}
union { UNSG32 u32Gbl_DroCounter;
struct w32Gbl_DroCounter;
};
///////////////////////////////////////////////////////////
SIE_vtr ie_vtr;
///////////////////////////////////////////////////////////
#define GET32Gbl_gic400_ctrl_cgfsdisable(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_gic400_ctrl_cgfsdisable(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_gic400_ctrl_cgfsdisable(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_gic400_ctrl_cgfsdisable(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_gic400_ctrl {\
UNSG32 ugic400_ctrl_cgfsdisable : 1;\
UNSG32 RSVDx938_b1 : 31;\
}
union { UNSG32 u32Gbl_gic400_ctrl;
struct w32Gbl_gic400_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPARE_CTRL_0_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_SPARE_CTRL_0_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_SPARE_CTRL_0 {\
UNSG32 uSPARE_CTRL_0_ctrl : 32;\
}
union { UNSG32 u32Gbl_SPARE_CTRL_0;
struct w32Gbl_SPARE_CTRL_0;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPARE_CTRL_1_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_SPARE_CTRL_1_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_SPARE_CTRL_1 {\
UNSG32 uSPARE_CTRL_1_ctrl : 32;\
}
union { UNSG32 u32Gbl_SPARE_CTRL_1;
struct w32Gbl_SPARE_CTRL_1;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPARE_CTRL_2_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_SPARE_CTRL_2_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_SPARE_CTRL_2 {\
UNSG32 uSPARE_CTRL_2_ctrl : 32;\
}
union { UNSG32 u32Gbl_SPARE_CTRL_2;
struct w32Gbl_SPARE_CTRL_2;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPARE_CTRL_3_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32Gbl_SPARE_CTRL_3_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32Gbl_SPARE_CTRL_3 {\
UNSG32 uSPARE_CTRL_3_ctrl : 32;\
}
union { UNSG32 u32Gbl_SPARE_CTRL_3;
struct w32Gbl_SPARE_CTRL_3;
};
///////////////////////////////////////////////////////////
SIE_efuse ie_efuse0;
///////////////////////////////////////////////////////////
SIE_efuse ie_efuse1;
///////////////////////////////////////////////////////////
SIE_PERIF ie_PERIF;
///////////////////////////////////////////////////////////
UNSG8 RSVDx9B0 [13904];
///////////////////////////////////////////////////////////
#define GET32Gbl_PadSelect_DVIO_OEN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_PadSelect_DVIO_OEN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_PadSelect_DVIO_OEN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_PadSelect_DVIO_OEN(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Gbl_PadSelect {\
UNSG32 uPadSelect_DVIO_OEN : 1;\
UNSG32 RSVDx4000_b1 : 31;\
}
union { UNSG32 u32Gbl_PadSelect;
struct w32Gbl_PadSelect;
};
///////////////////////////////////////////////////////////
SIE_padRing ie_I2C_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_SD0_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_TSI_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_SPI_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_NAND_PADRING;
///////////////////////////////////////////////////////////
#define GET32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL(r32) _BFGET_(r32, 2, 0)
#define SET32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL(r16) _BFGET_(r16, 2, 0)
#define SET16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA(r32) _BFGET_(r32, 5, 3)
#define SET32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA(r16) _BFGET_(r16, 5, 3)
#define SET16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA(r16,v) _BFSET_(r16, 5, 3,v)
#define w32Gbl_DDC_PAD_CTRL {\
UNSG32 uDDC_PAD_CTRL_ZN_TW1_SCL : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_TW1_SDA : 3;\
UNSG32 RSVDx402C_b6 : 26;\
}
union { UNSG32 u32Gbl_DDC_PAD_CTRL;
struct w32Gbl_DDC_PAD_CTRL;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDx4030 [16336];
///////////////////////////////////////////////////////////
#define GET32Gbl_pinMuxCntlBus_URT0_RXD(r32) _BFGET_(r32, 2, 0)
#define SET32Gbl_pinMuxCntlBus_URT0_RXD(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Gbl_pinMuxCntlBus_URT0_RXD(r16) _BFGET_(r16, 2, 0)
#define SET16Gbl_pinMuxCntlBus_URT0_RXD(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32Gbl_pinMuxCntlBus_URT0_TXD(r32) _BFGET_(r32, 5, 3)
#define SET32Gbl_pinMuxCntlBus_URT0_TXD(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16Gbl_pinMuxCntlBus_URT0_TXD(r16) _BFGET_(r16, 5, 3)
#define SET16Gbl_pinMuxCntlBus_URT0_TXD(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SS0n(r32) _BFGET_(r32, 8, 6)
#define SET32Gbl_pinMuxCntlBus_SPI1_SS0n(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16Gbl_pinMuxCntlBus_SPI1_SS0n(r16) _BFGET_(r16, 8, 6)
#define SET16Gbl_pinMuxCntlBus_SPI1_SS0n(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SS1n(r32) _BFGET_(r32,11, 9)
#define SET32Gbl_pinMuxCntlBus_SPI1_SS1n(r32,v) _BFSET_(r32,11, 9,v)
#define GET16Gbl_pinMuxCntlBus_SPI1_SS1n(r16) _BFGET_(r16,11, 9)
#define SET16Gbl_pinMuxCntlBus_SPI1_SS1n(r16,v) _BFSET_(r16,11, 9,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SS2n(r32) _BFGET_(r32,14,12)
#define SET32Gbl_pinMuxCntlBus_SPI1_SS2n(r32,v) _BFSET_(r32,14,12,v)
#define GET16Gbl_pinMuxCntlBus_SPI1_SS2n(r16) _BFGET_(r16,14,12)
#define SET16Gbl_pinMuxCntlBus_SPI1_SS2n(r16,v) _BFSET_(r16,14,12,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SCLK(r32) _BFGET_(r32,17,15)
#define SET32Gbl_pinMuxCntlBus_SPI1_SCLK(r32,v) _BFSET_(r32,17,15,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SDO(r32) _BFGET_(r32,20,18)
#define SET32Gbl_pinMuxCntlBus_SPI1_SDO(r32,v) _BFSET_(r32,20,18,v)
#define GET16Gbl_pinMuxCntlBus_SPI1_SDO(r16) _BFGET_(r16, 4, 2)
#define SET16Gbl_pinMuxCntlBus_SPI1_SDO(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32Gbl_pinMuxCntlBus_SPI1_SDI(r32) _BFGET_(r32,23,21)
#define SET32Gbl_pinMuxCntlBus_SPI1_SDI(r32,v) _BFSET_(r32,23,21,v)
#define GET16Gbl_pinMuxCntlBus_SPI1_SDI(r16) _BFGET_(r16, 7, 5)
#define SET16Gbl_pinMuxCntlBus_SPI1_SDI(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32Gbl_pinMuxCntlBus_USB1_DRV_VBUS(r32) _BFGET_(r32,26,24)
#define SET32Gbl_pinMuxCntlBus_USB1_DRV_VBUS(r32,v) _BFSET_(r32,26,24,v)
#define GET16Gbl_pinMuxCntlBus_USB1_DRV_VBUS(r16) _BFGET_(r16,10, 8)
#define SET16Gbl_pinMuxCntlBus_USB1_DRV_VBUS(r16,v) _BFSET_(r16,10, 8,v)
#define GET32Gbl_pinMuxCntlBus_TW1_SCL(r32) _BFGET_(r32,29,27)
#define SET32Gbl_pinMuxCntlBus_TW1_SCL(r32,v) _BFSET_(r32,29,27,v)
#define GET16Gbl_pinMuxCntlBus_TW1_SCL(r16) _BFGET_(r16,13,11)
#define SET16Gbl_pinMuxCntlBus_TW1_SCL(r16,v) _BFSET_(r16,13,11,v)
#define w32Gbl_pinMuxCntlBus {\
UNSG32 upinMuxCntlBus_URT0_RXD : 3;\
UNSG32 upinMuxCntlBus_URT0_TXD : 3;\
UNSG32 upinMuxCntlBus_SPI1_SS0n : 3;\
UNSG32 upinMuxCntlBus_SPI1_SS1n : 3;\
UNSG32 upinMuxCntlBus_SPI1_SS2n : 3;\
UNSG32 upinMuxCntlBus_SPI1_SCLK : 3;\
UNSG32 upinMuxCntlBus_SPI1_SDO : 3;\
UNSG32 upinMuxCntlBus_SPI1_SDI : 3;\
UNSG32 upinMuxCntlBus_USB1_DRV_VBUS : 3;\
UNSG32 upinMuxCntlBus_TW1_SCL : 3;\
UNSG32 RSVDx8000_b30 : 2;\
}
union { UNSG32 u32Gbl_pinMuxCntlBus;
struct w32Gbl_pinMuxCntlBus;
};
#define GET32Gbl_pinMuxCntlBus_TW1_SDA(r32) _BFGET_(r32, 2, 0)
#define SET32Gbl_pinMuxCntlBus_TW1_SDA(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Gbl_pinMuxCntlBus_TW1_SDA(r16) _BFGET_(r16, 2, 0)
#define SET16Gbl_pinMuxCntlBus_TW1_SDA(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32Gbl_pinMuxCntlBus_HDMI_CEC(r32) _BFGET_(r32, 5, 3)
#define SET32Gbl_pinMuxCntlBus_HDMI_CEC(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16Gbl_pinMuxCntlBus_HDMI_CEC(r16) _BFGET_(r16, 5, 3)
#define SET16Gbl_pinMuxCntlBus_HDMI_CEC(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32Gbl_pinMuxCntlBus_HDMI_HPD(r32) _BFGET_(r32, 8, 6)
#define SET32Gbl_pinMuxCntlBus_HDMI_HPD(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16Gbl_pinMuxCntlBus_HDMI_HPD(r16) _BFGET_(r16, 8, 6)
#define SET16Gbl_pinMuxCntlBus_HDMI_HPD(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO0(r32) _BFGET_(r32,11, 9)
#define SET32Gbl_pinMuxCntlBus_NAND_IO0(r32,v) _BFSET_(r32,11, 9,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO0(r16) _BFGET_(r16,11, 9)
#define SET16Gbl_pinMuxCntlBus_NAND_IO0(r16,v) _BFSET_(r16,11, 9,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO1(r32) _BFGET_(r32,14,12)
#define SET32Gbl_pinMuxCntlBus_NAND_IO1(r32,v) _BFSET_(r32,14,12,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO1(r16) _BFGET_(r16,14,12)
#define SET16Gbl_pinMuxCntlBus_NAND_IO1(r16,v) _BFSET_(r16,14,12,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO2(r32) _BFGET_(r32,17,15)
#define SET32Gbl_pinMuxCntlBus_NAND_IO2(r32,v) _BFSET_(r32,17,15,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO3(r32) _BFGET_(r32,20,18)
#define SET32Gbl_pinMuxCntlBus_NAND_IO3(r32,v) _BFSET_(r32,20,18,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO3(r16) _BFGET_(r16, 4, 2)
#define SET16Gbl_pinMuxCntlBus_NAND_IO3(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO4(r32) _BFGET_(r32,23,21)
#define SET32Gbl_pinMuxCntlBus_NAND_IO4(r32,v) _BFSET_(r32,23,21,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO4(r16) _BFGET_(r16, 7, 5)
#define SET16Gbl_pinMuxCntlBus_NAND_IO4(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO5(r32) _BFGET_(r32,26,24)
#define SET32Gbl_pinMuxCntlBus_NAND_IO5(r32,v) _BFSET_(r32,26,24,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO5(r16) _BFGET_(r16,10, 8)
#define SET16Gbl_pinMuxCntlBus_NAND_IO5(r16,v) _BFSET_(r16,10, 8,v)
#define GET32Gbl_pinMuxCntlBus_NAND_IO6(r32) _BFGET_(r32,29,27)
#define SET32Gbl_pinMuxCntlBus_NAND_IO6(r32,v) _BFSET_(r32,29,27,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO6(r16) _BFGET_(r16,13,11)
#define SET16Gbl_pinMuxCntlBus_NAND_IO6(r16,v) _BFSET_(r16,13,11,v)
#define w32Gbl_pinMuxCntlBus1 {\
UNSG32 upinMuxCntlBus_TW1_SDA : 3;\
UNSG32 upinMuxCntlBus_HDMI_CEC : 3;\
UNSG32 upinMuxCntlBus_HDMI_HPD : 3;\
UNSG32 upinMuxCntlBus_NAND_IO0 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO1 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO2 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO3 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO4 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO5 : 3;\
UNSG32 upinMuxCntlBus_NAND_IO6 : 3;\
UNSG32 RSVDx8004_b30 : 2;\
}
union { UNSG32 u32Gbl_pinMuxCntlBus1;
struct w32Gbl_pinMuxCntlBus1;
};
#define GET32Gbl_pinMuxCntlBus_NAND_IO7(r32) _BFGET_(r32, 2, 0)
#define SET32Gbl_pinMuxCntlBus_NAND_IO7(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Gbl_pinMuxCntlBus_NAND_IO7(r16) _BFGET_(r16, 2, 0)
#define SET16Gbl_pinMuxCntlBus_NAND_IO7(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32Gbl_pinMuxCntlBus_NAND_ALE(r32) _BFGET_(r32, 5, 3)
#define SET32Gbl_pinMuxCntlBus_NAND_ALE(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16Gbl_pinMuxCntlBus_NAND_ALE(r16) _BFGET_(r16, 5, 3)
#define SET16Gbl_pinMuxCntlBus_NAND_ALE(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32Gbl_pinMuxCntlBus_NAND_CLE(r32) _BFGET_(r32, 8, 6)
#define SET32Gbl_pinMuxCntlBus_NAND_CLE(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16Gbl_pinMuxCntlBus_NAND_CLE(r16) _BFGET_(r16, 8, 6)
#define SET16Gbl_pinMuxCntlBus_NAND_CLE(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32Gbl_pinMuxCntlBus_NAND_WEn(r32) _BFGET_(r32,11, 9)
#define SET32Gbl_pinMuxCntlBus_NAND_WEn(r32,v) _BFSET_(r32,11, 9,v)
#define GET16Gbl_pinMuxCntlBus_NAND_WEn(r16) _BFGET_(r16,11, 9)
#define SET16Gbl_pinMuxCntlBus_NAND_WEn(r16,v) _BFSET_(r16,11, 9,v)
#define GET32Gbl_pinMuxCntlBus_NAND_REn(r32) _BFGET_(r32,14,12)
#define SET32Gbl_pinMuxCntlBus_NAND_REn(r32,v) _BFSET_(r32,14,12,v)
#define GET16Gbl_pinMuxCntlBus_NAND_REn(r16) _BFGET_(r16,14,12)
#define SET16Gbl_pinMuxCntlBus_NAND_REn(r16,v) _BFSET_(r16,14,12,v)
#define GET32Gbl_pinMuxCntlBus_NAND_WPn(r32) _BFGET_(r32,17,15)
#define SET32Gbl_pinMuxCntlBus_NAND_WPn(r32,v) _BFSET_(r32,17,15,v)
#define GET32Gbl_pinMuxCntlBus_NAND_CEn(r32) _BFGET_(r32,20,18)
#define SET32Gbl_pinMuxCntlBus_NAND_CEn(r32,v) _BFSET_(r32,20,18,v)
#define GET16Gbl_pinMuxCntlBus_NAND_CEn(r16) _BFGET_(r16, 4, 2)
#define SET16Gbl_pinMuxCntlBus_NAND_CEn(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32Gbl_pinMuxCntlBus_NAND_RDY(r32) _BFGET_(r32,23,21)
#define SET32Gbl_pinMuxCntlBus_NAND_RDY(r32,v) _BFSET_(r32,23,21,v)
#define GET16Gbl_pinMuxCntlBus_NAND_RDY(r16) _BFGET_(r16, 7, 5)
#define SET16Gbl_pinMuxCntlBus_NAND_RDY(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32Gbl_pinMuxCntlBus_SD0_CLK(r32) _BFGET_(r32,26,24)
#define SET32Gbl_pinMuxCntlBus_SD0_CLK(r32,v) _BFSET_(r32,26,24,v)
#define GET16Gbl_pinMuxCntlBus_SD0_CLK(r16) _BFGET_(r16,10, 8)
#define SET16Gbl_pinMuxCntlBus_SD0_CLK(r16,v) _BFSET_(r16,10, 8,v)
#define GET32Gbl_pinMuxCntlBus_SD0_DAT0(r32) _BFGET_(r32,29,27)
#define SET32Gbl_pinMuxCntlBus_SD0_DAT0(r32,v) _BFSET_(r32,29,27,v)
#define GET16Gbl_pinMuxCntlBus_SD0_DAT0(r16) _BFGET_(r16,13,11)
#define SET16Gbl_pinMuxCntlBus_SD0_DAT0(r16,v) _BFSET_(r16,13,11,v)
#define w32Gbl_pinMuxCntlBus2 {\
UNSG32 upinMuxCntlBus_NAND_IO7 : 3;\
UNSG32 upinMuxCntlBus_NAND_ALE : 3;\
UNSG32 upinMuxCntlBus_NAND_CLE : 3;\
UNSG32 upinMuxCntlBus_NAND_WEn : 3;\
UNSG32 upinMuxCntlBus_NAND_REn : 3;\
UNSG32 upinMuxCntlBus_NAND_WPn : 3;\
UNSG32 upinMuxCntlBus_NAND_CEn : 3;\
UNSG32 upinMuxCntlBus_NAND_RDY : 3;\
UNSG32 upinMuxCntlBus_SD0_CLK : 3;\
UNSG32 upinMuxCntlBus_SD0_DAT0 : 3;\
UNSG32 RSVDx8008_b30 : 2;\
}
union { UNSG32 u32Gbl_pinMuxCntlBus2;
struct w32Gbl_pinMuxCntlBus2;
};
#define GET32Gbl_pinMuxCntlBus_SD0_DAT1(r32) _BFGET_(r32, 2, 0)
#define SET32Gbl_pinMuxCntlBus_SD0_DAT1(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Gbl_pinMuxCntlBus_SD0_DAT1(r16) _BFGET_(r16, 2, 0)
#define SET16Gbl_pinMuxCntlBus_SD0_DAT1(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32Gbl_pinMuxCntlBus_SD0_DAT2(r32) _BFGET_(r32, 5, 3)
#define SET32Gbl_pinMuxCntlBus_SD0_DAT2(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16Gbl_pinMuxCntlBus_SD0_DAT2(r16) _BFGET_(r16, 5, 3)
#define SET16Gbl_pinMuxCntlBus_SD0_DAT2(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32Gbl_pinMuxCntlBus_SD0_DAT3(r32) _BFGET_(r32, 8, 6)
#define SET32Gbl_pinMuxCntlBus_SD0_DAT3(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16Gbl_pinMuxCntlBus_SD0_DAT3(r16) _BFGET_(r16, 8, 6)
#define SET16Gbl_pinMuxCntlBus_SD0_DAT3(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32Gbl_pinMuxCntlBus_SD0_CDn(r32) _BFGET_(r32,11, 9)
#define SET32Gbl_pinMuxCntlBus_SD0_CDn(r32,v) _BFSET_(r32,11, 9,v)
#define GET16Gbl_pinMuxCntlBus_SD0_CDn(r16) _BFGET_(r16,11, 9)
#define SET16Gbl_pinMuxCntlBus_SD0_CDn(r16,v) _BFSET_(r16,11, 9,v)
#define GET32Gbl_pinMuxCntlBus_SD0_CMD(r32) _BFGET_(r32,14,12)
#define SET32Gbl_pinMuxCntlBus_SD0_CMD(r32,v) _BFSET_(r32,14,12,v)
#define GET16Gbl_pinMuxCntlBus_SD0_CMD(r16) _BFGET_(r16,14,12)
#define SET16Gbl_pinMuxCntlBus_SD0_CMD(r16,v) _BFSET_(r16,14,12,v)
#define GET32Gbl_pinMuxCntlBus_SD0_WP(r32) _BFGET_(r32,17,15)
#define SET32Gbl_pinMuxCntlBus_SD0_WP(r32,v) _BFSET_(r32,17,15,v)
#define GET32Gbl_pinMuxCntlBus_STS0_CLK(r32) _BFGET_(r32,20,18)
#define SET32Gbl_pinMuxCntlBus_STS0_CLK(r32,v) _BFSET_(r32,20,18,v)
#define GET16Gbl_pinMuxCntlBus_STS0_CLK(r16) _BFGET_(r16, 4, 2)
#define SET16Gbl_pinMuxCntlBus_STS0_CLK(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32Gbl_pinMuxCntlBus_STS0_SOP(r32) _BFGET_(r32,23,21)
#define SET32Gbl_pinMuxCntlBus_STS0_SOP(r32,v) _BFSET_(r32,23,21,v)
#define GET16Gbl_pinMuxCntlBus_STS0_SOP(r16) _BFGET_(r16, 7, 5)
#define SET16Gbl_pinMuxCntlBus_STS0_SOP(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32Gbl_pinMuxCntlBus_STS0_VALD(r32) _BFGET_(r32,26,24)
#define SET32Gbl_pinMuxCntlBus_STS0_VALD(r32,v) _BFSET_(r32,26,24,v)
#define GET16Gbl_pinMuxCntlBus_STS0_VALD(r16) _BFGET_(r16,10, 8)
#define SET16Gbl_pinMuxCntlBus_STS0_VALD(r16,v) _BFSET_(r16,10, 8,v)
#define GET32Gbl_pinMuxCntlBus_STS0_SD(r32) _BFGET_(r32,29,27)
#define SET32Gbl_pinMuxCntlBus_STS0_SD(r32,v) _BFSET_(r32,29,27,v)
#define GET16Gbl_pinMuxCntlBus_STS0_SD(r16) _BFGET_(r16,13,11)
#define SET16Gbl_pinMuxCntlBus_STS0_SD(r16,v) _BFSET_(r16,13,11,v)
#define w32Gbl_pinMuxCntlBus3 {\
UNSG32 upinMuxCntlBus_SD0_DAT1 : 3;\
UNSG32 upinMuxCntlBus_SD0_DAT2 : 3;\
UNSG32 upinMuxCntlBus_SD0_DAT3 : 3;\
UNSG32 upinMuxCntlBus_SD0_CDn : 3;\
UNSG32 upinMuxCntlBus_SD0_CMD : 3;\
UNSG32 upinMuxCntlBus_SD0_WP : 3;\
UNSG32 upinMuxCntlBus_STS0_CLK : 3;\
UNSG32 upinMuxCntlBus_STS0_SOP : 3;\
UNSG32 upinMuxCntlBus_STS0_VALD : 3;\
UNSG32 upinMuxCntlBus_STS0_SD : 3;\
UNSG32 RSVDx800C_b30 : 2;\
}
union { UNSG32 u32Gbl_pinMuxCntlBus3;
struct w32Gbl_pinMuxCntlBus3;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_URT0_RXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_URT0_RXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_URT0_RXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_URT0_RXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_URT0_RXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_URT0_RXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_URT0_RXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_URT0_RXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_URT0_RXDCntl {\
UNSG32 uURT0_RXDCntl_PD_EN : 1;\
UNSG32 uURT0_RXDCntl_PU_EN : 1;\
UNSG32 RSVDx8010_b2 : 30;\
}
union { UNSG32 u32Gbl_URT0_RXDCntl;
struct w32Gbl_URT0_RXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_URT0_TXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_URT0_TXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_URT0_TXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_URT0_TXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_URT0_TXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_URT0_TXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_URT0_TXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_URT0_TXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_URT0_TXDCntl {\
UNSG32 uURT0_TXDCntl_PD_EN : 1;\
UNSG32 uURT0_TXDCntl_PU_EN : 1;\
UNSG32 RSVDx8014_b2 : 30;\
}
union { UNSG32 u32Gbl_URT0_TXDCntl;
struct w32Gbl_URT0_TXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SS0nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SS0nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SS0nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SS0nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SS0nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SS0nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SS0nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SS0nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SS0nCntl {\
UNSG32 uSPI1_SS0nCntl_PD_EN : 1;\
UNSG32 uSPI1_SS0nCntl_PU_EN : 1;\
UNSG32 RSVDx8018_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SS0nCntl;
struct w32Gbl_SPI1_SS0nCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SS1nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SS1nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SS1nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SS1nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SS1nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SS1nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SS1nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SS1nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SS1nCntl {\
UNSG32 uSPI1_SS1nCntl_PD_EN : 1;\
UNSG32 uSPI1_SS1nCntl_PU_EN : 1;\
UNSG32 RSVDx801C_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SS1nCntl;
struct w32Gbl_SPI1_SS1nCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SS2nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SS2nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SS2nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SS2nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SS2nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SS2nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SS2nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SS2nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SS2nCntl {\
UNSG32 uSPI1_SS2nCntl_PD_EN : 1;\
UNSG32 uSPI1_SS2nCntl_PU_EN : 1;\
UNSG32 RSVDx8020_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SS2nCntl;
struct w32Gbl_SPI1_SS2nCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SCLKCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SCLKCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SCLKCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SCLKCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SCLKCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SCLKCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SCLKCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SCLKCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SCLKCntl {\
UNSG32 uSPI1_SCLKCntl_PD_EN : 1;\
UNSG32 uSPI1_SCLKCntl_PU_EN : 1;\
UNSG32 RSVDx8024_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SCLKCntl;
struct w32Gbl_SPI1_SCLKCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SDOCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SDOCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SDOCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SDOCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SDOCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SDOCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SDOCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SDOCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SDOCntl {\
UNSG32 uSPI1_SDOCntl_PD_EN : 1;\
UNSG32 uSPI1_SDOCntl_PU_EN : 1;\
UNSG32 RSVDx8028_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SDOCntl;
struct w32Gbl_SPI1_SDOCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SPI1_SDICntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SPI1_SDICntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SPI1_SDICntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SPI1_SDICntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SPI1_SDICntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SPI1_SDICntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SPI1_SDICntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SPI1_SDICntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SPI1_SDICntl {\
UNSG32 uSPI1_SDICntl_PD_EN : 1;\
UNSG32 uSPI1_SDICntl_PU_EN : 1;\
UNSG32 RSVDx802C_b2 : 30;\
}
union { UNSG32 u32Gbl_SPI1_SDICntl;
struct w32Gbl_SPI1_SDICntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_USB1_DRV_VBUSCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_USB1_DRV_VBUSCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_USB1_DRV_VBUSCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_USB1_DRV_VBUSCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_USB1_DRV_VBUSCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_USB1_DRV_VBUSCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_USB1_DRV_VBUSCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_USB1_DRV_VBUSCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_USB1_DRV_VBUSCntl {\
UNSG32 uUSB1_DRV_VBUSCntl_PD_EN : 1;\
UNSG32 uUSB1_DRV_VBUSCntl_PU_EN : 1;\
UNSG32 RSVDx8030_b2 : 30;\
}
union { UNSG32 u32Gbl_USB1_DRV_VBUSCntl;
struct w32Gbl_USB1_DRV_VBUSCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO0Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO0Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO0Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO0Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO0Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO0Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO0Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO0Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO0Cntl {\
UNSG32 uNAND_IO0Cntl_PD_EN : 1;\
UNSG32 uNAND_IO0Cntl_PU_EN : 1;\
UNSG32 RSVDx8034_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO0Cntl;
struct w32Gbl_NAND_IO0Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO1Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO1Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO1Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO1Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO1Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO1Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO1Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO1Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO1Cntl {\
UNSG32 uNAND_IO1Cntl_PD_EN : 1;\
UNSG32 uNAND_IO1Cntl_PU_EN : 1;\
UNSG32 RSVDx8038_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO1Cntl;
struct w32Gbl_NAND_IO1Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO2Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO2Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO2Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO2Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO2Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO2Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO2Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO2Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO2Cntl {\
UNSG32 uNAND_IO2Cntl_PD_EN : 1;\
UNSG32 uNAND_IO2Cntl_PU_EN : 1;\
UNSG32 RSVDx803C_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO2Cntl;
struct w32Gbl_NAND_IO2Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO3Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO3Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO3Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO3Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO3Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO3Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO3Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO3Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO3Cntl {\
UNSG32 uNAND_IO3Cntl_PD_EN : 1;\
UNSG32 uNAND_IO3Cntl_PU_EN : 1;\
UNSG32 RSVDx8040_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO3Cntl;
struct w32Gbl_NAND_IO3Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO4Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO4Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO4Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO4Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO4Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO4Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO4Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO4Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO4Cntl {\
UNSG32 uNAND_IO4Cntl_PD_EN : 1;\
UNSG32 uNAND_IO4Cntl_PU_EN : 1;\
UNSG32 RSVDx8044_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO4Cntl;
struct w32Gbl_NAND_IO4Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO5Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO5Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO5Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO5Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO5Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO5Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO5Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO5Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO5Cntl {\
UNSG32 uNAND_IO5Cntl_PD_EN : 1;\
UNSG32 uNAND_IO5Cntl_PU_EN : 1;\
UNSG32 RSVDx8048_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO5Cntl;
struct w32Gbl_NAND_IO5Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO6Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO6Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO6Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO6Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO6Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO6Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO6Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO6Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO6Cntl {\
UNSG32 uNAND_IO6Cntl_PD_EN : 1;\
UNSG32 uNAND_IO6Cntl_PU_EN : 1;\
UNSG32 RSVDx804C_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO6Cntl;
struct w32Gbl_NAND_IO6Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_IO7Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_IO7Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_IO7Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_IO7Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_IO7Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_IO7Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_IO7Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_IO7Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_IO7Cntl {\
UNSG32 uNAND_IO7Cntl_PD_EN : 1;\
UNSG32 uNAND_IO7Cntl_PU_EN : 1;\
UNSG32 RSVDx8050_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_IO7Cntl;
struct w32Gbl_NAND_IO7Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_ALECntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_ALECntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_ALECntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_ALECntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_ALECntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_ALECntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_ALECntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_ALECntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_ALECntl {\
UNSG32 uNAND_ALECntl_PD_EN : 1;\
UNSG32 uNAND_ALECntl_PU_EN : 1;\
UNSG32 RSVDx8054_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_ALECntl;
struct w32Gbl_NAND_ALECntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_CLECntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_CLECntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_CLECntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_CLECntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_CLECntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_CLECntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_CLECntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_CLECntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_CLECntl {\
UNSG32 uNAND_CLECntl_PD_EN : 1;\
UNSG32 uNAND_CLECntl_PU_EN : 1;\
UNSG32 RSVDx8058_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_CLECntl;
struct w32Gbl_NAND_CLECntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_WEnCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_WEnCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_WEnCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_WEnCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_WEnCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_WEnCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_WEnCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_WEnCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_WEnCntl {\
UNSG32 uNAND_WEnCntl_PD_EN : 1;\
UNSG32 uNAND_WEnCntl_PU_EN : 1;\
UNSG32 RSVDx805C_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_WEnCntl;
struct w32Gbl_NAND_WEnCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_REnCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_REnCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_REnCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_REnCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_REnCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_REnCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_REnCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_REnCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_REnCntl {\
UNSG32 uNAND_REnCntl_PD_EN : 1;\
UNSG32 uNAND_REnCntl_PU_EN : 1;\
UNSG32 RSVDx8060_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_REnCntl;
struct w32Gbl_NAND_REnCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_WPnCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_WPnCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_WPnCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_WPnCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_WPnCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_WPnCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_WPnCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_WPnCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_WPnCntl {\
UNSG32 uNAND_WPnCntl_PD_EN : 1;\
UNSG32 uNAND_WPnCntl_PU_EN : 1;\
UNSG32 RSVDx8064_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_WPnCntl;
struct w32Gbl_NAND_WPnCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_CEnCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_CEnCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_CEnCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_CEnCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_CEnCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_CEnCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_CEnCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_CEnCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_CEnCntl {\
UNSG32 uNAND_CEnCntl_PD_EN : 1;\
UNSG32 uNAND_CEnCntl_PU_EN : 1;\
UNSG32 RSVDx8068_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_CEnCntl;
struct w32Gbl_NAND_CEnCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_NAND_RDYCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_NAND_RDYCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_NAND_RDYCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_NAND_RDYCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_NAND_RDYCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_NAND_RDYCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_NAND_RDYCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_NAND_RDYCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_NAND_RDYCntl {\
UNSG32 uNAND_RDYCntl_PD_EN : 1;\
UNSG32 uNAND_RDYCntl_PU_EN : 1;\
UNSG32 RSVDx806C_b2 : 30;\
}
union { UNSG32 u32Gbl_NAND_RDYCntl;
struct w32Gbl_NAND_RDYCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_CLKCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_CLKCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_CLKCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_CLKCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_CLKCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_CLKCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_CLKCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_CLKCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_CLKCntl {\
UNSG32 uSD0_CLKCntl_PD_EN : 1;\
UNSG32 uSD0_CLKCntl_PU_EN : 1;\
UNSG32 RSVDx8070_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_CLKCntl;
struct w32Gbl_SD0_CLKCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_DAT0Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_DAT0Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_DAT0Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_DAT0Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_DAT0Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_DAT0Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_DAT0Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_DAT0Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_DAT0Cntl {\
UNSG32 uSD0_DAT0Cntl_PD_EN : 1;\
UNSG32 uSD0_DAT0Cntl_PU_EN : 1;\
UNSG32 RSVDx8074_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_DAT0Cntl;
struct w32Gbl_SD0_DAT0Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_DAT1Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_DAT1Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_DAT1Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_DAT1Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_DAT1Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_DAT1Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_DAT1Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_DAT1Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_DAT1Cntl {\
UNSG32 uSD0_DAT1Cntl_PD_EN : 1;\
UNSG32 uSD0_DAT1Cntl_PU_EN : 1;\
UNSG32 RSVDx8078_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_DAT1Cntl;
struct w32Gbl_SD0_DAT1Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_DAT2Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_DAT2Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_DAT2Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_DAT2Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_DAT2Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_DAT2Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_DAT2Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_DAT2Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_DAT2Cntl {\
UNSG32 uSD0_DAT2Cntl_PD_EN : 1;\
UNSG32 uSD0_DAT2Cntl_PU_EN : 1;\
UNSG32 RSVDx807C_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_DAT2Cntl;
struct w32Gbl_SD0_DAT2Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_DAT3Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_DAT3Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_DAT3Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_DAT3Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_DAT3Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_DAT3Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_DAT3Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_DAT3Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_DAT3Cntl {\
UNSG32 uSD0_DAT3Cntl_PD_EN : 1;\
UNSG32 uSD0_DAT3Cntl_PU_EN : 1;\
UNSG32 RSVDx8080_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_DAT3Cntl;
struct w32Gbl_SD0_DAT3Cntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_CDnCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_CDnCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_CDnCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_CDnCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_CDnCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_CDnCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_CDnCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_CDnCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_CDnCntl {\
UNSG32 uSD0_CDnCntl_PD_EN : 1;\
UNSG32 uSD0_CDnCntl_PU_EN : 1;\
UNSG32 RSVDx8084_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_CDnCntl;
struct w32Gbl_SD0_CDnCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_CMDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_CMDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_CMDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_CMDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_CMDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_CMDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_CMDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_CMDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_CMDCntl {\
UNSG32 uSD0_CMDCntl_PD_EN : 1;\
UNSG32 uSD0_CMDCntl_PU_EN : 1;\
UNSG32 RSVDx8088_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_CMDCntl;
struct w32Gbl_SD0_CMDCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_SD0_WPCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_SD0_WPCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_SD0_WPCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_SD0_WPCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_SD0_WPCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_SD0_WPCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_SD0_WPCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_SD0_WPCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_SD0_WPCntl {\
UNSG32 uSD0_WPCntl_PD_EN : 1;\
UNSG32 uSD0_WPCntl_PU_EN : 1;\
UNSG32 RSVDx808C_b2 : 30;\
}
union { UNSG32 u32Gbl_SD0_WPCntl;
struct w32Gbl_SD0_WPCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_STS0_CLKCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_STS0_CLKCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_STS0_CLKCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_STS0_CLKCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_STS0_CLKCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_STS0_CLKCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_STS0_CLKCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_STS0_CLKCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_STS0_CLKCntl {\
UNSG32 uSTS0_CLKCntl_PD_EN : 1;\
UNSG32 uSTS0_CLKCntl_PU_EN : 1;\
UNSG32 RSVDx8090_b2 : 30;\
}
union { UNSG32 u32Gbl_STS0_CLKCntl;
struct w32Gbl_STS0_CLKCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_STS0_SOPCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_STS0_SOPCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_STS0_SOPCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_STS0_SOPCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_STS0_SOPCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_STS0_SOPCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_STS0_SOPCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_STS0_SOPCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_STS0_SOPCntl {\
UNSG32 uSTS0_SOPCntl_PD_EN : 1;\
UNSG32 uSTS0_SOPCntl_PU_EN : 1;\
UNSG32 RSVDx8094_b2 : 30;\
}
union { UNSG32 u32Gbl_STS0_SOPCntl;
struct w32Gbl_STS0_SOPCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_STS0_VALDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_STS0_VALDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_STS0_VALDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_STS0_VALDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_STS0_VALDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_STS0_VALDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_STS0_VALDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_STS0_VALDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_STS0_VALDCntl {\
UNSG32 uSTS0_VALDCntl_PD_EN : 1;\
UNSG32 uSTS0_VALDCntl_PU_EN : 1;\
UNSG32 RSVDx8098_b2 : 30;\
}
union { UNSG32 u32Gbl_STS0_VALDCntl;
struct w32Gbl_STS0_VALDCntl;
};
///////////////////////////////////////////////////////////
#define GET32Gbl_STS0_SDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Gbl_STS0_SDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Gbl_STS0_SDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Gbl_STS0_SDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Gbl_STS0_SDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32Gbl_STS0_SDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Gbl_STS0_SDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16Gbl_STS0_SDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Gbl_STS0_SDCntl {\
UNSG32 uSTS0_SDCntl_PD_EN : 1;\
UNSG32 uSTS0_SDCntl_PU_EN : 1;\
UNSG32 RSVDx809C_b2 : 30;\
}
union { UNSG32 u32Gbl_STS0_SDCntl;
struct w32Gbl_STS0_SDCntl;
};
///////////////////////////////////////////////////////////
} SIE_Gbl;
typedef union T32Gbl_ProductId
{ UNSG32 u32;
struct w32Gbl_ProductId;
} T32Gbl_ProductId;
typedef union T32Gbl_ProductId_ext
{ UNSG32 u32;
struct w32Gbl_ProductId_ext;
} T32Gbl_ProductId_ext;
typedef union T32Gbl_INT_ID
{ UNSG32 u32;
struct w32Gbl_INT_ID;
} T32Gbl_INT_ID;
typedef union T32Gbl_bootStrap
{ UNSG32 u32;
struct w32Gbl_bootStrap;
} T32Gbl_bootStrap;
typedef union T32Gbl_bootStrapEn
{ UNSG32 u32;
struct w32Gbl_bootStrapEn;
} T32Gbl_bootStrapEn;
typedef union T32Gbl_chipCntl
{ UNSG32 u32;
struct w32Gbl_chipCntl;
} T32Gbl_chipCntl;
typedef union T32Gbl_sw_generic0
{ UNSG32 u32;
struct w32Gbl_sw_generic0;
} T32Gbl_sw_generic0;
typedef union T32Gbl_sw_generic1
{ UNSG32 u32;
struct w32Gbl_sw_generic1;
} T32Gbl_sw_generic1;
typedef union T32Gbl_sw_generic2
{ UNSG32 u32;
struct w32Gbl_sw_generic2;
} T32Gbl_sw_generic2;
typedef union T32Gbl_sw_generic3
{ UNSG32 u32;
struct w32Gbl_sw_generic3;
} T32Gbl_sw_generic3;
typedef union T32Gbl_RWTC_gfx3D31to0
{ UNSG32 u32;
struct w32Gbl_RWTC_gfx3D31to0;
} T32Gbl_RWTC_gfx3D31to0;
typedef union T32Gbl_RWTC_gfx3D57to32
{ UNSG32 u32;
struct w32Gbl_RWTC_gfx3D57to32;
} T32Gbl_RWTC_gfx3D57to32;
typedef union T32Gbl_RWTC_top31to0
{ UNSG32 u32;
struct w32Gbl_RWTC_top31to0;
} T32Gbl_RWTC_top31to0;
typedef union T32Gbl_RWTC_top57to32
{ UNSG32 u32;
struct w32Gbl_RWTC_top57to32;
} T32Gbl_RWTC_top57to32;
typedef union T32Gbl_RWTC_vPro31to0
{ UNSG32 u32;
struct w32Gbl_RWTC_vPro31to0;
} T32Gbl_RWTC_vPro31to0;
typedef union T32Gbl_RWTC_vPro57to32
{ UNSG32 u32;
struct w32Gbl_RWTC_vPro57to32;
} T32Gbl_RWTC_vPro57to32;
typedef union T32Gbl_RWTC_g1Wrap31to0
{ UNSG32 u32;
struct w32Gbl_RWTC_g1Wrap31to0;
} T32Gbl_RWTC_g1Wrap31to0;
typedef union T32Gbl_RWTC_g1Wrap57to32
{ UNSG32 u32;
struct w32Gbl_RWTC_g1Wrap57to32;
} T32Gbl_RWTC_g1Wrap57to32;
typedef union T32Gbl_RWTC_mr7to0
{ UNSG32 u32;
struct w32Gbl_RWTC_mr7to0;
} T32Gbl_RWTC_mr7to0;
typedef union T32Gbl_FPGAR
{ UNSG32 u32;
struct w32Gbl_FPGAR;
} T32Gbl_FPGAR;
typedef union T32Gbl_FPGARW
{ UNSG32 u32;
struct w32Gbl_FPGARW;
} T32Gbl_FPGARW;
typedef union T32Gbl_ResetTrigger
{ UNSG32 u32;
struct w32Gbl_ResetTrigger;
} T32Gbl_ResetTrigger;
typedef union T32Gbl_ResetStatus
{ UNSG32 u32;
struct w32Gbl_ResetStatus;
} T32Gbl_ResetStatus;
typedef union T32Gbl_gfx3DReset
{ UNSG32 u32;
struct w32Gbl_gfx3DReset;
} T32Gbl_gfx3DReset;
typedef union T32Gbl_gfx3DResetStatus
{ UNSG32 u32;
struct w32Gbl_gfx3DResetStatus;
} T32Gbl_gfx3DResetStatus;
typedef union T32Gbl_clkEnable
{ UNSG32 u32;
struct w32Gbl_clkEnable;
} T32Gbl_clkEnable;
typedef union T32Gbl_ClkSwitch
{ UNSG32 u32;
struct w32Gbl_ClkSwitch;
} T32Gbl_ClkSwitch;
typedef union T32Gbl_SECURE_SCAN_EN
{ UNSG32 u32;
struct w32Gbl_SECURE_SCAN_EN;
} T32Gbl_SECURE_SCAN_EN;
typedef union T32Gbl_NandCtrl
{ UNSG32 u32;
struct w32Gbl_NandCtrl;
} T32Gbl_NandCtrl;
typedef union T32Gbl_sdioDllMstCtrl
{ UNSG32 u32;
struct w32Gbl_sdioDllMstCtrl;
} T32Gbl_sdioDllMstCtrl;
typedef union T32Gbl_sdioDllMstCtrl1
{ UNSG32 u32;
struct w32Gbl_sdioDllMstCtrl1;
} T32Gbl_sdioDllMstCtrl1;
typedef union T32Gbl_sdioDllMstStatus
{ UNSG32 u32;
struct w32Gbl_sdioDllMstStatus;
} T32Gbl_sdioDllMstStatus;
typedef union T32Gbl_sdioDllMstStatus1
{ UNSG32 u32;
struct w32Gbl_sdioDllMstStatus1;
} T32Gbl_sdioDllMstStatus1;
typedef union T32Gbl_gfx3DDisRamClkGate
{ UNSG32 u32;
struct w32Gbl_gfx3DDisRamClkGate;
} T32Gbl_gfx3DDisRamClkGate;
typedef union T32Gbl_DroEn
{ UNSG32 u32;
struct w32Gbl_DroEn;
} T32Gbl_DroEn;
typedef union T32Gbl_DroEn1
{ UNSG32 u32;
struct w32Gbl_DroEn1;
} T32Gbl_DroEn1;
typedef union T32Gbl_DroShift
{ UNSG32 u32;
struct w32Gbl_DroShift;
} T32Gbl_DroShift;
typedef union T32Gbl_DroStatus
{ UNSG32 u32;
struct w32Gbl_DroStatus;
} T32Gbl_DroStatus;
typedef union T32Gbl_DroCounter
{ UNSG32 u32;
struct w32Gbl_DroCounter;
} T32Gbl_DroCounter;
typedef union T32Gbl_gic400_ctrl
{ UNSG32 u32;
struct w32Gbl_gic400_ctrl;
} T32Gbl_gic400_ctrl;
typedef union T32Gbl_SPARE_CTRL_0
{ UNSG32 u32;
struct w32Gbl_SPARE_CTRL_0;
} T32Gbl_SPARE_CTRL_0;
typedef union T32Gbl_SPARE_CTRL_1
{ UNSG32 u32;
struct w32Gbl_SPARE_CTRL_1;
} T32Gbl_SPARE_CTRL_1;
typedef union T32Gbl_SPARE_CTRL_2
{ UNSG32 u32;
struct w32Gbl_SPARE_CTRL_2;
} T32Gbl_SPARE_CTRL_2;
typedef union T32Gbl_SPARE_CTRL_3
{ UNSG32 u32;
struct w32Gbl_SPARE_CTRL_3;
} T32Gbl_SPARE_CTRL_3;
typedef union T32Gbl_PadSelect
{ UNSG32 u32;
struct w32Gbl_PadSelect;
} T32Gbl_PadSelect;
typedef union T32Gbl_DDC_PAD_CTRL
{ UNSG32 u32;
struct w32Gbl_DDC_PAD_CTRL;
} T32Gbl_DDC_PAD_CTRL;
typedef union T32Gbl_pinMuxCntlBus
{ UNSG32 u32;
struct w32Gbl_pinMuxCntlBus;
} T32Gbl_pinMuxCntlBus;
typedef union T32Gbl_pinMuxCntlBus1
{ UNSG32 u32;
struct w32Gbl_pinMuxCntlBus1;
} T32Gbl_pinMuxCntlBus1;
typedef union T32Gbl_pinMuxCntlBus2
{ UNSG32 u32;
struct w32Gbl_pinMuxCntlBus2;
} T32Gbl_pinMuxCntlBus2;
typedef union T32Gbl_pinMuxCntlBus3
{ UNSG32 u32;
struct w32Gbl_pinMuxCntlBus3;
} T32Gbl_pinMuxCntlBus3;
typedef union T32Gbl_URT0_RXDCntl
{ UNSG32 u32;
struct w32Gbl_URT0_RXDCntl;
} T32Gbl_URT0_RXDCntl;
typedef union T32Gbl_URT0_TXDCntl
{ UNSG32 u32;
struct w32Gbl_URT0_TXDCntl;
} T32Gbl_URT0_TXDCntl;
typedef union T32Gbl_SPI1_SS0nCntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SS0nCntl;
} T32Gbl_SPI1_SS0nCntl;
typedef union T32Gbl_SPI1_SS1nCntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SS1nCntl;
} T32Gbl_SPI1_SS1nCntl;
typedef union T32Gbl_SPI1_SS2nCntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SS2nCntl;
} T32Gbl_SPI1_SS2nCntl;
typedef union T32Gbl_SPI1_SCLKCntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SCLKCntl;
} T32Gbl_SPI1_SCLKCntl;
typedef union T32Gbl_SPI1_SDOCntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SDOCntl;
} T32Gbl_SPI1_SDOCntl;
typedef union T32Gbl_SPI1_SDICntl
{ UNSG32 u32;
struct w32Gbl_SPI1_SDICntl;
} T32Gbl_SPI1_SDICntl;
typedef union T32Gbl_USB1_DRV_VBUSCntl
{ UNSG32 u32;
struct w32Gbl_USB1_DRV_VBUSCntl;
} T32Gbl_USB1_DRV_VBUSCntl;
typedef union T32Gbl_NAND_IO0Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO0Cntl;
} T32Gbl_NAND_IO0Cntl;
typedef union T32Gbl_NAND_IO1Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO1Cntl;
} T32Gbl_NAND_IO1Cntl;
typedef union T32Gbl_NAND_IO2Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO2Cntl;
} T32Gbl_NAND_IO2Cntl;
typedef union T32Gbl_NAND_IO3Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO3Cntl;
} T32Gbl_NAND_IO3Cntl;
typedef union T32Gbl_NAND_IO4Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO4Cntl;
} T32Gbl_NAND_IO4Cntl;
typedef union T32Gbl_NAND_IO5Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO5Cntl;
} T32Gbl_NAND_IO5Cntl;
typedef union T32Gbl_NAND_IO6Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO6Cntl;
} T32Gbl_NAND_IO6Cntl;
typedef union T32Gbl_NAND_IO7Cntl
{ UNSG32 u32;
struct w32Gbl_NAND_IO7Cntl;
} T32Gbl_NAND_IO7Cntl;
typedef union T32Gbl_NAND_ALECntl
{ UNSG32 u32;
struct w32Gbl_NAND_ALECntl;
} T32Gbl_NAND_ALECntl;
typedef union T32Gbl_NAND_CLECntl
{ UNSG32 u32;
struct w32Gbl_NAND_CLECntl;
} T32Gbl_NAND_CLECntl;
typedef union T32Gbl_NAND_WEnCntl
{ UNSG32 u32;
struct w32Gbl_NAND_WEnCntl;
} T32Gbl_NAND_WEnCntl;
typedef union T32Gbl_NAND_REnCntl
{ UNSG32 u32;
struct w32Gbl_NAND_REnCntl;
} T32Gbl_NAND_REnCntl;
typedef union T32Gbl_NAND_WPnCntl
{ UNSG32 u32;
struct w32Gbl_NAND_WPnCntl;
} T32Gbl_NAND_WPnCntl;
typedef union T32Gbl_NAND_CEnCntl
{ UNSG32 u32;
struct w32Gbl_NAND_CEnCntl;
} T32Gbl_NAND_CEnCntl;
typedef union T32Gbl_NAND_RDYCntl
{ UNSG32 u32;
struct w32Gbl_NAND_RDYCntl;
} T32Gbl_NAND_RDYCntl;
typedef union T32Gbl_SD0_CLKCntl
{ UNSG32 u32;
struct w32Gbl_SD0_CLKCntl;
} T32Gbl_SD0_CLKCntl;
typedef union T32Gbl_SD0_DAT0Cntl
{ UNSG32 u32;
struct w32Gbl_SD0_DAT0Cntl;
} T32Gbl_SD0_DAT0Cntl;
typedef union T32Gbl_SD0_DAT1Cntl
{ UNSG32 u32;
struct w32Gbl_SD0_DAT1Cntl;
} T32Gbl_SD0_DAT1Cntl;
typedef union T32Gbl_SD0_DAT2Cntl
{ UNSG32 u32;
struct w32Gbl_SD0_DAT2Cntl;
} T32Gbl_SD0_DAT2Cntl;
typedef union T32Gbl_SD0_DAT3Cntl
{ UNSG32 u32;
struct w32Gbl_SD0_DAT3Cntl;
} T32Gbl_SD0_DAT3Cntl;
typedef union T32Gbl_SD0_CDnCntl
{ UNSG32 u32;
struct w32Gbl_SD0_CDnCntl;
} T32Gbl_SD0_CDnCntl;
typedef union T32Gbl_SD0_CMDCntl
{ UNSG32 u32;
struct w32Gbl_SD0_CMDCntl;
} T32Gbl_SD0_CMDCntl;
typedef union T32Gbl_SD0_WPCntl
{ UNSG32 u32;
struct w32Gbl_SD0_WPCntl;
} T32Gbl_SD0_WPCntl;
typedef union T32Gbl_STS0_CLKCntl
{ UNSG32 u32;
struct w32Gbl_STS0_CLKCntl;
} T32Gbl_STS0_CLKCntl;
typedef union T32Gbl_STS0_SOPCntl
{ UNSG32 u32;
struct w32Gbl_STS0_SOPCntl;
} T32Gbl_STS0_SOPCntl;
typedef union T32Gbl_STS0_VALDCntl
{ UNSG32 u32;
struct w32Gbl_STS0_VALDCntl;
} T32Gbl_STS0_VALDCntl;
typedef union T32Gbl_STS0_SDCntl
{ UNSG32 u32;
struct w32Gbl_STS0_SDCntl;
} T32Gbl_STS0_SDCntl;
///////////////////////////////////////////////////////////
typedef union TGbl_ProductId
{ UNSG32 u32[1];
struct {
struct w32Gbl_ProductId;
};
} TGbl_ProductId;
typedef union TGbl_ProductId_ext
{ UNSG32 u32[1];
struct {
struct w32Gbl_ProductId_ext;
};
} TGbl_ProductId_ext;
typedef union TGbl_INT_ID
{ UNSG32 u32[1];
struct {
struct w32Gbl_INT_ID;
};
} TGbl_INT_ID;
typedef union TGbl_bootStrap
{ UNSG32 u32[1];
struct {
struct w32Gbl_bootStrap;
};
} TGbl_bootStrap;
typedef union TGbl_bootStrapEn
{ UNSG32 u32[1];
struct {
struct w32Gbl_bootStrapEn;
};
} TGbl_bootStrapEn;
typedef union TGbl_chipCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_chipCntl;
};
} TGbl_chipCntl;
typedef union TGbl_sw_generic0
{ UNSG32 u32[1];
struct {
struct w32Gbl_sw_generic0;
};
} TGbl_sw_generic0;
typedef union TGbl_sw_generic1
{ UNSG32 u32[1];
struct {
struct w32Gbl_sw_generic1;
};
} TGbl_sw_generic1;
typedef union TGbl_sw_generic2
{ UNSG32 u32[1];
struct {
struct w32Gbl_sw_generic2;
};
} TGbl_sw_generic2;
typedef union TGbl_sw_generic3
{ UNSG32 u32[1];
struct {
struct w32Gbl_sw_generic3;
};
} TGbl_sw_generic3;
typedef union TGbl_RWTC_gfx3D31to0
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_gfx3D31to0;
};
} TGbl_RWTC_gfx3D31to0;
typedef union TGbl_RWTC_gfx3D57to32
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_gfx3D57to32;
};
} TGbl_RWTC_gfx3D57to32;
typedef union TGbl_RWTC_top31to0
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_top31to0;
};
} TGbl_RWTC_top31to0;
typedef union TGbl_RWTC_top57to32
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_top57to32;
};
} TGbl_RWTC_top57to32;
typedef union TGbl_RWTC_vPro31to0
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_vPro31to0;
};
} TGbl_RWTC_vPro31to0;
typedef union TGbl_RWTC_vPro57to32
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_vPro57to32;
};
} TGbl_RWTC_vPro57to32;
typedef union TGbl_RWTC_g1Wrap31to0
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_g1Wrap31to0;
};
} TGbl_RWTC_g1Wrap31to0;
typedef union TGbl_RWTC_g1Wrap57to32
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_g1Wrap57to32;
};
} TGbl_RWTC_g1Wrap57to32;
typedef union TGbl_RWTC_mr7to0
{ UNSG32 u32[1];
struct {
struct w32Gbl_RWTC_mr7to0;
};
} TGbl_RWTC_mr7to0;
typedef union TGbl_FPGAR
{ UNSG32 u32[1];
struct {
struct w32Gbl_FPGAR;
};
} TGbl_FPGAR;
typedef union TGbl_FPGARW
{ UNSG32 u32[1];
struct {
struct w32Gbl_FPGARW;
};
} TGbl_FPGARW;
typedef union TGbl_ResetTrigger
{ UNSG32 u32[1];
struct {
struct w32Gbl_ResetTrigger;
};
} TGbl_ResetTrigger;
typedef union TGbl_ResetStatus
{ UNSG32 u32[1];
struct {
struct w32Gbl_ResetStatus;
};
} TGbl_ResetStatus;
typedef union TGbl_gfx3DReset
{ UNSG32 u32[1];
struct {
struct w32Gbl_gfx3DReset;
};
} TGbl_gfx3DReset;
typedef union TGbl_gfx3DResetStatus
{ UNSG32 u32[1];
struct {
struct w32Gbl_gfx3DResetStatus;
};
} TGbl_gfx3DResetStatus;
typedef union TGbl_clkEnable
{ UNSG32 u32[1];
struct {
struct w32Gbl_clkEnable;
};
} TGbl_clkEnable;
typedef union TGbl_ClkSwitch
{ UNSG32 u32[1];
struct {
struct w32Gbl_ClkSwitch;
};
} TGbl_ClkSwitch;
typedef union TGbl_SECURE_SCAN_EN
{ UNSG32 u32[1];
struct {
struct w32Gbl_SECURE_SCAN_EN;
};
} TGbl_SECURE_SCAN_EN;
typedef union TGbl_NandCtrl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NandCtrl;
};
} TGbl_NandCtrl;
typedef union TGbl_sdioDllMstCtrl
{ UNSG32 u32[2];
struct {
struct w32Gbl_sdioDllMstCtrl;
struct w32Gbl_sdioDllMstCtrl1;
};
} TGbl_sdioDllMstCtrl;
typedef union TGbl_sdioDllMstStatus
{ UNSG32 u32[2];
struct {
struct w32Gbl_sdioDllMstStatus;
struct w32Gbl_sdioDllMstStatus1;
};
} TGbl_sdioDllMstStatus;
typedef union TGbl_gfx3DDisRamClkGate
{ UNSG32 u32[1];
struct {
struct w32Gbl_gfx3DDisRamClkGate;
};
} TGbl_gfx3DDisRamClkGate;
typedef union TGbl_DroEn
{ UNSG32 u32[2];
struct {
struct w32Gbl_DroEn;
struct w32Gbl_DroEn1;
};
} TGbl_DroEn;
typedef union TGbl_DroShift
{ UNSG32 u32[1];
struct {
struct w32Gbl_DroShift;
};
} TGbl_DroShift;
typedef union TGbl_DroStatus
{ UNSG32 u32[1];
struct {
struct w32Gbl_DroStatus;
};
} TGbl_DroStatus;
typedef union TGbl_DroCounter
{ UNSG32 u32[1];
struct {
struct w32Gbl_DroCounter;
};
} TGbl_DroCounter;
typedef union TGbl_gic400_ctrl
{ UNSG32 u32[1];
struct {
struct w32Gbl_gic400_ctrl;
};
} TGbl_gic400_ctrl;
typedef union TGbl_SPARE_CTRL_0
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPARE_CTRL_0;
};
} TGbl_SPARE_CTRL_0;
typedef union TGbl_SPARE_CTRL_1
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPARE_CTRL_1;
};
} TGbl_SPARE_CTRL_1;
typedef union TGbl_SPARE_CTRL_2
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPARE_CTRL_2;
};
} TGbl_SPARE_CTRL_2;
typedef union TGbl_SPARE_CTRL_3
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPARE_CTRL_3;
};
} TGbl_SPARE_CTRL_3;
typedef union TGbl_PadSelect
{ UNSG32 u32[1];
struct {
struct w32Gbl_PadSelect;
};
} TGbl_PadSelect;
typedef union TGbl_DDC_PAD_CTRL
{ UNSG32 u32[1];
struct {
struct w32Gbl_DDC_PAD_CTRL;
};
} TGbl_DDC_PAD_CTRL;
typedef union TGbl_pinMuxCntlBus
{ UNSG32 u32[4];
struct {
struct w32Gbl_pinMuxCntlBus;
struct w32Gbl_pinMuxCntlBus1;
struct w32Gbl_pinMuxCntlBus2;
struct w32Gbl_pinMuxCntlBus3;
};
} TGbl_pinMuxCntlBus;
typedef union TGbl_URT0_RXDCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_URT0_RXDCntl;
};
} TGbl_URT0_RXDCntl;
typedef union TGbl_URT0_TXDCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_URT0_TXDCntl;
};
} TGbl_URT0_TXDCntl;
typedef union TGbl_SPI1_SS0nCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SS0nCntl;
};
} TGbl_SPI1_SS0nCntl;
typedef union TGbl_SPI1_SS1nCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SS1nCntl;
};
} TGbl_SPI1_SS1nCntl;
typedef union TGbl_SPI1_SS2nCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SS2nCntl;
};
} TGbl_SPI1_SS2nCntl;
typedef union TGbl_SPI1_SCLKCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SCLKCntl;
};
} TGbl_SPI1_SCLKCntl;
typedef union TGbl_SPI1_SDOCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SDOCntl;
};
} TGbl_SPI1_SDOCntl;
typedef union TGbl_SPI1_SDICntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SPI1_SDICntl;
};
} TGbl_SPI1_SDICntl;
typedef union TGbl_USB1_DRV_VBUSCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_USB1_DRV_VBUSCntl;
};
} TGbl_USB1_DRV_VBUSCntl;
typedef union TGbl_NAND_IO0Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO0Cntl;
};
} TGbl_NAND_IO0Cntl;
typedef union TGbl_NAND_IO1Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO1Cntl;
};
} TGbl_NAND_IO1Cntl;
typedef union TGbl_NAND_IO2Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO2Cntl;
};
} TGbl_NAND_IO2Cntl;
typedef union TGbl_NAND_IO3Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO3Cntl;
};
} TGbl_NAND_IO3Cntl;
typedef union TGbl_NAND_IO4Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO4Cntl;
};
} TGbl_NAND_IO4Cntl;
typedef union TGbl_NAND_IO5Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO5Cntl;
};
} TGbl_NAND_IO5Cntl;
typedef union TGbl_NAND_IO6Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO6Cntl;
};
} TGbl_NAND_IO6Cntl;
typedef union TGbl_NAND_IO7Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_IO7Cntl;
};
} TGbl_NAND_IO7Cntl;
typedef union TGbl_NAND_ALECntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_ALECntl;
};
} TGbl_NAND_ALECntl;
typedef union TGbl_NAND_CLECntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_CLECntl;
};
} TGbl_NAND_CLECntl;
typedef union TGbl_NAND_WEnCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_WEnCntl;
};
} TGbl_NAND_WEnCntl;
typedef union TGbl_NAND_REnCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_REnCntl;
};
} TGbl_NAND_REnCntl;
typedef union TGbl_NAND_WPnCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_WPnCntl;
};
} TGbl_NAND_WPnCntl;
typedef union TGbl_NAND_CEnCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_CEnCntl;
};
} TGbl_NAND_CEnCntl;
typedef union TGbl_NAND_RDYCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_NAND_RDYCntl;
};
} TGbl_NAND_RDYCntl;
typedef union TGbl_SD0_CLKCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_CLKCntl;
};
} TGbl_SD0_CLKCntl;
typedef union TGbl_SD0_DAT0Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_DAT0Cntl;
};
} TGbl_SD0_DAT0Cntl;
typedef union TGbl_SD0_DAT1Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_DAT1Cntl;
};
} TGbl_SD0_DAT1Cntl;
typedef union TGbl_SD0_DAT2Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_DAT2Cntl;
};
} TGbl_SD0_DAT2Cntl;
typedef union TGbl_SD0_DAT3Cntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_DAT3Cntl;
};
} TGbl_SD0_DAT3Cntl;
typedef union TGbl_SD0_CDnCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_CDnCntl;
};
} TGbl_SD0_CDnCntl;
typedef union TGbl_SD0_CMDCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_CMDCntl;
};
} TGbl_SD0_CMDCntl;
typedef union TGbl_SD0_WPCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_SD0_WPCntl;
};
} TGbl_SD0_WPCntl;
typedef union TGbl_STS0_CLKCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_STS0_CLKCntl;
};
} TGbl_STS0_CLKCntl;
typedef union TGbl_STS0_SOPCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_STS0_SOPCntl;
};
} TGbl_STS0_SOPCntl;
typedef union TGbl_STS0_VALDCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_STS0_VALDCntl;
};
} TGbl_STS0_VALDCntl;
typedef union TGbl_STS0_SDCntl
{ UNSG32 u32[1];
struct {
struct w32Gbl_STS0_SDCntl;
};
} TGbl_STS0_SDCntl;
///////////////////////////////////////////////////////////
SIGN32 Gbl_drvrd(SIE_Gbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 Gbl_drvwr(SIE_Gbl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void Gbl_reset(SIE_Gbl *p);
SIGN32 Gbl_cmp (SIE_Gbl *p, SIE_Gbl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define Gbl_check(p,pie,pfx,hLOG) Gbl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define Gbl_print(p, pfx,hLOG) Gbl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: Gbl
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: global.h
////////////////////////////////////////////////////////////