| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| #ifndef __RA_MctrlDual__H__ |
| #define __RA_MctrlDual__H__ |
| |
| #define RA_seSetting_setting 0x0000 |
| #define BA_seSetting_setting_startAddr3116 0x0000 |
| #define B16seSetting_setting_startAddr3116 0x0000 |
| #define LSb32seSetting_setting_startAddr3116 0 |
| #define LSb16seSetting_setting_startAddr3116 0 |
| #define bseSetting_setting_startAddr3116 16 |
| #define MSK32seSetting_setting_startAddr3116 0x0000FFFF |
| #define BA_seSetting_setting_regionSize 0x0002 |
| #define B16seSetting_setting_regionSize 0x0002 |
| #define LSb32seSetting_setting_regionSize 16 |
| #define LSb16seSetting_setting_regionSize 0 |
| #define bseSetting_setting_regionSize 4 |
| #define MSK32seSetting_setting_regionSize 0x000F0000 |
| #define seSetting_setting_regionSize_size64KB 0x0 |
| #define seSetting_setting_regionSize_size128KB 0x1 |
| #define seSetting_setting_regionSize_size256KB 0x2 |
| #define seSetting_setting_regionSize_size512KB 0x3 |
| #define seSetting_setting_regionSize_size1MB 0x4 |
| #define seSetting_setting_regionSize_size2MB 0x5 |
| #define seSetting_setting_regionSize_size4MB 0x6 |
| #define seSetting_setting_regionSize_size8MB 0x7 |
| #define seSetting_setting_regionSize_size16MB 0x8 |
| #define seSetting_setting_regionSize_size32MB 0x9 |
| #define seSetting_setting_regionSize_size64MB 0xA |
| #define seSetting_setting_regionSize_size128MB 0xB |
| #define seSetting_setting_regionSize_size256MB 0xC |
| #define seSetting_setting_regionSize_size512MB 0xD |
| #define BA_seSetting_setting_enable 0x0002 |
| #define B16seSetting_setting_enable 0x0002 |
| #define LSb32seSetting_setting_enable 20 |
| #define LSb16seSetting_setting_enable 4 |
| #define bseSetting_setting_enable 1 |
| #define MSK32seSetting_setting_enable 0x00100000 |
| #define RA_seRegion_CTRL0 0x0000 |
| #define RA_seRegion_CTRL1 0x0004 |
| #define RA_seRegion_CTRL2 0x0008 |
| #define RA_seRegion_CTRL3 0x000C |
| #define RA_seRegion_CTRL4 0x0010 |
| #define RA_seRegion_CTRL5 0x0014 |
| #define RA_seRegion_CTRL6 0x0018 |
| #define RA_seRegion_CTRL7 0x001C |
| #define RA_ACCTX_CPU0WMEM 0x0000 |
| #define RA_ACCTX_CPU0RMEM 0x0020 |
| #define RA_ACCTX_PERIFMSTWMEM 0x0040 |
| #define RA_ACCTX_PERIFMSTRMEM 0x0060 |
| #define RA_DRV_TERM_Ctrl 0x0000 |
| #define BA_DRV_TERM_Ctrl_WCK_DLY 0x0000 |
| #define B16DRV_TERM_Ctrl_WCK_DLY 0x0000 |
| #define LSb32DRV_TERM_Ctrl_WCK_DLY 0 |
| #define LSb16DRV_TERM_Ctrl_WCK_DLY 0 |
| #define bDRV_TERM_Ctrl_WCK_DLY 3 |
| #define MSK32DRV_TERM_Ctrl_WCK_DLY 0x00000007 |
| #define BA_DRV_TERM_Ctrl_ZPDRV 0x0000 |
| #define B16DRV_TERM_Ctrl_ZPDRV 0x0000 |
| #define LSb32DRV_TERM_Ctrl_ZPDRV 3 |
| #define LSb16DRV_TERM_Ctrl_ZPDRV 3 |
| #define bDRV_TERM_Ctrl_ZPDRV 4 |
| #define MSK32DRV_TERM_Ctrl_ZPDRV 0x00000078 |
| #define BA_DRV_TERM_Ctrl_ZNDRV 0x0000 |
| #define B16DRV_TERM_Ctrl_ZNDRV 0x0000 |
| #define LSb32DRV_TERM_Ctrl_ZNDRV 7 |
| #define LSb16DRV_TERM_Ctrl_ZNDRV 7 |
| #define bDRV_TERM_Ctrl_ZNDRV 4 |
| #define MSK32DRV_TERM_Ctrl_ZNDRV 0x00000780 |
| #define BA_DRV_TERM_Ctrl_ZPTRM 0x0001 |
| #define B16DRV_TERM_Ctrl_ZPTRM 0x0000 |
| #define LSb32DRV_TERM_Ctrl_ZPTRM 11 |
| #define LSb16DRV_TERM_Ctrl_ZPTRM 11 |
| #define bDRV_TERM_Ctrl_ZPTRM 4 |
| #define MSK32DRV_TERM_Ctrl_ZPTRM 0x00007800 |
| #define BA_DRV_TERM_Ctrl_ZNTRM 0x0001 |
| #define B16DRV_TERM_Ctrl_ZNTRM 0x0000 |
| #define LSb32DRV_TERM_Ctrl_ZNTRM 15 |
| #define LSb16DRV_TERM_Ctrl_ZNTRM 15 |
| #define bDRV_TERM_Ctrl_ZNTRM 4 |
| #define MSK32DRV_TERM_Ctrl_ZNTRM 0x00078000 |
| #define BA_DRV_TERM_Ctrl_VREF_SEL 0x0002 |
| #define B16DRV_TERM_Ctrl_VREF_SEL 0x0002 |
| #define LSb32DRV_TERM_Ctrl_VREF_SEL 19 |
| #define LSb16DRV_TERM_Ctrl_VREF_SEL 3 |
| #define bDRV_TERM_Ctrl_VREF_SEL 2 |
| #define MSK32DRV_TERM_Ctrl_VREF_SEL 0x00180000 |
| #define BA_DRV_TERM_Ctrl_ZPR 0x0002 |
| #define B16DRV_TERM_Ctrl_ZPR 0x0002 |
| #define LSb32DRV_TERM_Ctrl_ZPR 21 |
| #define LSb16DRV_TERM_Ctrl_ZPR 5 |
| #define bDRV_TERM_Ctrl_ZPR 4 |
| #define MSK32DRV_TERM_Ctrl_ZPR 0x01E00000 |
| #define BA_DRV_TERM_Ctrl_ZNR 0x0003 |
| #define B16DRV_TERM_Ctrl_ZNR 0x0002 |
| #define LSb32DRV_TERM_Ctrl_ZNR 25 |
| #define LSb16DRV_TERM_Ctrl_ZNR 9 |
| #define bDRV_TERM_Ctrl_ZNR 4 |
| #define MSK32DRV_TERM_Ctrl_ZNR 0x1E000000 |
| #define BA_DRV_TERM_Ctrl_ZD 0x0003 |
| #define B16DRV_TERM_Ctrl_ZD 0x0002 |
| #define LSb32DRV_TERM_Ctrl_ZD 29 |
| #define LSb16DRV_TERM_Ctrl_ZD 13 |
| #define bDRV_TERM_Ctrl_ZD 1 |
| #define MSK32DRV_TERM_Ctrl_ZD 0x20000000 |
| #define BA_DRV_TERM_Ctrl_MODE 0x0003 |
| #define B16DRV_TERM_Ctrl_MODE 0x0002 |
| #define LSb32DRV_TERM_Ctrl_MODE 30 |
| #define LSb16DRV_TERM_Ctrl_MODE 14 |
| #define bDRV_TERM_Ctrl_MODE 1 |
| #define MSK32DRV_TERM_Ctrl_MODE 0x40000000 |
| #define BA_DRV_TERM_Ctrl_PD 0x0003 |
| #define B16DRV_TERM_Ctrl_PD 0x0002 |
| #define LSb32DRV_TERM_Ctrl_PD 31 |
| #define LSb16DRV_TERM_Ctrl_PD 15 |
| #define bDRV_TERM_Ctrl_PD 1 |
| #define MSK32DRV_TERM_Ctrl_PD 0x80000000 |
| #define RA_DRV_TERM_rcvCtrl 0x0004 |
| #define BA_DRV_TERM_rcvCtrl_RCVTYPE 0x0004 |
| #define B16DRV_TERM_rcvCtrl_RCVTYPE 0x0004 |
| #define LSb32DRV_TERM_rcvCtrl_RCVTYPE 0 |
| #define LSb16DRV_TERM_rcvCtrl_RCVTYPE 0 |
| #define bDRV_TERM_rcvCtrl_RCVTYPE 1 |
| #define MSK32DRV_TERM_rcvCtrl_RCVTYPE 0x00000001 |
| #define BA_DRV_TERM_rcvCtrl_RCVEN 0x0004 |
| #define B16DRV_TERM_rcvCtrl_RCVEN 0x0004 |
| #define LSb32DRV_TERM_rcvCtrl_RCVEN 1 |
| #define LSb16DRV_TERM_rcvCtrl_RCVEN 1 |
| #define bDRV_TERM_rcvCtrl_RCVEN 3 |
| #define MSK32DRV_TERM_rcvCtrl_RCVEN 0x0000000E |
| #define BA_DRV_TERM_rcvCtrl_RCVEP 0x0004 |
| #define B16DRV_TERM_rcvCtrl_RCVEP 0x0004 |
| #define LSb32DRV_TERM_rcvCtrl_RCVEP 4 |
| #define LSb16DRV_TERM_rcvCtrl_RCVEP 4 |
| #define bDRV_TERM_rcvCtrl_RCVEP 3 |
| #define MSK32DRV_TERM_rcvCtrl_RCVEP 0x00000070 |
| #define BA_DLL_DELAY_DELAY_TEST_VAL 0x0000 |
| #define B16DLL_DELAY_DELAY_TEST_VAL 0x0000 |
| #define LSb32DLL_DELAY_DELAY_TEST_VAL 0 |
| #define LSb16DLL_DELAY_DELAY_TEST_VAL 0 |
| #define bDLL_DELAY_DELAY_TEST_VAL 9 |
| #define MSK32DLL_DELAY_DELAY_TEST_VAL 0x000001FF |
| #define BA_DLL_DELAY_PHASE_SEL_VAL 0x0001 |
| #define B16DLL_DELAY_PHASE_SEL_VAL 0x0000 |
| #define LSb32DLL_DELAY_PHASE_SEL_VAL 9 |
| #define LSb16DLL_DELAY_PHASE_SEL_VAL 9 |
| #define bDLL_DELAY_PHASE_SEL_VAL 5 |
| #define MSK32DLL_DELAY_PHASE_SEL_VAL 0x00003E00 |
| #define RA_PHY_Timing 0x0000 |
| #define BA_PHY_Timing_rlat 0x0000 |
| #define B16PHY_Timing_rlat 0x0000 |
| #define LSb32PHY_Timing_rlat 0 |
| #define LSb16PHY_Timing_rlat 0 |
| #define bPHY_Timing_rlat 3 |
| #define MSK32PHY_Timing_rlat 0x00000007 |
| #define BA_PHY_Timing_en2vld 0x0000 |
| #define B16PHY_Timing_en2vld 0x0000 |
| #define LSb32PHY_Timing_en2vld 3 |
| #define LSb16PHY_Timing_en2vld 3 |
| #define bPHY_Timing_en2vld 3 |
| #define MSK32PHY_Timing_en2vld 0x00000038 |
| #define BA_PHY_Timing_full_preamble 0x0000 |
| #define B16PHY_Timing_full_preamble 0x0000 |
| #define LSb32PHY_Timing_full_preamble 6 |
| #define LSb16PHY_Timing_full_preamble 6 |
| #define bPHY_Timing_full_preamble 1 |
| #define MSK32PHY_Timing_full_preamble 0x00000040 |
| #define RA_PHY_Enable 0x0004 |
| #define BA_PHY_Enable_OEAC 0x0004 |
| #define B16PHY_Enable_OEAC 0x0004 |
| #define LSb32PHY_Enable_OEAC 0 |
| #define LSb16PHY_Enable_OEAC 0 |
| #define bPHY_Enable_OEAC 1 |
| #define MSK32PHY_Enable_OEAC 0x00000001 |
| #define BA_PHY_Enable_OECK 0x0004 |
| #define B16PHY_Enable_OECK 0x0004 |
| #define LSb32PHY_Enable_OECK 1 |
| #define LSb16PHY_Enable_OECK 1 |
| #define bPHY_Enable_OECK 1 |
| #define MSK32PHY_Enable_OECK 0x00000002 |
| #define BA_PHY_Enable_OERST 0x0004 |
| #define B16PHY_Enable_OERST 0x0004 |
| #define LSb32PHY_Enable_OERST 2 |
| #define LSb16PHY_Enable_OERST 2 |
| #define bPHY_Enable_OERST 1 |
| #define MSK32PHY_Enable_OERST 0x00000004 |
| #define BA_PHY_Enable_AC_RECEN 0x0004 |
| #define B16PHY_Enable_AC_RECEN 0x0004 |
| #define LSb32PHY_Enable_AC_RECEN 3 |
| #define LSb16PHY_Enable_AC_RECEN 3 |
| #define bPHY_Enable_AC_RECEN 1 |
| #define MSK32PHY_Enable_AC_RECEN 0x00000008 |
| #define BA_PHY_Enable_CK_RECEN 0x0004 |
| #define B16PHY_Enable_CK_RECEN 0x0004 |
| #define LSb32PHY_Enable_CK_RECEN 4 |
| #define LSb16PHY_Enable_CK_RECEN 4 |
| #define bPHY_Enable_CK_RECEN 1 |
| #define MSK32PHY_Enable_CK_RECEN 0x00000010 |
| #define BA_PHY_Enable_RST_RECEN 0x0004 |
| #define B16PHY_Enable_RST_RECEN 0x0004 |
| #define LSb32PHY_Enable_RST_RECEN 5 |
| #define LSb16PHY_Enable_RST_RECEN 5 |
| #define bPHY_Enable_RST_RECEN 1 |
| #define MSK32PHY_Enable_RST_RECEN 0x00000020 |
| #define BA_PHY_Enable_RST_Output 0x0004 |
| #define B16PHY_Enable_RST_Output 0x0004 |
| #define LSb32PHY_Enable_RST_Output 6 |
| #define LSb16PHY_Enable_RST_Output 6 |
| #define bPHY_Enable_RST_Output 1 |
| #define MSK32PHY_Enable_RST_Output 0x00000040 |
| #define RA_PHY_DLL 0x0008 |
| #define BA_PHY_DLL_RESET 0x0008 |
| #define B16PHY_DLL_RESET 0x0008 |
| #define LSb32PHY_DLL_RESET 0 |
| #define LSb16PHY_DLL_RESET 0 |
| #define bPHY_DLL_RESET 1 |
| #define MSK32PHY_DLL_RESET 0x00000001 |
| #define BA_PHY_DLL_BYPASS_EN 0x0008 |
| #define B16PHY_DLL_BYPASS_EN 0x0008 |
| #define LSb32PHY_DLL_BYPASS_EN 1 |
| #define LSb16PHY_DLL_BYPASS_EN 1 |
| #define bPHY_DLL_BYPASS_EN 1 |
| #define MSK32PHY_DLL_BYPASS_EN 0x00000002 |
| #define BA_PHY_DLL_AUTO_UPDATE_EN 0x0008 |
| #define B16PHY_DLL_AUTO_UPDATE_EN 0x0008 |
| #define LSb32PHY_DLL_AUTO_UPDATE_EN 2 |
| #define LSb16PHY_DLL_AUTO_UPDATE_EN 2 |
| #define bPHY_DLL_AUTO_UPDATE_EN 1 |
| #define MSK32PHY_DLL_AUTO_UPDATE_EN 0x00000004 |
| #define BA_PHY_DLL_UPDATE_EN 0x0008 |
| #define B16PHY_DLL_UPDATE_EN 0x0008 |
| #define LSb32PHY_DLL_UPDATE_EN 3 |
| #define LSb16PHY_DLL_UPDATE_EN 3 |
| #define bPHY_DLL_UPDATE_EN 1 |
| #define MSK32PHY_DLL_UPDATE_EN 0x00000008 |
| #define BA_PHY_DLL_UPDATE_MASK 0x0008 |
| #define B16PHY_DLL_UPDATE_MASK 0x0008 |
| #define LSb32PHY_DLL_UPDATE_MASK 4 |
| #define LSb16PHY_DLL_UPDATE_MASK 4 |
| #define bPHY_DLL_UPDATE_MASK 8 |
| #define MSK32PHY_DLL_UPDATE_MASK 0x00000FF0 |
| #define BA_PHY_DLL_DELAY_TEST 0x0009 |
| #define B16PHY_DLL_DELAY_TEST 0x0008 |
| #define LSb32PHY_DLL_DELAY_TEST 12 |
| #define LSb16PHY_DLL_DELAY_TEST 12 |
| #define bPHY_DLL_DELAY_TEST 9 |
| #define MSK32PHY_DLL_DELAY_TEST 0x001FF000 |
| #define BA_PHY_DLL_PHSEL 0x000A |
| #define B16PHY_DLL_PHSEL 0x000A |
| #define LSb32PHY_DLL_PHSEL 21 |
| #define LSb16PHY_DLL_PHSEL 5 |
| #define bPHY_DLL_PHSEL 5 |
| #define MSK32PHY_DLL_PHSEL 0x03E00000 |
| #define BA_PHY_DLL_TEST_EN 0x000B |
| #define B16PHY_DLL_TEST_EN 0x000A |
| #define LSb32PHY_DLL_TEST_EN 26 |
| #define LSb16PHY_DLL_TEST_EN 10 |
| #define bPHY_DLL_TEST_EN 1 |
| #define MSK32PHY_DLL_TEST_EN 0x04000000 |
| #define RA_PHY_DELAY_VAL0 0x000C |
| #define RA_PHY_DELAY_VAL1 0x0010 |
| #define RA_PHY_DELAY_VAL2 0x0014 |
| #define RA_PHY_DELAY_VAL3 0x0018 |
| #define RA_PHY_DELAY_VAL4 0x001C |
| #define RA_PHY_DELAY_VAL5 0x0020 |
| #define RA_PHY_DELAY_VAL6 0x0024 |
| #define RA_PHY_DELAY_VAL7 0x0028 |
| #define RA_PHY_PLL1 0x002C |
| #define BA_PHY_PLL1_RESET 0x002C |
| #define B16PHY_PLL1_RESET 0x002C |
| #define LSb32PHY_PLL1_RESET 0 |
| #define LSb16PHY_PLL1_RESET 0 |
| #define bPHY_PLL1_RESET 1 |
| #define MSK32PHY_PLL1_RESET 0x00000001 |
| #define BA_PHY_PLL1_SYNC_TYPE 0x002C |
| #define B16PHY_PLL1_SYNC_TYPE 0x002C |
| #define LSb32PHY_PLL1_SYNC_TYPE 1 |
| #define LSb16PHY_PLL1_SYNC_TYPE 1 |
| #define bPHY_PLL1_SYNC_TYPE 1 |
| #define MSK32PHY_PLL1_SYNC_TYPE 0x00000002 |
| #define BA_PHY_PLL1_FBDIV 0x002C |
| #define B16PHY_PLL1_FBDIV 0x002C |
| #define LSb32PHY_PLL1_FBDIV 2 |
| #define LSb16PHY_PLL1_FBDIV 2 |
| #define bPHY_PLL1_FBDIV 9 |
| #define MSK32PHY_PLL1_FBDIV 0x000007FC |
| #define BA_PHY_PLL1_FBDLY 0x002D |
| #define B16PHY_PLL1_FBDLY 0x002C |
| #define LSb32PHY_PLL1_FBDLY 11 |
| #define LSb16PHY_PLL1_FBDLY 11 |
| #define bPHY_PLL1_FBDLY 4 |
| #define MSK32PHY_PLL1_FBDLY 0x00007800 |
| #define BA_PHY_PLL1_ICP 0x002D |
| #define B16PHY_PLL1_ICP 0x002C |
| #define LSb32PHY_PLL1_ICP 15 |
| #define LSb16PHY_PLL1_ICP 15 |
| #define bPHY_PLL1_ICP 3 |
| #define MSK32PHY_PLL1_ICP 0x00038000 |
| #define BA_PHY_PLL1_KVCO 0x002E |
| #define B16PHY_PLL1_KVCO 0x002E |
| #define LSb32PHY_PLL1_KVCO 18 |
| #define LSb16PHY_PLL1_KVCO 2 |
| #define bPHY_PLL1_KVCO 3 |
| #define MSK32PHY_PLL1_KVCO 0x001C0000 |
| #define BA_PHY_PLL1_PU_PLL 0x002E |
| #define B16PHY_PLL1_PU_PLL 0x002E |
| #define LSb32PHY_PLL1_PU_PLL 21 |
| #define LSb16PHY_PLL1_PU_PLL 5 |
| #define bPHY_PLL1_PU_PLL 1 |
| #define MSK32PHY_PLL1_PU_PLL 0x00200000 |
| #define RA_PHY_PLL2 0x0030 |
| #define BA_PHY_PLL2_REFDIV 0x0030 |
| #define B16PHY_PLL2_REFDIV 0x0030 |
| #define LSb32PHY_PLL2_REFDIV 0 |
| #define LSb16PHY_PLL2_REFDIV 0 |
| #define bPHY_PLL2_REFDIV 9 |
| #define MSK32PHY_PLL2_REFDIV 0x000001FF |
| #define BA_PHY_PLL2_REFDLY 0x0031 |
| #define B16PHY_PLL2_REFDLY 0x0030 |
| #define LSb32PHY_PLL2_REFDLY 9 |
| #define LSb16PHY_PLL2_REFDLY 9 |
| #define bPHY_PLL2_REFDLY 4 |
| #define MSK32PHY_PLL2_REFDLY 0x00001E00 |
| #define BA_PHY_PLL2_RESERVE 0x0031 |
| #define B16PHY_PLL2_RESERVE 0x0030 |
| #define LSb32PHY_PLL2_RESERVE 13 |
| #define LSb16PHY_PLL2_RESERVE 13 |
| #define bPHY_PLL2_RESERVE 2 |
| #define MSK32PHY_PLL2_RESERVE 0x00006000 |
| #define BA_PHY_PLL2_SEL 0x0031 |
| #define B16PHY_PLL2_SEL 0x0030 |
| #define LSb32PHY_PLL2_SEL 15 |
| #define LSb16PHY_PLL2_SEL 15 |
| #define bPHY_PLL2_SEL 2 |
| #define MSK32PHY_PLL2_SEL 0x00018000 |
| #define BA_PHY_PLL2_TEST_MON 0x0032 |
| #define B16PHY_PLL2_TEST_MON 0x0032 |
| #define LSb32PHY_PLL2_TEST_MON 17 |
| #define LSb16PHY_PLL2_TEST_MON 1 |
| #define bPHY_PLL2_TEST_MON 4 |
| #define MSK32PHY_PLL2_TEST_MON 0x001E0000 |
| #define BA_PHY_PLL2_VCO_VRNG 0x0032 |
| #define B16PHY_PLL2_VCO_VRNG 0x0032 |
| #define LSb32PHY_PLL2_VCO_VRNG 21 |
| #define LSb16PHY_PLL2_VCO_VRNG 5 |
| #define bPHY_PLL2_VCO_VRNG 2 |
| #define MSK32PHY_PLL2_VCO_VRNG 0x00600000 |
| #define BA_PHY_PLL2_VCOFBST 0x0032 |
| #define B16PHY_PLL2_VCOFBST 0x0032 |
| #define LSb32PHY_PLL2_VCOFBST 23 |
| #define LSb16PHY_PLL2_VCOFBST 7 |
| #define bPHY_PLL2_VCOFBST 1 |
| #define MSK32PHY_PLL2_VCOFBST 0x00800000 |
| #define BA_PHY_PLL2_VDDL 0x0033 |
| #define B16PHY_PLL2_VDDL 0x0032 |
| #define LSb32PHY_PLL2_VDDL 24 |
| #define LSb16PHY_PLL2_VDDL 8 |
| #define bPHY_PLL2_VDDL 2 |
| #define MSK32PHY_PLL2_VDDL 0x03000000 |
| #define BA_PHY_PLL2_VDDM 0x0033 |
| #define B16PHY_PLL2_VDDM 0x0032 |
| #define LSb32PHY_PLL2_VDDM 26 |
| #define LSb16PHY_PLL2_VDDM 10 |
| #define bPHY_PLL2_VDDM 2 |
| #define MSK32PHY_PLL2_VDDM 0x0C000000 |
| #define RA_PHY_STS 0x0034 |
| #define BA_PHY_STS_CAL_DONE 0x0034 |
| #define B16PHY_STS_CAL_DONE 0x0034 |
| #define LSb32PHY_STS_CAL_DONE 0 |
| #define LSb16PHY_STS_CAL_DONE 0 |
| #define bPHY_STS_CAL_DONE 1 |
| #define MSK32PHY_STS_CAL_DONE 0x00000001 |
| #define BA_PHY_STS_CAL_ZPR 0x0034 |
| #define B16PHY_STS_CAL_ZPR 0x0034 |
| #define LSb32PHY_STS_CAL_ZPR 1 |
| #define LSb16PHY_STS_CAL_ZPR 1 |
| #define bPHY_STS_CAL_ZPR 4 |
| #define MSK32PHY_STS_CAL_ZPR 0x0000001E |
| #define BA_PHY_STS_CAL_ZNR 0x0034 |
| #define B16PHY_STS_CAL_ZNR 0x0034 |
| #define LSb32PHY_STS_CAL_ZNR 5 |
| #define LSb16PHY_STS_CAL_ZNR 5 |
| #define bPHY_STS_CAL_ZNR 4 |
| #define MSK32PHY_STS_CAL_ZNR 0x000001E0 |
| #define BA_PHY_STS_PLL0_LOCK 0x0035 |
| #define B16PHY_STS_PLL0_LOCK 0x0034 |
| #define LSb32PHY_STS_PLL0_LOCK 9 |
| #define LSb16PHY_STS_PLL0_LOCK 9 |
| #define bPHY_STS_PLL0_LOCK 1 |
| #define MSK32PHY_STS_PLL0_LOCK 0x00000200 |
| #define BA_PHY_STS_PLL1_LOCK 0x0035 |
| #define B16PHY_STS_PLL1_LOCK 0x0034 |
| #define LSb32PHY_STS_PLL1_LOCK 10 |
| #define LSb16PHY_STS_PLL1_LOCK 10 |
| #define bPHY_STS_PLL1_LOCK 1 |
| #define MSK32PHY_STS_PLL1_LOCK 0x00000400 |
| #define BA_PHY_STS_DLL0_DELAY_OUT 0x0035 |
| #define B16PHY_STS_DLL0_DELAY_OUT 0x0034 |
| #define LSb32PHY_STS_DLL0_DELAY_OUT 11 |
| #define LSb16PHY_STS_DLL0_DELAY_OUT 11 |
| #define bPHY_STS_DLL0_DELAY_OUT 8 |
| #define MSK32PHY_STS_DLL0_DELAY_OUT 0x0007F800 |
| #define BA_PHY_STS_DLL1_DELAY_OUT 0x0036 |
| #define B16PHY_STS_DLL1_DELAY_OUT 0x0036 |
| #define LSb32PHY_STS_DLL1_DELAY_OUT 19 |
| #define LSb16PHY_STS_DLL1_DELAY_OUT 3 |
| #define bPHY_STS_DLL1_DELAY_OUT 8 |
| #define MSK32PHY_STS_DLL1_DELAY_OUT 0x07F80000 |
| #define RA_PHY_CH0_DLL_STS 0x0038 |
| #define BA_PHY_CH0_DLL_STS_DLL0_DELAY_OUT 0x0038 |
| #define B16PHY_CH0_DLL_STS_DLL0_DELAY_OUT 0x0038 |
| #define LSb32PHY_CH0_DLL_STS_DLL0_DELAY_OUT 0 |
| #define LSb16PHY_CH0_DLL_STS_DLL0_DELAY_OUT 0 |
| #define bPHY_CH0_DLL_STS_DLL0_DELAY_OUT 8 |
| #define MSK32PHY_CH0_DLL_STS_DLL0_DELAY_OUT 0x000000FF |
| #define BA_PHY_CH0_DLL_STS_DLL1_DELAY_OUT 0x0039 |
| #define B16PHY_CH0_DLL_STS_DLL1_DELAY_OUT 0x0038 |
| #define LSb32PHY_CH0_DLL_STS_DLL1_DELAY_OUT 8 |
| #define LSb16PHY_CH0_DLL_STS_DLL1_DELAY_OUT 8 |
| #define bPHY_CH0_DLL_STS_DLL1_DELAY_OUT 8 |
| #define MSK32PHY_CH0_DLL_STS_DLL1_DELAY_OUT 0x0000FF00 |
| #define BA_PHY_CH0_DLL_STS_DLL2_DELAY_OUT 0x003A |
| #define B16PHY_CH0_DLL_STS_DLL2_DELAY_OUT 0x003A |
| #define LSb32PHY_CH0_DLL_STS_DLL2_DELAY_OUT 16 |
| #define LSb16PHY_CH0_DLL_STS_DLL2_DELAY_OUT 0 |
| #define bPHY_CH0_DLL_STS_DLL2_DELAY_OUT 8 |
| #define MSK32PHY_CH0_DLL_STS_DLL2_DELAY_OUT 0x00FF0000 |
| #define BA_PHY_CH0_DLL_STS_DLL3_DELAY_OUT 0x003B |
| #define B16PHY_CH0_DLL_STS_DLL3_DELAY_OUT 0x003A |
| #define LSb32PHY_CH0_DLL_STS_DLL3_DELAY_OUT 24 |
| #define LSb16PHY_CH0_DLL_STS_DLL3_DELAY_OUT 8 |
| #define bPHY_CH0_DLL_STS_DLL3_DELAY_OUT 8 |
| #define MSK32PHY_CH0_DLL_STS_DLL3_DELAY_OUT 0xFF000000 |
| #define RA_PHY_CH1_DLL_STS 0x003C |
| #define BA_PHY_CH1_DLL_STS_DLL4_DELAY_OUT 0x003C |
| #define B16PHY_CH1_DLL_STS_DLL4_DELAY_OUT 0x003C |
| #define LSb32PHY_CH1_DLL_STS_DLL4_DELAY_OUT 0 |
| #define LSb16PHY_CH1_DLL_STS_DLL4_DELAY_OUT 0 |
| #define bPHY_CH1_DLL_STS_DLL4_DELAY_OUT 8 |
| #define MSK32PHY_CH1_DLL_STS_DLL4_DELAY_OUT 0x000000FF |
| #define BA_PHY_CH1_DLL_STS_DLL5_DELAY_OUT 0x003D |
| #define B16PHY_CH1_DLL_STS_DLL5_DELAY_OUT 0x003C |
| #define LSb32PHY_CH1_DLL_STS_DLL5_DELAY_OUT 8 |
| #define LSb16PHY_CH1_DLL_STS_DLL5_DELAY_OUT 8 |
| #define bPHY_CH1_DLL_STS_DLL5_DELAY_OUT 8 |
| #define MSK32PHY_CH1_DLL_STS_DLL5_DELAY_OUT 0x0000FF00 |
| #define BA_PHY_CH1_DLL_STS_DLL6_DELAY_OUT 0x003E |
| #define B16PHY_CH1_DLL_STS_DLL6_DELAY_OUT 0x003E |
| #define LSb32PHY_CH1_DLL_STS_DLL6_DELAY_OUT 16 |
| #define LSb16PHY_CH1_DLL_STS_DLL6_DELAY_OUT 0 |
| #define bPHY_CH1_DLL_STS_DLL6_DELAY_OUT 8 |
| #define MSK32PHY_CH1_DLL_STS_DLL6_DELAY_OUT 0x00FF0000 |
| #define BA_PHY_CH1_DLL_STS_DLL7_DELAY_OUT 0x003F |
| #define B16PHY_CH1_DLL_STS_DLL7_DELAY_OUT 0x003E |
| #define LSb32PHY_CH1_DLL_STS_DLL7_DELAY_OUT 24 |
| #define LSb16PHY_CH1_DLL_STS_DLL7_DELAY_OUT 8 |
| #define bPHY_CH1_DLL_STS_DLL7_DELAY_OUT 8 |
| #define MSK32PHY_CH1_DLL_STS_DLL7_DELAY_OUT 0xFF000000 |
| #define RA_PHY_DQ 0x0040 |
| #define RA_PHY_DQS 0x0048 |
| #define RA_PHY_ADCM 0x0050 |
| #define RA_PHY_CK 0x0058 |
| #define RA_TTBPort_Setup 0x0000 |
| #define BA_TTBPort_Setup_enable 0x0000 |
| #define B16TTBPort_Setup_enable 0x0000 |
| #define LSb32TTBPort_Setup_enable 0 |
| #define LSb16TTBPort_Setup_enable 0 |
| #define bTTBPort_Setup_enable 1 |
| #define MSK32TTBPort_Setup_enable 0x00000001 |
| #define BA_TTBPort_Setup_interrupt 0x0000 |
| #define B16TTBPort_Setup_interrupt 0x0000 |
| #define LSb32TTBPort_Setup_interrupt 1 |
| #define LSb16TTBPort_Setup_interrupt 1 |
| #define bTTBPort_Setup_interrupt 1 |
| #define MSK32TTBPort_Setup_interrupt 0x00000002 |
| #define BA_TTBPort_Setup_recordInfoSel 0x0000 |
| #define B16TTBPort_Setup_recordInfoSel 0x0000 |
| #define LSb32TTBPort_Setup_recordInfoSel 2 |
| #define LSb16TTBPort_Setup_recordInfoSel 2 |
| #define bTTBPort_Setup_recordInfoSel 2 |
| #define MSK32TTBPort_Setup_recordInfoSel 0x0000000C |
| #define BA_TTBPort_Setup_no_cycle_afterward 0x0000 |
| #define B16TTBPort_Setup_no_cycle_afterward 0x0000 |
| #define LSb32TTBPort_Setup_no_cycle_afterward 4 |
| #define LSb16TTBPort_Setup_no_cycle_afterward 4 |
| #define bTTBPort_Setup_no_cycle_afterward 16 |
| #define MSK32TTBPort_Setup_no_cycle_afterward 0x000FFFF0 |
| #define BA_TTBPort_Setup_RESERVE_MODE 0x0002 |
| #define B16TTBPort_Setup_RESERVE_MODE 0x0002 |
| #define LSb32TTBPort_Setup_RESERVE_MODE 20 |
| #define LSb16TTBPort_Setup_RESERVE_MODE 4 |
| #define bTTBPort_Setup_RESERVE_MODE 12 |
| #define MSK32TTBPort_Setup_RESERVE_MODE 0xFFF00000 |
| #define RA_TTBPort_MonAddr 0x0004 |
| #define BA_TTBPort_MonAddr_RESERVE_MADD 0x0004 |
| #define B16TTBPort_MonAddr_RESERVE_MADD 0x0004 |
| #define LSb32TTBPort_MonAddr_RESERVE_MADD 0 |
| #define LSb16TTBPort_MonAddr_RESERVE_MADD 0 |
| #define bTTBPort_MonAddr_RESERVE_MADD 3 |
| #define MSK32TTBPort_MonAddr_RESERVE_MADD 0x00000007 |
| #define BA_TTBPort_MonAddr_mAddr 0x0004 |
| #define B16TTBPort_MonAddr_mAddr 0x0004 |
| #define LSb32TTBPort_MonAddr_mAddr 3 |
| #define LSb16TTBPort_MonAddr_mAddr 3 |
| #define bTTBPort_MonAddr_mAddr 29 |
| #define MSK32TTBPort_MonAddr_mAddr 0xFFFFFFF8 |
| #define RA_TTBPort_MonAddrMask 0x0008 |
| #define BA_TTBPort_MonAddrMask_RESERVE_MKADD 0x0008 |
| #define B16TTBPort_MonAddrMask_RESERVE_MKADD 0x0008 |
| #define LSb32TTBPort_MonAddrMask_RESERVE_MKADD 0 |
| #define LSb16TTBPort_MonAddrMask_RESERVE_MKADD 0 |
| #define bTTBPort_MonAddrMask_RESERVE_MKADD 3 |
| #define MSK32TTBPort_MonAddrMask_RESERVE_MKADD 0x00000007 |
| #define BA_TTBPort_MonAddrMask_mAddrMask 0x0008 |
| #define B16TTBPort_MonAddrMask_mAddrMask 0x0008 |
| #define LSb32TTBPort_MonAddrMask_mAddrMask 3 |
| #define LSb16TTBPort_MonAddrMask_mAddrMask 3 |
| #define bTTBPort_MonAddrMask_mAddrMask 29 |
| #define MSK32TTBPort_MonAddrMask_mAddrMask 0xFFFFFFF8 |
| #define RA_TTBPort_MonLen 0x000C |
| #define BA_TTBPort_MonLen_mLen 0x000C |
| #define B16TTBPort_MonLen_mLen 0x000C |
| #define LSb32TTBPort_MonLen_mLen 0 |
| #define LSb16TTBPort_MonLen_mLen 0 |
| #define bTTBPort_MonLen_mLen 4 |
| #define MSK32TTBPort_MonLen_mLen 0x0000000F |
| #define BA_TTBPort_MonLen_mLenMask 0x000C |
| #define B16TTBPort_MonLen_mLenMask 0x000C |
| #define LSb32TTBPort_MonLen_mLenMask 4 |
| #define LSb16TTBPort_MonLen_mLenMask 4 |
| #define bTTBPort_MonLen_mLenMask 4 |
| #define MSK32TTBPort_MonLen_mLenMask 0x000000F0 |
| #define BA_TTBPort_MonLen_RESERVE_MLEN 0x000D |
| #define B16TTBPort_MonLen_RESERVE_MLEN 0x000C |
| #define LSb32TTBPort_MonLen_RESERVE_MLEN 8 |
| #define LSb16TTBPort_MonLen_RESERVE_MLEN 8 |
| #define bTTBPort_MonLen_RESERVE_MLEN 24 |
| #define MSK32TTBPort_MonLen_RESERVE_MLEN 0xFFFFFF00 |
| #define RA_TTBPort_Status 0x0010 |
| #define BA_TTBPort_Status_no_of_trigger 0x0010 |
| #define B16TTBPort_Status_no_of_trigger 0x0010 |
| #define LSb32TTBPort_Status_no_of_trigger 0 |
| #define LSb16TTBPort_Status_no_of_trigger 0 |
| #define bTTBPort_Status_no_of_trigger 16 |
| #define MSK32TTBPort_Status_no_of_trigger 0x0000FFFF |
| #define BA_TTBPort_Status_RESERVE_STATUS 0x0012 |
| #define B16TTBPort_Status_RESERVE_STATUS 0x0012 |
| #define LSb32TTBPort_Status_RESERVE_STATUS 16 |
| #define LSb16TTBPort_Status_RESERVE_STATUS 0 |
| #define bTTBPort_Status_RESERVE_STATUS 16 |
| #define MSK32TTBPort_Status_RESERVE_STATUS 0xFFFF0000 |
| #define RA_TTBPort_TriggerAddr 0x0014 |
| #define BA_TTBPort_TriggerAddr_RESERVE_TADDR 0x0014 |
| #define B16TTBPort_TriggerAddr_RESERVE_TADDR 0x0014 |
| #define LSb32TTBPort_TriggerAddr_RESERVE_TADDR 0 |
| #define LSb16TTBPort_TriggerAddr_RESERVE_TADDR 0 |
| #define bTTBPort_TriggerAddr_RESERVE_TADDR 3 |
| #define MSK32TTBPort_TriggerAddr_RESERVE_TADDR 0x00000007 |
| #define BA_TTBPort_TriggerAddr_tAddr 0x0014 |
| #define B16TTBPort_TriggerAddr_tAddr 0x0014 |
| #define LSb32TTBPort_TriggerAddr_tAddr 3 |
| #define LSb16TTBPort_TriggerAddr_tAddr 3 |
| #define bTTBPort_TriggerAddr_tAddr 29 |
| #define MSK32TTBPort_TriggerAddr_tAddr 0xFFFFFFF8 |
| #define RA_TTBPort_TAddrMask 0x0018 |
| #define BA_TTBPort_TAddrMask_RESERVE_TAM 0x0018 |
| #define B16TTBPort_TAddrMask_RESERVE_TAM 0x0018 |
| #define LSb32TTBPort_TAddrMask_RESERVE_TAM 0 |
| #define LSb16TTBPort_TAddrMask_RESERVE_TAM 0 |
| #define bTTBPort_TAddrMask_RESERVE_TAM 3 |
| #define MSK32TTBPort_TAddrMask_RESERVE_TAM 0x00000007 |
| #define BA_TTBPort_TAddrMask_tAddrMask 0x0018 |
| #define B16TTBPort_TAddrMask_tAddrMask 0x0018 |
| #define LSb32TTBPort_TAddrMask_tAddrMask 3 |
| #define LSb16TTBPort_TAddrMask_tAddrMask 3 |
| #define bTTBPort_TAddrMask_tAddrMask 29 |
| #define MSK32TTBPort_TAddrMask_tAddrMask 0xFFFFFFF8 |
| #define RA_TTBPort_TriggerPoint 0x001C |
| #define BA_TTBPort_TriggerPoint_tPos 0x001C |
| #define B16TTBPort_TriggerPoint_tPos 0x001C |
| #define LSb32TTBPort_TriggerPoint_tPos 0 |
| #define LSb16TTBPort_TriggerPoint_tPos 0 |
| #define bTTBPort_TriggerPoint_tPos 32 |
| #define MSK32TTBPort_TriggerPoint_tPos 0xFFFFFFFF |
| #define RA_MctrlDual_CommConfig 0x0000 |
| #define BA_MctrlDual_CommConfig_dual_channel 0x0000 |
| #define B16MctrlDual_CommConfig_dual_channel 0x0000 |
| #define LSb32MctrlDual_CommConfig_dual_channel 0 |
| #define LSb16MctrlDual_CommConfig_dual_channel 0 |
| #define bMctrlDual_CommConfig_dual_channel 1 |
| #define MSK32MctrlDual_CommConfig_dual_channel 0x00000001 |
| #define BA_MctrlDual_CommConfig_asymAddrMode 0x0000 |
| #define B16MctrlDual_CommConfig_asymAddrMode 0x0000 |
| #define LSb32MctrlDual_CommConfig_asymAddrMode 1 |
| #define LSb16MctrlDual_CommConfig_asymAddrMode 1 |
| #define bMctrlDual_CommConfig_asymAddrMode 2 |
| #define MSK32MctrlDual_CommConfig_asymAddrMode 0x00000006 |
| #define BA_MctrlDual_CommConfig_asymAddrSel 0x0000 |
| #define B16MctrlDual_CommConfig_asymAddrSel 0x0000 |
| #define LSb32MctrlDual_CommConfig_asymAddrSel 3 |
| #define LSb16MctrlDual_CommConfig_asymAddrSel 3 |
| #define bMctrlDual_CommConfig_asymAddrSel 2 |
| #define MSK32MctrlDual_CommConfig_asymAddrSel 0x00000018 |
| #define BA_MctrlDual_CommConfig_al_sel 0x0000 |
| #define B16MctrlDual_CommConfig_al_sel 0x0000 |
| #define LSb32MctrlDual_CommConfig_al_sel 5 |
| #define LSb16MctrlDual_CommConfig_al_sel 5 |
| #define bMctrlDual_CommConfig_al_sel 3 |
| #define MSK32MctrlDual_CommConfig_al_sel 0x000000E0 |
| #define BA_MctrlDual_CommConfig_cl_sel 0x0001 |
| #define B16MctrlDual_CommConfig_cl_sel 0x0000 |
| #define LSb32MctrlDual_CommConfig_cl_sel 8 |
| #define LSb16MctrlDual_CommConfig_cl_sel 8 |
| #define bMctrlDual_CommConfig_cl_sel 4 |
| #define MSK32MctrlDual_CommConfig_cl_sel 0x00000F00 |
| #define BA_MctrlDual_CommConfig_bank_mode 0x0001 |
| #define B16MctrlDual_CommConfig_bank_mode 0x0000 |
| #define LSb32MctrlDual_CommConfig_bank_mode 12 |
| #define LSb16MctrlDual_CommConfig_bank_mode 12 |
| #define bMctrlDual_CommConfig_bank_mode 1 |
| #define MSK32MctrlDual_CommConfig_bank_mode 0x00001000 |
| #define BA_MctrlDual_CommConfig_mem_type 0x0001 |
| #define B16MctrlDual_CommConfig_mem_type 0x0000 |
| #define LSb32MctrlDual_CommConfig_mem_type 13 |
| #define LSb16MctrlDual_CommConfig_mem_type 13 |
| #define bMctrlDual_CommConfig_mem_type 3 |
| #define MSK32MctrlDual_CommConfig_mem_type 0x0000E000 |
| #define MctrlDual_CommConfig_mem_type_memTypeDDRI 0x0 |
| #define MctrlDual_CommConfig_mem_type_memTypeSDR 0x1 |
| #define MctrlDual_CommConfig_mem_type_memTypeMDDR 0x2 |
| #define MctrlDual_CommConfig_mem_type_memTypeMSDR 0x3 |
| #define MctrlDual_CommConfig_mem_type_memTypeDDRII 0x4 |
| #define MctrlDual_CommConfig_mem_type_memTypeDDRIII 0x6 |
| #define BA_MctrlDual_CommConfig_data_width 0x0002 |
| #define B16MctrlDual_CommConfig_data_width 0x0002 |
| #define LSb32MctrlDual_CommConfig_data_width 16 |
| #define LSb16MctrlDual_CommConfig_data_width 0 |
| #define bMctrlDual_CommConfig_data_width 2 |
| #define MSK32MctrlDual_CommConfig_data_width 0x00030000 |
| #define MctrlDual_CommConfig_data_width_BY16 0x0 |
| #define MctrlDual_CommConfig_data_width_BY32 0x1 |
| #define RA_MctrlDual_Trigger 0x0004 |
| #define BA_MctrlDual_Trigger_sdram0_init_req 0x0004 |
| #define B16MctrlDual_Trigger_sdram0_init_req 0x0004 |
| #define LSb32MctrlDual_Trigger_sdram0_init_req 0 |
| #define LSb16MctrlDual_Trigger_sdram0_init_req 0 |
| #define bMctrlDual_Trigger_sdram0_init_req 1 |
| #define MSK32MctrlDual_Trigger_sdram0_init_req 0x00000001 |
| #define BA_MctrlDual_Trigger_sdram1_init_req 0x0004 |
| #define B16MctrlDual_Trigger_sdram1_init_req 0x0004 |
| #define LSb32MctrlDual_Trigger_sdram1_init_req 1 |
| #define LSb16MctrlDual_Trigger_sdram1_init_req 1 |
| #define bMctrlDual_Trigger_sdram1_init_req 1 |
| #define MSK32MctrlDual_Trigger_sdram1_init_req 0x00000002 |
| #define BA_MctrlDual_Trigger_pwrsav_exitReq_ch0 0x0004 |
| #define B16MctrlDual_Trigger_pwrsav_exitReq_ch0 0x0004 |
| #define LSb32MctrlDual_Trigger_pwrsav_exitReq_ch0 2 |
| #define LSb16MctrlDual_Trigger_pwrsav_exitReq_ch0 2 |
| #define bMctrlDual_Trigger_pwrsav_exitReq_ch0 1 |
| #define MSK32MctrlDual_Trigger_pwrsav_exitReq_ch0 0x00000004 |
| #define BA_MctrlDual_Trigger_pwrsav_exitReq_ch1 0x0004 |
| #define B16MctrlDual_Trigger_pwrsav_exitReq_ch1 0x0004 |
| #define LSb32MctrlDual_Trigger_pwrsav_exitReq_ch1 3 |
| #define LSb16MctrlDual_Trigger_pwrsav_exitReq_ch1 3 |
| #define bMctrlDual_Trigger_pwrsav_exitReq_ch1 1 |
| #define MSK32MctrlDual_Trigger_pwrsav_exitReq_ch1 0x00000008 |
| #define BA_MctrlDual_Trigger_pwrsav_actReq_ch0 0x0004 |
| #define B16MctrlDual_Trigger_pwrsav_actReq_ch0 0x0004 |
| #define LSb32MctrlDual_Trigger_pwrsav_actReq_ch0 4 |
| #define LSb16MctrlDual_Trigger_pwrsav_actReq_ch0 4 |
| #define bMctrlDual_Trigger_pwrsav_actReq_ch0 1 |
| #define MSK32MctrlDual_Trigger_pwrsav_actReq_ch0 0x00000010 |
| #define BA_MctrlDual_Trigger_pwrsav_actReq_ch1 0x0004 |
| #define B16MctrlDual_Trigger_pwrsav_actReq_ch1 0x0004 |
| #define LSb32MctrlDual_Trigger_pwrsav_actReq_ch1 5 |
| #define LSb16MctrlDual_Trigger_pwrsav_actReq_ch1 5 |
| #define bMctrlDual_Trigger_pwrsav_actReq_ch1 1 |
| #define MSK32MctrlDual_Trigger_pwrsav_actReq_ch1 0x00000020 |
| #define BA_MctrlDual_Trigger_auto_pwrsav_ch0 0x0004 |
| #define B16MctrlDual_Trigger_auto_pwrsav_ch0 0x0004 |
| #define LSb32MctrlDual_Trigger_auto_pwrsav_ch0 6 |
| #define LSb16MctrlDual_Trigger_auto_pwrsav_ch0 6 |
| #define bMctrlDual_Trigger_auto_pwrsav_ch0 1 |
| #define MSK32MctrlDual_Trigger_auto_pwrsav_ch0 0x00000040 |
| #define BA_MctrlDual_Trigger_auto_pwrsav_ch1 0x0004 |
| #define B16MctrlDual_Trigger_auto_pwrsav_ch1 0x0004 |
| #define LSb32MctrlDual_Trigger_auto_pwrsav_ch1 7 |
| #define LSb16MctrlDual_Trigger_auto_pwrsav_ch1 7 |
| #define bMctrlDual_Trigger_auto_pwrsav_ch1 1 |
| #define MSK32MctrlDual_Trigger_auto_pwrsav_ch1 0x00000080 |
| #define BA_MctrlDual_Trigger_wBufferFlushCh0 0x0005 |
| #define B16MctrlDual_Trigger_wBufferFlushCh0 0x0004 |
| #define LSb32MctrlDual_Trigger_wBufferFlushCh0 8 |
| #define LSb16MctrlDual_Trigger_wBufferFlushCh0 8 |
| #define bMctrlDual_Trigger_wBufferFlushCh0 1 |
| #define MSK32MctrlDual_Trigger_wBufferFlushCh0 0x00000100 |
| #define BA_MctrlDual_Trigger_wBufferFlushCh1 0x0005 |
| #define B16MctrlDual_Trigger_wBufferFlushCh1 0x0004 |
| #define LSb32MctrlDual_Trigger_wBufferFlushCh1 9 |
| #define LSb16MctrlDual_Trigger_wBufferFlushCh1 9 |
| #define bMctrlDual_Trigger_wBufferFlushCh1 1 |
| #define MSK32MctrlDual_Trigger_wBufferFlushCh1 0x00000200 |
| #define BA_MctrlDual_Trigger_cal_req 0x0005 |
| #define B16MctrlDual_Trigger_cal_req 0x0004 |
| #define LSb32MctrlDual_Trigger_cal_req 10 |
| #define LSb16MctrlDual_Trigger_cal_req 10 |
| #define bMctrlDual_Trigger_cal_req 1 |
| #define MSK32MctrlDual_Trigger_cal_req 0x00000400 |
| #define BA_MctrlDual_Trigger_ttbFlush 0x0005 |
| #define B16MctrlDual_Trigger_ttbFlush 0x0004 |
| #define LSb32MctrlDual_Trigger_ttbFlush 11 |
| #define LSb16MctrlDual_Trigger_ttbFlush 11 |
| #define bMctrlDual_Trigger_ttbFlush 1 |
| #define MSK32MctrlDual_Trigger_ttbFlush 0x00000800 |
| #define BA_MctrlDual_Trigger_loopBackTestCh0 0x0005 |
| #define B16MctrlDual_Trigger_loopBackTestCh0 0x0004 |
| #define LSb32MctrlDual_Trigger_loopBackTestCh0 12 |
| #define LSb16MctrlDual_Trigger_loopBackTestCh0 12 |
| #define bMctrlDual_Trigger_loopBackTestCh0 1 |
| #define MSK32MctrlDual_Trigger_loopBackTestCh0 0x00001000 |
| #define BA_MctrlDual_Trigger_loopBackTestCh1 0x0005 |
| #define B16MctrlDual_Trigger_loopBackTestCh1 0x0004 |
| #define LSb32MctrlDual_Trigger_loopBackTestCh1 13 |
| #define LSb16MctrlDual_Trigger_loopBackTestCh1 13 |
| #define bMctrlDual_Trigger_loopBackTestCh1 1 |
| #define MSK32MctrlDual_Trigger_loopBackTestCh1 0x00002000 |
| #define RA_MctrlDual_Status 0x0008 |
| #define BA_MctrlDual_Status_sdram0_init_done 0x0008 |
| #define B16MctrlDual_Status_sdram0_init_done 0x0008 |
| #define LSb32MctrlDual_Status_sdram0_init_done 0 |
| #define LSb16MctrlDual_Status_sdram0_init_done 0 |
| #define bMctrlDual_Status_sdram0_init_done 1 |
| #define MSK32MctrlDual_Status_sdram0_init_done 0x00000001 |
| #define BA_MctrlDual_Status_sdram1_init_done 0x0008 |
| #define B16MctrlDual_Status_sdram1_init_done 0x0008 |
| #define LSb32MctrlDual_Status_sdram1_init_done 1 |
| #define LSb16MctrlDual_Status_sdram1_init_done 1 |
| #define bMctrlDual_Status_sdram1_init_done 1 |
| #define MSK32MctrlDual_Status_sdram1_init_done 0x00000002 |
| #define BA_MctrlDual_Status_pwrsav_exitDone_ch0 0x0008 |
| #define B16MctrlDual_Status_pwrsav_exitDone_ch0 0x0008 |
| #define LSb32MctrlDual_Status_pwrsav_exitDone_ch0 2 |
| #define LSb16MctrlDual_Status_pwrsav_exitDone_ch0 2 |
| #define bMctrlDual_Status_pwrsav_exitDone_ch0 1 |
| #define MSK32MctrlDual_Status_pwrsav_exitDone_ch0 0x00000004 |
| #define BA_MctrlDual_Status_pwrsav_exitDone_ch1 0x0008 |
| #define B16MctrlDual_Status_pwrsav_exitDone_ch1 0x0008 |
| #define LSb32MctrlDual_Status_pwrsav_exitDone_ch1 3 |
| #define LSb16MctrlDual_Status_pwrsav_exitDone_ch1 3 |
| #define bMctrlDual_Status_pwrsav_exitDone_ch1 1 |
| #define MSK32MctrlDual_Status_pwrsav_exitDone_ch1 0x00000008 |
| #define BA_MctrlDual_Status_pwrsav_actDone_ch0 0x0008 |
| #define B16MctrlDual_Status_pwrsav_actDone_ch0 0x0008 |
| #define LSb32MctrlDual_Status_pwrsav_actDone_ch0 4 |
| #define LSb16MctrlDual_Status_pwrsav_actDone_ch0 4 |
| #define bMctrlDual_Status_pwrsav_actDone_ch0 1 |
| #define MSK32MctrlDual_Status_pwrsav_actDone_ch0 0x00000010 |
| #define BA_MctrlDual_Status_pwrsav_actDone_ch1 0x0008 |
| #define B16MctrlDual_Status_pwrsav_actDone_ch1 0x0008 |
| #define LSb32MctrlDual_Status_pwrsav_actDone_ch1 5 |
| #define LSb16MctrlDual_Status_pwrsav_actDone_ch1 5 |
| #define bMctrlDual_Status_pwrsav_actDone_ch1 1 |
| #define MSK32MctrlDual_Status_pwrsav_actDone_ch1 0x00000020 |
| #define BA_MctrlDual_Status_aps_on_ch0 0x0008 |
| #define B16MctrlDual_Status_aps_on_ch0 0x0008 |
| #define LSb32MctrlDual_Status_aps_on_ch0 6 |
| #define LSb16MctrlDual_Status_aps_on_ch0 6 |
| #define bMctrlDual_Status_aps_on_ch0 1 |
| #define MSK32MctrlDual_Status_aps_on_ch0 0x00000040 |
| #define BA_MctrlDual_Status_aps_on_ch1 0x0008 |
| #define B16MctrlDual_Status_aps_on_ch1 0x0008 |
| #define LSb32MctrlDual_Status_aps_on_ch1 7 |
| #define LSb16MctrlDual_Status_aps_on_ch1 7 |
| #define bMctrlDual_Status_aps_on_ch1 1 |
| #define MSK32MctrlDual_Status_aps_on_ch1 0x00000080 |
| #define BA_MctrlDual_Status_wBufferEmptyCh0 0x0009 |
| #define B16MctrlDual_Status_wBufferEmptyCh0 0x0008 |
| #define LSb32MctrlDual_Status_wBufferEmptyCh0 8 |
| #define LSb16MctrlDual_Status_wBufferEmptyCh0 8 |
| #define bMctrlDual_Status_wBufferEmptyCh0 1 |
| #define MSK32MctrlDual_Status_wBufferEmptyCh0 0x00000100 |
| #define BA_MctrlDual_Status_wBufferEmptyCh1 0x0009 |
| #define B16MctrlDual_Status_wBufferEmptyCh1 0x0008 |
| #define LSb32MctrlDual_Status_wBufferEmptyCh1 9 |
| #define LSb16MctrlDual_Status_wBufferEmptyCh1 9 |
| #define bMctrlDual_Status_wBufferEmptyCh1 1 |
| #define MSK32MctrlDual_Status_wBufferEmptyCh1 0x00000200 |
| #define BA_MctrlDual_Status_inq0_empty 0x0009 |
| #define B16MctrlDual_Status_inq0_empty 0x0008 |
| #define LSb32MctrlDual_Status_inq0_empty 10 |
| #define LSb16MctrlDual_Status_inq0_empty 10 |
| #define bMctrlDual_Status_inq0_empty 1 |
| #define MSK32MctrlDual_Status_inq0_empty 0x00000400 |
| #define BA_MctrlDual_Status_inq0_full 0x0009 |
| #define B16MctrlDual_Status_inq0_full 0x0008 |
| #define LSb32MctrlDual_Status_inq0_full 11 |
| #define LSb16MctrlDual_Status_inq0_full 11 |
| #define bMctrlDual_Status_inq0_full 1 |
| #define MSK32MctrlDual_Status_inq0_full 0x00000800 |
| #define BA_MctrlDual_Status_inq1_empty 0x0009 |
| #define B16MctrlDual_Status_inq1_empty 0x0008 |
| #define LSb32MctrlDual_Status_inq1_empty 12 |
| #define LSb16MctrlDual_Status_inq1_empty 12 |
| #define bMctrlDual_Status_inq1_empty 1 |
| #define MSK32MctrlDual_Status_inq1_empty 0x00001000 |
| #define BA_MctrlDual_Status_inq1_full 0x0009 |
| #define B16MctrlDual_Status_inq1_full 0x0008 |
| #define LSb32MctrlDual_Status_inq1_full 13 |
| #define LSb16MctrlDual_Status_inq1_full 13 |
| #define bMctrlDual_Status_inq1_full 1 |
| #define MSK32MctrlDual_Status_inq1_full 0x00002000 |
| #define BA_MctrlDual_Status_ttbEmpty 0x0009 |
| #define B16MctrlDual_Status_ttbEmpty 0x0008 |
| #define LSb32MctrlDual_Status_ttbEmpty 14 |
| #define LSb16MctrlDual_Status_ttbEmpty 14 |
| #define bMctrlDual_Status_ttbEmpty 1 |
| #define MSK32MctrlDual_Status_ttbEmpty 0x00004000 |
| #define BA_MctrlDual_Status_loopBackPassCh0 0x0009 |
| #define B16MctrlDual_Status_loopBackPassCh0 0x0008 |
| #define LSb32MctrlDual_Status_loopBackPassCh0 15 |
| #define LSb16MctrlDual_Status_loopBackPassCh0 15 |
| #define bMctrlDual_Status_loopBackPassCh0 1 |
| #define MSK32MctrlDual_Status_loopBackPassCh0 0x00008000 |
| #define BA_MctrlDual_Status_loopBackDoneCh0 0x000A |
| #define B16MctrlDual_Status_loopBackDoneCh0 0x000A |
| #define LSb32MctrlDual_Status_loopBackDoneCh0 16 |
| #define LSb16MctrlDual_Status_loopBackDoneCh0 0 |
| #define bMctrlDual_Status_loopBackDoneCh0 1 |
| #define MSK32MctrlDual_Status_loopBackDoneCh0 0x00010000 |
| #define BA_MctrlDual_Status_loopBackPassCh1 0x000A |
| #define B16MctrlDual_Status_loopBackPassCh1 0x000A |
| #define LSb32MctrlDual_Status_loopBackPassCh1 17 |
| #define LSb16MctrlDual_Status_loopBackPassCh1 1 |
| #define bMctrlDual_Status_loopBackPassCh1 1 |
| #define MSK32MctrlDual_Status_loopBackPassCh1 0x00020000 |
| #define BA_MctrlDual_Status_loopBackDoneCh1 0x000A |
| #define B16MctrlDual_Status_loopBackDoneCh1 0x000A |
| #define LSb32MctrlDual_Status_loopBackDoneCh1 18 |
| #define LSb16MctrlDual_Status_loopBackDoneCh1 2 |
| #define bMctrlDual_Status_loopBackDoneCh1 1 |
| #define MSK32MctrlDual_Status_loopBackDoneCh1 0x00040000 |
| #define RA_MctrlDual_SettingChannel0 0x000C |
| #define BA_MctrlDual_SettingChannel0_noColumnAddrCh0 0x000C |
| #define B16MctrlDual_SettingChannel0_noColumnAddrCh0 0x000C |
| #define LSb32MctrlDual_SettingChannel0_noColumnAddrCh0 0 |
| #define LSb16MctrlDual_SettingChannel0_noColumnAddrCh0 0 |
| #define bMctrlDual_SettingChannel0_noColumnAddrCh0 4 |
| #define MSK32MctrlDual_SettingChannel0_noColumnAddrCh0 0x0000000F |
| #define BA_MctrlDual_SettingChannel0_noRowAddrCh0 0x000C |
| #define B16MctrlDual_SettingChannel0_noRowAddrCh0 0x000C |
| #define LSb32MctrlDual_SettingChannel0_noRowAddrCh0 4 |
| #define LSb16MctrlDual_SettingChannel0_noRowAddrCh0 4 |
| #define bMctrlDual_SettingChannel0_noRowAddrCh0 4 |
| #define MSK32MctrlDual_SettingChannel0_noRowAddrCh0 0x000000F0 |
| #define BA_MctrlDual_SettingChannel0_bankSelCh0 0x000D |
| #define B16MctrlDual_SettingChannel0_bankSelCh0 0x000C |
| #define LSb32MctrlDual_SettingChannel0_bankSelCh0 8 |
| #define LSb16MctrlDual_SettingChannel0_bankSelCh0 8 |
| #define bMctrlDual_SettingChannel0_bankSelCh0 1 |
| #define MSK32MctrlDual_SettingChannel0_bankSelCh0 0x00000100 |
| #define MctrlDual_SettingChannel0_bankSelCh0_SDRAM4BankCH0 0x0 |
| #define MctrlDual_SettingChannel0_bankSelCh0_SDRAM8BankCH0 0x1 |
| #define BA_MctrlDual_SettingChannel0_noChipSelectCh0 0x000D |
| #define B16MctrlDual_SettingChannel0_noChipSelectCh0 0x000C |
| #define LSb32MctrlDual_SettingChannel0_noChipSelectCh0 9 |
| #define LSb16MctrlDual_SettingChannel0_noChipSelectCh0 9 |
| #define bMctrlDual_SettingChannel0_noChipSelectCh0 2 |
| #define MSK32MctrlDual_SettingChannel0_noChipSelectCh0 0x00000600 |
| #define RA_MctrlDual_SettingChannel1 0x0010 |
| #define BA_MctrlDual_SettingChannel1_noColumnAddrCh1 0x0010 |
| #define B16MctrlDual_SettingChannel1_noColumnAddrCh1 0x0010 |
| #define LSb32MctrlDual_SettingChannel1_noColumnAddrCh1 0 |
| #define LSb16MctrlDual_SettingChannel1_noColumnAddrCh1 0 |
| #define bMctrlDual_SettingChannel1_noColumnAddrCh1 4 |
| #define MSK32MctrlDual_SettingChannel1_noColumnAddrCh1 0x0000000F |
| #define BA_MctrlDual_SettingChannel1_noRowAddrCh1 0x0010 |
| #define B16MctrlDual_SettingChannel1_noRowAddrCh1 0x0010 |
| #define LSb32MctrlDual_SettingChannel1_noRowAddrCh1 4 |
| #define LSb16MctrlDual_SettingChannel1_noRowAddrCh1 4 |
| #define bMctrlDual_SettingChannel1_noRowAddrCh1 4 |
| #define MSK32MctrlDual_SettingChannel1_noRowAddrCh1 0x000000F0 |
| #define BA_MctrlDual_SettingChannel1_bankSelCh1 0x0011 |
| #define B16MctrlDual_SettingChannel1_bankSelCh1 0x0010 |
| #define LSb32MctrlDual_SettingChannel1_bankSelCh1 8 |
| #define LSb16MctrlDual_SettingChannel1_bankSelCh1 8 |
| #define bMctrlDual_SettingChannel1_bankSelCh1 1 |
| #define MSK32MctrlDual_SettingChannel1_bankSelCh1 0x00000100 |
| #define MctrlDual_SettingChannel1_bankSelCh1_SDRAM4BankCH1 0x0 |
| #define MctrlDual_SettingChannel1_bankSelCh1_SDRAM8BankCH1 0x1 |
| #define BA_MctrlDual_SettingChannel1_noChipSelectCh1 0x0011 |
| #define B16MctrlDual_SettingChannel1_noChipSelectCh1 0x0010 |
| #define LSb32MctrlDual_SettingChannel1_noChipSelectCh1 9 |
| #define LSb16MctrlDual_SettingChannel1_noChipSelectCh1 9 |
| #define bMctrlDual_SettingChannel1_noChipSelectCh1 2 |
| #define MSK32MctrlDual_SettingChannel1_noChipSelectCh1 0x00000600 |
| #define RA_MctrlDual_Timing1 0x0014 |
| #define BA_MctrlDual_Timing1_init_tras 0x0014 |
| #define B16MctrlDual_Timing1_init_tras 0x0014 |
| #define LSb32MctrlDual_Timing1_init_tras 0 |
| #define LSb16MctrlDual_Timing1_init_tras 0 |
| #define bMctrlDual_Timing1_init_tras 8 |
| #define MSK32MctrlDual_Timing1_init_tras 0x000000FF |
| #define BA_MctrlDual_Timing1_init_trfc 0x0015 |
| #define B16MctrlDual_Timing1_init_trfc 0x0014 |
| #define LSb32MctrlDual_Timing1_init_trfc 8 |
| #define LSb16MctrlDual_Timing1_init_trfc 8 |
| #define bMctrlDual_Timing1_init_trfc 8 |
| #define MSK32MctrlDual_Timing1_init_trfc 0x0000FF00 |
| #define BA_MctrlDual_Timing1_init_trc 0x0016 |
| #define B16MctrlDual_Timing1_init_trc 0x0016 |
| #define LSb32MctrlDual_Timing1_init_trc 16 |
| #define LSb16MctrlDual_Timing1_init_trc 0 |
| #define bMctrlDual_Timing1_init_trc 8 |
| #define MSK32MctrlDual_Timing1_init_trc 0x00FF0000 |
| #define BA_MctrlDual_Timing1_init_refc 0x0017 |
| #define B16MctrlDual_Timing1_init_refc 0x0016 |
| #define LSb32MctrlDual_Timing1_init_refc 24 |
| #define LSb16MctrlDual_Timing1_init_refc 8 |
| #define bMctrlDual_Timing1_init_refc 8 |
| #define MSK32MctrlDual_Timing1_init_refc 0xFF000000 |
| #define RA_MctrlDual_Timing2 0x0018 |
| #define BA_MctrlDual_Timing2_init_trp 0x0018 |
| #define B16MctrlDual_Timing2_init_trp 0x0018 |
| #define LSb32MctrlDual_Timing2_init_trp 0 |
| #define LSb16MctrlDual_Timing2_init_trp 0 |
| #define bMctrlDual_Timing2_init_trp 4 |
| #define MSK32MctrlDual_Timing2_init_trp 0x0000000F |
| #define BA_MctrlDual_Timing2_init_trrd 0x0018 |
| #define B16MctrlDual_Timing2_init_trrd 0x0018 |
| #define LSb32MctrlDual_Timing2_init_trrd 4 |
| #define LSb16MctrlDual_Timing2_init_trrd 4 |
| #define bMctrlDual_Timing2_init_trrd 4 |
| #define MSK32MctrlDual_Timing2_init_trrd 0x000000F0 |
| #define BA_MctrlDual_Timing2_init_trcd 0x0019 |
| #define B16MctrlDual_Timing2_init_trcd 0x0018 |
| #define LSb32MctrlDual_Timing2_init_trcd 8 |
| #define LSb16MctrlDual_Timing2_init_trcd 8 |
| #define bMctrlDual_Timing2_init_trcd 4 |
| #define MSK32MctrlDual_Timing2_init_trcd 0x00000F00 |
| #define BA_MctrlDual_Timing2_init_twr 0x0019 |
| #define B16MctrlDual_Timing2_init_twr 0x0018 |
| #define LSb32MctrlDual_Timing2_init_twr 12 |
| #define LSb16MctrlDual_Timing2_init_twr 12 |
| #define bMctrlDual_Timing2_init_twr 4 |
| #define MSK32MctrlDual_Timing2_init_twr 0x0000F000 |
| #define BA_MctrlDual_Timing2_init_trtp 0x001A |
| #define B16MctrlDual_Timing2_init_trtp 0x001A |
| #define LSb32MctrlDual_Timing2_init_trtp 16 |
| #define LSb16MctrlDual_Timing2_init_trtp 0 |
| #define bMctrlDual_Timing2_init_trtp 4 |
| #define MSK32MctrlDual_Timing2_init_trtp 0x000F0000 |
| #define BA_MctrlDual_Timing2_init_twtr 0x001A |
| #define B16MctrlDual_Timing2_init_twtr 0x001A |
| #define LSb32MctrlDual_Timing2_init_twtr 20 |
| #define LSb16MctrlDual_Timing2_init_twtr 4 |
| #define bMctrlDual_Timing2_init_twtr 4 |
| #define MSK32MctrlDual_Timing2_init_twtr 0x00F00000 |
| #define BA_MctrlDual_Timing2_init_tmrd 0x001B |
| #define B16MctrlDual_Timing2_init_tmrd 0x001A |
| #define LSb32MctrlDual_Timing2_init_tmrd 24 |
| #define LSb16MctrlDual_Timing2_init_tmrd 8 |
| #define bMctrlDual_Timing2_init_tmrd 4 |
| #define MSK32MctrlDual_Timing2_init_tmrd 0x0F000000 |
| #define RA_MctrlDual_Timing3 0x001C |
| #define BA_MctrlDual_Timing3_init_txsnr 0x001C |
| #define B16MctrlDual_Timing3_init_txsnr 0x001C |
| #define LSb32MctrlDual_Timing3_init_txsnr 0 |
| #define LSb16MctrlDual_Timing3_init_txsnr 0 |
| #define bMctrlDual_Timing3_init_txsnr 8 |
| #define MSK32MctrlDual_Timing3_init_txsnr 0x000000FF |
| #define BA_MctrlDual_Timing3_init_tick 0x001D |
| #define B16MctrlDual_Timing3_init_tick 0x001C |
| #define LSb32MctrlDual_Timing3_init_tick 8 |
| #define LSb16MctrlDual_Timing3_init_tick 8 |
| #define bMctrlDual_Timing3_init_tick 8 |
| #define MSK32MctrlDual_Timing3_init_tick 0x0000FF00 |
| #define BA_MctrlDual_Timing3_init_tfaw 0x001E |
| #define B16MctrlDual_Timing3_init_tfaw 0x001E |
| #define LSb32MctrlDual_Timing3_init_tfaw 16 |
| #define LSb16MctrlDual_Timing3_init_tfaw 0 |
| #define bMctrlDual_Timing3_init_tfaw 8 |
| #define MSK32MctrlDual_Timing3_init_tfaw 0x00FF0000 |
| #define BA_MctrlDual_Timing3_init_trfcmax 0x001F |
| #define B16MctrlDual_Timing3_init_trfcmax 0x001E |
| #define LSb32MctrlDual_Timing3_init_trfcmax 24 |
| #define LSb16MctrlDual_Timing3_init_trfcmax 8 |
| #define bMctrlDual_Timing3_init_trfcmax 8 |
| #define MSK32MctrlDual_Timing3_init_trfcmax 0xFF000000 |
| #define RA_MctrlDual_Timing4 0x0020 |
| #define BA_MctrlDual_Timing4_init_trst 0x0020 |
| #define B16MctrlDual_Timing4_init_trst 0x0020 |
| #define LSb32MctrlDual_Timing4_init_trst 0 |
| #define LSb16MctrlDual_Timing4_init_trst 0 |
| #define bMctrlDual_Timing4_init_trst 12 |
| #define MSK32MctrlDual_Timing4_init_trst 0x00000FFF |
| #define BA_MctrlDual_Timing4_init_tmod 0x0021 |
| #define B16MctrlDual_Timing4_init_tmod 0x0020 |
| #define LSb32MctrlDual_Timing4_init_tmod 12 |
| #define LSb16MctrlDual_Timing4_init_tmod 12 |
| #define bMctrlDual_Timing4_init_tmod 4 |
| #define MSK32MctrlDual_Timing4_init_tmod 0x0000F000 |
| #define BA_MctrlDual_Timing4_init_tzqi 0x0022 |
| #define B16MctrlDual_Timing4_init_tzqi 0x0022 |
| #define LSb32MctrlDual_Timing4_init_tzqi 16 |
| #define LSb16MctrlDual_Timing4_init_tzqi 0 |
| #define bMctrlDual_Timing4_init_tzqi 8 |
| #define MSK32MctrlDual_Timing4_init_tzqi 0x00FF0000 |
| #define RA_MctrlDual_Control1 0x0024 |
| #define BA_MctrlDual_Control1_init_taps 0x0024 |
| #define B16MctrlDual_Control1_init_taps 0x0024 |
| #define LSb32MctrlDual_Control1_init_taps 0 |
| #define LSb16MctrlDual_Control1_init_taps 0 |
| #define bMctrlDual_Control1_init_taps 8 |
| #define MSK32MctrlDual_Control1_init_taps 0x000000FF |
| #define BA_MctrlDual_Control1_wCollectEnb 0x0025 |
| #define B16MctrlDual_Control1_wCollectEnb 0x0024 |
| #define LSb32MctrlDual_Control1_wCollectEnb 8 |
| #define LSb16MctrlDual_Control1_wCollectEnb 8 |
| #define bMctrlDual_Control1_wCollectEnb 1 |
| #define MSK32MctrlDual_Control1_wCollectEnb 0x00000100 |
| #define BA_MctrlDual_Control1_bankStatusArb 0x0025 |
| #define B16MctrlDual_Control1_bankStatusArb 0x0024 |
| #define LSb32MctrlDual_Control1_bankStatusArb 9 |
| #define LSb16MctrlDual_Control1_bankStatusArb 9 |
| #define bMctrlDual_Control1_bankStatusArb 1 |
| #define MSK32MctrlDual_Control1_bankStatusArb 0x00000200 |
| #define BA_MctrlDual_Control1_xbarQosEnb 0x0025 |
| #define B16MctrlDual_Control1_xbarQosEnb 0x0024 |
| #define LSb32MctrlDual_Control1_xbarQosEnb 10 |
| #define LSb16MctrlDual_Control1_xbarQosEnb 10 |
| #define bMctrlDual_Control1_xbarQosEnb 1 |
| #define MSK32MctrlDual_Control1_xbarQosEnb 0x00000400 |
| #define BA_MctrlDual_Control1_bQReorder 0x0025 |
| #define B16MctrlDual_Control1_bQReorder 0x0024 |
| #define LSb32MctrlDual_Control1_bQReorder 11 |
| #define LSb16MctrlDual_Control1_bQReorder 11 |
| #define bMctrlDual_Control1_bQReorder 4 |
| #define MSK32MctrlDual_Control1_bQReorder 0x00007800 |
| #define BA_MctrlDual_Control1_cpu_read_force 0x0025 |
| #define B16MctrlDual_Control1_cpu_read_force 0x0024 |
| #define LSb32MctrlDual_Control1_cpu_read_force 15 |
| #define LSb16MctrlDual_Control1_cpu_read_force 15 |
| #define bMctrlDual_Control1_cpu_read_force 1 |
| #define MSK32MctrlDual_Control1_cpu_read_force 0x00008000 |
| #define BA_MctrlDual_Control1_pcmdq_size 0x0026 |
| #define B16MctrlDual_Control1_pcmdq_size 0x0026 |
| #define LSb32MctrlDual_Control1_pcmdq_size 16 |
| #define LSb16MctrlDual_Control1_pcmdq_size 0 |
| #define bMctrlDual_Control1_pcmdq_size 2 |
| #define MSK32MctrlDual_Control1_pcmdq_size 0x00030000 |
| #define BA_MctrlDual_Control1_apre_on 0x0026 |
| #define B16MctrlDual_Control1_apre_on 0x0026 |
| #define LSb32MctrlDual_Control1_apre_on 18 |
| #define LSb16MctrlDual_Control1_apre_on 2 |
| #define bMctrlDual_Control1_apre_on 1 |
| #define MSK32MctrlDual_Control1_apre_on 0x00040000 |
| #define BA_MctrlDual_Control1_sdarb_on 0x0026 |
| #define B16MctrlDual_Control1_sdarb_on 0x0026 |
| #define LSb32MctrlDual_Control1_sdarb_on 19 |
| #define LSb16MctrlDual_Control1_sdarb_on 3 |
| #define bMctrlDual_Control1_sdarb_on 1 |
| #define MSK32MctrlDual_Control1_sdarb_on 0x00080000 |
| #define BA_MctrlDual_Control1_perfCountEnb 0x0026 |
| #define B16MctrlDual_Control1_perfCountEnb 0x0026 |
| #define LSb32MctrlDual_Control1_perfCountEnb 20 |
| #define LSb16MctrlDual_Control1_perfCountEnb 4 |
| #define bMctrlDual_Control1_perfCountEnb 1 |
| #define MSK32MctrlDual_Control1_perfCountEnb 0x00100000 |
| #define BA_MctrlDual_Control1_cpuThrottle 0x0026 |
| #define B16MctrlDual_Control1_cpuThrottle 0x0026 |
| #define LSb32MctrlDual_Control1_cpuThrottle 21 |
| #define LSb16MctrlDual_Control1_cpuThrottle 5 |
| #define bMctrlDual_Control1_cpuThrottle 1 |
| #define MSK32MctrlDual_Control1_cpuThrottle 0x00200000 |
| #define BA_MctrlDual_Control1_wait4QoS 0x0026 |
| #define B16MctrlDual_Control1_wait4QoS 0x0026 |
| #define LSb32MctrlDual_Control1_wait4QoS 22 |
| #define LSb16MctrlDual_Control1_wait4QoS 6 |
| #define bMctrlDual_Control1_wait4QoS 1 |
| #define MSK32MctrlDual_Control1_wait4QoS 0x00400000 |
| #define RA_MctrlDual_Control2 0x0028 |
| #define BA_MctrlDual_Control2_xsrlmr_on 0x0028 |
| #define B16MctrlDual_Control2_xsrlmr_on 0x0028 |
| #define LSb32MctrlDual_Control2_xsrlmr_on 0 |
| #define LSb16MctrlDual_Control2_xsrlmr_on 0 |
| #define bMctrlDual_Control2_xsrlmr_on 1 |
| #define MSK32MctrlDual_Control2_xsrlmr_on 0x00000001 |
| #define BA_MctrlDual_Control2_pwrsav_mode 0x0028 |
| #define B16MctrlDual_Control2_pwrsav_mode 0x0028 |
| #define LSb32MctrlDual_Control2_pwrsav_mode 1 |
| #define LSb16MctrlDual_Control2_pwrsav_mode 1 |
| #define bMctrlDual_Control2_pwrsav_mode 3 |
| #define MSK32MctrlDual_Control2_pwrsav_mode 0x0000000E |
| #define BA_MctrlDual_Control2_tcsr_sel 0x0028 |
| #define B16MctrlDual_Control2_tcsr_sel 0x0028 |
| #define LSb32MctrlDual_Control2_tcsr_sel 4 |
| #define LSb16MctrlDual_Control2_tcsr_sel 4 |
| #define bMctrlDual_Control2_tcsr_sel 2 |
| #define MSK32MctrlDual_Control2_tcsr_sel 0x00000030 |
| #define BA_MctrlDual_Control2_srcv_sel 0x0028 |
| #define B16MctrlDual_Control2_srcv_sel 0x0028 |
| #define LSb32MctrlDual_Control2_srcv_sel 6 |
| #define LSb16MctrlDual_Control2_srcv_sel 6 |
| #define bMctrlDual_Control2_srcv_sel 3 |
| #define MSK32MctrlDual_Control2_srcv_sel 0x000001C0 |
| #define BA_MctrlDual_Control2_sref_rate 0x0029 |
| #define B16MctrlDual_Control2_sref_rate 0x0028 |
| #define LSb32MctrlDual_Control2_sref_rate 9 |
| #define LSb16MctrlDual_Control2_sref_rate 9 |
| #define bMctrlDual_Control2_sref_rate 1 |
| #define MSK32MctrlDual_Control2_sref_rate 0x00000200 |
| #define BA_MctrlDual_Control2_qout_oen 0x0029 |
| #define B16MctrlDual_Control2_qout_oen 0x0028 |
| #define LSb32MctrlDual_Control2_qout_oen 10 |
| #define LSb16MctrlDual_Control2_qout_oen 10 |
| #define bMctrlDual_Control2_qout_oen 1 |
| #define MSK32MctrlDual_Control2_qout_oen 0x00000400 |
| #define BA_MctrlDual_Control2_rtt_sel 0x0029 |
| #define B16MctrlDual_Control2_rtt_sel 0x0028 |
| #define LSb32MctrlDual_Control2_rtt_sel 11 |
| #define LSb16MctrlDual_Control2_rtt_sel 11 |
| #define bMctrlDual_Control2_rtt_sel 3 |
| #define MSK32MctrlDual_Control2_rtt_sel 0x00003800 |
| #define BA_MctrlDual_Control2_odrs_sel 0x0029 |
| #define B16MctrlDual_Control2_odrs_sel 0x0028 |
| #define LSb32MctrlDual_Control2_odrs_sel 14 |
| #define LSb16MctrlDual_Control2_odrs_sel 14 |
| #define bMctrlDual_Control2_odrs_sel 2 |
| #define MSK32MctrlDual_Control2_odrs_sel 0x0000C000 |
| #define BA_MctrlDual_Control2_twr_sel 0x002A |
| #define B16MctrlDual_Control2_twr_sel 0x002A |
| #define LSb32MctrlDual_Control2_twr_sel 16 |
| #define LSb16MctrlDual_Control2_twr_sel 0 |
| #define bMctrlDual_Control2_twr_sel 3 |
| #define MSK32MctrlDual_Control2_twr_sel 0x00070000 |
| #define BA_MctrlDual_Control2_pdext_sel 0x002A |
| #define B16MctrlDual_Control2_pdext_sel 0x002A |
| #define LSb32MctrlDual_Control2_pdext_sel 19 |
| #define LSb16MctrlDual_Control2_pdext_sel 3 |
| #define bMctrlDual_Control2_pdext_sel 1 |
| #define MSK32MctrlDual_Control2_pdext_sel 0x00080000 |
| #define BA_MctrlDual_Control2_rtt_wr 0x002A |
| #define B16MctrlDual_Control2_rtt_wr 0x002A |
| #define LSb32MctrlDual_Control2_rtt_wr 20 |
| #define LSb16MctrlDual_Control2_rtt_wr 4 |
| #define bMctrlDual_Control2_rtt_wr 2 |
| #define MSK32MctrlDual_Control2_rtt_wr 0x00300000 |
| #define BA_MctrlDual_Control2_asr_sel 0x002A |
| #define B16MctrlDual_Control2_asr_sel 0x002A |
| #define LSb32MctrlDual_Control2_asr_sel 22 |
| #define LSb16MctrlDual_Control2_asr_sel 6 |
| #define bMctrlDual_Control2_asr_sel 1 |
| #define MSK32MctrlDual_Control2_asr_sel 0x00400000 |
| #define BA_MctrlDual_Control2_cwl_sel 0x002A |
| #define B16MctrlDual_Control2_cwl_sel 0x002A |
| #define LSb32MctrlDual_Control2_cwl_sel 23 |
| #define LSb16MctrlDual_Control2_cwl_sel 7 |
| #define bMctrlDual_Control2_cwl_sel 3 |
| #define MSK32MctrlDual_Control2_cwl_sel 0x03800000 |
| #define BA_MctrlDual_Control2_mpr_sel 0x002B |
| #define B16MctrlDual_Control2_mpr_sel 0x002A |
| #define LSb32MctrlDual_Control2_mpr_sel 26 |
| #define LSb16MctrlDual_Control2_mpr_sel 10 |
| #define bMctrlDual_Control2_mpr_sel 1 |
| #define MSK32MctrlDual_Control2_mpr_sel 0x04000000 |
| #define BA_MctrlDual_Control2_mpr_addr_sel 0x002B |
| #define B16MctrlDual_Control2_mpr_addr_sel 0x002A |
| #define LSb32MctrlDual_Control2_mpr_addr_sel 27 |
| #define LSb16MctrlDual_Control2_mpr_addr_sel 11 |
| #define bMctrlDual_Control2_mpr_addr_sel 2 |
| #define MSK32MctrlDual_Control2_mpr_addr_sel 0x18000000 |
| #define BA_MctrlDual_Control2_wlevel_sel 0x002B |
| #define B16MctrlDual_Control2_wlevel_sel 0x002A |
| #define LSb32MctrlDual_Control2_wlevel_sel 29 |
| #define LSb16MctrlDual_Control2_wlevel_sel 13 |
| #define bMctrlDual_Control2_wlevel_sel 1 |
| #define MSK32MctrlDual_Control2_wlevel_sel 0x20000000 |
| #define RA_MctrlDual_PriorityLevel 0x002C |
| #define BA_MctrlDual_PriorityLevel_CPU0WritePriorityLevel 0x002C |
| #define B16MctrlDual_PriorityLevel_CPU0WritePriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_CPU0WritePriorityLevel 0 |
| #define LSb16MctrlDual_PriorityLevel_CPU0WritePriorityLevel 0 |
| #define bMctrlDual_PriorityLevel_CPU0WritePriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_CPU0WritePriorityLevel 0x00000003 |
| #define BA_MctrlDual_PriorityLevel_CPU1WritePriorityLevel 0x002C |
| #define B16MctrlDual_PriorityLevel_CPU1WritePriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_CPU1WritePriorityLevel 2 |
| #define LSb16MctrlDual_PriorityLevel_CPU1WritePriorityLevel 2 |
| #define bMctrlDual_PriorityLevel_CPU1WritePriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_CPU1WritePriorityLevel 0x0000000C |
| #define BA_MctrlDual_PriorityLevel_writePriorityLevel 0x002C |
| #define B16MctrlDual_PriorityLevel_writePriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_writePriorityLevel 4 |
| #define LSb16MctrlDual_PriorityLevel_writePriorityLevel 4 |
| #define bMctrlDual_PriorityLevel_writePriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_writePriorityLevel 0x00000030 |
| #define BA_MctrlDual_PriorityLevel_CPU0ReadPriorityLevel 0x002C |
| #define B16MctrlDual_PriorityLevel_CPU0ReadPriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_CPU0ReadPriorityLevel 6 |
| #define LSb16MctrlDual_PriorityLevel_CPU0ReadPriorityLevel 6 |
| #define bMctrlDual_PriorityLevel_CPU0ReadPriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_CPU0ReadPriorityLevel 0x000000C0 |
| #define BA_MctrlDual_PriorityLevel_CPU1ReadPriorityLevel 0x002D |
| #define B16MctrlDual_PriorityLevel_CPU1ReadPriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_CPU1ReadPriorityLevel 8 |
| #define LSb16MctrlDual_PriorityLevel_CPU1ReadPriorityLevel 8 |
| #define bMctrlDual_PriorityLevel_CPU1ReadPriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_CPU1ReadPriorityLevel 0x00000300 |
| #define BA_MctrlDual_PriorityLevel_read1PriorityLevel 0x002D |
| #define B16MctrlDual_PriorityLevel_read1PriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_read1PriorityLevel 10 |
| #define LSb16MctrlDual_PriorityLevel_read1PriorityLevel 10 |
| #define bMctrlDual_PriorityLevel_read1PriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_read1PriorityLevel 0x00000C00 |
| #define BA_MctrlDual_PriorityLevel_read2PriorityLevel 0x002D |
| #define B16MctrlDual_PriorityLevel_read2PriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_read2PriorityLevel 12 |
| #define LSb16MctrlDual_PriorityLevel_read2PriorityLevel 12 |
| #define bMctrlDual_PriorityLevel_read2PriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_read2PriorityLevel 0x00003000 |
| #define BA_MctrlDual_PriorityLevel_read3PriorityLevel 0x002D |
| #define B16MctrlDual_PriorityLevel_read3PriorityLevel 0x002C |
| #define LSb32MctrlDual_PriorityLevel_read3PriorityLevel 14 |
| #define LSb16MctrlDual_PriorityLevel_read3PriorityLevel 14 |
| #define bMctrlDual_PriorityLevel_read3PriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_read3PriorityLevel 0x0000C000 |
| #define BA_MctrlDual_PriorityLevel_read4PriorityLevel 0x002E |
| #define B16MctrlDual_PriorityLevel_read4PriorityLevel 0x002E |
| #define LSb32MctrlDual_PriorityLevel_read4PriorityLevel 16 |
| #define LSb16MctrlDual_PriorityLevel_read4PriorityLevel 0 |
| #define bMctrlDual_PriorityLevel_read4PriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_read4PriorityLevel 0x00030000 |
| #define BA_MctrlDual_PriorityLevel_read5PriorityLevel 0x002E |
| #define B16MctrlDual_PriorityLevel_read5PriorityLevel 0x002E |
| #define LSb32MctrlDual_PriorityLevel_read5PriorityLevel 18 |
| #define LSb16MctrlDual_PriorityLevel_read5PriorityLevel 2 |
| #define bMctrlDual_PriorityLevel_read5PriorityLevel 2 |
| #define MSK32MctrlDual_PriorityLevel_read5PriorityLevel 0x000C0000 |
| #define BA_MctrlDual_PriorityLevel_priorityMode 0x002E |
| #define B16MctrlDual_PriorityLevel_priorityMode 0x002E |
| #define LSb32MctrlDual_PriorityLevel_priorityMode 20 |
| #define LSb16MctrlDual_PriorityLevel_priorityMode 4 |
| #define bMctrlDual_PriorityLevel_priorityMode 1 |
| #define MSK32MctrlDual_PriorityLevel_priorityMode 0x00100000 |
| #define BA_MctrlDual_PriorityLevel_chArb0To1StopCount 0x002E |
| #define B16MctrlDual_PriorityLevel_chArb0To1StopCount 0x002E |
| #define LSb32MctrlDual_PriorityLevel_chArb0To1StopCount 21 |
| #define LSb16MctrlDual_PriorityLevel_chArb0To1StopCount 5 |
| #define bMctrlDual_PriorityLevel_chArb0To1StopCount 4 |
| #define MSK32MctrlDual_PriorityLevel_chArb0To1StopCount 0x01E00000 |
| #define BA_MctrlDual_PriorityLevel_chArb1To2StopCount 0x002F |
| #define B16MctrlDual_PriorityLevel_chArb1To2StopCount 0x002E |
| #define LSb32MctrlDual_PriorityLevel_chArb1To2StopCount 25 |
| #define LSb16MctrlDual_PriorityLevel_chArb1To2StopCount 9 |
| #define bMctrlDual_PriorityLevel_chArb1To2StopCount 4 |
| #define MSK32MctrlDual_PriorityLevel_chArb1To2StopCount 0x1E000000 |
| #define RA_MctrlDual_TTBStartAddr 0x0030 |
| #define BA_MctrlDual_TTBStartAddr_RESERVE_TTBSart 0x0030 |
| #define B16MctrlDual_TTBStartAddr_RESERVE_TTBSart 0x0030 |
| #define LSb32MctrlDual_TTBStartAddr_RESERVE_TTBSart 0 |
| #define LSb16MctrlDual_TTBStartAddr_RESERVE_TTBSart 0 |
| #define bMctrlDual_TTBStartAddr_RESERVE_TTBSart 5 |
| #define MSK32MctrlDual_TTBStartAddr_RESERVE_TTBSart 0x0000001F |
| #define BA_MctrlDual_TTBStartAddr_ttbStartAddr 0x0030 |
| #define B16MctrlDual_TTBStartAddr_ttbStartAddr 0x0030 |
| #define LSb32MctrlDual_TTBStartAddr_ttbStartAddr 5 |
| #define LSb16MctrlDual_TTBStartAddr_ttbStartAddr 5 |
| #define bMctrlDual_TTBStartAddr_ttbStartAddr 27 |
| #define MSK32MctrlDual_TTBStartAddr_ttbStartAddr 0xFFFFFFE0 |
| #define RA_MctrlDual_TTBEndAddr 0x0034 |
| #define BA_MctrlDual_TTBEndAddr_RESERVE_TTBEnd 0x0034 |
| #define B16MctrlDual_TTBEndAddr_RESERVE_TTBEnd 0x0034 |
| #define LSb32MctrlDual_TTBEndAddr_RESERVE_TTBEnd 0 |
| #define LSb16MctrlDual_TTBEndAddr_RESERVE_TTBEnd 0 |
| #define bMctrlDual_TTBEndAddr_RESERVE_TTBEnd 5 |
| #define MSK32MctrlDual_TTBEndAddr_RESERVE_TTBEnd 0x0000001F |
| #define BA_MctrlDual_TTBEndAddr_ttbEndAddr 0x0034 |
| #define B16MctrlDual_TTBEndAddr_ttbEndAddr 0x0034 |
| #define LSb32MctrlDual_TTBEndAddr_ttbEndAddr 5 |
| #define LSb16MctrlDual_TTBEndAddr_ttbEndAddr 5 |
| #define bMctrlDual_TTBEndAddr_ttbEndAddr 27 |
| #define MSK32MctrlDual_TTBEndAddr_ttbEndAddr 0xFFFFFFE0 |
| #define RA_MctrlDual_TTBWritePrt 0x0038 |
| #define BA_MctrlDual_TTBWritePrt_RESERVE_TTBWPTR 0x0038 |
| #define B16MctrlDual_TTBWritePrt_RESERVE_TTBWPTR 0x0038 |
| #define LSb32MctrlDual_TTBWritePrt_RESERVE_TTBWPTR 0 |
| #define LSb16MctrlDual_TTBWritePrt_RESERVE_TTBWPTR 0 |
| #define bMctrlDual_TTBWritePrt_RESERVE_TTBWPTR 5 |
| #define MSK32MctrlDual_TTBWritePrt_RESERVE_TTBWPTR 0x0000001F |
| #define BA_MctrlDual_TTBWritePrt_ttbWPtr 0x0038 |
| #define B16MctrlDual_TTBWritePrt_ttbWPtr 0x0038 |
| #define LSb32MctrlDual_TTBWritePrt_ttbWPtr 5 |
| #define LSb16MctrlDual_TTBWritePrt_ttbWPtr 5 |
| #define bMctrlDual_TTBWritePrt_ttbWPtr 27 |
| #define MSK32MctrlDual_TTBWritePrt_ttbWPtr 0xFFFFFFE0 |
| #define RA_MctrlDual_cpu0WPort 0x003C |
| #define RA_MctrlDual_cpu1WPort 0x005C |
| #define RA_MctrlDual_busWPort 0x007C |
| #define RA_MctrlDual_cpu0RPort 0x009C |
| #define RA_MctrlDual_cpu1RPort 0x00BC |
| #define RA_MctrlDual_busRPort1 0x00DC |
| #define RA_MctrlDual_busRPort2 0x00FC |
| #define RA_MctrlDual_busRPort3 0x011C |
| #define RA_MctrlDual_busRPort4 0x013C |
| #define RA_MctrlDual_busRPort5 0x015C |
| #define RA_MctrlDual_DebugTrigger 0x017C |
| #define BA_MctrlDual_DebugTrigger_mt_loop 0x017C |
| #define B16MctrlDual_DebugTrigger_mt_loop 0x017C |
| #define LSb32MctrlDual_DebugTrigger_mt_loop 0 |
| #define LSb16MctrlDual_DebugTrigger_mt_loop 0 |
| #define bMctrlDual_DebugTrigger_mt_loop 1 |
| #define MSK32MctrlDual_DebugTrigger_mt_loop 0x00000001 |
| #define BA_MctrlDual_DebugTrigger_mt_active 0x017C |
| #define B16MctrlDual_DebugTrigger_mt_active 0x017C |
| #define LSb32MctrlDual_DebugTrigger_mt_active 1 |
| #define LSb16MctrlDual_DebugTrigger_mt_active 1 |
| #define bMctrlDual_DebugTrigger_mt_active 1 |
| #define MSK32MctrlDual_DebugTrigger_mt_active 0x00000002 |
| #define BA_MctrlDual_DebugTrigger_mt_mode 0x017C |
| #define B16MctrlDual_DebugTrigger_mt_mode 0x017C |
| #define LSb32MctrlDual_DebugTrigger_mt_mode 2 |
| #define LSb16MctrlDual_DebugTrigger_mt_mode 2 |
| #define bMctrlDual_DebugTrigger_mt_mode 1 |
| #define MSK32MctrlDual_DebugTrigger_mt_mode 0x00000004 |
| #define BA_MctrlDual_DebugTrigger_mt_coe 0x017C |
| #define B16MctrlDual_DebugTrigger_mt_coe 0x017C |
| #define LSb32MctrlDual_DebugTrigger_mt_coe 3 |
| #define LSb16MctrlDual_DebugTrigger_mt_coe 3 |
| #define bMctrlDual_DebugTrigger_mt_coe 1 |
| #define MSK32MctrlDual_DebugTrigger_mt_coe 0x00000008 |
| #define RA_MctrlDual_DebugStAddr 0x0180 |
| #define BA_MctrlDual_DebugStAddr_addr_start 0x0180 |
| #define B16MctrlDual_DebugStAddr_addr_start 0x0180 |
| #define LSb32MctrlDual_DebugStAddr_addr_start 0 |
| #define LSb16MctrlDual_DebugStAddr_addr_start 0 |
| #define bMctrlDual_DebugStAddr_addr_start 32 |
| #define MSK32MctrlDual_DebugStAddr_addr_start 0xFFFFFFFF |
| #define RA_MctrlDual_DebugEdAddr 0x0184 |
| #define BA_MctrlDual_DebugEdAddr_addr_end 0x0184 |
| #define B16MctrlDual_DebugEdAddr_addr_end 0x0184 |
| #define LSb32MctrlDual_DebugEdAddr_addr_end 0 |
| #define LSb16MctrlDual_DebugEdAddr_addr_end 0 |
| #define bMctrlDual_DebugEdAddr_addr_end 32 |
| #define MSK32MctrlDual_DebugEdAddr_addr_end 0xFFFFFFFF |
| #define RA_MctrlDual_DebugStatus 0x0188 |
| #define BA_MctrlDual_DebugStatus_mt_done 0x0188 |
| #define B16MctrlDual_DebugStatus_mt_done 0x0188 |
| #define LSb32MctrlDual_DebugStatus_mt_done 0 |
| #define LSb16MctrlDual_DebugStatus_mt_done 0 |
| #define bMctrlDual_DebugStatus_mt_done 1 |
| #define MSK32MctrlDual_DebugStatus_mt_done 0x00000001 |
| #define BA_MctrlDual_DebugStatus_mt_error 0x0188 |
| #define B16MctrlDual_DebugStatus_mt_error 0x0188 |
| #define LSb32MctrlDual_DebugStatus_mt_error 1 |
| #define LSb16MctrlDual_DebugStatus_mt_error 1 |
| #define bMctrlDual_DebugStatus_mt_error 2 |
| #define MSK32MctrlDual_DebugStatus_mt_error 0x00000006 |
| #define RA_MctrlDual_DebugRaddr 0x018C |
| #define BA_MctrlDual_DebugRaddr_mt_raddr 0x018C |
| #define B16MctrlDual_DebugRaddr_mt_raddr 0x018C |
| #define LSb32MctrlDual_DebugRaddr_mt_raddr 0 |
| #define LSb16MctrlDual_DebugRaddr_mt_raddr 0 |
| #define bMctrlDual_DebugRaddr_mt_raddr 32 |
| #define MSK32MctrlDual_DebugRaddr_mt_raddr 0xFFFFFFFF |
| #define RA_MctrlDual_DebugRdata0 0x0190 |
| #define BA_MctrlDual_DebugRdata0_mt_rdata0 0x0190 |
| #define B16MctrlDual_DebugRdata0_mt_rdata0 0x0190 |
| #define LSb32MctrlDual_DebugRdata0_mt_rdata0 0 |
| #define LSb16MctrlDual_DebugRdata0_mt_rdata0 0 |
| #define bMctrlDual_DebugRdata0_mt_rdata0 32 |
| #define MSK32MctrlDual_DebugRdata0_mt_rdata0 0xFFFFFFFF |
| #define RA_MctrlDual_DebugRdata1 0x0194 |
| #define BA_MctrlDual_DebugRdata1_mt_rdata1 0x0194 |
| #define B16MctrlDual_DebugRdata1_mt_rdata1 0x0194 |
| #define LSb32MctrlDual_DebugRdata1_mt_rdata1 0 |
| #define LSb16MctrlDual_DebugRdata1_mt_rdata1 0 |
| #define bMctrlDual_DebugRdata1_mt_rdata1 32 |
| #define MSK32MctrlDual_DebugRdata1_mt_rdata1 0xFFFFFFFF |
| #define RA_MctrlDual_DebugOData 0x0198 |
| #define BA_MctrlDual_DebugOData_mt_odd 0x0198 |
| #define B16MctrlDual_DebugOData_mt_odd 0x0198 |
| #define LSb32MctrlDual_DebugOData_mt_odd 0 |
| #define LSb16MctrlDual_DebugOData_mt_odd 0 |
| #define bMctrlDual_DebugOData_mt_odd 32 |
| #define MSK32MctrlDual_DebugOData_mt_odd 0xFFFFFFFF |
| #define RA_MctrlDual_DebugEData 0x019C |
| #define BA_MctrlDual_DebugEData_mt_even 0x019C |
| #define B16MctrlDual_DebugEData_mt_even 0x019C |
| #define LSb32MctrlDual_DebugEData_mt_even 0 |
| #define LSb16MctrlDual_DebugEData_mt_even 0 |
| #define bMctrlDual_DebugEData_mt_even 32 |
| #define MSK32MctrlDual_DebugEData_mt_even 0xFFFFFFFF |
| #define RA_MctrlDual_PHY 0x01A0 |
| #define RA_MctrlDual_InterruptMask 0x0200 |
| #define BA_MctrlDual_InterruptMask_intMaskPort0 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPort0 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPort0 0 |
| #define LSb16MctrlDual_InterruptMask_intMaskPort0 0 |
| #define bMctrlDual_InterruptMask_intMaskPort0 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPort0 0x00000001 |
| #define BA_MctrlDual_InterruptMask_intMaskPort1 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPort1 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPort1 1 |
| #define LSb16MctrlDual_InterruptMask_intMaskPort1 1 |
| #define bMctrlDual_InterruptMask_intMaskPort1 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPort1 0x00000002 |
| #define BA_MctrlDual_InterruptMask_intMaskPort2 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPort2 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPort2 2 |
| #define LSb16MctrlDual_InterruptMask_intMaskPort2 2 |
| #define bMctrlDual_InterruptMask_intMaskPort2 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPort2 0x00000004 |
| #define BA_MctrlDual_InterruptMask_intMaskPort3 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPort3 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPort3 3 |
| #define LSb16MctrlDual_InterruptMask_intMaskPort3 3 |
| #define bMctrlDual_InterruptMask_intMaskPort3 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPort3 0x00000008 |
| #define BA_MctrlDual_InterruptMask_intMaskPor4 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPor4 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPor4 4 |
| #define LSb16MctrlDual_InterruptMask_intMaskPor4 4 |
| #define bMctrlDual_InterruptMask_intMaskPor4 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPor4 0x00000010 |
| #define BA_MctrlDual_InterruptMask_intMaskPort5 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskPort5 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskPort5 5 |
| #define LSb16MctrlDual_InterruptMask_intMaskPort5 5 |
| #define bMctrlDual_InterruptMask_intMaskPort5 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskPort5 0x00000020 |
| #define BA_MctrlDual_InterruptMask_intMaskCpu0R 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskCpu0R 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskCpu0R 6 |
| #define LSb16MctrlDual_InterruptMask_intMaskCpu0R 6 |
| #define bMctrlDual_InterruptMask_intMaskCpu0R 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskCpu0R 0x00000040 |
| #define BA_MctrlDual_InterruptMask_intMaskCpu1R 0x0200 |
| #define B16MctrlDual_InterruptMask_intMaskCpu1R 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskCpu1R 7 |
| #define LSb16MctrlDual_InterruptMask_intMaskCpu1R 7 |
| #define bMctrlDual_InterruptMask_intMaskCpu1R 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskCpu1R 0x00000080 |
| #define BA_MctrlDual_InterruptMask_intMaskCpu0W 0x0201 |
| #define B16MctrlDual_InterruptMask_intMaskCpu0W 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskCpu0W 8 |
| #define LSb16MctrlDual_InterruptMask_intMaskCpu0W 8 |
| #define bMctrlDual_InterruptMask_intMaskCpu0W 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskCpu0W 0x00000100 |
| #define BA_MctrlDual_InterruptMask_intMaskCpu1W 0x0201 |
| #define B16MctrlDual_InterruptMask_intMaskCpu1W 0x0200 |
| #define LSb32MctrlDual_InterruptMask_intMaskCpu1W 9 |
| #define LSb16MctrlDual_InterruptMask_intMaskCpu1W 9 |
| #define bMctrlDual_InterruptMask_intMaskCpu1W 1 |
| #define MSK32MctrlDual_InterruptMask_intMaskCpu1W 0x00000200 |
| #define RA_MctrlDual_interruptStatus 0x0204 |
| #define BA_MctrlDual_interruptStatus_interruptPort0 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort0 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort0 0 |
| #define LSb16MctrlDual_interruptStatus_interruptPort0 0 |
| #define bMctrlDual_interruptStatus_interruptPort0 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort0 0x00000001 |
| #define BA_MctrlDual_interruptStatus_interruptPort1 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort1 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort1 1 |
| #define LSb16MctrlDual_interruptStatus_interruptPort1 1 |
| #define bMctrlDual_interruptStatus_interruptPort1 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort1 0x00000002 |
| #define BA_MctrlDual_interruptStatus_interruptPort2 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort2 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort2 2 |
| #define LSb16MctrlDual_interruptStatus_interruptPort2 2 |
| #define bMctrlDual_interruptStatus_interruptPort2 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort2 0x00000004 |
| #define BA_MctrlDual_interruptStatus_interruptPort3 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort3 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort3 3 |
| #define LSb16MctrlDual_interruptStatus_interruptPort3 3 |
| #define bMctrlDual_interruptStatus_interruptPort3 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort3 0x00000008 |
| #define BA_MctrlDual_interruptStatus_interruptPort4 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort4 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort4 4 |
| #define LSb16MctrlDual_interruptStatus_interruptPort4 4 |
| #define bMctrlDual_interruptStatus_interruptPort4 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort4 0x00000010 |
| #define BA_MctrlDual_interruptStatus_interruptPort5 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptPort5 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptPort5 5 |
| #define LSb16MctrlDual_interruptStatus_interruptPort5 5 |
| #define bMctrlDual_interruptStatus_interruptPort5 1 |
| #define MSK32MctrlDual_interruptStatus_interruptPort5 0x00000020 |
| #define BA_MctrlDual_interruptStatus_interruptCpu0W 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptCpu0W 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptCpu0W 6 |
| #define LSb16MctrlDual_interruptStatus_interruptCpu0W 6 |
| #define bMctrlDual_interruptStatus_interruptCpu0W 1 |
| #define MSK32MctrlDual_interruptStatus_interruptCpu0W 0x00000040 |
| #define BA_MctrlDual_interruptStatus_interruptCpu0R 0x0204 |
| #define B16MctrlDual_interruptStatus_interruptCpu0R 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptCpu0R 7 |
| #define LSb16MctrlDual_interruptStatus_interruptCpu0R 7 |
| #define bMctrlDual_interruptStatus_interruptCpu0R 1 |
| #define MSK32MctrlDual_interruptStatus_interruptCpu0R 0x00000080 |
| #define BA_MctrlDual_interruptStatus_interruptCpu1W 0x0205 |
| #define B16MctrlDual_interruptStatus_interruptCpu1W 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptCpu1W 8 |
| #define LSb16MctrlDual_interruptStatus_interruptCpu1W 8 |
| #define bMctrlDual_interruptStatus_interruptCpu1W 1 |
| #define MSK32MctrlDual_interruptStatus_interruptCpu1W 0x00000100 |
| #define BA_MctrlDual_interruptStatus_interruptCpu1R 0x0205 |
| #define B16MctrlDual_interruptStatus_interruptCpu1R 0x0204 |
| #define LSb32MctrlDual_interruptStatus_interruptCpu1R 9 |
| #define LSb16MctrlDual_interruptStatus_interruptCpu1R 9 |
| #define bMctrlDual_interruptStatus_interruptCpu1R 1 |
| #define MSK32MctrlDual_interruptStatus_interruptCpu1R 0x00000200 |
| #define RA_MctrlDual_LFSRData 0x0208 |
| #define BA_MctrlDual_LFSRData_lfsrOut 0x0208 |
| #define B16MctrlDual_LFSRData_lfsrOut 0x0208 |
| #define LSb32MctrlDual_LFSRData_lfsrOut 0 |
| #define LSb16MctrlDual_LFSRData_lfsrOut 0 |
| #define bMctrlDual_LFSRData_lfsrOut 32 |
| #define MSK32MctrlDual_LFSRData_lfsrOut 0xFFFFFFFF |
| #define RA_MctrlDual_PerfCounterRst 0x020C |
| #define BA_MctrlDual_PerfCounterRst_cycleCountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_cycleCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_cycleCountRst 0 |
| #define LSb16MctrlDual_PerfCounterRst_cycleCountRst 0 |
| #define bMctrlDual_PerfCounterRst_cycleCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cycleCountRst 0x00000001 |
| #define BA_MctrlDual_PerfCounterRst_ctrlIdleCountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_ctrlIdleCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_ctrlIdleCountRst 1 |
| #define LSb16MctrlDual_PerfCounterRst_ctrlIdleCountRst 1 |
| #define bMctrlDual_PerfCounterRst_ctrlIdleCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_ctrlIdleCountRst 0x00000002 |
| #define BA_MctrlDual_PerfCounterRst_dBusBusyCh0CountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_dBusBusyCh0CountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_dBusBusyCh0CountRst 2 |
| #define LSb16MctrlDual_PerfCounterRst_dBusBusyCh0CountRst 2 |
| #define bMctrlDual_PerfCounterRst_dBusBusyCh0CountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_dBusBusyCh0CountRst 0x00000004 |
| #define BA_MctrlDual_PerfCounterRst_dBusBusyCh1CountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_dBusBusyCh1CountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_dBusBusyCh1CountRst 3 |
| #define LSb16MctrlDual_PerfCounterRst_dBusBusyCh1CountRst 3 |
| #define bMctrlDual_PerfCounterRst_dBusBusyCh1CountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_dBusBusyCh1CountRst 0x00000008 |
| #define BA_MctrlDual_PerfCounterRst_busyCh0CountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_busyCh0CountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_busyCh0CountRst 4 |
| #define LSb16MctrlDual_PerfCounterRst_busyCh0CountRst 4 |
| #define bMctrlDual_PerfCounterRst_busyCh0CountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_busyCh0CountRst 0x00000010 |
| #define BA_MctrlDual_PerfCounterRst_busyCh1CountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_busyCh1CountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_busyCh1CountRst 5 |
| #define LSb16MctrlDual_PerfCounterRst_busyCh1CountRst 5 |
| #define bMctrlDual_PerfCounterRst_busyCh1CountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_busyCh1CountRst 0x00000020 |
| #define BA_MctrlDual_PerfCounterRst_cpu0WReqCountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_cpu0WReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_cpu0WReqCountRst 6 |
| #define LSb16MctrlDual_PerfCounterRst_cpu0WReqCountRst 6 |
| #define bMctrlDual_PerfCounterRst_cpu0WReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu0WReqCountRst 0x00000040 |
| #define BA_MctrlDual_PerfCounterRst_cpu1WReqCountRst 0x020C |
| #define B16MctrlDual_PerfCounterRst_cpu1WReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_cpu1WReqCountRst 7 |
| #define LSb16MctrlDual_PerfCounterRst_cpu1WReqCountRst 7 |
| #define bMctrlDual_PerfCounterRst_cpu1WReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu1WReqCountRst 0x00000080 |
| #define BA_MctrlDual_PerfCounterRst_cpu0RReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_cpu0RReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_cpu0RReqCountRst 8 |
| #define LSb16MctrlDual_PerfCounterRst_cpu0RReqCountRst 8 |
| #define bMctrlDual_PerfCounterRst_cpu0RReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu0RReqCountRst 0x00000100 |
| #define BA_MctrlDual_PerfCounterRst_cpu1RReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_cpu1RReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_cpu1RReqCountRst 9 |
| #define LSb16MctrlDual_PerfCounterRst_cpu1RReqCountRst 9 |
| #define bMctrlDual_PerfCounterRst_cpu1RReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu1RReqCountRst 0x00000200 |
| #define BA_MctrlDual_PerfCounterRst_port0ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port0ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port0ReqCountRst 10 |
| #define LSb16MctrlDual_PerfCounterRst_port0ReqCountRst 10 |
| #define bMctrlDual_PerfCounterRst_port0ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port0ReqCountRst 0x00000400 |
| #define BA_MctrlDual_PerfCounterRst_port1ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port1ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port1ReqCountRst 11 |
| #define LSb16MctrlDual_PerfCounterRst_port1ReqCountRst 11 |
| #define bMctrlDual_PerfCounterRst_port1ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port1ReqCountRst 0x00000800 |
| #define BA_MctrlDual_PerfCounterRst_port2ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port2ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port2ReqCountRst 12 |
| #define LSb16MctrlDual_PerfCounterRst_port2ReqCountRst 12 |
| #define bMctrlDual_PerfCounterRst_port2ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port2ReqCountRst 0x00001000 |
| #define BA_MctrlDual_PerfCounterRst_port3ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port3ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port3ReqCountRst 13 |
| #define LSb16MctrlDual_PerfCounterRst_port3ReqCountRst 13 |
| #define bMctrlDual_PerfCounterRst_port3ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port3ReqCountRst 0x00002000 |
| #define BA_MctrlDual_PerfCounterRst_port4ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port4ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port4ReqCountRst 14 |
| #define LSb16MctrlDual_PerfCounterRst_port4ReqCountRst 14 |
| #define bMctrlDual_PerfCounterRst_port4ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port4ReqCountRst 0x00004000 |
| #define BA_MctrlDual_PerfCounterRst_port5ReqCountRst 0x020D |
| #define B16MctrlDual_PerfCounterRst_port5ReqCountRst 0x020C |
| #define LSb32MctrlDual_PerfCounterRst_port5ReqCountRst 15 |
| #define LSb16MctrlDual_PerfCounterRst_port5ReqCountRst 15 |
| #define bMctrlDual_PerfCounterRst_port5ReqCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port5ReqCountRst 0x00008000 |
| #define BA_MctrlDual_PerfCounterRst_port0FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port0FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port0FCCountRst 16 |
| #define LSb16MctrlDual_PerfCounterRst_port0FCCountRst 0 |
| #define bMctrlDual_PerfCounterRst_port0FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port0FCCountRst 0x00010000 |
| #define BA_MctrlDual_PerfCounterRst_port1FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port1FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port1FCCountRst 17 |
| #define LSb16MctrlDual_PerfCounterRst_port1FCCountRst 1 |
| #define bMctrlDual_PerfCounterRst_port1FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port1FCCountRst 0x00020000 |
| #define BA_MctrlDual_PerfCounterRst_port2FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port2FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port2FCCountRst 18 |
| #define LSb16MctrlDual_PerfCounterRst_port2FCCountRst 2 |
| #define bMctrlDual_PerfCounterRst_port2FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port2FCCountRst 0x00040000 |
| #define BA_MctrlDual_PerfCounterRst_port3FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port3FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port3FCCountRst 19 |
| #define LSb16MctrlDual_PerfCounterRst_port3FCCountRst 3 |
| #define bMctrlDual_PerfCounterRst_port3FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port3FCCountRst 0x00080000 |
| #define BA_MctrlDual_PerfCounterRst_port4FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port4FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port4FCCountRst 20 |
| #define LSb16MctrlDual_PerfCounterRst_port4FCCountRst 4 |
| #define bMctrlDual_PerfCounterRst_port4FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port4FCCountRst 0x00100000 |
| #define BA_MctrlDual_PerfCounterRst_port5FCCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_port5FCCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_port5FCCountRst 21 |
| #define LSb16MctrlDual_PerfCounterRst_port5FCCountRst 5 |
| #define bMctrlDual_PerfCounterRst_port5FCCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_port5FCCountRst 0x00200000 |
| #define BA_MctrlDual_PerfCounterRst_cpu0WSeCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_cpu0WSeCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_cpu0WSeCountRst 22 |
| #define LSb16MctrlDual_PerfCounterRst_cpu0WSeCountRst 6 |
| #define bMctrlDual_PerfCounterRst_cpu0WSeCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu0WSeCountRst 0x00400000 |
| #define BA_MctrlDual_PerfCounterRst_cpu0RSeCountRst 0x020E |
| #define B16MctrlDual_PerfCounterRst_cpu0RSeCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_cpu0RSeCountRst 23 |
| #define LSb16MctrlDual_PerfCounterRst_cpu0RSeCountRst 7 |
| #define bMctrlDual_PerfCounterRst_cpu0RSeCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_cpu0RSeCountRst 0x00800000 |
| #define BA_MctrlDual_PerfCounterRst_extMWSeCountRst 0x020F |
| #define B16MctrlDual_PerfCounterRst_extMWSeCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_extMWSeCountRst 24 |
| #define LSb16MctrlDual_PerfCounterRst_extMWSeCountRst 8 |
| #define bMctrlDual_PerfCounterRst_extMWSeCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_extMWSeCountRst 0x01000000 |
| #define BA_MctrlDual_PerfCounterRst_extMRSeCountRst 0x020F |
| #define B16MctrlDual_PerfCounterRst_extMRSeCountRst 0x020E |
| #define LSb32MctrlDual_PerfCounterRst_extMRSeCountRst 25 |
| #define LSb16MctrlDual_PerfCounterRst_extMRSeCountRst 9 |
| #define bMctrlDual_PerfCounterRst_extMRSeCountRst 1 |
| #define MSK32MctrlDual_PerfCounterRst_extMRSeCountRst 0x02000000 |
| #define RA_MctrlDual_CycleCount 0x0210 |
| #define BA_MctrlDual_CycleCount_value 0x0210 |
| #define B16MctrlDual_CycleCount_value 0x0210 |
| #define LSb32MctrlDual_CycleCount_value 0 |
| #define LSb16MctrlDual_CycleCount_value 0 |
| #define bMctrlDual_CycleCount_value 32 |
| #define MSK32MctrlDual_CycleCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_ReqIdleCount 0x0214 |
| #define BA_MctrlDual_ReqIdleCount_value 0x0214 |
| #define B16MctrlDual_ReqIdleCount_value 0x0214 |
| #define LSb32MctrlDual_ReqIdleCount_value 0 |
| #define LSb16MctrlDual_ReqIdleCount_value 0 |
| #define bMctrlDual_ReqIdleCount_value 32 |
| #define MSK32MctrlDual_ReqIdleCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_oneChActCount 0x0218 |
| #define BA_MctrlDual_oneChActCount_value 0x0218 |
| #define B16MctrlDual_oneChActCount_value 0x0218 |
| #define LSb32MctrlDual_oneChActCount_value 0 |
| #define LSb16MctrlDual_oneChActCount_value 0 |
| #define bMctrlDual_oneChActCount_value 32 |
| #define MSK32MctrlDual_oneChActCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_DBusyCountCh0 0x021C |
| #define BA_MctrlDual_DBusyCountCh0_value 0x021C |
| #define B16MctrlDual_DBusyCountCh0_value 0x021C |
| #define LSb32MctrlDual_DBusyCountCh0_value 0 |
| #define LSb16MctrlDual_DBusyCountCh0_value 0 |
| #define bMctrlDual_DBusyCountCh0_value 32 |
| #define MSK32MctrlDual_DBusyCountCh0_value 0xFFFFFFFF |
| #define RA_MctrlDual_DBusyCountCh1 0x0220 |
| #define BA_MctrlDual_DBusyCountCh1_value 0x0220 |
| #define B16MctrlDual_DBusyCountCh1_value 0x0220 |
| #define LSb32MctrlDual_DBusyCountCh1_value 0 |
| #define LSb16MctrlDual_DBusyCountCh1_value 0 |
| #define bMctrlDual_DBusyCountCh1_value 32 |
| #define MSK32MctrlDual_DBusyCountCh1_value 0xFFFFFFFF |
| #define RA_MctrlDual_busyCountCh0 0x0224 |
| #define BA_MctrlDual_busyCountCh0_value 0x0224 |
| #define B16MctrlDual_busyCountCh0_value 0x0224 |
| #define LSb32MctrlDual_busyCountCh0_value 0 |
| #define LSb16MctrlDual_busyCountCh0_value 0 |
| #define bMctrlDual_busyCountCh0_value 32 |
| #define MSK32MctrlDual_busyCountCh0_value 0xFFFFFFFF |
| #define RA_MctrlDual_busyCountCh1 0x0228 |
| #define BA_MctrlDual_busyCountCh1_value 0x0228 |
| #define B16MctrlDual_busyCountCh1_value 0x0228 |
| #define LSb32MctrlDual_busyCountCh1_value 0 |
| #define LSb16MctrlDual_busyCountCh1_value 0 |
| #define bMctrlDual_busyCountCh1_value 32 |
| #define MSK32MctrlDual_busyCountCh1_value 0xFFFFFFFF |
| #define RA_MctrlDual_CPU0WReqCount 0x022C |
| #define BA_MctrlDual_CPU0WReqCount_value 0x022C |
| #define B16MctrlDual_CPU0WReqCount_value 0x022C |
| #define LSb32MctrlDual_CPU0WReqCount_value 0 |
| #define LSb16MctrlDual_CPU0WReqCount_value 0 |
| #define bMctrlDual_CPU0WReqCount_value 32 |
| #define MSK32MctrlDual_CPU0WReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_CPU1WReqCount 0x0230 |
| #define BA_MctrlDual_CPU1WReqCount_value 0x0230 |
| #define B16MctrlDual_CPU1WReqCount_value 0x0230 |
| #define LSb32MctrlDual_CPU1WReqCount_value 0 |
| #define LSb16MctrlDual_CPU1WReqCount_value 0 |
| #define bMctrlDual_CPU1WReqCount_value 32 |
| #define MSK32MctrlDual_CPU1WReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_CPU0RReqCount 0x0234 |
| #define BA_MctrlDual_CPU0RReqCount_value 0x0234 |
| #define B16MctrlDual_CPU0RReqCount_value 0x0234 |
| #define LSb32MctrlDual_CPU0RReqCount_value 0 |
| #define LSb16MctrlDual_CPU0RReqCount_value 0 |
| #define bMctrlDual_CPU0RReqCount_value 32 |
| #define MSK32MctrlDual_CPU0RReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_CPU1RReqCount 0x0238 |
| #define BA_MctrlDual_CPU1RReqCount_value 0x0238 |
| #define B16MctrlDual_CPU1RReqCount_value 0x0238 |
| #define LSb32MctrlDual_CPU1RReqCount_value 0 |
| #define LSb16MctrlDual_CPU1RReqCount_value 0 |
| #define bMctrlDual_CPU1RReqCount_value 32 |
| #define MSK32MctrlDual_CPU1RReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port0ReqCount 0x023C |
| #define BA_MctrlDual_Port0ReqCount_value 0x023C |
| #define B16MctrlDual_Port0ReqCount_value 0x023C |
| #define LSb32MctrlDual_Port0ReqCount_value 0 |
| #define LSb16MctrlDual_Port0ReqCount_value 0 |
| #define bMctrlDual_Port0ReqCount_value 32 |
| #define MSK32MctrlDual_Port0ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port1ReqCount 0x0240 |
| #define BA_MctrlDual_Port1ReqCount_value 0x0240 |
| #define B16MctrlDual_Port1ReqCount_value 0x0240 |
| #define LSb32MctrlDual_Port1ReqCount_value 0 |
| #define LSb16MctrlDual_Port1ReqCount_value 0 |
| #define bMctrlDual_Port1ReqCount_value 32 |
| #define MSK32MctrlDual_Port1ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port2ReqCount 0x0244 |
| #define BA_MctrlDual_Port2ReqCount_value 0x0244 |
| #define B16MctrlDual_Port2ReqCount_value 0x0244 |
| #define LSb32MctrlDual_Port2ReqCount_value 0 |
| #define LSb16MctrlDual_Port2ReqCount_value 0 |
| #define bMctrlDual_Port2ReqCount_value 32 |
| #define MSK32MctrlDual_Port2ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port3ReqCount 0x0248 |
| #define BA_MctrlDual_Port3ReqCount_value 0x0248 |
| #define B16MctrlDual_Port3ReqCount_value 0x0248 |
| #define LSb32MctrlDual_Port3ReqCount_value 0 |
| #define LSb16MctrlDual_Port3ReqCount_value 0 |
| #define bMctrlDual_Port3ReqCount_value 32 |
| #define MSK32MctrlDual_Port3ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port4ReqCount 0x024C |
| #define BA_MctrlDual_Port4ReqCount_value 0x024C |
| #define B16MctrlDual_Port4ReqCount_value 0x024C |
| #define LSb32MctrlDual_Port4ReqCount_value 0 |
| #define LSb16MctrlDual_Port4ReqCount_value 0 |
| #define bMctrlDual_Port4ReqCount_value 32 |
| #define MSK32MctrlDual_Port4ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port5ReqCount 0x0250 |
| #define BA_MctrlDual_Port5ReqCount_value 0x0250 |
| #define B16MctrlDual_Port5ReqCount_value 0x0250 |
| #define LSb32MctrlDual_Port5ReqCount_value 0 |
| #define LSb16MctrlDual_Port5ReqCount_value 0 |
| #define bMctrlDual_Port5ReqCount_value 32 |
| #define MSK32MctrlDual_Port5ReqCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port0FCCount 0x0254 |
| #define BA_MctrlDual_Port0FCCount_value 0x0254 |
| #define B16MctrlDual_Port0FCCount_value 0x0254 |
| #define LSb32MctrlDual_Port0FCCount_value 0 |
| #define LSb16MctrlDual_Port0FCCount_value 0 |
| #define bMctrlDual_Port0FCCount_value 32 |
| #define MSK32MctrlDual_Port0FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port1FCCount 0x0258 |
| #define BA_MctrlDual_Port1FCCount_value 0x0258 |
| #define B16MctrlDual_Port1FCCount_value 0x0258 |
| #define LSb32MctrlDual_Port1FCCount_value 0 |
| #define LSb16MctrlDual_Port1FCCount_value 0 |
| #define bMctrlDual_Port1FCCount_value 32 |
| #define MSK32MctrlDual_Port1FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port2FCCount 0x025C |
| #define BA_MctrlDual_Port2FCCount_value 0x025C |
| #define B16MctrlDual_Port2FCCount_value 0x025C |
| #define LSb32MctrlDual_Port2FCCount_value 0 |
| #define LSb16MctrlDual_Port2FCCount_value 0 |
| #define bMctrlDual_Port2FCCount_value 32 |
| #define MSK32MctrlDual_Port2FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port3FCCount 0x0260 |
| #define BA_MctrlDual_Port3FCCount_value 0x0260 |
| #define B16MctrlDual_Port3FCCount_value 0x0260 |
| #define LSb32MctrlDual_Port3FCCount_value 0 |
| #define LSb16MctrlDual_Port3FCCount_value 0 |
| #define bMctrlDual_Port3FCCount_value 32 |
| #define MSK32MctrlDual_Port3FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port4FCCount 0x0264 |
| #define BA_MctrlDual_Port4FCCount_value 0x0264 |
| #define B16MctrlDual_Port4FCCount_value 0x0264 |
| #define LSb32MctrlDual_Port4FCCount_value 0 |
| #define LSb16MctrlDual_Port4FCCount_value 0 |
| #define bMctrlDual_Port4FCCount_value 32 |
| #define MSK32MctrlDual_Port4FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Port5FCCount 0x0268 |
| #define BA_MctrlDual_Port5FCCount_value 0x0268 |
| #define B16MctrlDual_Port5FCCount_value 0x0268 |
| #define LSb32MctrlDual_Port5FCCount_value 0 |
| #define LSb16MctrlDual_Port5FCCount_value 0 |
| #define bMctrlDual_Port5FCCount_value 32 |
| #define MSK32MctrlDual_Port5FCCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Cpu0WSeCount 0x026C |
| #define BA_MctrlDual_Cpu0WSeCount_value 0x026C |
| #define B16MctrlDual_Cpu0WSeCount_value 0x026C |
| #define LSb32MctrlDual_Cpu0WSeCount_value 0 |
| #define LSb16MctrlDual_Cpu0WSeCount_value 0 |
| #define bMctrlDual_Cpu0WSeCount_value 32 |
| #define MSK32MctrlDual_Cpu0WSeCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_Cpu0RSeCount 0x0270 |
| #define BA_MctrlDual_Cpu0RSeCount_value 0x0270 |
| #define B16MctrlDual_Cpu0RSeCount_value 0x0270 |
| #define LSb32MctrlDual_Cpu0RSeCount_value 0 |
| #define LSb16MctrlDual_Cpu0RSeCount_value 0 |
| #define bMctrlDual_Cpu0RSeCount_value 32 |
| #define MSK32MctrlDual_Cpu0RSeCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_ExtMWSeCount 0x0274 |
| #define BA_MctrlDual_ExtMWSeCount_value 0x0274 |
| #define B16MctrlDual_ExtMWSeCount_value 0x0274 |
| #define LSb32MctrlDual_ExtMWSeCount_value 0 |
| #define LSb16MctrlDual_ExtMWSeCount_value 0 |
| #define bMctrlDual_ExtMWSeCount_value 32 |
| #define MSK32MctrlDual_ExtMWSeCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_ExtMRSeCount 0x0278 |
| #define BA_MctrlDual_ExtMRSeCount_value 0x0278 |
| #define B16MctrlDual_ExtMRSeCount_value 0x0278 |
| #define LSb32MctrlDual_ExtMRSeCount_value 0 |
| #define LSb16MctrlDual_ExtMRSeCount_value 0 |
| #define bMctrlDual_ExtMRSeCount_value 32 |
| #define MSK32MctrlDual_ExtMRSeCount_value 0xFFFFFFFF |
| #define RA_MctrlDual_tRCDBlockCount0 0x027C |
| #define BA_MctrlDual_tRCDBlockCount0_value 0x027C |
| #define B16MctrlDual_tRCDBlockCount0_value 0x027C |
| #define LSb32MctrlDual_tRCDBlockCount0_value 0 |
| #define LSb16MctrlDual_tRCDBlockCount0_value 0 |
| #define bMctrlDual_tRCDBlockCount0_value 32 |
| #define MSK32MctrlDual_tRCDBlockCount0_value 0xFFFFFFFF |
| #define RA_MctrlDual_ACTBlockCount0 0x0280 |
| #define BA_MctrlDual_ACTBlockCount0_value 0x0280 |
| #define B16MctrlDual_ACTBlockCount0_value 0x0280 |
| #define LSb32MctrlDual_ACTBlockCount0_value 0 |
| #define LSb16MctrlDual_ACTBlockCount0_value 0 |
| #define bMctrlDual_ACTBlockCount0_value 32 |
| #define MSK32MctrlDual_ACTBlockCount0_value 0xFFFFFFFF |
| #define RA_MctrlDual_PREBlockCount0 0x0284 |
| #define BA_MctrlDual_PREBlockCount0_value 0x0284 |
| #define B16MctrlDual_PREBlockCount0_value 0x0284 |
| #define LSb32MctrlDual_PREBlockCount0_value 0 |
| #define LSb16MctrlDual_PREBlockCount0_value 0 |
| #define bMctrlDual_PREBlockCount0_value 32 |
| #define MSK32MctrlDual_PREBlockCount0_value 0xFFFFFFFF |
| #define RA_MctrlDual_RWBlockCount0 0x0288 |
| #define BA_MctrlDual_RWBlockCount0_value 0x0288 |
| #define B16MctrlDual_RWBlockCount0_value 0x0288 |
| #define LSb32MctrlDual_RWBlockCount0_value 0 |
| #define LSb16MctrlDual_RWBlockCount0_value 0 |
| #define bMctrlDual_RWBlockCount0_value 32 |
| #define MSK32MctrlDual_RWBlockCount0_value 0xFFFFFFFF |
| #define RA_MctrlDual_REFCountCh0 0x028C |
| #define BA_MctrlDual_REFCountCh0_value 0x028C |
| #define B16MctrlDual_REFCountCh0_value 0x028C |
| #define LSb32MctrlDual_REFCountCh0_value 0 |
| #define LSb16MctrlDual_REFCountCh0_value 0 |
| #define bMctrlDual_REFCountCh0_value 32 |
| #define MSK32MctrlDual_REFCountCh0_value 0xFFFFFFFF |
| #define RA_MctrlDual_tRCDBlockCount1 0x0290 |
| #define BA_MctrlDual_tRCDBlockCount1_value 0x0290 |
| #define B16MctrlDual_tRCDBlockCount1_value 0x0290 |
| #define LSb32MctrlDual_tRCDBlockCount1_value 0 |
| #define LSb16MctrlDual_tRCDBlockCount1_value 0 |
| #define bMctrlDual_tRCDBlockCount1_value 32 |
| #define MSK32MctrlDual_tRCDBlockCount1_value 0xFFFFFFFF |
| #define RA_MctrlDual_ACTBlockCount1 0x0294 |
| #define BA_MctrlDual_ACTBlockCount1_value 0x0294 |
| #define B16MctrlDual_ACTBlockCount1_value 0x0294 |
| #define LSb32MctrlDual_ACTBlockCount1_value 0 |
| #define LSb16MctrlDual_ACTBlockCount1_value 0 |
| #define bMctrlDual_ACTBlockCount1_value 32 |
| #define MSK32MctrlDual_ACTBlockCount1_value 0xFFFFFFFF |
| #define RA_MctrlDual_PREBlockCount1 0x0298 |
| #define BA_MctrlDual_PREBlockCount1_value 0x0298 |
| #define B16MctrlDual_PREBlockCount1_value 0x0298 |
| #define LSb32MctrlDual_PREBlockCount1_value 0 |
| #define LSb16MctrlDual_PREBlockCount1_value 0 |
| #define bMctrlDual_PREBlockCount1_value 32 |
| #define MSK32MctrlDual_PREBlockCount1_value 0xFFFFFFFF |
| #define RA_MctrlDual_RWBlockCount1 0x029C |
| #define BA_MctrlDual_RWBlockCount1_value 0x029C |
| #define B16MctrlDual_RWBlockCount1_value 0x029C |
| #define LSb32MctrlDual_RWBlockCount1_value 0 |
| #define LSb16MctrlDual_RWBlockCount1_value 0 |
| #define bMctrlDual_RWBlockCount1_value 32 |
| #define MSK32MctrlDual_RWBlockCount1_value 0xFFFFFFFF |
| #define RA_MctrlDual_REFCountCh1 0x02A0 |
| #define BA_MctrlDual_REFCountCh1_value 0x02A0 |
| #define B16MctrlDual_REFCountCh1_value 0x02A0 |
| #define LSb32MctrlDual_REFCountCh1_value 0 |
| #define LSb16MctrlDual_REFCountCh1_value 0 |
| #define bMctrlDual_REFCountCh1_value 32 |
| #define MSK32MctrlDual_REFCountCh1_value 0xFFFFFFFF |
| #define RA_MctrlDual_rBufBlockCount0 0x02A4 |
| #define BA_MctrlDual_rBufBlockCount0_value 0x02A4 |
| #define B16MctrlDual_rBufBlockCount0_value 0x02A4 |
| #define LSb32MctrlDual_rBufBlockCount0_value 0 |
| #define LSb16MctrlDual_rBufBlockCount0_value 0 |
| #define bMctrlDual_rBufBlockCount0_value 32 |
| #define MSK32MctrlDual_rBufBlockCount0_value 0xFFFFFFFF |
| #define RA_MctrlDual_rBufBlockCount1 0x02A8 |
| #define BA_MctrlDual_rBufBlockCount1_value 0x02A8 |
| #define B16MctrlDual_rBufBlockCount1_value 0x02A8 |
| #define LSb32MctrlDual_rBufBlockCount1_value 0 |
| #define LSb16MctrlDual_rBufBlockCount1_value 0 |
| #define bMctrlDual_rBufBlockCount1_value 32 |
| #define MSK32MctrlDual_rBufBlockCount1_value 0xFFFFFFFF |
| #define RA_MctrlDual_rBufBlockCount2 0x02AC |
| #define BA_MctrlDual_rBufBlockCount2_value 0x02AC |
| #define B16MctrlDual_rBufBlockCount2_value 0x02AC |
| #define LSb32MctrlDual_rBufBlockCount2_value 0 |
| #define LSb16MctrlDual_rBufBlockCount2_value 0 |
| #define bMctrlDual_rBufBlockCount2_value 32 |
| #define MSK32MctrlDual_rBufBlockCount2_value 0xFFFFFFFF |
| #define RA_MctrlDual_GFXCmdGnt 0x02B0 |
| #define BA_MctrlDual_GFXCmdGnt_pattern 0x02B0 |
| #define B16MctrlDual_GFXCmdGnt_pattern 0x02B0 |
| #define LSb32MctrlDual_GFXCmdGnt_pattern 0 |
| #define LSb16MctrlDual_GFXCmdGnt_pattern 0 |
| #define bMctrlDual_GFXCmdGnt_pattern 32 |
| #define MSK32MctrlDual_GFXCmdGnt_pattern 0xFFFFFFFF |
| #define RA_MctrlDual_SeCtrlCpu0WMem 0x02B4 |
| #define RA_MctrlDual_SeCtrlCpu0RMem 0x02D4 |
| #define RA_MctrlDual_SeCtrlExtMWMem 0x02F4 |
| #define RA_MctrlDual_SeCtrlExtMRMem 0x0314 |
| #define RA_MctrlDual_loopBackExpLow0 0x0334 |
| #define BA_MctrlDual_loopBackExpLow0_value 0x0334 |
| #define B16MctrlDual_loopBackExpLow0_value 0x0334 |
| #define LSb32MctrlDual_loopBackExpLow0_value 0 |
| #define LSb16MctrlDual_loopBackExpLow0_value 0 |
| #define bMctrlDual_loopBackExpLow0_value 32 |
| #define MSK32MctrlDual_loopBackExpLow0_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackExpHigh0 0x0338 |
| #define BA_MctrlDual_loopBackExpHigh0_value 0x0338 |
| #define B16MctrlDual_loopBackExpHigh0_value 0x0338 |
| #define LSb32MctrlDual_loopBackExpHigh0_value 0 |
| #define LSb16MctrlDual_loopBackExpHigh0_value 0 |
| #define bMctrlDual_loopBackExpHigh0_value 32 |
| #define MSK32MctrlDual_loopBackExpHigh0_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackRcvLow0 0x033C |
| #define BA_MctrlDual_loopBackRcvLow0_value 0x033C |
| #define B16MctrlDual_loopBackRcvLow0_value 0x033C |
| #define LSb32MctrlDual_loopBackRcvLow0_value 0 |
| #define LSb16MctrlDual_loopBackRcvLow0_value 0 |
| #define bMctrlDual_loopBackRcvLow0_value 32 |
| #define MSK32MctrlDual_loopBackRcvLow0_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackRcvHigh0 0x0340 |
| #define BA_MctrlDual_loopBackRcvHigh0_value 0x0340 |
| #define B16MctrlDual_loopBackRcvHigh0_value 0x0340 |
| #define LSb32MctrlDual_loopBackRcvHigh0_value 0 |
| #define LSb16MctrlDual_loopBackRcvHigh0_value 0 |
| #define bMctrlDual_loopBackRcvHigh0_value 32 |
| #define MSK32MctrlDual_loopBackRcvHigh0_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackDQM0 0x0344 |
| #define BA_MctrlDual_loopBackDQM0_dqm_exp 0x0344 |
| #define B16MctrlDual_loopBackDQM0_dqm_exp 0x0344 |
| #define LSb32MctrlDual_loopBackDQM0_dqm_exp 0 |
| #define LSb16MctrlDual_loopBackDQM0_dqm_exp 0 |
| #define bMctrlDual_loopBackDQM0_dqm_exp 8 |
| #define MSK32MctrlDual_loopBackDQM0_dqm_exp 0x000000FF |
| #define BA_MctrlDual_loopBackDQM0_dqm_rcv 0x0345 |
| #define B16MctrlDual_loopBackDQM0_dqm_rcv 0x0344 |
| #define LSb32MctrlDual_loopBackDQM0_dqm_rcv 8 |
| #define LSb16MctrlDual_loopBackDQM0_dqm_rcv 8 |
| #define bMctrlDual_loopBackDQM0_dqm_rcv 8 |
| #define MSK32MctrlDual_loopBackDQM0_dqm_rcv 0x0000FF00 |
| #define RA_MctrlDual_loopBackExpAC0 0x0348 |
| #define BA_MctrlDual_loopBackExpAC0_value 0x0348 |
| #define B16MctrlDual_loopBackExpAC0_value 0x0348 |
| #define LSb32MctrlDual_loopBackExpAC0_value 0 |
| #define LSb16MctrlDual_loopBackExpAC0_value 0 |
| #define bMctrlDual_loopBackExpAC0_value 23 |
| #define MSK32MctrlDual_loopBackExpAC0_value 0x007FFFFF |
| #define RA_MctrlDual_loopBackRcvAC0 0x034C |
| #define BA_MctrlDual_loopBackRcvAC0_value 0x034C |
| #define B16MctrlDual_loopBackRcvAC0_value 0x034C |
| #define LSb32MctrlDual_loopBackRcvAC0_value 0 |
| #define LSb16MctrlDual_loopBackRcvAC0_value 0 |
| #define bMctrlDual_loopBackRcvAC0_value 23 |
| #define MSK32MctrlDual_loopBackRcvAC0_value 0x007FFFFF |
| #define RA_MctrlDual_loopBackExpLow1 0x0350 |
| #define BA_MctrlDual_loopBackExpLow1_value 0x0350 |
| #define B16MctrlDual_loopBackExpLow1_value 0x0350 |
| #define LSb32MctrlDual_loopBackExpLow1_value 0 |
| #define LSb16MctrlDual_loopBackExpLow1_value 0 |
| #define bMctrlDual_loopBackExpLow1_value 32 |
| #define MSK32MctrlDual_loopBackExpLow1_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackExpHigh1 0x0354 |
| #define BA_MctrlDual_loopBackExpHigh1_value 0x0354 |
| #define B16MctrlDual_loopBackExpHigh1_value 0x0354 |
| #define LSb32MctrlDual_loopBackExpHigh1_value 0 |
| #define LSb16MctrlDual_loopBackExpHigh1_value 0 |
| #define bMctrlDual_loopBackExpHigh1_value 32 |
| #define MSK32MctrlDual_loopBackExpHigh1_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackRcvLow1 0x0358 |
| #define BA_MctrlDual_loopBackRcvLow1_value 0x0358 |
| #define B16MctrlDual_loopBackRcvLow1_value 0x0358 |
| #define LSb32MctrlDual_loopBackRcvLow1_value 0 |
| #define LSb16MctrlDual_loopBackRcvLow1_value 0 |
| #define bMctrlDual_loopBackRcvLow1_value 32 |
| #define MSK32MctrlDual_loopBackRcvLow1_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackRcvHigh1 0x035C |
| #define BA_MctrlDual_loopBackRcvHigh1_value 0x035C |
| #define B16MctrlDual_loopBackRcvHigh1_value 0x035C |
| #define LSb32MctrlDual_loopBackRcvHigh1_value 0 |
| #define LSb16MctrlDual_loopBackRcvHigh1_value 0 |
| #define bMctrlDual_loopBackRcvHigh1_value 32 |
| #define MSK32MctrlDual_loopBackRcvHigh1_value 0xFFFFFFFF |
| #define RA_MctrlDual_loopBackDQM1 0x0360 |
| #define BA_MctrlDual_loopBackDQM1_dqm_exp 0x0360 |
| #define B16MctrlDual_loopBackDQM1_dqm_exp 0x0360 |
| #define LSb32MctrlDual_loopBackDQM1_dqm_exp 0 |
| #define LSb16MctrlDual_loopBackDQM1_dqm_exp 0 |
| #define bMctrlDual_loopBackDQM1_dqm_exp 8 |
| #define MSK32MctrlDual_loopBackDQM1_dqm_exp 0x000000FF |
| #define BA_MctrlDual_loopBackDQM1_dqm_rcv 0x0361 |
| #define B16MctrlDual_loopBackDQM1_dqm_rcv 0x0360 |
| #define LSb32MctrlDual_loopBackDQM1_dqm_rcv 8 |
| #define LSb16MctrlDual_loopBackDQM1_dqm_rcv 8 |
| #define bMctrlDual_loopBackDQM1_dqm_rcv 8 |
| #define MSK32MctrlDual_loopBackDQM1_dqm_rcv 0x0000FF00 |
| #define RA_MctrlDual_loopBackExpAC1 0x0364 |
| #define BA_MctrlDual_loopBackExpAC1_value 0x0364 |
| #define B16MctrlDual_loopBackExpAC1_value 0x0364 |
| #define LSb32MctrlDual_loopBackExpAC1_value 0 |
| #define LSb16MctrlDual_loopBackExpAC1_value 0 |
| #define bMctrlDual_loopBackExpAC1_value 23 |
| #define MSK32MctrlDual_loopBackExpAC1_value 0x007FFFFF |
| #define RA_MctrlDual_loopBackRcvAC1 0x0368 |
| #define BA_MctrlDual_loopBackRcvAC1_value 0x0368 |
| #define B16MctrlDual_loopBackRcvAC1_value 0x0368 |
| #define LSb32MctrlDual_loopBackRcvAC1_value 0 |
| #define LSb16MctrlDual_loopBackRcvAC1_value 0 |
| #define bMctrlDual_loopBackRcvAC1_value 23 |
| #define MSK32MctrlDual_loopBackRcvAC1_value 0x007FFFFF |
| |
| #endif |
| |
