| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| #ifndef __RA_Gbl__H__ |
| #define __RA_Gbl__H__ |
| |
| #define RA_pll_ctrl 0x0000 |
| #define BA_pll_ctrl_PU 0x0000 |
| #define B16pll_ctrl_PU 0x0000 |
| #define LSb32pll_ctrl_PU 0 |
| #define LSb16pll_ctrl_PU 0 |
| #define bpll_ctrl_PU 1 |
| #define MSK32pll_ctrl_PU 0x00000001 |
| #define BA_pll_ctrl_RESET 0x0000 |
| #define B16pll_ctrl_RESET 0x0000 |
| #define LSb32pll_ctrl_RESET 1 |
| #define LSb16pll_ctrl_RESET 1 |
| #define bpll_ctrl_RESET 1 |
| #define MSK32pll_ctrl_RESET 0x00000002 |
| #define BA_pll_ctrl_AVDD1815_SEL 0x0000 |
| #define B16pll_ctrl_AVDD1815_SEL 0x0000 |
| #define LSb32pll_ctrl_AVDD1815_SEL 2 |
| #define LSb16pll_ctrl_AVDD1815_SEL 2 |
| #define bpll_ctrl_AVDD1815_SEL 1 |
| #define MSK32pll_ctrl_AVDD1815_SEL 0x00000004 |
| #define BA_pll_ctrl_REFDIV 0x0000 |
| #define B16pll_ctrl_REFDIV 0x0000 |
| #define LSb32pll_ctrl_REFDIV 3 |
| #define LSb16pll_ctrl_REFDIV 3 |
| #define bpll_ctrl_REFDIV 9 |
| #define MSK32pll_ctrl_REFDIV 0x00000FF8 |
| #define BA_pll_ctrl_FBDIV 0x0001 |
| #define B16pll_ctrl_FBDIV 0x0000 |
| #define LSb32pll_ctrl_FBDIV 12 |
| #define LSb16pll_ctrl_FBDIV 12 |
| #define bpll_ctrl_FBDIV 9 |
| #define MSK32pll_ctrl_FBDIV 0x001FF000 |
| #define BA_pll_ctrl_VDDM 0x0002 |
| #define B16pll_ctrl_VDDM 0x0002 |
| #define LSb32pll_ctrl_VDDM 21 |
| #define LSb16pll_ctrl_VDDM 5 |
| #define bpll_ctrl_VDDM 2 |
| #define MSK32pll_ctrl_VDDM 0x00600000 |
| #define BA_pll_ctrl_VDDL 0x0002 |
| #define B16pll_ctrl_VDDL 0x0002 |
| #define LSb32pll_ctrl_VDDL 23 |
| #define LSb16pll_ctrl_VDDL 7 |
| #define bpll_ctrl_VDDL 3 |
| #define MSK32pll_ctrl_VDDL 0x03800000 |
| #define BA_pll_ctrl_ICP 0x0003 |
| #define B16pll_ctrl_ICP 0x0002 |
| #define LSb32pll_ctrl_ICP 26 |
| #define LSb16pll_ctrl_ICP 10 |
| #define bpll_ctrl_ICP 4 |
| #define MSK32pll_ctrl_ICP 0x3C000000 |
| #define BA_pll_ctrl_PLL_BW_SEL 0x0003 |
| #define B16pll_ctrl_PLL_BW_SEL 0x0002 |
| #define LSb32pll_ctrl_PLL_BW_SEL 30 |
| #define LSb16pll_ctrl_PLL_BW_SEL 14 |
| #define bpll_ctrl_PLL_BW_SEL 1 |
| #define MSK32pll_ctrl_PLL_BW_SEL 0x40000000 |
| #define RA_pll_ctrl1 0x0004 |
| #define BA_pll_ctrl_KVCO 0x0004 |
| #define B16pll_ctrl_KVCO 0x0004 |
| #define LSb32pll_ctrl_KVCO 0 |
| #define LSb16pll_ctrl_KVCO 0 |
| #define bpll_ctrl_KVCO 4 |
| #define MSK32pll_ctrl_KVCO 0x0000000F |
| #define BA_pll_ctrl_CTUNE 0x0004 |
| #define B16pll_ctrl_CTUNE 0x0004 |
| #define LSb32pll_ctrl_CTUNE 4 |
| #define LSb16pll_ctrl_CTUNE 4 |
| #define bpll_ctrl_CTUNE 2 |
| #define MSK32pll_ctrl_CTUNE 0x00000030 |
| #define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004 |
| #define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6 |
| #define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6 |
| #define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 3 |
| #define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x000001C0 |
| #define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005 |
| #define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 9 |
| #define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 9 |
| #define bpll_ctrl_CLKOUT_SE_DIV_SEL 3 |
| #define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00000E00 |
| #define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0005 |
| #define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 12 |
| #define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 12 |
| #define bpll_ctrl_CLKOUT_SOURCE_SEL 1 |
| #define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x00001000 |
| #define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0005 |
| #define B16pll_ctrl_CLKOUT_DIFF_EN 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_DIFF_EN 13 |
| #define LSb16pll_ctrl_CLKOUT_DIFF_EN 13 |
| #define bpll_ctrl_CLKOUT_DIFF_EN 1 |
| #define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x00002000 |
| #define BA_pll_ctrl_BYPASS_EN 0x0005 |
| #define B16pll_ctrl_BYPASS_EN 0x0004 |
| #define LSb32pll_ctrl_BYPASS_EN 14 |
| #define LSb16pll_ctrl_BYPASS_EN 14 |
| #define bpll_ctrl_BYPASS_EN 1 |
| #define MSK32pll_ctrl_BYPASS_EN 0x00004000 |
| #define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0005 |
| #define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 15 |
| #define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 15 |
| #define bpll_ctrl_CLKOUT_SE_GATING_EN 1 |
| #define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x00008000 |
| #define BA_pll_ctrl_FBCLK_EXT_SEL 0x0006 |
| #define B16pll_ctrl_FBCLK_EXT_SEL 0x0006 |
| #define LSb32pll_ctrl_FBCLK_EXT_SEL 16 |
| #define LSb16pll_ctrl_FBCLK_EXT_SEL 0 |
| #define bpll_ctrl_FBCLK_EXT_SEL 1 |
| #define MSK32pll_ctrl_FBCLK_EXT_SEL 0x00010000 |
| #define BA_pll_ctrl_FBCDLY 0x0006 |
| #define B16pll_ctrl_FBCDLY 0x0006 |
| #define LSb32pll_ctrl_FBCDLY 17 |
| #define LSb16pll_ctrl_FBCDLY 1 |
| #define bpll_ctrl_FBCDLY 6 |
| #define MSK32pll_ctrl_FBCDLY 0x007E0000 |
| #define BA_pll_ctrl_FD 0x0006 |
| #define B16pll_ctrl_FD 0x0006 |
| #define LSb32pll_ctrl_FD 23 |
| #define LSb16pll_ctrl_FD 7 |
| #define bpll_ctrl_FD 3 |
| #define MSK32pll_ctrl_FD 0x03800000 |
| #define BA_pll_ctrl_INTPI 0x0007 |
| #define B16pll_ctrl_INTPI 0x0006 |
| #define LSb32pll_ctrl_INTPI 26 |
| #define LSb16pll_ctrl_INTPI 10 |
| #define bpll_ctrl_INTPI 4 |
| #define MSK32pll_ctrl_INTPI 0x3C000000 |
| #define RA_pll_ctrl2 0x0008 |
| #define BA_pll_ctrl_INTPR 0x0008 |
| #define B16pll_ctrl_INTPR 0x0008 |
| #define LSb32pll_ctrl_INTPR 0 |
| #define LSb16pll_ctrl_INTPR 0 |
| #define bpll_ctrl_INTPR 3 |
| #define MSK32pll_ctrl_INTPR 0x00000007 |
| #define BA_pll_ctrl_PI_EN 0x0008 |
| #define B16pll_ctrl_PI_EN 0x0008 |
| #define LSb32pll_ctrl_PI_EN 3 |
| #define LSb16pll_ctrl_PI_EN 3 |
| #define bpll_ctrl_PI_EN 1 |
| #define MSK32pll_ctrl_PI_EN 0x00000008 |
| #define BA_pll_ctrl_PI_LOOP_MODE 0x0008 |
| #define B16pll_ctrl_PI_LOOP_MODE 0x0008 |
| #define LSb32pll_ctrl_PI_LOOP_MODE 4 |
| #define LSb16pll_ctrl_PI_LOOP_MODE 4 |
| #define bpll_ctrl_PI_LOOP_MODE 1 |
| #define MSK32pll_ctrl_PI_LOOP_MODE 0x00000010 |
| #define BA_pll_ctrl_CLK_DET_EN 0x0008 |
| #define B16pll_ctrl_CLK_DET_EN 0x0008 |
| #define LSb32pll_ctrl_CLK_DET_EN 5 |
| #define LSb16pll_ctrl_CLK_DET_EN 5 |
| #define bpll_ctrl_CLK_DET_EN 1 |
| #define MSK32pll_ctrl_CLK_DET_EN 0x00000020 |
| #define BA_pll_ctrl_RESET_PI 0x0008 |
| #define B16pll_ctrl_RESET_PI 0x0008 |
| #define LSb32pll_ctrl_RESET_PI 6 |
| #define LSb16pll_ctrl_RESET_PI 6 |
| #define bpll_ctrl_RESET_PI 1 |
| #define MSK32pll_ctrl_RESET_PI 0x00000040 |
| #define BA_pll_ctrl_RESET_SSC 0x0008 |
| #define B16pll_ctrl_RESET_SSC 0x0008 |
| #define LSb32pll_ctrl_RESET_SSC 7 |
| #define LSb16pll_ctrl_RESET_SSC 7 |
| #define bpll_ctrl_RESET_SSC 1 |
| #define MSK32pll_ctrl_RESET_SSC 0x00000080 |
| #define BA_pll_ctrl_FREQ_OFFSET_EN 0x0009 |
| #define B16pll_ctrl_FREQ_OFFSET_EN 0x0008 |
| #define LSb32pll_ctrl_FREQ_OFFSET_EN 8 |
| #define LSb16pll_ctrl_FREQ_OFFSET_EN 8 |
| #define bpll_ctrl_FREQ_OFFSET_EN 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00000100 |
| #define BA_pll_ctrl_FREQ_OFFSET 0x0009 |
| #define B16pll_ctrl_FREQ_OFFSET 0x0008 |
| #define LSb32pll_ctrl_FREQ_OFFSET 9 |
| #define LSb16pll_ctrl_FREQ_OFFSET 9 |
| #define bpll_ctrl_FREQ_OFFSET 17 |
| #define MSK32pll_ctrl_FREQ_OFFSET 0x03FFFE00 |
| #define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000B |
| #define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000A |
| #define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 26 |
| #define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 10 |
| #define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x04000000 |
| #define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000B |
| #define B16pll_ctrl_FREQ_OFFSET_VALID 0x000A |
| #define LSb32pll_ctrl_FREQ_OFFSET_VALID 27 |
| #define LSb16pll_ctrl_FREQ_OFFSET_VALID 11 |
| #define bpll_ctrl_FREQ_OFFSET_VALID 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x08000000 |
| #define BA_pll_ctrl_SSC_CLK_EN 0x000B |
| #define B16pll_ctrl_SSC_CLK_EN 0x000A |
| #define LSb32pll_ctrl_SSC_CLK_EN 28 |
| #define LSb16pll_ctrl_SSC_CLK_EN 12 |
| #define bpll_ctrl_SSC_CLK_EN 1 |
| #define MSK32pll_ctrl_SSC_CLK_EN 0x10000000 |
| #define BA_pll_ctrl_SSC_MODE 0x000B |
| #define B16pll_ctrl_SSC_MODE 0x000A |
| #define LSb32pll_ctrl_SSC_MODE 29 |
| #define LSb16pll_ctrl_SSC_MODE 13 |
| #define bpll_ctrl_SSC_MODE 1 |
| #define MSK32pll_ctrl_SSC_MODE 0x20000000 |
| #define RA_pll_ctrl3 0x000C |
| #define BA_pll_ctrl_SSC_FREQ_DIV 0x000C |
| #define B16pll_ctrl_SSC_FREQ_DIV 0x000C |
| #define LSb32pll_ctrl_SSC_FREQ_DIV 0 |
| #define LSb16pll_ctrl_SSC_FREQ_DIV 0 |
| #define bpll_ctrl_SSC_FREQ_DIV 16 |
| #define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF |
| #define BA_pll_ctrl_SSC_RNGE 0x000E |
| #define B16pll_ctrl_SSC_RNGE 0x000E |
| #define LSb32pll_ctrl_SSC_RNGE 16 |
| #define LSb16pll_ctrl_SSC_RNGE 0 |
| #define bpll_ctrl_SSC_RNGE 11 |
| #define MSK32pll_ctrl_SSC_RNGE 0x07FF0000 |
| #define BA_pll_ctrl_TEST_ANA 0x000F |
| #define B16pll_ctrl_TEST_ANA 0x000E |
| #define LSb32pll_ctrl_TEST_ANA 27 |
| #define LSb16pll_ctrl_TEST_ANA 11 |
| #define bpll_ctrl_TEST_ANA 4 |
| #define MSK32pll_ctrl_TEST_ANA 0x78000000 |
| #define RA_pll_ctrl4 0x0010 |
| #define BA_pll_ctrl_RESERVE_IN 0x0010 |
| #define B16pll_ctrl_RESERVE_IN 0x0010 |
| #define LSb32pll_ctrl_RESERVE_IN 0 |
| #define LSb16pll_ctrl_RESERVE_IN 0 |
| #define bpll_ctrl_RESERVE_IN 8 |
| #define MSK32pll_ctrl_RESERVE_IN 0x000000FF |
| #define RA_pll_status 0x0014 |
| #define BA_pll_status_PLL_LOCK 0x0014 |
| #define B16pll_status_PLL_LOCK 0x0014 |
| #define LSb32pll_status_PLL_LOCK 0 |
| #define LSb16pll_status_PLL_LOCK 0 |
| #define bpll_status_PLL_LOCK 1 |
| #define MSK32pll_status_PLL_LOCK 0x00000001 |
| #define BA_pll_status_CLK_CFMOD 0x0014 |
| #define B16pll_status_CLK_CFMOD 0x0014 |
| #define LSb32pll_status_CLK_CFMOD 1 |
| #define LSb16pll_status_CLK_CFMOD 1 |
| #define bpll_status_CLK_CFMOD 1 |
| #define MSK32pll_status_CLK_CFMOD 0x00000002 |
| #define BA_pll_status_CLK_FMOD 0x0014 |
| #define B16pll_status_CLK_FMOD 0x0014 |
| #define LSb32pll_status_CLK_FMOD 2 |
| #define LSb16pll_status_CLK_FMOD 2 |
| #define bpll_status_CLK_FMOD 1 |
| #define MSK32pll_status_CLK_FMOD 0x00000004 |
| #define BA_pll_status_RESERVE_OUT 0x0014 |
| #define B16pll_status_RESERVE_OUT 0x0014 |
| #define LSb32pll_status_RESERVE_OUT 3 |
| #define LSb16pll_status_RESERVE_OUT 3 |
| #define bpll_status_RESERVE_OUT 8 |
| #define MSK32pll_status_RESERVE_OUT 0x000007F8 |
| #define RA_avpllCh_ctrl 0x0000 |
| #define BA_avpllCh_ctrl_POSTDIV 0x0000 |
| #define B16avpllCh_ctrl_POSTDIV 0x0000 |
| #define LSb32avpllCh_ctrl_POSTDIV 0 |
| #define LSb16avpllCh_ctrl_POSTDIV 0 |
| #define bavpllCh_ctrl_POSTDIV 13 |
| #define MSK32avpllCh_ctrl_POSTDIV 0x00001FFF |
| #define BA_avpllCh_ctrl_POSTDIV_0P5 0x0001 |
| #define B16avpllCh_ctrl_POSTDIV_0P5 0x0000 |
| #define LSb32avpllCh_ctrl_POSTDIV_0P5 13 |
| #define LSb16avpllCh_ctrl_POSTDIV_0P5 13 |
| #define bavpllCh_ctrl_POSTDIV_0P5 1 |
| #define MSK32avpllCh_ctrl_POSTDIV_0P5 0x00002000 |
| #define BA_avpllCh_ctrl_EN_DPLL 0x0001 |
| #define B16avpllCh_ctrl_EN_DPLL 0x0000 |
| #define LSb32avpllCh_ctrl_EN_DPLL 14 |
| #define LSb16avpllCh_ctrl_EN_DPLL 14 |
| #define bavpllCh_ctrl_EN_DPLL 1 |
| #define MSK32avpllCh_ctrl_EN_DPLL 0x00004000 |
| #define BA_avpllCh_ctrl_EN_LP 0x0001 |
| #define B16avpllCh_ctrl_EN_LP 0x0000 |
| #define LSb32avpllCh_ctrl_EN_LP 15 |
| #define LSb16avpllCh_ctrl_EN_LP 15 |
| #define bavpllCh_ctrl_EN_LP 2 |
| #define MSK32avpllCh_ctrl_EN_LP 0x00018000 |
| #define RA_avpllCh_ctrl1 0x0004 |
| #define BA_avpllCh_ctrl_FREQ_OFFSET 0x0004 |
| #define B16avpllCh_ctrl_FREQ_OFFSET 0x0004 |
| #define LSb32avpllCh_ctrl_FREQ_OFFSET 0 |
| #define LSb16avpllCh_ctrl_FREQ_OFFSET 0 |
| #define bavpllCh_ctrl_FREQ_OFFSET 19 |
| #define MSK32avpllCh_ctrl_FREQ_OFFSET 0x0007FFFF |
| #define BA_avpllCh_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define B16avpllCh_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define LSb32avpllCh_ctrl_FREQ_OFFSET_READY 19 |
| #define LSb16avpllCh_ctrl_FREQ_OFFSET_READY 3 |
| #define bavpllCh_ctrl_FREQ_OFFSET_READY 1 |
| #define MSK32avpllCh_ctrl_FREQ_OFFSET_READY 0x00080000 |
| #define BA_avpllCh_ctrl_PU 0x0006 |
| #define B16avpllCh_ctrl_PU 0x0006 |
| #define LSb32avpllCh_ctrl_PU 20 |
| #define LSb16avpllCh_ctrl_PU 4 |
| #define bavpllCh_ctrl_PU 1 |
| #define MSK32avpllCh_ctrl_PU 0x00100000 |
| #define BA_avpllCh_ctrl_PU_OFST_CTRL 0x0006 |
| #define B16avpllCh_ctrl_PU_OFST_CTRL 0x0006 |
| #define LSb32avpllCh_ctrl_PU_OFST_CTRL 21 |
| #define LSb16avpllCh_ctrl_PU_OFST_CTRL 5 |
| #define bavpllCh_ctrl_PU_OFST_CTRL 1 |
| #define MSK32avpllCh_ctrl_PU_OFST_CTRL 0x00200000 |
| #define RA_avpllCh_ctrl2 0x0008 |
| #define BA_avpllCh_ctrl_P_SYNC1 0x0008 |
| #define B16avpllCh_ctrl_P_SYNC1 0x0008 |
| #define LSb32avpllCh_ctrl_P_SYNC1 0 |
| #define LSb16avpllCh_ctrl_P_SYNC1 0 |
| #define bavpllCh_ctrl_P_SYNC1 20 |
| #define MSK32avpllCh_ctrl_P_SYNC1 0x000FFFFF |
| #define RA_avpllCh_ctrl3 0x000C |
| #define BA_avpllCh_ctrl_P_SYNC2 0x000C |
| #define B16avpllCh_ctrl_P_SYNC2 0x000C |
| #define LSb32avpllCh_ctrl_P_SYNC2 0 |
| #define LSb16avpllCh_ctrl_P_SYNC2 0 |
| #define bavpllCh_ctrl_P_SYNC2 20 |
| #define MSK32avpllCh_ctrl_P_SYNC2 0x000FFFFF |
| #define BA_avpllCh_ctrl_RESET 0x000E |
| #define B16avpllCh_ctrl_RESET 0x000E |
| #define LSb32avpllCh_ctrl_RESET 20 |
| #define LSb16avpllCh_ctrl_RESET 4 |
| #define bavpllCh_ctrl_RESET 1 |
| #define MSK32avpllCh_ctrl_RESET 0x00100000 |
| #define BA_avpllCh_ctrl_RESERVE_IN 0x000E |
| #define B16avpllCh_ctrl_RESERVE_IN 0x000E |
| #define LSb32avpllCh_ctrl_RESERVE_IN 21 |
| #define LSb16avpllCh_ctrl_RESERVE_IN 5 |
| #define bavpllCh_ctrl_RESERVE_IN 2 |
| #define MSK32avpllCh_ctrl_RESERVE_IN 0x00600000 |
| #define RA_avpllCh8_ctrl 0x0000 |
| #define BA_avpllCh8_ctrl_POSTDIV 0x0000 |
| #define B16avpllCh8_ctrl_POSTDIV 0x0000 |
| #define LSb32avpllCh8_ctrl_POSTDIV 0 |
| #define LSb16avpllCh8_ctrl_POSTDIV 0 |
| #define bavpllCh8_ctrl_POSTDIV 13 |
| #define MSK32avpllCh8_ctrl_POSTDIV 0x00001FFF |
| #define BA_avpllCh8_ctrl_POSTDIV_0P5 0x0001 |
| #define B16avpllCh8_ctrl_POSTDIV_0P5 0x0000 |
| #define LSb32avpllCh8_ctrl_POSTDIV_0P5 13 |
| #define LSb16avpllCh8_ctrl_POSTDIV_0P5 13 |
| #define bavpllCh8_ctrl_POSTDIV_0P5 1 |
| #define MSK32avpllCh8_ctrl_POSTDIV_0P5 0x00002000 |
| #define BA_avpllCh8_ctrl_EN_DPLL 0x0001 |
| #define B16avpllCh8_ctrl_EN_DPLL 0x0000 |
| #define LSb32avpllCh8_ctrl_EN_DPLL 14 |
| #define LSb16avpllCh8_ctrl_EN_DPLL 14 |
| #define bavpllCh8_ctrl_EN_DPLL 1 |
| #define MSK32avpllCh8_ctrl_EN_DPLL 0x00004000 |
| #define BA_avpllCh8_ctrl_EN_LP 0x0001 |
| #define B16avpllCh8_ctrl_EN_LP 0x0000 |
| #define LSb32avpllCh8_ctrl_EN_LP 15 |
| #define LSb16avpllCh8_ctrl_EN_LP 15 |
| #define bavpllCh8_ctrl_EN_LP 2 |
| #define MSK32avpllCh8_ctrl_EN_LP 0x00018000 |
| #define RA_avpllCh8_ctrl1 0x0004 |
| #define BA_avpllCh8_ctrl_FREQ_OFFSET 0x0004 |
| #define B16avpllCh8_ctrl_FREQ_OFFSET 0x0004 |
| #define LSb32avpllCh8_ctrl_FREQ_OFFSET 0 |
| #define LSb16avpllCh8_ctrl_FREQ_OFFSET 0 |
| #define bavpllCh8_ctrl_FREQ_OFFSET 19 |
| #define MSK32avpllCh8_ctrl_FREQ_OFFSET 0x0007FFFF |
| #define BA_avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define B16avpllCh8_ctrl_FREQ_OFFSET_READY 0x0006 |
| #define LSb32avpllCh8_ctrl_FREQ_OFFSET_READY 19 |
| #define LSb16avpllCh8_ctrl_FREQ_OFFSET_READY 3 |
| #define bavpllCh8_ctrl_FREQ_OFFSET_READY 1 |
| #define MSK32avpllCh8_ctrl_FREQ_OFFSET_READY 0x00080000 |
| #define BA_avpllCh8_ctrl_PU 0x0006 |
| #define B16avpllCh8_ctrl_PU 0x0006 |
| #define LSb32avpllCh8_ctrl_PU 20 |
| #define LSb16avpllCh8_ctrl_PU 4 |
| #define bavpllCh8_ctrl_PU 1 |
| #define MSK32avpllCh8_ctrl_PU 0x00100000 |
| #define BA_avpllCh8_ctrl_PU_OFST_CTRL 0x0006 |
| #define B16avpllCh8_ctrl_PU_OFST_CTRL 0x0006 |
| #define LSb32avpllCh8_ctrl_PU_OFST_CTRL 21 |
| #define LSb16avpllCh8_ctrl_PU_OFST_CTRL 5 |
| #define bavpllCh8_ctrl_PU_OFST_CTRL 1 |
| #define MSK32avpllCh8_ctrl_PU_OFST_CTRL 0x00200000 |
| #define RA_avpllCh8_ctrl2 0x0008 |
| #define BA_avpllCh8_ctrl_P_SYNC1 0x0008 |
| #define B16avpllCh8_ctrl_P_SYNC1 0x0008 |
| #define LSb32avpllCh8_ctrl_P_SYNC1 0 |
| #define LSb16avpllCh8_ctrl_P_SYNC1 0 |
| #define bavpllCh8_ctrl_P_SYNC1 20 |
| #define MSK32avpllCh8_ctrl_P_SYNC1 0x000FFFFF |
| #define RA_avpllCh8_ctrl3 0x000C |
| #define BA_avpllCh8_ctrl_P_SYNC2 0x000C |
| #define B16avpllCh8_ctrl_P_SYNC2 0x000C |
| #define LSb32avpllCh8_ctrl_P_SYNC2 0 |
| #define LSb16avpllCh8_ctrl_P_SYNC2 0 |
| #define bavpllCh8_ctrl_P_SYNC2 20 |
| #define MSK32avpllCh8_ctrl_P_SYNC2 0x000FFFFF |
| #define BA_avpllCh8_ctrl_RESET 0x000E |
| #define B16avpllCh8_ctrl_RESET 0x000E |
| #define LSb32avpllCh8_ctrl_RESET 20 |
| #define LSb16avpllCh8_ctrl_RESET 4 |
| #define bavpllCh8_ctrl_RESET 1 |
| #define MSK32avpllCh8_ctrl_RESET 0x00100000 |
| #define BA_avpllCh8_ctrl_RESERVE_IN 0x000E |
| #define B16avpllCh8_ctrl_RESERVE_IN 0x000E |
| #define LSb32avpllCh8_ctrl_RESERVE_IN 21 |
| #define LSb16avpllCh8_ctrl_RESERVE_IN 5 |
| #define bavpllCh8_ctrl_RESERVE_IN 2 |
| #define MSK32avpllCh8_ctrl_RESERVE_IN 0x00600000 |
| #define RA_avPll_ctrlPLL 0x0000 |
| #define BA_avPll_ctrlPLL_RESET 0x0000 |
| #define B16avPll_ctrlPLL_RESET 0x0000 |
| #define LSb32avPll_ctrlPLL_RESET 0 |
| #define LSb16avPll_ctrlPLL_RESET 0 |
| #define bavPll_ctrlPLL_RESET 1 |
| #define MSK32avPll_ctrlPLL_RESET 0x00000001 |
| #define BA_avPll_ctrlPLL_PU 0x0000 |
| #define B16avPll_ctrlPLL_PU 0x0000 |
| #define LSb32avPll_ctrlPLL_PU 1 |
| #define LSb16avPll_ctrlPLL_PU 1 |
| #define bavPll_ctrlPLL_PU 1 |
| #define MSK32avPll_ctrlPLL_PU 0x00000002 |
| #define BA_avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000 |
| #define B16avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_PLL_VDDRA_SEL 2 |
| #define LSb16avPll_ctrlPLL_PLL_VDDRA_SEL 2 |
| #define bavPll_ctrlPLL_PLL_VDDRA_SEL 3 |
| #define MSK32avPll_ctrlPLL_PLL_VDDRA_SEL 0x0000001C |
| #define BA_avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000 |
| #define B16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x0000 |
| #define LSb32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5 |
| #define LSb16avPll_ctrlPLL_REG_RING_EXTRA_I_EN 5 |
| #define bavPll_ctrlPLL_REG_RING_EXTRA_I_EN 1 |
| #define MSK32avPll_ctrlPLL_REG_RING_EXTRA_I_EN 0x00000020 |
| #define BA_avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000 |
| #define B16avPll_ctrlPLL_VCO_REF1P45_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_VCO_REF1P45_SEL 6 |
| #define LSb16avPll_ctrlPLL_VCO_REF1P45_SEL 6 |
| #define bavPll_ctrlPLL_VCO_REF1P45_SEL 2 |
| #define MSK32avPll_ctrlPLL_VCO_REF1P45_SEL 0x000000C0 |
| #define BA_avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0001 |
| #define B16avPll_ctrlPLL_VDDA23_PUMP_SEL 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDA23_PUMP_SEL 8 |
| #define LSb16avPll_ctrlPLL_VDDA23_PUMP_SEL 8 |
| #define bavPll_ctrlPLL_VDDA23_PUMP_SEL 2 |
| #define MSK32avPll_ctrlPLL_VDDA23_PUMP_SEL 0x00000300 |
| #define BA_avPll_ctrlPLL_VDDBUF_ADJ 0x0001 |
| #define B16avPll_ctrlPLL_VDDBUF_ADJ 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDBUF_ADJ 10 |
| #define LSb16avPll_ctrlPLL_VDDBUF_ADJ 10 |
| #define bavPll_ctrlPLL_VDDBUF_ADJ 3 |
| #define MSK32avPll_ctrlPLL_VDDBUF_ADJ 0x00001C00 |
| #define BA_avPll_ctrlPLL_VDDL 0x0001 |
| #define B16avPll_ctrlPLL_VDDL 0x0000 |
| #define LSb32avPll_ctrlPLL_VDDL 13 |
| #define LSb16avPll_ctrlPLL_VDDL 13 |
| #define bavPll_ctrlPLL_VDDL 4 |
| #define MSK32avPll_ctrlPLL_VDDL 0x0001E000 |
| #define BA_avPll_ctrlPLL_FBDIV 0x0002 |
| #define B16avPll_ctrlPLL_FBDIV 0x0002 |
| #define LSb32avPll_ctrlPLL_FBDIV 17 |
| #define LSb16avPll_ctrlPLL_FBDIV 1 |
| #define bavPll_ctrlPLL_FBDIV 9 |
| #define MSK32avPll_ctrlPLL_FBDIV 0x03FE0000 |
| #define BA_avPll_ctrlPLL_ICP 0x0003 |
| #define B16avPll_ctrlPLL_ICP 0x0002 |
| #define LSb32avPll_ctrlPLL_ICP 26 |
| #define LSb16avPll_ctrlPLL_ICP 10 |
| #define bavPll_ctrlPLL_ICP 4 |
| #define MSK32avPll_ctrlPLL_ICP 0x3C000000 |
| #define BA_avPll_ctrlPLL_PLL_LPFC2_LESS 0x0003 |
| #define B16avPll_ctrlPLL_PLL_LPFC2_LESS 0x0002 |
| #define LSb32avPll_ctrlPLL_PLL_LPFC2_LESS 30 |
| #define LSb16avPll_ctrlPLL_PLL_LPFC2_LESS 14 |
| #define bavPll_ctrlPLL_PLL_LPFC2_LESS 1 |
| #define MSK32avPll_ctrlPLL_PLL_LPFC2_LESS 0x40000000 |
| #define RA_avPll_ctrlPLL1 0x0004 |
| #define BA_avPll_ctrlPLL_REFDIV 0x0004 |
| #define B16avPll_ctrlPLL_REFDIV 0x0004 |
| #define LSb32avPll_ctrlPLL_REFDIV 0 |
| #define LSb16avPll_ctrlPLL_REFDIV 0 |
| #define bavPll_ctrlPLL_REFDIV 7 |
| #define MSK32avPll_ctrlPLL_REFDIV 0x0000007F |
| #define BA_avPll_ctrlPLL_RESERVE_PLL_IN 0x0004 |
| #define B16avPll_ctrlPLL_RESERVE_PLL_IN 0x0004 |
| #define LSb32avPll_ctrlPLL_RESERVE_PLL_IN 7 |
| #define LSb16avPll_ctrlPLL_RESERVE_PLL_IN 7 |
| #define bavPll_ctrlPLL_RESERVE_PLL_IN 6 |
| #define MSK32avPll_ctrlPLL_RESERVE_PLL_IN 0x00001F80 |
| #define BA_avPll_ctrlPLL_EXT_SPEED 0x0005 |
| #define B16avPll_ctrlPLL_EXT_SPEED 0x0004 |
| #define LSb32avPll_ctrlPLL_EXT_SPEED 13 |
| #define LSb16avPll_ctrlPLL_EXT_SPEED 13 |
| #define bavPll_ctrlPLL_EXT_SPEED 4 |
| #define MSK32avPll_ctrlPLL_EXT_SPEED 0x0001E000 |
| #define BA_avPll_ctrlPLL_SPEED_FBRES 0x0006 |
| #define B16avPll_ctrlPLL_SPEED_FBRES 0x0006 |
| #define LSb32avPll_ctrlPLL_SPEED_FBRES 17 |
| #define LSb16avPll_ctrlPLL_SPEED_FBRES 1 |
| #define bavPll_ctrlPLL_SPEED_FBRES 4 |
| #define MSK32avPll_ctrlPLL_SPEED_FBRES 0x001E0000 |
| #define BA_avPll_ctrlPLL_UPDATE_SEL 0x0006 |
| #define B16avPll_ctrlPLL_UPDATE_SEL 0x0006 |
| #define LSb32avPll_ctrlPLL_UPDATE_SEL 21 |
| #define LSb16avPll_ctrlPLL_UPDATE_SEL 5 |
| #define bavPll_ctrlPLL_UPDATE_SEL 1 |
| #define MSK32avPll_ctrlPLL_UPDATE_SEL 0x00200000 |
| #define RA_avPll_ctrlCAL 0x0008 |
| #define BA_avPll_ctrlCAL_CAL_FBDIV 0x0008 |
| #define B16avPll_ctrlCAL_CAL_FBDIV 0x0008 |
| #define LSb32avPll_ctrlCAL_CAL_FBDIV 0 |
| #define LSb16avPll_ctrlCAL_CAL_FBDIV 0 |
| #define bavPll_ctrlCAL_CAL_FBDIV 9 |
| #define MSK32avPll_ctrlCAL_CAL_FBDIV 0x000001FF |
| #define BA_avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SLLP_DAC_EN 9 |
| #define LSb16avPll_ctrlCAL_EXT_SLLP_DAC_EN 9 |
| #define bavPll_ctrlCAL_EXT_SLLP_DAC_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SLLP_DAC_EN 0x00000200 |
| #define BA_avPll_ctrlCAL_EXT_SPEED_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SPEED_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SPEED_EN 10 |
| #define LSb16avPll_ctrlCAL_EXT_SPEED_EN 10 |
| #define bavPll_ctrlCAL_EXT_SPEED_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SPEED_EN 0x00000400 |
| #define BA_avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0009 |
| #define B16avPll_ctrlCAL_EXT_SP_FBRES_EN 0x0008 |
| #define LSb32avPll_ctrlCAL_EXT_SP_FBRES_EN 11 |
| #define LSb16avPll_ctrlCAL_EXT_SP_FBRES_EN 11 |
| #define bavPll_ctrlCAL_EXT_SP_FBRES_EN 1 |
| #define MSK32avPll_ctrlCAL_EXT_SP_FBRES_EN 0x00000800 |
| #define BA_avPll_ctrlCAL_PLL_CALCLK_DIV 0x0009 |
| #define B16avPll_ctrlCAL_PLL_CALCLK_DIV 0x0008 |
| #define LSb32avPll_ctrlCAL_PLL_CALCLK_DIV 12 |
| #define LSb16avPll_ctrlCAL_PLL_CALCLK_DIV 12 |
| #define bavPll_ctrlCAL_PLL_CALCLK_DIV 5 |
| #define MSK32avPll_ctrlCAL_PLL_CALCLK_DIV 0x0001F000 |
| #define BA_avPll_ctrlCAL_PLL_CAL_START 0x000A |
| #define B16avPll_ctrlCAL_PLL_CAL_START 0x000A |
| #define LSb32avPll_ctrlCAL_PLL_CAL_START 17 |
| #define LSb16avPll_ctrlCAL_PLL_CAL_START 1 |
| #define bavPll_ctrlCAL_PLL_CAL_START 1 |
| #define MSK32avPll_ctrlCAL_PLL_CAL_START 0x00020000 |
| #define BA_avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A |
| #define B16avPll_ctrlCAL_REG_SETTLE_LIMIT 0x000A |
| #define LSb32avPll_ctrlCAL_REG_SETTLE_LIMIT 18 |
| #define LSb16avPll_ctrlCAL_REG_SETTLE_LIMIT 2 |
| #define bavPll_ctrlCAL_REG_SETTLE_LIMIT 4 |
| #define MSK32avPll_ctrlCAL_REG_SETTLE_LIMIT 0x003C0000 |
| #define BA_avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A |
| #define B16avPll_ctrlCAL_SEL_VTHVCOCONT 0x000A |
| #define LSb32avPll_ctrlCAL_SEL_VTHVCOCONT 22 |
| #define LSb16avPll_ctrlCAL_SEL_VTHVCOCONT 6 |
| #define bavPll_ctrlCAL_SEL_VTHVCOCONT 1 |
| #define MSK32avPll_ctrlCAL_SEL_VTHVCOCONT 0x00400000 |
| #define BA_avPll_ctrlCAL_SPEED_THRESH 0x000A |
| #define B16avPll_ctrlCAL_SPEED_THRESH 0x000A |
| #define LSb32avPll_ctrlCAL_SPEED_THRESH 23 |
| #define LSb16avPll_ctrlCAL_SPEED_THRESH 7 |
| #define bavPll_ctrlCAL_SPEED_THRESH 6 |
| #define MSK32avPll_ctrlCAL_SPEED_THRESH 0x1F800000 |
| #define BA_avPll_ctrlCAL_VCON_SEL 0x000B |
| #define B16avPll_ctrlCAL_VCON_SEL 0x000A |
| #define LSb32avPll_ctrlCAL_VCON_SEL 29 |
| #define LSb16avPll_ctrlCAL_VCON_SEL 13 |
| #define bavPll_ctrlCAL_VCON_SEL 2 |
| #define MSK32avPll_ctrlCAL_VCON_SEL 0x60000000 |
| #define RA_avPll_ctrlCAL1 0x000C |
| #define BA_avPll_ctrlCAL_EXT_SLLP_DAC 0x000C |
| #define B16avPll_ctrlCAL_EXT_SLLP_DAC 0x000C |
| #define LSb32avPll_ctrlCAL_EXT_SLLP_DAC 0 |
| #define LSb16avPll_ctrlCAL_EXT_SLLP_DAC 0 |
| #define bavPll_ctrlCAL_EXT_SLLP_DAC 7 |
| #define MSK32avPll_ctrlCAL_EXT_SLLP_DAC 0x0000007F |
| #define BA_avPll_ctrlCAL_VTH_VCO_CAL 0x000C |
| #define B16avPll_ctrlCAL_VTH_VCO_CAL 0x000C |
| #define LSb32avPll_ctrlCAL_VTH_VCO_CAL 7 |
| #define LSb16avPll_ctrlCAL_VTH_VCO_CAL 7 |
| #define bavPll_ctrlCAL_VTH_VCO_CAL 2 |
| #define MSK32avPll_ctrlCAL_VTH_VCO_CAL 0x00000180 |
| #define BA_avPll_ctrlCAL_VTH_VCO_PTAT 0x000D |
| #define B16avPll_ctrlCAL_VTH_VCO_PTAT 0x000C |
| #define LSb32avPll_ctrlCAL_VTH_VCO_PTAT 9 |
| #define LSb16avPll_ctrlCAL_VTH_VCO_PTAT 9 |
| #define bavPll_ctrlCAL_VTH_VCO_PTAT 2 |
| #define MSK32avPll_ctrlCAL_VTH_VCO_PTAT 0x00000600 |
| #define RA_avPll_ctrlSlowLoop 0x0010 |
| #define BA_avPll_ctrlSlowLoop_PW_SLLP 0x0010 |
| #define B16avPll_ctrlSlowLoop_PW_SLLP 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_PW_SLLP 0 |
| #define LSb16avPll_ctrlSlowLoop_PW_SLLP 0 |
| #define bavPll_ctrlSlowLoop_PW_SLLP 3 |
| #define MSK32avPll_ctrlSlowLoop_PW_SLLP 0x00000007 |
| #define BA_avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 3 |
| #define bavPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 1 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_CLK_DIV5EN 0x00000008 |
| #define BA_avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_EN_DIS 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_EN_DIS 4 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_EN_DIS 4 |
| #define bavPll_ctrlSlowLoop_SLLP_EN_DIS 1 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_EN_DIS 0x00000010 |
| #define BA_avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010 |
| #define B16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x0010 |
| #define LSb32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5 |
| #define LSb16avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 5 |
| #define bavPll_ctrlSlowLoop_SLLP_PSF_LEVEL 3 |
| #define MSK32avPll_ctrlSlowLoop_SLLP_PSF_LEVEL 0x000000E0 |
| #define RA_avPll_ctrlINTP 0x0014 |
| #define BA_avPll_ctrlINTP_CLK_DET_EN 0x0014 |
| #define B16avPll_ctrlINTP_CLK_DET_EN 0x0014 |
| #define LSb32avPll_ctrlINTP_CLK_DET_EN 0 |
| #define LSb16avPll_ctrlINTP_CLK_DET_EN 0 |
| #define bavPll_ctrlINTP_CLK_DET_EN 1 |
| #define MSK32avPll_ctrlINTP_CLK_DET_EN 0x00000001 |
| #define BA_avPll_ctrlINTP_DPHER_DLY_SEL 0x0014 |
| #define B16avPll_ctrlINTP_DPHER_DLY_SEL 0x0014 |
| #define LSb32avPll_ctrlINTP_DPHER_DLY_SEL 1 |
| #define LSb16avPll_ctrlINTP_DPHER_DLY_SEL 1 |
| #define bavPll_ctrlINTP_DPHER_DLY_SEL 2 |
| #define MSK32avPll_ctrlINTP_DPHER_DLY_SEL 0x00000006 |
| #define BA_avPll_ctrlINTP_INTPI 0x0014 |
| #define B16avPll_ctrlINTP_INTPI 0x0014 |
| #define LSb32avPll_ctrlINTP_INTPI 3 |
| #define LSb16avPll_ctrlINTP_INTPI 3 |
| #define bavPll_ctrlINTP_INTPI 4 |
| #define MSK32avPll_ctrlINTP_INTPI 0x00000078 |
| #define BA_avPll_ctrlINTP_INTPR 0x0014 |
| #define B16avPll_ctrlINTP_INTPR 0x0014 |
| #define LSb32avPll_ctrlINTP_INTPR 7 |
| #define LSb16avPll_ctrlINTP_INTPR 7 |
| #define bavPll_ctrlINTP_INTPR 3 |
| #define MSK32avPll_ctrlINTP_INTPR 0x00000380 |
| #define RA_avPll_ctrlC8AddOn 0x0018 |
| #define BA_avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018 |
| #define B16avPll_ctrlC8AddOn_MASTER_SLAVEB 0x0018 |
| #define LSb32avPll_ctrlC8AddOn_MASTER_SLAVEB 0 |
| #define LSb16avPll_ctrlC8AddOn_MASTER_SLAVEB 0 |
| #define bavPll_ctrlC8AddOn_MASTER_SLAVEB 1 |
| #define MSK32avPll_ctrlC8AddOn_MASTER_SLAVEB 0x00000001 |
| #define BA_avPll_ctrlC8AddOn_MODE 0x0018 |
| #define B16avPll_ctrlC8AddOn_MODE 0x0018 |
| #define LSb32avPll_ctrlC8AddOn_MODE 1 |
| #define LSb16avPll_ctrlC8AddOn_MODE 1 |
| #define bavPll_ctrlC8AddOn_MODE 2 |
| #define MSK32avPll_ctrlC8AddOn_MODE 0x00000006 |
| #define RA_avPll_C1 0x001C |
| #define RA_avPll_C2 0x002C |
| #define RA_avPll_C3 0x003C |
| #define RA_avPll_C4 0x004C |
| #define RA_avPll_C5 0x005C |
| #define RA_avPll_C6 0x006C |
| #define RA_avPll_C7 0x007C |
| #define RA_avPll_C8 0x008C |
| #define RA_avPll_ctrlTest 0x009C |
| #define BA_avPll_ctrlTest_CLKOUT_TST_EN 0x009C |
| #define B16avPll_ctrlTest_CLKOUT_TST_EN 0x009C |
| #define LSb32avPll_ctrlTest_CLKOUT_TST_EN 0 |
| #define LSb16avPll_ctrlTest_CLKOUT_TST_EN 0 |
| #define bavPll_ctrlTest_CLKOUT_TST_EN 1 |
| #define MSK32avPll_ctrlTest_CLKOUT_TST_EN 0x00000001 |
| #define BA_avPll_ctrlTest_TEST_MON 0x009C |
| #define B16avPll_ctrlTest_TEST_MON 0x009C |
| #define LSb32avPll_ctrlTest_TEST_MON 1 |
| #define LSb16avPll_ctrlTest_TEST_MON 1 |
| #define bavPll_ctrlTest_TEST_MON 6 |
| #define MSK32avPll_ctrlTest_TEST_MON 0x0000007E |
| #define RA_avPll_status 0x00A0 |
| #define BA_avPll_status_PLL_LOCK 0x00A0 |
| #define B16avPll_status_PLL_LOCK 0x00A0 |
| #define LSb32avPll_status_PLL_LOCK 0 |
| #define LSb16avPll_status_PLL_LOCK 0 |
| #define bavPll_status_PLL_LOCK 1 |
| #define MSK32avPll_status_PLL_LOCK 0x00000001 |
| #define BA_avPll_status_RESERVE_PLL_OUT 0x00A0 |
| #define B16avPll_status_RESERVE_PLL_OUT 0x00A0 |
| #define LSb32avPll_status_RESERVE_PLL_OUT 1 |
| #define LSb16avPll_status_RESERVE_PLL_OUT 1 |
| #define bavPll_status_RESERVE_PLL_OUT 6 |
| #define MSK32avPll_status_RESERVE_PLL_OUT 0x0000007E |
| #define BA_avPll_status_FBDIV_RD 0x00A0 |
| #define B16avPll_status_FBDIV_RD 0x00A0 |
| #define LSb32avPll_status_FBDIV_RD 7 |
| #define LSb16avPll_status_FBDIV_RD 7 |
| #define bavPll_status_FBDIV_RD 9 |
| #define MSK32avPll_status_FBDIV_RD 0x0000FF80 |
| #define BA_avPll_status_PLL_CAL_DONE 0x00A2 |
| #define B16avPll_status_PLL_CAL_DONE 0x00A2 |
| #define LSb32avPll_status_PLL_CAL_DONE 16 |
| #define LSb16avPll_status_PLL_CAL_DONE 0 |
| #define bavPll_status_PLL_CAL_DONE 1 |
| #define MSK32avPll_status_PLL_CAL_DONE 0x00010000 |
| #define BA_avPll_status_SPEED_CNT 0x00A2 |
| #define B16avPll_status_SPEED_CNT 0x00A2 |
| #define LSb32avPll_status_SPEED_CNT 17 |
| #define LSb16avPll_status_SPEED_CNT 1 |
| #define bavPll_status_SPEED_CNT 6 |
| #define MSK32avPll_status_SPEED_CNT 0x007E0000 |
| #define BA_avPll_status_SPEED_RD 0x00A2 |
| #define B16avPll_status_SPEED_RD 0x00A2 |
| #define LSb32avPll_status_SPEED_RD 23 |
| #define LSb16avPll_status_SPEED_RD 7 |
| #define bavPll_status_SPEED_RD 4 |
| #define MSK32avPll_status_SPEED_RD 0x07800000 |
| #define RA_avPll_status1 0x00A4 |
| #define BA_avPll_status_SLLP_DAC_RD 0x00A4 |
| #define B16avPll_status_SLLP_DAC_RD 0x00A4 |
| #define LSb32avPll_status_SLLP_DAC_RD 0 |
| #define LSb16avPll_status_SLLP_DAC_RD 0 |
| #define bavPll_status_SLLP_DAC_RD 7 |
| #define MSK32avPll_status_SLLP_DAC_RD 0x0000007F |
| #define RA_pwrOff_ctrl 0x0000 |
| #define BA_pwrOff_ctrl_iso_eN 0x0000 |
| #define B16pwrOff_ctrl_iso_eN 0x0000 |
| #define LSb32pwrOff_ctrl_iso_eN 0 |
| #define LSb16pwrOff_ctrl_iso_eN 0 |
| #define bpwrOff_ctrl_iso_eN 1 |
| #define MSK32pwrOff_ctrl_iso_eN 0x00000001 |
| #define pwrOff_ctrl_iso_eN_enable 0x0 |
| #define pwrOff_ctrl_iso_eN_disable 0x1 |
| #define BA_pwrOff_ctrl_pwrSwitchCtrl 0x0000 |
| #define B16pwrOff_ctrl_pwrSwitchCtrl 0x0000 |
| #define LSb32pwrOff_ctrl_pwrSwitchCtrl 1 |
| #define LSb16pwrOff_ctrl_pwrSwitchCtrl 1 |
| #define bpwrOff_ctrl_pwrSwitchCtrl 2 |
| #define MSK32pwrOff_ctrl_pwrSwitchCtrl 0x00000006 |
| #define pwrOff_ctrl_pwrSwitchCtrl_PWROFF 0x0 |
| #define pwrOff_ctrl_pwrSwitchCtrl_PWRON 0x3 |
| #define BA_pwrOff_ctrl_pwrDomainRstN 0x0000 |
| #define B16pwrOff_ctrl_pwrDomainRstN 0x0000 |
| #define LSb32pwrOff_ctrl_pwrDomainRstN 3 |
| #define LSb16pwrOff_ctrl_pwrDomainRstN 3 |
| #define bpwrOff_ctrl_pwrDomainRstN 1 |
| #define MSK32pwrOff_ctrl_pwrDomainRstN 0x00000008 |
| #define pwrOff_ctrl_pwrDomainRstN_enable 0x0 |
| #define pwrOff_ctrl_pwrDomainRstN_disable 0x1 |
| #define RA_pwrOff_status 0x0004 |
| #define BA_pwrOff_status_pwrStatus 0x0004 |
| #define B16pwrOff_status_pwrStatus 0x0004 |
| #define LSb32pwrOff_status_pwrStatus 0 |
| #define LSb16pwrOff_status_pwrStatus 0 |
| #define bpwrOff_status_pwrStatus 2 |
| #define MSK32pwrOff_status_pwrStatus 0x00000003 |
| #define RA_pwrOn_ctrl 0x0000 |
| #define BA_pwrOn_ctrl_iso_eN 0x0000 |
| #define B16pwrOn_ctrl_iso_eN 0x0000 |
| #define LSb32pwrOn_ctrl_iso_eN 0 |
| #define LSb16pwrOn_ctrl_iso_eN 0 |
| #define bpwrOn_ctrl_iso_eN 1 |
| #define MSK32pwrOn_ctrl_iso_eN 0x00000001 |
| #define pwrOn_ctrl_iso_eN_enable 0x0 |
| #define pwrOn_ctrl_iso_eN_disable 0x1 |
| #define BA_pwrOn_ctrl_pwrSwitchCtrl 0x0000 |
| #define B16pwrOn_ctrl_pwrSwitchCtrl 0x0000 |
| #define LSb32pwrOn_ctrl_pwrSwitchCtrl 1 |
| #define LSb16pwrOn_ctrl_pwrSwitchCtrl 1 |
| #define bpwrOn_ctrl_pwrSwitchCtrl 2 |
| #define MSK32pwrOn_ctrl_pwrSwitchCtrl 0x00000006 |
| #define BA_pwrOn_ctrl_pwrDomainRstN 0x0000 |
| #define B16pwrOn_ctrl_pwrDomainRstN 0x0000 |
| #define LSb32pwrOn_ctrl_pwrDomainRstN 3 |
| #define LSb16pwrOn_ctrl_pwrDomainRstN 3 |
| #define bpwrOn_ctrl_pwrDomainRstN 1 |
| #define MSK32pwrOn_ctrl_pwrDomainRstN 0x00000008 |
| #define RA_pwrOn_status 0x0004 |
| #define BA_pwrOn_status_pwrStatus 0x0004 |
| #define B16pwrOn_status_pwrStatus 0x0004 |
| #define LSb32pwrOn_status_pwrStatus 0 |
| #define LSb16pwrOn_status_pwrStatus 0 |
| #define bpwrOn_status_pwrStatus 2 |
| #define MSK32pwrOn_status_pwrStatus 0x00000003 |
| #define RA_clkD1_ctrl 0x0000 |
| #define BA_clkD1_ctrl_ClkEn 0x0000 |
| #define B16clkD1_ctrl_ClkEn 0x0000 |
| #define LSb32clkD1_ctrl_ClkEn 0 |
| #define LSb16clkD1_ctrl_ClkEn 0 |
| #define bclkD1_ctrl_ClkEn 1 |
| #define MSK32clkD1_ctrl_ClkEn 0x00000001 |
| #define clkD1_ctrl_ClkEn_enable 0x1 |
| #define clkD1_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD1_ctrl_ClkPllSel 0x0000 |
| #define B16clkD1_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD1_ctrl_ClkPllSel 1 |
| #define LSb16clkD1_ctrl_ClkPllSel 1 |
| #define bclkD1_ctrl_ClkPllSel 3 |
| #define MSK32clkD1_ctrl_ClkPllSel 0x0000000E |
| #define clkD1_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD1_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD1_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD1_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD1_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD1_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD1_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD1_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD1_ctrl_ClkPllSwitch 4 |
| #define bclkD1_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD1_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD1_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD1_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD1_ctrl_ClkSwitch 0x0000 |
| #define B16clkD1_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD1_ctrl_ClkSwitch 5 |
| #define LSb16clkD1_ctrl_ClkSwitch 5 |
| #define bclkD1_ctrl_ClkSwitch 1 |
| #define MSK32clkD1_ctrl_ClkSwitch 0x00000020 |
| #define clkD1_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD1_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD1_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD1_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD1_ctrl_ClkD3Switch 6 |
| #define LSb16clkD1_ctrl_ClkD3Switch 6 |
| #define bclkD1_ctrl_ClkD3Switch 1 |
| #define MSK32clkD1_ctrl_ClkD3Switch 0x00000040 |
| #define clkD1_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD1_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD1_ctrl_ClkSel 0x0000 |
| #define B16clkD1_ctrl_ClkSel 0x0000 |
| #define LSb32clkD1_ctrl_ClkSel 7 |
| #define LSb16clkD1_ctrl_ClkSel 7 |
| #define bclkD1_ctrl_ClkSel 3 |
| #define MSK32clkD1_ctrl_ClkSel 0x00000380 |
| #define clkD1_ctrl_ClkSel_d2 0x1 |
| #define clkD1_ctrl_ClkSel_d4 0x2 |
| #define clkD1_ctrl_ClkSel_d6 0x3 |
| #define clkD1_ctrl_ClkSel_d8 0x4 |
| #define clkD1_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD2_ctrl 0x0000 |
| #define BA_clkD2_ctrl_ClkEn 0x0000 |
| #define B16clkD2_ctrl_ClkEn 0x0000 |
| #define LSb32clkD2_ctrl_ClkEn 0 |
| #define LSb16clkD2_ctrl_ClkEn 0 |
| #define bclkD2_ctrl_ClkEn 1 |
| #define MSK32clkD2_ctrl_ClkEn 0x00000001 |
| #define clkD2_ctrl_ClkEn_enable 0x1 |
| #define clkD2_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD2_ctrl_ClkPllSel 0x0000 |
| #define B16clkD2_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD2_ctrl_ClkPllSel 1 |
| #define LSb16clkD2_ctrl_ClkPllSel 1 |
| #define bclkD2_ctrl_ClkPllSel 3 |
| #define MSK32clkD2_ctrl_ClkPllSel 0x0000000E |
| #define clkD2_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD2_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD2_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD2_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD2_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD2_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD2_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD2_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD2_ctrl_ClkPllSwitch 4 |
| #define bclkD2_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD2_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD2_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD2_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD2_ctrl_ClkSwitch 0x0000 |
| #define B16clkD2_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD2_ctrl_ClkSwitch 5 |
| #define LSb16clkD2_ctrl_ClkSwitch 5 |
| #define bclkD2_ctrl_ClkSwitch 1 |
| #define MSK32clkD2_ctrl_ClkSwitch 0x00000020 |
| #define clkD2_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD2_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD2_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD2_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD2_ctrl_ClkD3Switch 6 |
| #define LSb16clkD2_ctrl_ClkD3Switch 6 |
| #define bclkD2_ctrl_ClkD3Switch 1 |
| #define MSK32clkD2_ctrl_ClkD3Switch 0x00000040 |
| #define clkD2_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD2_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD2_ctrl_ClkSel 0x0000 |
| #define B16clkD2_ctrl_ClkSel 0x0000 |
| #define LSb32clkD2_ctrl_ClkSel 7 |
| #define LSb16clkD2_ctrl_ClkSel 7 |
| #define bclkD2_ctrl_ClkSel 3 |
| #define MSK32clkD2_ctrl_ClkSel 0x00000380 |
| #define clkD2_ctrl_ClkSel_d2 0x1 |
| #define clkD2_ctrl_ClkSel_d4 0x2 |
| #define clkD2_ctrl_ClkSel_d6 0x3 |
| #define clkD2_ctrl_ClkSel_d8 0x4 |
| #define clkD2_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD4_ctrl 0x0000 |
| #define BA_clkD4_ctrl_ClkEn 0x0000 |
| #define B16clkD4_ctrl_ClkEn 0x0000 |
| #define LSb32clkD4_ctrl_ClkEn 0 |
| #define LSb16clkD4_ctrl_ClkEn 0 |
| #define bclkD4_ctrl_ClkEn 1 |
| #define MSK32clkD4_ctrl_ClkEn 0x00000001 |
| #define clkD4_ctrl_ClkEn_enable 0x1 |
| #define clkD4_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD4_ctrl_ClkPllSel 0x0000 |
| #define B16clkD4_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD4_ctrl_ClkPllSel 1 |
| #define LSb16clkD4_ctrl_ClkPllSel 1 |
| #define bclkD4_ctrl_ClkPllSel 3 |
| #define MSK32clkD4_ctrl_ClkPllSel 0x0000000E |
| #define clkD4_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD4_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD4_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD4_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD4_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD4_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD4_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD4_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD4_ctrl_ClkPllSwitch 4 |
| #define bclkD4_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD4_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD4_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD4_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD4_ctrl_ClkSwitch 0x0000 |
| #define B16clkD4_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD4_ctrl_ClkSwitch 5 |
| #define LSb16clkD4_ctrl_ClkSwitch 5 |
| #define bclkD4_ctrl_ClkSwitch 1 |
| #define MSK32clkD4_ctrl_ClkSwitch 0x00000020 |
| #define clkD4_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD4_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD4_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD4_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD4_ctrl_ClkD3Switch 6 |
| #define LSb16clkD4_ctrl_ClkD3Switch 6 |
| #define bclkD4_ctrl_ClkD3Switch 1 |
| #define MSK32clkD4_ctrl_ClkD3Switch 0x00000040 |
| #define clkD4_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD4_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD4_ctrl_ClkSel 0x0000 |
| #define B16clkD4_ctrl_ClkSel 0x0000 |
| #define LSb32clkD4_ctrl_ClkSel 7 |
| #define LSb16clkD4_ctrl_ClkSel 7 |
| #define bclkD4_ctrl_ClkSel 3 |
| #define MSK32clkD4_ctrl_ClkSel 0x00000380 |
| #define clkD4_ctrl_ClkSel_d2 0x1 |
| #define clkD4_ctrl_ClkSel_d4 0x2 |
| #define clkD4_ctrl_ClkSel_d6 0x3 |
| #define clkD4_ctrl_ClkSel_d8 0x4 |
| #define clkD4_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD6_ctrl 0x0000 |
| #define BA_clkD6_ctrl_ClkEn 0x0000 |
| #define B16clkD6_ctrl_ClkEn 0x0000 |
| #define LSb32clkD6_ctrl_ClkEn 0 |
| #define LSb16clkD6_ctrl_ClkEn 0 |
| #define bclkD6_ctrl_ClkEn 1 |
| #define MSK32clkD6_ctrl_ClkEn 0x00000001 |
| #define clkD6_ctrl_ClkEn_enable 0x1 |
| #define clkD6_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD6_ctrl_ClkPllSel 0x0000 |
| #define B16clkD6_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD6_ctrl_ClkPllSel 1 |
| #define LSb16clkD6_ctrl_ClkPllSel 1 |
| #define bclkD6_ctrl_ClkPllSel 3 |
| #define MSK32clkD6_ctrl_ClkPllSel 0x0000000E |
| #define clkD6_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD6_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD6_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD6_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD6_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD6_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD6_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD6_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD6_ctrl_ClkPllSwitch 4 |
| #define bclkD6_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD6_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD6_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD6_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD6_ctrl_ClkSwitch 0x0000 |
| #define B16clkD6_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD6_ctrl_ClkSwitch 5 |
| #define LSb16clkD6_ctrl_ClkSwitch 5 |
| #define bclkD6_ctrl_ClkSwitch 1 |
| #define MSK32clkD6_ctrl_ClkSwitch 0x00000020 |
| #define clkD6_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD6_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD6_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD6_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD6_ctrl_ClkD3Switch 6 |
| #define LSb16clkD6_ctrl_ClkD3Switch 6 |
| #define bclkD6_ctrl_ClkD3Switch 1 |
| #define MSK32clkD6_ctrl_ClkD3Switch 0x00000040 |
| #define clkD6_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD6_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD6_ctrl_ClkSel 0x0000 |
| #define B16clkD6_ctrl_ClkSel 0x0000 |
| #define LSb32clkD6_ctrl_ClkSel 7 |
| #define LSb16clkD6_ctrl_ClkSel 7 |
| #define bclkD6_ctrl_ClkSel 3 |
| #define MSK32clkD6_ctrl_ClkSel 0x00000380 |
| #define clkD6_ctrl_ClkSel_d2 0x1 |
| #define clkD6_ctrl_ClkSel_d4 0x2 |
| #define clkD6_ctrl_ClkSel_d6 0x3 |
| #define clkD6_ctrl_ClkSel_d8 0x4 |
| #define clkD6_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD8_ctrl 0x0000 |
| #define BA_clkD8_ctrl_ClkEn 0x0000 |
| #define B16clkD8_ctrl_ClkEn 0x0000 |
| #define LSb32clkD8_ctrl_ClkEn 0 |
| #define LSb16clkD8_ctrl_ClkEn 0 |
| #define bclkD8_ctrl_ClkEn 1 |
| #define MSK32clkD8_ctrl_ClkEn 0x00000001 |
| #define clkD8_ctrl_ClkEn_enable 0x1 |
| #define clkD8_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD8_ctrl_ClkPllSel 0x0000 |
| #define B16clkD8_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD8_ctrl_ClkPllSel 1 |
| #define LSb16clkD8_ctrl_ClkPllSel 1 |
| #define bclkD8_ctrl_ClkPllSel 3 |
| #define MSK32clkD8_ctrl_ClkPllSel 0x0000000E |
| #define clkD8_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD8_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD8_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD8_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD8_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD8_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD8_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD8_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD8_ctrl_ClkPllSwitch 4 |
| #define bclkD8_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD8_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD8_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD8_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD8_ctrl_ClkSwitch 0x0000 |
| #define B16clkD8_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD8_ctrl_ClkSwitch 5 |
| #define LSb16clkD8_ctrl_ClkSwitch 5 |
| #define bclkD8_ctrl_ClkSwitch 1 |
| #define MSK32clkD8_ctrl_ClkSwitch 0x00000020 |
| #define clkD8_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD8_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD8_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD8_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD8_ctrl_ClkD3Switch 6 |
| #define LSb16clkD8_ctrl_ClkD3Switch 6 |
| #define bclkD8_ctrl_ClkD3Switch 1 |
| #define MSK32clkD8_ctrl_ClkD3Switch 0x00000040 |
| #define clkD8_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD8_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD8_ctrl_ClkSel 0x0000 |
| #define B16clkD8_ctrl_ClkSel 0x0000 |
| #define LSb32clkD8_ctrl_ClkSel 7 |
| #define LSb16clkD8_ctrl_ClkSel 7 |
| #define bclkD8_ctrl_ClkSel 3 |
| #define MSK32clkD8_ctrl_ClkSel 0x00000380 |
| #define clkD8_ctrl_ClkSel_d2 0x1 |
| #define clkD8_ctrl_ClkSel_d4 0x2 |
| #define clkD8_ctrl_ClkSel_d6 0x3 |
| #define clkD8_ctrl_ClkSel_d8 0x4 |
| #define clkD8_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD12_ctrl 0x0000 |
| #define BA_clkD12_ctrl_ClkEn 0x0000 |
| #define B16clkD12_ctrl_ClkEn 0x0000 |
| #define LSb32clkD12_ctrl_ClkEn 0 |
| #define LSb16clkD12_ctrl_ClkEn 0 |
| #define bclkD12_ctrl_ClkEn 1 |
| #define MSK32clkD12_ctrl_ClkEn 0x00000001 |
| #define clkD12_ctrl_ClkEn_enable 0x1 |
| #define clkD12_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD12_ctrl_ClkPllSel 0x0000 |
| #define B16clkD12_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD12_ctrl_ClkPllSel 1 |
| #define LSb16clkD12_ctrl_ClkPllSel 1 |
| #define bclkD12_ctrl_ClkPllSel 3 |
| #define MSK32clkD12_ctrl_ClkPllSel 0x0000000E |
| #define clkD12_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD12_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD12_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD12_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD12_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD12_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD12_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD12_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD12_ctrl_ClkPllSwitch 4 |
| #define bclkD12_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD12_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD12_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD12_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD12_ctrl_ClkSwitch 0x0000 |
| #define B16clkD12_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD12_ctrl_ClkSwitch 5 |
| #define LSb16clkD12_ctrl_ClkSwitch 5 |
| #define bclkD12_ctrl_ClkSwitch 1 |
| #define MSK32clkD12_ctrl_ClkSwitch 0x00000020 |
| #define clkD12_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD12_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD12_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD12_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD12_ctrl_ClkD3Switch 6 |
| #define LSb16clkD12_ctrl_ClkD3Switch 6 |
| #define bclkD12_ctrl_ClkD3Switch 1 |
| #define MSK32clkD12_ctrl_ClkD3Switch 0x00000040 |
| #define clkD12_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD12_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD12_ctrl_ClkSel 0x0000 |
| #define B16clkD12_ctrl_ClkSel 0x0000 |
| #define LSb32clkD12_ctrl_ClkSel 7 |
| #define LSb16clkD12_ctrl_ClkSel 7 |
| #define bclkD12_ctrl_ClkSel 3 |
| #define MSK32clkD12_ctrl_ClkSel 0x00000380 |
| #define clkD12_ctrl_ClkSel_d2 0x1 |
| #define clkD12_ctrl_ClkSel_d4 0x2 |
| #define clkD12_ctrl_ClkSel_d6 0x3 |
| #define clkD12_ctrl_ClkSel_d8 0x4 |
| #define clkD12_ctrl_ClkSel_d12 0x5 |
| #define RA_efuse_ctrl 0x0000 |
| #define BA_efuse_ctrl_PROG_SEQ_CODE 0x0000 |
| #define B16efuse_ctrl_PROG_SEQ_CODE 0x0000 |
| #define LSb32efuse_ctrl_PROG_SEQ_CODE 0 |
| #define LSb16efuse_ctrl_PROG_SEQ_CODE 0 |
| #define befuse_ctrl_PROG_SEQ_CODE 1 |
| #define MSK32efuse_ctrl_PROG_SEQ_CODE 0x00000001 |
| #define BA_efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define B16efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define LSb32efuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define LSb16efuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define befuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define MSK32efuse_ctrl_PROG_SEQ_CODE_CLK 0x00000002 |
| #define BA_efuse_ctrl_SCLK 0x0000 |
| #define B16efuse_ctrl_SCLK 0x0000 |
| #define LSb32efuse_ctrl_SCLK 2 |
| #define LSb16efuse_ctrl_SCLK 2 |
| #define befuse_ctrl_SCLK 1 |
| #define MSK32efuse_ctrl_SCLK 0x00000004 |
| #define BA_efuse_ctrl_PRDT 0x0000 |
| #define B16efuse_ctrl_PRDT 0x0000 |
| #define LSb32efuse_ctrl_PRDT 3 |
| #define LSb16efuse_ctrl_PRDT 3 |
| #define befuse_ctrl_PRDT 1 |
| #define MSK32efuse_ctrl_PRDT 0x00000008 |
| #define BA_efuse_ctrl_POR_B 0x0000 |
| #define B16efuse_ctrl_POR_B 0x0000 |
| #define LSb32efuse_ctrl_POR_B 4 |
| #define LSb16efuse_ctrl_POR_B 4 |
| #define befuse_ctrl_POR_B 1 |
| #define MSK32efuse_ctrl_POR_B 0x00000010 |
| #define BA_efuse_ctrl_CSB 0x0000 |
| #define B16efuse_ctrl_CSB 0x0000 |
| #define LSb32efuse_ctrl_CSB 5 |
| #define LSb16efuse_ctrl_CSB 5 |
| #define befuse_ctrl_CSB 1 |
| #define MSK32efuse_ctrl_CSB 0x00000020 |
| #define BA_efuse_ctrl_PGM 0x0000 |
| #define B16efuse_ctrl_PGM 0x0000 |
| #define LSb32efuse_ctrl_PGM 6 |
| #define LSb16efuse_ctrl_PGM 6 |
| #define befuse_ctrl_PGM 1 |
| #define MSK32efuse_ctrl_PGM 0x00000040 |
| #define BA_efuse_ctrl_WPROT 0x0000 |
| #define B16efuse_ctrl_WPROT 0x0000 |
| #define LSb32efuse_ctrl_WPROT 7 |
| #define LSb16efuse_ctrl_WPROT 7 |
| #define befuse_ctrl_WPROT 1 |
| #define MSK32efuse_ctrl_WPROT 0x00000080 |
| #define BA_efuse_ctrl_TEST 0x0001 |
| #define B16efuse_ctrl_TEST 0x0000 |
| #define LSb32efuse_ctrl_TEST 8 |
| #define LSb16efuse_ctrl_TEST 8 |
| #define befuse_ctrl_TEST 4 |
| #define MSK32efuse_ctrl_TEST 0x00000F00 |
| #define RA_efuse_status_match 0x0004 |
| #define BA_efuse_status_match_MATCH_VALUE 0x0004 |
| #define B16efuse_status_match_MATCH_VALUE 0x0004 |
| #define LSb32efuse_status_match_MATCH_VALUE 0 |
| #define LSb16efuse_status_match_MATCH_VALUE 0 |
| #define befuse_status_match_MATCH_VALUE 1 |
| #define MSK32efuse_status_match_MATCH_VALUE 0x00000001 |
| #define RA_efuse_status_qout 0x0008 |
| #define BA_efuse_status_qout_QOUT_31_0 0x0008 |
| #define B16efuse_status_qout_QOUT_31_0 0x0008 |
| #define LSb32efuse_status_qout_QOUT_31_0 0 |
| #define LSb16efuse_status_qout_QOUT_31_0 0 |
| #define befuse_status_qout_QOUT_31_0 32 |
| #define MSK32efuse_status_qout_QOUT_31_0 0xFFFFFFFF |
| #define RA_efuse_status_qout1 0x000C |
| #define BA_efuse_status_qout_QOUT_63_32 0x000C |
| #define B16efuse_status_qout_QOUT_63_32 0x000C |
| #define LSb32efuse_status_qout_QOUT_63_32 0 |
| #define LSb16efuse_status_qout_QOUT_63_32 0 |
| #define befuse_status_qout_QOUT_63_32 32 |
| #define MSK32efuse_status_qout_QOUT_63_32 0xFFFFFFFF |
| #define RA_efuse_status_qout2 0x0010 |
| #define BA_efuse_status_qout_QOUT_95_64 0x0010 |
| #define B16efuse_status_qout_QOUT_95_64 0x0010 |
| #define LSb32efuse_status_qout_QOUT_95_64 0 |
| #define LSb16efuse_status_qout_QOUT_95_64 0 |
| #define befuse_status_qout_QOUT_95_64 32 |
| #define MSK32efuse_status_qout_QOUT_95_64 0xFFFFFFFF |
| #define RA_efuse_status_qout3 0x0014 |
| #define BA_efuse_status_qout_QOUT_127_96 0x0014 |
| #define B16efuse_status_qout_QOUT_127_96 0x0014 |
| #define LSb32efuse_status_qout_QOUT_127_96 0 |
| #define LSb16efuse_status_qout_QOUT_127_96 0 |
| #define befuse_status_qout_QOUT_127_96 32 |
| #define MSK32efuse_status_qout_QOUT_127_96 0xFFFFFFFF |
| #define RA_efuse_status_qout4 0x0018 |
| #define BA_efuse_status_qout_QOUT_159_128 0x0018 |
| #define B16efuse_status_qout_QOUT_159_128 0x0018 |
| #define LSb32efuse_status_qout_QOUT_159_128 0 |
| #define LSb16efuse_status_qout_QOUT_159_128 0 |
| #define befuse_status_qout_QOUT_159_128 32 |
| #define MSK32efuse_status_qout_QOUT_159_128 0xFFFFFFFF |
| #define RA_efuse_status_qout5 0x001C |
| #define BA_efuse_status_qout_QOUT_191_160 0x001C |
| #define B16efuse_status_qout_QOUT_191_160 0x001C |
| #define LSb32efuse_status_qout_QOUT_191_160 0 |
| #define LSb16efuse_status_qout_QOUT_191_160 0 |
| #define befuse_status_qout_QOUT_191_160 32 |
| #define MSK32efuse_status_qout_QOUT_191_160 0xFFFFFFFF |
| #define RA_efuse_status_qout6 0x0020 |
| #define BA_efuse_status_qout_QOUT_223_192 0x0020 |
| #define B16efuse_status_qout_QOUT_223_192 0x0020 |
| #define LSb32efuse_status_qout_QOUT_223_192 0 |
| #define LSb16efuse_status_qout_QOUT_223_192 0 |
| #define befuse_status_qout_QOUT_223_192 32 |
| #define MSK32efuse_status_qout_QOUT_223_192 0xFFFFFFFF |
| #define RA_efuse_status_qout7 0x0024 |
| #define BA_efuse_status_qout_QOUT_255_224 0x0024 |
| #define B16efuse_status_qout_QOUT_255_224 0x0024 |
| #define LSb32efuse_status_qout_QOUT_255_224 0 |
| #define LSb16efuse_status_qout_QOUT_255_224 0 |
| #define befuse_status_qout_QOUT_255_224 32 |
| #define MSK32efuse_status_qout_QOUT_255_224 0xFFFFFFFF |
| #define RA_efuse_status_qout8 0x0028 |
| #define BA_efuse_status_qout_QOUT_272_256 0x0028 |
| #define B16efuse_status_qout_QOUT_272_256 0x0028 |
| #define LSb32efuse_status_qout_QOUT_272_256 0 |
| #define LSb16efuse_status_qout_QOUT_272_256 0 |
| #define befuse_status_qout_QOUT_272_256 17 |
| #define MSK32efuse_status_qout_QOUT_272_256 0x0001FFFF |
| #define RA_PERIF_PHY_DBG_CTRL 0x0000 |
| #define BA_PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x0000 |
| #define B16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x0000 |
| #define LSb32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0 |
| #define LSb16PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0 |
| #define bPERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 1 |
| #define MSK32PERIF_PHY_DBG_CTRL_USB0_SATA_PHY_DBG 0x00000001 |
| #define RA_PERIF_USB_CTRL 0x0004 |
| #define BA_PERIF_USB_CTRL_DISABLE_EL16 0x0004 |
| #define B16PERIF_USB_CTRL_DISABLE_EL16 0x0004 |
| #define LSb32PERIF_USB_CTRL_DISABLE_EL16 0 |
| #define LSb16PERIF_USB_CTRL_DISABLE_EL16 0 |
| #define bPERIF_USB_CTRL_DISABLE_EL16 1 |
| #define MSK32PERIF_USB_CTRL_DISABLE_EL16 0x00000001 |
| #define BA_PERIF_USB_CTRL_CTRL_MODE 0x0004 |
| #define B16PERIF_USB_CTRL_CTRL_MODE 0x0004 |
| #define LSb32PERIF_USB_CTRL_CTRL_MODE 1 |
| #define LSb16PERIF_USB_CTRL_CTRL_MODE 1 |
| #define bPERIF_USB_CTRL_CTRL_MODE 2 |
| #define MSK32PERIF_USB_CTRL_CTRL_MODE 0x00000006 |
| #define RA_PERIF_RSERVED_CTRL0 0x0008 |
| #define BA_PERIF_RSERVED_CTRL0_ctrl 0x0008 |
| #define B16PERIF_RSERVED_CTRL0_ctrl 0x0008 |
| #define LSb32PERIF_RSERVED_CTRL0_ctrl 0 |
| #define LSb16PERIF_RSERVED_CTRL0_ctrl 0 |
| #define bPERIF_RSERVED_CTRL0_ctrl 32 |
| #define MSK32PERIF_RSERVED_CTRL0_ctrl 0xFFFFFFFF |
| #define RA_padRing_ctrl 0x0000 |
| #define BA_padRing_ctrl_REG_PDB_CORE 0x0000 |
| #define B16padRing_ctrl_REG_PDB_CORE 0x0000 |
| #define LSb32padRing_ctrl_REG_PDB_CORE 0 |
| #define LSb16padRing_ctrl_REG_PDB_CORE 0 |
| #define bpadRing_ctrl_REG_PDB_CORE 1 |
| #define MSK32padRing_ctrl_REG_PDB_CORE 0x00000001 |
| #define padRing_ctrl_REG_PDB_CORE_NORMAL 0x1 |
| #define padRing_ctrl_REG_PDB_CORE_PWRDN 0x0 |
| #define BA_padRing_ctrl_REF_INT_EN 0x0000 |
| #define B16padRing_ctrl_REF_INT_EN 0x0000 |
| #define LSb32padRing_ctrl_REF_INT_EN 1 |
| #define LSb16padRing_ctrl_REF_INT_EN 1 |
| #define bpadRing_ctrl_REF_INT_EN 1 |
| #define MSK32padRing_ctrl_REF_INT_EN 0x00000002 |
| #define padRing_ctrl_REF_INT_EN_NORMAL 0x1 |
| #define padRing_ctrl_REF_INT_EN_REF_DOWN 0x0 |
| #define BA_padRing_ctrl_V18EN_CORE 0x0000 |
| #define B16padRing_ctrl_V18EN_CORE 0x0000 |
| #define LSb32padRing_ctrl_V18EN_CORE 2 |
| #define LSb16padRing_ctrl_V18EN_CORE 2 |
| #define bpadRing_ctrl_V18EN_CORE 1 |
| #define MSK32padRing_ctrl_V18EN_CORE 0x00000004 |
| #define BA_padRing_ctrl_V25EN_CORE 0x0000 |
| #define B16padRing_ctrl_V25EN_CORE 0x0000 |
| #define LSb32padRing_ctrl_V25EN_CORE 3 |
| #define LSb16padRing_ctrl_V25EN_CORE 3 |
| #define bpadRing_ctrl_V25EN_CORE 1 |
| #define MSK32padRing_ctrl_V25EN_CORE 0x00000008 |
| #define BA_padRing_ctrl_ZP 0x0000 |
| #define B16padRing_ctrl_ZP 0x0000 |
| #define LSb32padRing_ctrl_ZP 4 |
| #define LSb16padRing_ctrl_ZP 4 |
| #define bpadRing_ctrl_ZP 4 |
| #define MSK32padRing_ctrl_ZP 0x000000F0 |
| #define BA_padRing_ctrl_ZN 0x0001 |
| #define B16padRing_ctrl_ZN 0x0000 |
| #define LSb32padRing_ctrl_ZN 8 |
| #define LSb16padRing_ctrl_ZN 8 |
| #define bpadRing_ctrl_ZN 4 |
| #define MSK32padRing_ctrl_ZN 0x00000F00 |
| #define BA_padRing_ctrl_CAL_ZP 0x0001 |
| #define B16padRing_ctrl_CAL_ZP 0x0000 |
| #define LSb32padRing_ctrl_CAL_ZP 12 |
| #define LSb16padRing_ctrl_CAL_ZP 12 |
| #define bpadRing_ctrl_CAL_ZP 4 |
| #define MSK32padRing_ctrl_CAL_ZP 0x0000F000 |
| #define BA_padRing_ctrl_CAL_ZN 0x0002 |
| #define B16padRing_ctrl_CAL_ZN 0x0002 |
| #define LSb32padRing_ctrl_CAL_ZN 16 |
| #define LSb16padRing_ctrl_CAL_ZN 0 |
| #define bpadRing_ctrl_CAL_ZN 4 |
| #define MSK32padRing_ctrl_CAL_ZN 0x000F0000 |
| #define BA_padRing_ctrl_CAL_P_EN 0x0002 |
| #define B16padRing_ctrl_CAL_P_EN 0x0002 |
| #define LSb32padRing_ctrl_CAL_P_EN 20 |
| #define LSb16padRing_ctrl_CAL_P_EN 4 |
| #define bpadRing_ctrl_CAL_P_EN 1 |
| #define MSK32padRing_ctrl_CAL_P_EN 0x00100000 |
| #define BA_padRing_ctrl_CAL_N_EN 0x0002 |
| #define B16padRing_ctrl_CAL_N_EN 0x0002 |
| #define LSb32padRing_ctrl_CAL_N_EN 21 |
| #define LSb16padRing_ctrl_CAL_N_EN 5 |
| #define bpadRing_ctrl_CAL_N_EN 1 |
| #define MSK32padRing_ctrl_CAL_N_EN 0x00200000 |
| #define BA_padRing_ctrl_ODR_EN 0x0002 |
| #define B16padRing_ctrl_ODR_EN 0x0002 |
| #define LSb32padRing_ctrl_ODR_EN 22 |
| #define LSb16padRing_ctrl_ODR_EN 6 |
| #define bpadRing_ctrl_ODR_EN 1 |
| #define MSK32padRing_ctrl_ODR_EN 0x00400000 |
| #define BA_padRing_ctrl_ODR 0x0002 |
| #define B16padRing_ctrl_ODR 0x0002 |
| #define LSb32padRing_ctrl_ODR 23 |
| #define LSb16padRing_ctrl_ODR 7 |
| #define bpadRing_ctrl_ODR 3 |
| #define MSK32padRing_ctrl_ODR 0x03800000 |
| #define BA_padRing_ctrl_ZP_AFT_CAL 0x0003 |
| #define B16padRing_ctrl_ZP_AFT_CAL 0x0002 |
| #define LSb32padRing_ctrl_ZP_AFT_CAL 26 |
| #define LSb16padRing_ctrl_ZP_AFT_CAL 10 |
| #define bpadRing_ctrl_ZP_AFT_CAL 4 |
| #define MSK32padRing_ctrl_ZP_AFT_CAL 0x3C000000 |
| #define RA_padRing_status 0x0004 |
| #define BA_padRing_status_CAL_P_INC 0x0004 |
| #define B16padRing_status_CAL_P_INC 0x0004 |
| #define LSb32padRing_status_CAL_P_INC 0 |
| #define LSb16padRing_status_CAL_P_INC 0 |
| #define bpadRing_status_CAL_P_INC 1 |
| #define MSK32padRing_status_CAL_P_INC 0x00000001 |
| #define BA_padRing_status_CAL_N_INC 0x0004 |
| #define B16padRing_status_CAL_N_INC 0x0004 |
| #define LSb32padRing_status_CAL_N_INC 1 |
| #define LSb16padRing_status_CAL_N_INC 1 |
| #define bpadRing_status_CAL_N_INC 1 |
| #define MSK32padRing_status_CAL_N_INC 0x00000002 |
| #define RA_padRingHS_ctrl 0x0000 |
| #define BA_padRingHS_ctrl_PDB_LV 0x0000 |
| #define B16padRingHS_ctrl_PDB_LV 0x0000 |
| #define LSb32padRingHS_ctrl_PDB_LV 0 |
| #define LSb16padRingHS_ctrl_PDB_LV 0 |
| #define bpadRingHS_ctrl_PDB_LV 1 |
| #define MSK32padRingHS_ctrl_PDB_LV 0x00000001 |
| #define padRingHS_ctrl_PDB_LV_NORMAL 0x1 |
| #define padRingHS_ctrl_PDB_LV_PWRDN 0x0 |
| #define BA_padRingHS_ctrl_V18EN_CORE 0x0000 |
| #define B16padRingHS_ctrl_V18EN_CORE 0x0000 |
| #define LSb32padRingHS_ctrl_V18EN_CORE 1 |
| #define LSb16padRingHS_ctrl_V18EN_CORE 1 |
| #define bpadRingHS_ctrl_V18EN_CORE 1 |
| #define MSK32padRingHS_ctrl_V18EN_CORE 0x00000002 |
| #define BA_padRingHS_ctrl_V25EN_CORE 0x0000 |
| #define B16padRingHS_ctrl_V25EN_CORE 0x0000 |
| #define LSb32padRingHS_ctrl_V25EN_CORE 2 |
| #define LSb16padRingHS_ctrl_V25EN_CORE 2 |
| #define bpadRingHS_ctrl_V25EN_CORE 1 |
| #define MSK32padRingHS_ctrl_V25EN_CORE 0x00000004 |
| #define BA_padRingHS_ctrl_ZP 0x0000 |
| #define B16padRingHS_ctrl_ZP 0x0000 |
| #define LSb32padRingHS_ctrl_ZP 3 |
| #define LSb16padRingHS_ctrl_ZP 3 |
| #define bpadRingHS_ctrl_ZP 3 |
| #define MSK32padRingHS_ctrl_ZP 0x00000038 |
| #define BA_padRingHS_ctrl_ZN 0x0000 |
| #define B16padRingHS_ctrl_ZN 0x0000 |
| #define LSb32padRingHS_ctrl_ZN 6 |
| #define LSb16padRingHS_ctrl_ZN 6 |
| #define bpadRingHS_ctrl_ZN 3 |
| #define MSK32padRingHS_ctrl_ZN 0x000001C0 |
| #define BA_padRingHS_ctrl_CAL_ZP 0x0001 |
| #define B16padRingHS_ctrl_CAL_ZP 0x0000 |
| #define LSb32padRingHS_ctrl_CAL_ZP 9 |
| #define LSb16padRingHS_ctrl_CAL_ZP 9 |
| #define bpadRingHS_ctrl_CAL_ZP 3 |
| #define MSK32padRingHS_ctrl_CAL_ZP 0x00000E00 |
| #define BA_padRingHS_ctrl_CAL_ZN 0x0001 |
| #define B16padRingHS_ctrl_CAL_ZN 0x0000 |
| #define LSb32padRingHS_ctrl_CAL_ZN 12 |
| #define LSb16padRingHS_ctrl_CAL_ZN 12 |
| #define bpadRingHS_ctrl_CAL_ZN 3 |
| #define MSK32padRingHS_ctrl_CAL_ZN 0x00007000 |
| #define BA_padRingHS_ctrl_CAL_RON_ADJ 0x0001 |
| #define B16padRingHS_ctrl_CAL_RON_ADJ 0x0000 |
| #define LSb32padRingHS_ctrl_CAL_RON_ADJ 15 |
| #define LSb16padRingHS_ctrl_CAL_RON_ADJ 15 |
| #define bpadRingHS_ctrl_CAL_RON_ADJ 3 |
| #define MSK32padRingHS_ctrl_CAL_RON_ADJ 0x00038000 |
| #define BA_padRingHS_ctrl_CAL_EN 0x0002 |
| #define B16padRingHS_ctrl_CAL_EN 0x0002 |
| #define LSb32padRingHS_ctrl_CAL_EN 18 |
| #define LSb16padRingHS_ctrl_CAL_EN 2 |
| #define bpadRingHS_ctrl_CAL_EN 1 |
| #define MSK32padRingHS_ctrl_CAL_EN 0x00040000 |
| #define BA_padRingHS_ctrl_CAL_DO 0x0002 |
| #define B16padRingHS_ctrl_CAL_DO 0x0002 |
| #define LSb32padRingHS_ctrl_CAL_DO 19 |
| #define LSb16padRingHS_ctrl_CAL_DO 3 |
| #define bpadRingHS_ctrl_CAL_DO 1 |
| #define MSK32padRingHS_ctrl_CAL_DO 0x00080000 |
| #define RA_padRingHS_status 0x0004 |
| #define BA_padRingHS_status_CAL_INC 0x0004 |
| #define B16padRingHS_status_CAL_INC 0x0004 |
| #define LSb32padRingHS_status_CAL_INC 0 |
| #define LSb16padRingHS_status_CAL_INC 0 |
| #define bpadRingHS_status_CAL_INC 1 |
| #define MSK32padRingHS_status_CAL_INC 0x00000001 |
| #define RA_vtr_ctrl 0x0000 |
| #define BA_vtr_ctrl_SWITCH_ON 0x0000 |
| #define B16vtr_ctrl_SWITCH_ON 0x0000 |
| #define LSb32vtr_ctrl_SWITCH_ON 0 |
| #define LSb16vtr_ctrl_SWITCH_ON 0 |
| #define bvtr_ctrl_SWITCH_ON 1 |
| #define MSK32vtr_ctrl_SWITCH_ON 0x00000001 |
| #define vtr_ctrl_SWITCH_ON_TRISTATE 0x0 |
| #define vtr_ctrl_SWITCH_ON_ENABLE 0x1 |
| #define BA_vtr_ctrl_VOLT_SEL 0x0000 |
| #define B16vtr_ctrl_VOLT_SEL 0x0000 |
| #define LSb32vtr_ctrl_VOLT_SEL 1 |
| #define LSb16vtr_ctrl_VOLT_SEL 1 |
| #define bvtr_ctrl_VOLT_SEL 2 |
| #define MSK32vtr_ctrl_VOLT_SEL 0x00000006 |
| #define BA_vtr_ctrl_PROG_SEQ_CODE 0x0000 |
| #define B16vtr_ctrl_PROG_SEQ_CODE 0x0000 |
| #define LSb32vtr_ctrl_PROG_SEQ_CODE 3 |
| #define LSb16vtr_ctrl_PROG_SEQ_CODE 3 |
| #define bvtr_ctrl_PROG_SEQ_CODE 1 |
| #define MSK32vtr_ctrl_PROG_SEQ_CODE 0x00000008 |
| #define BA_vtr_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define B16vtr_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define LSb32vtr_ctrl_PROG_SEQ_CODE_CLK 4 |
| #define LSb16vtr_ctrl_PROG_SEQ_CODE_CLK 4 |
| #define bvtr_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define MSK32vtr_ctrl_PROG_SEQ_CODE_CLK 0x00000010 |
| #define RA_vtr_status 0x0004 |
| #define BA_vtr_status_MATCH 0x0004 |
| #define B16vtr_status_MATCH 0x0004 |
| #define LSb32vtr_status_MATCH 0 |
| #define LSb16vtr_status_MATCH 0 |
| #define bvtr_status_MATCH 1 |
| #define MSK32vtr_status_MATCH 0x00000001 |
| #define RA_Gbl_ProductId 0x0000 |
| #define BA_Gbl_ProductId_Id 0x0000 |
| #define B16Gbl_ProductId_Id 0x0000 |
| #define LSb32Gbl_ProductId_Id 0 |
| #define LSb16Gbl_ProductId_Id 0 |
| #define bGbl_ProductId_Id 32 |
| #define MSK32Gbl_ProductId_Id 0xFFFFFFFF |
| #define RA_Gbl_ProductId_ext 0x0004 |
| #define BA_Gbl_ProductId_ext_ID_EXT 0x0004 |
| #define B16Gbl_ProductId_ext_ID_EXT 0x0004 |
| #define LSb32Gbl_ProductId_ext_ID_EXT 0 |
| #define LSb16Gbl_ProductId_ext_ID_EXT 0 |
| #define bGbl_ProductId_ext_ID_EXT 8 |
| #define MSK32Gbl_ProductId_ext_ID_EXT 0x000000FF |
| #define RA_Gbl_INT_ID 0x0008 |
| #define BA_Gbl_INT_ID_VALUE 0x0008 |
| #define B16Gbl_INT_ID_VALUE 0x0008 |
| #define LSb32Gbl_INT_ID_VALUE 0 |
| #define LSb16Gbl_INT_ID_VALUE 0 |
| #define bGbl_INT_ID_VALUE 8 |
| #define MSK32Gbl_INT_ID_VALUE 0x000000FF |
| #define RA_Gbl_bootStrap 0x000C |
| #define BA_Gbl_bootStrap_softwareStrap 0x000C |
| #define B16Gbl_bootStrap_softwareStrap 0x000C |
| #define LSb32Gbl_bootStrap_softwareStrap 0 |
| #define LSb16Gbl_bootStrap_softwareStrap 0 |
| #define bGbl_bootStrap_softwareStrap 2 |
| #define MSK32Gbl_bootStrap_softwareStrap 0x00000003 |
| #define BA_Gbl_bootStrap_bootSrc 0x000C |
| #define B16Gbl_bootStrap_bootSrc 0x000C |
| #define LSb32Gbl_bootStrap_bootSrc 2 |
| #define LSb16Gbl_bootStrap_bootSrc 2 |
| #define bGbl_bootStrap_bootSrc 2 |
| #define MSK32Gbl_bootStrap_bootSrc 0x0000000C |
| #define Gbl_bootStrap_bootSrc_ROM_SPI_BOOT 0x0 |
| #define Gbl_bootStrap_bootSrc_ROM_NAND_BOOT 0x1 |
| #define Gbl_bootStrap_bootSrc_ROM_EMMC_BOOT 0x2 |
| #define Gbl_bootStrap_bootSrc_ROM_SPI_DIRECT_BOOT 0x3 |
| #define BA_Gbl_bootStrap_cpuRstByps 0x000C |
| #define B16Gbl_bootStrap_cpuRstByps 0x000C |
| #define LSb32Gbl_bootStrap_cpuRstByps 4 |
| #define LSb16Gbl_bootStrap_cpuRstByps 4 |
| #define bGbl_bootStrap_cpuRstByps 1 |
| #define MSK32Gbl_bootStrap_cpuRstByps 0x00000010 |
| #define Gbl_bootStrap_cpuRstByps_CPU_INT_RST_BYPS 0x1 |
| #define Gbl_bootStrap_cpuRstByps_CPU_INT_RST_EN 0x0 |
| #define BA_Gbl_bootStrap_pwrCntlByps 0x000C |
| #define B16Gbl_bootStrap_pwrCntlByps 0x000C |
| #define LSb32Gbl_bootStrap_pwrCntlByps 5 |
| #define LSb16Gbl_bootStrap_pwrCntlByps 5 |
| #define bGbl_bootStrap_pwrCntlByps 1 |
| #define MSK32Gbl_bootStrap_pwrCntlByps 0x00000020 |
| #define Gbl_bootStrap_pwrCntlByps_PWR_SWITCH_ON 0x1 |
| #define Gbl_bootStrap_pwrCntlByps_PWR_SWITCH_OFF 0x0 |
| #define BA_Gbl_bootStrap_pllPwrDown 0x000C |
| #define B16Gbl_bootStrap_pllPwrDown 0x000C |
| #define LSb32Gbl_bootStrap_pllPwrDown 6 |
| #define LSb16Gbl_bootStrap_pllPwrDown 6 |
| #define bGbl_bootStrap_pllPwrDown 1 |
| #define MSK32Gbl_bootStrap_pllPwrDown 0x00000040 |
| #define Gbl_bootStrap_pllPwrDown_PWR_DOWN 0x1 |
| #define Gbl_bootStrap_pllPwrDown_PWR_UP 0x0 |
| #define BA_Gbl_bootStrap_sysPllByps 0x000C |
| #define B16Gbl_bootStrap_sysPllByps 0x000C |
| #define LSb32Gbl_bootStrap_sysPllByps 7 |
| #define LSb16Gbl_bootStrap_sysPllByps 7 |
| #define bGbl_bootStrap_sysPllByps 1 |
| #define MSK32Gbl_bootStrap_sysPllByps 0x00000080 |
| #define Gbl_bootStrap_sysPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_sysPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_memPllByps 0x000D |
| #define B16Gbl_bootStrap_memPllByps 0x000C |
| #define LSb32Gbl_bootStrap_memPllByps 8 |
| #define LSb16Gbl_bootStrap_memPllByps 8 |
| #define bGbl_bootStrap_memPllByps 1 |
| #define MSK32Gbl_bootStrap_memPllByps 0x00000100 |
| #define Gbl_bootStrap_memPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_memPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_cpuPllByps 0x000D |
| #define B16Gbl_bootStrap_cpuPllByps 0x000C |
| #define LSb32Gbl_bootStrap_cpuPllByps 9 |
| #define LSb16Gbl_bootStrap_cpuPllByps 9 |
| #define bGbl_bootStrap_cpuPllByps 1 |
| #define MSK32Gbl_bootStrap_cpuPllByps 0x00000200 |
| #define Gbl_bootStrap_cpuPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_cpuPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_nandV18Enable 0x000D |
| #define B16Gbl_bootStrap_nandV18Enable 0x000C |
| #define LSb32Gbl_bootStrap_nandV18Enable 10 |
| #define LSb16Gbl_bootStrap_nandV18Enable 10 |
| #define bGbl_bootStrap_nandV18Enable 1 |
| #define MSK32Gbl_bootStrap_nandV18Enable 0x00000400 |
| #define Gbl_bootStrap_nandV18Enable_V1R8 0x0 |
| #define Gbl_bootStrap_nandV18Enable_V3R3 0x1 |
| #define BA_Gbl_bootStrap_dftStrap 0x000D |
| #define B16Gbl_bootStrap_dftStrap 0x000C |
| #define LSb32Gbl_bootStrap_dftStrap 11 |
| #define LSb16Gbl_bootStrap_dftStrap 11 |
| #define bGbl_bootStrap_dftStrap 1 |
| #define MSK32Gbl_bootStrap_dftStrap 0x00000800 |
| #define BA_Gbl_bootStrap_ENG_EN 0x000D |
| #define B16Gbl_bootStrap_ENG_EN 0x000C |
| #define LSb32Gbl_bootStrap_ENG_EN 12 |
| #define LSb16Gbl_bootStrap_ENG_EN 12 |
| #define bGbl_bootStrap_ENG_EN 1 |
| #define MSK32Gbl_bootStrap_ENG_EN 0x00001000 |
| #define Gbl_bootStrap_ENG_EN_PRODUCTION_MODE 0x0 |
| #define Gbl_bootStrap_ENG_EN_DEVELOPE_MODE 0x1 |
| #define RA_Gbl_bootStrapEn 0x0010 |
| #define BA_Gbl_bootStrapEn_cpuRstBypsEn 0x0010 |
| #define B16Gbl_bootStrapEn_cpuRstBypsEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_cpuRstBypsEn 0 |
| #define LSb16Gbl_bootStrapEn_cpuRstBypsEn 0 |
| #define bGbl_bootStrapEn_cpuRstBypsEn 1 |
| #define MSK32Gbl_bootStrapEn_cpuRstBypsEn 0x00000001 |
| #define Gbl_bootStrapEn_cpuRstBypsEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_cpuRstBypsEn_DISABLE 0x0 |
| #define BA_Gbl_bootStrapEn_pwrCntlBypsEn 0x0010 |
| #define B16Gbl_bootStrapEn_pwrCntlBypsEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_pwrCntlBypsEn 1 |
| #define LSb16Gbl_bootStrapEn_pwrCntlBypsEn 1 |
| #define bGbl_bootStrapEn_pwrCntlBypsEn 1 |
| #define MSK32Gbl_bootStrapEn_pwrCntlBypsEn 0x00000002 |
| #define Gbl_bootStrapEn_pwrCntlBypsEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_pwrCntlBypsEn_DISABLE 0x0 |
| #define BA_Gbl_bootStrapEn_pllPwrDownEn 0x0010 |
| #define B16Gbl_bootStrapEn_pllPwrDownEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_pllPwrDownEn 2 |
| #define LSb16Gbl_bootStrapEn_pllPwrDownEn 2 |
| #define bGbl_bootStrapEn_pllPwrDownEn 1 |
| #define MSK32Gbl_bootStrapEn_pllPwrDownEn 0x00000004 |
| #define Gbl_bootStrapEn_pllPwrDownEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_pllPwrDownEn_DISABLE 0x0 |
| #define BA_Gbl_bootStrapEn_sysPLLBypsEn 0x0010 |
| #define B16Gbl_bootStrapEn_sysPLLBypsEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_sysPLLBypsEn 3 |
| #define LSb16Gbl_bootStrapEn_sysPLLBypsEn 3 |
| #define bGbl_bootStrapEn_sysPLLBypsEn 1 |
| #define MSK32Gbl_bootStrapEn_sysPLLBypsEn 0x00000008 |
| #define Gbl_bootStrapEn_sysPLLBypsEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_sysPLLBypsEn_DISABLE 0x0 |
| #define BA_Gbl_bootStrapEn_memPLLBypsEn 0x0010 |
| #define B16Gbl_bootStrapEn_memPLLBypsEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_memPLLBypsEn 4 |
| #define LSb16Gbl_bootStrapEn_memPLLBypsEn 4 |
| #define bGbl_bootStrapEn_memPLLBypsEn 1 |
| #define MSK32Gbl_bootStrapEn_memPLLBypsEn 0x00000010 |
| #define Gbl_bootStrapEn_memPLLBypsEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_memPLLBypsEn_DISABLE 0x0 |
| #define BA_Gbl_bootStrapEn_cpuPLLBypsEn 0x0010 |
| #define B16Gbl_bootStrapEn_cpuPLLBypsEn 0x0010 |
| #define LSb32Gbl_bootStrapEn_cpuPLLBypsEn 5 |
| #define LSb16Gbl_bootStrapEn_cpuPLLBypsEn 5 |
| #define bGbl_bootStrapEn_cpuPLLBypsEn 1 |
| #define MSK32Gbl_bootStrapEn_cpuPLLBypsEn 0x00000020 |
| #define Gbl_bootStrapEn_cpuPLLBypsEn_ENABLE 0x1 |
| #define Gbl_bootStrapEn_cpuPLLBypsEn_DISABLE 0x0 |
| #define RA_Gbl_chipCntl 0x0014 |
| #define BA_Gbl_chipCntl_SD0_CLK_LPBK_EN 0x0014 |
| #define B16Gbl_chipCntl_SD0_CLK_LPBK_EN 0x0014 |
| #define LSb32Gbl_chipCntl_SD0_CLK_LPBK_EN 0 |
| #define LSb16Gbl_chipCntl_SD0_CLK_LPBK_EN 0 |
| #define bGbl_chipCntl_SD0_CLK_LPBK_EN 1 |
| #define MSK32Gbl_chipCntl_SD0_CLK_LPBK_EN 0x00000001 |
| #define BA_Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x0014 |
| #define B16Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x0014 |
| #define LSb32Gbl_chipCntl_EMMC_CLK_LPBK_EN 1 |
| #define LSb16Gbl_chipCntl_EMMC_CLK_LPBK_EN 1 |
| #define bGbl_chipCntl_EMMC_CLK_LPBK_EN 1 |
| #define MSK32Gbl_chipCntl_EMMC_CLK_LPBK_EN 0x00000002 |
| #define BA_Gbl_chipCntl_FE_MDIO_SEL 0x0014 |
| #define B16Gbl_chipCntl_FE_MDIO_SEL 0x0014 |
| #define LSb32Gbl_chipCntl_FE_MDIO_SEL 2 |
| #define LSb16Gbl_chipCntl_FE_MDIO_SEL 2 |
| #define bGbl_chipCntl_FE_MDIO_SEL 1 |
| #define MSK32Gbl_chipCntl_FE_MDIO_SEL 0x00000004 |
| #define BA_Gbl_chipCntl_eth1_PHY_SEL 0x0014 |
| #define B16Gbl_chipCntl_eth1_PHY_SEL 0x0014 |
| #define LSb32Gbl_chipCntl_eth1_PHY_SEL 3 |
| #define LSb16Gbl_chipCntl_eth1_PHY_SEL 3 |
| #define bGbl_chipCntl_eth1_PHY_SEL 1 |
| #define MSK32Gbl_chipCntl_eth1_PHY_SEL 0x00000008 |
| #define RA_Gbl_sw_generic0 0x0018 |
| #define BA_Gbl_sw_generic0_swReg0 0x0018 |
| #define B16Gbl_sw_generic0_swReg0 0x0018 |
| #define LSb32Gbl_sw_generic0_swReg0 0 |
| #define LSb16Gbl_sw_generic0_swReg0 0 |
| #define bGbl_sw_generic0_swReg0 32 |
| #define MSK32Gbl_sw_generic0_swReg0 0xFFFFFFFF |
| #define RA_Gbl_sw_generic1 0x001C |
| #define BA_Gbl_sw_generic1_swReg1 0x001C |
| #define B16Gbl_sw_generic1_swReg1 0x001C |
| #define LSb32Gbl_sw_generic1_swReg1 0 |
| #define LSb16Gbl_sw_generic1_swReg1 0 |
| #define bGbl_sw_generic1_swReg1 32 |
| #define MSK32Gbl_sw_generic1_swReg1 0xFFFFFFFF |
| #define RA_Gbl_sw_generic2 0x0020 |
| #define BA_Gbl_sw_generic2_swReg2 0x0020 |
| #define B16Gbl_sw_generic2_swReg2 0x0020 |
| #define LSb32Gbl_sw_generic2_swReg2 0 |
| #define LSb16Gbl_sw_generic2_swReg2 0 |
| #define bGbl_sw_generic2_swReg2 32 |
| #define MSK32Gbl_sw_generic2_swReg2 0xFFFFFFFF |
| #define RA_Gbl_sw_generic3 0x0024 |
| #define BA_Gbl_sw_generic3_swReg3 0x0024 |
| #define B16Gbl_sw_generic3_swReg3 0x0024 |
| #define LSb32Gbl_sw_generic3_swReg3 0 |
| #define LSb16Gbl_sw_generic3_swReg3 0 |
| #define bGbl_sw_generic3_swReg3 32 |
| #define MSK32Gbl_sw_generic3_swReg3 0xFFFFFFFF |
| #define RA_Gbl_RWTC_gfx3D31to0 0x0028 |
| #define BA_Gbl_RWTC_gfx3D31to0_value 0x0028 |
| #define B16Gbl_RWTC_gfx3D31to0_value 0x0028 |
| #define LSb32Gbl_RWTC_gfx3D31to0_value 0 |
| #define LSb16Gbl_RWTC_gfx3D31to0_value 0 |
| #define bGbl_RWTC_gfx3D31to0_value 32 |
| #define MSK32Gbl_RWTC_gfx3D31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_gfx3D57to32 0x002C |
| #define BA_Gbl_RWTC_gfx3D57to32_value 0x002C |
| #define B16Gbl_RWTC_gfx3D57to32_value 0x002C |
| #define LSb32Gbl_RWTC_gfx3D57to32_value 0 |
| #define LSb16Gbl_RWTC_gfx3D57to32_value 0 |
| #define bGbl_RWTC_gfx3D57to32_value 26 |
| #define MSK32Gbl_RWTC_gfx3D57to32_value 0x03FFFFFF |
| #define RA_Gbl_RWTC_top31to0 0x0030 |
| #define BA_Gbl_RWTC_top31to0_value 0x0030 |
| #define B16Gbl_RWTC_top31to0_value 0x0030 |
| #define LSb32Gbl_RWTC_top31to0_value 0 |
| #define LSb16Gbl_RWTC_top31to0_value 0 |
| #define bGbl_RWTC_top31to0_value 32 |
| #define MSK32Gbl_RWTC_top31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_top57to32 0x0034 |
| #define BA_Gbl_RWTC_top57to32_value 0x0034 |
| #define B16Gbl_RWTC_top57to32_value 0x0034 |
| #define LSb32Gbl_RWTC_top57to32_value 0 |
| #define LSb16Gbl_RWTC_top57to32_value 0 |
| #define bGbl_RWTC_top57to32_value 26 |
| #define MSK32Gbl_RWTC_top57to32_value 0x03FFFFFF |
| #define RA_Gbl_RWTC_vPro31to0 0x0038 |
| #define BA_Gbl_RWTC_vPro31to0_value 0x0038 |
| #define B16Gbl_RWTC_vPro31to0_value 0x0038 |
| #define LSb32Gbl_RWTC_vPro31to0_value 0 |
| #define LSb16Gbl_RWTC_vPro31to0_value 0 |
| #define bGbl_RWTC_vPro31to0_value 32 |
| #define MSK32Gbl_RWTC_vPro31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_vPro57to32 0x003C |
| #define BA_Gbl_RWTC_vPro57to32_value 0x003C |
| #define B16Gbl_RWTC_vPro57to32_value 0x003C |
| #define LSb32Gbl_RWTC_vPro57to32_value 0 |
| #define LSb16Gbl_RWTC_vPro57to32_value 0 |
| #define bGbl_RWTC_vPro57to32_value 26 |
| #define MSK32Gbl_RWTC_vPro57to32_value 0x03FFFFFF |
| #define RA_Gbl_RWTC_g1Wrap31to0 0x0040 |
| #define BA_Gbl_RWTC_g1Wrap31to0_value 0x0040 |
| #define B16Gbl_RWTC_g1Wrap31to0_value 0x0040 |
| #define LSb32Gbl_RWTC_g1Wrap31to0_value 0 |
| #define LSb16Gbl_RWTC_g1Wrap31to0_value 0 |
| #define bGbl_RWTC_g1Wrap31to0_value 32 |
| #define MSK32Gbl_RWTC_g1Wrap31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_g1Wrap57to32 0x0044 |
| #define BA_Gbl_RWTC_g1Wrap57to32_value 0x0044 |
| #define B16Gbl_RWTC_g1Wrap57to32_value 0x0044 |
| #define LSb32Gbl_RWTC_g1Wrap57to32_value 0 |
| #define LSb16Gbl_RWTC_g1Wrap57to32_value 0 |
| #define bGbl_RWTC_g1Wrap57to32_value 26 |
| #define MSK32Gbl_RWTC_g1Wrap57to32_value 0x03FFFFFF |
| #define RA_Gbl_RWTC_mr7to0 0x0048 |
| #define BA_Gbl_RWTC_mr7to0_value 0x0048 |
| #define B16Gbl_RWTC_mr7to0_value 0x0048 |
| #define LSb32Gbl_RWTC_mr7to0_value 0 |
| #define LSb16Gbl_RWTC_mr7to0_value 0 |
| #define bGbl_RWTC_mr7to0_value 8 |
| #define MSK32Gbl_RWTC_mr7to0_value 0x000000FF |
| #define RA_Gbl_FPGAR 0x004C |
| #define BA_Gbl_FPGAR_FPGAR 0x004C |
| #define B16Gbl_FPGAR_FPGAR 0x004C |
| #define LSb32Gbl_FPGAR_FPGAR 0 |
| #define LSb16Gbl_FPGAR_FPGAR 0 |
| #define bGbl_FPGAR_FPGAR 32 |
| #define MSK32Gbl_FPGAR_FPGAR 0xFFFFFFFF |
| #define RA_Gbl_FPGARW 0x0050 |
| #define BA_Gbl_FPGARW_FPGARW 0x0050 |
| #define B16Gbl_FPGARW_FPGARW 0x0050 |
| #define LSb32Gbl_FPGARW_FPGARW 0 |
| #define LSb16Gbl_FPGARW_FPGARW 0 |
| #define bGbl_FPGARW_FPGARW 32 |
| #define MSK32Gbl_FPGARW_FPGARW 0xFFFFFFFF |
| #define RA_Gbl_sysPll 0x0200 |
| #define RA_Gbl_AVPLLB 0x0300 |
| #define RA_Gbl_ResetTrigger 0x0600 |
| #define BA_Gbl_ResetTrigger_chipReset 0x0600 |
| #define B16Gbl_ResetTrigger_chipReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_chipReset 0 |
| #define LSb16Gbl_ResetTrigger_chipReset 0 |
| #define bGbl_ResetTrigger_chipReset 1 |
| #define MSK32Gbl_ResetTrigger_chipReset 0x00000001 |
| #define Gbl_ResetTrigger_chipReset_assert 0x1 |
| #define Gbl_ResetTrigger_chipReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_socDdrSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_socDdrSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_socDdrSyncReset 1 |
| #define LSb16Gbl_ResetTrigger_socDdrSyncReset 1 |
| #define bGbl_ResetTrigger_socDdrSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_socDdrSyncReset 0x00000002 |
| #define Gbl_ResetTrigger_socDdrSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_socDdrSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_avioSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_avioSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_avioSyncReset 2 |
| #define LSb16Gbl_ResetTrigger_avioSyncReset 2 |
| #define bGbl_ResetTrigger_avioSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_avioSyncReset 0x00000004 |
| #define Gbl_ResetTrigger_avioSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_avioSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_zspSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_zspSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_zspSyncReset 3 |
| #define LSb16Gbl_ResetTrigger_zspSyncReset 3 |
| #define bGbl_ResetTrigger_zspSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_zspSyncReset 0x00000008 |
| #define Gbl_ResetTrigger_zspSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_zspSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_perifSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_perifSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_perifSyncReset 4 |
| #define LSb16Gbl_ResetTrigger_perifSyncReset 4 |
| #define bGbl_ResetTrigger_perifSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_perifSyncReset 0x00000010 |
| #define Gbl_ResetTrigger_perifSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_perifSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_ethSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_ethSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_ethSyncReset 5 |
| #define LSb16Gbl_ResetTrigger_ethSyncReset 5 |
| #define bGbl_ResetTrigger_ethSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_ethSyncReset 0x00000020 |
| #define Gbl_ResetTrigger_ethSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_ethSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_ahbApbSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_ahbApbSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_ahbApbSyncReset 6 |
| #define LSb16Gbl_ResetTrigger_ahbApbSyncReset 6 |
| #define bGbl_ResetTrigger_ahbApbSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_ahbApbSyncReset 0x00000040 |
| #define Gbl_ResetTrigger_ahbApbSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_ahbApbSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_nanfSyncReset 0x0600 |
| #define B16Gbl_ResetTrigger_nanfSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_nanfSyncReset 7 |
| #define LSb16Gbl_ResetTrigger_nanfSyncReset 7 |
| #define bGbl_ResetTrigger_nanfSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_nanfSyncReset 0x00000080 |
| #define Gbl_ResetTrigger_nanfSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_nanfSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_usb0SyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_usb0SyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_usb0SyncReset 8 |
| #define LSb16Gbl_ResetTrigger_usb0SyncReset 8 |
| #define bGbl_ResetTrigger_usb0SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_usb0SyncReset 0x00000100 |
| #define Gbl_ResetTrigger_usb0SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_usb0SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_pBridgeSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_pBridgeSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_pBridgeSyncReset 9 |
| #define LSb16Gbl_ResetTrigger_pBridgeSyncReset 9 |
| #define bGbl_ResetTrigger_pBridgeSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_pBridgeSyncReset 0x00000200 |
| #define Gbl_ResetTrigger_pBridgeSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_pBridgeSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_sdioSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_sdioSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_sdioSyncReset 10 |
| #define LSb16Gbl_ResetTrigger_sdioSyncReset 10 |
| #define bGbl_ResetTrigger_sdioSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_sdioSyncReset 0x00000400 |
| #define Gbl_ResetTrigger_sdioSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_sdioSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_tspSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_tspSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_tspSyncReset 11 |
| #define LSb16Gbl_ResetTrigger_tspSyncReset 11 |
| #define bGbl_ResetTrigger_tspSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_tspSyncReset 0x00000800 |
| #define Gbl_ResetTrigger_tspSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_tspSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_v2gSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_v2gSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_v2gSyncReset 12 |
| #define LSb16Gbl_ResetTrigger_v2gSyncReset 12 |
| #define bGbl_ResetTrigger_v2gSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_v2gSyncReset 0x00001000 |
| #define Gbl_ResetTrigger_v2gSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_v2gSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_g1SyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_g1SyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_g1SyncReset 13 |
| #define LSb16Gbl_ResetTrigger_g1SyncReset 13 |
| #define bGbl_ResetTrigger_g1SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_g1SyncReset 0x00002000 |
| #define Gbl_ResetTrigger_g1SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_g1SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_bcmSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_bcmSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_bcmSyncReset 14 |
| #define LSb16Gbl_ResetTrigger_bcmSyncReset 14 |
| #define bGbl_ResetTrigger_bcmSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_bcmSyncReset 0x00004000 |
| #define Gbl_ResetTrigger_bcmSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_bcmSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_atbSyncReset 0x0601 |
| #define B16Gbl_ResetTrigger_atbSyncReset 0x0600 |
| #define LSb32Gbl_ResetTrigger_atbSyncReset 15 |
| #define LSb16Gbl_ResetTrigger_atbSyncReset 15 |
| #define bGbl_ResetTrigger_atbSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_atbSyncReset 0x00008000 |
| #define Gbl_ResetTrigger_atbSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_atbSyncReset_deassert 0x0 |
| #define RA_Gbl_ResetStatus 0x0604 |
| #define BA_Gbl_ResetStatus_ChipResetStatus 0x0604 |
| #define B16Gbl_ResetStatus_ChipResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_ChipResetStatus 0 |
| #define LSb16Gbl_ResetStatus_ChipResetStatus 0 |
| #define bGbl_ResetStatus_ChipResetStatus 1 |
| #define MSK32Gbl_ResetStatus_ChipResetStatus 0x00000001 |
| #define Gbl_ResetStatus_ChipResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_ChipResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd0Status 0x0604 |
| #define B16Gbl_ResetStatus_wd0Status 0x0604 |
| #define LSb32Gbl_ResetStatus_wd0Status 1 |
| #define LSb16Gbl_ResetStatus_wd0Status 1 |
| #define bGbl_ResetStatus_wd0Status 1 |
| #define MSK32Gbl_ResetStatus_wd0Status 0x00000002 |
| #define Gbl_ResetStatus_wd0Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd0Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd1Status 0x0604 |
| #define B16Gbl_ResetStatus_wd1Status 0x0604 |
| #define LSb32Gbl_ResetStatus_wd1Status 2 |
| #define LSb16Gbl_ResetStatus_wd1Status 2 |
| #define bGbl_ResetStatus_wd1Status 1 |
| #define MSK32Gbl_ResetStatus_wd1Status 0x00000004 |
| #define Gbl_ResetStatus_wd1Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd1Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd2Status 0x0604 |
| #define B16Gbl_ResetStatus_wd2Status 0x0604 |
| #define LSb32Gbl_ResetStatus_wd2Status 3 |
| #define LSb16Gbl_ResetStatus_wd2Status 3 |
| #define bGbl_ResetStatus_wd2Status 1 |
| #define MSK32Gbl_ResetStatus_wd2Status 0x00000008 |
| #define Gbl_ResetStatus_wd2Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd2Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_socDdrSyncResetStatus 0x0604 |
| #define B16Gbl_ResetStatus_socDdrSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_socDdrSyncResetStatus 4 |
| #define LSb16Gbl_ResetStatus_socDdrSyncResetStatus 4 |
| #define bGbl_ResetStatus_socDdrSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_socDdrSyncResetStatus 0x00000010 |
| #define Gbl_ResetStatus_socDdrSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_socDdrSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_avioSyncResetStatus 0x0604 |
| #define B16Gbl_ResetStatus_avioSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_avioSyncResetStatus 5 |
| #define LSb16Gbl_ResetStatus_avioSyncResetStatus 5 |
| #define bGbl_ResetStatus_avioSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_avioSyncResetStatus 0x00000020 |
| #define Gbl_ResetStatus_avioSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_avioSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_zspSyncResetStatus 0x0604 |
| #define B16Gbl_ResetStatus_zspSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_zspSyncResetStatus 6 |
| #define LSb16Gbl_ResetStatus_zspSyncResetStatus 6 |
| #define bGbl_ResetStatus_zspSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_zspSyncResetStatus 0x00000040 |
| #define Gbl_ResetStatus_zspSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_zspSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_perifSyncResetStatus 0x0604 |
| #define B16Gbl_ResetStatus_perifSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_perifSyncResetStatus 7 |
| #define LSb16Gbl_ResetStatus_perifSyncResetStatus 7 |
| #define bGbl_ResetStatus_perifSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_perifSyncResetStatus 0x00000080 |
| #define Gbl_ResetStatus_perifSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_perifSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_ethSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_ethSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_ethSyncResetStatus 8 |
| #define LSb16Gbl_ResetStatus_ethSyncResetStatus 8 |
| #define bGbl_ResetStatus_ethSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_ethSyncResetStatus 0x00000100 |
| #define Gbl_ResetStatus_ethSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_ethSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_ahbApbSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_ahbApbSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_ahbApbSyncResetStatus 9 |
| #define LSb16Gbl_ResetStatus_ahbApbSyncResetStatus 9 |
| #define bGbl_ResetStatus_ahbApbSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_ahbApbSyncResetStatus 0x00000200 |
| #define Gbl_ResetStatus_ahbApbSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_ahbApbSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_nanfSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_nanfSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_nanfSyncResetStatus 10 |
| #define LSb16Gbl_ResetStatus_nanfSyncResetStatus 10 |
| #define bGbl_ResetStatus_nanfSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_nanfSyncResetStatus 0x00000400 |
| #define Gbl_ResetStatus_nanfSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_nanfSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_usb0SyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_usb0SyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_usb0SyncResetStatus 11 |
| #define LSb16Gbl_ResetStatus_usb0SyncResetStatus 11 |
| #define bGbl_ResetStatus_usb0SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_usb0SyncResetStatus 0x00000800 |
| #define Gbl_ResetStatus_usb0SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_usb0SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_pBridgeSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_pBridgeSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_pBridgeSyncResetStatus 12 |
| #define LSb16Gbl_ResetStatus_pBridgeSyncResetStatus 12 |
| #define bGbl_ResetStatus_pBridgeSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_pBridgeSyncResetStatus 0x00001000 |
| #define Gbl_ResetStatus_pBridgeSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_pBridgeSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_sdioSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_sdioSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_sdioSyncResetStatus 13 |
| #define LSb16Gbl_ResetStatus_sdioSyncResetStatus 13 |
| #define bGbl_ResetStatus_sdioSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_sdioSyncResetStatus 0x00002000 |
| #define Gbl_ResetStatus_sdioSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_sdioSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_tspSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_tspSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_tspSyncResetStatus 14 |
| #define LSb16Gbl_ResetStatus_tspSyncResetStatus 14 |
| #define bGbl_ResetStatus_tspSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_tspSyncResetStatus 0x00004000 |
| #define Gbl_ResetStatus_tspSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_tspSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_v2gSyncResetStatus 0x0605 |
| #define B16Gbl_ResetStatus_v2gSyncResetStatus 0x0604 |
| #define LSb32Gbl_ResetStatus_v2gSyncResetStatus 15 |
| #define LSb16Gbl_ResetStatus_v2gSyncResetStatus 15 |
| #define bGbl_ResetStatus_v2gSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_v2gSyncResetStatus 0x00008000 |
| #define Gbl_ResetStatus_v2gSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_v2gSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_g1SyncResetStatus 0x0606 |
| #define B16Gbl_ResetStatus_g1SyncResetStatus 0x0606 |
| #define LSb32Gbl_ResetStatus_g1SyncResetStatus 16 |
| #define LSb16Gbl_ResetStatus_g1SyncResetStatus 0 |
| #define bGbl_ResetStatus_g1SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_g1SyncResetStatus 0x00010000 |
| #define Gbl_ResetStatus_g1SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_g1SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_bcmSyncResetStatus 0x0606 |
| #define B16Gbl_ResetStatus_bcmSyncResetStatus 0x0606 |
| #define LSb32Gbl_ResetStatus_bcmSyncResetStatus 17 |
| #define LSb16Gbl_ResetStatus_bcmSyncResetStatus 1 |
| #define bGbl_ResetStatus_bcmSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_bcmSyncResetStatus 0x00020000 |
| #define Gbl_ResetStatus_bcmSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_bcmSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_atbSyncResetStatus 0x0606 |
| #define B16Gbl_ResetStatus_atbSyncResetStatus 0x0606 |
| #define LSb32Gbl_ResetStatus_atbSyncResetStatus 18 |
| #define LSb16Gbl_ResetStatus_atbSyncResetStatus 2 |
| #define bGbl_ResetStatus_atbSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_atbSyncResetStatus 0x00040000 |
| #define Gbl_ResetStatus_atbSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_atbSyncResetStatus_deasserted 0x0 |
| #define RA_Gbl_gfx3DReset 0x0608 |
| #define BA_Gbl_gfx3DReset_SyncReset 0x0608 |
| #define B16Gbl_gfx3DReset_SyncReset 0x0608 |
| #define LSb32Gbl_gfx3DReset_SyncReset 0 |
| #define LSb16Gbl_gfx3DReset_SyncReset 0 |
| #define bGbl_gfx3DReset_SyncReset 1 |
| #define MSK32Gbl_gfx3DReset_SyncReset 0x00000001 |
| #define Gbl_gfx3DReset_SyncReset_assert 0x1 |
| #define Gbl_gfx3DReset_SyncReset_deassert 0x0 |
| #define RA_Gbl_gfx3DResetStatus 0x060C |
| #define BA_Gbl_gfx3DResetStatus_SyncReset 0x060C |
| #define B16Gbl_gfx3DResetStatus_SyncReset 0x060C |
| #define LSb32Gbl_gfx3DResetStatus_SyncReset 0 |
| #define LSb16Gbl_gfx3DResetStatus_SyncReset 0 |
| #define bGbl_gfx3DResetStatus_SyncReset 1 |
| #define MSK32Gbl_gfx3DResetStatus_SyncReset 0x00000001 |
| #define Gbl_gfx3DResetStatus_SyncReset_assert 0x1 |
| #define Gbl_gfx3DResetStatus_SyncReset_deassert 0x0 |
| #define RA_Gbl_avioPwrCtrl 0x0610 |
| #define RA_Gbl_gfx3DPwrCtrl 0x0618 |
| #define RA_Gbl_g1PwrCtrl 0x0620 |
| #define RA_Gbl_v2gPwrCtrl 0x0628 |
| #define RA_Gbl_clkEnable 0x0630 |
| #define BA_Gbl_clkEnable_ethCoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_ethCoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_ethCoreClkEn 0 |
| #define LSb16Gbl_clkEnable_ethCoreClkEn 0 |
| #define bGbl_clkEnable_ethCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_ethCoreClkEn 0x00000001 |
| #define Gbl_clkEnable_ethCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_ethCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_ahbApbCoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_ahbApbCoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_ahbApbCoreClkEn 1 |
| #define LSb16Gbl_clkEnable_ahbApbCoreClkEn 1 |
| #define bGbl_clkEnable_ahbApbCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_ahbApbCoreClkEn 0x00000002 |
| #define Gbl_clkEnable_ahbApbCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_ahbApbCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_usb0CoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_usb0CoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_usb0CoreClkEn 2 |
| #define LSb16Gbl_clkEnable_usb0CoreClkEn 2 |
| #define bGbl_clkEnable_usb0CoreClkEn 1 |
| #define MSK32Gbl_clkEnable_usb0CoreClkEn 0x00000004 |
| #define Gbl_clkEnable_usb0CoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_usb0CoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_pBridgeCoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_pBridgeCoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_pBridgeCoreClkEn 3 |
| #define LSb16Gbl_clkEnable_pBridgeCoreClkEn 3 |
| #define bGbl_clkEnable_pBridgeCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_pBridgeCoreClkEn 0x00000008 |
| #define Gbl_clkEnable_pBridgeCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_pBridgeCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_sdioCoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_sdioCoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_sdioCoreClkEn 4 |
| #define LSb16Gbl_clkEnable_sdioCoreClkEn 4 |
| #define bGbl_clkEnable_sdioCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_sdioCoreClkEn 0x00000010 |
| #define Gbl_clkEnable_sdioCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_sdioCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_nfcCoreClkEn 0x0630 |
| #define B16Gbl_clkEnable_nfcCoreClkEn 0x0630 |
| #define LSb32Gbl_clkEnable_nfcCoreClkEn 5 |
| #define LSb16Gbl_clkEnable_nfcCoreClkEn 5 |
| #define bGbl_clkEnable_nfcCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_nfcCoreClkEn 0x00000020 |
| #define Gbl_clkEnable_nfcCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_nfcCoreClkEn_disable 0x0 |
| #define RA_Gbl_ClkSwitch 0x0634 |
| #define BA_Gbl_ClkSwitch_sysPLLSWBypass 0x0634 |
| #define B16Gbl_ClkSwitch_sysPLLSWBypass 0x0634 |
| #define LSb32Gbl_ClkSwitch_sysPLLSWBypass 0 |
| #define LSb16Gbl_ClkSwitch_sysPLLSWBypass 0 |
| #define bGbl_ClkSwitch_sysPLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_sysPLLSWBypass 0x00000001 |
| #define Gbl_ClkSwitch_sysPLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_sysPLLSWBypass_pllClk 0x0 |
| #define BA_Gbl_ClkSwitch_memPLLSWBypass 0x0634 |
| #define B16Gbl_ClkSwitch_memPLLSWBypass 0x0634 |
| #define LSb32Gbl_ClkSwitch_memPLLSWBypass 1 |
| #define LSb16Gbl_ClkSwitch_memPLLSWBypass 1 |
| #define bGbl_ClkSwitch_memPLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_memPLLSWBypass 0x00000002 |
| #define Gbl_ClkSwitch_memPLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_memPLLSWBypass_pllClk 0x0 |
| #define BA_Gbl_ClkSwitch_cpuPLLSWBypass 0x0634 |
| #define B16Gbl_ClkSwitch_cpuPLLSWBypass 0x0634 |
| #define LSb32Gbl_ClkSwitch_cpuPLLSWBypass 2 |
| #define LSb16Gbl_ClkSwitch_cpuPLLSWBypass 2 |
| #define bGbl_ClkSwitch_cpuPLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_cpuPLLSWBypass 0x00000004 |
| #define Gbl_ClkSwitch_cpuPLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_cpuPLLSWBypass_pllClk 0x0 |
| #define RA_Gbl_cpufastRefClk 0x0638 |
| #define RA_Gbl_memfastRefClk 0x063C |
| #define RA_Gbl_cfgClk 0x0640 |
| #define RA_Gbl_sysClk 0x0644 |
| #define RA_Gbl_v2gClk 0x0648 |
| #define RA_Gbl_v2gM3Clk 0x064C |
| #define RA_Gbl_g1CoreClk 0x0650 |
| #define RA_Gbl_gfx3DCoreClk 0x0654 |
| #define RA_Gbl_gfx3DSysClk 0x0658 |
| #define RA_Gbl_avioSysClk 0x065C |
| #define RA_Gbl_appClk 0x0660 |
| #define RA_Gbl_vppSysClk 0x0664 |
| #define RA_Gbl_arcRefClk 0x0668 |
| #define RA_Gbl_hdmirxMClk 0x066C |
| #define RA_Gbl_perifClk 0x0670 |
| #define RA_Gbl_zspClk 0x0674 |
| #define RA_Gbl_tspClk 0x0678 |
| #define RA_Gbl_tspRefClk 0x067C |
| #define RA_Gbl_atbClk 0x0680 |
| #define RA_Gbl_bcmClk 0x0684 |
| #define RA_Gbl_nfcEccClk 0x0688 |
| #define RA_Gbl_sd0Clk 0x068C |
| #define RA_Gbl_usb2TestClk 0x0690 |
| #define RA_Gbl_sdio3DllMstRefClk 0x0694 |
| #define RA_Gbl_SECURE_SCAN_EN 0x0900 |
| #define BA_Gbl_SECURE_SCAN_EN_SET 0x0900 |
| #define B16Gbl_SECURE_SCAN_EN_SET 0x0900 |
| #define LSb32Gbl_SECURE_SCAN_EN_SET 0 |
| #define LSb16Gbl_SECURE_SCAN_EN_SET 0 |
| #define bGbl_SECURE_SCAN_EN_SET 1 |
| #define MSK32Gbl_SECURE_SCAN_EN_SET 0x00000001 |
| #define RA_Gbl_NandCtrl 0x0904 |
| #define BA_Gbl_NandCtrl_NAND_WPn_Sel 0x0904 |
| #define B16Gbl_NandCtrl_NAND_WPn_Sel 0x0904 |
| #define LSb32Gbl_NandCtrl_NAND_WPn_Sel 0 |
| #define LSb16Gbl_NandCtrl_NAND_WPn_Sel 0 |
| #define bGbl_NandCtrl_NAND_WPn_Sel 1 |
| #define MSK32Gbl_NandCtrl_NAND_WPn_Sel 0x00000001 |
| #define BA_Gbl_NandCtrl_NAND_CLE_OE 0x0904 |
| #define B16Gbl_NandCtrl_NAND_CLE_OE 0x0904 |
| #define LSb32Gbl_NandCtrl_NAND_CLE_OE 1 |
| #define LSb16Gbl_NandCtrl_NAND_CLE_OE 1 |
| #define bGbl_NandCtrl_NAND_CLE_OE 1 |
| #define MSK32Gbl_NandCtrl_NAND_CLE_OE 0x00000002 |
| #define BA_Gbl_NandCtrl_NAND_ALE_OE 0x0904 |
| #define B16Gbl_NandCtrl_NAND_ALE_OE 0x0904 |
| #define LSb32Gbl_NandCtrl_NAND_ALE_OE 2 |
| #define LSb16Gbl_NandCtrl_NAND_ALE_OE 2 |
| #define bGbl_NandCtrl_NAND_ALE_OE 1 |
| #define MSK32Gbl_NandCtrl_NAND_ALE_OE 0x00000004 |
| #define RA_Gbl_sdioDllMstCtrl 0x0908 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL1 0x0908 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL1 0x0908 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL1 0 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL1 0 |
| #define bGbl_sdioDllMstCtrl_PH_SEL1 6 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL1 0x0000003F |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL2 0x0908 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL2 0x0908 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL2 6 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL2 6 |
| #define bGbl_sdioDllMstCtrl_PH_SEL2 6 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL2 0x00000FC0 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL3 0x0909 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL3 0x0908 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL3 12 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL3 12 |
| #define bGbl_sdioDllMstCtrl_PH_SEL3 6 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL3 0x0003F000 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL4 0x090A |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL4 0x090A |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL4 18 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL4 2 |
| #define bGbl_sdioDllMstCtrl_PH_SEL4 6 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL4 0x00FC0000 |
| #define BA_Gbl_sdioDllMstCtrl_RESET 0x090B |
| #define B16Gbl_sdioDllMstCtrl_RESET 0x090A |
| #define LSb32Gbl_sdioDllMstCtrl_RESET 24 |
| #define LSb16Gbl_sdioDllMstCtrl_RESET 8 |
| #define bGbl_sdioDllMstCtrl_RESET 1 |
| #define MSK32Gbl_sdioDllMstCtrl_RESET 0x01000000 |
| #define BA_Gbl_sdioDllMstCtrl_GAIN2X 0x090B |
| #define B16Gbl_sdioDllMstCtrl_GAIN2X 0x090A |
| #define LSb32Gbl_sdioDllMstCtrl_GAIN2X 25 |
| #define LSb16Gbl_sdioDllMstCtrl_GAIN2X 9 |
| #define bGbl_sdioDllMstCtrl_GAIN2X 1 |
| #define MSK32Gbl_sdioDllMstCtrl_GAIN2X 0x02000000 |
| #define BA_Gbl_sdioDllMstCtrl_TEST_EN 0x090B |
| #define B16Gbl_sdioDllMstCtrl_TEST_EN 0x090A |
| #define LSb32Gbl_sdioDllMstCtrl_TEST_EN 26 |
| #define LSb16Gbl_sdioDllMstCtrl_TEST_EN 10 |
| #define bGbl_sdioDllMstCtrl_TEST_EN 1 |
| #define MSK32Gbl_sdioDllMstCtrl_TEST_EN 0x04000000 |
| #define BA_Gbl_sdioDllMstCtrl_RESERVE 0x090B |
| #define B16Gbl_sdioDllMstCtrl_RESERVE 0x090A |
| #define LSb32Gbl_sdioDllMstCtrl_RESERVE 27 |
| #define LSb16Gbl_sdioDllMstCtrl_RESERVE 11 |
| #define bGbl_sdioDllMstCtrl_RESERVE 5 |
| #define MSK32Gbl_sdioDllMstCtrl_RESERVE 0xF8000000 |
| #define RA_Gbl_sdioDllMstCtrl1 0x090C |
| #define BA_Gbl_sdioDllMstCtrl_FAST_LOCK 0x090C |
| #define B16Gbl_sdioDllMstCtrl_FAST_LOCK 0x090C |
| #define LSb32Gbl_sdioDllMstCtrl_FAST_LOCK 0 |
| #define LSb16Gbl_sdioDllMstCtrl_FAST_LOCK 0 |
| #define bGbl_sdioDllMstCtrl_FAST_LOCK 1 |
| #define MSK32Gbl_sdioDllMstCtrl_FAST_LOCK 0x00000001 |
| #define RA_Gbl_sdioDllMstStatus 0x0910 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL1 0x0910 |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL1 0x0910 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL1 0 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL1 0 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL1 10 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL1 0x000003FF |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL2 0x0911 |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL2 0x0910 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL2 10 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL2 10 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL2 10 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL2 0x000FFC00 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL3 0x0912 |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL3 0x0912 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL3 20 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL3 4 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL3 10 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL3 0x3FF00000 |
| #define RA_Gbl_sdioDllMstStatus1 0x0914 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL4 0x0914 |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL4 0x0914 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL4 0 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL4 0 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL4 10 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL4 0x000003FF |
| #define BA_Gbl_sdioDllMstStatus_DLL_LOCK 0x0915 |
| #define B16Gbl_sdioDllMstStatus_DLL_LOCK 0x0914 |
| #define LSb32Gbl_sdioDllMstStatus_DLL_LOCK 10 |
| #define LSb16Gbl_sdioDllMstStatus_DLL_LOCK 10 |
| #define bGbl_sdioDllMstStatus_DLL_LOCK 1 |
| #define MSK32Gbl_sdioDllMstStatus_DLL_LOCK 0x00000400 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_OUT 0x0915 |
| #define B16Gbl_sdioDllMstStatus_DELAY_OUT 0x0914 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_OUT 11 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_OUT 11 |
| #define bGbl_sdioDllMstStatus_DELAY_OUT 10 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_OUT 0x001FF800 |
| #define RA_Gbl_gfx3DDisRamClkGate 0x0918 |
| #define BA_Gbl_gfx3DDisRamClkGate_drcg 0x0918 |
| #define B16Gbl_gfx3DDisRamClkGate_drcg 0x0918 |
| #define LSb32Gbl_gfx3DDisRamClkGate_drcg 0 |
| #define LSb16Gbl_gfx3DDisRamClkGate_drcg 0 |
| #define bGbl_gfx3DDisRamClkGate_drcg 1 |
| #define MSK32Gbl_gfx3DDisRamClkGate_drcg 0x00000001 |
| #define Gbl_gfx3DDisRamClkGate_drcg_drcgActive 0x1 |
| #define Gbl_gfx3DDisRamClkGate_drcg_drcgInactive 0x0 |
| #define RA_Gbl_DroEn 0x091C |
| #define BA_Gbl_DroEn_Start 0x091C |
| #define B16Gbl_DroEn_Start 0x091C |
| #define LSb32Gbl_DroEn_Start 0 |
| #define LSb16Gbl_DroEn_Start 0 |
| #define bGbl_DroEn_Start 1 |
| #define MSK32Gbl_DroEn_Start 0x00000001 |
| #define Gbl_DroEn_Start_dro_en_start 0x1 |
| #define BA_Gbl_DroEn_CountVal 0x091C |
| #define B16Gbl_DroEn_CountVal 0x091C |
| #define LSb32Gbl_DroEn_CountVal 1 |
| #define LSb16Gbl_DroEn_CountVal 1 |
| #define bGbl_DroEn_CountVal 16 |
| #define MSK32Gbl_DroEn_CountVal 0x0001FFFE |
| #define RA_Gbl_DroEn1 0x0920 |
| #define BA_Gbl_DroEn_WaitVal 0x0920 |
| #define B16Gbl_DroEn_WaitVal 0x0920 |
| #define LSb32Gbl_DroEn_WaitVal 0 |
| #define LSb16Gbl_DroEn_WaitVal 0 |
| #define bGbl_DroEn_WaitVal 16 |
| #define MSK32Gbl_DroEn_WaitVal 0x0000FFFF |
| #define RA_Gbl_DroShift 0x0924 |
| #define BA_Gbl_DroShift_Start 0x0924 |
| #define B16Gbl_DroShift_Start 0x0924 |
| #define LSb32Gbl_DroShift_Start 0 |
| #define LSb16Gbl_DroShift_Start 0 |
| #define bGbl_DroShift_Start 1 |
| #define MSK32Gbl_DroShift_Start 0x00000001 |
| #define Gbl_DroShift_Start_dro_shift_start 0x1 |
| #define BA_Gbl_DroShift_CountVal 0x0924 |
| #define B16Gbl_DroShift_CountVal 0x0924 |
| #define LSb32Gbl_DroShift_CountVal 1 |
| #define LSb16Gbl_DroShift_CountVal 1 |
| #define bGbl_DroShift_CountVal 16 |
| #define MSK32Gbl_DroShift_CountVal 0x0001FFFE |
| #define RA_Gbl_DroStatus 0x0928 |
| #define BA_Gbl_DroStatus_En 0x0928 |
| #define B16Gbl_DroStatus_En 0x0928 |
| #define LSb32Gbl_DroStatus_En 0 |
| #define LSb16Gbl_DroStatus_En 0 |
| #define bGbl_DroStatus_En 1 |
| #define MSK32Gbl_DroStatus_En 0x00000001 |
| #define BA_Gbl_DroStatus_Shift_Done 0x0928 |
| #define B16Gbl_DroStatus_Shift_Done 0x0928 |
| #define LSb32Gbl_DroStatus_Shift_Done 1 |
| #define LSb16Gbl_DroStatus_Shift_Done 1 |
| #define bGbl_DroStatus_Shift_Done 1 |
| #define MSK32Gbl_DroStatus_Shift_Done 0x00000002 |
| #define RA_Gbl_DroCounter 0x092C |
| #define BA_Gbl_DroCounter_Out 0x092C |
| #define B16Gbl_DroCounter_Out 0x092C |
| #define LSb32Gbl_DroCounter_Out 0 |
| #define LSb16Gbl_DroCounter_Out 0 |
| #define bGbl_DroCounter_Out 32 |
| #define MSK32Gbl_DroCounter_Out 0xFFFFFFFF |
| #define RA_Gbl_vtr 0x0930 |
| #define RA_Gbl_gic400_ctrl 0x0938 |
| #define BA_Gbl_gic400_ctrl_cgfsdisable 0x0938 |
| #define B16Gbl_gic400_ctrl_cgfsdisable 0x0938 |
| #define LSb32Gbl_gic400_ctrl_cgfsdisable 0 |
| #define LSb16Gbl_gic400_ctrl_cgfsdisable 0 |
| #define bGbl_gic400_ctrl_cgfsdisable 1 |
| #define MSK32Gbl_gic400_ctrl_cgfsdisable 0x00000001 |
| #define RA_Gbl_SPARE_CTRL_0 0x093C |
| #define BA_Gbl_SPARE_CTRL_0_ctrl 0x093C |
| #define B16Gbl_SPARE_CTRL_0_ctrl 0x093C |
| #define LSb32Gbl_SPARE_CTRL_0_ctrl 0 |
| #define LSb16Gbl_SPARE_CTRL_0_ctrl 0 |
| #define bGbl_SPARE_CTRL_0_ctrl 32 |
| #define MSK32Gbl_SPARE_CTRL_0_ctrl 0xFFFFFFFF |
| #define RA_Gbl_SPARE_CTRL_1 0x0940 |
| #define BA_Gbl_SPARE_CTRL_1_ctrl 0x0940 |
| #define B16Gbl_SPARE_CTRL_1_ctrl 0x0940 |
| #define LSb32Gbl_SPARE_CTRL_1_ctrl 0 |
| #define LSb16Gbl_SPARE_CTRL_1_ctrl 0 |
| #define bGbl_SPARE_CTRL_1_ctrl 32 |
| #define MSK32Gbl_SPARE_CTRL_1_ctrl 0xFFFFFFFF |
| #define RA_Gbl_SPARE_CTRL_2 0x0944 |
| #define BA_Gbl_SPARE_CTRL_2_ctrl 0x0944 |
| #define B16Gbl_SPARE_CTRL_2_ctrl 0x0944 |
| #define LSb32Gbl_SPARE_CTRL_2_ctrl 0 |
| #define LSb16Gbl_SPARE_CTRL_2_ctrl 0 |
| #define bGbl_SPARE_CTRL_2_ctrl 32 |
| #define MSK32Gbl_SPARE_CTRL_2_ctrl 0xFFFFFFFF |
| #define RA_Gbl_SPARE_CTRL_3 0x0948 |
| #define BA_Gbl_SPARE_CTRL_3_ctrl 0x0948 |
| #define B16Gbl_SPARE_CTRL_3_ctrl 0x0948 |
| #define LSb32Gbl_SPARE_CTRL_3_ctrl 0 |
| #define LSb16Gbl_SPARE_CTRL_3_ctrl 0 |
| #define bGbl_SPARE_CTRL_3_ctrl 32 |
| #define MSK32Gbl_SPARE_CTRL_3_ctrl 0xFFFFFFFF |
| #define RA_Gbl_efuse0 0x094C |
| #define RA_Gbl_efuse1 0x0978 |
| #define RA_Gbl_PERIF 0x09A4 |
| #define RA_Gbl_PadSelect 0x4000 |
| #define BA_Gbl_PadSelect_DVIO_OEN 0x4000 |
| #define B16Gbl_PadSelect_DVIO_OEN 0x4000 |
| #define LSb32Gbl_PadSelect_DVIO_OEN 0 |
| #define LSb16Gbl_PadSelect_DVIO_OEN 0 |
| #define bGbl_PadSelect_DVIO_OEN 1 |
| #define MSK32Gbl_PadSelect_DVIO_OEN 0x00000001 |
| #define Gbl_PadSelect_DVIO_OEN_Enable 0x1 |
| #define Gbl_PadSelect_DVIO_OEN_Disable 0x0 |
| #define RA_Gbl_I2C_PADRING 0x4004 |
| #define RA_Gbl_SD0_PADRING 0x400C |
| #define RA_Gbl_TSI_PADRING 0x4014 |
| #define RA_Gbl_SPI_PADRING 0x401C |
| #define RA_Gbl_NAND_PADRING 0x4024 |
| #define RA_Gbl_DDC_PAD_CTRL 0x402C |
| #define BA_Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x402C |
| #define B16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x402C |
| #define LSb32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0 |
| #define LSb16Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0 |
| #define bGbl_DDC_PAD_CTRL_ZN_TW1_SCL 3 |
| #define MSK32Gbl_DDC_PAD_CTRL_ZN_TW1_SCL 0x00000007 |
| #define BA_Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x402C |
| #define B16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x402C |
| #define LSb32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 3 |
| #define LSb16Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 3 |
| #define bGbl_DDC_PAD_CTRL_ZN_TW1_SDA 3 |
| #define MSK32Gbl_DDC_PAD_CTRL_ZN_TW1_SDA 0x00000038 |
| #define RA_Gbl_pinMuxCntlBus 0x8000 |
| #define BA_Gbl_pinMuxCntlBus_URT0_RXD 0x8000 |
| #define B16Gbl_pinMuxCntlBus_URT0_RXD 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_URT0_RXD 0 |
| #define LSb16Gbl_pinMuxCntlBus_URT0_RXD 0 |
| #define bGbl_pinMuxCntlBus_URT0_RXD 3 |
| #define MSK32Gbl_pinMuxCntlBus_URT0_RXD 0x00000007 |
| #define Gbl_pinMuxCntlBus_URT0_RXD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_URT0_RXD_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_URT0_TXD 0x8000 |
| #define B16Gbl_pinMuxCntlBus_URT0_TXD 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_URT0_TXD 3 |
| #define LSb16Gbl_pinMuxCntlBus_URT0_TXD 3 |
| #define bGbl_pinMuxCntlBus_URT0_TXD 3 |
| #define MSK32Gbl_pinMuxCntlBus_URT0_TXD 0x00000038 |
| #define Gbl_pinMuxCntlBus_URT0_TXD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_URT0_TXD_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SS0n 0x8000 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SS0n 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SS0n 6 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SS0n 6 |
| #define bGbl_pinMuxCntlBus_SPI1_SS0n 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SS0n 0x000001C0 |
| #define Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SS0n_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SS1n 0x8001 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SS1n 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SS1n 9 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SS1n 9 |
| #define bGbl_pinMuxCntlBus_SPI1_SS1n 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SS1n 0x00000E00 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SPI1_SS1n_MODE_5 0x5 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SS2n 0x8001 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SS2n 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SS2n 12 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SS2n 12 |
| #define bGbl_pinMuxCntlBus_SPI1_SS2n 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SS2n 0x00007000 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SPI1_SS2n_MODE_5 0x5 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SCLK 0x8001 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SCLK 0x8000 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SCLK 15 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SCLK 15 |
| #define bGbl_pinMuxCntlBus_SPI1_SCLK 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SCLK 0x00038000 |
| #define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SPI1_SCLK_MODE_2 0x2 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SDO 0x8002 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SDO 0x8002 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SDO 18 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SDO 2 |
| #define bGbl_pinMuxCntlBus_SPI1_SDO 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SDO 0x001C0000 |
| #define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SPI1_SDO_MODE_2 0x2 |
| #define BA_Gbl_pinMuxCntlBus_SPI1_SDI 0x8002 |
| #define B16Gbl_pinMuxCntlBus_SPI1_SDI 0x8002 |
| #define LSb32Gbl_pinMuxCntlBus_SPI1_SDI 21 |
| #define LSb16Gbl_pinMuxCntlBus_SPI1_SDI 5 |
| #define bGbl_pinMuxCntlBus_SPI1_SDI 3 |
| #define MSK32Gbl_pinMuxCntlBus_SPI1_SDI 0x00E00000 |
| #define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SPI1_SDI_MODE_2 0x2 |
| #define BA_Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x8003 |
| #define B16Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x8002 |
| #define LSb32Gbl_pinMuxCntlBus_USB1_DRV_VBUS 24 |
| #define LSb16Gbl_pinMuxCntlBus_USB1_DRV_VBUS 8 |
| #define bGbl_pinMuxCntlBus_USB1_DRV_VBUS 3 |
| #define MSK32Gbl_pinMuxCntlBus_USB1_DRV_VBUS 0x07000000 |
| #define Gbl_pinMuxCntlBus_USB1_DRV_VBUS_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_USB1_DRV_VBUS_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_TW1_SCL 0x8003 |
| #define B16Gbl_pinMuxCntlBus_TW1_SCL 0x8002 |
| #define LSb32Gbl_pinMuxCntlBus_TW1_SCL 27 |
| #define LSb16Gbl_pinMuxCntlBus_TW1_SCL 11 |
| #define bGbl_pinMuxCntlBus_TW1_SCL 3 |
| #define MSK32Gbl_pinMuxCntlBus_TW1_SCL 0x38000000 |
| #define Gbl_pinMuxCntlBus_TW1_SCL_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_TW1_SCL_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_TW1_SCL_MODE_2 0x2 |
| #define RA_Gbl_pinMuxCntlBus1 0x8004 |
| #define BA_Gbl_pinMuxCntlBus_TW1_SDA 0x8004 |
| #define B16Gbl_pinMuxCntlBus_TW1_SDA 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_TW1_SDA 0 |
| #define LSb16Gbl_pinMuxCntlBus_TW1_SDA 0 |
| #define bGbl_pinMuxCntlBus_TW1_SDA 3 |
| #define MSK32Gbl_pinMuxCntlBus_TW1_SDA 0x00000007 |
| #define Gbl_pinMuxCntlBus_TW1_SDA_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_TW1_SDA_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_TW1_SDA_MODE_2 0x2 |
| #define BA_Gbl_pinMuxCntlBus_HDMI_CEC 0x8004 |
| #define B16Gbl_pinMuxCntlBus_HDMI_CEC 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_HDMI_CEC 3 |
| #define LSb16Gbl_pinMuxCntlBus_HDMI_CEC 3 |
| #define bGbl_pinMuxCntlBus_HDMI_CEC 3 |
| #define MSK32Gbl_pinMuxCntlBus_HDMI_CEC 0x00000038 |
| #define Gbl_pinMuxCntlBus_HDMI_CEC_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_HDMI_CEC_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_HDMI_HPD 0x8004 |
| #define B16Gbl_pinMuxCntlBus_HDMI_HPD 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_HDMI_HPD 6 |
| #define LSb16Gbl_pinMuxCntlBus_HDMI_HPD 6 |
| #define bGbl_pinMuxCntlBus_HDMI_HPD 3 |
| #define MSK32Gbl_pinMuxCntlBus_HDMI_HPD 0x000001C0 |
| #define Gbl_pinMuxCntlBus_HDMI_HPD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_HDMI_HPD_MODE_1 0x1 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO0 0x8005 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO0 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO0 9 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO0 9 |
| #define bGbl_pinMuxCntlBus_NAND_IO0 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO0 0x00000E00 |
| #define Gbl_pinMuxCntlBus_NAND_IO0_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO0_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO0_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO0_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO0_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO1 0x8005 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO1 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO1 12 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO1 12 |
| #define bGbl_pinMuxCntlBus_NAND_IO1 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO1 0x00007000 |
| #define Gbl_pinMuxCntlBus_NAND_IO1_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO1_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO1_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO1_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO1_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO2 0x8005 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO2 0x8004 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO2 15 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO2 15 |
| #define bGbl_pinMuxCntlBus_NAND_IO2 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO2 0x00038000 |
| #define Gbl_pinMuxCntlBus_NAND_IO2_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO2_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO2_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO2_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO2_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO3 0x8006 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO3 0x8006 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO3 18 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO3 2 |
| #define bGbl_pinMuxCntlBus_NAND_IO3 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO3 0x001C0000 |
| #define Gbl_pinMuxCntlBus_NAND_IO3_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO3_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO3_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO3_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO3_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO4 0x8006 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO4 0x8006 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO4 21 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO4 5 |
| #define bGbl_pinMuxCntlBus_NAND_IO4 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO4 0x00E00000 |
| #define Gbl_pinMuxCntlBus_NAND_IO4_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO4_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO4_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO4_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO4_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO5 0x8007 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO5 0x8006 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO5 24 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO5 8 |
| #define bGbl_pinMuxCntlBus_NAND_IO5 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO5 0x07000000 |
| #define Gbl_pinMuxCntlBus_NAND_IO5_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO5_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO5_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO5_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO5_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO6 0x8007 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO6 0x8006 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO6 27 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO6 11 |
| #define bGbl_pinMuxCntlBus_NAND_IO6 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO6 0x38000000 |
| #define Gbl_pinMuxCntlBus_NAND_IO6_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO6_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO6_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO6_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO6_MODE_4 0x4 |
| #define RA_Gbl_pinMuxCntlBus2 0x8008 |
| #define BA_Gbl_pinMuxCntlBus_NAND_IO7 0x8008 |
| #define B16Gbl_pinMuxCntlBus_NAND_IO7 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_IO7 0 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_IO7 0 |
| #define bGbl_pinMuxCntlBus_NAND_IO7 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_IO7 0x00000007 |
| #define Gbl_pinMuxCntlBus_NAND_IO7_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_IO7_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_IO7_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_IO7_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_IO7_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_ALE 0x8008 |
| #define B16Gbl_pinMuxCntlBus_NAND_ALE 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_ALE 3 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_ALE 3 |
| #define bGbl_pinMuxCntlBus_NAND_ALE 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_ALE 0x00000038 |
| #define Gbl_pinMuxCntlBus_NAND_ALE_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_ALE_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_ALE_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_ALE_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_NAND_ALE_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_NAND_CLE 0x8008 |
| #define B16Gbl_pinMuxCntlBus_NAND_CLE 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_CLE 6 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_CLE 6 |
| #define bGbl_pinMuxCntlBus_NAND_CLE 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_CLE 0x000001C0 |
| #define Gbl_pinMuxCntlBus_NAND_CLE_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_CLE_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_CLE_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_NAND_CLE_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_NAND_WEn 0x8009 |
| #define B16Gbl_pinMuxCntlBus_NAND_WEn 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_WEn 9 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_WEn 9 |
| #define bGbl_pinMuxCntlBus_NAND_WEn 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_WEn 0x00000E00 |
| #define Gbl_pinMuxCntlBus_NAND_WEn_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_WEn_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_WEn_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_NAND_REn 0x8009 |
| #define B16Gbl_pinMuxCntlBus_NAND_REn 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_REn 12 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_REn 12 |
| #define bGbl_pinMuxCntlBus_NAND_REn 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_REn 0x00007000 |
| #define Gbl_pinMuxCntlBus_NAND_REn_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_REn_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_REn_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_NAND_WPn 0x8009 |
| #define B16Gbl_pinMuxCntlBus_NAND_WPn 0x8008 |
| #define LSb32Gbl_pinMuxCntlBus_NAND_WPn 15 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_WPn 15 |
| #define bGbl_pinMuxCntlBus_NAND_WPn 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_WPn 0x00038000 |
| #define Gbl_pinMuxCntlBus_NAND_WPn_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_WPn_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_WPn_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_NAND_CEn 0x800A |
| #define B16Gbl_pinMuxCntlBus_NAND_CEn 0x800A |
| #define LSb32Gbl_pinMuxCntlBus_NAND_CEn 18 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_CEn 2 |
| #define bGbl_pinMuxCntlBus_NAND_CEn 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_CEn 0x001C0000 |
| #define Gbl_pinMuxCntlBus_NAND_CEn_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_CEn_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_CEn_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_NAND_RDY 0x800A |
| #define B16Gbl_pinMuxCntlBus_NAND_RDY 0x800A |
| #define LSb32Gbl_pinMuxCntlBus_NAND_RDY 21 |
| #define LSb16Gbl_pinMuxCntlBus_NAND_RDY 5 |
| #define bGbl_pinMuxCntlBus_NAND_RDY 3 |
| #define MSK32Gbl_pinMuxCntlBus_NAND_RDY 0x00E00000 |
| #define Gbl_pinMuxCntlBus_NAND_RDY_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_NAND_RDY_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_NAND_RDY_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_SD0_CLK 0x800B |
| #define B16Gbl_pinMuxCntlBus_SD0_CLK 0x800A |
| #define LSb32Gbl_pinMuxCntlBus_SD0_CLK 24 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_CLK 8 |
| #define bGbl_pinMuxCntlBus_SD0_CLK 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_CLK 0x07000000 |
| #define Gbl_pinMuxCntlBus_SD0_CLK_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_CLK_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_CLK_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_CLK_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_DAT0 0x800B |
| #define B16Gbl_pinMuxCntlBus_SD0_DAT0 0x800A |
| #define LSb32Gbl_pinMuxCntlBus_SD0_DAT0 27 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_DAT0 11 |
| #define bGbl_pinMuxCntlBus_SD0_DAT0 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_DAT0 0x38000000 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_DAT0_MODE_7 0x7 |
| #define RA_Gbl_pinMuxCntlBus3 0x800C |
| #define BA_Gbl_pinMuxCntlBus_SD0_DAT1 0x800C |
| #define B16Gbl_pinMuxCntlBus_SD0_DAT1 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_DAT1 0 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_DAT1 0 |
| #define bGbl_pinMuxCntlBus_SD0_DAT1 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_DAT1 0x00000007 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_DAT1_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_DAT2 0x800C |
| #define B16Gbl_pinMuxCntlBus_SD0_DAT2 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_DAT2 3 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_DAT2 3 |
| #define bGbl_pinMuxCntlBus_SD0_DAT2 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_DAT2 0x00000038 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_DAT2_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_DAT3 0x800C |
| #define B16Gbl_pinMuxCntlBus_SD0_DAT3 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_DAT3 6 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_DAT3 6 |
| #define bGbl_pinMuxCntlBus_SD0_DAT3 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_DAT3 0x000001C0 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_DAT3_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_CDn 0x800D |
| #define B16Gbl_pinMuxCntlBus_SD0_CDn 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_CDn 9 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_CDn 9 |
| #define bGbl_pinMuxCntlBus_SD0_CDn 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_CDn 0x00000E00 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_CDn_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_CMD 0x800D |
| #define B16Gbl_pinMuxCntlBus_SD0_CMD 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_CMD 12 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_CMD 12 |
| #define bGbl_pinMuxCntlBus_SD0_CMD 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_CMD 0x00007000 |
| #define Gbl_pinMuxCntlBus_SD0_CMD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_CMD_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_CMD_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_CMD_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_SD0_WP 0x800D |
| #define B16Gbl_pinMuxCntlBus_SD0_WP 0x800C |
| #define LSb32Gbl_pinMuxCntlBus_SD0_WP 15 |
| #define LSb16Gbl_pinMuxCntlBus_SD0_WP 15 |
| #define bGbl_pinMuxCntlBus_SD0_WP 3 |
| #define MSK32Gbl_pinMuxCntlBus_SD0_WP 0x00038000 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_3 0x3 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_4 0x4 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_5 0x5 |
| #define Gbl_pinMuxCntlBus_SD0_WP_MODE_7 0x7 |
| #define BA_Gbl_pinMuxCntlBus_STS0_CLK 0x800E |
| #define B16Gbl_pinMuxCntlBus_STS0_CLK 0x800E |
| #define LSb32Gbl_pinMuxCntlBus_STS0_CLK 18 |
| #define LSb16Gbl_pinMuxCntlBus_STS0_CLK 2 |
| #define bGbl_pinMuxCntlBus_STS0_CLK 3 |
| #define MSK32Gbl_pinMuxCntlBus_STS0_CLK 0x001C0000 |
| #define Gbl_pinMuxCntlBus_STS0_CLK_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_STS0_CLK_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_STS0_CLK_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_STS0_CLK_MODE_4 0x4 |
| #define BA_Gbl_pinMuxCntlBus_STS0_SOP 0x800E |
| #define B16Gbl_pinMuxCntlBus_STS0_SOP 0x800E |
| #define LSb32Gbl_pinMuxCntlBus_STS0_SOP 21 |
| #define LSb16Gbl_pinMuxCntlBus_STS0_SOP 5 |
| #define bGbl_pinMuxCntlBus_STS0_SOP 3 |
| #define MSK32Gbl_pinMuxCntlBus_STS0_SOP 0x00E00000 |
| #define Gbl_pinMuxCntlBus_STS0_SOP_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_STS0_SOP_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_STS0_SOP_MODE_2 0x2 |
| #define BA_Gbl_pinMuxCntlBus_STS0_VALD 0x800F |
| #define B16Gbl_pinMuxCntlBus_STS0_VALD 0x800E |
| #define LSb32Gbl_pinMuxCntlBus_STS0_VALD 24 |
| #define LSb16Gbl_pinMuxCntlBus_STS0_VALD 8 |
| #define bGbl_pinMuxCntlBus_STS0_VALD 3 |
| #define MSK32Gbl_pinMuxCntlBus_STS0_VALD 0x07000000 |
| #define Gbl_pinMuxCntlBus_STS0_VALD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_STS0_VALD_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_STS0_VALD_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_STS0_VALD_MODE_3 0x3 |
| #define BA_Gbl_pinMuxCntlBus_STS0_SD 0x800F |
| #define B16Gbl_pinMuxCntlBus_STS0_SD 0x800E |
| #define LSb32Gbl_pinMuxCntlBus_STS0_SD 27 |
| #define LSb16Gbl_pinMuxCntlBus_STS0_SD 11 |
| #define bGbl_pinMuxCntlBus_STS0_SD 3 |
| #define MSK32Gbl_pinMuxCntlBus_STS0_SD 0x38000000 |
| #define Gbl_pinMuxCntlBus_STS0_SD_MODE_0 0x0 |
| #define Gbl_pinMuxCntlBus_STS0_SD_MODE_1 0x1 |
| #define Gbl_pinMuxCntlBus_STS0_SD_MODE_2 0x2 |
| #define Gbl_pinMuxCntlBus_STS0_SD_MODE_3 0x3 |
| #define RA_Gbl_URT0_RXDCntl 0x8010 |
| #define BA_Gbl_URT0_RXDCntl_PD_EN 0x8010 |
| #define B16Gbl_URT0_RXDCntl_PD_EN 0x8010 |
| #define LSb32Gbl_URT0_RXDCntl_PD_EN 0 |
| #define LSb16Gbl_URT0_RXDCntl_PD_EN 0 |
| #define bGbl_URT0_RXDCntl_PD_EN 1 |
| #define MSK32Gbl_URT0_RXDCntl_PD_EN 0x00000001 |
| #define BA_Gbl_URT0_RXDCntl_PU_EN 0x8010 |
| #define B16Gbl_URT0_RXDCntl_PU_EN 0x8010 |
| #define LSb32Gbl_URT0_RXDCntl_PU_EN 1 |
| #define LSb16Gbl_URT0_RXDCntl_PU_EN 1 |
| #define bGbl_URT0_RXDCntl_PU_EN 1 |
| #define MSK32Gbl_URT0_RXDCntl_PU_EN 0x00000002 |
| #define RA_Gbl_URT0_TXDCntl 0x8014 |
| #define BA_Gbl_URT0_TXDCntl_PD_EN 0x8014 |
| #define B16Gbl_URT0_TXDCntl_PD_EN 0x8014 |
| #define LSb32Gbl_URT0_TXDCntl_PD_EN 0 |
| #define LSb16Gbl_URT0_TXDCntl_PD_EN 0 |
| #define bGbl_URT0_TXDCntl_PD_EN 1 |
| #define MSK32Gbl_URT0_TXDCntl_PD_EN 0x00000001 |
| #define BA_Gbl_URT0_TXDCntl_PU_EN 0x8014 |
| #define B16Gbl_URT0_TXDCntl_PU_EN 0x8014 |
| #define LSb32Gbl_URT0_TXDCntl_PU_EN 1 |
| #define LSb16Gbl_URT0_TXDCntl_PU_EN 1 |
| #define bGbl_URT0_TXDCntl_PU_EN 1 |
| #define MSK32Gbl_URT0_TXDCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SS0nCntl 0x8018 |
| #define BA_Gbl_SPI1_SS0nCntl_PD_EN 0x8018 |
| #define B16Gbl_SPI1_SS0nCntl_PD_EN 0x8018 |
| #define LSb32Gbl_SPI1_SS0nCntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SS0nCntl_PD_EN 0 |
| #define bGbl_SPI1_SS0nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS0nCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS0nCntl_PU_EN 0x8018 |
| #define B16Gbl_SPI1_SS0nCntl_PU_EN 0x8018 |
| #define LSb32Gbl_SPI1_SS0nCntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SS0nCntl_PU_EN 1 |
| #define bGbl_SPI1_SS0nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS0nCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SS1nCntl 0x801C |
| #define BA_Gbl_SPI1_SS1nCntl_PD_EN 0x801C |
| #define B16Gbl_SPI1_SS1nCntl_PD_EN 0x801C |
| #define LSb32Gbl_SPI1_SS1nCntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SS1nCntl_PD_EN 0 |
| #define bGbl_SPI1_SS1nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS1nCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS1nCntl_PU_EN 0x801C |
| #define B16Gbl_SPI1_SS1nCntl_PU_EN 0x801C |
| #define LSb32Gbl_SPI1_SS1nCntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SS1nCntl_PU_EN 1 |
| #define bGbl_SPI1_SS1nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS1nCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SS2nCntl 0x8020 |
| #define BA_Gbl_SPI1_SS2nCntl_PD_EN 0x8020 |
| #define B16Gbl_SPI1_SS2nCntl_PD_EN 0x8020 |
| #define LSb32Gbl_SPI1_SS2nCntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SS2nCntl_PD_EN 0 |
| #define bGbl_SPI1_SS2nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS2nCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS2nCntl_PU_EN 0x8020 |
| #define B16Gbl_SPI1_SS2nCntl_PU_EN 0x8020 |
| #define LSb32Gbl_SPI1_SS2nCntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SS2nCntl_PU_EN 1 |
| #define bGbl_SPI1_SS2nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS2nCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SCLKCntl 0x8024 |
| #define BA_Gbl_SPI1_SCLKCntl_PD_EN 0x8024 |
| #define B16Gbl_SPI1_SCLKCntl_PD_EN 0x8024 |
| #define LSb32Gbl_SPI1_SCLKCntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SCLKCntl_PD_EN 0 |
| #define bGbl_SPI1_SCLKCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SCLKCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SCLKCntl_PU_EN 0x8024 |
| #define B16Gbl_SPI1_SCLKCntl_PU_EN 0x8024 |
| #define LSb32Gbl_SPI1_SCLKCntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SCLKCntl_PU_EN 1 |
| #define bGbl_SPI1_SCLKCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SCLKCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SDOCntl 0x8028 |
| #define BA_Gbl_SPI1_SDOCntl_PD_EN 0x8028 |
| #define B16Gbl_SPI1_SDOCntl_PD_EN 0x8028 |
| #define LSb32Gbl_SPI1_SDOCntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SDOCntl_PD_EN 0 |
| #define bGbl_SPI1_SDOCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SDOCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SDOCntl_PU_EN 0x8028 |
| #define B16Gbl_SPI1_SDOCntl_PU_EN 0x8028 |
| #define LSb32Gbl_SPI1_SDOCntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SDOCntl_PU_EN 1 |
| #define bGbl_SPI1_SDOCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SDOCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SPI1_SDICntl 0x802C |
| #define BA_Gbl_SPI1_SDICntl_PD_EN 0x802C |
| #define B16Gbl_SPI1_SDICntl_PD_EN 0x802C |
| #define LSb32Gbl_SPI1_SDICntl_PD_EN 0 |
| #define LSb16Gbl_SPI1_SDICntl_PD_EN 0 |
| #define bGbl_SPI1_SDICntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SDICntl_PD_EN 0x00000001 |
| #define BA_Gbl_SPI1_SDICntl_PU_EN 0x802C |
| #define B16Gbl_SPI1_SDICntl_PU_EN 0x802C |
| #define LSb32Gbl_SPI1_SDICntl_PU_EN 1 |
| #define LSb16Gbl_SPI1_SDICntl_PU_EN 1 |
| #define bGbl_SPI1_SDICntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SDICntl_PU_EN 0x00000002 |
| #define RA_Gbl_USB1_DRV_VBUSCntl 0x8030 |
| #define BA_Gbl_USB1_DRV_VBUSCntl_PD_EN 0x8030 |
| #define B16Gbl_USB1_DRV_VBUSCntl_PD_EN 0x8030 |
| #define LSb32Gbl_USB1_DRV_VBUSCntl_PD_EN 0 |
| #define LSb16Gbl_USB1_DRV_VBUSCntl_PD_EN 0 |
| #define bGbl_USB1_DRV_VBUSCntl_PD_EN 1 |
| #define MSK32Gbl_USB1_DRV_VBUSCntl_PD_EN 0x00000001 |
| #define BA_Gbl_USB1_DRV_VBUSCntl_PU_EN 0x8030 |
| #define B16Gbl_USB1_DRV_VBUSCntl_PU_EN 0x8030 |
| #define LSb32Gbl_USB1_DRV_VBUSCntl_PU_EN 1 |
| #define LSb16Gbl_USB1_DRV_VBUSCntl_PU_EN 1 |
| #define bGbl_USB1_DRV_VBUSCntl_PU_EN 1 |
| #define MSK32Gbl_USB1_DRV_VBUSCntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO0Cntl 0x8034 |
| #define BA_Gbl_NAND_IO0Cntl_PD_EN 0x8034 |
| #define B16Gbl_NAND_IO0Cntl_PD_EN 0x8034 |
| #define LSb32Gbl_NAND_IO0Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO0Cntl_PD_EN 0 |
| #define bGbl_NAND_IO0Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO0Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO0Cntl_PU_EN 0x8034 |
| #define B16Gbl_NAND_IO0Cntl_PU_EN 0x8034 |
| #define LSb32Gbl_NAND_IO0Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO0Cntl_PU_EN 1 |
| #define bGbl_NAND_IO0Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO0Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO1Cntl 0x8038 |
| #define BA_Gbl_NAND_IO1Cntl_PD_EN 0x8038 |
| #define B16Gbl_NAND_IO1Cntl_PD_EN 0x8038 |
| #define LSb32Gbl_NAND_IO1Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO1Cntl_PD_EN 0 |
| #define bGbl_NAND_IO1Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO1Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO1Cntl_PU_EN 0x8038 |
| #define B16Gbl_NAND_IO1Cntl_PU_EN 0x8038 |
| #define LSb32Gbl_NAND_IO1Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO1Cntl_PU_EN 1 |
| #define bGbl_NAND_IO1Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO1Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO2Cntl 0x803C |
| #define BA_Gbl_NAND_IO2Cntl_PD_EN 0x803C |
| #define B16Gbl_NAND_IO2Cntl_PD_EN 0x803C |
| #define LSb32Gbl_NAND_IO2Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO2Cntl_PD_EN 0 |
| #define bGbl_NAND_IO2Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO2Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO2Cntl_PU_EN 0x803C |
| #define B16Gbl_NAND_IO2Cntl_PU_EN 0x803C |
| #define LSb32Gbl_NAND_IO2Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO2Cntl_PU_EN 1 |
| #define bGbl_NAND_IO2Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO2Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO3Cntl 0x8040 |
| #define BA_Gbl_NAND_IO3Cntl_PD_EN 0x8040 |
| #define B16Gbl_NAND_IO3Cntl_PD_EN 0x8040 |
| #define LSb32Gbl_NAND_IO3Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO3Cntl_PD_EN 0 |
| #define bGbl_NAND_IO3Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO3Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO3Cntl_PU_EN 0x8040 |
| #define B16Gbl_NAND_IO3Cntl_PU_EN 0x8040 |
| #define LSb32Gbl_NAND_IO3Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO3Cntl_PU_EN 1 |
| #define bGbl_NAND_IO3Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO3Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO4Cntl 0x8044 |
| #define BA_Gbl_NAND_IO4Cntl_PD_EN 0x8044 |
| #define B16Gbl_NAND_IO4Cntl_PD_EN 0x8044 |
| #define LSb32Gbl_NAND_IO4Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO4Cntl_PD_EN 0 |
| #define bGbl_NAND_IO4Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO4Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO4Cntl_PU_EN 0x8044 |
| #define B16Gbl_NAND_IO4Cntl_PU_EN 0x8044 |
| #define LSb32Gbl_NAND_IO4Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO4Cntl_PU_EN 1 |
| #define bGbl_NAND_IO4Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO4Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO5Cntl 0x8048 |
| #define BA_Gbl_NAND_IO5Cntl_PD_EN 0x8048 |
| #define B16Gbl_NAND_IO5Cntl_PD_EN 0x8048 |
| #define LSb32Gbl_NAND_IO5Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO5Cntl_PD_EN 0 |
| #define bGbl_NAND_IO5Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO5Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO5Cntl_PU_EN 0x8048 |
| #define B16Gbl_NAND_IO5Cntl_PU_EN 0x8048 |
| #define LSb32Gbl_NAND_IO5Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO5Cntl_PU_EN 1 |
| #define bGbl_NAND_IO5Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO5Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO6Cntl 0x804C |
| #define BA_Gbl_NAND_IO6Cntl_PD_EN 0x804C |
| #define B16Gbl_NAND_IO6Cntl_PD_EN 0x804C |
| #define LSb32Gbl_NAND_IO6Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO6Cntl_PD_EN 0 |
| #define bGbl_NAND_IO6Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO6Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO6Cntl_PU_EN 0x804C |
| #define B16Gbl_NAND_IO6Cntl_PU_EN 0x804C |
| #define LSb32Gbl_NAND_IO6Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO6Cntl_PU_EN 1 |
| #define bGbl_NAND_IO6Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO6Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_IO7Cntl 0x8050 |
| #define BA_Gbl_NAND_IO7Cntl_PD_EN 0x8050 |
| #define B16Gbl_NAND_IO7Cntl_PD_EN 0x8050 |
| #define LSb32Gbl_NAND_IO7Cntl_PD_EN 0 |
| #define LSb16Gbl_NAND_IO7Cntl_PD_EN 0 |
| #define bGbl_NAND_IO7Cntl_PD_EN 1 |
| #define MSK32Gbl_NAND_IO7Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_IO7Cntl_PU_EN 0x8050 |
| #define B16Gbl_NAND_IO7Cntl_PU_EN 0x8050 |
| #define LSb32Gbl_NAND_IO7Cntl_PU_EN 1 |
| #define LSb16Gbl_NAND_IO7Cntl_PU_EN 1 |
| #define bGbl_NAND_IO7Cntl_PU_EN 1 |
| #define MSK32Gbl_NAND_IO7Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_ALECntl 0x8054 |
| #define BA_Gbl_NAND_ALECntl_PD_EN 0x8054 |
| #define B16Gbl_NAND_ALECntl_PD_EN 0x8054 |
| #define LSb32Gbl_NAND_ALECntl_PD_EN 0 |
| #define LSb16Gbl_NAND_ALECntl_PD_EN 0 |
| #define bGbl_NAND_ALECntl_PD_EN 1 |
| #define MSK32Gbl_NAND_ALECntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_ALECntl_PU_EN 0x8054 |
| #define B16Gbl_NAND_ALECntl_PU_EN 0x8054 |
| #define LSb32Gbl_NAND_ALECntl_PU_EN 1 |
| #define LSb16Gbl_NAND_ALECntl_PU_EN 1 |
| #define bGbl_NAND_ALECntl_PU_EN 1 |
| #define MSK32Gbl_NAND_ALECntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_CLECntl 0x8058 |
| #define BA_Gbl_NAND_CLECntl_PD_EN 0x8058 |
| #define B16Gbl_NAND_CLECntl_PD_EN 0x8058 |
| #define LSb32Gbl_NAND_CLECntl_PD_EN 0 |
| #define LSb16Gbl_NAND_CLECntl_PD_EN 0 |
| #define bGbl_NAND_CLECntl_PD_EN 1 |
| #define MSK32Gbl_NAND_CLECntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_CLECntl_PU_EN 0x8058 |
| #define B16Gbl_NAND_CLECntl_PU_EN 0x8058 |
| #define LSb32Gbl_NAND_CLECntl_PU_EN 1 |
| #define LSb16Gbl_NAND_CLECntl_PU_EN 1 |
| #define bGbl_NAND_CLECntl_PU_EN 1 |
| #define MSK32Gbl_NAND_CLECntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_WEnCntl 0x805C |
| #define BA_Gbl_NAND_WEnCntl_PD_EN 0x805C |
| #define B16Gbl_NAND_WEnCntl_PD_EN 0x805C |
| #define LSb32Gbl_NAND_WEnCntl_PD_EN 0 |
| #define LSb16Gbl_NAND_WEnCntl_PD_EN 0 |
| #define bGbl_NAND_WEnCntl_PD_EN 1 |
| #define MSK32Gbl_NAND_WEnCntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_WEnCntl_PU_EN 0x805C |
| #define B16Gbl_NAND_WEnCntl_PU_EN 0x805C |
| #define LSb32Gbl_NAND_WEnCntl_PU_EN 1 |
| #define LSb16Gbl_NAND_WEnCntl_PU_EN 1 |
| #define bGbl_NAND_WEnCntl_PU_EN 1 |
| #define MSK32Gbl_NAND_WEnCntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_REnCntl 0x8060 |
| #define BA_Gbl_NAND_REnCntl_PD_EN 0x8060 |
| #define B16Gbl_NAND_REnCntl_PD_EN 0x8060 |
| #define LSb32Gbl_NAND_REnCntl_PD_EN 0 |
| #define LSb16Gbl_NAND_REnCntl_PD_EN 0 |
| #define bGbl_NAND_REnCntl_PD_EN 1 |
| #define MSK32Gbl_NAND_REnCntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_REnCntl_PU_EN 0x8060 |
| #define B16Gbl_NAND_REnCntl_PU_EN 0x8060 |
| #define LSb32Gbl_NAND_REnCntl_PU_EN 1 |
| #define LSb16Gbl_NAND_REnCntl_PU_EN 1 |
| #define bGbl_NAND_REnCntl_PU_EN 1 |
| #define MSK32Gbl_NAND_REnCntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_WPnCntl 0x8064 |
| #define BA_Gbl_NAND_WPnCntl_PD_EN 0x8064 |
| #define B16Gbl_NAND_WPnCntl_PD_EN 0x8064 |
| #define LSb32Gbl_NAND_WPnCntl_PD_EN 0 |
| #define LSb16Gbl_NAND_WPnCntl_PD_EN 0 |
| #define bGbl_NAND_WPnCntl_PD_EN 1 |
| #define MSK32Gbl_NAND_WPnCntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_WPnCntl_PU_EN 0x8064 |
| #define B16Gbl_NAND_WPnCntl_PU_EN 0x8064 |
| #define LSb32Gbl_NAND_WPnCntl_PU_EN 1 |
| #define LSb16Gbl_NAND_WPnCntl_PU_EN 1 |
| #define bGbl_NAND_WPnCntl_PU_EN 1 |
| #define MSK32Gbl_NAND_WPnCntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_CEnCntl 0x8068 |
| #define BA_Gbl_NAND_CEnCntl_PD_EN 0x8068 |
| #define B16Gbl_NAND_CEnCntl_PD_EN 0x8068 |
| #define LSb32Gbl_NAND_CEnCntl_PD_EN 0 |
| #define LSb16Gbl_NAND_CEnCntl_PD_EN 0 |
| #define bGbl_NAND_CEnCntl_PD_EN 1 |
| #define MSK32Gbl_NAND_CEnCntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_CEnCntl_PU_EN 0x8068 |
| #define B16Gbl_NAND_CEnCntl_PU_EN 0x8068 |
| #define LSb32Gbl_NAND_CEnCntl_PU_EN 1 |
| #define LSb16Gbl_NAND_CEnCntl_PU_EN 1 |
| #define bGbl_NAND_CEnCntl_PU_EN 1 |
| #define MSK32Gbl_NAND_CEnCntl_PU_EN 0x00000002 |
| #define RA_Gbl_NAND_RDYCntl 0x806C |
| #define BA_Gbl_NAND_RDYCntl_PD_EN 0x806C |
| #define B16Gbl_NAND_RDYCntl_PD_EN 0x806C |
| #define LSb32Gbl_NAND_RDYCntl_PD_EN 0 |
| #define LSb16Gbl_NAND_RDYCntl_PD_EN 0 |
| #define bGbl_NAND_RDYCntl_PD_EN 1 |
| #define MSK32Gbl_NAND_RDYCntl_PD_EN 0x00000001 |
| #define BA_Gbl_NAND_RDYCntl_PU_EN 0x806C |
| #define B16Gbl_NAND_RDYCntl_PU_EN 0x806C |
| #define LSb32Gbl_NAND_RDYCntl_PU_EN 1 |
| #define LSb16Gbl_NAND_RDYCntl_PU_EN 1 |
| #define bGbl_NAND_RDYCntl_PU_EN 1 |
| #define MSK32Gbl_NAND_RDYCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_CLKCntl 0x8070 |
| #define BA_Gbl_SD0_CLKCntl_PD_EN 0x8070 |
| #define B16Gbl_SD0_CLKCntl_PD_EN 0x8070 |
| #define LSb32Gbl_SD0_CLKCntl_PD_EN 0 |
| #define LSb16Gbl_SD0_CLKCntl_PD_EN 0 |
| #define bGbl_SD0_CLKCntl_PD_EN 1 |
| #define MSK32Gbl_SD0_CLKCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_CLKCntl_PU_EN 0x8070 |
| #define B16Gbl_SD0_CLKCntl_PU_EN 0x8070 |
| #define LSb32Gbl_SD0_CLKCntl_PU_EN 1 |
| #define LSb16Gbl_SD0_CLKCntl_PU_EN 1 |
| #define bGbl_SD0_CLKCntl_PU_EN 1 |
| #define MSK32Gbl_SD0_CLKCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_DAT0Cntl 0x8074 |
| #define BA_Gbl_SD0_DAT0Cntl_PD_EN 0x8074 |
| #define B16Gbl_SD0_DAT0Cntl_PD_EN 0x8074 |
| #define LSb32Gbl_SD0_DAT0Cntl_PD_EN 0 |
| #define LSb16Gbl_SD0_DAT0Cntl_PD_EN 0 |
| #define bGbl_SD0_DAT0Cntl_PD_EN 1 |
| #define MSK32Gbl_SD0_DAT0Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_DAT0Cntl_PU_EN 0x8074 |
| #define B16Gbl_SD0_DAT0Cntl_PU_EN 0x8074 |
| #define LSb32Gbl_SD0_DAT0Cntl_PU_EN 1 |
| #define LSb16Gbl_SD0_DAT0Cntl_PU_EN 1 |
| #define bGbl_SD0_DAT0Cntl_PU_EN 1 |
| #define MSK32Gbl_SD0_DAT0Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_DAT1Cntl 0x8078 |
| #define BA_Gbl_SD0_DAT1Cntl_PD_EN 0x8078 |
| #define B16Gbl_SD0_DAT1Cntl_PD_EN 0x8078 |
| #define LSb32Gbl_SD0_DAT1Cntl_PD_EN 0 |
| #define LSb16Gbl_SD0_DAT1Cntl_PD_EN 0 |
| #define bGbl_SD0_DAT1Cntl_PD_EN 1 |
| #define MSK32Gbl_SD0_DAT1Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_DAT1Cntl_PU_EN 0x8078 |
| #define B16Gbl_SD0_DAT1Cntl_PU_EN 0x8078 |
| #define LSb32Gbl_SD0_DAT1Cntl_PU_EN 1 |
| #define LSb16Gbl_SD0_DAT1Cntl_PU_EN 1 |
| #define bGbl_SD0_DAT1Cntl_PU_EN 1 |
| #define MSK32Gbl_SD0_DAT1Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_DAT2Cntl 0x807C |
| #define BA_Gbl_SD0_DAT2Cntl_PD_EN 0x807C |
| #define B16Gbl_SD0_DAT2Cntl_PD_EN 0x807C |
| #define LSb32Gbl_SD0_DAT2Cntl_PD_EN 0 |
| #define LSb16Gbl_SD0_DAT2Cntl_PD_EN 0 |
| #define bGbl_SD0_DAT2Cntl_PD_EN 1 |
| #define MSK32Gbl_SD0_DAT2Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_DAT2Cntl_PU_EN 0x807C |
| #define B16Gbl_SD0_DAT2Cntl_PU_EN 0x807C |
| #define LSb32Gbl_SD0_DAT2Cntl_PU_EN 1 |
| #define LSb16Gbl_SD0_DAT2Cntl_PU_EN 1 |
| #define bGbl_SD0_DAT2Cntl_PU_EN 1 |
| #define MSK32Gbl_SD0_DAT2Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_DAT3Cntl 0x8080 |
| #define BA_Gbl_SD0_DAT3Cntl_PD_EN 0x8080 |
| #define B16Gbl_SD0_DAT3Cntl_PD_EN 0x8080 |
| #define LSb32Gbl_SD0_DAT3Cntl_PD_EN 0 |
| #define LSb16Gbl_SD0_DAT3Cntl_PD_EN 0 |
| #define bGbl_SD0_DAT3Cntl_PD_EN 1 |
| #define MSK32Gbl_SD0_DAT3Cntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_DAT3Cntl_PU_EN 0x8080 |
| #define B16Gbl_SD0_DAT3Cntl_PU_EN 0x8080 |
| #define LSb32Gbl_SD0_DAT3Cntl_PU_EN 1 |
| #define LSb16Gbl_SD0_DAT3Cntl_PU_EN 1 |
| #define bGbl_SD0_DAT3Cntl_PU_EN 1 |
| #define MSK32Gbl_SD0_DAT3Cntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_CDnCntl 0x8084 |
| #define BA_Gbl_SD0_CDnCntl_PD_EN 0x8084 |
| #define B16Gbl_SD0_CDnCntl_PD_EN 0x8084 |
| #define LSb32Gbl_SD0_CDnCntl_PD_EN 0 |
| #define LSb16Gbl_SD0_CDnCntl_PD_EN 0 |
| #define bGbl_SD0_CDnCntl_PD_EN 1 |
| #define MSK32Gbl_SD0_CDnCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_CDnCntl_PU_EN 0x8084 |
| #define B16Gbl_SD0_CDnCntl_PU_EN 0x8084 |
| #define LSb32Gbl_SD0_CDnCntl_PU_EN 1 |
| #define LSb16Gbl_SD0_CDnCntl_PU_EN 1 |
| #define bGbl_SD0_CDnCntl_PU_EN 1 |
| #define MSK32Gbl_SD0_CDnCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_CMDCntl 0x8088 |
| #define BA_Gbl_SD0_CMDCntl_PD_EN 0x8088 |
| #define B16Gbl_SD0_CMDCntl_PD_EN 0x8088 |
| #define LSb32Gbl_SD0_CMDCntl_PD_EN 0 |
| #define LSb16Gbl_SD0_CMDCntl_PD_EN 0 |
| #define bGbl_SD0_CMDCntl_PD_EN 1 |
| #define MSK32Gbl_SD0_CMDCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_CMDCntl_PU_EN 0x8088 |
| #define B16Gbl_SD0_CMDCntl_PU_EN 0x8088 |
| #define LSb32Gbl_SD0_CMDCntl_PU_EN 1 |
| #define LSb16Gbl_SD0_CMDCntl_PU_EN 1 |
| #define bGbl_SD0_CMDCntl_PU_EN 1 |
| #define MSK32Gbl_SD0_CMDCntl_PU_EN 0x00000002 |
| #define RA_Gbl_SD0_WPCntl 0x808C |
| #define BA_Gbl_SD0_WPCntl_PD_EN 0x808C |
| #define B16Gbl_SD0_WPCntl_PD_EN 0x808C |
| #define LSb32Gbl_SD0_WPCntl_PD_EN 0 |
| #define LSb16Gbl_SD0_WPCntl_PD_EN 0 |
| #define bGbl_SD0_WPCntl_PD_EN 1 |
| #define MSK32Gbl_SD0_WPCntl_PD_EN 0x00000001 |
| #define BA_Gbl_SD0_WPCntl_PU_EN 0x808C |
| #define B16Gbl_SD0_WPCntl_PU_EN 0x808C |
| #define LSb32Gbl_SD0_WPCntl_PU_EN 1 |
| #define LSb16Gbl_SD0_WPCntl_PU_EN 1 |
| #define bGbl_SD0_WPCntl_PU_EN 1 |
| #define MSK32Gbl_SD0_WPCntl_PU_EN 0x00000002 |
| #define RA_Gbl_STS0_CLKCntl 0x8090 |
| #define BA_Gbl_STS0_CLKCntl_PD_EN 0x8090 |
| #define B16Gbl_STS0_CLKCntl_PD_EN 0x8090 |
| #define LSb32Gbl_STS0_CLKCntl_PD_EN 0 |
| #define LSb16Gbl_STS0_CLKCntl_PD_EN 0 |
| #define bGbl_STS0_CLKCntl_PD_EN 1 |
| #define MSK32Gbl_STS0_CLKCntl_PD_EN 0x00000001 |
| #define BA_Gbl_STS0_CLKCntl_PU_EN 0x8090 |
| #define B16Gbl_STS0_CLKCntl_PU_EN 0x8090 |
| #define LSb32Gbl_STS0_CLKCntl_PU_EN 1 |
| #define LSb16Gbl_STS0_CLKCntl_PU_EN 1 |
| #define bGbl_STS0_CLKCntl_PU_EN 1 |
| #define MSK32Gbl_STS0_CLKCntl_PU_EN 0x00000002 |
| #define RA_Gbl_STS0_SOPCntl 0x8094 |
| #define BA_Gbl_STS0_SOPCntl_PD_EN 0x8094 |
| #define B16Gbl_STS0_SOPCntl_PD_EN 0x8094 |
| #define LSb32Gbl_STS0_SOPCntl_PD_EN 0 |
| #define LSb16Gbl_STS0_SOPCntl_PD_EN 0 |
| #define bGbl_STS0_SOPCntl_PD_EN 1 |
| #define MSK32Gbl_STS0_SOPCntl_PD_EN 0x00000001 |
| #define BA_Gbl_STS0_SOPCntl_PU_EN 0x8094 |
| #define B16Gbl_STS0_SOPCntl_PU_EN 0x8094 |
| #define LSb32Gbl_STS0_SOPCntl_PU_EN 1 |
| #define LSb16Gbl_STS0_SOPCntl_PU_EN 1 |
| #define bGbl_STS0_SOPCntl_PU_EN 1 |
| #define MSK32Gbl_STS0_SOPCntl_PU_EN 0x00000002 |
| #define RA_Gbl_STS0_VALDCntl 0x8098 |
| #define BA_Gbl_STS0_VALDCntl_PD_EN 0x8098 |
| #define B16Gbl_STS0_VALDCntl_PD_EN 0x8098 |
| #define LSb32Gbl_STS0_VALDCntl_PD_EN 0 |
| #define LSb16Gbl_STS0_VALDCntl_PD_EN 0 |
| #define bGbl_STS0_VALDCntl_PD_EN 1 |
| #define MSK32Gbl_STS0_VALDCntl_PD_EN 0x00000001 |
| #define BA_Gbl_STS0_VALDCntl_PU_EN 0x8098 |
| #define B16Gbl_STS0_VALDCntl_PU_EN 0x8098 |
| #define LSb32Gbl_STS0_VALDCntl_PU_EN 1 |
| #define LSb16Gbl_STS0_VALDCntl_PU_EN 1 |
| #define bGbl_STS0_VALDCntl_PU_EN 1 |
| #define MSK32Gbl_STS0_VALDCntl_PU_EN 0x00000002 |
| #define RA_Gbl_STS0_SDCntl 0x809C |
| #define BA_Gbl_STS0_SDCntl_PD_EN 0x809C |
| #define B16Gbl_STS0_SDCntl_PD_EN 0x809C |
| #define LSb32Gbl_STS0_SDCntl_PD_EN 0 |
| #define LSb16Gbl_STS0_SDCntl_PD_EN 0 |
| #define bGbl_STS0_SDCntl_PD_EN 1 |
| #define MSK32Gbl_STS0_SDCntl_PD_EN 0x00000001 |
| #define BA_Gbl_STS0_SDCntl_PU_EN 0x809C |
| #define B16Gbl_STS0_SDCntl_PU_EN 0x809C |
| #define LSb32Gbl_STS0_SDCntl_PU_EN 1 |
| #define LSb16Gbl_STS0_SDCntl_PU_EN 1 |
| #define bGbl_STS0_SDCntl_PU_EN 1 |
| #define MSK32Gbl_STS0_SDCntl_PU_EN 0x00000002 |
| |
| #endif |
| |
