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nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP / ssPll.h
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/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: ssPll.h
////////////////////////////////////////////////////////////
#ifndef ssPll_h
#define ssPll_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE pll (4,4)
/// ###
/// * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
/// * adding in a fixed frequency offset in about 1 ppm/step resolution.
/// * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
/// * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
/// * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
/// * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
/// * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
/// * M: Reference Divider: 1 to 511.
/// * N: Feedback Divider: 1 to 511.
/// * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
/// * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
/// * Divider value = 1 1,2,3,4….128.
/// * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
/// * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
/// * applicable only in the low power mode and cannot be used with the SSC function. In order to
/// * use the SSC function VCO must be operated above 1.5GHz.
/// * .. Cycle to Cycle Jitter (max): <30 ps.
/// * .. Programmable Reference and Feedback Divider.
/// * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
/// * Divider setting.
/// * .. SSC frequency range: 30 KHz ~ 100 KHz
/// * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
/// * .. Supporting both down-spread and center-spread modes.
/// * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
/// * .. Locking time: < 50 us
/// * .. Process Node: 28 nm LP
/// * .. Analog Power Supply: 1.8 V (+10%, -5%)
/// * .. Digital Power Supply: 1.05 V (±10%)
/// * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
/// * .. Output Duty Cycle: 45% - 55% for any post divider ratio
/// * .. Built-in Bandgap circuit.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * PLL Control register
/// ###
/// %unsigned 1 PU 0x1
/// ###
/// * PLL Power-Up
/// * 1: power up.
/// * 0: power down.
/// ###
/// %unsigned 1 RESET 0x0
/// ###
/// * Power On Reset. Active high, reset PLL and all logic.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 AVDD1815_SEL 0x1
/// ###
/// * AVDD Select.
/// * Selects whether AVDD is 1.8V
/// * or 1.5V.
/// * 1: 1.8V
/// * 0: 1.5V
/// ###
/// %unsigned 9 REFDIV 0x2
/// ###
/// * Reference Clock Divider
/// * Select.
/// * Divider = REFDIV[8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * REFDIV[8:0] range is 1~250
/// ###
/// %unsigned 9 FBDIV 0x20
/// ###
/// * Feedback Clock Divider Select.
/// * Divider= FBDIV [8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * FBDIV range is 9 to 94
/// ###
/// %unsigned 2 VDDM 0x1
/// ###
/// * VCO Supply Control.
/// * 11: 1.3 V
/// * 10: 1.25 V
/// * 01: 1.2 V
/// * 00: 1.15 V.
/// ###
/// %unsigned 3 VDDL 0x4
/// ###
/// * Internal VDD Supply
/// * Control.
/// * 000:0.9V
/// * 001:0.95V
/// * 010:1V
/// * 011:1.05V
/// * 100:1.1V
/// * 101:1.15V
/// * 110:1.2V
/// * 111:1.2V.
/// ###
/// %unsigned 4 ICP 0x1
/// ###
/// * Charge-pump Current Control Bits.
/// * 0000: 3 uA
/// * 0001: 3.75 uA
/// * 0010: 4.5 uA
/// * 0011: 5.25 uA
/// * 0100: 6 uA
/// * 0101: 7.5 uA
/// * 0110: 9 uA
/// * 0111: 10.5 uA
/// * 1000: 12 uA
/// * 1001: 15 uA
/// * 1010: 18 uA
/// * 1011: 21 uA
/// * 1100: 24 uA
/// * 1101: 30 uA
/// * 1110: 36 uA
/// * 1111: 42 uA.
/// * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
/// * If PU_BW_SEL = 1, then increase ICP value by 2x
/// ###
/// %unsigned 1 PLL_BW_SEL 0x0
/// ###
/// * PLL Bandwidth Select.
/// * 1: BW x 2
/// * 0: Normal PLL bandwidth.
/// * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
/// * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 4 KVCO 0xA
/// ###
/// * KVCO Frequency Range
/// * Select.
/// * 0000~0111: Reserved.
/// * 1000:1.2GHz ~ 1.35GHz
/// * 1001:1.35GHz ~ 1.5GHz
/// * 1010:1.5GHz ~ 1.75GHz
/// * 1011:1.75GHz ~ 2.00GHz
/// * 1100: 2GHz ~ 2.2GHz
/// * 1101: 2.2GHz ~ 2.4GHz
/// * 1110: 2.4GHz ~ 2.6GHz
/// * 1111: 2.6GHz ~ 3GHz
/// * SSC mode is only supported for frequency >=2 GHz
/// * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
/// ###
/// %unsigned 2 CTUNE 0x1
/// ###
/// * VCO Capacitor Select.
/// * 00: No Cap Loading
/// * 01: One Unit Cap Loading
/// * 10: Two Unit Cap Loading
/// * 11: Three Unit Cap Loading.
/// ###
/// %unsigned 3 CLKOUT_DIFF_DIV_SEL 0x2
/// ###
/// * Post Divider For Differential
/// * Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 3 CLKOUT_SE_DIV_SEL 0x2
/// ###
/// * Post Divider For
/// * Single-ended Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 1 CLKOUT_SOURCE_SEL 0x1
/// ###
/// * Differential Clock And
/// * Single-ended Clock Source Control.
/// * 0: from the phase interpolator.
/// * 1: from VCO directly.
/// * Note: This is used in test mode only. Select ‘1’ for normal operation.
/// ###
/// %unsigned 1 CLKOUT_DIFF_EN 0x1
/// ###
/// * Differential Clock Enable.
/// * 0:Disable differential clock
/// * 1:Enable differential clock
/// ###
/// %unsigned 1 BYPASS_EN 0x0
/// ###
/// * PLL Clock Bypass Enable.
/// * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
/// * 0: CLKOUT is derived from the PLL clock.
/// * NOTE: Bypass only works for the single ended clock.
/// * If BYPASS_EN==1. CLKOUT= REFCLK.
/// * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
/// ###
/// %unsigned 1 CLKOUT_SE_GATING_EN 0x0
/// ###
/// * Clock Output Gating Control.
/// * Selection for using the PLL lock signal to gate the output clock.
/// * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
/// * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
/// ###
/// %unsigned 1 FBCLK_EXT_SEL 0x0
/// ###
/// * External Or Internal Feedback
/// * Clock Select.
/// * 0: select internal feedback clock
/// * 1: select external feedback clock.
/// * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
/// ###
/// %unsigned 6 FBCDLY 0x0
/// ###
/// * Fine Tune Delay Select
/// * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
/// * FBCDLY[5] is the sign bit.
/// * 1 = FBCLK_EXT will lag REFCLK.
/// * 0 = FBCLK_EXT will lead REFCLK.
/// * FBCDLY[4:0] decides the actual amount of delay.
/// * 00000: No delay.
/// * Each additional step has these
/// * delays:
/// * 00h = No delay
/// * 01h = 15 - 50 ps phase difference
/// * 02h = 30 - 100 ps phase difference
/// * 03h = 45 - 150 ps phase difference
/// * ...
/// * 3Fh = 945 ps - 3150 ps phase difference.
/// * Note: Used in DSPLL application, do not use in regular PLL application.
/// ###
/// %unsigned 3 FD 0x4
/// ###
/// * Tune Frequency Detector Precision
/// * FD[0]: Reserved.
/// * FD[2:1] FD precision
/// * 00 +/- 0.1%
/// * 01 +/- 0.2%
/// * 10 +/- 0.4%
/// * 11 +/- 0.8%.
/// ###
/// %unsigned 4 INTPI 0x6
/// ###
/// * Phase Interpolator Bias Current Select.
/// * 1.2 ~ 1.5 GHz NOT SUPPORTED
/// * 0101: (VCO:1.5 ~ 2 GHz)
/// * 0110: (VCO:2 ~ 2.5 GHz)
/// * 1000: (VCO:2.5 ~ 3GHz).
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 3 INTPR 0x4
/// ###
/// * Phase Interpolator Resistor Select.
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %unsigned 1 PI_EN 0x0
/// ###
/// * Phase Interpolator Enable.
/// * 1: Enable phase interpolator
/// * 0: Disable phase interpolator.
/// ###
/// %unsigned 1 PI_LOOP_MODE 0x0
/// ###
/// * Phase Interpolator Loop Control.
/// * 1: PI is in the PLL loop.
/// * 0: PI is out of the PLL loop
/// ###
/// %unsigned 1 CLK_DET_EN 0x1
/// ###
/// * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
/// ###
/// %unsigned 1 RESET_PI 0x0
/// ###
/// * External Interpolator Reset.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 RESET_SSC 0x0
/// ###
/// * SSC reset
/// * 0 : No reset
/// * 1 : Reset
/// ###
/// %unsigned 1 FREQ_OFFSET_EN 0x0
/// ###
/// * Frequency Offset Enable.
/// * 0: Disable
/// * 1: Enable.
/// ###
/// %unsigned 17 FREQ_OFFSET 0x0
/// ###
/// * Frequency Offset Value
/// * Control.
/// * [16]: Sign-Bit.
/// * 0: Frequency down
/// * 1: Frequency up
/// * [15:0] : 1 LSB 1 ppm, upto 5%
/// * 1LSB=10e6/(4*128 *2048) ppm
/// * [16]=0--->Sign= 1
/// * [16]=1--->Sign= -1
/// * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
/// ###
/// %unsigned 1 FREQ_OFFSET_MODE_SELECTION 0x0
/// ###
/// * Frequency Offset Mode Select.
/// * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
/// * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
/// * (It has to be valid at the rising edge of CK_DIV64_OUT).
/// * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
/// ###
/// %unsigned 1 FREQ_OFFSET_VALID 0x0
/// ###
/// * Frequency Offset Value Valid.
/// * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
/// * Note:
/// * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
/// * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
/// ###
/// %unsigned 1 SSC_CLK_EN 0x0
/// ###
/// * SSC Clock Enable.
/// * This selection enables the PI output clock for SSC digital logic.
/// ###
/// %unsigned 1 SSC_MODE 0x1
/// ###
/// * SSC Mode Select.
/// * 0: center spread
/// * 1: down spread.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 16 SSC_FREQ_DIV 0x0
/// ###
/// * SSC Frequency Select.
/// ###
/// %unsigned 11 SSC_RNGE 0x0
/// ###
/// * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
/// * Rounding to integer required.
/// ###
/// %unsigned 4 TEST_ANA 0x0
/// ###
/// * Analog test point
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00010 ctrl4
/// %unsigned 8 RESERVE_IN 0x0
/// ###
/// * Reserved input pins
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00014 status (R-)
/// ###
/// * PLL status register
/// ###
/// %unsigned 1 PLL_LOCK
/// ###
/// * PLL Lock Detect.
/// * 1: PLL locked.
/// * 0: PLL not locked.
/// * Note:
/// * After PLL is powered up, wait for 50 us to check for the lock status.
/// * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
/// * This signal is for testing purpose only, do not use it for any functional use.
/// ###
/// %unsigned 1 CLK_CFMOD
/// ###
/// * Clock Mode Output.
/// * • For down spread and
/// * PI_LOOP_MODE = 0, output
/// * is 0.
/// * • For down spread and
/// * PI_LOOP_MODE = 1, output
/// * is 1.
/// * • For center spread, output a
/// * clock with SSC modulation
/// * frequency.
/// ###
/// %unsigned 1 CLK_FMOD
/// ###
/// * Clock Output And Modulation
/// * Frequency.
/// * For down spread, output a clock
/// * with SSC modulation frequency.
/// * For center spread, output a clock
/// * with double SSC modulation
/// * frequency.
/// ###
/// %unsigned 8 RESERVE_OUT
/// ###
/// * Reserve Output Register pins.
/// ###
/// %% 21 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 24B, bits: 141b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}
#define RA_pll_ctrl 0x0000
#define BA_pll_ctrl_PU 0x0000
#define B16pll_ctrl_PU 0x0000
#define LSb32pll_ctrl_PU 0
#define LSb16pll_ctrl_PU 0
#define bpll_ctrl_PU 1
#define MSK32pll_ctrl_PU 0x00000001
#define BA_pll_ctrl_RESET 0x0000
#define B16pll_ctrl_RESET 0x0000
#define LSb32pll_ctrl_RESET 1
#define LSb16pll_ctrl_RESET 1
#define bpll_ctrl_RESET 1
#define MSK32pll_ctrl_RESET 0x00000002
#define BA_pll_ctrl_AVDD1815_SEL 0x0000
#define B16pll_ctrl_AVDD1815_SEL 0x0000
#define LSb32pll_ctrl_AVDD1815_SEL 2
#define LSb16pll_ctrl_AVDD1815_SEL 2
#define bpll_ctrl_AVDD1815_SEL 1
#define MSK32pll_ctrl_AVDD1815_SEL 0x00000004
#define BA_pll_ctrl_REFDIV 0x0000
#define B16pll_ctrl_REFDIV 0x0000
#define LSb32pll_ctrl_REFDIV 3
#define LSb16pll_ctrl_REFDIV 3
#define bpll_ctrl_REFDIV 9
#define MSK32pll_ctrl_REFDIV 0x00000FF8
#define BA_pll_ctrl_FBDIV 0x0001
#define B16pll_ctrl_FBDIV 0x0000
#define LSb32pll_ctrl_FBDIV 12
#define LSb16pll_ctrl_FBDIV 12
#define bpll_ctrl_FBDIV 9
#define MSK32pll_ctrl_FBDIV 0x001FF000
#define BA_pll_ctrl_VDDM 0x0002
#define B16pll_ctrl_VDDM 0x0002
#define LSb32pll_ctrl_VDDM 21
#define LSb16pll_ctrl_VDDM 5
#define bpll_ctrl_VDDM 2
#define MSK32pll_ctrl_VDDM 0x00600000
#define BA_pll_ctrl_VDDL 0x0002
#define B16pll_ctrl_VDDL 0x0002
#define LSb32pll_ctrl_VDDL 23
#define LSb16pll_ctrl_VDDL 7
#define bpll_ctrl_VDDL 3
#define MSK32pll_ctrl_VDDL 0x03800000
#define BA_pll_ctrl_ICP 0x0003
#define B16pll_ctrl_ICP 0x0002
#define LSb32pll_ctrl_ICP 26
#define LSb16pll_ctrl_ICP 10
#define bpll_ctrl_ICP 4
#define MSK32pll_ctrl_ICP 0x3C000000
#define BA_pll_ctrl_PLL_BW_SEL 0x0003
#define B16pll_ctrl_PLL_BW_SEL 0x0002
#define LSb32pll_ctrl_PLL_BW_SEL 30
#define LSb16pll_ctrl_PLL_BW_SEL 14
#define bpll_ctrl_PLL_BW_SEL 1
#define MSK32pll_ctrl_PLL_BW_SEL 0x40000000
#define RA_pll_ctrl1 0x0004
#define BA_pll_ctrl_KVCO 0x0004
#define B16pll_ctrl_KVCO 0x0004
#define LSb32pll_ctrl_KVCO 0
#define LSb16pll_ctrl_KVCO 0
#define bpll_ctrl_KVCO 4
#define MSK32pll_ctrl_KVCO 0x0000000F
#define BA_pll_ctrl_CTUNE 0x0004
#define B16pll_ctrl_CTUNE 0x0004
#define LSb32pll_ctrl_CTUNE 4
#define LSb16pll_ctrl_CTUNE 4
#define bpll_ctrl_CTUNE 2
#define MSK32pll_ctrl_CTUNE 0x00000030
#define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x000001C0
#define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define bpll_ctrl_CLKOUT_SE_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00000E00
#define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 12
#define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 12
#define bpll_ctrl_CLKOUT_SOURCE_SEL 1
#define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x00001000
#define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0005
#define B16pll_ctrl_CLKOUT_DIFF_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_EN 13
#define LSb16pll_ctrl_CLKOUT_DIFF_EN 13
#define bpll_ctrl_CLKOUT_DIFF_EN 1
#define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x00002000
#define BA_pll_ctrl_BYPASS_EN 0x0005
#define B16pll_ctrl_BYPASS_EN 0x0004
#define LSb32pll_ctrl_BYPASS_EN 14
#define LSb16pll_ctrl_BYPASS_EN 14
#define bpll_ctrl_BYPASS_EN 1
#define MSK32pll_ctrl_BYPASS_EN 0x00004000
#define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0005
#define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 15
#define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 15
#define bpll_ctrl_CLKOUT_SE_GATING_EN 1
#define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x00008000
#define BA_pll_ctrl_FBCLK_EXT_SEL 0x0006
#define B16pll_ctrl_FBCLK_EXT_SEL 0x0006
#define LSb32pll_ctrl_FBCLK_EXT_SEL 16
#define LSb16pll_ctrl_FBCLK_EXT_SEL 0
#define bpll_ctrl_FBCLK_EXT_SEL 1
#define MSK32pll_ctrl_FBCLK_EXT_SEL 0x00010000
#define BA_pll_ctrl_FBCDLY 0x0006
#define B16pll_ctrl_FBCDLY 0x0006
#define LSb32pll_ctrl_FBCDLY 17
#define LSb16pll_ctrl_FBCDLY 1
#define bpll_ctrl_FBCDLY 6
#define MSK32pll_ctrl_FBCDLY 0x007E0000
#define BA_pll_ctrl_FD 0x0006
#define B16pll_ctrl_FD 0x0006
#define LSb32pll_ctrl_FD 23
#define LSb16pll_ctrl_FD 7
#define bpll_ctrl_FD 3
#define MSK32pll_ctrl_FD 0x03800000
#define BA_pll_ctrl_INTPI 0x0007
#define B16pll_ctrl_INTPI 0x0006
#define LSb32pll_ctrl_INTPI 26
#define LSb16pll_ctrl_INTPI 10
#define bpll_ctrl_INTPI 4
#define MSK32pll_ctrl_INTPI 0x3C000000
#define RA_pll_ctrl2 0x0008
#define BA_pll_ctrl_INTPR 0x0008
#define B16pll_ctrl_INTPR 0x0008
#define LSb32pll_ctrl_INTPR 0
#define LSb16pll_ctrl_INTPR 0
#define bpll_ctrl_INTPR 3
#define MSK32pll_ctrl_INTPR 0x00000007
#define BA_pll_ctrl_PI_EN 0x0008
#define B16pll_ctrl_PI_EN 0x0008
#define LSb32pll_ctrl_PI_EN 3
#define LSb16pll_ctrl_PI_EN 3
#define bpll_ctrl_PI_EN 1
#define MSK32pll_ctrl_PI_EN 0x00000008
#define BA_pll_ctrl_PI_LOOP_MODE 0x0008
#define B16pll_ctrl_PI_LOOP_MODE 0x0008
#define LSb32pll_ctrl_PI_LOOP_MODE 4
#define LSb16pll_ctrl_PI_LOOP_MODE 4
#define bpll_ctrl_PI_LOOP_MODE 1
#define MSK32pll_ctrl_PI_LOOP_MODE 0x00000010
#define BA_pll_ctrl_CLK_DET_EN 0x0008
#define B16pll_ctrl_CLK_DET_EN 0x0008
#define LSb32pll_ctrl_CLK_DET_EN 5
#define LSb16pll_ctrl_CLK_DET_EN 5
#define bpll_ctrl_CLK_DET_EN 1
#define MSK32pll_ctrl_CLK_DET_EN 0x00000020
#define BA_pll_ctrl_RESET_PI 0x0008
#define B16pll_ctrl_RESET_PI 0x0008
#define LSb32pll_ctrl_RESET_PI 6
#define LSb16pll_ctrl_RESET_PI 6
#define bpll_ctrl_RESET_PI 1
#define MSK32pll_ctrl_RESET_PI 0x00000040
#define BA_pll_ctrl_RESET_SSC 0x0008
#define B16pll_ctrl_RESET_SSC 0x0008
#define LSb32pll_ctrl_RESET_SSC 7
#define LSb16pll_ctrl_RESET_SSC 7
#define bpll_ctrl_RESET_SSC 1
#define MSK32pll_ctrl_RESET_SSC 0x00000080
#define BA_pll_ctrl_FREQ_OFFSET_EN 0x0009
#define B16pll_ctrl_FREQ_OFFSET_EN 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET_EN 8
#define LSb16pll_ctrl_FREQ_OFFSET_EN 8
#define bpll_ctrl_FREQ_OFFSET_EN 1
#define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00000100
#define BA_pll_ctrl_FREQ_OFFSET 0x0009
#define B16pll_ctrl_FREQ_OFFSET 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET 9
#define LSb16pll_ctrl_FREQ_OFFSET 9
#define bpll_ctrl_FREQ_OFFSET 17
#define MSK32pll_ctrl_FREQ_OFFSET 0x03FFFE00
#define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000B
#define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 26
#define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 10
#define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1
#define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x04000000
#define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000B
#define B16pll_ctrl_FREQ_OFFSET_VALID 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_VALID 27
#define LSb16pll_ctrl_FREQ_OFFSET_VALID 11
#define bpll_ctrl_FREQ_OFFSET_VALID 1
#define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x08000000
#define BA_pll_ctrl_SSC_CLK_EN 0x000B
#define B16pll_ctrl_SSC_CLK_EN 0x000A
#define LSb32pll_ctrl_SSC_CLK_EN 28
#define LSb16pll_ctrl_SSC_CLK_EN 12
#define bpll_ctrl_SSC_CLK_EN 1
#define MSK32pll_ctrl_SSC_CLK_EN 0x10000000
#define BA_pll_ctrl_SSC_MODE 0x000B
#define B16pll_ctrl_SSC_MODE 0x000A
#define LSb32pll_ctrl_SSC_MODE 29
#define LSb16pll_ctrl_SSC_MODE 13
#define bpll_ctrl_SSC_MODE 1
#define MSK32pll_ctrl_SSC_MODE 0x20000000
#define RA_pll_ctrl3 0x000C
#define BA_pll_ctrl_SSC_FREQ_DIV 0x000C
#define B16pll_ctrl_SSC_FREQ_DIV 0x000C
#define LSb32pll_ctrl_SSC_FREQ_DIV 0
#define LSb16pll_ctrl_SSC_FREQ_DIV 0
#define bpll_ctrl_SSC_FREQ_DIV 16
#define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF
#define BA_pll_ctrl_SSC_RNGE 0x000E
#define B16pll_ctrl_SSC_RNGE 0x000E
#define LSb32pll_ctrl_SSC_RNGE 16
#define LSb16pll_ctrl_SSC_RNGE 0
#define bpll_ctrl_SSC_RNGE 11
#define MSK32pll_ctrl_SSC_RNGE 0x07FF0000
#define BA_pll_ctrl_TEST_ANA 0x000F
#define B16pll_ctrl_TEST_ANA 0x000E
#define LSb32pll_ctrl_TEST_ANA 27
#define LSb16pll_ctrl_TEST_ANA 11
#define bpll_ctrl_TEST_ANA 4
#define MSK32pll_ctrl_TEST_ANA 0x78000000
#define RA_pll_ctrl4 0x0010
#define BA_pll_ctrl_RESERVE_IN 0x0010
#define B16pll_ctrl_RESERVE_IN 0x0010
#define LSb32pll_ctrl_RESERVE_IN 0
#define LSb16pll_ctrl_RESERVE_IN 0
#define bpll_ctrl_RESERVE_IN 8
#define MSK32pll_ctrl_RESERVE_IN 0x000000FF
///////////////////////////////////////////////////////////
#define RA_pll_status 0x0014
#define BA_pll_status_PLL_LOCK 0x0014
#define B16pll_status_PLL_LOCK 0x0014
#define LSb32pll_status_PLL_LOCK 0
#define LSb16pll_status_PLL_LOCK 0
#define bpll_status_PLL_LOCK 1
#define MSK32pll_status_PLL_LOCK 0x00000001
#define BA_pll_status_CLK_CFMOD 0x0014
#define B16pll_status_CLK_CFMOD 0x0014
#define LSb32pll_status_CLK_CFMOD 1
#define LSb16pll_status_CLK_CFMOD 1
#define bpll_status_CLK_CFMOD 1
#define MSK32pll_status_CLK_CFMOD 0x00000002
#define BA_pll_status_CLK_FMOD 0x0014
#define B16pll_status_CLK_FMOD 0x0014
#define LSb32pll_status_CLK_FMOD 2
#define LSb16pll_status_CLK_FMOD 2
#define bpll_status_CLK_FMOD 1
#define MSK32pll_status_CLK_FMOD 0x00000004
#define BA_pll_status_RESERVE_OUT 0x0014
#define B16pll_status_RESERVE_OUT 0x0014
#define LSb32pll_status_RESERVE_OUT 3
#define LSb16pll_status_RESERVE_OUT 3
#define bpll_status_RESERVE_OUT 8
#define MSK32pll_status_RESERVE_OUT 0x000007F8
///////////////////////////////////////////////////////////
typedef struct SIE_pll {
///////////////////////////////////////////////////////////
#define GET32pll_ctrl_PU(r32) _BFGET_(r32, 0, 0)
#define SET32pll_ctrl_PU(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_ctrl_PU(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_PU(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_RESET(r32) _BFGET_(r32, 1, 1)
#define SET32pll_ctrl_RESET(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_ctrl_RESET(r16) _BFGET_(r16, 1, 1)
#define SET16pll_ctrl_RESET(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_ctrl_AVDD1815_SEL(r32) _BFGET_(r32, 2, 2)
#define SET32pll_ctrl_AVDD1815_SEL(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_ctrl_AVDD1815_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16pll_ctrl_AVDD1815_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_ctrl_REFDIV(r32) _BFGET_(r32,11, 3)
#define SET32pll_ctrl_REFDIV(r32,v) _BFSET_(r32,11, 3,v)
#define GET16pll_ctrl_REFDIV(r16) _BFGET_(r16,11, 3)
#define SET16pll_ctrl_REFDIV(r16,v) _BFSET_(r16,11, 3,v)
#define GET32pll_ctrl_FBDIV(r32) _BFGET_(r32,20,12)
#define SET32pll_ctrl_FBDIV(r32,v) _BFSET_(r32,20,12,v)
#define GET32pll_ctrl_VDDM(r32) _BFGET_(r32,22,21)
#define SET32pll_ctrl_VDDM(r32,v) _BFSET_(r32,22,21,v)
#define GET16pll_ctrl_VDDM(r16) _BFGET_(r16, 6, 5)
#define SET16pll_ctrl_VDDM(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32pll_ctrl_VDDL(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_VDDL(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_VDDL(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_VDDL(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_ICP(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_ICP(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_ICP(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_ICP(r16,v) _BFSET_(r16,13,10,v)
#define GET32pll_ctrl_PLL_BW_SEL(r32) _BFGET_(r32,30,30)
#define SET32pll_ctrl_PLL_BW_SEL(r32,v) _BFSET_(r32,30,30,v)
#define GET16pll_ctrl_PLL_BW_SEL(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_PLL_BW_SEL(r16,v) _BFSET_(r16,14,14,v)
#define w32pll_ctrl {\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_AVDD1815_SEL : 1;\
UNSG32 uctrl_REFDIV : 9;\
UNSG32 uctrl_FBDIV : 9;\
UNSG32 uctrl_VDDM : 2;\
UNSG32 uctrl_VDDL : 3;\
UNSG32 uctrl_ICP : 4;\
UNSG32 uctrl_PLL_BW_SEL : 1;\
UNSG32 RSVDx0_b31 : 1;\
}
union { UNSG32 u32pll_ctrl;
struct w32pll_ctrl;
};
#define GET32pll_ctrl_KVCO(r32) _BFGET_(r32, 3, 0)
#define SET32pll_ctrl_KVCO(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16pll_ctrl_KVCO(r16) _BFGET_(r16, 3, 0)
#define SET16pll_ctrl_KVCO(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32pll_ctrl_CTUNE(r32) _BFGET_(r32, 5, 4)
#define SET32pll_ctrl_CTUNE(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16pll_ctrl_CTUNE(r16) _BFGET_(r16, 5, 4)
#define SET16pll_ctrl_CTUNE(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32) _BFGET_(r32, 8, 6)
#define SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16) _BFGET_(r16, 8, 6)
#define SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32) _BFGET_(r32,11, 9)
#define SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v) _BFSET_(r32,11, 9,v)
#define GET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16) _BFGET_(r16,11, 9)
#define SET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16,v) _BFSET_(r16,11, 9,v)
#define GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32) _BFGET_(r32,12,12)
#define SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v) _BFSET_(r32,12,12,v)
#define GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_CLKOUT_DIFF_EN(r32) _BFGET_(r32,13,13)
#define SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v) _BFSET_(r32,13,13,v)
#define GET16pll_ctrl_CLKOUT_DIFF_EN(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32pll_ctrl_BYPASS_EN(r32) _BFGET_(r32,14,14)
#define SET32pll_ctrl_BYPASS_EN(r32,v) _BFSET_(r32,14,14,v)
#define GET16pll_ctrl_BYPASS_EN(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_BYPASS_EN(r16,v) _BFSET_(r16,14,14,v)
#define GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32) _BFGET_(r32,15,15)
#define SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v) _BFSET_(r32,15,15,v)
#define GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16) _BFGET_(r16,15,15)
#define SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v) _BFSET_(r16,15,15,v)
#define GET32pll_ctrl_FBCLK_EXT_SEL(r32) _BFGET_(r32,16,16)
#define SET32pll_ctrl_FBCLK_EXT_SEL(r32,v) _BFSET_(r32,16,16,v)
#define GET16pll_ctrl_FBCLK_EXT_SEL(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_FBCLK_EXT_SEL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_FBCDLY(r32) _BFGET_(r32,22,17)
#define SET32pll_ctrl_FBCDLY(r32,v) _BFSET_(r32,22,17,v)
#define GET16pll_ctrl_FBCDLY(r16) _BFGET_(r16, 6, 1)
#define SET16pll_ctrl_FBCDLY(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32pll_ctrl_FD(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_FD(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_FD(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_FD(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_INTPI(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_INTPI(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_INTPI(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_INTPI(r16,v) _BFSET_(r16,13,10,v)
#define w32pll_ctrl1 {\
UNSG32 uctrl_KVCO : 4;\
UNSG32 uctrl_CTUNE : 2;\
UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SE_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SOURCE_SEL : 1;\
UNSG32 uctrl_CLKOUT_DIFF_EN : 1;\
UNSG32 uctrl_BYPASS_EN : 1;\
UNSG32 uctrl_CLKOUT_SE_GATING_EN : 1;\
UNSG32 uctrl_FBCLK_EXT_SEL : 1;\
UNSG32 uctrl_FBCDLY : 6;\
UNSG32 uctrl_FD : 3;\
UNSG32 uctrl_INTPI : 4;\
UNSG32 RSVDx4_b30 : 2;\
}
union { UNSG32 u32pll_ctrl1;
struct w32pll_ctrl1;
};
#define GET32pll_ctrl_INTPR(r32) _BFGET_(r32, 2, 0)
#define SET32pll_ctrl_INTPR(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16pll_ctrl_INTPR(r16) _BFGET_(r16, 2, 0)
#define SET16pll_ctrl_INTPR(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32pll_ctrl_PI_EN(r32) _BFGET_(r32, 3, 3)
#define SET32pll_ctrl_PI_EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pll_ctrl_PI_EN(r16) _BFGET_(r16, 3, 3)
#define SET16pll_ctrl_PI_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32pll_ctrl_PI_LOOP_MODE(r32) _BFGET_(r32, 4, 4)
#define SET32pll_ctrl_PI_LOOP_MODE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16pll_ctrl_PI_LOOP_MODE(r16) _BFGET_(r16, 4, 4)
#define SET16pll_ctrl_PI_LOOP_MODE(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32pll_ctrl_CLK_DET_EN(r32) _BFGET_(r32, 5, 5)
#define SET32pll_ctrl_CLK_DET_EN(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16pll_ctrl_CLK_DET_EN(r16) _BFGET_(r16, 5, 5)
#define SET16pll_ctrl_CLK_DET_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32pll_ctrl_RESET_PI(r32) _BFGET_(r32, 6, 6)
#define SET32pll_ctrl_RESET_PI(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16pll_ctrl_RESET_PI(r16) _BFGET_(r16, 6, 6)
#define SET16pll_ctrl_RESET_PI(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32pll_ctrl_RESET_SSC(r32) _BFGET_(r32, 7, 7)
#define SET32pll_ctrl_RESET_SSC(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16pll_ctrl_RESET_SSC(r16) _BFGET_(r16, 7, 7)
#define SET16pll_ctrl_RESET_SSC(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32pll_ctrl_FREQ_OFFSET_EN(r32) _BFGET_(r32, 8, 8)
#define SET32pll_ctrl_FREQ_OFFSET_EN(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16pll_ctrl_FREQ_OFFSET_EN(r16) _BFGET_(r16, 8, 8)
#define SET16pll_ctrl_FREQ_OFFSET_EN(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32pll_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,25, 9)
#define SET32pll_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,25, 9,v)
#define GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32) _BFGET_(r32,26,26)
#define SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v) _BFSET_(r32,26,26,v)
#define GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16) _BFGET_(r16,10,10)
#define SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v) _BFSET_(r16,10,10,v)
#define GET32pll_ctrl_FREQ_OFFSET_VALID(r32) _BFGET_(r32,27,27)
#define SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v) _BFSET_(r32,27,27,v)
#define GET16pll_ctrl_FREQ_OFFSET_VALID(r16) _BFGET_(r16,11,11)
#define SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v) _BFSET_(r16,11,11,v)
#define GET32pll_ctrl_SSC_CLK_EN(r32) _BFGET_(r32,28,28)
#define SET32pll_ctrl_SSC_CLK_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16pll_ctrl_SSC_CLK_EN(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_SSC_CLK_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_SSC_MODE(r32) _BFGET_(r32,29,29)
#define SET32pll_ctrl_SSC_MODE(r32,v) _BFSET_(r32,29,29,v)
#define GET16pll_ctrl_SSC_MODE(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_SSC_MODE(r16,v) _BFSET_(r16,13,13,v)
#define w32pll_ctrl2 {\
UNSG32 uctrl_INTPR : 3;\
UNSG32 uctrl_PI_EN : 1;\
UNSG32 uctrl_PI_LOOP_MODE : 1;\
UNSG32 uctrl_CLK_DET_EN : 1;\
UNSG32 uctrl_RESET_PI : 1;\
UNSG32 uctrl_RESET_SSC : 1;\
UNSG32 uctrl_FREQ_OFFSET_EN : 1;\
UNSG32 uctrl_FREQ_OFFSET : 17;\
UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION : 1;\
UNSG32 uctrl_FREQ_OFFSET_VALID : 1;\
UNSG32 uctrl_SSC_CLK_EN : 1;\
UNSG32 uctrl_SSC_MODE : 1;\
UNSG32 RSVDx8_b30 : 2;\
}
union { UNSG32 u32pll_ctrl2;
struct w32pll_ctrl2;
};
#define GET32pll_ctrl_SSC_FREQ_DIV(r32) _BFGET_(r32,15, 0)
#define SET32pll_ctrl_SSC_FREQ_DIV(r32,v) _BFSET_(r32,15, 0,v)
#define GET16pll_ctrl_SSC_FREQ_DIV(r16) _BFGET_(r16,15, 0)
#define SET16pll_ctrl_SSC_FREQ_DIV(r16,v) _BFSET_(r16,15, 0,v)
#define GET32pll_ctrl_SSC_RNGE(r32) _BFGET_(r32,26,16)
#define SET32pll_ctrl_SSC_RNGE(r32,v) _BFSET_(r32,26,16,v)
#define GET16pll_ctrl_SSC_RNGE(r16) _BFGET_(r16,10, 0)
#define SET16pll_ctrl_SSC_RNGE(r16,v) _BFSET_(r16,10, 0,v)
#define GET32pll_ctrl_TEST_ANA(r32) _BFGET_(r32,30,27)
#define SET32pll_ctrl_TEST_ANA(r32,v) _BFSET_(r32,30,27,v)
#define GET16pll_ctrl_TEST_ANA(r16) _BFGET_(r16,14,11)
#define SET16pll_ctrl_TEST_ANA(r16,v) _BFSET_(r16,14,11,v)
#define w32pll_ctrl3 {\
UNSG32 uctrl_SSC_FREQ_DIV : 16;\
UNSG32 uctrl_SSC_RNGE : 11;\
UNSG32 uctrl_TEST_ANA : 4;\
UNSG32 RSVDxC_b31 : 1;\
}
union { UNSG32 u32pll_ctrl3;
struct w32pll_ctrl3;
};
#define GET32pll_ctrl_RESERVE_IN(r32) _BFGET_(r32, 7, 0)
#define SET32pll_ctrl_RESERVE_IN(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16pll_ctrl_RESERVE_IN(r16) _BFGET_(r16, 7, 0)
#define SET16pll_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 7, 0,v)
#define w32pll_ctrl4 {\
UNSG32 uctrl_RESERVE_IN : 8;\
UNSG32 RSVDx10_b8 : 24;\
}
union { UNSG32 u32pll_ctrl4;
struct w32pll_ctrl4;
};
///////////////////////////////////////////////////////////
#define GET32pll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32pll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16pll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_status_CLK_CFMOD(r32) _BFGET_(r32, 1, 1)
#define SET32pll_status_CLK_CFMOD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_status_CLK_CFMOD(r16) _BFGET_(r16, 1, 1)
#define SET16pll_status_CLK_CFMOD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_status_CLK_FMOD(r32) _BFGET_(r32, 2, 2)
#define SET32pll_status_CLK_FMOD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_status_CLK_FMOD(r16) _BFGET_(r16, 2, 2)
#define SET16pll_status_CLK_FMOD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_status_RESERVE_OUT(r32) _BFGET_(r32,10, 3)
#define SET32pll_status_RESERVE_OUT(r32,v) _BFSET_(r32,10, 3,v)
#define GET16pll_status_RESERVE_OUT(r16) _BFGET_(r16,10, 3)
#define SET16pll_status_RESERVE_OUT(r16,v) _BFSET_(r16,10, 3,v)
#define w32pll_status {\
UNSG32 ustatus_PLL_LOCK : 1;\
UNSG32 ustatus_CLK_CFMOD : 1;\
UNSG32 ustatus_CLK_FMOD : 1;\
UNSG32 ustatus_RESERVE_OUT : 8;\
UNSG32 RSVDx14_b11 : 21;\
}
union { UNSG32 u32pll_status;
struct w32pll_status;
};
///////////////////////////////////////////////////////////
} SIE_pll;
typedef union T32pll_ctrl
{ UNSG32 u32;
struct w32pll_ctrl;
} T32pll_ctrl;
typedef union T32pll_ctrl1
{ UNSG32 u32;
struct w32pll_ctrl1;
} T32pll_ctrl1;
typedef union T32pll_ctrl2
{ UNSG32 u32;
struct w32pll_ctrl2;
} T32pll_ctrl2;
typedef union T32pll_ctrl3
{ UNSG32 u32;
struct w32pll_ctrl3;
} T32pll_ctrl3;
typedef union T32pll_ctrl4
{ UNSG32 u32;
struct w32pll_ctrl4;
} T32pll_ctrl4;
typedef union T32pll_status
{ UNSG32 u32;
struct w32pll_status;
} T32pll_status;
///////////////////////////////////////////////////////////
typedef union Tpll_ctrl
{ UNSG32 u32[5];
struct {
struct w32pll_ctrl;
struct w32pll_ctrl1;
struct w32pll_ctrl2;
struct w32pll_ctrl3;
struct w32pll_ctrl4;
};
} Tpll_ctrl;
typedef union Tpll_status
{ UNSG32 u32[1];
struct {
struct w32pll_status;
};
} Tpll_status;
///////////////////////////////////////////////////////////
SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pll_reset(SIE_pll *p);
SIGN32 pll_cmp (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pll_print(p, pfx,hLOG) pll_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: ssPll.h
////////////////////////////////////////////////////////////