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nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP / vpp.h
blob: 746d9f7b50c770e5548bedc9d4eeda4345bbfe00 [file] [log] [blame]
/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: vpp.h
////////////////////////////////////////////////////////////
#ifndef vpp_h
#define vpp_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE oneReg (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (R-)
/// %unsigned 32 0x00000000
/// ###
/// * One Register in K2 block.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_oneReg
#define h_oneReg (){}
#define BA_oneReg_0x00000000 0x0000
#define B16oneReg_0x00000000 0x0000
#define LSb32oneReg_0x00000000 0
#define LSb16oneReg_0x00000000 0
#define boneReg_0x00000000 32
#define MSK32oneReg_0x00000000 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_oneReg {
///////////////////////////////////////////////////////////
#define GET32oneReg_0x00000000(r32) _BFGET_(r32,31, 0)
#define SET32oneReg_0x00000000(r32,v) _BFSET_(r32,31, 0,v)
UNSG32 u_0x00000000 : 32;
///////////////////////////////////////////////////////////
} SIE_oneReg;
///////////////////////////////////////////////////////////
SIGN32 oneReg_drvrd(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 oneReg_drvwr(SIE_oneReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void oneReg_reset(SIE_oneReg *p);
SIGN32 oneReg_cmp (SIE_oneReg *p, SIE_oneReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define oneReg_check(p,pie,pfx,hLOG) oneReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define oneReg_print(p, pfx,hLOG) oneReg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: oneReg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE VPP_REG (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 dummy
/// $oneReg dummy REG [16384]
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 65536B, bits: 524288b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_VPP_REG
#define h_VPP_REG (){}
#define RA_VPP_REG_dummy 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_VPP_REG {
///////////////////////////////////////////////////////////
SIE_oneReg ie_dummy[16384];
///////////////////////////////////////////////////////////
} SIE_VPP_REG;
///////////////////////////////////////////////////////////
SIGN32 VPP_REG_drvrd(SIE_VPP_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 VPP_REG_drvwr(SIE_VPP_REG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void VPP_REG_reset(SIE_VPP_REG *p);
SIGN32 VPP_REG_cmp (SIE_VPP_REG *p, SIE_VPP_REG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define VPP_REG_check(p,pie,pfx,hLOG) VPP_REG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define VPP_REG_print(p, pfx,hLOG) VPP_REG_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: VPP_REG
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CLK (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P)
/// %unsigned 1 clkSwitch 0x1
/// : SrcClk 0x0
/// : DivClk 0x1
/// ###
/// * Selects between source clock & divider clock
/// ###
/// %unsigned 1 clkD3Switch 0x0
/// : NonDiv3Clk 0x0
/// : Div3Clk 0x1
/// ###
/// * Selects between non-divide by-3 vs divide by-3 clocks.
/// ###
/// %unsigned 1 clkEn 0x1
/// : disable 0x0
/// : enable 0x1
/// ###
/// * disable/enable control.
/// ###
/// %unsigned 3 clkSel 0x1
/// : d2 0x1
/// : d4 0x2
/// : d6 0x3
/// : d8 0x4
/// : d12 0x5
/// ###
/// * clock selection.
/// ###
/// %% 26 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CLK
#define h_CLK (){}
#define RA_CLK_ctrl 0x0000
#define BA_CLK_ctrl_clkSwitch 0x0000
#define B16CLK_ctrl_clkSwitch 0x0000
#define LSb32CLK_ctrl_clkSwitch 0
#define LSb16CLK_ctrl_clkSwitch 0
#define bCLK_ctrl_clkSwitch 1
#define MSK32CLK_ctrl_clkSwitch 0x00000001
#define CLK_ctrl_clkSwitch_SrcClk 0x0
#define CLK_ctrl_clkSwitch_DivClk 0x1
#define BA_CLK_ctrl_clkD3Switch 0x0000
#define B16CLK_ctrl_clkD3Switch 0x0000
#define LSb32CLK_ctrl_clkD3Switch 1
#define LSb16CLK_ctrl_clkD3Switch 1
#define bCLK_ctrl_clkD3Switch 1
#define MSK32CLK_ctrl_clkD3Switch 0x00000002
#define CLK_ctrl_clkD3Switch_NonDiv3Clk 0x0
#define CLK_ctrl_clkD3Switch_Div3Clk 0x1
#define BA_CLK_ctrl_clkEn 0x0000
#define B16CLK_ctrl_clkEn 0x0000
#define LSb32CLK_ctrl_clkEn 2
#define LSb16CLK_ctrl_clkEn 2
#define bCLK_ctrl_clkEn 1
#define MSK32CLK_ctrl_clkEn 0x00000004
#define CLK_ctrl_clkEn_disable 0x0
#define CLK_ctrl_clkEn_enable 0x1
#define BA_CLK_ctrl_clkSel 0x0000
#define B16CLK_ctrl_clkSel 0x0000
#define LSb32CLK_ctrl_clkSel 3
#define LSb16CLK_ctrl_clkSel 3
#define bCLK_ctrl_clkSel 3
#define MSK32CLK_ctrl_clkSel 0x00000038
#define CLK_ctrl_clkSel_d2 0x1
#define CLK_ctrl_clkSel_d4 0x2
#define CLK_ctrl_clkSel_d6 0x3
#define CLK_ctrl_clkSel_d8 0x4
#define CLK_ctrl_clkSel_d12 0x5
///////////////////////////////////////////////////////////
typedef struct SIE_CLK {
///////////////////////////////////////////////////////////
#define GET32CLK_ctrl_clkSwitch(r32) _BFGET_(r32, 0, 0)
#define SET32CLK_ctrl_clkSwitch(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CLK_ctrl_clkSwitch(r16) _BFGET_(r16, 0, 0)
#define SET16CLK_ctrl_clkSwitch(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CLK_ctrl_clkD3Switch(r32) _BFGET_(r32, 1, 1)
#define SET32CLK_ctrl_clkD3Switch(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CLK_ctrl_clkD3Switch(r16) _BFGET_(r16, 1, 1)
#define SET16CLK_ctrl_clkD3Switch(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CLK_ctrl_clkEn(r32) _BFGET_(r32, 2, 2)
#define SET32CLK_ctrl_clkEn(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CLK_ctrl_clkEn(r16) _BFGET_(r16, 2, 2)
#define SET16CLK_ctrl_clkEn(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CLK_ctrl_clkSel(r32) _BFGET_(r32, 5, 3)
#define SET32CLK_ctrl_clkSel(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16CLK_ctrl_clkSel(r16) _BFGET_(r16, 5, 3)
#define SET16CLK_ctrl_clkSel(r16,v) _BFSET_(r16, 5, 3,v)
#define w32CLK_ctrl {\
UNSG32 uctrl_clkSwitch : 1;\
UNSG32 uctrl_clkD3Switch : 1;\
UNSG32 uctrl_clkEn : 1;\
UNSG32 uctrl_clkSel : 3;\
UNSG32 RSVDx0_b6 : 26;\
}
union { UNSG32 u32CLK_ctrl;
struct w32CLK_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_CLK;
typedef union T32CLK_ctrl
{ UNSG32 u32;
struct w32CLK_ctrl;
} T32CLK_ctrl;
///////////////////////////////////////////////////////////
typedef union TCLK_ctrl
{ UNSG32 u32[1];
struct {
struct w32CLK_ctrl;
};
} TCLK_ctrl;
///////////////////////////////////////////////////////////
SIGN32 CLK_drvrd(SIE_CLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CLK_drvwr(SIE_CLK *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CLK_reset(SIE_CLK *p);
SIGN32 CLK_cmp (SIE_CLK *p, SIE_CLK *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CLK_check(p,pie,pfx,hLOG) CLK_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CLK_print(p, pfx,hLOG) CLK_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CLK
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE FE_BE (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 FIFO_CTRL (P)
/// %unsigned 8 fifo_ctrl 0x0
/// %% 24 # Stuffing bits...
/// @ 0x00004 LRST (P)
/// %unsigned 12 lrst 0x0
/// ###
/// * This register is used to generate the line reset for AUX scaler (FRC5) in the horizontal blanking region.
/// * Value of this register should be [(CPCB0 Htotal – CPCB0 Hactive)/2]
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00008 FRST (P)
/// %unsigned 8 frst 0x0
/// ###
/// * This register is used to generate the frame reset for AUX scaler (FRC5) in the vertical blanking region.
/// * Value of this register should be [(CPCB0 Vtotal – CPCB0 Vactive)/2]
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0000C SYNC_CTRL (P)
/// %unsigned 8 sync_ctrl 0x0
/// ###
/// * Don't care when CPCB2 is working in free-running mode, which is the case for Berlin.
/// ###
/// %% 24 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 36b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_FE_BE
#define h_FE_BE (){}
#define RA_FE_BE_FIFO_CTRL 0x0000
#define BA_FE_BE_FIFO_CTRL_fifo_ctrl 0x0000
#define B16FE_BE_FIFO_CTRL_fifo_ctrl 0x0000
#define LSb32FE_BE_FIFO_CTRL_fifo_ctrl 0
#define LSb16FE_BE_FIFO_CTRL_fifo_ctrl 0
#define bFE_BE_FIFO_CTRL_fifo_ctrl 8
#define MSK32FE_BE_FIFO_CTRL_fifo_ctrl 0x000000FF
///////////////////////////////////////////////////////////
#define RA_FE_BE_LRST 0x0004
#define BA_FE_BE_LRST_lrst 0x0004
#define B16FE_BE_LRST_lrst 0x0004
#define LSb32FE_BE_LRST_lrst 0
#define LSb16FE_BE_LRST_lrst 0
#define bFE_BE_LRST_lrst 12
#define MSK32FE_BE_LRST_lrst 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_FE_BE_FRST 0x0008
#define BA_FE_BE_FRST_frst 0x0008
#define B16FE_BE_FRST_frst 0x0008
#define LSb32FE_BE_FRST_frst 0
#define LSb16FE_BE_FRST_frst 0
#define bFE_BE_FRST_frst 8
#define MSK32FE_BE_FRST_frst 0x000000FF
///////////////////////////////////////////////////////////
#define RA_FE_BE_SYNC_CTRL 0x000C
#define BA_FE_BE_SYNC_CTRL_sync_ctrl 0x000C
#define B16FE_BE_SYNC_CTRL_sync_ctrl 0x000C
#define LSb32FE_BE_SYNC_CTRL_sync_ctrl 0
#define LSb16FE_BE_SYNC_CTRL_sync_ctrl 0
#define bFE_BE_SYNC_CTRL_sync_ctrl 8
#define MSK32FE_BE_SYNC_CTRL_sync_ctrl 0x000000FF
///////////////////////////////////////////////////////////
typedef struct SIE_FE_BE {
///////////////////////////////////////////////////////////
#define GET32FE_BE_FIFO_CTRL_fifo_ctrl(r32) _BFGET_(r32, 7, 0)
#define SET32FE_BE_FIFO_CTRL_fifo_ctrl(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16FE_BE_FIFO_CTRL_fifo_ctrl(r16) _BFGET_(r16, 7, 0)
#define SET16FE_BE_FIFO_CTRL_fifo_ctrl(r16,v) _BFSET_(r16, 7, 0,v)
#define w32FE_BE_FIFO_CTRL {\
UNSG32 uFIFO_CTRL_fifo_ctrl : 8;\
UNSG32 RSVDx0_b8 : 24;\
}
union { UNSG32 u32FE_BE_FIFO_CTRL;
struct w32FE_BE_FIFO_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32FE_BE_LRST_lrst(r32) _BFGET_(r32,11, 0)
#define SET32FE_BE_LRST_lrst(r32,v) _BFSET_(r32,11, 0,v)
#define GET16FE_BE_LRST_lrst(r16) _BFGET_(r16,11, 0)
#define SET16FE_BE_LRST_lrst(r16,v) _BFSET_(r16,11, 0,v)
#define w32FE_BE_LRST {\
UNSG32 uLRST_lrst : 12;\
UNSG32 RSVDx4_b12 : 20;\
}
union { UNSG32 u32FE_BE_LRST;
struct w32FE_BE_LRST;
};
///////////////////////////////////////////////////////////
#define GET32FE_BE_FRST_frst(r32) _BFGET_(r32, 7, 0)
#define SET32FE_BE_FRST_frst(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16FE_BE_FRST_frst(r16) _BFGET_(r16, 7, 0)
#define SET16FE_BE_FRST_frst(r16,v) _BFSET_(r16, 7, 0,v)
#define w32FE_BE_FRST {\
UNSG32 uFRST_frst : 8;\
UNSG32 RSVDx8_b8 : 24;\
}
union { UNSG32 u32FE_BE_FRST;
struct w32FE_BE_FRST;
};
///////////////////////////////////////////////////////////
#define GET32FE_BE_SYNC_CTRL_sync_ctrl(r32) _BFGET_(r32, 7, 0)
#define SET32FE_BE_SYNC_CTRL_sync_ctrl(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16FE_BE_SYNC_CTRL_sync_ctrl(r16) _BFGET_(r16, 7, 0)
#define SET16FE_BE_SYNC_CTRL_sync_ctrl(r16,v) _BFSET_(r16, 7, 0,v)
#define w32FE_BE_SYNC_CTRL {\
UNSG32 uSYNC_CTRL_sync_ctrl : 8;\
UNSG32 RSVDxC_b8 : 24;\
}
union { UNSG32 u32FE_BE_SYNC_CTRL;
struct w32FE_BE_SYNC_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_FE_BE;
typedef union T32FE_BE_FIFO_CTRL
{ UNSG32 u32;
struct w32FE_BE_FIFO_CTRL;
} T32FE_BE_FIFO_CTRL;
typedef union T32FE_BE_LRST
{ UNSG32 u32;
struct w32FE_BE_LRST;
} T32FE_BE_LRST;
typedef union T32FE_BE_FRST
{ UNSG32 u32;
struct w32FE_BE_FRST;
} T32FE_BE_FRST;
typedef union T32FE_BE_SYNC_CTRL
{ UNSG32 u32;
struct w32FE_BE_SYNC_CTRL;
} T32FE_BE_SYNC_CTRL;
///////////////////////////////////////////////////////////
typedef union TFE_BE_FIFO_CTRL
{ UNSG32 u32[1];
struct {
struct w32FE_BE_FIFO_CTRL;
};
} TFE_BE_FIFO_CTRL;
typedef union TFE_BE_LRST
{ UNSG32 u32[1];
struct {
struct w32FE_BE_LRST;
};
} TFE_BE_LRST;
typedef union TFE_BE_FRST
{ UNSG32 u32[1];
struct {
struct w32FE_BE_FRST;
};
} TFE_BE_FRST;
typedef union TFE_BE_SYNC_CTRL
{ UNSG32 u32[1];
struct {
struct w32FE_BE_SYNC_CTRL;
};
} TFE_BE_SYNC_CTRL;
///////////////////////////////////////////////////////////
SIGN32 FE_BE_drvrd(SIE_FE_BE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 FE_BE_drvwr(SIE_FE_BE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void FE_BE_reset(SIE_FE_BE *p);
SIGN32 FE_BE_cmp (SIE_FE_BE *p, SIE_FE_BE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define FE_BE_check(p,pie,pfx,hLOG) FE_BE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define FE_BE_print(p, pfx,hLOG) FE_BE_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: FE_BE
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE DVI_FE_BE (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 FIFO_CTRL (P)
/// %unsigned 8 fifo_ctrl 0x0
/// %% 24 # Stuffing bits...
/// @ 0x00004 LRST (P)
/// %unsigned 12 lrst 0x0
/// ###
/// * This register is used to generate the line reset for DVI VIP scaler (VIP_FRC) in the horizontal blanking region.
/// * Value of this register should be [(DVI Htotal – DVI Hactive)/2]
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00008 FRST (P)
/// %unsigned 8 frst 0x0
/// ###
/// * This register is used to generate the frame reset for DVI VIP scaler (VIP_FRC) in the vertical blanking region.
/// * Value of this register should be [(DVI Vtotal – DVI Vactive)/2]
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0000C SYNC_CTRL (P)
/// %unsigned 8 sync_ctrl 0x0
/// ###
/// * Don't care when VIP DVI is working in free-running mode, which is the case for Berlin.
/// ###
/// %% 24 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 36b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_DVI_FE_BE
#define h_DVI_FE_BE (){}
#define RA_DVI_FE_BE_FIFO_CTRL 0x0000
#define BA_DVI_FE_BE_FIFO_CTRL_fifo_ctrl 0x0000
#define B16DVI_FE_BE_FIFO_CTRL_fifo_ctrl 0x0000
#define LSb32DVI_FE_BE_FIFO_CTRL_fifo_ctrl 0
#define LSb16DVI_FE_BE_FIFO_CTRL_fifo_ctrl 0
#define bDVI_FE_BE_FIFO_CTRL_fifo_ctrl 8
#define MSK32DVI_FE_BE_FIFO_CTRL_fifo_ctrl 0x000000FF
///////////////////////////////////////////////////////////
#define RA_DVI_FE_BE_LRST 0x0004
#define BA_DVI_FE_BE_LRST_lrst 0x0004
#define B16DVI_FE_BE_LRST_lrst 0x0004
#define LSb32DVI_FE_BE_LRST_lrst 0
#define LSb16DVI_FE_BE_LRST_lrst 0
#define bDVI_FE_BE_LRST_lrst 12
#define MSK32DVI_FE_BE_LRST_lrst 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_DVI_FE_BE_FRST 0x0008
#define BA_DVI_FE_BE_FRST_frst 0x0008
#define B16DVI_FE_BE_FRST_frst 0x0008
#define LSb32DVI_FE_BE_FRST_frst 0
#define LSb16DVI_FE_BE_FRST_frst 0
#define bDVI_FE_BE_FRST_frst 8
#define MSK32DVI_FE_BE_FRST_frst 0x000000FF
///////////////////////////////////////////////////////////
#define RA_DVI_FE_BE_SYNC_CTRL 0x000C
#define BA_DVI_FE_BE_SYNC_CTRL_sync_ctrl 0x000C
#define B16DVI_FE_BE_SYNC_CTRL_sync_ctrl 0x000C
#define LSb32DVI_FE_BE_SYNC_CTRL_sync_ctrl 0
#define LSb16DVI_FE_BE_SYNC_CTRL_sync_ctrl 0
#define bDVI_FE_BE_SYNC_CTRL_sync_ctrl 8
#define MSK32DVI_FE_BE_SYNC_CTRL_sync_ctrl 0x000000FF
///////////////////////////////////////////////////////////
typedef struct SIE_DVI_FE_BE {
///////////////////////////////////////////////////////////
#define GET32DVI_FE_BE_FIFO_CTRL_fifo_ctrl(r32) _BFGET_(r32, 7, 0)
#define SET32DVI_FE_BE_FIFO_CTRL_fifo_ctrl(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16DVI_FE_BE_FIFO_CTRL_fifo_ctrl(r16) _BFGET_(r16, 7, 0)
#define SET16DVI_FE_BE_FIFO_CTRL_fifo_ctrl(r16,v) _BFSET_(r16, 7, 0,v)
#define w32DVI_FE_BE_FIFO_CTRL {\
UNSG32 uFIFO_CTRL_fifo_ctrl : 8;\
UNSG32 RSVDx0_b8 : 24;\
}
union { UNSG32 u32DVI_FE_BE_FIFO_CTRL;
struct w32DVI_FE_BE_FIFO_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32DVI_FE_BE_LRST_lrst(r32) _BFGET_(r32,11, 0)
#define SET32DVI_FE_BE_LRST_lrst(r32,v) _BFSET_(r32,11, 0,v)
#define GET16DVI_FE_BE_LRST_lrst(r16) _BFGET_(r16,11, 0)
#define SET16DVI_FE_BE_LRST_lrst(r16,v) _BFSET_(r16,11, 0,v)
#define w32DVI_FE_BE_LRST {\
UNSG32 uLRST_lrst : 12;\
UNSG32 RSVDx4_b12 : 20;\
}
union { UNSG32 u32DVI_FE_BE_LRST;
struct w32DVI_FE_BE_LRST;
};
///////////////////////////////////////////////////////////
#define GET32DVI_FE_BE_FRST_frst(r32) _BFGET_(r32, 7, 0)
#define SET32DVI_FE_BE_FRST_frst(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16DVI_FE_BE_FRST_frst(r16) _BFGET_(r16, 7, 0)
#define SET16DVI_FE_BE_FRST_frst(r16,v) _BFSET_(r16, 7, 0,v)
#define w32DVI_FE_BE_FRST {\
UNSG32 uFRST_frst : 8;\
UNSG32 RSVDx8_b8 : 24;\
}
union { UNSG32 u32DVI_FE_BE_FRST;
struct w32DVI_FE_BE_FRST;
};
///////////////////////////////////////////////////////////
#define GET32DVI_FE_BE_SYNC_CTRL_sync_ctrl(r32) _BFGET_(r32, 7, 0)
#define SET32DVI_FE_BE_SYNC_CTRL_sync_ctrl(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16DVI_FE_BE_SYNC_CTRL_sync_ctrl(r16) _BFGET_(r16, 7, 0)
#define SET16DVI_FE_BE_SYNC_CTRL_sync_ctrl(r16,v) _BFSET_(r16, 7, 0,v)
#define w32DVI_FE_BE_SYNC_CTRL {\
UNSG32 uSYNC_CTRL_sync_ctrl : 8;\
UNSG32 RSVDxC_b8 : 24;\
}
union { UNSG32 u32DVI_FE_BE_SYNC_CTRL;
struct w32DVI_FE_BE_SYNC_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_DVI_FE_BE;
typedef union T32DVI_FE_BE_FIFO_CTRL
{ UNSG32 u32;
struct w32DVI_FE_BE_FIFO_CTRL;
} T32DVI_FE_BE_FIFO_CTRL;
typedef union T32DVI_FE_BE_LRST
{ UNSG32 u32;
struct w32DVI_FE_BE_LRST;
} T32DVI_FE_BE_LRST;
typedef union T32DVI_FE_BE_FRST
{ UNSG32 u32;
struct w32DVI_FE_BE_FRST;
} T32DVI_FE_BE_FRST;
typedef union T32DVI_FE_BE_SYNC_CTRL
{ UNSG32 u32;
struct w32DVI_FE_BE_SYNC_CTRL;
} T32DVI_FE_BE_SYNC_CTRL;
///////////////////////////////////////////////////////////
typedef union TDVI_FE_BE_FIFO_CTRL
{ UNSG32 u32[1];
struct {
struct w32DVI_FE_BE_FIFO_CTRL;
};
} TDVI_FE_BE_FIFO_CTRL;
typedef union TDVI_FE_BE_LRST
{ UNSG32 u32[1];
struct {
struct w32DVI_FE_BE_LRST;
};
} TDVI_FE_BE_LRST;
typedef union TDVI_FE_BE_FRST
{ UNSG32 u32[1];
struct {
struct w32DVI_FE_BE_FRST;
};
} TDVI_FE_BE_FRST;
typedef union TDVI_FE_BE_SYNC_CTRL
{ UNSG32 u32[1];
struct {
struct w32DVI_FE_BE_SYNC_CTRL;
};
} TDVI_FE_BE_SYNC_CTRL;
///////////////////////////////////////////////////////////
SIGN32 DVI_FE_BE_drvrd(SIE_DVI_FE_BE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 DVI_FE_BE_drvwr(SIE_DVI_FE_BE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void DVI_FE_BE_reset(SIE_DVI_FE_BE *p);
SIGN32 DVI_FE_BE_cmp (SIE_DVI_FE_BE *p, SIE_DVI_FE_BE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define DVI_FE_BE_check(p,pie,pfx,hLOG) DVI_FE_BE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define DVI_FE_BE_print(p, pfx,hLOG) DVI_FE_BE_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: DVI_FE_BE
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE DAC_ctrl (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl0 (P)
/// %unsigned 8 g_a 0xD6
/// ###
/// * 8 bit gain DAC control
/// ###
/// %unsigned 1 pu_a 0x0
/// ###
/// * powers up VDAC
/// ###
/// %unsigned 1 pu_refgen 0x0
/// ###
/// * power up signal of reference generator
/// ###
/// %unsigned 1 force_bg_start 0x0
/// ###
/// * digital input force bandgap startup
/// ###
/// %unsigned 8 tst 0x0
/// ###
/// * 8 bit digital control for test purposes
/// ###
/// %unsigned 4 vbg_val 0x0
/// ###
/// * 4 bit digital control for trimming bandgap voltage
/// ###
/// %% 9 # Stuffing bits...
/// @ 0x00004 ctrl1 (P)
/// %unsigned 32 Reserved 0x0
/// ###
/// * Reserved for future use
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 55b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_DAC_ctrl
#define h_DAC_ctrl (){}
#define RA_DAC_ctrl_ctrl0 0x0000
#define BA_DAC_ctrl_ctrl0_g_a 0x0000
#define B16DAC_ctrl_ctrl0_g_a 0x0000
#define LSb32DAC_ctrl_ctrl0_g_a 0
#define LSb16DAC_ctrl_ctrl0_g_a 0
#define bDAC_ctrl_ctrl0_g_a 8
#define MSK32DAC_ctrl_ctrl0_g_a 0x000000FF
#define BA_DAC_ctrl_ctrl0_pu_a 0x0001
#define B16DAC_ctrl_ctrl0_pu_a 0x0000
#define LSb32DAC_ctrl_ctrl0_pu_a 8
#define LSb16DAC_ctrl_ctrl0_pu_a 8
#define bDAC_ctrl_ctrl0_pu_a 1
#define MSK32DAC_ctrl_ctrl0_pu_a 0x00000100
#define BA_DAC_ctrl_ctrl0_pu_refgen 0x0001
#define B16DAC_ctrl_ctrl0_pu_refgen 0x0000
#define LSb32DAC_ctrl_ctrl0_pu_refgen 9
#define LSb16DAC_ctrl_ctrl0_pu_refgen 9
#define bDAC_ctrl_ctrl0_pu_refgen 1
#define MSK32DAC_ctrl_ctrl0_pu_refgen 0x00000200
#define BA_DAC_ctrl_ctrl0_force_bg_start 0x0001
#define B16DAC_ctrl_ctrl0_force_bg_start 0x0000
#define LSb32DAC_ctrl_ctrl0_force_bg_start 10
#define LSb16DAC_ctrl_ctrl0_force_bg_start 10
#define bDAC_ctrl_ctrl0_force_bg_start 1
#define MSK32DAC_ctrl_ctrl0_force_bg_start 0x00000400
#define BA_DAC_ctrl_ctrl0_tst 0x0001
#define B16DAC_ctrl_ctrl0_tst 0x0000
#define LSb32DAC_ctrl_ctrl0_tst 11
#define LSb16DAC_ctrl_ctrl0_tst 11
#define bDAC_ctrl_ctrl0_tst 8
#define MSK32DAC_ctrl_ctrl0_tst 0x0007F800
#define BA_DAC_ctrl_ctrl0_vbg_val 0x0002
#define B16DAC_ctrl_ctrl0_vbg_val 0x0002
#define LSb32DAC_ctrl_ctrl0_vbg_val 19
#define LSb16DAC_ctrl_ctrl0_vbg_val 3
#define bDAC_ctrl_ctrl0_vbg_val 4
#define MSK32DAC_ctrl_ctrl0_vbg_val 0x00780000
///////////////////////////////////////////////////////////
#define RA_DAC_ctrl_ctrl1 0x0004
#define BA_DAC_ctrl_ctrl1_Reserved 0x0004
#define B16DAC_ctrl_ctrl1_Reserved 0x0004
#define LSb32DAC_ctrl_ctrl1_Reserved 0
#define LSb16DAC_ctrl_ctrl1_Reserved 0
#define bDAC_ctrl_ctrl1_Reserved 32
#define MSK32DAC_ctrl_ctrl1_Reserved 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_DAC_ctrl {
///////////////////////////////////////////////////////////
#define GET32DAC_ctrl_ctrl0_g_a(r32) _BFGET_(r32, 7, 0)
#define SET32DAC_ctrl_ctrl0_g_a(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16DAC_ctrl_ctrl0_g_a(r16) _BFGET_(r16, 7, 0)
#define SET16DAC_ctrl_ctrl0_g_a(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32DAC_ctrl_ctrl0_pu_a(r32) _BFGET_(r32, 8, 8)
#define SET32DAC_ctrl_ctrl0_pu_a(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16DAC_ctrl_ctrl0_pu_a(r16) _BFGET_(r16, 8, 8)
#define SET16DAC_ctrl_ctrl0_pu_a(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32DAC_ctrl_ctrl0_pu_refgen(r32) _BFGET_(r32, 9, 9)
#define SET32DAC_ctrl_ctrl0_pu_refgen(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16DAC_ctrl_ctrl0_pu_refgen(r16) _BFGET_(r16, 9, 9)
#define SET16DAC_ctrl_ctrl0_pu_refgen(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32DAC_ctrl_ctrl0_force_bg_start(r32) _BFGET_(r32,10,10)
#define SET32DAC_ctrl_ctrl0_force_bg_start(r32,v) _BFSET_(r32,10,10,v)
#define GET16DAC_ctrl_ctrl0_force_bg_start(r16) _BFGET_(r16,10,10)
#define SET16DAC_ctrl_ctrl0_force_bg_start(r16,v) _BFSET_(r16,10,10,v)
#define GET32DAC_ctrl_ctrl0_tst(r32) _BFGET_(r32,18,11)
#define SET32DAC_ctrl_ctrl0_tst(r32,v) _BFSET_(r32,18,11,v)
#define GET32DAC_ctrl_ctrl0_vbg_val(r32) _BFGET_(r32,22,19)
#define SET32DAC_ctrl_ctrl0_vbg_val(r32,v) _BFSET_(r32,22,19,v)
#define GET16DAC_ctrl_ctrl0_vbg_val(r16) _BFGET_(r16, 6, 3)
#define SET16DAC_ctrl_ctrl0_vbg_val(r16,v) _BFSET_(r16, 6, 3,v)
#define w32DAC_ctrl_ctrl0 {\
UNSG32 uctrl0_g_a : 8;\
UNSG32 uctrl0_pu_a : 1;\
UNSG32 uctrl0_pu_refgen : 1;\
UNSG32 uctrl0_force_bg_start : 1;\
UNSG32 uctrl0_tst : 8;\
UNSG32 uctrl0_vbg_val : 4;\
UNSG32 RSVDx0_b23 : 9;\
}
union { UNSG32 u32DAC_ctrl_ctrl0;
struct w32DAC_ctrl_ctrl0;
};
///////////////////////////////////////////////////////////
#define GET32DAC_ctrl_ctrl1_Reserved(r32) _BFGET_(r32,31, 0)
#define SET32DAC_ctrl_ctrl1_Reserved(r32,v) _BFSET_(r32,31, 0,v)
#define w32DAC_ctrl_ctrl1 {\
UNSG32 uctrl1_Reserved : 32;\
}
union { UNSG32 u32DAC_ctrl_ctrl1;
struct w32DAC_ctrl_ctrl1;
};
///////////////////////////////////////////////////////////
} SIE_DAC_ctrl;
typedef union T32DAC_ctrl_ctrl0
{ UNSG32 u32;
struct w32DAC_ctrl_ctrl0;
} T32DAC_ctrl_ctrl0;
typedef union T32DAC_ctrl_ctrl1
{ UNSG32 u32;
struct w32DAC_ctrl_ctrl1;
} T32DAC_ctrl_ctrl1;
///////////////////////////////////////////////////////////
typedef union TDAC_ctrl_ctrl0
{ UNSG32 u32[1];
struct {
struct w32DAC_ctrl_ctrl0;
};
} TDAC_ctrl_ctrl0;
typedef union TDAC_ctrl_ctrl1
{ UNSG32 u32[1];
struct {
struct w32DAC_ctrl_ctrl1;
};
} TDAC_ctrl_ctrl1;
///////////////////////////////////////////////////////////
SIGN32 DAC_ctrl_drvrd(SIE_DAC_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 DAC_ctrl_drvwr(SIE_DAC_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void DAC_ctrl_reset(SIE_DAC_ctrl *p);
SIGN32 DAC_ctrl_cmp (SIE_DAC_ctrl *p, SIE_DAC_ctrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define DAC_ctrl_check(p,pie,pfx,hLOG) DAC_ctrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define DAC_ctrl_print(p, pfx,hLOG) DAC_ctrl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: DAC_ctrl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE DAC_sts (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (R-)
/// %unsigned 8 Reserved 0x0
/// %% 24 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 8b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_DAC_sts
#define h_DAC_sts (){}
#define BA_DAC_sts_Reserved 0x0000
#define B16DAC_sts_Reserved 0x0000
#define LSb32DAC_sts_Reserved 0
#define LSb16DAC_sts_Reserved 0
#define bDAC_sts_Reserved 8
#define MSK32DAC_sts_Reserved 0x000000FF
///////////////////////////////////////////////////////////
typedef struct SIE_DAC_sts {
///////////////////////////////////////////////////////////
#define GET32DAC_sts_Reserved(r32) _BFGET_(r32, 7, 0)
#define SET32DAC_sts_Reserved(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16DAC_sts_Reserved(r16) _BFGET_(r16, 7, 0)
#define SET16DAC_sts_Reserved(r16,v) _BFSET_(r16, 7, 0,v)
UNSG32 u_Reserved : 8;
UNSG32 RSVDx0_b8 : 24;
///////////////////////////////////////////////////////////
} SIE_DAC_sts;
///////////////////////////////////////////////////////////
SIGN32 DAC_sts_drvrd(SIE_DAC_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 DAC_sts_drvwr(SIE_DAC_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void DAC_sts_reset(SIE_DAC_sts *p);
SIGN32 DAC_sts_cmp (SIE_DAC_sts *p, SIE_DAC_sts *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define DAC_sts_check(p,pie,pfx,hLOG) DAC_sts_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define DAC_sts_print(p, pfx,hLOG) DAC_sts_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: DAC_sts
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE VDAC_ctrl biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 a
/// $DAC_ctrl a REG
/// @ 0x00008 clk (P)
/// %unsigned 3 N 0x0
/// ###
/// * N to select gdac_ck/2^N clock
/// ###
/// %unsigned 1 En 0x1
/// ###
/// * Enables clock
/// ###
/// %unsigned 1 Switch 0x0
/// ###
/// * Enables clock switching
/// ###
/// %% 27 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 12B, bits: 60b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_VDAC_ctrl
#define h_VDAC_ctrl (){}
#define RA_VDAC_ctrl_a 0x0000
///////////////////////////////////////////////////////////
#define RA_VDAC_ctrl_clk 0x0008
#define BA_VDAC_ctrl_clk_N 0x0008
#define B16VDAC_ctrl_clk_N 0x0008
#define LSb32VDAC_ctrl_clk_N 0
#define LSb16VDAC_ctrl_clk_N 0
#define bVDAC_ctrl_clk_N 3
#define MSK32VDAC_ctrl_clk_N 0x00000007
#define BA_VDAC_ctrl_clk_En 0x0008
#define B16VDAC_ctrl_clk_En 0x0008
#define LSb32VDAC_ctrl_clk_En 3
#define LSb16VDAC_ctrl_clk_En 3
#define bVDAC_ctrl_clk_En 1
#define MSK32VDAC_ctrl_clk_En 0x00000008
#define BA_VDAC_ctrl_clk_Switch 0x0008
#define B16VDAC_ctrl_clk_Switch 0x0008
#define LSb32VDAC_ctrl_clk_Switch 4
#define LSb16VDAC_ctrl_clk_Switch 4
#define bVDAC_ctrl_clk_Switch 1
#define MSK32VDAC_ctrl_clk_Switch 0x00000010
///////////////////////////////////////////////////////////
typedef struct SIE_VDAC_ctrl {
///////////////////////////////////////////////////////////
SIE_DAC_ctrl ie_a;
///////////////////////////////////////////////////////////
#define GET32VDAC_ctrl_clk_N(r32) _BFGET_(r32, 2, 0)
#define SET32VDAC_ctrl_clk_N(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16VDAC_ctrl_clk_N(r16) _BFGET_(r16, 2, 0)
#define SET16VDAC_ctrl_clk_N(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32VDAC_ctrl_clk_En(r32) _BFGET_(r32, 3, 3)
#define SET32VDAC_ctrl_clk_En(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16VDAC_ctrl_clk_En(r16) _BFGET_(r16, 3, 3)
#define SET16VDAC_ctrl_clk_En(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32VDAC_ctrl_clk_Switch(r32) _BFGET_(r32, 4, 4)
#define SET32VDAC_ctrl_clk_Switch(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16VDAC_ctrl_clk_Switch(r16) _BFGET_(r16, 4, 4)
#define SET16VDAC_ctrl_clk_Switch(r16,v) _BFSET_(r16, 4, 4,v)
#define w32VDAC_ctrl_clk {\
UNSG32 uclk_N : 3;\
UNSG32 uclk_En : 1;\
UNSG32 uclk_Switch : 1;\
UNSG32 RSVDx8_b5 : 27;\
}
union { UNSG32 u32VDAC_ctrl_clk;
struct w32VDAC_ctrl_clk;
};
///////////////////////////////////////////////////////////
} SIE_VDAC_ctrl;
typedef union T32VDAC_ctrl_clk
{ UNSG32 u32;
struct w32VDAC_ctrl_clk;
} T32VDAC_ctrl_clk;
///////////////////////////////////////////////////////////
typedef union TVDAC_ctrl_clk
{ UNSG32 u32[1];
struct {
struct w32VDAC_ctrl_clk;
};
} TVDAC_ctrl_clk;
///////////////////////////////////////////////////////////
SIGN32 VDAC_ctrl_drvrd(SIE_VDAC_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 VDAC_ctrl_drvwr(SIE_VDAC_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void VDAC_ctrl_reset(SIE_VDAC_ctrl *p);
SIGN32 VDAC_ctrl_cmp (SIE_VDAC_ctrl *p, SIE_VDAC_ctrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define VDAC_ctrl_check(p,pie,pfx,hLOG) VDAC_ctrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define VDAC_ctrl_print(p, pfx,hLOG) VDAC_ctrl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: VDAC_ctrl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE VDAC_sts biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 a
/// $DAC_sts a REG
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 8b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_VDAC_sts
#define h_VDAC_sts (){}
#define RA_VDAC_sts_a 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_VDAC_sts {
///////////////////////////////////////////////////////////
SIE_DAC_sts ie_a;
///////////////////////////////////////////////////////////
} SIE_VDAC_sts;
///////////////////////////////////////////////////////////
SIGN32 VDAC_sts_drvrd(SIE_VDAC_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 VDAC_sts_drvwr(SIE_VDAC_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void VDAC_sts_reset(SIE_VDAC_sts *p);
SIGN32 VDAC_sts_cmp (SIE_VDAC_sts *p, SIE_VDAC_sts *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define VDAC_sts_check(p,pie,pfx,hLOG) VDAC_sts_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define VDAC_sts_print(p, pfx,hLOG) VDAC_sts_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: VDAC_sts
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE HDMI_ctrl biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// %unsigned 1 PD_IREF 0x1
/// ###
/// * Power down reference current (LS;AH)
/// * 0: no power down; normal operation
/// * 1: power down.
/// * Software MUST write 0x0 to this field to enable the HDMI-PHY.
/// * Note: Software needs to follow the following sequence to power up the HDMI-PHY:
/// * set PD_IREF to 1'b0
/// * Wait for 10us
/// * Set the PD_TX to 4'h0
/// ###
/// %unsigned 1 RESET_TX 0x0
/// ###
/// * Reset TX (LS;AH)
/// * 0: no reset; normal operation
/// * 1: reset the transmitter.
/// ###
/// %unsigned 4 PD_TX 0xF
/// ###
/// * One bit per channel, bit0 is for channel0 (LS;AH)
/// * 1: power down the transmitter
/// * 0: no power-down; normal operation.
/// * Software MUST write 0x0 to this field to enable the HDMI-PHY.
/// * Note: Software needs to follow the following sequence to power up the HDMI-PHY:
/// * set PD_IREF to 1'b0
/// * Wait for 10us
/// * Set the PD_TX to 4'h0
/// ###
/// %unsigned 4 LOOPBACK 0x0
/// ###
/// * Enable Loop-back path (LS;AH)
/// * Not applicable for Berlin; always set to 0x0.
/// ###
/// %unsigned 4 POLSWAP_TX 0x0
/// ###
/// * Swap the Polarity of TXP/TXN (LS;AH)
/// * One bit per channel; bit0 is for channel0.
/// * 0: data-P is driven on TXP and data-N is driven on TXN
/// * 1: data-P is driven on TXN and data-N is driven on TXP.
/// ###
/// %unsigned 4 INV_CK20T 0x0
/// ###
/// * Invert the Polarity of 20T clock (LS;AH)
/// * One bit per channel; bit0 is for channel0.
/// * 0: don't invert
/// * 1: invert.
/// ###
/// %unsigned 1 SYNC 0x1
/// ###
/// * Synchronize four channels together (LS;AH)
/// ###
/// %unsigned 12 DAMP 0xB6D
/// ###
/// * Data Amplitude [11:9],[8:6],[5:3],[2:0] -> for channels 3->0
/// ###
/// %% 1 # Stuffing bits...
/// %unsigned 12 EAMP 0x492
/// ###
/// * Pre-Emphasis Amplitude [11:9],[8:6],[5:3],[2:0]
/// ###
/// %unsigned 16 IDRV 0xFFFF
/// ###
/// * 4-bits per channel.
/// * 1111 for highest speed
/// ###
/// %unsigned 4 TXDRVX2 0x0
/// ###
/// * Extra 50% current for VDD_DRV
/// ###
/// %unsigned 12 SVTX 0x0
/// ###
/// * SER regulated vddl control (LS;AH)
/// * [11:9],[8:6],[5:3],[2:0]
/// * 000:1.00 (16/20); 001:1.07 (15/20);
/// * 010:1.14 (14/20); 011:1.22 (13/20);
/// * 1XX: for higher voltage
/// ###
/// %unsigned 8 CP 0x0
/// %unsigned 4 AJ_D 0x0
/// ###
/// * AC JTAG Data.
/// ###
/// %unsigned 4 AJ_EN 0x0
/// ###
/// * AC JTAG Enable.
/// ###
/// %% 4 # Stuffing bits...
/// %unsigned 5 TP_EN 0x0
/// ###
/// * Test point enable; one bit per channel.
/// * 1: enables the channel for test
/// * 0: test path of the channel is disabled.
/// * At any time, one channel must be enabled.
/// ###
/// %unsigned 4 TPC 0x0
/// ###
/// * Test point select control.
/// * Selects different available test-points within one channel.
/// ###
/// %unsigned 8 AUX 0x0
/// ###
/// * AUX[0]: turns on the termination resistance.
/// * AUX[1]: if the input current is 20UA, this bit shall be set to 1.
/// * AUX[5:2]: Reserved for future use.
/// ###
/// %unsigned 1 ARC_PU 0x0
/// %unsigned 1 ARC_EN 0x0
/// %unsigned 1 ARC_CMODE 0x0
/// %unsigned 2 ARC_HYST 0x0
/// %unsigned 1 M_EN_ARC 0x0
/// %unsigned 1 P_EN_ARC 0x1
/// %unsigned 1 POLSWAP_ARC 0x1
/// %unsigned 1 TM_EN_ARC 0x1
/// %unsigned 3 IPP_CTL 0x4
/// %% 3 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 120b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_HDMI_ctrl
#define h_HDMI_ctrl (){}
#define BA_HDMI_ctrl_PD_IREF 0x0000
#define B16HDMI_ctrl_PD_IREF 0x0000
#define LSb32HDMI_ctrl_PD_IREF 0
#define LSb16HDMI_ctrl_PD_IREF 0
#define bHDMI_ctrl_PD_IREF 1
#define MSK32HDMI_ctrl_PD_IREF 0x00000001
#define BA_HDMI_ctrl_RESET_TX 0x0000
#define B16HDMI_ctrl_RESET_TX 0x0000
#define LSb32HDMI_ctrl_RESET_TX 1
#define LSb16HDMI_ctrl_RESET_TX 1
#define bHDMI_ctrl_RESET_TX 1
#define MSK32HDMI_ctrl_RESET_TX 0x00000002
#define BA_HDMI_ctrl_PD_TX 0x0000
#define B16HDMI_ctrl_PD_TX 0x0000
#define LSb32HDMI_ctrl_PD_TX 2
#define LSb16HDMI_ctrl_PD_TX 2
#define bHDMI_ctrl_PD_TX 4
#define MSK32HDMI_ctrl_PD_TX 0x0000003C
#define BA_HDMI_ctrl_LOOPBACK 0x0000
#define B16HDMI_ctrl_LOOPBACK 0x0000
#define LSb32HDMI_ctrl_LOOPBACK 6
#define LSb16HDMI_ctrl_LOOPBACK 6
#define bHDMI_ctrl_LOOPBACK 4
#define MSK32HDMI_ctrl_LOOPBACK 0x000003C0
#define BA_HDMI_ctrl_POLSWAP_TX 0x0001
#define B16HDMI_ctrl_POLSWAP_TX 0x0000
#define LSb32HDMI_ctrl_POLSWAP_TX 10
#define LSb16HDMI_ctrl_POLSWAP_TX 10
#define bHDMI_ctrl_POLSWAP_TX 4
#define MSK32HDMI_ctrl_POLSWAP_TX 0x00003C00
#define BA_HDMI_ctrl_INV_CK20T 0x0001
#define B16HDMI_ctrl_INV_CK20T 0x0000
#define LSb32HDMI_ctrl_INV_CK20T 14
#define LSb16HDMI_ctrl_INV_CK20T 14
#define bHDMI_ctrl_INV_CK20T 4
#define MSK32HDMI_ctrl_INV_CK20T 0x0003C000
#define BA_HDMI_ctrl_SYNC 0x0002
#define B16HDMI_ctrl_SYNC 0x0002
#define LSb32HDMI_ctrl_SYNC 18
#define LSb16HDMI_ctrl_SYNC 2
#define bHDMI_ctrl_SYNC 1
#define MSK32HDMI_ctrl_SYNC 0x00040000
#define BA_HDMI_ctrl_DAMP 0x0002
#define B16HDMI_ctrl_DAMP 0x0002
#define LSb32HDMI_ctrl_DAMP 19
#define LSb16HDMI_ctrl_DAMP 3
#define bHDMI_ctrl_DAMP 12
#define MSK32HDMI_ctrl_DAMP 0x7FF80000
#define BA_HDMI_ctrl_EAMP 0x0004
#define B16HDMI_ctrl_EAMP 0x0004
#define LSb32HDMI_ctrl_EAMP 0
#define LSb16HDMI_ctrl_EAMP 0
#define bHDMI_ctrl_EAMP 12
#define MSK32HDMI_ctrl_EAMP 0x00000FFF
#define BA_HDMI_ctrl_IDRV 0x0005
#define B16HDMI_ctrl_IDRV 0x0004
#define LSb32HDMI_ctrl_IDRV 12
#define LSb16HDMI_ctrl_IDRV 12
#define bHDMI_ctrl_IDRV 16
#define MSK32HDMI_ctrl_IDRV 0x0FFFF000
#define BA_HDMI_ctrl_TXDRVX2 0x0007
#define B16HDMI_ctrl_TXDRVX2 0x0006
#define LSb32HDMI_ctrl_TXDRVX2 28
#define LSb16HDMI_ctrl_TXDRVX2 12
#define bHDMI_ctrl_TXDRVX2 4
#define MSK32HDMI_ctrl_TXDRVX2 0xF0000000
#define BA_HDMI_ctrl_SVTX 0x0008
#define B16HDMI_ctrl_SVTX 0x0008
#define LSb32HDMI_ctrl_SVTX 0
#define LSb16HDMI_ctrl_SVTX 0
#define bHDMI_ctrl_SVTX 12
#define MSK32HDMI_ctrl_SVTX 0x00000FFF
#define BA_HDMI_ctrl_CP 0x0009
#define B16HDMI_ctrl_CP 0x0008
#define LSb32HDMI_ctrl_CP 12
#define LSb16HDMI_ctrl_CP 12
#define bHDMI_ctrl_CP 8
#define MSK32HDMI_ctrl_CP 0x000FF000
#define BA_HDMI_ctrl_AJ_D 0x000A
#define B16HDMI_ctrl_AJ_D 0x000A
#define LSb32HDMI_ctrl_AJ_D 20
#define LSb16HDMI_ctrl_AJ_D 4
#define bHDMI_ctrl_AJ_D 4
#define MSK32HDMI_ctrl_AJ_D 0x00F00000
#define BA_HDMI_ctrl_AJ_EN 0x000B
#define B16HDMI_ctrl_AJ_EN 0x000A
#define LSb32HDMI_ctrl_AJ_EN 24
#define LSb16HDMI_ctrl_AJ_EN 8
#define bHDMI_ctrl_AJ_EN 4
#define MSK32HDMI_ctrl_AJ_EN 0x0F000000
#define BA_HDMI_ctrl_TP_EN 0x000C
#define B16HDMI_ctrl_TP_EN 0x000C
#define LSb32HDMI_ctrl_TP_EN 0
#define LSb16HDMI_ctrl_TP_EN 0
#define bHDMI_ctrl_TP_EN 5
#define MSK32HDMI_ctrl_TP_EN 0x0000001F
#define BA_HDMI_ctrl_TPC 0x000C
#define B16HDMI_ctrl_TPC 0x000C
#define LSb32HDMI_ctrl_TPC 5
#define LSb16HDMI_ctrl_TPC 5
#define bHDMI_ctrl_TPC 4
#define MSK32HDMI_ctrl_TPC 0x000001E0
#define BA_HDMI_ctrl_AUX 0x000D
#define B16HDMI_ctrl_AUX 0x000C
#define LSb32HDMI_ctrl_AUX 9
#define LSb16HDMI_ctrl_AUX 9
#define bHDMI_ctrl_AUX 8
#define MSK32HDMI_ctrl_AUX 0x0001FE00
#define BA_HDMI_ctrl_ARC_PU 0x000E
#define B16HDMI_ctrl_ARC_PU 0x000E
#define LSb32HDMI_ctrl_ARC_PU 17
#define LSb16HDMI_ctrl_ARC_PU 1
#define bHDMI_ctrl_ARC_PU 1
#define MSK32HDMI_ctrl_ARC_PU 0x00020000
#define BA_HDMI_ctrl_ARC_EN 0x000E
#define B16HDMI_ctrl_ARC_EN 0x000E
#define LSb32HDMI_ctrl_ARC_EN 18
#define LSb16HDMI_ctrl_ARC_EN 2
#define bHDMI_ctrl_ARC_EN 1
#define MSK32HDMI_ctrl_ARC_EN 0x00040000
#define BA_HDMI_ctrl_ARC_CMODE 0x000E
#define B16HDMI_ctrl_ARC_CMODE 0x000E
#define LSb32HDMI_ctrl_ARC_CMODE 19
#define LSb16HDMI_ctrl_ARC_CMODE 3
#define bHDMI_ctrl_ARC_CMODE 1
#define MSK32HDMI_ctrl_ARC_CMODE 0x00080000
#define BA_HDMI_ctrl_ARC_HYST 0x000E
#define B16HDMI_ctrl_ARC_HYST 0x000E
#define LSb32HDMI_ctrl_ARC_HYST 20
#define LSb16HDMI_ctrl_ARC_HYST 4
#define bHDMI_ctrl_ARC_HYST 2
#define MSK32HDMI_ctrl_ARC_HYST 0x00300000
#define BA_HDMI_ctrl_M_EN_ARC 0x000E
#define B16HDMI_ctrl_M_EN_ARC 0x000E
#define LSb32HDMI_ctrl_M_EN_ARC 22
#define LSb16HDMI_ctrl_M_EN_ARC 6
#define bHDMI_ctrl_M_EN_ARC 1
#define MSK32HDMI_ctrl_M_EN_ARC 0x00400000
#define BA_HDMI_ctrl_P_EN_ARC 0x000E
#define B16HDMI_ctrl_P_EN_ARC 0x000E
#define LSb32HDMI_ctrl_P_EN_ARC 23
#define LSb16HDMI_ctrl_P_EN_ARC 7
#define bHDMI_ctrl_P_EN_ARC 1
#define MSK32HDMI_ctrl_P_EN_ARC 0x00800000
#define BA_HDMI_ctrl_POLSWAP_ARC 0x000F
#define B16HDMI_ctrl_POLSWAP_ARC 0x000E
#define LSb32HDMI_ctrl_POLSWAP_ARC 24
#define LSb16HDMI_ctrl_POLSWAP_ARC 8
#define bHDMI_ctrl_POLSWAP_ARC 1
#define MSK32HDMI_ctrl_POLSWAP_ARC 0x01000000
#define BA_HDMI_ctrl_TM_EN_ARC 0x000F
#define B16HDMI_ctrl_TM_EN_ARC 0x000E
#define LSb32HDMI_ctrl_TM_EN_ARC 25
#define LSb16HDMI_ctrl_TM_EN_ARC 9
#define bHDMI_ctrl_TM_EN_ARC 1
#define MSK32HDMI_ctrl_TM_EN_ARC 0x02000000
#define BA_HDMI_ctrl_IPP_CTL 0x000F
#define B16HDMI_ctrl_IPP_CTL 0x000E
#define LSb32HDMI_ctrl_IPP_CTL 26
#define LSb16HDMI_ctrl_IPP_CTL 10
#define bHDMI_ctrl_IPP_CTL 3
#define MSK32HDMI_ctrl_IPP_CTL 0x1C000000
///////////////////////////////////////////////////////////
typedef struct SIE_HDMI_ctrl {
///////////////////////////////////////////////////////////
#define GET32HDMI_ctrl_PD_IREF(r32) _BFGET_(r32, 0, 0)
#define SET32HDMI_ctrl_PD_IREF(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16HDMI_ctrl_PD_IREF(r16) _BFGET_(r16, 0, 0)
#define SET16HDMI_ctrl_PD_IREF(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32HDMI_ctrl_RESET_TX(r32) _BFGET_(r32, 1, 1)
#define SET32HDMI_ctrl_RESET_TX(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16HDMI_ctrl_RESET_TX(r16) _BFGET_(r16, 1, 1)
#define SET16HDMI_ctrl_RESET_TX(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32HDMI_ctrl_PD_TX(r32) _BFGET_(r32, 5, 2)
#define SET32HDMI_ctrl_PD_TX(r32,v) _BFSET_(r32, 5, 2,v)
#define GET16HDMI_ctrl_PD_TX(r16) _BFGET_(r16, 5, 2)
#define SET16HDMI_ctrl_PD_TX(r16,v) _BFSET_(r16, 5, 2,v)
#define GET32HDMI_ctrl_LOOPBACK(r32) _BFGET_(r32, 9, 6)
#define SET32HDMI_ctrl_LOOPBACK(r32,v) _BFSET_(r32, 9, 6,v)
#define GET16HDMI_ctrl_LOOPBACK(r16) _BFGET_(r16, 9, 6)
#define SET16HDMI_ctrl_LOOPBACK(r16,v) _BFSET_(r16, 9, 6,v)
#define GET32HDMI_ctrl_POLSWAP_TX(r32) _BFGET_(r32,13,10)
#define SET32HDMI_ctrl_POLSWAP_TX(r32,v) _BFSET_(r32,13,10,v)
#define GET16HDMI_ctrl_POLSWAP_TX(r16) _BFGET_(r16,13,10)
#define SET16HDMI_ctrl_POLSWAP_TX(r16,v) _BFSET_(r16,13,10,v)
#define GET32HDMI_ctrl_INV_CK20T(r32) _BFGET_(r32,17,14)
#define SET32HDMI_ctrl_INV_CK20T(r32,v) _BFSET_(r32,17,14,v)
#define GET32HDMI_ctrl_SYNC(r32) _BFGET_(r32,18,18)
#define SET32HDMI_ctrl_SYNC(r32,v) _BFSET_(r32,18,18,v)
#define GET16HDMI_ctrl_SYNC(r16) _BFGET_(r16, 2, 2)
#define SET16HDMI_ctrl_SYNC(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32HDMI_ctrl_DAMP(r32) _BFGET_(r32,30,19)
#define SET32HDMI_ctrl_DAMP(r32,v) _BFSET_(r32,30,19,v)
#define GET16HDMI_ctrl_DAMP(r16) _BFGET_(r16,14, 3)
#define SET16HDMI_ctrl_DAMP(r16,v) _BFSET_(r16,14, 3,v)
UNSG32 u_PD_IREF : 1;
UNSG32 u_RESET_TX : 1;
UNSG32 u_PD_TX : 4;
UNSG32 u_LOOPBACK : 4;
UNSG32 u_POLSWAP_TX : 4;
UNSG32 u_INV_CK20T : 4;
UNSG32 u_SYNC : 1;
UNSG32 u_DAMP : 12;
UNSG32 RSVDx0_b31 : 1;
///////////////////////////////////////////////////////////
#define GET32HDMI_ctrl_EAMP(r32) _BFGET_(r32,11, 0)
#define SET32HDMI_ctrl_EAMP(r32,v) _BFSET_(r32,11, 0,v)
#define GET16HDMI_ctrl_EAMP(r16) _BFGET_(r16,11, 0)
#define SET16HDMI_ctrl_EAMP(r16,v) _BFSET_(r16,11, 0,v)
#define GET32HDMI_ctrl_IDRV(r32) _BFGET_(r32,27,12)
#define SET32HDMI_ctrl_IDRV(r32,v) _BFSET_(r32,27,12,v)
#define GET32HDMI_ctrl_TXDRVX2(r32) _BFGET_(r32,31,28)
#define SET32HDMI_ctrl_TXDRVX2(r32,v) _BFSET_(r32,31,28,v)
#define GET16HDMI_ctrl_TXDRVX2(r16) _BFGET_(r16,15,12)
#define SET16HDMI_ctrl_TXDRVX2(r16,v) _BFSET_(r16,15,12,v)
UNSG32 u_EAMP : 12;
UNSG32 u_IDRV : 16;
UNSG32 u_TXDRVX2 : 4;
///////////////////////////////////////////////////////////
#define GET32HDMI_ctrl_SVTX(r32) _BFGET_(r32,11, 0)
#define SET32HDMI_ctrl_SVTX(r32,v) _BFSET_(r32,11, 0,v)
#define GET16HDMI_ctrl_SVTX(r16) _BFGET_(r16,11, 0)
#define SET16HDMI_ctrl_SVTX(r16,v) _BFSET_(r16,11, 0,v)
#define GET32HDMI_ctrl_CP(r32) _BFGET_(r32,19,12)
#define SET32HDMI_ctrl_CP(r32,v) _BFSET_(r32,19,12,v)
#define GET32HDMI_ctrl_AJ_D(r32) _BFGET_(r32,23,20)
#define SET32HDMI_ctrl_AJ_D(r32,v) _BFSET_(r32,23,20,v)
#define GET16HDMI_ctrl_AJ_D(r16) _BFGET_(r16, 7, 4)
#define SET16HDMI_ctrl_AJ_D(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32HDMI_ctrl_AJ_EN(r32) _BFGET_(r32,27,24)
#define SET32HDMI_ctrl_AJ_EN(r32,v) _BFSET_(r32,27,24,v)
#define GET16HDMI_ctrl_AJ_EN(r16) _BFGET_(r16,11, 8)
#define SET16HDMI_ctrl_AJ_EN(r16,v) _BFSET_(r16,11, 8,v)
UNSG32 u_SVTX : 12;
UNSG32 u_CP : 8;
UNSG32 u_AJ_D : 4;
UNSG32 u_AJ_EN : 4;
UNSG32 RSVDx8_b28 : 4;
///////////////////////////////////////////////////////////
#define GET32HDMI_ctrl_TP_EN(r32) _BFGET_(r32, 4, 0)
#define SET32HDMI_ctrl_TP_EN(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16HDMI_ctrl_TP_EN(r16) _BFGET_(r16, 4, 0)
#define SET16HDMI_ctrl_TP_EN(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32HDMI_ctrl_TPC(r32) _BFGET_(r32, 8, 5)
#define SET32HDMI_ctrl_TPC(r32,v) _BFSET_(r32, 8, 5,v)
#define GET16HDMI_ctrl_TPC(r16) _BFGET_(r16, 8, 5)
#define SET16HDMI_ctrl_TPC(r16,v) _BFSET_(r16, 8, 5,v)
#define GET32HDMI_ctrl_AUX(r32) _BFGET_(r32,16, 9)
#define SET32HDMI_ctrl_AUX(r32,v) _BFSET_(r32,16, 9,v)
#define GET32HDMI_ctrl_ARC_PU(r32) _BFGET_(r32,17,17)
#define SET32HDMI_ctrl_ARC_PU(r32,v) _BFSET_(r32,17,17,v)
#define GET16HDMI_ctrl_ARC_PU(r16) _BFGET_(r16, 1, 1)
#define SET16HDMI_ctrl_ARC_PU(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32HDMI_ctrl_ARC_EN(r32) _BFGET_(r32,18,18)
#define SET32HDMI_ctrl_ARC_EN(r32,v) _BFSET_(r32,18,18,v)
#define GET16HDMI_ctrl_ARC_EN(r16) _BFGET_(r16, 2, 2)
#define SET16HDMI_ctrl_ARC_EN(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32HDMI_ctrl_ARC_CMODE(r32) _BFGET_(r32,19,19)
#define SET32HDMI_ctrl_ARC_CMODE(r32,v) _BFSET_(r32,19,19,v)
#define GET16HDMI_ctrl_ARC_CMODE(r16) _BFGET_(r16, 3, 3)
#define SET16HDMI_ctrl_ARC_CMODE(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32HDMI_ctrl_ARC_HYST(r32) _BFGET_(r32,21,20)
#define SET32HDMI_ctrl_ARC_HYST(r32,v) _BFSET_(r32,21,20,v)
#define GET16HDMI_ctrl_ARC_HYST(r16) _BFGET_(r16, 5, 4)
#define SET16HDMI_ctrl_ARC_HYST(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32HDMI_ctrl_M_EN_ARC(r32) _BFGET_(r32,22,22)
#define SET32HDMI_ctrl_M_EN_ARC(r32,v) _BFSET_(r32,22,22,v)
#define GET16HDMI_ctrl_M_EN_ARC(r16) _BFGET_(r16, 6, 6)
#define SET16HDMI_ctrl_M_EN_ARC(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32HDMI_ctrl_P_EN_ARC(r32) _BFGET_(r32,23,23)
#define SET32HDMI_ctrl_P_EN_ARC(r32,v) _BFSET_(r32,23,23,v)
#define GET16HDMI_ctrl_P_EN_ARC(r16) _BFGET_(r16, 7, 7)
#define SET16HDMI_ctrl_P_EN_ARC(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32HDMI_ctrl_POLSWAP_ARC(r32) _BFGET_(r32,24,24)
#define SET32HDMI_ctrl_POLSWAP_ARC(r32,v) _BFSET_(r32,24,24,v)
#define GET16HDMI_ctrl_POLSWAP_ARC(r16) _BFGET_(r16, 8, 8)
#define SET16HDMI_ctrl_POLSWAP_ARC(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32HDMI_ctrl_TM_EN_ARC(r32) _BFGET_(r32,25,25)
#define SET32HDMI_ctrl_TM_EN_ARC(r32,v) _BFSET_(r32,25,25,v)
#define GET16HDMI_ctrl_TM_EN_ARC(r16) _BFGET_(r16, 9, 9)
#define SET16HDMI_ctrl_TM_EN_ARC(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32HDMI_ctrl_IPP_CTL(r32) _BFGET_(r32,28,26)
#define SET32HDMI_ctrl_IPP_CTL(r32,v) _BFSET_(r32,28,26,v)
#define GET16HDMI_ctrl_IPP_CTL(r16) _BFGET_(r16,12,10)
#define SET16HDMI_ctrl_IPP_CTL(r16,v) _BFSET_(r16,12,10,v)
UNSG32 u_TP_EN : 5;
UNSG32 u_TPC : 4;
UNSG32 u_AUX : 8;
UNSG32 u_ARC_PU : 1;
UNSG32 u_ARC_EN : 1;
UNSG32 u_ARC_CMODE : 1;
UNSG32 u_ARC_HYST : 2;
UNSG32 u_M_EN_ARC : 1;
UNSG32 u_P_EN_ARC : 1;
UNSG32 u_POLSWAP_ARC : 1;
UNSG32 u_TM_EN_ARC : 1;
UNSG32 u_IPP_CTL : 3;
UNSG32 RSVDxC_b29 : 3;
///////////////////////////////////////////////////////////
} SIE_HDMI_ctrl;
///////////////////////////////////////////////////////////
SIGN32 HDMI_ctrl_drvrd(SIE_HDMI_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 HDMI_ctrl_drvwr(SIE_HDMI_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void HDMI_ctrl_reset(SIE_HDMI_ctrl *p);
SIGN32 HDMI_ctrl_cmp (SIE_HDMI_ctrl *p, SIE_HDMI_ctrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define HDMI_ctrl_check(p,pie,pfx,hLOG) HDMI_ctrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define HDMI_ctrl_print(p, pfx,hLOG) HDMI_ctrl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: HDMI_ctrl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE HDMI_sts biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (R-)
/// %unsigned 4 AUXO 0x0
/// %% 28 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 4b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_HDMI_sts
#define h_HDMI_sts (){}
#define BA_HDMI_sts_AUXO 0x0000
#define B16HDMI_sts_AUXO 0x0000
#define LSb32HDMI_sts_AUXO 0
#define LSb16HDMI_sts_AUXO 0
#define bHDMI_sts_AUXO 4
#define MSK32HDMI_sts_AUXO 0x0000000F
///////////////////////////////////////////////////////////
typedef struct SIE_HDMI_sts {
///////////////////////////////////////////////////////////
#define GET32HDMI_sts_AUXO(r32) _BFGET_(r32, 3, 0)
#define SET32HDMI_sts_AUXO(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16HDMI_sts_AUXO(r16) _BFGET_(r16, 3, 0)
#define SET16HDMI_sts_AUXO(r16,v) _BFSET_(r16, 3, 0,v)
UNSG32 u_AUXO : 4;
UNSG32 RSVDx0_b4 : 28;
///////////////////////////////////////////////////////////
} SIE_HDMI_sts;
///////////////////////////////////////////////////////////
SIGN32 HDMI_sts_drvrd(SIE_HDMI_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 HDMI_sts_drvwr(SIE_HDMI_sts *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void HDMI_sts_reset(SIE_HDMI_sts *p);
SIGN32 HDMI_sts_cmp (SIE_HDMI_sts *p, SIE_HDMI_sts *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define HDMI_sts_check(p,pie,pfx,hLOG) HDMI_sts_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define HDMI_sts_print(p, pfx,hLOG) HDMI_sts_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: HDMI_sts
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE PLANE biu (4,4)
/// ###
/// * Register specification of interface PLANE
/// * Defines the size of the plane.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 SIZE (P)
/// %unsigned 16 Y 0x438
/// %unsigned 16 X 0x780
/// ###
/// * Size of the plane.
/// * Defines the left crop of the plane in unit of pixel.
/// ###
/// @ 0x00004 CROP (P)
/// %unsigned 16 LEFT 0x0
/// ###
/// * Left crop counter in unit of pixel. Since video data (BG/Main/PIP planes) is in UYVY pixel pair format, the crop count should be a even number to make sure the correct order.
/// * For all other planes (PG, IG, Cursor or MOSD), crop can be any number.
/// ###
/// %unsigned 16 WPL 0x20
/// ###
/// * WPL defines how many beats (one beat is 64-bit word) read from DMA per line.
/// * (CROP_LEFT+SIZEX)/ppw(pixels per word)=WPL.
/// * FORMAT defines the input format and order
/// ###
/// @ 0x00008 FORMAT (P)
/// %unsigned 3 SRCFMT 0x0
/// : YUV422 0x0
/// : ARGB32 0x0
/// : ARGB24 0x1
/// : ARGB4444 0x2
/// : RGB565 0x3
/// : ARGB1555 0x4
/// : LUT8 0x5
/// ###
/// * YUV422 shall be used for video planes (Main, PIP and BG)
/// * LUT8 or ARGB32 shall be used for graphic planes (IG, PG, Cursor and MOSD)
/// ###
/// %unsigned 2 FMTORDER 0x0
/// : ARGB 0x0
/// : ABGR 0x1
/// : RGBA 0x2
/// : BGRA 0x3
/// : AVYU 0x0
/// : AUYV 0x1
/// : VYUA 0x2
/// : UYVA 0x3
/// ###
/// * This configuration is for graphic plane
/// * Eg: for ARGB, A is stored at low address, and B is stored at high address in DRAM.
/// ###
/// : UYVY 0x0
/// : VYUY 0x1
/// : YUYV 0x2
/// : YVYU 0x3
/// ###
/// * This configuration is for video plane
/// * Eg: for UYVY (read it as U0Y0V0Y1), U0 is stored at low address and Y1 is stored at high address.
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x0000C START (P-)
/// %unsigned 1 EN 0x0
/// ###
/// * kickoff bit.
/// * write '1' to this register will enable the channel.
/// * write '0' to this register has no effect.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00010 CLEAR (P-)
/// %unsigned 1 EN 0x0
/// ###
/// * channel clear bit.
/// * write '1' to this register will clear all the FIFOs and pipeline data inside the channel.
/// * End of plane register group
/// ###
/// %% 31 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 20B, bits: 71b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_PLANE
#define h_PLANE (){}
#define RA_PLANE_SIZE 0x0000
#define BA_PLANE_SIZE_Y 0x0000
#define B16PLANE_SIZE_Y 0x0000
#define LSb32PLANE_SIZE_Y 0
#define LSb16PLANE_SIZE_Y 0
#define bPLANE_SIZE_Y 16
#define MSK32PLANE_SIZE_Y 0x0000FFFF
#define BA_PLANE_SIZE_X 0x0002
#define B16PLANE_SIZE_X 0x0002
#define LSb32PLANE_SIZE_X 16
#define LSb16PLANE_SIZE_X 0
#define bPLANE_SIZE_X 16
#define MSK32PLANE_SIZE_X 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_PLANE_CROP 0x0004
#define BA_PLANE_CROP_LEFT 0x0004
#define B16PLANE_CROP_LEFT 0x0004
#define LSb32PLANE_CROP_LEFT 0
#define LSb16PLANE_CROP_LEFT 0
#define bPLANE_CROP_LEFT 16
#define MSK32PLANE_CROP_LEFT 0x0000FFFF
#define BA_PLANE_CROP_WPL 0x0006
#define B16PLANE_CROP_WPL 0x0006
#define LSb32PLANE_CROP_WPL 16
#define LSb16PLANE_CROP_WPL 0
#define bPLANE_CROP_WPL 16
#define MSK32PLANE_CROP_WPL 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_PLANE_FORMAT 0x0008
#define BA_PLANE_FORMAT_SRCFMT 0x0008
#define B16PLANE_FORMAT_SRCFMT 0x0008
#define LSb32PLANE_FORMAT_SRCFMT 0
#define LSb16PLANE_FORMAT_SRCFMT 0
#define bPLANE_FORMAT_SRCFMT 3
#define MSK32PLANE_FORMAT_SRCFMT 0x00000007
#define PLANE_FORMAT_SRCFMT_YUV422 0x0
#define PLANE_FORMAT_SRCFMT_ARGB32 0x0
#define PLANE_FORMAT_SRCFMT_ARGB24 0x1
#define PLANE_FORMAT_SRCFMT_ARGB4444 0x2
#define PLANE_FORMAT_SRCFMT_RGB565 0x3
#define PLANE_FORMAT_SRCFMT_ARGB1555 0x4
#define PLANE_FORMAT_SRCFMT_LUT8 0x5
#define BA_PLANE_FORMAT_FMTORDER 0x0008
#define B16PLANE_FORMAT_FMTORDER 0x0008
#define LSb32PLANE_FORMAT_FMTORDER 3
#define LSb16PLANE_FORMAT_FMTORDER 3
#define bPLANE_FORMAT_FMTORDER 2
#define MSK32PLANE_FORMAT_FMTORDER 0x00000018
#define PLANE_FORMAT_FMTORDER_ARGB 0x0
#define PLANE_FORMAT_FMTORDER_ABGR 0x1
#define PLANE_FORMAT_FMTORDER_RGBA 0x2
#define PLANE_FORMAT_FMTORDER_BGRA 0x3
#define PLANE_FORMAT_FMTORDER_AVYU 0x0
#define PLANE_FORMAT_FMTORDER_AUYV 0x1
#define PLANE_FORMAT_FMTORDER_VYUA 0x2
#define PLANE_FORMAT_FMTORDER_UYVA 0x3
#define PLANE_FORMAT_FMTORDER_UYVY 0x0
#define PLANE_FORMAT_FMTORDER_VYUY 0x1
#define PLANE_FORMAT_FMTORDER_YUYV 0x2
#define PLANE_FORMAT_FMTORDER_YVYU 0x3
///////////////////////////////////////////////////////////
#define RA_PLANE_START 0x000C
#define BA_PLANE_START_EN 0x000C
#define B16PLANE_START_EN 0x000C
#define LSb32PLANE_START_EN 0
#define LSb16PLANE_START_EN 0
#define bPLANE_START_EN 1
#define MSK32PLANE_START_EN 0x00000001
///////////////////////////////////////////////////////////
#define RA_PLANE_CLEAR 0x0010
#define BA_PLANE_CLEAR_EN 0x0010
#define B16PLANE_CLEAR_EN 0x0010
#define LSb32PLANE_CLEAR_EN 0
#define LSb16PLANE_CLEAR_EN 0
#define bPLANE_CLEAR_EN 1
#define MSK32PLANE_CLEAR_EN 0x00000001
///////////////////////////////////////////////////////////
typedef struct SIE_PLANE {
///////////////////////////////////////////////////////////
#define GET32PLANE_SIZE_Y(r32) _BFGET_(r32,15, 0)
#define SET32PLANE_SIZE_Y(r32,v) _BFSET_(r32,15, 0,v)
#define GET16PLANE_SIZE_Y(r16) _BFGET_(r16,15, 0)
#define SET16PLANE_SIZE_Y(r16,v) _BFSET_(r16,15, 0,v)
#define GET32PLANE_SIZE_X(r32) _BFGET_(r32,31,16)
#define SET32PLANE_SIZE_X(r32,v) _BFSET_(r32,31,16,v)
#define GET16PLANE_SIZE_X(r16) _BFGET_(r16,15, 0)
#define SET16PLANE_SIZE_X(r16,v) _BFSET_(r16,15, 0,v)
#define w32PLANE_SIZE {\
UNSG32 uSIZE_Y : 16;\
UNSG32 uSIZE_X : 16;\
}
union { UNSG32 u32PLANE_SIZE;
struct w32PLANE_SIZE;
};
///////////////////////////////////////////////////////////
#define GET32PLANE_CROP_LEFT(r32) _BFGET_(r32,15, 0)
#define SET32PLANE_CROP_LEFT(r32,v) _BFSET_(r32,15, 0,v)
#define GET16PLANE_CROP_LEFT(r16) _BFGET_(r16,15, 0)
#define SET16PLANE_CROP_LEFT(r16,v) _BFSET_(r16,15, 0,v)
#define GET32PLANE_CROP_WPL(r32) _BFGET_(r32,31,16)
#define SET32PLANE_CROP_WPL(r32,v) _BFSET_(r32,31,16,v)
#define GET16PLANE_CROP_WPL(r16) _BFGET_(r16,15, 0)
#define SET16PLANE_CROP_WPL(r16,v) _BFSET_(r16,15, 0,v)
#define w32PLANE_CROP {\
UNSG32 uCROP_LEFT : 16;\
UNSG32 uCROP_WPL : 16;\
}
union { UNSG32 u32PLANE_CROP;
struct w32PLANE_CROP;
};
///////////////////////////////////////////////////////////
#define GET32PLANE_FORMAT_SRCFMT(r32) _BFGET_(r32, 2, 0)
#define SET32PLANE_FORMAT_SRCFMT(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16PLANE_FORMAT_SRCFMT(r16) _BFGET_(r16, 2, 0)
#define SET16PLANE_FORMAT_SRCFMT(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32PLANE_FORMAT_FMTORDER(r32) _BFGET_(r32, 4, 3)
#define SET32PLANE_FORMAT_FMTORDER(r32,v) _BFSET_(r32, 4, 3,v)
#define GET16PLANE_FORMAT_FMTORDER(r16) _BFGET_(r16, 4, 3)
#define SET16PLANE_FORMAT_FMTORDER(r16,v) _BFSET_(r16, 4, 3,v)
#define w32PLANE_FORMAT {\
UNSG32 uFORMAT_SRCFMT : 3;\
UNSG32 uFORMAT_FMTORDER : 2;\
UNSG32 RSVDx8_b5 : 27;\
}
union { UNSG32 u32PLANE_FORMAT;
struct w32PLANE_FORMAT;
};
///////////////////////////////////////////////////////////
#define GET32PLANE_START_EN(r32) _BFGET_(r32, 0, 0)
#define SET32PLANE_START_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16PLANE_START_EN(r16) _BFGET_(r16, 0, 0)
#define SET16PLANE_START_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define w32PLANE_START {\
UNSG32 uSTART_EN : 1;\
UNSG32 RSVDxC_b1 : 31;\
}
union { UNSG32 u32PLANE_START;
struct w32PLANE_START;
};
///////////////////////////////////////////////////////////
#define GET32PLANE_CLEAR_EN(r32) _BFGET_(r32, 0, 0)
#define SET32PLANE_CLEAR_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16PLANE_CLEAR_EN(r16) _BFGET_(r16, 0, 0)
#define SET16PLANE_CLEAR_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define w32PLANE_CLEAR {\
UNSG32 uCLEAR_EN : 1;\
UNSG32 RSVDx10_b1 : 31;\
}
union { UNSG32 u32PLANE_CLEAR;
struct w32PLANE_CLEAR;
};
///////////////////////////////////////////////////////////
} SIE_PLANE;
typedef union T32PLANE_SIZE
{ UNSG32 u32;
struct w32PLANE_SIZE;
} T32PLANE_SIZE;
typedef union T32PLANE_CROP
{ UNSG32 u32;
struct w32PLANE_CROP;
} T32PLANE_CROP;
typedef union T32PLANE_FORMAT
{ UNSG32 u32;
struct w32PLANE_FORMAT;
} T32PLANE_FORMAT;
typedef union T32PLANE_START
{ UNSG32 u32;
struct w32PLANE_START;
} T32PLANE_START;
typedef union T32PLANE_CLEAR
{ UNSG32 u32;
struct w32PLANE_CLEAR;
} T32PLANE_CLEAR;
///////////////////////////////////////////////////////////
typedef union TPLANE_SIZE
{ UNSG32 u32[1];
struct {
struct w32PLANE_SIZE;
};
} TPLANE_SIZE;
typedef union TPLANE_CROP
{ UNSG32 u32[1];
struct {
struct w32PLANE_CROP;
};
} TPLANE_CROP;
typedef union TPLANE_FORMAT
{ UNSG32 u32[1];
struct {
struct w32PLANE_FORMAT;
};
} TPLANE_FORMAT;
typedef union TPLANE_START
{ UNSG32 u32[1];
struct {
struct w32PLANE_START;
};
} TPLANE_START;
typedef union TPLANE_CLEAR
{ UNSG32 u32[1];
struct {
struct w32PLANE_CLEAR;
};
} TPLANE_CLEAR;
///////////////////////////////////////////////////////////
SIGN32 PLANE_drvrd(SIE_PLANE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 PLANE_drvwr(SIE_PLANE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void PLANE_reset(SIE_PLANE *p);
SIGN32 PLANE_cmp (SIE_PLANE *p, SIE_PLANE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define PLANE_check(p,pie,pfx,hLOG) PLANE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define PLANE_print(p, pfx,hLOG) PLANE_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: PLANE
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CQUAD (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ARGB (P)
/// %unsigned 8 A
/// %unsigned 8 R_V
/// %unsigned 8 G_Y
/// %unsigned 8 B_U
/// ###
/// * 8-bit index to 32-bit ARGB/AYUV table lookup
/// * A is stored at [7:0], R/V is stored at [15:8], G/Y is stored at [23:16] and B/U is stored at [31:24].
/// * End of Color QUAD LUT definition.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CQUAD
#define h_CQUAD (){}
#define RA_CQUAD_ARGB 0x0000
#define BA_CQUAD_ARGB_A 0x0000
#define B16CQUAD_ARGB_A 0x0000
#define LSb32CQUAD_ARGB_A 0
#define LSb16CQUAD_ARGB_A 0
#define bCQUAD_ARGB_A 8
#define MSK32CQUAD_ARGB_A 0x000000FF
#define BA_CQUAD_ARGB_R_V 0x0001
#define B16CQUAD_ARGB_R_V 0x0000
#define LSb32CQUAD_ARGB_R_V 8
#define LSb16CQUAD_ARGB_R_V 8
#define bCQUAD_ARGB_R_V 8
#define MSK32CQUAD_ARGB_R_V 0x0000FF00
#define BA_CQUAD_ARGB_G_Y 0x0002
#define B16CQUAD_ARGB_G_Y 0x0002
#define LSb32CQUAD_ARGB_G_Y 16
#define LSb16CQUAD_ARGB_G_Y 0
#define bCQUAD_ARGB_G_Y 8
#define MSK32CQUAD_ARGB_G_Y 0x00FF0000
#define BA_CQUAD_ARGB_B_U 0x0003
#define B16CQUAD_ARGB_B_U 0x0002
#define LSb32CQUAD_ARGB_B_U 24
#define LSb16CQUAD_ARGB_B_U 8
#define bCQUAD_ARGB_B_U 8
#define MSK32CQUAD_ARGB_B_U 0xFF000000
///////////////////////////////////////////////////////////
typedef struct SIE_CQUAD {
///////////////////////////////////////////////////////////
#define GET32CQUAD_ARGB_A(r32) _BFGET_(r32, 7, 0)
#define SET32CQUAD_ARGB_A(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16CQUAD_ARGB_A(r16) _BFGET_(r16, 7, 0)
#define SET16CQUAD_ARGB_A(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32CQUAD_ARGB_R_V(r32) _BFGET_(r32,15, 8)
#define SET32CQUAD_ARGB_R_V(r32,v) _BFSET_(r32,15, 8,v)
#define GET16CQUAD_ARGB_R_V(r16) _BFGET_(r16,15, 8)
#define SET16CQUAD_ARGB_R_V(r16,v) _BFSET_(r16,15, 8,v)
#define GET32CQUAD_ARGB_G_Y(r32) _BFGET_(r32,23,16)
#define SET32CQUAD_ARGB_G_Y(r32,v) _BFSET_(r32,23,16,v)
#define GET16CQUAD_ARGB_G_Y(r16) _BFGET_(r16, 7, 0)
#define SET16CQUAD_ARGB_G_Y(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32CQUAD_ARGB_B_U(r32) _BFGET_(r32,31,24)
#define SET32CQUAD_ARGB_B_U(r32,v) _BFSET_(r32,31,24,v)
#define GET16CQUAD_ARGB_B_U(r16) _BFGET_(r16,15, 8)
#define SET16CQUAD_ARGB_B_U(r16,v) _BFSET_(r16,15, 8,v)
#define w32CQUAD_ARGB {\
UNSG32 uARGB_A : 8;\
UNSG32 uARGB_R_V : 8;\
UNSG32 uARGB_G_Y : 8;\
UNSG32 uARGB_B_U : 8;\
}
union { UNSG32 u32CQUAD_ARGB;
struct w32CQUAD_ARGB;
};
///////////////////////////////////////////////////////////
} SIE_CQUAD;
typedef union T32CQUAD_ARGB
{ UNSG32 u32;
struct w32CQUAD_ARGB;
} T32CQUAD_ARGB;
///////////////////////////////////////////////////////////
typedef union TCQUAD_ARGB
{ UNSG32 u32[1];
struct {
struct w32CQUAD_ARGB;
};
} TCQUAD_ARGB;
///////////////////////////////////////////////////////////
SIGN32 CQUAD_drvrd(SIE_CQUAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CQUAD_drvwr(SIE_CQUAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CQUAD_reset(SIE_CQUAD *p);
SIGN32 CQUAD_cmp (SIE_CQUAD *p, SIE_CQUAD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CQUAD_check(p,pie,pfx,hLOG) CQUAD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CQUAD_print(p, pfx,hLOG) CQUAD_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CQUAD
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CLUT (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 CLUT
/// $CQUAD CLUT REG [256]
/// ###
/// * 8-bit index to 32-bit ARGB/AYUV table lookup
/// * End of Color CLUT definition.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 1024B, bits: 8192b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CLUT
#define h_CLUT (){}
#define RA_CLUT_CLUT 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_CLUT {
///////////////////////////////////////////////////////////
SIE_CQUAD ie_CLUT[256];
///////////////////////////////////////////////////////////
} SIE_CLUT;
///////////////////////////////////////////////////////////
SIGN32 CLUT_drvrd(SIE_CLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CLUT_drvwr(SIE_CLUT *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CLUT_reset(SIE_CLUT *p);
SIGN32 CLUT_cmp (SIE_CLUT *p, SIE_CLUT *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CLUT_check(p,pie,pfx,hLOG) CLUT_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CLUT_print(p, pfx,hLOG) CLUT_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CLUT
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CSC (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 const_C0 (P)
/// %unsigned 14 C0 0x200
/// %% 18 # Stuffing bits...
/// @ 0x00004 const_C1 (P)
/// %unsigned 14 C1 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00008 const_C2 (P)
/// %unsigned 14 C2 0x0
/// %% 18 # Stuffing bits...
/// @ 0x0000C const_C3 (P)
/// %unsigned 14 C3 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00010 const_C4 (P)
/// %unsigned 14 C4 0x200
/// %% 18 # Stuffing bits...
/// @ 0x00014 const_C5 (P)
/// %unsigned 14 C5 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00018 const_C6 (P)
/// %unsigned 14 C6 0x0
/// %% 18 # Stuffing bits...
/// @ 0x0001C const_C7 (P)
/// %unsigned 14 C7 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00020 const_C8 (P)
/// %unsigned 14 C8 0x200
/// ###
/// * Coefficients used by CSC.
/// ###
/// %% 18 # Stuffing bits...
/// @ 0x00024 off_A0 (P)
/// %unsigned 16 A0 0x0
/// %% 16 # Stuffing bits...
/// @ 0x00028 off_A1 (P)
/// %unsigned 16 A1 0x0
/// %% 16 # Stuffing bits...
/// @ 0x0002C off_A2 (P)
/// %unsigned 16 A2 0x0
/// ###
/// * Offsets used by CSC.
/// ###
/// %% 16 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 48B, bits: 174b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CSC
#define h_CSC (){}
#define RA_CSC_const_C0 0x0000
#define BA_CSC_const_C0_C0 0x0000
#define B16CSC_const_C0_C0 0x0000
#define LSb32CSC_const_C0_C0 0
#define LSb16CSC_const_C0_C0 0
#define bCSC_const_C0_C0 14
#define MSK32CSC_const_C0_C0 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C1 0x0004
#define BA_CSC_const_C1_C1 0x0004
#define B16CSC_const_C1_C1 0x0004
#define LSb32CSC_const_C1_C1 0
#define LSb16CSC_const_C1_C1 0
#define bCSC_const_C1_C1 14
#define MSK32CSC_const_C1_C1 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C2 0x0008
#define BA_CSC_const_C2_C2 0x0008
#define B16CSC_const_C2_C2 0x0008
#define LSb32CSC_const_C2_C2 0
#define LSb16CSC_const_C2_C2 0
#define bCSC_const_C2_C2 14
#define MSK32CSC_const_C2_C2 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C3 0x000C
#define BA_CSC_const_C3_C3 0x000C
#define B16CSC_const_C3_C3 0x000C
#define LSb32CSC_const_C3_C3 0
#define LSb16CSC_const_C3_C3 0
#define bCSC_const_C3_C3 14
#define MSK32CSC_const_C3_C3 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C4 0x0010
#define BA_CSC_const_C4_C4 0x0010
#define B16CSC_const_C4_C4 0x0010
#define LSb32CSC_const_C4_C4 0
#define LSb16CSC_const_C4_C4 0
#define bCSC_const_C4_C4 14
#define MSK32CSC_const_C4_C4 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C5 0x0014
#define BA_CSC_const_C5_C5 0x0014
#define B16CSC_const_C5_C5 0x0014
#define LSb32CSC_const_C5_C5 0
#define LSb16CSC_const_C5_C5 0
#define bCSC_const_C5_C5 14
#define MSK32CSC_const_C5_C5 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C6 0x0018
#define BA_CSC_const_C6_C6 0x0018
#define B16CSC_const_C6_C6 0x0018
#define LSb32CSC_const_C6_C6 0
#define LSb16CSC_const_C6_C6 0
#define bCSC_const_C6_C6 14
#define MSK32CSC_const_C6_C6 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C7 0x001C
#define BA_CSC_const_C7_C7 0x001C
#define B16CSC_const_C7_C7 0x001C
#define LSb32CSC_const_C7_C7 0
#define LSb16CSC_const_C7_C7 0
#define bCSC_const_C7_C7 14
#define MSK32CSC_const_C7_C7 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_const_C8 0x0020
#define BA_CSC_const_C8_C8 0x0020
#define B16CSC_const_C8_C8 0x0020
#define LSb32CSC_const_C8_C8 0
#define LSb16CSC_const_C8_C8 0
#define bCSC_const_C8_C8 14
#define MSK32CSC_const_C8_C8 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_CSC_off_A0 0x0024
#define BA_CSC_off_A0_A0 0x0024
#define B16CSC_off_A0_A0 0x0024
#define LSb32CSC_off_A0_A0 0
#define LSb16CSC_off_A0_A0 0
#define bCSC_off_A0_A0 16
#define MSK32CSC_off_A0_A0 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_CSC_off_A1 0x0028
#define BA_CSC_off_A1_A1 0x0028
#define B16CSC_off_A1_A1 0x0028
#define LSb32CSC_off_A1_A1 0
#define LSb16CSC_off_A1_A1 0
#define bCSC_off_A1_A1 16
#define MSK32CSC_off_A1_A1 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_CSC_off_A2 0x002C
#define BA_CSC_off_A2_A2 0x002C
#define B16CSC_off_A2_A2 0x002C
#define LSb32CSC_off_A2_A2 0
#define LSb16CSC_off_A2_A2 0
#define bCSC_off_A2_A2 16
#define MSK32CSC_off_A2_A2 0x0000FFFF
///////////////////////////////////////////////////////////
typedef struct SIE_CSC {
///////////////////////////////////////////////////////////
#define GET32CSC_const_C0_C0(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C0_C0(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C0_C0(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C0_C0(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C0 {\
UNSG32 uconst_C0_C0 : 14;\
UNSG32 RSVDx0_b14 : 18;\
}
union { UNSG32 u32CSC_const_C0;
struct w32CSC_const_C0;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C1_C1(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C1_C1(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C1_C1(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C1_C1(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C1 {\
UNSG32 uconst_C1_C1 : 14;\
UNSG32 RSVDx4_b14 : 18;\
}
union { UNSG32 u32CSC_const_C1;
struct w32CSC_const_C1;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C2_C2(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C2_C2(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C2_C2(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C2_C2(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C2 {\
UNSG32 uconst_C2_C2 : 14;\
UNSG32 RSVDx8_b14 : 18;\
}
union { UNSG32 u32CSC_const_C2;
struct w32CSC_const_C2;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C3_C3(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C3_C3(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C3_C3(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C3_C3(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C3 {\
UNSG32 uconst_C3_C3 : 14;\
UNSG32 RSVDxC_b14 : 18;\
}
union { UNSG32 u32CSC_const_C3;
struct w32CSC_const_C3;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C4_C4(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C4_C4(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C4_C4(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C4_C4(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C4 {\
UNSG32 uconst_C4_C4 : 14;\
UNSG32 RSVDx10_b14 : 18;\
}
union { UNSG32 u32CSC_const_C4;
struct w32CSC_const_C4;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C5_C5(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C5_C5(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C5_C5(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C5_C5(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C5 {\
UNSG32 uconst_C5_C5 : 14;\
UNSG32 RSVDx14_b14 : 18;\
}
union { UNSG32 u32CSC_const_C5;
struct w32CSC_const_C5;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C6_C6(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C6_C6(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C6_C6(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C6_C6(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C6 {\
UNSG32 uconst_C6_C6 : 14;\
UNSG32 RSVDx18_b14 : 18;\
}
union { UNSG32 u32CSC_const_C6;
struct w32CSC_const_C6;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C7_C7(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C7_C7(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C7_C7(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C7_C7(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C7 {\
UNSG32 uconst_C7_C7 : 14;\
UNSG32 RSVDx1C_b14 : 18;\
}
union { UNSG32 u32CSC_const_C7;
struct w32CSC_const_C7;
};
///////////////////////////////////////////////////////////
#define GET32CSC_const_C8_C8(r32) _BFGET_(r32,13, 0)
#define SET32CSC_const_C8_C8(r32,v) _BFSET_(r32,13, 0,v)
#define GET16CSC_const_C8_C8(r16) _BFGET_(r16,13, 0)
#define SET16CSC_const_C8_C8(r16,v) _BFSET_(r16,13, 0,v)
#define w32CSC_const_C8 {\
UNSG32 uconst_C8_C8 : 14;\
UNSG32 RSVDx20_b14 : 18;\
}
union { UNSG32 u32CSC_const_C8;
struct w32CSC_const_C8;
};
///////////////////////////////////////////////////////////
#define GET32CSC_off_A0_A0(r32) _BFGET_(r32,15, 0)
#define SET32CSC_off_A0_A0(r32,v) _BFSET_(r32,15, 0,v)
#define GET16CSC_off_A0_A0(r16) _BFGET_(r16,15, 0)
#define SET16CSC_off_A0_A0(r16,v) _BFSET_(r16,15, 0,v)
#define w32CSC_off_A0 {\
UNSG32 uoff_A0_A0 : 16;\
UNSG32 RSVDx24_b16 : 16;\
}
union { UNSG32 u32CSC_off_A0;
struct w32CSC_off_A0;
};
///////////////////////////////////////////////////////////
#define GET32CSC_off_A1_A1(r32) _BFGET_(r32,15, 0)
#define SET32CSC_off_A1_A1(r32,v) _BFSET_(r32,15, 0,v)
#define GET16CSC_off_A1_A1(r16) _BFGET_(r16,15, 0)
#define SET16CSC_off_A1_A1(r16,v) _BFSET_(r16,15, 0,v)
#define w32CSC_off_A1 {\
UNSG32 uoff_A1_A1 : 16;\
UNSG32 RSVDx28_b16 : 16;\
}
union { UNSG32 u32CSC_off_A1;
struct w32CSC_off_A1;
};
///////////////////////////////////////////////////////////
#define GET32CSC_off_A2_A2(r32) _BFGET_(r32,15, 0)
#define SET32CSC_off_A2_A2(r32,v) _BFSET_(r32,15, 0,v)
#define GET16CSC_off_A2_A2(r16) _BFGET_(r16,15, 0)
#define SET16CSC_off_A2_A2(r16,v) _BFSET_(r16,15, 0,v)
#define w32CSC_off_A2 {\
UNSG32 uoff_A2_A2 : 16;\
UNSG32 RSVDx2C_b16 : 16;\
}
union { UNSG32 u32CSC_off_A2;
struct w32CSC_off_A2;
};
///////////////////////////////////////////////////////////
} SIE_CSC;
typedef union T32CSC_const_C0
{ UNSG32 u32;
struct w32CSC_const_C0;
} T32CSC_const_C0;
typedef union T32CSC_const_C1
{ UNSG32 u32;
struct w32CSC_const_C1;
} T32CSC_const_C1;
typedef union T32CSC_const_C2
{ UNSG32 u32;
struct w32CSC_const_C2;
} T32CSC_const_C2;
typedef union T32CSC_const_C3
{ UNSG32 u32;
struct w32CSC_const_C3;
} T32CSC_const_C3;
typedef union T32CSC_const_C4
{ UNSG32 u32;
struct w32CSC_const_C4;
} T32CSC_const_C4;
typedef union T32CSC_const_C5
{ UNSG32 u32;
struct w32CSC_const_C5;
} T32CSC_const_C5;
typedef union T32CSC_const_C6
{ UNSG32 u32;
struct w32CSC_const_C6;
} T32CSC_const_C6;
typedef union T32CSC_const_C7
{ UNSG32 u32;
struct w32CSC_const_C7;
} T32CSC_const_C7;
typedef union T32CSC_const_C8
{ UNSG32 u32;
struct w32CSC_const_C8;
} T32CSC_const_C8;
typedef union T32CSC_off_A0
{ UNSG32 u32;
struct w32CSC_off_A0;
} T32CSC_off_A0;
typedef union T32CSC_off_A1
{ UNSG32 u32;
struct w32CSC_off_A1;
} T32CSC_off_A1;
typedef union T32CSC_off_A2
{ UNSG32 u32;
struct w32CSC_off_A2;
} T32CSC_off_A2;
///////////////////////////////////////////////////////////
typedef union TCSC_const_C0
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C0;
};
} TCSC_const_C0;
typedef union TCSC_const_C1
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C1;
};
} TCSC_const_C1;
typedef union TCSC_const_C2
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C2;
};
} TCSC_const_C2;
typedef union TCSC_const_C3
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C3;
};
} TCSC_const_C3;
typedef union TCSC_const_C4
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C4;
};
} TCSC_const_C4;
typedef union TCSC_const_C5
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C5;
};
} TCSC_const_C5;
typedef union TCSC_const_C6
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C6;
};
} TCSC_const_C6;
typedef union TCSC_const_C7
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C7;
};
} TCSC_const_C7;
typedef union TCSC_const_C8
{ UNSG32 u32[1];
struct {
struct w32CSC_const_C8;
};
} TCSC_const_C8;
typedef union TCSC_off_A0
{ UNSG32 u32[1];
struct {
struct w32CSC_off_A0;
};
} TCSC_off_A0;
typedef union TCSC_off_A1
{ UNSG32 u32[1];
struct {
struct w32CSC_off_A1;
};
} TCSC_off_A1;
typedef union TCSC_off_A2
{ UNSG32 u32[1];
struct {
struct w32CSC_off_A2;
};
} TCSC_off_A2;
///////////////////////////////////////////////////////////
SIGN32 CSC_drvrd(SIE_CSC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CSC_drvwr(SIE_CSC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CSC_reset(SIE_CSC *p);
SIGN32 CSC_cmp (SIE_CSC *p, SIE_CSC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CSC_check(p,pie,pfx,hLOG) CSC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CSC_print(p, pfx,hLOG) CSC_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CSC
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE ICSC (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 const_C0 (P)
/// %unsigned 14 C0 0x200
/// %% 18 # Stuffing bits...
/// @ 0x00004 const_C1 (P)
/// %unsigned 14 C1 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00008 const_C2 (P)
/// %unsigned 14 C2 0x0
/// %% 18 # Stuffing bits...
/// @ 0x0000C const_C3 (P)
/// %unsigned 14 C3 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00010 const_C4 (P)
/// %unsigned 14 C4 0x200
/// %% 18 # Stuffing bits...
/// @ 0x00014 const_C5 (P)
/// %unsigned 14 C5 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00018 const_C6 (P)
/// %unsigned 14 C6 0x0
/// %% 18 # Stuffing bits...
/// @ 0x0001C const_C7 (P)
/// %unsigned 14 C7 0x0
/// %% 18 # Stuffing bits...
/// @ 0x00020 const_C8 (P)
/// %unsigned 14 C8 0x200
/// ###
/// * Coefficients used by ICSC.
/// ###
/// %% 18 # Stuffing bits...
/// @ 0x00024 off_A0 (P)
/// %unsigned 18 A0 0x0
/// %% 14 # Stuffing bits...
/// @ 0x00028 off_A1 (P)
/// %unsigned 18 A1 0x0
/// %% 14 # Stuffing bits...
/// @ 0x0002C off_A2 (P)
/// %unsigned 18 A2 0x0
/// ###
/// * Offsets used by ICSC.
/// ###
/// %% 14 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 48B, bits: 180b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_ICSC
#define h_ICSC (){}
#define RA_ICSC_const_C0 0x0000
#define BA_ICSC_const_C0_C0 0x0000
#define B16ICSC_const_C0_C0 0x0000
#define LSb32ICSC_const_C0_C0 0
#define LSb16ICSC_const_C0_C0 0
#define bICSC_const_C0_C0 14
#define MSK32ICSC_const_C0_C0 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C1 0x0004
#define BA_ICSC_const_C1_C1 0x0004
#define B16ICSC_const_C1_C1 0x0004
#define LSb32ICSC_const_C1_C1 0
#define LSb16ICSC_const_C1_C1 0
#define bICSC_const_C1_C1 14
#define MSK32ICSC_const_C1_C1 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C2 0x0008
#define BA_ICSC_const_C2_C2 0x0008
#define B16ICSC_const_C2_C2 0x0008
#define LSb32ICSC_const_C2_C2 0
#define LSb16ICSC_const_C2_C2 0
#define bICSC_const_C2_C2 14
#define MSK32ICSC_const_C2_C2 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C3 0x000C
#define BA_ICSC_const_C3_C3 0x000C
#define B16ICSC_const_C3_C3 0x000C
#define LSb32ICSC_const_C3_C3 0
#define LSb16ICSC_const_C3_C3 0
#define bICSC_const_C3_C3 14
#define MSK32ICSC_const_C3_C3 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C4 0x0010
#define BA_ICSC_const_C4_C4 0x0010
#define B16ICSC_const_C4_C4 0x0010
#define LSb32ICSC_const_C4_C4 0
#define LSb16ICSC_const_C4_C4 0
#define bICSC_const_C4_C4 14
#define MSK32ICSC_const_C4_C4 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C5 0x0014
#define BA_ICSC_const_C5_C5 0x0014
#define B16ICSC_const_C5_C5 0x0014
#define LSb32ICSC_const_C5_C5 0
#define LSb16ICSC_const_C5_C5 0
#define bICSC_const_C5_C5 14
#define MSK32ICSC_const_C5_C5 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C6 0x0018
#define BA_ICSC_const_C6_C6 0x0018
#define B16ICSC_const_C6_C6 0x0018
#define LSb32ICSC_const_C6_C6 0
#define LSb16ICSC_const_C6_C6 0
#define bICSC_const_C6_C6 14
#define MSK32ICSC_const_C6_C6 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C7 0x001C
#define BA_ICSC_const_C7_C7 0x001C
#define B16ICSC_const_C7_C7 0x001C
#define LSb32ICSC_const_C7_C7 0
#define LSb16ICSC_const_C7_C7 0
#define bICSC_const_C7_C7 14
#define MSK32ICSC_const_C7_C7 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_const_C8 0x0020
#define BA_ICSC_const_C8_C8 0x0020
#define B16ICSC_const_C8_C8 0x0020
#define LSb32ICSC_const_C8_C8 0
#define LSb16ICSC_const_C8_C8 0
#define bICSC_const_C8_C8 14
#define MSK32ICSC_const_C8_C8 0x00003FFF
///////////////////////////////////////////////////////////
#define RA_ICSC_off_A0 0x0024
#define BA_ICSC_off_A0_A0 0x0024
#define B16ICSC_off_A0_A0 0x0024
#define LSb32ICSC_off_A0_A0 0
#define LSb16ICSC_off_A0_A0 0
#define bICSC_off_A0_A0 18
#define MSK32ICSC_off_A0_A0 0x0003FFFF
///////////////////////////////////////////////////////////
#define RA_ICSC_off_A1 0x0028
#define BA_ICSC_off_A1_A1 0x0028
#define B16ICSC_off_A1_A1 0x0028
#define LSb32ICSC_off_A1_A1 0
#define LSb16ICSC_off_A1_A1 0
#define bICSC_off_A1_A1 18
#define MSK32ICSC_off_A1_A1 0x0003FFFF
///////////////////////////////////////////////////////////
#define RA_ICSC_off_A2 0x002C
#define BA_ICSC_off_A2_A2 0x002C
#define B16ICSC_off_A2_A2 0x002C
#define LSb32ICSC_off_A2_A2 0
#define LSb16ICSC_off_A2_A2 0
#define bICSC_off_A2_A2 18
#define MSK32ICSC_off_A2_A2 0x0003FFFF
///////////////////////////////////////////////////////////
typedef struct SIE_ICSC {
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C0_C0(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C0_C0(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C0_C0(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C0_C0(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C0 {\
UNSG32 uconst_C0_C0 : 14;\
UNSG32 RSVDx0_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C0;
struct w32ICSC_const_C0;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C1_C1(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C1_C1(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C1_C1(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C1_C1(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C1 {\
UNSG32 uconst_C1_C1 : 14;\
UNSG32 RSVDx4_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C1;
struct w32ICSC_const_C1;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C2_C2(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C2_C2(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C2_C2(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C2_C2(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C2 {\
UNSG32 uconst_C2_C2 : 14;\
UNSG32 RSVDx8_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C2;
struct w32ICSC_const_C2;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C3_C3(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C3_C3(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C3_C3(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C3_C3(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C3 {\
UNSG32 uconst_C3_C3 : 14;\
UNSG32 RSVDxC_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C3;
struct w32ICSC_const_C3;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C4_C4(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C4_C4(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C4_C4(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C4_C4(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C4 {\
UNSG32 uconst_C4_C4 : 14;\
UNSG32 RSVDx10_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C4;
struct w32ICSC_const_C4;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C5_C5(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C5_C5(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C5_C5(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C5_C5(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C5 {\
UNSG32 uconst_C5_C5 : 14;\
UNSG32 RSVDx14_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C5;
struct w32ICSC_const_C5;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C6_C6(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C6_C6(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C6_C6(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C6_C6(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C6 {\
UNSG32 uconst_C6_C6 : 14;\
UNSG32 RSVDx18_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C6;
struct w32ICSC_const_C6;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C7_C7(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C7_C7(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C7_C7(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C7_C7(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C7 {\
UNSG32 uconst_C7_C7 : 14;\
UNSG32 RSVDx1C_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C7;
struct w32ICSC_const_C7;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_const_C8_C8(r32) _BFGET_(r32,13, 0)
#define SET32ICSC_const_C8_C8(r32,v) _BFSET_(r32,13, 0,v)
#define GET16ICSC_const_C8_C8(r16) _BFGET_(r16,13, 0)
#define SET16ICSC_const_C8_C8(r16,v) _BFSET_(r16,13, 0,v)
#define w32ICSC_const_C8 {\
UNSG32 uconst_C8_C8 : 14;\
UNSG32 RSVDx20_b14 : 18;\
}
union { UNSG32 u32ICSC_const_C8;
struct w32ICSC_const_C8;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_off_A0_A0(r32) _BFGET_(r32,17, 0)
#define SET32ICSC_off_A0_A0(r32,v) _BFSET_(r32,17, 0,v)
#define w32ICSC_off_A0 {\
UNSG32 uoff_A0_A0 : 18;\
UNSG32 RSVDx24_b18 : 14;\
}
union { UNSG32 u32ICSC_off_A0;
struct w32ICSC_off_A0;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_off_A1_A1(r32) _BFGET_(r32,17, 0)
#define SET32ICSC_off_A1_A1(r32,v) _BFSET_(r32,17, 0,v)
#define w32ICSC_off_A1 {\
UNSG32 uoff_A1_A1 : 18;\
UNSG32 RSVDx28_b18 : 14;\
}
union { UNSG32 u32ICSC_off_A1;
struct w32ICSC_off_A1;
};
///////////////////////////////////////////////////////////
#define GET32ICSC_off_A2_A2(r32) _BFGET_(r32,17, 0)
#define SET32ICSC_off_A2_A2(r32,v) _BFSET_(r32,17, 0,v)
#define w32ICSC_off_A2 {\
UNSG32 uoff_A2_A2 : 18;\
UNSG32 RSVDx2C_b18 : 14;\
}
union { UNSG32 u32ICSC_off_A2;
struct w32ICSC_off_A2;
};
///////////////////////////////////////////////////////////
} SIE_ICSC;
typedef union T32ICSC_const_C0
{ UNSG32 u32;
struct w32ICSC_const_C0;
} T32ICSC_const_C0;
typedef union T32ICSC_const_C1
{ UNSG32 u32;
struct w32ICSC_const_C1;
} T32ICSC_const_C1;
typedef union T32ICSC_const_C2
{ UNSG32 u32;
struct w32ICSC_const_C2;
} T32ICSC_const_C2;
typedef union T32ICSC_const_C3
{ UNSG32 u32;
struct w32ICSC_const_C3;
} T32ICSC_const_C3;
typedef union T32ICSC_const_C4
{ UNSG32 u32;
struct w32ICSC_const_C4;
} T32ICSC_const_C4;
typedef union T32ICSC_const_C5
{ UNSG32 u32;
struct w32ICSC_const_C5;
} T32ICSC_const_C5;
typedef union T32ICSC_const_C6
{ UNSG32 u32;
struct w32ICSC_const_C6;
} T32ICSC_const_C6;
typedef union T32ICSC_const_C7
{ UNSG32 u32;
struct w32ICSC_const_C7;
} T32ICSC_const_C7;
typedef union T32ICSC_const_C8
{ UNSG32 u32;
struct w32ICSC_const_C8;
} T32ICSC_const_C8;
typedef union T32ICSC_off_A0
{ UNSG32 u32;
struct w32ICSC_off_A0;
} T32ICSC_off_A0;
typedef union T32ICSC_off_A1
{ UNSG32 u32;
struct w32ICSC_off_A1;
} T32ICSC_off_A1;
typedef union T32ICSC_off_A2
{ UNSG32 u32;
struct w32ICSC_off_A2;
} T32ICSC_off_A2;
///////////////////////////////////////////////////////////
typedef union TICSC_const_C0
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C0;
};
} TICSC_const_C0;
typedef union TICSC_const_C1
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C1;
};
} TICSC_const_C1;
typedef union TICSC_const_C2
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C2;
};
} TICSC_const_C2;
typedef union TICSC_const_C3
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C3;
};
} TICSC_const_C3;
typedef union TICSC_const_C4
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C4;
};
} TICSC_const_C4;
typedef union TICSC_const_C5
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C5;
};
} TICSC_const_C5;
typedef union TICSC_const_C6
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C6;
};
} TICSC_const_C6;
typedef union TICSC_const_C7
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C7;
};
} TICSC_const_C7;
typedef union TICSC_const_C8
{ UNSG32 u32[1];
struct {
struct w32ICSC_const_C8;
};
} TICSC_const_C8;
typedef union TICSC_off_A0
{ UNSG32 u32[1];
struct {
struct w32ICSC_off_A0;
};
} TICSC_off_A0;
typedef union TICSC_off_A1
{ UNSG32 u32[1];
struct {
struct w32ICSC_off_A1;
};
} TICSC_off_A1;
typedef union TICSC_off_A2
{ UNSG32 u32[1];
struct {
struct w32ICSC_off_A2;
};
} TICSC_off_A2;
///////////////////////////////////////////////////////////
SIGN32 ICSC_drvrd(SIE_ICSC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 ICSC_drvwr(SIE_ICSC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void ICSC_reset(SIE_ICSC *p);
SIGN32 ICSC_cmp (SIE_ICSC *p, SIE_ICSC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define ICSC_check(p,pie,pfx,hLOG) ICSC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define ICSC_print(p, pfx,hLOG) ICSC_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: ICSC
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE INV_SCAN (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 SEL (P)
/// %unsigned 3 BYTE0 0x0
/// %unsigned 3 BYTE1 0x1
/// %unsigned 3 BYTE2 0x2
/// %unsigned 3 BYTE3 0x3
/// %unsigned 3 BYTE4 0x4
/// %unsigned 3 BYTE5 0x5
/// %unsigned 3 BYTE6 0x6
/// %unsigned 3 BYTE7 0x7
/// ###
/// * Specifies mapping of new byte locations within 64 bit data from DRAM which need to be used to form pixels for Inverse Scan mode.
/// * Normal dHub data order:
/// * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in LSB
/// * Inverse Scan dHub data order:
/// * {Y3,Cr2,Y2,Cb2,Y1,Cr0,Y0,Cb0} First pixel in MSB
/// * Following different data orders can be generated to be presented to first UPS in the pipe.
/// * UPS_IN_ORDER1:
/// * {Y0,Cr0,Y1,Cb0,Y2,Cr2,Y3,Cb2} => {1,2,3,0,5,6,7,4} [byte order change w.r.t. dHub byte order]
/// * y_shift=0, c_shift=0, cb_cr_swap=0 (for 1st UPS)
/// * UPS_IN_ORDER2:
/// * {Y0,Cb0,Y1,Cr0,Y2,Cb2,Y3,Cr2} => {1,0,3,2,5,4,7,6} [byte order change w.r.t. dHub byte order]
/// * y_shift=1, c_shift=0, cb_cr_swap=0 (for 1st UPS)
/// * UPS_IN_ORDER3:
/// * {Y0,Cb0,Y1,Cr0,Y2,Cb2,Y3,Cr2} => {1,0,3,2,5,4,7,6} [byte order change w.r.t. dHub byte order]
/// * y_shift=0, c_shift=0, cb_cr_swap=1 (for 1st UPS)
/// ###
/// %% 8 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 24b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_INV_SCAN
#define h_INV_SCAN (){}
#define RA_INV_SCAN_SEL 0x0000
#define BA_INV_SCAN_SEL_BYTE0 0x0000
#define B16INV_SCAN_SEL_BYTE0 0x0000
#define LSb32INV_SCAN_SEL_BYTE0 0
#define LSb16INV_SCAN_SEL_BYTE0 0
#define bINV_SCAN_SEL_BYTE0 3
#define MSK32INV_SCAN_SEL_BYTE0 0x00000007
#define BA_INV_SCAN_SEL_BYTE1 0x0000
#define B16INV_SCAN_SEL_BYTE1 0x0000
#define LSb32INV_SCAN_SEL_BYTE1 3
#define LSb16INV_SCAN_SEL_BYTE1 3
#define bINV_SCAN_SEL_BYTE1 3
#define MSK32INV_SCAN_SEL_BYTE1 0x00000038
#define BA_INV_SCAN_SEL_BYTE2 0x0000
#define B16INV_SCAN_SEL_BYTE2 0x0000
#define LSb32INV_SCAN_SEL_BYTE2 6
#define LSb16INV_SCAN_SEL_BYTE2 6
#define bINV_SCAN_SEL_BYTE2 3
#define MSK32INV_SCAN_SEL_BYTE2 0x000001C0
#define BA_INV_SCAN_SEL_BYTE3 0x0001
#define B16INV_SCAN_SEL_BYTE3 0x0000
#define LSb32INV_SCAN_SEL_BYTE3 9
#define LSb16INV_SCAN_SEL_BYTE3 9
#define bINV_SCAN_SEL_BYTE3 3
#define MSK32INV_SCAN_SEL_BYTE3 0x00000E00
#define BA_INV_SCAN_SEL_BYTE4 0x0001
#define B16INV_SCAN_SEL_BYTE4 0x0000
#define LSb32INV_SCAN_SEL_BYTE4 12
#define LSb16INV_SCAN_SEL_BYTE4 12
#define bINV_SCAN_SEL_BYTE4 3
#define MSK32INV_SCAN_SEL_BYTE4 0x00007000
#define BA_INV_SCAN_SEL_BYTE5 0x0001
#define B16INV_SCAN_SEL_BYTE5 0x0000
#define LSb32INV_SCAN_SEL_BYTE5 15
#define LSb16INV_SCAN_SEL_BYTE5 15
#define bINV_SCAN_SEL_BYTE5 3
#define MSK32INV_SCAN_SEL_BYTE5 0x00038000
#define BA_INV_SCAN_SEL_BYTE6 0x0002
#define B16INV_SCAN_SEL_BYTE6 0x0002
#define LSb32INV_SCAN_SEL_BYTE6 18
#define LSb16INV_SCAN_SEL_BYTE6 2
#define bINV_SCAN_SEL_BYTE6 3
#define MSK32INV_SCAN_SEL_BYTE6 0x001C0000
#define BA_INV_SCAN_SEL_BYTE7 0x0002
#define B16INV_SCAN_SEL_BYTE7 0x0002
#define LSb32INV_SCAN_SEL_BYTE7 21
#define LSb16INV_SCAN_SEL_BYTE7 5
#define bINV_SCAN_SEL_BYTE7 3
#define MSK32INV_SCAN_SEL_BYTE7 0x00E00000
///////////////////////////////////////////////////////////
typedef struct SIE_INV_SCAN {
///////////////////////////////////////////////////////////
#define GET32INV_SCAN_SEL_BYTE0(r32) _BFGET_(r32, 2, 0)
#define SET32INV_SCAN_SEL_BYTE0(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16INV_SCAN_SEL_BYTE0(r16) _BFGET_(r16, 2, 0)
#define SET16INV_SCAN_SEL_BYTE0(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32INV_SCAN_SEL_BYTE1(r32) _BFGET_(r32, 5, 3)
#define SET32INV_SCAN_SEL_BYTE1(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16INV_SCAN_SEL_BYTE1(r16) _BFGET_(r16, 5, 3)
#define SET16INV_SCAN_SEL_BYTE1(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32INV_SCAN_SEL_BYTE2(r32) _BFGET_(r32, 8, 6)
#define SET32INV_SCAN_SEL_BYTE2(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16INV_SCAN_SEL_BYTE2(r16) _BFGET_(r16, 8, 6)
#define SET16INV_SCAN_SEL_BYTE2(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32INV_SCAN_SEL_BYTE3(r32) _BFGET_(r32,11, 9)
#define SET32INV_SCAN_SEL_BYTE3(r32,v) _BFSET_(r32,11, 9,v)
#define GET16INV_SCAN_SEL_BYTE3(r16) _BFGET_(r16,11, 9)
#define SET16INV_SCAN_SEL_BYTE3(r16,v) _BFSET_(r16,11, 9,v)
#define GET32INV_SCAN_SEL_BYTE4(r32) _BFGET_(r32,14,12)
#define SET32INV_SCAN_SEL_BYTE4(r32,v) _BFSET_(r32,14,12,v)
#define GET16INV_SCAN_SEL_BYTE4(r16) _BFGET_(r16,14,12)
#define SET16INV_SCAN_SEL_BYTE4(r16,v) _BFSET_(r16,14,12,v)
#define GET32INV_SCAN_SEL_BYTE5(r32) _BFGET_(r32,17,15)
#define SET32INV_SCAN_SEL_BYTE5(r32,v) _BFSET_(r32,17,15,v)
#define GET32INV_SCAN_SEL_BYTE6(r32) _BFGET_(r32,20,18)
#define SET32INV_SCAN_SEL_BYTE6(r32,v) _BFSET_(r32,20,18,v)
#define GET16INV_SCAN_SEL_BYTE6(r16) _BFGET_(r16, 4, 2)
#define SET16INV_SCAN_SEL_BYTE6(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32INV_SCAN_SEL_BYTE7(r32) _BFGET_(r32,23,21)
#define SET32INV_SCAN_SEL_BYTE7(r32,v) _BFSET_(r32,23,21,v)
#define GET16INV_SCAN_SEL_BYTE7(r16) _BFGET_(r16, 7, 5)
#define SET16INV_SCAN_SEL_BYTE7(r16,v) _BFSET_(r16, 7, 5,v)
#define w32INV_SCAN_SEL {\
UNSG32 uSEL_BYTE0 : 3;\
UNSG32 uSEL_BYTE1 : 3;\
UNSG32 uSEL_BYTE2 : 3;\
UNSG32 uSEL_BYTE3 : 3;\
UNSG32 uSEL_BYTE4 : 3;\
UNSG32 uSEL_BYTE5 : 3;\
UNSG32 uSEL_BYTE6 : 3;\
UNSG32 uSEL_BYTE7 : 3;\
UNSG32 RSVDx0_b24 : 8;\
}
union { UNSG32 u32INV_SCAN_SEL;
struct w32INV_SCAN_SEL;
};
///////////////////////////////////////////////////////////
} SIE_INV_SCAN;
typedef union T32INV_SCAN_SEL
{ UNSG32 u32;
struct w32INV_SCAN_SEL;
} T32INV_SCAN_SEL;
///////////////////////////////////////////////////////////
typedef union TINV_SCAN_SEL
{ UNSG32 u32[1];
struct {
struct w32INV_SCAN_SEL;
};
} TINV_SCAN_SEL;
///////////////////////////////////////////////////////////
SIGN32 INV_SCAN_drvrd(SIE_INV_SCAN *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 INV_SCAN_drvwr(SIE_INV_SCAN *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void INV_SCAN_reset(SIE_INV_SCAN *p);
SIGN32 INV_SCAN_cmp (SIE_INV_SCAN *p, SIE_INV_SCAN *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define INV_SCAN_check(p,pie,pfx,hLOG) INV_SCAN_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define INV_SCAN_print(p, pfx,hLOG) INV_SCAN_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: INV_SCAN
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SENSIO biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// %unsigned 1 Process_Enable 0x0
/// ###
/// * Sensio Filter Enable
/// ###
/// %unsigned 1 LR_frame 0x0
/// ###
/// * 0: Left Frame
/// * 1: Right Frame
/// ###
/// %unsigned 1 SCL_bypass 0x1
/// ###
/// * HSCALE Bypass Enable.
/// ###
/// %unsigned 1 SCL_ups_en 0x1
/// ###
/// * Up Sampler (outside HSCALE) Enable bit
/// ###
/// %unsigned 1 SCL_dns_en 0x1
/// ###
/// * Down Sampler (inside HSCALE) Enable bit
/// ###
/// %unsigned 12 SCL_ihres 0x0
/// ###
/// * Input X resolution (SCL_IHRES) for HSCALE
/// ###
/// %unsigned 12 SCL_ohres 0x0
/// ###
/// * Output X resolution (SCL_OHRES) for HSCALE
/// ###
/// %unsigned 1 SCL_black 0x0
/// ###
/// * Always 0, YUV color space for HSCALE
/// ###
/// %% 2 # Stuffing bits...
/// %unsigned 5 SCL_sign_frac 0x0
/// ###
/// * Horizontal scalar coefficients format for HSCALE
/// * frac[3:0]: Number of fractional bits in the coefficient (8-12d)
/// * sign[4]: Stores the format of the scalar coefficients.
/// * 0 : Unsigned 12 bit coefficient
/// * 1 : Signed 12 bit coefficient in sign magnitude format.
/// ###
/// %unsigned 24 SCL_hratio 0x0
/// ###
/// * Horizontal DDA Increment (SCL_HRATIO) for HSCALE
/// ###
/// %% 3 # Stuffing bits...
/// %unsigned 20 SCL_hinitph 0x0
/// ###
/// * MSB 8 Bits: Initial phase fo horizontal DDA Counter (SCL_HINITPH) for HSCALE.
/// * LSB 12 Bits = 0
/// ###
/// %unsigned 5 SCL_init_centertap 0x0
/// ###
/// * {{2{htap_offset[2]}}, htap_offset[2:0]}, where
/// * htap_offset[2:0] - Tap offset in Hscale from the normal value (SCL_HTAP) for HSCALE.
/// * Tap offset in hscalar. Indicates change in the number of black pixels at the beginning of the line from the normal calculations. Usually, the number of initial black pixels is 5. Initial number of black pixels vary as follows with the register value:
/// * 000: 5
/// * 001: 6
/// * 010: 7
/// * 011: 8
/// * 100: 1
/// * 101: 2
/// * 110: 3
/// * 111: 4
/// ###
/// %unsigned 1 SCL_hnl_en 0x0
/// ###
/// * Horizontal non-linear mode enable for HSCALE
/// * 0 : Horizontal non-linear scaling disabled (Default)
/// * 1 : Horizontal non-linear scaling enabled
/// ###
/// %% 6 # Stuffing bits...
/// %unsigned 12 SCL_nlxres 0x0
/// ###
/// * Value of (SCL_OHRES – SCL_NLCRES)>>1 for HSCALE
/// ###
/// %unsigned 12 SCL_cxres 0x0
/// ###
/// * Central undistorted width of the output image in non-linear 3 zone scaling (SCL_NLCRES) for HSCALE.
/// ###
/// %% 8 # Stuffing bits...
/// %unsigned 24 SCL_init_ratio 0x0
/// ###
/// * Initial DDA increment for NL3zone (SCL_INIT_RATIO) for HSCALE.
/// ###
/// %% 8 # Stuffing bits...
/// %unsigned 24 SCL_inc_ratio 0x0
/// ###
/// * Increment to DDA increment for NL3zone (SCL_INC_RATIO) for HSCALE
/// ###
/// %unsigned 3 SCL_crop_ctrl 0x0
/// ###
/// * Crops the first pixel and/or last pixel before the H-scaler (after 422->444 conversion) of the Main channel.
/// * [0]: controls 1st pixel crop, 1: crop first pixel, 0: don't crop first pixel
/// * [1]: controls last pixel crop, 1: crop last pixel, 0: don't crop last pixel.
/// * [2]: controls last 2 pixel crop, 1: crop last two pixels, 0: don't crop last two pixels. Note: Setting bit[2] to 1 makes bit [1] don't care.
/// ###
/// %% 5 # Stuffing bits...
/// %unsigned 8 LB_dummy_data 0x0
/// %unsigned 8 SCL_prog_delay 0x18
/// ###
/// * This parameter needs to be programmed depending on latency through hscale module for a downscale factor(D).
/// * Hscale has following latency for different downscale factors.
/// * D=1 , Latency = 24
/// * D=2, Latency = 40
/// * D=4, Latency = 72
/// * Generalized Eqn for Latency = (8 + 16D)
/// ###
/// %unsigned 8 SCL_VDE_Dly 0x30
/// ###
/// * This needs to be programmed to (Hblank/2)-2; where Hblank is Horizontal blanking programmed for VP_TG.
/// ###
/// %unsigned 1 SCL_VDE_Sel 0x0
/// ###
/// * 0: VDE generated using SCL_VDE_Dly
/// * 1: VDE generated using SCL_prog_delay
/// * Control signals for Sensio Integration.
/// ###
/// %% 7 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 28B, bits: 185b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SENSIO
#define h_SENSIO (){}
#define BA_SENSIO_Process_Enable 0x0000
#define B16SENSIO_Process_Enable 0x0000
#define LSb32SENSIO_Process_Enable 0
#define LSb16SENSIO_Process_Enable 0
#define bSENSIO_Process_Enable 1
#define MSK32SENSIO_Process_Enable 0x00000001
#define BA_SENSIO_LR_frame 0x0000
#define B16SENSIO_LR_frame 0x0000
#define LSb32SENSIO_LR_frame 1
#define LSb16SENSIO_LR_frame 1
#define bSENSIO_LR_frame 1
#define MSK32SENSIO_LR_frame 0x00000002
#define BA_SENSIO_SCL_bypass 0x0000
#define B16SENSIO_SCL_bypass 0x0000
#define LSb32SENSIO_SCL_bypass 2
#define LSb16SENSIO_SCL_bypass 2
#define bSENSIO_SCL_bypass 1
#define MSK32SENSIO_SCL_bypass 0x00000004
#define BA_SENSIO_SCL_ups_en 0x0000
#define B16SENSIO_SCL_ups_en 0x0000
#define LSb32SENSIO_SCL_ups_en 3
#define LSb16SENSIO_SCL_ups_en 3
#define bSENSIO_SCL_ups_en 1
#define MSK32SENSIO_SCL_ups_en 0x00000008
#define BA_SENSIO_SCL_dns_en 0x0000
#define B16SENSIO_SCL_dns_en 0x0000
#define LSb32SENSIO_SCL_dns_en 4
#define LSb16SENSIO_SCL_dns_en 4
#define bSENSIO_SCL_dns_en 1
#define MSK32SENSIO_SCL_dns_en 0x00000010
#define BA_SENSIO_SCL_ihres 0x0000
#define B16SENSIO_SCL_ihres 0x0000
#define LSb32SENSIO_SCL_ihres 5
#define LSb16SENSIO_SCL_ihres 5
#define bSENSIO_SCL_ihres 12
#define MSK32SENSIO_SCL_ihres 0x0001FFE0
#define BA_SENSIO_SCL_ohres 0x0002
#define B16SENSIO_SCL_ohres 0x0002
#define LSb32SENSIO_SCL_ohres 17
#define LSb16SENSIO_SCL_ohres 1
#define bSENSIO_SCL_ohres 12
#define MSK32SENSIO_SCL_ohres 0x1FFE0000
#define BA_SENSIO_SCL_black 0x0003
#define B16SENSIO_SCL_black 0x0002
#define LSb32SENSIO_SCL_black 29
#define LSb16SENSIO_SCL_black 13
#define bSENSIO_SCL_black 1
#define MSK32SENSIO_SCL_black 0x20000000
#define BA_SENSIO_SCL_sign_frac 0x0004
#define B16SENSIO_SCL_sign_frac 0x0004
#define LSb32SENSIO_SCL_sign_frac 0
#define LSb16SENSIO_SCL_sign_frac 0
#define bSENSIO_SCL_sign_frac 5
#define MSK32SENSIO_SCL_sign_frac 0x0000001F
#define BA_SENSIO_SCL_hratio 0x0004
#define B16SENSIO_SCL_hratio 0x0004
#define LSb32SENSIO_SCL_hratio 5
#define LSb16SENSIO_SCL_hratio 5
#define bSENSIO_SCL_hratio 24
#define MSK32SENSIO_SCL_hratio 0x1FFFFFE0
#define BA_SENSIO_SCL_hinitph 0x0008
#define B16SENSIO_SCL_hinitph 0x0008
#define LSb32SENSIO_SCL_hinitph 0
#define LSb16SENSIO_SCL_hinitph 0
#define bSENSIO_SCL_hinitph 20
#define MSK32SENSIO_SCL_hinitph 0x000FFFFF
#define BA_SENSIO_SCL_init_centertap 0x000A
#define B16SENSIO_SCL_init_centertap 0x000A
#define LSb32SENSIO_SCL_init_centertap 20
#define LSb16SENSIO_SCL_init_centertap 4
#define bSENSIO_SCL_init_centertap 5
#define MSK32SENSIO_SCL_init_centertap 0x01F00000
#define BA_SENSIO_SCL_hnl_en 0x000B
#define B16SENSIO_SCL_hnl_en 0x000A
#define LSb32SENSIO_SCL_hnl_en 25
#define LSb16SENSIO_SCL_hnl_en 9
#define bSENSIO_SCL_hnl_en 1
#define MSK32SENSIO_SCL_hnl_en 0x02000000
#define BA_SENSIO_SCL_nlxres 0x000C
#define B16SENSIO_SCL_nlxres 0x000C
#define LSb32SENSIO_SCL_nlxres 0
#define LSb16SENSIO_SCL_nlxres 0
#define bSENSIO_SCL_nlxres 12
#define MSK32SENSIO_SCL_nlxres 0x00000FFF
#define BA_SENSIO_SCL_cxres 0x000D
#define B16SENSIO_SCL_cxres 0x000C
#define LSb32SENSIO_SCL_cxres 12
#define LSb16SENSIO_SCL_cxres 12
#define bSENSIO_SCL_cxres 12
#define MSK32SENSIO_SCL_cxres 0x00FFF000
#define BA_SENSIO_SCL_init_ratio 0x0010
#define B16SENSIO_SCL_init_ratio 0x0010
#define LSb32SENSIO_SCL_init_ratio 0
#define LSb16SENSIO_SCL_init_ratio 0
#define bSENSIO_SCL_init_ratio 24
#define MSK32SENSIO_SCL_init_ratio 0x00FFFFFF
#define BA_SENSIO_SCL_inc_ratio 0x0014
#define B16SENSIO_SCL_inc_ratio 0x0014
#define LSb32SENSIO_SCL_inc_ratio 0
#define LSb16SENSIO_SCL_inc_ratio 0
#define bSENSIO_SCL_inc_ratio 24
#define MSK32SENSIO_SCL_inc_ratio 0x00FFFFFF
#define BA_SENSIO_SCL_crop_ctrl 0x0017
#define B16SENSIO_SCL_crop_ctrl 0x0016
#define LSb32SENSIO_SCL_crop_ctrl 24
#define LSb16SENSIO_SCL_crop_ctrl 8
#define bSENSIO_SCL_crop_ctrl 3
#define MSK32SENSIO_SCL_crop_ctrl 0x07000000
#define BA_SENSIO_LB_dummy_data 0x0018
#define B16SENSIO_LB_dummy_data 0x0018
#define LSb32SENSIO_LB_dummy_data 0
#define LSb16SENSIO_LB_dummy_data 0
#define bSENSIO_LB_dummy_data 8
#define MSK32SENSIO_LB_dummy_data 0x000000FF
#define BA_SENSIO_SCL_prog_delay 0x0019
#define B16SENSIO_SCL_prog_delay 0x0018
#define LSb32SENSIO_SCL_prog_delay 8
#define LSb16SENSIO_SCL_prog_delay 8
#define bSENSIO_SCL_prog_delay 8
#define MSK32SENSIO_SCL_prog_delay 0x0000FF00
#define BA_SENSIO_SCL_VDE_Dly 0x001A
#define B16SENSIO_SCL_VDE_Dly 0x001A
#define LSb32SENSIO_SCL_VDE_Dly 16
#define LSb16SENSIO_SCL_VDE_Dly 0
#define bSENSIO_SCL_VDE_Dly 8
#define MSK32SENSIO_SCL_VDE_Dly 0x00FF0000
#define BA_SENSIO_SCL_VDE_Sel 0x001B
#define B16SENSIO_SCL_VDE_Sel 0x001A
#define LSb32SENSIO_SCL_VDE_Sel 24
#define LSb16SENSIO_SCL_VDE_Sel 8
#define bSENSIO_SCL_VDE_Sel 1
#define MSK32SENSIO_SCL_VDE_Sel 0x01000000
///////////////////////////////////////////////////////////
typedef struct SIE_SENSIO {
///////////////////////////////////////////////////////////
#define GET32SENSIO_Process_Enable(r32) _BFGET_(r32, 0, 0)
#define SET32SENSIO_Process_Enable(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16SENSIO_Process_Enable(r16) _BFGET_(r16, 0, 0)
#define SET16SENSIO_Process_Enable(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32SENSIO_LR_frame(r32) _BFGET_(r32, 1, 1)
#define SET32SENSIO_LR_frame(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16SENSIO_LR_frame(r16) _BFGET_(r16, 1, 1)
#define SET16SENSIO_LR_frame(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32SENSIO_SCL_bypass(r32) _BFGET_(r32, 2, 2)
#define SET32SENSIO_SCL_bypass(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16SENSIO_SCL_bypass(r16) _BFGET_(r16, 2, 2)
#define SET16SENSIO_SCL_bypass(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32SENSIO_SCL_ups_en(r32) _BFGET_(r32, 3, 3)
#define SET32SENSIO_SCL_ups_en(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16SENSIO_SCL_ups_en(r16) _BFGET_(r16, 3, 3)
#define SET16SENSIO_SCL_ups_en(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32SENSIO_SCL_dns_en(r32) _BFGET_(r32, 4, 4)
#define SET32SENSIO_SCL_dns_en(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16SENSIO_SCL_dns_en(r16) _BFGET_(r16, 4, 4)
#define SET16SENSIO_SCL_dns_en(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32SENSIO_SCL_ihres(r32) _BFGET_(r32,16, 5)
#define SET32SENSIO_SCL_ihres(r32,v) _BFSET_(r32,16, 5,v)
#define GET32SENSIO_SCL_ohres(r32) _BFGET_(r32,28,17)
#define SET32SENSIO_SCL_ohres(r32,v) _BFSET_(r32,28,17,v)
#define GET16SENSIO_SCL_ohres(r16) _BFGET_(r16,12, 1)
#define SET16SENSIO_SCL_ohres(r16,v) _BFSET_(r16,12, 1,v)
#define GET32SENSIO_SCL_black(r32) _BFGET_(r32,29,29)
#define SET32SENSIO_SCL_black(r32,v) _BFSET_(r32,29,29,v)
#define GET16SENSIO_SCL_black(r16) _BFGET_(r16,13,13)
#define SET16SENSIO_SCL_black(r16,v) _BFSET_(r16,13,13,v)
UNSG32 u_Process_Enable : 1;
UNSG32 u_LR_frame : 1;
UNSG32 u_SCL_bypass : 1;
UNSG32 u_SCL_ups_en : 1;
UNSG32 u_SCL_dns_en : 1;
UNSG32 u_SCL_ihres : 12;
UNSG32 u_SCL_ohres : 12;
UNSG32 u_SCL_black : 1;
UNSG32 RSVDx0_b30 : 2;
///////////////////////////////////////////////////////////
#define GET32SENSIO_SCL_sign_frac(r32) _BFGET_(r32, 4, 0)
#define SET32SENSIO_SCL_sign_frac(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16SENSIO_SCL_sign_frac(r16) _BFGET_(r16, 4, 0)
#define SET16SENSIO_SCL_sign_frac(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32SENSIO_SCL_hratio(r32) _BFGET_(r32,28, 5)
#define SET32SENSIO_SCL_hratio(r32,v) _BFSET_(r32,28, 5,v)
UNSG32 u_SCL_sign_frac : 5;
UNSG32 u_SCL_hratio : 24;
UNSG32 RSVDx4_b29 : 3;
///////////////////////////////////////////////////////////
#define GET32SENSIO_SCL_hinitph(r32) _BFGET_(r32,19, 0)
#define SET32SENSIO_SCL_hinitph(r32,v) _BFSET_(r32,19, 0,v)
#define GET32SENSIO_SCL_init_centertap(r32) _BFGET_(r32,24,20)
#define SET32SENSIO_SCL_init_centertap(r32,v) _BFSET_(r32,24,20,v)
#define GET16SENSIO_SCL_init_centertap(r16) _BFGET_(r16, 8, 4)
#define SET16SENSIO_SCL_init_centertap(r16,v) _BFSET_(r16, 8, 4,v)
#define GET32SENSIO_SCL_hnl_en(r32) _BFGET_(r32,25,25)
#define SET32SENSIO_SCL_hnl_en(r32,v) _BFSET_(r32,25,25,v)
#define GET16SENSIO_SCL_hnl_en(r16) _BFGET_(r16, 9, 9)
#define SET16SENSIO_SCL_hnl_en(r16,v) _BFSET_(r16, 9, 9,v)
UNSG32 u_SCL_hinitph : 20;
UNSG32 u_SCL_init_centertap : 5;
UNSG32 u_SCL_hnl_en : 1;
UNSG32 RSVDx8_b26 : 6;
///////////////////////////////////////////////////////////
#define GET32SENSIO_SCL_nlxres(r32) _BFGET_(r32,11, 0)
#define SET32SENSIO_SCL_nlxres(r32,v) _BFSET_(r32,11, 0,v)
#define GET16SENSIO_SCL_nlxres(r16) _BFGET_(r16,11, 0)
#define SET16SENSIO_SCL_nlxres(r16,v) _BFSET_(r16,11, 0,v)
#define GET32SENSIO_SCL_cxres(r32) _BFGET_(r32,23,12)
#define SET32SENSIO_SCL_cxres(r32,v) _BFSET_(r32,23,12,v)
UNSG32 u_SCL_nlxres : 12;
UNSG32 u_SCL_cxres : 12;
UNSG32 RSVDxC_b24 : 8;
///////////////////////////////////////////////////////////
#define GET32SENSIO_SCL_init_ratio(r32) _BFGET_(r32,23, 0)
#define SET32SENSIO_SCL_init_ratio(r32,v) _BFSET_(r32,23, 0,v)
UNSG32 u_SCL_init_ratio : 24;
UNSG32 RSVDx10_b24 : 8;
///////////////////////////////////////////////////////////
#define GET32SENSIO_SCL_inc_ratio(r32) _BFGET_(r32,23, 0)
#define SET32SENSIO_SCL_inc_ratio(r32,v) _BFSET_(r32,23, 0,v)
#define GET32SENSIO_SCL_crop_ctrl(r32) _BFGET_(r32,26,24)
#define SET32SENSIO_SCL_crop_ctrl(r32,v) _BFSET_(r32,26,24,v)
#define GET16SENSIO_SCL_crop_ctrl(r16) _BFGET_(r16,10, 8)
#define SET16SENSIO_SCL_crop_ctrl(r16,v) _BFSET_(r16,10, 8,v)
UNSG32 u_SCL_inc_ratio : 24;
UNSG32 u_SCL_crop_ctrl : 3;
UNSG32 RSVDx14_b27 : 5;
///////////////////////////////////////////////////////////
#define GET32SENSIO_LB_dummy_data(r32) _BFGET_(r32, 7, 0)
#define SET32SENSIO_LB_dummy_data(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16SENSIO_LB_dummy_data(r16) _BFGET_(r16, 7, 0)
#define SET16SENSIO_LB_dummy_data(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32SENSIO_SCL_prog_delay(r32) _BFGET_(r32,15, 8)
#define SET32SENSIO_SCL_prog_delay(r32,v) _BFSET_(r32,15, 8,v)
#define GET16SENSIO_SCL_prog_delay(r16) _BFGET_(r16,15, 8)
#define SET16SENSIO_SCL_prog_delay(r16,v) _BFSET_(r16,15, 8,v)
#define GET32SENSIO_SCL_VDE_Dly(r32) _BFGET_(r32,23,16)
#define SET32SENSIO_SCL_VDE_Dly(r32,v) _BFSET_(r32,23,16,v)
#define GET16SENSIO_SCL_VDE_Dly(r16) _BFGET_(r16, 7, 0)
#define SET16SENSIO_SCL_VDE_Dly(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32SENSIO_SCL_VDE_Sel(r32) _BFGET_(r32,24,24)
#define SET32SENSIO_SCL_VDE_Sel(r32,v) _BFSET_(r32,24,24,v)
#define GET16SENSIO_SCL_VDE_Sel(r16) _BFGET_(r16, 8, 8)
#define SET16SENSIO_SCL_VDE_Sel(r16,v) _BFSET_(r16, 8, 8,v)
UNSG32 u_LB_dummy_data : 8;
UNSG32 u_SCL_prog_delay : 8;
UNSG32 u_SCL_VDE_Dly : 8;
UNSG32 u_SCL_VDE_Sel : 1;
UNSG32 RSVDx18_b25 : 7;
///////////////////////////////////////////////////////////
} SIE_SENSIO;
///////////////////////////////////////////////////////////
SIGN32 SENSIO_drvrd(SIE_SENSIO *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 SENSIO_drvwr(SIE_SENSIO *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void SENSIO_reset(SIE_SENSIO *p);
SIGN32 SENSIO_cmp (SIE_SENSIO *p, SIE_SENSIO *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define SENSIO_check(p,pie,pfx,hLOG) SENSIO_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define SENSIO_print(p, pfx,hLOG) SENSIO_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: SENSIO
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE BG biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 20B, bits: 71b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_BG
#define h_BG (){}
#define RA_BG_PLANE 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_BG {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
} SIE_BG;
///////////////////////////////////////////////////////////
SIGN32 BG_drvrd(SIE_BG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 BG_drvwr(SIE_BG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void BG_reset(SIE_BG *p);
SIGN32 BG_cmp (SIE_BG *p, SIE_BG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define BG_check(p,pie,pfx,hLOG) BG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define BG_print(p, pfx,hLOG) BG_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: BG
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE MAIN biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 20B, bits: 71b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_MAIN
#define h_MAIN (){}
#define RA_MAIN_PLANE 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_MAIN {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
} SIE_MAIN;
///////////////////////////////////////////////////////////
SIGN32 MAIN_drvrd(SIE_MAIN *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 MAIN_drvwr(SIE_MAIN *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void MAIN_reset(SIE_MAIN *p);
SIGN32 MAIN_cmp (SIE_MAIN *p, SIE_MAIN *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define MAIN_check(p,pie,pfx,hLOG) MAIN_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define MAIN_print(p, pfx,hLOG) MAIN_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: MAIN
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE PIP biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 20B, bits: 71b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_PIP
#define h_PIP (){}
#define RA_PIP_PLANE 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_PIP {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
} SIE_PIP;
///////////////////////////////////////////////////////////
SIGN32 PIP_drvrd(SIE_PIP *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 PIP_drvwr(SIE_PIP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void PIP_reset(SIE_PIP *p);
SIGN32 PIP_cmp (SIE_PIP *p, SIE_PIP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define PIP_check(p,pie,pfx,hLOG) PIP_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define PIP_print(p, pfx,hLOG) PIP_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: PIP
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE PG biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// @ 0x00014 (W-)
/// # # Stuffing bytes...
/// %% 8032
/// @ 0x00400 (P)
/// # 0x00400 LUT
/// $CLUT LUT MEM
/// ###
/// * LUT for color index look-up.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 2048B, bits: 103b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_PG
#define h_PG (){}
#define RA_PG_PLANE 0x0000
///////////////////////////////////////////////////////////
#define RA_PG_LUT 0x0400
///////////////////////////////////////////////////////////
typedef struct SIE_PG {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
UNSG8 RSVDx14 [1004];
///////////////////////////////////////////////////////////
SIE_CLUT ie_LUT;
///////////////////////////////////////////////////////////
} SIE_PG;
///////////////////////////////////////////////////////////
SIGN32 PG_drvrd(SIE_PG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 PG_drvwr(SIE_PG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void PG_reset(SIE_PG *p);
SIGN32 PG_cmp (SIE_PG *p, SIE_PG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define PG_check(p,pie,pfx,hLOG) PG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define PG_print(p, pfx,hLOG) PG_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: PG
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE IG biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// @ 0x00014 (W-)
/// # # Stuffing bytes...
/// %% 8032
/// @ 0x00400 (P)
/// # 0x00400 LUT
/// $CLUT LUT MEM
/// ###
/// * LUT for color index look-up.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 2048B, bits: 103b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_IG
#define h_IG (){}
#define RA_IG_PLANE 0x0000
///////////////////////////////////////////////////////////
#define RA_IG_LUT 0x0400
///////////////////////////////////////////////////////////
typedef struct SIE_IG {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
UNSG8 RSVDx14 [1004];
///////////////////////////////////////////////////////////
SIE_CLUT ie_LUT;
///////////////////////////////////////////////////////////
} SIE_IG;
///////////////////////////////////////////////////////////
SIGN32 IG_drvrd(SIE_IG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 IG_drvwr(SIE_IG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void IG_reset(SIE_IG *p);
SIGN32 IG_cmp (SIE_IG *p, SIE_IG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define IG_check(p,pie,pfx,hLOG) IG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define IG_print(p, pfx,hLOG) IG_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: IG
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CURSOR biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// @ 0x00014 (W-)
/// # # Stuffing bytes...
/// %% 8032
/// @ 0x00400 (P)
/// # 0x00400 LUT
/// $CLUT LUT MEM
/// ###
/// * LUT for color index look-up.
/// ###
/// @ 0x00800 (P)
/// # 0x00800 CSC
/// $CSC CSC REG
/// ###
/// * Color-space converter coefficients.
/// ###
/// @ 0x00830 (W-)
/// # # Stuffing bytes...
/// %% 7808
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 3072B, bits: 277b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CURSOR
#define h_CURSOR (){}
#define RA_CURSOR_PLANE 0x0000
///////////////////////////////////////////////////////////
#define RA_CURSOR_LUT 0x0400
///////////////////////////////////////////////////////////
#define RA_CURSOR_CSC 0x0800
///////////////////////////////////////////////////////////
typedef struct SIE_CURSOR {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
UNSG8 RSVDx14 [1004];
///////////////////////////////////////////////////////////
SIE_CLUT ie_LUT;
///////////////////////////////////////////////////////////
SIE_CSC ie_CSC;
///////////////////////////////////////////////////////////
UNSG8 RSVDx830 [976];
///////////////////////////////////////////////////////////
} SIE_CURSOR;
///////////////////////////////////////////////////////////
SIGN32 CURSOR_drvrd(SIE_CURSOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CURSOR_drvwr(SIE_CURSOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CURSOR_reset(SIE_CURSOR *p);
SIGN32 CURSOR_cmp (SIE_CURSOR *p, SIE_CURSOR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CURSOR_check(p,pie,pfx,hLOG) CURSOR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CURSOR_print(p, pfx,hLOG) CURSOR_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CURSOR
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE MOSD biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 PLANE
/// $PLANE PLANE REG
/// ###
/// * Plane related registers.
/// ###
/// @ 0x00014 (W-)
/// # # Stuffing bytes...
/// %% 8032
/// @ 0x00400 (P)
/// # 0x00400 LUT
/// $CLUT LUT MEM
/// ###
/// * LUT for color index look-up.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 2048B, bits: 103b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_MOSD
#define h_MOSD (){}
#define RA_MOSD_PLANE 0x0000
///////////////////////////////////////////////////////////
#define RA_MOSD_LUT 0x0400
///////////////////////////////////////////////////////////
typedef struct SIE_MOSD {
///////////////////////////////////////////////////////////
SIE_PLANE ie_PLANE;
///////////////////////////////////////////////////////////
UNSG8 RSVDx14 [1004];
///////////////////////////////////////////////////////////
SIE_CLUT ie_LUT;
///////////////////////////////////////////////////////////
} SIE_MOSD;
///////////////////////////////////////////////////////////
SIGN32 MOSD_drvrd(SIE_MOSD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 MOSD_drvwr(SIE_MOSD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void MOSD_reset(SIE_MOSD *p);
SIGN32 MOSD_cmp (SIE_MOSD *p, SIE_MOSD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define MOSD_check(p,pie,pfx,hLOG) MOSD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define MOSD_print(p, pfx,hLOG) MOSD_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: MOSD
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE LDR biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 BG
/// $BG BG REG
/// ###
/// * BG channel loader related registers
/// ###
/// @ 0x00014 (P)
/// # 0x00014 MAIN
/// $MAIN MAIN REG
/// ###
/// * Main channel loader related registers
/// ###
/// @ 0x00028 (P)
/// # 0x00028 PIP
/// $PIP PIP REG
/// ###
/// * PIP channel loader related registers
/// ###
/// @ 0x0003C (W-)
/// # # Stuffing bytes...
/// %% 7712
/// @ 0x00400 (P)
/// # 0x00400 PG
/// $PG PG REG
/// ###
/// * PG channel loader related registers
/// ###
/// @ 0x00C00 (P)
/// # 0x00C00 IG
/// $IG IG REG
/// ###
/// * IG channel loader related registers
/// ###
/// @ 0x01400 (P)
/// # 0x01400 CURSOR
/// $CURSOR CURSOR REG
/// ###
/// * Cursor channel loader related registers
/// ###
/// @ 0x02000 (P)
/// # 0x02000 MOSD
/// $MOSD MOSD REG
/// ###
/// * MOSD channel loader related registers
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 10240B, bits: 799b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_LDR
#define h_LDR (){}
#define RA_LDR_BG 0x0000
///////////////////////////////////////////////////////////
#define RA_LDR_MAIN 0x0014
///////////////////////////////////////////////////////////
#define RA_LDR_PIP 0x0028
///////////////////////////////////////////////////////////
#define RA_LDR_PG 0x0400
///////////////////////////////////////////////////////////
#define RA_LDR_IG 0x0C00
///////////////////////////////////////////////////////////
#define RA_LDR_CURSOR 0x1400
///////////////////////////////////////////////////////////
#define RA_LDR_MOSD 0x2000
///////////////////////////////////////////////////////////
typedef struct SIE_LDR {
///////////////////////////////////////////////////////////
SIE_BG ie_BG;
///////////////////////////////////////////////////////////
SIE_MAIN ie_MAIN;
///////////////////////////////////////////////////////////
SIE_PIP ie_PIP;
///////////////////////////////////////////////////////////
UNSG8 RSVDx3C [964];
///////////////////////////////////////////////////////////
SIE_PG ie_PG;
///////////////////////////////////////////////////////////
SIE_IG ie_IG;
///////////////////////////////////////////////////////////
SIE_CURSOR ie_CURSOR;
///////////////////////////////////////////////////////////
SIE_MOSD ie_MOSD;
///////////////////////////////////////////////////////////
} SIE_LDR;
///////////////////////////////////////////////////////////
SIGN32 LDR_drvrd(SIE_LDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 LDR_drvwr(SIE_LDR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void LDR_reset(SIE_LDR *p);
SIGN32 LDR_cmp (SIE_LDR *p, SIE_LDR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define LDR_check(p,pie,pfx,hLOG) LDR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define LDR_print(p, pfx,hLOG) LDR_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: LDR
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CLKGAT_CTRL (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (P)
/// %unsigned 1 main_det_sclEnb 0x1
/// %unsigned 1 pip_sclEnb 0x1
/// %unsigned 1 ig_sclEnb 0x1
/// %unsigned 1 pg_sclEnb 0x1
/// %unsigned 1 mosd_sclEnb 0x1
/// %unsigned 1 aux_sclEnb 0x1
/// %unsigned 1 asd_vopEnb 0x1
/// %unsigned 1 ahd_vopEnb 0x1
/// %unsigned 1 hdmi_vopEnb 0x1
/// %unsigned 1 lvds_vopEnb 0x1
/// %unsigned 1 ttl24_vopEnb 0x1
/// %unsigned 1 ttl30_vopEnb 0x1
/// %unsigned 1 cmuTop_Enb 0x1
/// %unsigned 1 videoEnc_Enb 0x1
/// %unsigned 1 hdmiTx_Enb 0x1
/// %unsigned 1 vpTop_Enb 0x1
/// ###
/// * Clock gating enables for different blocks. Default, clock gating is disabled. Write 0 to gate the clock.
/// ###
/// %% 16 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 16b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CLKGAT_CTRL
#define h_CLKGAT_CTRL (){}
#define RA_CLKGAT_CTRL_CTRL 0x0000
#define BA_CLKGAT_CTRL_CTRL_main_det_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_main_det_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_main_det_sclEnb 0
#define LSb16CLKGAT_CTRL_CTRL_main_det_sclEnb 0
#define bCLKGAT_CTRL_CTRL_main_det_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_main_det_sclEnb 0x00000001
#define BA_CLKGAT_CTRL_CTRL_pip_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_pip_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_pip_sclEnb 1
#define LSb16CLKGAT_CTRL_CTRL_pip_sclEnb 1
#define bCLKGAT_CTRL_CTRL_pip_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_pip_sclEnb 0x00000002
#define BA_CLKGAT_CTRL_CTRL_ig_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_ig_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_ig_sclEnb 2
#define LSb16CLKGAT_CTRL_CTRL_ig_sclEnb 2
#define bCLKGAT_CTRL_CTRL_ig_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_ig_sclEnb 0x00000004
#define BA_CLKGAT_CTRL_CTRL_pg_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_pg_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_pg_sclEnb 3
#define LSb16CLKGAT_CTRL_CTRL_pg_sclEnb 3
#define bCLKGAT_CTRL_CTRL_pg_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_pg_sclEnb 0x00000008
#define BA_CLKGAT_CTRL_CTRL_mosd_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_mosd_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_mosd_sclEnb 4
#define LSb16CLKGAT_CTRL_CTRL_mosd_sclEnb 4
#define bCLKGAT_CTRL_CTRL_mosd_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_mosd_sclEnb 0x00000010
#define BA_CLKGAT_CTRL_CTRL_aux_sclEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_aux_sclEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_aux_sclEnb 5
#define LSb16CLKGAT_CTRL_CTRL_aux_sclEnb 5
#define bCLKGAT_CTRL_CTRL_aux_sclEnb 1
#define MSK32CLKGAT_CTRL_CTRL_aux_sclEnb 0x00000020
#define BA_CLKGAT_CTRL_CTRL_asd_vopEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_asd_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_asd_vopEnb 6
#define LSb16CLKGAT_CTRL_CTRL_asd_vopEnb 6
#define bCLKGAT_CTRL_CTRL_asd_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_asd_vopEnb 0x00000040
#define BA_CLKGAT_CTRL_CTRL_ahd_vopEnb 0x0000
#define B16CLKGAT_CTRL_CTRL_ahd_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_ahd_vopEnb 7
#define LSb16CLKGAT_CTRL_CTRL_ahd_vopEnb 7
#define bCLKGAT_CTRL_CTRL_ahd_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_ahd_vopEnb 0x00000080
#define BA_CLKGAT_CTRL_CTRL_hdmi_vopEnb 0x0001
#define B16CLKGAT_CTRL_CTRL_hdmi_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_hdmi_vopEnb 8
#define LSb16CLKGAT_CTRL_CTRL_hdmi_vopEnb 8
#define bCLKGAT_CTRL_CTRL_hdmi_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_hdmi_vopEnb 0x00000100
#define BA_CLKGAT_CTRL_CTRL_lvds_vopEnb 0x0001
#define B16CLKGAT_CTRL_CTRL_lvds_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_lvds_vopEnb 9
#define LSb16CLKGAT_CTRL_CTRL_lvds_vopEnb 9
#define bCLKGAT_CTRL_CTRL_lvds_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_lvds_vopEnb 0x00000200
#define BA_CLKGAT_CTRL_CTRL_ttl24_vopEnb 0x0001
#define B16CLKGAT_CTRL_CTRL_ttl24_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_ttl24_vopEnb 10
#define LSb16CLKGAT_CTRL_CTRL_ttl24_vopEnb 10
#define bCLKGAT_CTRL_CTRL_ttl24_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_ttl24_vopEnb 0x00000400
#define BA_CLKGAT_CTRL_CTRL_ttl30_vopEnb 0x0001
#define B16CLKGAT_CTRL_CTRL_ttl30_vopEnb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_ttl30_vopEnb 11
#define LSb16CLKGAT_CTRL_CTRL_ttl30_vopEnb 11
#define bCLKGAT_CTRL_CTRL_ttl30_vopEnb 1
#define MSK32CLKGAT_CTRL_CTRL_ttl30_vopEnb 0x00000800
#define BA_CLKGAT_CTRL_CTRL_cmuTop_Enb 0x0001
#define B16CLKGAT_CTRL_CTRL_cmuTop_Enb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_cmuTop_Enb 12
#define LSb16CLKGAT_CTRL_CTRL_cmuTop_Enb 12
#define bCLKGAT_CTRL_CTRL_cmuTop_Enb 1
#define MSK32CLKGAT_CTRL_CTRL_cmuTop_Enb 0x00001000
#define BA_CLKGAT_CTRL_CTRL_videoEnc_Enb 0x0001
#define B16CLKGAT_CTRL_CTRL_videoEnc_Enb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_videoEnc_Enb 13
#define LSb16CLKGAT_CTRL_CTRL_videoEnc_Enb 13
#define bCLKGAT_CTRL_CTRL_videoEnc_Enb 1
#define MSK32CLKGAT_CTRL_CTRL_videoEnc_Enb 0x00002000
#define BA_CLKGAT_CTRL_CTRL_hdmiTx_Enb 0x0001
#define B16CLKGAT_CTRL_CTRL_hdmiTx_Enb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_hdmiTx_Enb 14
#define LSb16CLKGAT_CTRL_CTRL_hdmiTx_Enb 14
#define bCLKGAT_CTRL_CTRL_hdmiTx_Enb 1
#define MSK32CLKGAT_CTRL_CTRL_hdmiTx_Enb 0x00004000
#define BA_CLKGAT_CTRL_CTRL_vpTop_Enb 0x0001
#define B16CLKGAT_CTRL_CTRL_vpTop_Enb 0x0000
#define LSb32CLKGAT_CTRL_CTRL_vpTop_Enb 15
#define LSb16CLKGAT_CTRL_CTRL_vpTop_Enb 15
#define bCLKGAT_CTRL_CTRL_vpTop_Enb 1
#define MSK32CLKGAT_CTRL_CTRL_vpTop_Enb 0x00008000
///////////////////////////////////////////////////////////
typedef struct SIE_CLKGAT_CTRL {
///////////////////////////////////////////////////////////
#define GET32CLKGAT_CTRL_CTRL_main_det_sclEnb(r32) _BFGET_(r32, 0, 0)
#define SET32CLKGAT_CTRL_CTRL_main_det_sclEnb(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CLKGAT_CTRL_CTRL_main_det_sclEnb(r16) _BFGET_(r16, 0, 0)
#define SET16CLKGAT_CTRL_CTRL_main_det_sclEnb(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CLKGAT_CTRL_CTRL_pip_sclEnb(r32) _BFGET_(r32, 1, 1)
#define SET32CLKGAT_CTRL_CTRL_pip_sclEnb(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CLKGAT_CTRL_CTRL_pip_sclEnb(r16) _BFGET_(r16, 1, 1)
#define SET16CLKGAT_CTRL_CTRL_pip_sclEnb(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CLKGAT_CTRL_CTRL_ig_sclEnb(r32) _BFGET_(r32, 2, 2)
#define SET32CLKGAT_CTRL_CTRL_ig_sclEnb(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CLKGAT_CTRL_CTRL_ig_sclEnb(r16) _BFGET_(r16, 2, 2)
#define SET16CLKGAT_CTRL_CTRL_ig_sclEnb(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CLKGAT_CTRL_CTRL_pg_sclEnb(r32) _BFGET_(r32, 3, 3)
#define SET32CLKGAT_CTRL_CTRL_pg_sclEnb(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CLKGAT_CTRL_CTRL_pg_sclEnb(r16) _BFGET_(r16, 3, 3)
#define SET16CLKGAT_CTRL_CTRL_pg_sclEnb(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CLKGAT_CTRL_CTRL_mosd_sclEnb(r32) _BFGET_(r32, 4, 4)
#define SET32CLKGAT_CTRL_CTRL_mosd_sclEnb(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CLKGAT_CTRL_CTRL_mosd_sclEnb(r16) _BFGET_(r16, 4, 4)
#define SET16CLKGAT_CTRL_CTRL_mosd_sclEnb(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CLKGAT_CTRL_CTRL_aux_sclEnb(r32) _BFGET_(r32, 5, 5)
#define SET32CLKGAT_CTRL_CTRL_aux_sclEnb(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16CLKGAT_CTRL_CTRL_aux_sclEnb(r16) _BFGET_(r16, 5, 5)
#define SET16CLKGAT_CTRL_CTRL_aux_sclEnb(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32CLKGAT_CTRL_CTRL_asd_vopEnb(r32) _BFGET_(r32, 6, 6)
#define SET32CLKGAT_CTRL_CTRL_asd_vopEnb(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16CLKGAT_CTRL_CTRL_asd_vopEnb(r16) _BFGET_(r16, 6, 6)
#define SET16CLKGAT_CTRL_CTRL_asd_vopEnb(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32CLKGAT_CTRL_CTRL_ahd_vopEnb(r32) _BFGET_(r32, 7, 7)
#define SET32CLKGAT_CTRL_CTRL_ahd_vopEnb(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16CLKGAT_CTRL_CTRL_ahd_vopEnb(r16) _BFGET_(r16, 7, 7)
#define SET16CLKGAT_CTRL_CTRL_ahd_vopEnb(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32CLKGAT_CTRL_CTRL_hdmi_vopEnb(r32) _BFGET_(r32, 8, 8)
#define SET32CLKGAT_CTRL_CTRL_hdmi_vopEnb(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16CLKGAT_CTRL_CTRL_hdmi_vopEnb(r16) _BFGET_(r16, 8, 8)
#define SET16CLKGAT_CTRL_CTRL_hdmi_vopEnb(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32CLKGAT_CTRL_CTRL_lvds_vopEnb(r32) _BFGET_(r32, 9, 9)
#define SET32CLKGAT_CTRL_CTRL_lvds_vopEnb(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16CLKGAT_CTRL_CTRL_lvds_vopEnb(r16) _BFGET_(r16, 9, 9)
#define SET16CLKGAT_CTRL_CTRL_lvds_vopEnb(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32CLKGAT_CTRL_CTRL_ttl24_vopEnb(r32) _BFGET_(r32,10,10)
#define SET32CLKGAT_CTRL_CTRL_ttl24_vopEnb(r32,v) _BFSET_(r32,10,10,v)
#define GET16CLKGAT_CTRL_CTRL_ttl24_vopEnb(r16) _BFGET_(r16,10,10)
#define SET16CLKGAT_CTRL_CTRL_ttl24_vopEnb(r16,v) _BFSET_(r16,10,10,v)
#define GET32CLKGAT_CTRL_CTRL_ttl30_vopEnb(r32) _BFGET_(r32,11,11)
#define SET32CLKGAT_CTRL_CTRL_ttl30_vopEnb(r32,v) _BFSET_(r32,11,11,v)
#define GET16CLKGAT_CTRL_CTRL_ttl30_vopEnb(r16) _BFGET_(r16,11,11)
#define SET16CLKGAT_CTRL_CTRL_ttl30_vopEnb(r16,v) _BFSET_(r16,11,11,v)
#define GET32CLKGAT_CTRL_CTRL_cmuTop_Enb(r32) _BFGET_(r32,12,12)
#define SET32CLKGAT_CTRL_CTRL_cmuTop_Enb(r32,v) _BFSET_(r32,12,12,v)
#define GET16CLKGAT_CTRL_CTRL_cmuTop_Enb(r16) _BFGET_(r16,12,12)
#define SET16CLKGAT_CTRL_CTRL_cmuTop_Enb(r16,v) _BFSET_(r16,12,12,v)
#define GET32CLKGAT_CTRL_CTRL_videoEnc_Enb(r32) _BFGET_(r32,13,13)
#define SET32CLKGAT_CTRL_CTRL_videoEnc_Enb(r32,v) _BFSET_(r32,13,13,v)
#define GET16CLKGAT_CTRL_CTRL_videoEnc_Enb(r16) _BFGET_(r16,13,13)
#define SET16CLKGAT_CTRL_CTRL_videoEnc_Enb(r16,v) _BFSET_(r16,13,13,v)
#define GET32CLKGAT_CTRL_CTRL_hdmiTx_Enb(r32) _BFGET_(r32,14,14)
#define SET32CLKGAT_CTRL_CTRL_hdmiTx_Enb(r32,v) _BFSET_(r32,14,14,v)
#define GET16CLKGAT_CTRL_CTRL_hdmiTx_Enb(r16) _BFGET_(r16,14,14)
#define SET16CLKGAT_CTRL_CTRL_hdmiTx_Enb(r16,v) _BFSET_(r16,14,14,v)
#define GET32CLKGAT_CTRL_CTRL_vpTop_Enb(r32) _BFGET_(r32,15,15)
#define SET32CLKGAT_CTRL_CTRL_vpTop_Enb(r32,v) _BFSET_(r32,15,15,v)
#define GET16CLKGAT_CTRL_CTRL_vpTop_Enb(r16) _BFGET_(r16,15,15)
#define SET16CLKGAT_CTRL_CTRL_vpTop_Enb(r16,v) _BFSET_(r16,15,15,v)
#define w32CLKGAT_CTRL_CTRL {\
UNSG32 uCTRL_main_det_sclEnb : 1;\
UNSG32 uCTRL_pip_sclEnb : 1;\
UNSG32 uCTRL_ig_sclEnb : 1;\
UNSG32 uCTRL_pg_sclEnb : 1;\
UNSG32 uCTRL_mosd_sclEnb : 1;\
UNSG32 uCTRL_aux_sclEnb : 1;\
UNSG32 uCTRL_asd_vopEnb : 1;\
UNSG32 uCTRL_ahd_vopEnb : 1;\
UNSG32 uCTRL_hdmi_vopEnb : 1;\
UNSG32 uCTRL_lvds_vopEnb : 1;\
UNSG32 uCTRL_ttl24_vopEnb : 1;\
UNSG32 uCTRL_ttl30_vopEnb : 1;\
UNSG32 uCTRL_cmuTop_Enb : 1;\
UNSG32 uCTRL_videoEnc_Enb : 1;\
UNSG32 uCTRL_hdmiTx_Enb : 1;\
UNSG32 uCTRL_vpTop_Enb : 1;\
UNSG32 RSVDx0_b16 : 16;\
}
union { UNSG32 u32CLKGAT_CTRL_CTRL;
struct w32CLKGAT_CTRL_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_CLKGAT_CTRL;
typedef union T32CLKGAT_CTRL_CTRL
{ UNSG32 u32;
struct w32CLKGAT_CTRL_CTRL;
} T32CLKGAT_CTRL_CTRL;
///////////////////////////////////////////////////////////
typedef union TCLKGAT_CTRL_CTRL
{ UNSG32 u32[1];
struct {
struct w32CLKGAT_CTRL_CTRL;
};
} TCLKGAT_CTRL_CTRL;
///////////////////////////////////////////////////////////
SIGN32 CLKGAT_CTRL_drvrd(SIE_CLKGAT_CTRL *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CLKGAT_CTRL_drvwr(SIE_CLKGAT_CTRL *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CLKGAT_CTRL_reset(SIE_CLKGAT_CTRL *p);
SIGN32 CLKGAT_CTRL_cmp (SIE_CLKGAT_CTRL *p, SIE_CLKGAT_CTRL *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CLKGAT_CTRL_check(p,pie,pfx,hLOG) CLKGAT_CTRL_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CLKGAT_CTRL_print(p, pfx,hLOG) CLKGAT_CTRL_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CLKGAT_CTRL
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE TG biu (4,4)
/// ###
/// * Register specification of interface Timing Generator
/// * There are two counters in the timing generator module. hCntr (from 1 to SIZE_X) and vCntr (from 1 to SIZE_Y).
/// * When start, the initial value will be loaded to the xCnt and yCnt
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 INIT (P)
/// %unsigned 16 Y 0x1
/// ###
/// * Initial Y value which will be used to load Y counter when tg is enabled.
/// ###
/// %unsigned 16 X 0x1
/// ###
/// * Initial X value which will be used to load X counter when tg is enabled.
/// * A whole frame scan size.
/// ###
/// @ 0x00004 SIZE (P)
/// %unsigned 16 Y 0x465
/// ###
/// * Total scan lines per frame.
/// ###
/// %unsigned 16 X 0x898
/// ###
/// * Total scan clock cycles per line.
/// * Hsync
/// ###
/// @ 0x00008 HS (P)
/// %unsigned 16 FE 0x1
/// ###
/// * Hsync front edge. The first pixel position of hsync pulse.
/// ###
/// %unsigned 16 BE 0x2C
/// ###
/// * Hsync back edge. The last pixel position of hsync pulse.
/// * HS = hCntr>=FE & hCntr<=BE
/// * HBlanking
/// ###
/// @ 0x0000C HB (P)
/// %unsigned 16 FE 0x841
/// ###
/// * Hblank front edge. The first pixel position of the hBlank pulse. SIZEX-HFP = 2200-88+1
/// ###
/// %unsigned 16 BE 0xC0
/// ###
/// * Hblank back edge. The last pixel position of the hBlank pulse. HPW + HBP = 44+148
/// * HB = hCntr>=FE || hCntr<=BE.
/// * VS0 defines the first first pixel position of the first VSYNC (progressive or interlace mode) pulse.
/// * For example
/// * 1080i60, the VTP is the last pixel of the last line. So set both VLCNT0 and VPCNT0 to 0.
/// ###
/// @ 0x00010 VS0 (P)
/// %unsigned 16 FE 0x1
/// ###
/// * Vsync pulse front edge.
/// * Vsync will be asserted at the beginning of this line.
/// ###
/// %unsigned 16 BE 0x5
/// ###
/// * Vsync pulse back edge.
/// * Vsycn pulse will be de-asserted after the end of this line.
/// * Vsync = (vCntr>=FE & vCntr<=BE)
/// * Vsync pulse 1
/// * defines the first pixel position of the second vSync pulse. For example
/// * 1080i60, the VTP is pixel 1100 of line 563. So set both VLCNT2=563. and VPCNT2 to 1100.
/// ###
/// @ 0x00014 VS1 (P)
/// %unsigned 16 FE 0x233
/// ###
/// * Vsync pulse 1 front edge line position.
/// * Vsync pulse 1 will be asserted at the middle of this line.
/// ###
/// %unsigned 16 BE 0x238
/// ###
/// * Vsync pulse 1 back edge line position.
/// * Vsync pulse 1 will be de-asserted at the middle of this line.
/// * Vsync1 = (vCntr>=FE & hCntr>SIZEX/2) & (vCntr<=BE & hCntr<=SIZEX/2)
/// * Vertical blanking.
/// * VB0 parameter definietion
/// ###
/// @ 0x00018 VB0 (P)
/// %unsigned 16 FE 0x462
/// ###
/// * Vblank front edge line position
/// * The first line of the vertical blanking.
/// ###
/// %unsigned 16 BE 0x29
/// ###
/// * Vblank back edge line position
/// * the last line number of the vertical blanking
/// * The default value is used for 1080p case.
/// * Vblank0 = vCntr>=FE || vCntr<=BE
/// ###
/// @ 0x0001C VB1 (P)
/// %unsigned 16 FE 0x231
/// ###
/// * Vblank front edge line postion
/// * The first line number of VB1.
/// ###
/// %unsigned 16 BE 0x247
/// ###
/// * Vblank back edge line postion
/// * the last line numer of VB1.
/// * VB1 = (vCntr>=FE & vCntr<=BE)
/// * SCAN mode
/// ###
/// @ 0x00020 SCAN (P)
/// %unsigned 1 MODE 0x0
/// : PROG 0x0
/// : INTER 0x1
/// ###
/// * Frame done interrupt position
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00024 INTPOS (P)
/// %unsigned 16 FRAME 0x465
/// ###
/// * Frame interrupt status will be set at the end of this line.
/// * Program 0 to this register will disable frame interrupt.
/// ###
/// %unsigned 16 FIELD 0x233
/// ###
/// * Field interrupt status will be set at the end of this line.
/// * Program 0 to this register will disable field interrupt.
/// * MODE
/// ###
/// @ 0x00028 MODE (P)
/// %unsigned 1 EN 0x0
/// : MASTER 0x0
/// : SLAVE 0x1
/// ###
/// * In master mode, TG drive the control signal.
/// * In slave mode, TG take the external hsync and vsync, it generate the internal sync and blank signal based on the programmed register and external hsync and vsync.
/// * HREF input for slave mode.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0002C HVREF (P)
/// %unsigned 1 SEL 0x0
/// : SYNC 0x0
/// : BLANK 0x1
/// ###
/// * In slave mode, tg will sync to the external tg generated HREF/VREF which could be HSYBC/VSYNC or HBLANK/VBLANK. Currently only HSYNC/VSYNC is supported.
/// * HSYNC and VSYNC have to be come in pair.
/// ###
/// %unsigned 1 POL 0x0
/// : NEG_PULSE 0x0
/// : POS_PULSE 0x1
/// ###
/// * 0 : indicate the input HREF/VREF are negative pulses
/// * 1: indicate the input HREF/VREFare positive pulses.
/// * HREF and VREF have to be the same polarity.
/// * End of TG register group
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 48B, bits: 292b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_TG
#define h_TG (){}
#define RA_TG_INIT 0x0000
#define BA_TG_INIT_Y 0x0000
#define B16TG_INIT_Y 0x0000
#define LSb32TG_INIT_Y 0
#define LSb16TG_INIT_Y 0
#define bTG_INIT_Y 16
#define MSK32TG_INIT_Y 0x0000FFFF
#define BA_TG_INIT_X 0x0002
#define B16TG_INIT_X 0x0002
#define LSb32TG_INIT_X 16
#define LSb16TG_INIT_X 0
#define bTG_INIT_X 16
#define MSK32TG_INIT_X 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_SIZE 0x0004
#define BA_TG_SIZE_Y 0x0004
#define B16TG_SIZE_Y 0x0004
#define LSb32TG_SIZE_Y 0
#define LSb16TG_SIZE_Y 0
#define bTG_SIZE_Y 16
#define MSK32TG_SIZE_Y 0x0000FFFF
#define BA_TG_SIZE_X 0x0006
#define B16TG_SIZE_X 0x0006
#define LSb32TG_SIZE_X 16
#define LSb16TG_SIZE_X 0
#define bTG_SIZE_X 16
#define MSK32TG_SIZE_X 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_HS 0x0008
#define BA_TG_HS_FE 0x0008
#define B16TG_HS_FE 0x0008
#define LSb32TG_HS_FE 0
#define LSb16TG_HS_FE 0
#define bTG_HS_FE 16
#define MSK32TG_HS_FE 0x0000FFFF
#define BA_TG_HS_BE 0x000A
#define B16TG_HS_BE 0x000A
#define LSb32TG_HS_BE 16
#define LSb16TG_HS_BE 0
#define bTG_HS_BE 16
#define MSK32TG_HS_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_HB 0x000C
#define BA_TG_HB_FE 0x000C
#define B16TG_HB_FE 0x000C
#define LSb32TG_HB_FE 0
#define LSb16TG_HB_FE 0
#define bTG_HB_FE 16
#define MSK32TG_HB_FE 0x0000FFFF
#define BA_TG_HB_BE 0x000E
#define B16TG_HB_BE 0x000E
#define LSb32TG_HB_BE 16
#define LSb16TG_HB_BE 0
#define bTG_HB_BE 16
#define MSK32TG_HB_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_VS0 0x0010
#define BA_TG_VS0_FE 0x0010
#define B16TG_VS0_FE 0x0010
#define LSb32TG_VS0_FE 0
#define LSb16TG_VS0_FE 0
#define bTG_VS0_FE 16
#define MSK32TG_VS0_FE 0x0000FFFF
#define BA_TG_VS0_BE 0x0012
#define B16TG_VS0_BE 0x0012
#define LSb32TG_VS0_BE 16
#define LSb16TG_VS0_BE 0
#define bTG_VS0_BE 16
#define MSK32TG_VS0_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_VS1 0x0014
#define BA_TG_VS1_FE 0x0014
#define B16TG_VS1_FE 0x0014
#define LSb32TG_VS1_FE 0
#define LSb16TG_VS1_FE 0
#define bTG_VS1_FE 16
#define MSK32TG_VS1_FE 0x0000FFFF
#define BA_TG_VS1_BE 0x0016
#define B16TG_VS1_BE 0x0016
#define LSb32TG_VS1_BE 16
#define LSb16TG_VS1_BE 0
#define bTG_VS1_BE 16
#define MSK32TG_VS1_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_VB0 0x0018
#define BA_TG_VB0_FE 0x0018
#define B16TG_VB0_FE 0x0018
#define LSb32TG_VB0_FE 0
#define LSb16TG_VB0_FE 0
#define bTG_VB0_FE 16
#define MSK32TG_VB0_FE 0x0000FFFF
#define BA_TG_VB0_BE 0x001A
#define B16TG_VB0_BE 0x001A
#define LSb32TG_VB0_BE 16
#define LSb16TG_VB0_BE 0
#define bTG_VB0_BE 16
#define MSK32TG_VB0_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_VB1 0x001C
#define BA_TG_VB1_FE 0x001C
#define B16TG_VB1_FE 0x001C
#define LSb32TG_VB1_FE 0
#define LSb16TG_VB1_FE 0
#define bTG_VB1_FE 16
#define MSK32TG_VB1_FE 0x0000FFFF
#define BA_TG_VB1_BE 0x001E
#define B16TG_VB1_BE 0x001E
#define LSb32TG_VB1_BE 16
#define LSb16TG_VB1_BE 0
#define bTG_VB1_BE 16
#define MSK32TG_VB1_BE 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_SCAN 0x0020
#define BA_TG_SCAN_MODE 0x0020
#define B16TG_SCAN_MODE 0x0020
#define LSb32TG_SCAN_MODE 0
#define LSb16TG_SCAN_MODE 0
#define bTG_SCAN_MODE 1
#define MSK32TG_SCAN_MODE 0x00000001
#define TG_SCAN_MODE_PROG 0x0
#define TG_SCAN_MODE_INTER 0x1
///////////////////////////////////////////////////////////
#define RA_TG_INTPOS 0x0024
#define BA_TG_INTPOS_FRAME 0x0024
#define B16TG_INTPOS_FRAME 0x0024
#define LSb32TG_INTPOS_FRAME 0
#define LSb16TG_INTPOS_FRAME 0
#define bTG_INTPOS_FRAME 16
#define MSK32TG_INTPOS_FRAME 0x0000FFFF
#define BA_TG_INTPOS_FIELD 0x0026
#define B16TG_INTPOS_FIELD 0x0026
#define LSb32TG_INTPOS_FIELD 16
#define LSb16TG_INTPOS_FIELD 0
#define bTG_INTPOS_FIELD 16
#define MSK32TG_INTPOS_FIELD 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_TG_MODE 0x0028
#define BA_TG_MODE_EN 0x0028
#define B16TG_MODE_EN 0x0028
#define LSb32TG_MODE_EN 0
#define LSb16TG_MODE_EN 0
#define bTG_MODE_EN 1
#define MSK32TG_MODE_EN 0x00000001
#define TG_MODE_EN_MASTER 0x0
#define TG_MODE_EN_SLAVE 0x1
///////////////////////////////////////////////////////////
#define RA_TG_HVREF 0x002C
#define BA_TG_HVREF_SEL 0x002C
#define B16TG_HVREF_SEL 0x002C
#define LSb32TG_HVREF_SEL 0
#define LSb16TG_HVREF_SEL 0
#define bTG_HVREF_SEL 1
#define MSK32TG_HVREF_SEL 0x00000001
#define TG_HVREF_SEL_SYNC 0x0
#define TG_HVREF_SEL_BLANK 0x1
#define BA_TG_HVREF_POL 0x002C
#define B16TG_HVREF_POL 0x002C
#define LSb32TG_HVREF_POL 1
#define LSb16TG_HVREF_POL 1
#define bTG_HVREF_POL 1
#define MSK32TG_HVREF_POL 0x00000002
#define TG_HVREF_POL_NEG_PULSE 0x0
#define TG_HVREF_POL_POS_PULSE 0x1
///////////////////////////////////////////////////////////
typedef struct SIE_TG {
///////////////////////////////////////////////////////////
#define GET32TG_INIT_Y(r32) _BFGET_(r32,15, 0)
#define SET32TG_INIT_Y(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_INIT_Y(r16) _BFGET_(r16,15, 0)
#define SET16TG_INIT_Y(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_INIT_X(r32) _BFGET_(r32,31,16)
#define SET32TG_INIT_X(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_INIT_X(r16) _BFGET_(r16,15, 0)
#define SET16TG_INIT_X(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_INIT {\
UNSG32 uINIT_Y : 16;\
UNSG32 uINIT_X : 16;\
}
union { UNSG32 u32TG_INIT;
struct w32TG_INIT;
};
///////////////////////////////////////////////////////////
#define GET32TG_SIZE_Y(r32) _BFGET_(r32,15, 0)
#define SET32TG_SIZE_Y(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_SIZE_Y(r16) _BFGET_(r16,15, 0)
#define SET16TG_SIZE_Y(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_SIZE_X(r32) _BFGET_(r32,31,16)
#define SET32TG_SIZE_X(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_SIZE_X(r16) _BFGET_(r16,15, 0)
#define SET16TG_SIZE_X(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_SIZE {\
UNSG32 uSIZE_Y : 16;\
UNSG32 uSIZE_X : 16;\
}
union { UNSG32 u32TG_SIZE;
struct w32TG_SIZE;
};
///////////////////////////////////////////////////////////
#define GET32TG_HS_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_HS_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_HS_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_HS_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_HS_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_HS_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_HS_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_HS_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_HS {\
UNSG32 uHS_FE : 16;\
UNSG32 uHS_BE : 16;\
}
union { UNSG32 u32TG_HS;
struct w32TG_HS;
};
///////////////////////////////////////////////////////////
#define GET32TG_HB_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_HB_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_HB_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_HB_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_HB_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_HB_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_HB_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_HB_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_HB {\
UNSG32 uHB_FE : 16;\
UNSG32 uHB_BE : 16;\
}
union { UNSG32 u32TG_HB;
struct w32TG_HB;
};
///////////////////////////////////////////////////////////
#define GET32TG_VS0_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_VS0_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_VS0_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VS0_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_VS0_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_VS0_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_VS0_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VS0_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_VS0 {\
UNSG32 uVS0_FE : 16;\
UNSG32 uVS0_BE : 16;\
}
union { UNSG32 u32TG_VS0;
struct w32TG_VS0;
};
///////////////////////////////////////////////////////////
#define GET32TG_VS1_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_VS1_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_VS1_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VS1_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_VS1_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_VS1_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_VS1_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VS1_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_VS1 {\
UNSG32 uVS1_FE : 16;\
UNSG32 uVS1_BE : 16;\
}
union { UNSG32 u32TG_VS1;
struct w32TG_VS1;
};
///////////////////////////////////////////////////////////
#define GET32TG_VB0_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_VB0_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_VB0_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VB0_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_VB0_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_VB0_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_VB0_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VB0_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_VB0 {\
UNSG32 uVB0_FE : 16;\
UNSG32 uVB0_BE : 16;\
}
union { UNSG32 u32TG_VB0;
struct w32TG_VB0;
};
///////////////////////////////////////////////////////////
#define GET32TG_VB1_FE(r32) _BFGET_(r32,15, 0)
#define SET32TG_VB1_FE(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_VB1_FE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VB1_FE(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_VB1_BE(r32) _BFGET_(r32,31,16)
#define SET32TG_VB1_BE(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_VB1_BE(r16) _BFGET_(r16,15, 0)
#define SET16TG_VB1_BE(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_VB1 {\
UNSG32 uVB1_FE : 16;\
UNSG32 uVB1_BE : 16;\
}
union { UNSG32 u32TG_VB1;
struct w32TG_VB1;
};
///////////////////////////////////////////////////////////
#define GET32TG_SCAN_MODE(r32) _BFGET_(r32, 0, 0)
#define SET32TG_SCAN_MODE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16TG_SCAN_MODE(r16) _BFGET_(r16, 0, 0)
#define SET16TG_SCAN_MODE(r16,v) _BFSET_(r16, 0, 0,v)
#define w32TG_SCAN {\
UNSG32 uSCAN_MODE : 1;\
UNSG32 RSVDx20_b1 : 31;\
}
union { UNSG32 u32TG_SCAN;
struct w32TG_SCAN;
};
///////////////////////////////////////////////////////////
#define GET32TG_INTPOS_FRAME(r32) _BFGET_(r32,15, 0)
#define SET32TG_INTPOS_FRAME(r32,v) _BFSET_(r32,15, 0,v)
#define GET16TG_INTPOS_FRAME(r16) _BFGET_(r16,15, 0)
#define SET16TG_INTPOS_FRAME(r16,v) _BFSET_(r16,15, 0,v)
#define GET32TG_INTPOS_FIELD(r32) _BFGET_(r32,31,16)
#define SET32TG_INTPOS_FIELD(r32,v) _BFSET_(r32,31,16,v)
#define GET16TG_INTPOS_FIELD(r16) _BFGET_(r16,15, 0)
#define SET16TG_INTPOS_FIELD(r16,v) _BFSET_(r16,15, 0,v)
#define w32TG_INTPOS {\
UNSG32 uINTPOS_FRAME : 16;\
UNSG32 uINTPOS_FIELD : 16;\
}
union { UNSG32 u32TG_INTPOS;
struct w32TG_INTPOS;
};
///////////////////////////////////////////////////////////
#define GET32TG_MODE_EN(r32) _BFGET_(r32, 0, 0)
#define SET32TG_MODE_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16TG_MODE_EN(r16) _BFGET_(r16, 0, 0)
#define SET16TG_MODE_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define w32TG_MODE {\
UNSG32 uMODE_EN : 1;\
UNSG32 RSVDx28_b1 : 31;\
}
union { UNSG32 u32TG_MODE;
struct w32TG_MODE;
};
///////////////////////////////////////////////////////////
#define GET32TG_HVREF_SEL(r32) _BFGET_(r32, 0, 0)
#define SET32TG_HVREF_SEL(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16TG_HVREF_SEL(r16) _BFGET_(r16, 0, 0)
#define SET16TG_HVREF_SEL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32TG_HVREF_POL(r32) _BFGET_(r32, 1, 1)
#define SET32TG_HVREF_POL(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16TG_HVREF_POL(r16) _BFGET_(r16, 1, 1)
#define SET16TG_HVREF_POL(r16,v) _BFSET_(r16, 1, 1,v)
#define w32TG_HVREF {\
UNSG32 uHVREF_SEL : 1;\
UNSG32 uHVREF_POL : 1;\
UNSG32 RSVDx2C_b2 : 30;\
}
union { UNSG32 u32TG_HVREF;
struct w32TG_HVREF;
};
///////////////////////////////////////////////////////////
} SIE_TG;
typedef union T32TG_INIT
{ UNSG32 u32;
struct w32TG_INIT;
} T32TG_INIT;
typedef union T32TG_SIZE
{ UNSG32 u32;
struct w32TG_SIZE;
} T32TG_SIZE;
typedef union T32TG_HS
{ UNSG32 u32;
struct w32TG_HS;
} T32TG_HS;
typedef union T32TG_HB
{ UNSG32 u32;
struct w32TG_HB;
} T32TG_HB;
typedef union T32TG_VS0
{ UNSG32 u32;
struct w32TG_VS0;
} T32TG_VS0;
typedef union T32TG_VS1
{ UNSG32 u32;
struct w32TG_VS1;
} T32TG_VS1;
typedef union T32TG_VB0
{ UNSG32 u32;
struct w32TG_VB0;
} T32TG_VB0;
typedef union T32TG_VB1
{ UNSG32 u32;
struct w32TG_VB1;
} T32TG_VB1;
typedef union T32TG_SCAN
{ UNSG32 u32;
struct w32TG_SCAN;
} T32TG_SCAN;
typedef union T32TG_INTPOS
{ UNSG32 u32;
struct w32TG_INTPOS;
} T32TG_INTPOS;
typedef union T32TG_MODE
{ UNSG32 u32;
struct w32TG_MODE;
} T32TG_MODE;
typedef union T32TG_HVREF
{ UNSG32 u32;
struct w32TG_HVREF;
} T32TG_HVREF;
///////////////////////////////////////////////////////////
typedef union TTG_INIT
{ UNSG32 u32[1];
struct {
struct w32TG_INIT;
};
} TTG_INIT;
typedef union TTG_SIZE
{ UNSG32 u32[1];
struct {
struct w32TG_SIZE;
};
} TTG_SIZE;
typedef union TTG_HS
{ UNSG32 u32[1];
struct {
struct w32TG_HS;
};
} TTG_HS;
typedef union TTG_HB
{ UNSG32 u32[1];
struct {
struct w32TG_HB;
};
} TTG_HB;
typedef union TTG_VS0
{ UNSG32 u32[1];
struct {
struct w32TG_VS0;
};
} TTG_VS0;
typedef union TTG_VS1
{ UNSG32 u32[1];
struct {
struct w32TG_VS1;
};
} TTG_VS1;
typedef union TTG_VB0
{ UNSG32 u32[1];
struct {
struct w32TG_VB0;
};
} TTG_VB0;
typedef union TTG_VB1
{ UNSG32 u32[1];
struct {
struct w32TG_VB1;
};
} TTG_VB1;
typedef union TTG_SCAN
{ UNSG32 u32[1];
struct {
struct w32TG_SCAN;
};
} TTG_SCAN;
typedef union TTG_INTPOS
{ UNSG32 u32[1];
struct {
struct w32TG_INTPOS;
};
} TTG_INTPOS;
typedef union TTG_MODE
{ UNSG32 u32[1];
struct {
struct w32TG_MODE;
};
} TTG_MODE;
typedef union TTG_HVREF
{ UNSG32 u32[1];
struct {
struct w32TG_HVREF;
};
} TTG_HVREF;
///////////////////////////////////////////////////////////
SIGN32 TG_drvrd(SIE_TG *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 TG_drvwr(SIE_TG *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void TG_reset(SIE_TG *p);
SIGN32 TG_cmp (SIE_TG *p, SIE_TG *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define TG_check(p,pie,pfx,hLOG) TG_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define TG_print(p, pfx,hLOG) TG_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: TG
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE VIP_ctrl biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// %unsigned 1 dvi_wc_clr 0x0
/// ###
/// * vip_dvi_wclient_clear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the FIFO between the respective client's packer and asynchronous FIFO used for that client.when this is set , also set fl_dvi_wclr .
/// ###
/// %unsigned 1 dvi_wc_st 0x0
/// ###
/// * vip_dvi_wclient_start
/// * Start bit for the respective clients.
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %unsigned 2 dvi_wc_packsel 0x0
/// ###
/// * vip_dvi_wclient_packsel
/// * 00 – data supported is 16 bit.
/// * 01, 10, 11 – data supported is 24 bit.
/// ###
/// %% 28 # Stuffing bits...
/// %unsigned 32 dvi_wc_pixtot 0x0
/// ###
/// * vip_dvi_wclient_pixtot
/// * Specifies the total number of pixels expected from VIP dither to its write client. This is used to generate flush in VIP_DVIW client to write the partially formed 64-bit data (if any) to DDR.
/// * Should be programmed with (vres*hres).
/// ###
/// %unsigned 1 vbi_wc_clr 0x0
/// ###
/// * vip_vbi_wclient_clear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the FIFO between the respective client's packer and asynchronous FIFO used for that client.when this is set , also set fl_vbi_wclr.
/// ###
/// %unsigned 1 vbi_wc_st 0x0
/// ###
/// * vip_vbi_wclient_start
/// * Start bit for the respective clients.
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %unsigned 2 vbi_wc_packsel 0x0
/// ###
/// * vip_vbi_wclient_packsel
/// ###
/// %% 28 # Stuffing bits...
/// %unsigned 32 vbi_wc_pixtot 0x0
/// ###
/// * vip_vbi_wclient_pixtot
/// * Specifies the total number of VBI pixels expected from its write client. This is used to generate flush in VBIW client to write the partially formed 64-bit data (if any) to DDR.
/// * i.e. it is the number of VBI pixel data expected over that frame and when programmed to max value, the flush will happen 1) after the max value of VBI data is written or if the interrupt is detected, whichever occurs 1st.
/// * actual value = (number of VBI lines * (number of bytes of VBI data / line)).
/// * max value = (no of VBI lines * 257)
/// ###
/// %unsigned 1 sd_wc_clr 0x0
/// ###
/// * SD video wclient clear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the FIFO between the respective client's packer and asynchronous FIFO used for that client.when this is set , also set fl_sd_wclr.
/// ###
/// %unsigned 1 sd_wc_st 0x0
/// ###
/// * SD video wclient_start
/// * Start bit for the respective clients.
/// * 0 – No effect on hardware.
/// * 1 – start the client. Setting this bit 1 allows the hardware write interrupt to restarts the write client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %unsigned 2 sd_wc_packsel 0x0
/// ###
/// * SD video wclient_packsel
/// * don't care
/// ###
/// %% 28 # Stuffing bits...
/// %unsigned 32 sd_wc_pixtot 0x0
/// ###
/// * SD video wclient_pixtot
/// * Specifies the total number of pixels expected from VIP dither to its write client. This is used to generate flush in VIP_SDW client to write the partially formed 64-bit data (if any) to DDR.
/// * should be programmed with hres*vres.
/// ###
/// %unsigned 1 sd_rc_clr 0x0
/// ###
/// * SD video rclient clear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the FIFO between the respective client's packer and asynchronous FIFO used for that client.when this is set , also set fl_sd_rclr.
/// ###
/// %unsigned 1 sd_rc_st 0x0
/// ###
/// * SD video rclient_start
/// * Start bit for the respective clients.
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %unsigned 2 sd_rc_packsel 0x0
/// ###
/// * SD video rclient_packsel
/// * don't care
/// ###
/// %% 28 # Stuffing bits...
/// %unsigned 32 sd_rc_pixtot 0x0
/// ###
/// * SD video rclient_pixtot
/// * Specifies the total number of pixels expected from VIP dither to its write client. This is used to generate flush in VIP_SDW client to write the partially formed 64-bit data (if any) to DDR.
/// * should be programmed with hres*vres.
/// ###
/// %unsigned 1 fl_sd_rclr 0x0
/// ###
/// * Flush SD video Rclear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the asynchronous FIFO between the respective client and dHub.
/// ###
/// %unsigned 1 fl_sd_wclr 0x0
/// ###
/// * Flush SD video Wclear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the asynchronous FIFO between the respective client and dHub.
/// ###
/// %unsigned 1 fl_dvi_wclr 0x0
/// ###
/// * Flush DVI Wclear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the asynchronous FIFO between the respective client and dHub.
/// ###
/// %unsigned 1 fl_vbi_wclr 0x0
/// ###
/// * Flush VBI Wclear
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the asynchronous FIFO between the respective client and dHub.
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00024 (P)
/// # 0x00024 DVI_FE_BE
/// $DVI_FE_BE DVI_FE_BE REG
/// ###
/// * All the FE_BE channel registers of VIP
/// ###
/// @ 0x00034 SCL_CLKEN_CTRL (P)
/// %unsigned 1 DVI 0x1
/// ###
/// * 0: Clock enable to scaler depends on the input FIFO status; scaler clken is deasserted when input side (dither) can't supply data to scaler.
/// * 1: Clock enable to scaler is always high.
/// * Since DVI scaler input always comes from Dither (VIP inputs) – its clock enable should be 1 whenever it is being used.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00038 DVI_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// ###
/// * Specifies the number of line buffer locations required to store one input (or scaled) line. How to calculate:
/// * If(hscaler before vscaler) hres = ohres;
/// * else hres = ihres;
/// * TS = Is 24 bit per pixel ? 5 : 8;
/// * lsize = ceil ( hres / (TS+1) )
/// ###
/// %% 23 # Stuffing bits...
/// @ 0x0003C OFRST_SEL (P)
/// %unsigned 1 DVI 0x0
/// ###
/// * 0 : Use frame reset (ofrst signal) generated by fe_be module in DVI pipe depending on the DVI_FE_BE_FRST value.
/// * 1 : Use register OFRST_SW_DVI as frame reset to DVI scaler.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00040 OFRST_SW (P)
/// %unsigned 1 DVI 0x0
/// ###
/// * when OFRST_SEL is 1,this bit is used as software frame reset instead of the internally generated frame reset signal. (this bit should follow register bit dvi_wc_st).
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00044 intr_sel (P)
/// %unsigned 1 DVI 0x1
/// ###
/// * 0 : Use selected frame reset depending on ofrst_sel signal as the interrupt.
/// * 1 : Use dvi vde falling edge as interrupt used to initialize DHUB.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00048 vbi_vde_cnt (P)
/// %unsigned 8 VBI 0x0
/// ###
/// * Can be programmed to any value between 0x00 to 0XFF, where
/// * vbi_vde_cnt = 0x00, represents a vde falling edge ,
/// * vbi_vde_cnt = (DVI Vtotal – DVI Vactive), represents a Vde rising edge,
/// * vbi_vde_cnt = [(DVI Vtotal – DVI Vactive) + 1], represents an Interrupt generated in vactive region generated for VBI Dhub
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0004C VBI_CTRL (P)
/// %unsigned 3 data_sel 0x0
/// ###
/// * VBI data dumping options:
/// * 000: DID + SDID + data_cnt + data_cnt num of user data bytes + checksum (this is default option and same as old).
/// * 001: DID + SDID + data_cnt + 256 bytes of user data irrespective of data_cnt + checksum.
/// * 010: preamble (00, FF, FF) + DID + SDID + data_cnt + data_cnt num of user data bytes + checksum.
/// * 011: preamble (00, FF, FF) + DID + SDID + data_cnt + 256 bytes of user data irrespective of data_cnt + checksum.
/// * 1xx : FF, 00, EAV + complete vertical blanking data + FF, 00, FAV
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00050 INTR_EN (P)
/// %unsigned 1 SD_WR 0x1
/// ###
/// * Enable SD write interrupt
/// ###
/// %unsigned 1 SD_RD 0x1
/// ###
/// * Enable SD read interrupt
/// ###
/// %unsigned 1 SD_ERR 0x1
/// ###
/// * Enable SD error interrupt
/// ###
/// %unsigned 1 VBI 0x1
/// ###
/// * Enable VBI interrupt
/// ###
/// %unsigned 1 DVI 0x1
/// ###
/// * Enable DVI interrupt
/// ###
/// %unsigned 1 SD_SIG_ERR 0x1
/// ###
/// * Enable SD VIP signature check error (for DRAM interface) interrupt
/// ###
/// %unsigned 1 BCM_INVALID 0x1
/// ###
/// * Enable BCM_INVALID interrupt when access to invalid address is made using BCM
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x00054 SIG_CTRL (P)
/// %unsigned 1 en 0x0
/// ###
/// * 0 : signature check is disabled.
/// * 1 : signature check is enabled.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00058 SIG_pix_cnt (P)
/// %unsigned 32 pix_cnt 0x0
/// ###
/// * Delay between write and read in terms of pixels. This value should be equal to number of active pixels in a frame (VACTIVE * HACTIVE). Signature check module calculates the signature over pix_cnt number of pixels on write_data and read_data and compares.
/// ###
/// @ 0x0005C SIG_STS (R-)
/// %unsigned 1 err 0x0
/// ###
/// * SD signature check module error status signal. This bit is set whenever signature is mismatched. This bit is cleared when SIG_CTRL.en bit is 0.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00060 VIP_PIPE_CLR (P)
/// %unsigned 1 dvi_wc_clr_hw 0x0
/// ###
/// * vip_dvi_wclient_clear_hw
/// * 0 – use (vip_dvi_wclient_clear) i.e VIP_ctrl_dvi_wc_clr to clear the DVI write client (FIFO between the respective client's packer and asynchronous FIFO used for that client.when this is set , also set fl_dvi_wclr ) on the interrupt.
/// * 1 – clear the client. Setting this bit 1 allows the hardware DVI write interrupt to clear the write client.
/// ###
/// %unsigned 1 dvi_wc_st_hw 0x0
/// ###
/// * vip_dvi_wclient_start_hw
/// * Start bit for the respective clients.
/// * 0 – use S/W vip_dvi_wclient_start bit to manually stop and start the client based on S/W read interrupt.
/// * 1 – start the client. Setting this bit 1 allows the hardware DVI write interrupt to restarts the write client.
/// ###
/// %unsigned 1 fl_dvi_wclr_hw 0x0
/// ###
/// * Flush DVI Wclear
/// * 0 – Clear the asynchronous FIFO between the respective client and dHub manually through S/W write to this register on the S/W read respective interrupt.
/// * 1- Setting this bit 1 allows the hardware write interrupt to Clear the asynchronous FIFO between the respective client and dHub based on interrupt
/// ###
/// %% 29 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 100B, bits: 252b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_VIP_ctrl
#define h_VIP_ctrl (){}
#define BA_VIP_ctrl_dvi_wc_clr 0x0000
#define B16VIP_ctrl_dvi_wc_clr 0x0000
#define LSb32VIP_ctrl_dvi_wc_clr 0
#define LSb16VIP_ctrl_dvi_wc_clr 0
#define bVIP_ctrl_dvi_wc_clr 1
#define MSK32VIP_ctrl_dvi_wc_clr 0x00000001
#define BA_VIP_ctrl_dvi_wc_st 0x0000
#define B16VIP_ctrl_dvi_wc_st 0x0000
#define LSb32VIP_ctrl_dvi_wc_st 1
#define LSb16VIP_ctrl_dvi_wc_st 1
#define bVIP_ctrl_dvi_wc_st 1
#define MSK32VIP_ctrl_dvi_wc_st 0x00000002
#define BA_VIP_ctrl_dvi_wc_packsel 0x0000
#define B16VIP_ctrl_dvi_wc_packsel 0x0000
#define LSb32VIP_ctrl_dvi_wc_packsel 2
#define LSb16VIP_ctrl_dvi_wc_packsel 2
#define bVIP_ctrl_dvi_wc_packsel 2
#define MSK32VIP_ctrl_dvi_wc_packsel 0x0000000C
#define BA_VIP_ctrl_dvi_wc_pixtot 0x0004
#define B16VIP_ctrl_dvi_wc_pixtot 0x0004
#define LSb32VIP_ctrl_dvi_wc_pixtot 0
#define LSb16VIP_ctrl_dvi_wc_pixtot 0
#define bVIP_ctrl_dvi_wc_pixtot 32
#define MSK32VIP_ctrl_dvi_wc_pixtot 0xFFFFFFFF
#define BA_VIP_ctrl_vbi_wc_clr 0x0008
#define B16VIP_ctrl_vbi_wc_clr 0x0008
#define LSb32VIP_ctrl_vbi_wc_clr 0
#define LSb16VIP_ctrl_vbi_wc_clr 0
#define bVIP_ctrl_vbi_wc_clr 1
#define MSK32VIP_ctrl_vbi_wc_clr 0x00000001
#define BA_VIP_ctrl_vbi_wc_st 0x0008
#define B16VIP_ctrl_vbi_wc_st 0x0008
#define LSb32VIP_ctrl_vbi_wc_st 1
#define LSb16VIP_ctrl_vbi_wc_st 1
#define bVIP_ctrl_vbi_wc_st 1
#define MSK32VIP_ctrl_vbi_wc_st 0x00000002
#define BA_VIP_ctrl_vbi_wc_packsel 0x0008
#define B16VIP_ctrl_vbi_wc_packsel 0x0008
#define LSb32VIP_ctrl_vbi_wc_packsel 2
#define LSb16VIP_ctrl_vbi_wc_packsel 2
#define bVIP_ctrl_vbi_wc_packsel 2
#define MSK32VIP_ctrl_vbi_wc_packsel 0x0000000C
#define BA_VIP_ctrl_vbi_wc_pixtot 0x000C
#define B16VIP_ctrl_vbi_wc_pixtot 0x000C
#define LSb32VIP_ctrl_vbi_wc_pixtot 0
#define LSb16VIP_ctrl_vbi_wc_pixtot 0
#define bVIP_ctrl_vbi_wc_pixtot 32
#define MSK32VIP_ctrl_vbi_wc_pixtot 0xFFFFFFFF
#define BA_VIP_ctrl_sd_wc_clr 0x0010
#define B16VIP_ctrl_sd_wc_clr 0x0010
#define LSb32VIP_ctrl_sd_wc_clr 0
#define LSb16VIP_ctrl_sd_wc_clr 0
#define bVIP_ctrl_sd_wc_clr 1
#define MSK32VIP_ctrl_sd_wc_clr 0x00000001
#define BA_VIP_ctrl_sd_wc_st 0x0010
#define B16VIP_ctrl_sd_wc_st 0x0010
#define LSb32VIP_ctrl_sd_wc_st 1
#define LSb16VIP_ctrl_sd_wc_st 1
#define bVIP_ctrl_sd_wc_st 1
#define MSK32VIP_ctrl_sd_wc_st 0x00000002
#define BA_VIP_ctrl_sd_wc_packsel 0x0010
#define B16VIP_ctrl_sd_wc_packsel 0x0010
#define LSb32VIP_ctrl_sd_wc_packsel 2
#define LSb16VIP_ctrl_sd_wc_packsel 2
#define bVIP_ctrl_sd_wc_packsel 2
#define MSK32VIP_ctrl_sd_wc_packsel 0x0000000C
#define BA_VIP_ctrl_sd_wc_pixtot 0x0014
#define B16VIP_ctrl_sd_wc_pixtot 0x0014
#define LSb32VIP_ctrl_sd_wc_pixtot 0
#define LSb16VIP_ctrl_sd_wc_pixtot 0
#define bVIP_ctrl_sd_wc_pixtot 32
#define MSK32VIP_ctrl_sd_wc_pixtot 0xFFFFFFFF
#define BA_VIP_ctrl_sd_rc_clr 0x0018
#define B16VIP_ctrl_sd_rc_clr 0x0018
#define LSb32VIP_ctrl_sd_rc_clr 0
#define LSb16VIP_ctrl_sd_rc_clr 0
#define bVIP_ctrl_sd_rc_clr 1
#define MSK32VIP_ctrl_sd_rc_clr 0x00000001
#define BA_VIP_ctrl_sd_rc_st 0x0018
#define B16VIP_ctrl_sd_rc_st 0x0018
#define LSb32VIP_ctrl_sd_rc_st 1
#define LSb16VIP_ctrl_sd_rc_st 1
#define bVIP_ctrl_sd_rc_st 1
#define MSK32VIP_ctrl_sd_rc_st 0x00000002
#define BA_VIP_ctrl_sd_rc_packsel 0x0018
#define B16VIP_ctrl_sd_rc_packsel 0x0018
#define LSb32VIP_ctrl_sd_rc_packsel 2
#define LSb16VIP_ctrl_sd_rc_packsel 2
#define bVIP_ctrl_sd_rc_packsel 2
#define MSK32VIP_ctrl_sd_rc_packsel 0x0000000C
#define BA_VIP_ctrl_sd_rc_pixtot 0x001C
#define B16VIP_ctrl_sd_rc_pixtot 0x001C
#define LSb32VIP_ctrl_sd_rc_pixtot 0
#define LSb16VIP_ctrl_sd_rc_pixtot 0
#define bVIP_ctrl_sd_rc_pixtot 32
#define MSK32VIP_ctrl_sd_rc_pixtot 0xFFFFFFFF
#define BA_VIP_ctrl_fl_sd_rclr 0x0020
#define B16VIP_ctrl_fl_sd_rclr 0x0020
#define LSb32VIP_ctrl_fl_sd_rclr 0
#define LSb16VIP_ctrl_fl_sd_rclr 0
#define bVIP_ctrl_fl_sd_rclr 1
#define MSK32VIP_ctrl_fl_sd_rclr 0x00000001
#define BA_VIP_ctrl_fl_sd_wclr 0x0020
#define B16VIP_ctrl_fl_sd_wclr 0x0020
#define LSb32VIP_ctrl_fl_sd_wclr 1
#define LSb16VIP_ctrl_fl_sd_wclr 1
#define bVIP_ctrl_fl_sd_wclr 1
#define MSK32VIP_ctrl_fl_sd_wclr 0x00000002
#define BA_VIP_ctrl_fl_dvi_wclr 0x0020
#define B16VIP_ctrl_fl_dvi_wclr 0x0020
#define LSb32VIP_ctrl_fl_dvi_wclr 2
#define LSb16VIP_ctrl_fl_dvi_wclr 2
#define bVIP_ctrl_fl_dvi_wclr 1
#define MSK32VIP_ctrl_fl_dvi_wclr 0x00000004
#define BA_VIP_ctrl_fl_vbi_wclr 0x0020
#define B16VIP_ctrl_fl_vbi_wclr 0x0020
#define LSb32VIP_ctrl_fl_vbi_wclr 3
#define LSb16VIP_ctrl_fl_vbi_wclr 3
#define bVIP_ctrl_fl_vbi_wclr 1
#define MSK32VIP_ctrl_fl_vbi_wclr 0x00000008
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_DVI_FE_BE 0x0024
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_SCL_CLKEN_CTRL 0x0034
#define BA_VIP_ctrl_SCL_CLKEN_CTRL_DVI 0x0034
#define B16VIP_ctrl_SCL_CLKEN_CTRL_DVI 0x0034
#define LSb32VIP_ctrl_SCL_CLKEN_CTRL_DVI 0
#define LSb16VIP_ctrl_SCL_CLKEN_CTRL_DVI 0
#define bVIP_ctrl_SCL_CLKEN_CTRL_DVI 1
#define MSK32VIP_ctrl_SCL_CLKEN_CTRL_DVI 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_DVI_LSIZE 0x0038
#define BA_VIP_ctrl_DVI_LSIZE_lsize 0x0038
#define B16VIP_ctrl_DVI_LSIZE_lsize 0x0038
#define LSb32VIP_ctrl_DVI_LSIZE_lsize 0
#define LSb16VIP_ctrl_DVI_LSIZE_lsize 0
#define bVIP_ctrl_DVI_LSIZE_lsize 9
#define MSK32VIP_ctrl_DVI_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_OFRST_SEL 0x003C
#define BA_VIP_ctrl_OFRST_SEL_DVI 0x003C
#define B16VIP_ctrl_OFRST_SEL_DVI 0x003C
#define LSb32VIP_ctrl_OFRST_SEL_DVI 0
#define LSb16VIP_ctrl_OFRST_SEL_DVI 0
#define bVIP_ctrl_OFRST_SEL_DVI 1
#define MSK32VIP_ctrl_OFRST_SEL_DVI 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_OFRST_SW 0x0040
#define BA_VIP_ctrl_OFRST_SW_DVI 0x0040
#define B16VIP_ctrl_OFRST_SW_DVI 0x0040
#define LSb32VIP_ctrl_OFRST_SW_DVI 0
#define LSb16VIP_ctrl_OFRST_SW_DVI 0
#define bVIP_ctrl_OFRST_SW_DVI 1
#define MSK32VIP_ctrl_OFRST_SW_DVI 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_intr_sel 0x0044
#define BA_VIP_ctrl_intr_sel_DVI 0x0044
#define B16VIP_ctrl_intr_sel_DVI 0x0044
#define LSb32VIP_ctrl_intr_sel_DVI 0
#define LSb16VIP_ctrl_intr_sel_DVI 0
#define bVIP_ctrl_intr_sel_DVI 1
#define MSK32VIP_ctrl_intr_sel_DVI 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_vbi_vde_cnt 0x0048
#define BA_VIP_ctrl_vbi_vde_cnt_VBI 0x0048
#define B16VIP_ctrl_vbi_vde_cnt_VBI 0x0048
#define LSb32VIP_ctrl_vbi_vde_cnt_VBI 0
#define LSb16VIP_ctrl_vbi_vde_cnt_VBI 0
#define bVIP_ctrl_vbi_vde_cnt_VBI 8
#define MSK32VIP_ctrl_vbi_vde_cnt_VBI 0x000000FF
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_VBI_CTRL 0x004C
#define BA_VIP_ctrl_VBI_CTRL_data_sel 0x004C
#define B16VIP_ctrl_VBI_CTRL_data_sel 0x004C
#define LSb32VIP_ctrl_VBI_CTRL_data_sel 0
#define LSb16VIP_ctrl_VBI_CTRL_data_sel 0
#define bVIP_ctrl_VBI_CTRL_data_sel 3
#define MSK32VIP_ctrl_VBI_CTRL_data_sel 0x00000007
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_INTR_EN 0x0050
#define BA_VIP_ctrl_INTR_EN_SD_WR 0x0050
#define B16VIP_ctrl_INTR_EN_SD_WR 0x0050
#define LSb32VIP_ctrl_INTR_EN_SD_WR 0
#define LSb16VIP_ctrl_INTR_EN_SD_WR 0
#define bVIP_ctrl_INTR_EN_SD_WR 1
#define MSK32VIP_ctrl_INTR_EN_SD_WR 0x00000001
#define BA_VIP_ctrl_INTR_EN_SD_RD 0x0050
#define B16VIP_ctrl_INTR_EN_SD_RD 0x0050
#define LSb32VIP_ctrl_INTR_EN_SD_RD 1
#define LSb16VIP_ctrl_INTR_EN_SD_RD 1
#define bVIP_ctrl_INTR_EN_SD_RD 1
#define MSK32VIP_ctrl_INTR_EN_SD_RD 0x00000002
#define BA_VIP_ctrl_INTR_EN_SD_ERR 0x0050
#define B16VIP_ctrl_INTR_EN_SD_ERR 0x0050
#define LSb32VIP_ctrl_INTR_EN_SD_ERR 2
#define LSb16VIP_ctrl_INTR_EN_SD_ERR 2
#define bVIP_ctrl_INTR_EN_SD_ERR 1
#define MSK32VIP_ctrl_INTR_EN_SD_ERR 0x00000004
#define BA_VIP_ctrl_INTR_EN_VBI 0x0050
#define B16VIP_ctrl_INTR_EN_VBI 0x0050
#define LSb32VIP_ctrl_INTR_EN_VBI 3
#define LSb16VIP_ctrl_INTR_EN_VBI 3
#define bVIP_ctrl_INTR_EN_VBI 1
#define MSK32VIP_ctrl_INTR_EN_VBI 0x00000008
#define BA_VIP_ctrl_INTR_EN_DVI 0x0050
#define B16VIP_ctrl_INTR_EN_DVI 0x0050
#define LSb32VIP_ctrl_INTR_EN_DVI 4
#define LSb16VIP_ctrl_INTR_EN_DVI 4
#define bVIP_ctrl_INTR_EN_DVI 1
#define MSK32VIP_ctrl_INTR_EN_DVI 0x00000010
#define BA_VIP_ctrl_INTR_EN_SD_SIG_ERR 0x0050
#define B16VIP_ctrl_INTR_EN_SD_SIG_ERR 0x0050
#define LSb32VIP_ctrl_INTR_EN_SD_SIG_ERR 5
#define LSb16VIP_ctrl_INTR_EN_SD_SIG_ERR 5
#define bVIP_ctrl_INTR_EN_SD_SIG_ERR 1
#define MSK32VIP_ctrl_INTR_EN_SD_SIG_ERR 0x00000020
#define BA_VIP_ctrl_INTR_EN_BCM_INVALID 0x0050
#define B16VIP_ctrl_INTR_EN_BCM_INVALID 0x0050
#define LSb32VIP_ctrl_INTR_EN_BCM_INVALID 6
#define LSb16VIP_ctrl_INTR_EN_BCM_INVALID 6
#define bVIP_ctrl_INTR_EN_BCM_INVALID 1
#define MSK32VIP_ctrl_INTR_EN_BCM_INVALID 0x00000040
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_SIG_CTRL 0x0054
#define BA_VIP_ctrl_SIG_CTRL_en 0x0054
#define B16VIP_ctrl_SIG_CTRL_en 0x0054
#define LSb32VIP_ctrl_SIG_CTRL_en 0
#define LSb16VIP_ctrl_SIG_CTRL_en 0
#define bVIP_ctrl_SIG_CTRL_en 1
#define MSK32VIP_ctrl_SIG_CTRL_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_SIG_pix_cnt 0x0058
#define BA_VIP_ctrl_SIG_pix_cnt_pix_cnt 0x0058
#define B16VIP_ctrl_SIG_pix_cnt_pix_cnt 0x0058
#define LSb32VIP_ctrl_SIG_pix_cnt_pix_cnt 0
#define LSb16VIP_ctrl_SIG_pix_cnt_pix_cnt 0
#define bVIP_ctrl_SIG_pix_cnt_pix_cnt 32
#define MSK32VIP_ctrl_SIG_pix_cnt_pix_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_SIG_STS 0x005C
#define BA_VIP_ctrl_SIG_STS_err 0x005C
#define B16VIP_ctrl_SIG_STS_err 0x005C
#define LSb32VIP_ctrl_SIG_STS_err 0
#define LSb16VIP_ctrl_SIG_STS_err 0
#define bVIP_ctrl_SIG_STS_err 1
#define MSK32VIP_ctrl_SIG_STS_err 0x00000001
///////////////////////////////////////////////////////////
#define RA_VIP_ctrl_VIP_PIPE_CLR 0x0060
#define BA_VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 0x0060
#define B16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 0x0060
#define LSb32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 0
#define LSb16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 0
#define bVIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 1
#define MSK32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw 0x00000001
#define BA_VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 0x0060
#define B16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 0x0060
#define LSb32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 1
#define LSb16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 1
#define bVIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 1
#define MSK32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw 0x00000002
#define BA_VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 0x0060
#define B16VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 0x0060
#define LSb32VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 2
#define LSb16VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 2
#define bVIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 1
#define MSK32VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw 0x00000004
///////////////////////////////////////////////////////////
typedef struct SIE_VIP_ctrl {
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_dvi_wc_clr(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_dvi_wc_clr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_dvi_wc_clr(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_dvi_wc_clr(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_dvi_wc_st(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_dvi_wc_st(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_dvi_wc_st(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_dvi_wc_st(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_dvi_wc_packsel(r32) _BFGET_(r32, 3, 2)
#define SET32VIP_ctrl_dvi_wc_packsel(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16VIP_ctrl_dvi_wc_packsel(r16) _BFGET_(r16, 3, 2)
#define SET16VIP_ctrl_dvi_wc_packsel(r16,v) _BFSET_(r16, 3, 2,v)
UNSG32 u_dvi_wc_clr : 1;
UNSG32 u_dvi_wc_st : 1;
UNSG32 u_dvi_wc_packsel : 2;
UNSG32 RSVDx0_b4 : 28;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_dvi_wc_pixtot(r32) _BFGET_(r32,31, 0)
#define SET32VIP_ctrl_dvi_wc_pixtot(r32,v) _BFSET_(r32,31, 0,v)
UNSG32 u_dvi_wc_pixtot : 32;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_vbi_wc_clr(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_vbi_wc_clr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_vbi_wc_clr(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_vbi_wc_clr(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_vbi_wc_st(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_vbi_wc_st(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_vbi_wc_st(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_vbi_wc_st(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_vbi_wc_packsel(r32) _BFGET_(r32, 3, 2)
#define SET32VIP_ctrl_vbi_wc_packsel(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16VIP_ctrl_vbi_wc_packsel(r16) _BFGET_(r16, 3, 2)
#define SET16VIP_ctrl_vbi_wc_packsel(r16,v) _BFSET_(r16, 3, 2,v)
UNSG32 u_vbi_wc_clr : 1;
UNSG32 u_vbi_wc_st : 1;
UNSG32 u_vbi_wc_packsel : 2;
UNSG32 RSVDx8_b4 : 28;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_vbi_wc_pixtot(r32) _BFGET_(r32,31, 0)
#define SET32VIP_ctrl_vbi_wc_pixtot(r32,v) _BFSET_(r32,31, 0,v)
UNSG32 u_vbi_wc_pixtot : 32;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_sd_wc_clr(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_sd_wc_clr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_sd_wc_clr(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_sd_wc_clr(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_sd_wc_st(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_sd_wc_st(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_sd_wc_st(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_sd_wc_st(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_sd_wc_packsel(r32) _BFGET_(r32, 3, 2)
#define SET32VIP_ctrl_sd_wc_packsel(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16VIP_ctrl_sd_wc_packsel(r16) _BFGET_(r16, 3, 2)
#define SET16VIP_ctrl_sd_wc_packsel(r16,v) _BFSET_(r16, 3, 2,v)
UNSG32 u_sd_wc_clr : 1;
UNSG32 u_sd_wc_st : 1;
UNSG32 u_sd_wc_packsel : 2;
UNSG32 RSVDx10_b4 : 28;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_sd_wc_pixtot(r32) _BFGET_(r32,31, 0)
#define SET32VIP_ctrl_sd_wc_pixtot(r32,v) _BFSET_(r32,31, 0,v)
UNSG32 u_sd_wc_pixtot : 32;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_sd_rc_clr(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_sd_rc_clr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_sd_rc_clr(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_sd_rc_clr(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_sd_rc_st(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_sd_rc_st(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_sd_rc_st(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_sd_rc_st(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_sd_rc_packsel(r32) _BFGET_(r32, 3, 2)
#define SET32VIP_ctrl_sd_rc_packsel(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16VIP_ctrl_sd_rc_packsel(r16) _BFGET_(r16, 3, 2)
#define SET16VIP_ctrl_sd_rc_packsel(r16,v) _BFSET_(r16, 3, 2,v)
UNSG32 u_sd_rc_clr : 1;
UNSG32 u_sd_rc_st : 1;
UNSG32 u_sd_rc_packsel : 2;
UNSG32 RSVDx18_b4 : 28;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_sd_rc_pixtot(r32) _BFGET_(r32,31, 0)
#define SET32VIP_ctrl_sd_rc_pixtot(r32,v) _BFSET_(r32,31, 0,v)
UNSG32 u_sd_rc_pixtot : 32;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_fl_sd_rclr(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_fl_sd_rclr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_fl_sd_rclr(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_fl_sd_rclr(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_fl_sd_wclr(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_fl_sd_wclr(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_fl_sd_wclr(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_fl_sd_wclr(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_fl_dvi_wclr(r32) _BFGET_(r32, 2, 2)
#define SET32VIP_ctrl_fl_dvi_wclr(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16VIP_ctrl_fl_dvi_wclr(r16) _BFGET_(r16, 2, 2)
#define SET16VIP_ctrl_fl_dvi_wclr(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32VIP_ctrl_fl_vbi_wclr(r32) _BFGET_(r32, 3, 3)
#define SET32VIP_ctrl_fl_vbi_wclr(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16VIP_ctrl_fl_vbi_wclr(r16) _BFGET_(r16, 3, 3)
#define SET16VIP_ctrl_fl_vbi_wclr(r16,v) _BFSET_(r16, 3, 3,v)
UNSG32 u_fl_sd_rclr : 1;
UNSG32 u_fl_sd_wclr : 1;
UNSG32 u_fl_dvi_wclr : 1;
UNSG32 u_fl_vbi_wclr : 1;
UNSG32 RSVDx20_b4 : 28;
///////////////////////////////////////////////////////////
SIE_DVI_FE_BE ie_DVI_FE_BE;
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_SCL_CLKEN_CTRL_DVI(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_SCL_CLKEN_CTRL_DVI(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_SCL_CLKEN_CTRL_DVI(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_SCL_CLKEN_CTRL_DVI(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_SCL_CLKEN_CTRL {\
UNSG32 uSCL_CLKEN_CTRL_DVI : 1;\
UNSG32 RSVDx34_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_SCL_CLKEN_CTRL;
struct w32VIP_ctrl_SCL_CLKEN_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_DVI_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32VIP_ctrl_DVI_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16VIP_ctrl_DVI_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16VIP_ctrl_DVI_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32VIP_ctrl_DVI_LSIZE {\
UNSG32 uDVI_LSIZE_lsize : 9;\
UNSG32 RSVDx38_b9 : 23;\
}
union { UNSG32 u32VIP_ctrl_DVI_LSIZE;
struct w32VIP_ctrl_DVI_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_OFRST_SEL_DVI(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_OFRST_SEL_DVI(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_OFRST_SEL_DVI(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_OFRST_SEL_DVI(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_OFRST_SEL {\
UNSG32 uOFRST_SEL_DVI : 1;\
UNSG32 RSVDx3C_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_OFRST_SEL;
struct w32VIP_ctrl_OFRST_SEL;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_OFRST_SW_DVI(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_OFRST_SW_DVI(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_OFRST_SW_DVI(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_OFRST_SW_DVI(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_OFRST_SW {\
UNSG32 uOFRST_SW_DVI : 1;\
UNSG32 RSVDx40_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_OFRST_SW;
struct w32VIP_ctrl_OFRST_SW;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_intr_sel_DVI(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_intr_sel_DVI(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_intr_sel_DVI(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_intr_sel_DVI(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_intr_sel {\
UNSG32 uintr_sel_DVI : 1;\
UNSG32 RSVDx44_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_intr_sel;
struct w32VIP_ctrl_intr_sel;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_vbi_vde_cnt_VBI(r32) _BFGET_(r32, 7, 0)
#define SET32VIP_ctrl_vbi_vde_cnt_VBI(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16VIP_ctrl_vbi_vde_cnt_VBI(r16) _BFGET_(r16, 7, 0)
#define SET16VIP_ctrl_vbi_vde_cnt_VBI(r16,v) _BFSET_(r16, 7, 0,v)
#define w32VIP_ctrl_vbi_vde_cnt {\
UNSG32 uvbi_vde_cnt_VBI : 8;\
UNSG32 RSVDx48_b8 : 24;\
}
union { UNSG32 u32VIP_ctrl_vbi_vde_cnt;
struct w32VIP_ctrl_vbi_vde_cnt;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_VBI_CTRL_data_sel(r32) _BFGET_(r32, 2, 0)
#define SET32VIP_ctrl_VBI_CTRL_data_sel(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16VIP_ctrl_VBI_CTRL_data_sel(r16) _BFGET_(r16, 2, 0)
#define SET16VIP_ctrl_VBI_CTRL_data_sel(r16,v) _BFSET_(r16, 2, 0,v)
#define w32VIP_ctrl_VBI_CTRL {\
UNSG32 uVBI_CTRL_data_sel : 3;\
UNSG32 RSVDx4C_b3 : 29;\
}
union { UNSG32 u32VIP_ctrl_VBI_CTRL;
struct w32VIP_ctrl_VBI_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_INTR_EN_SD_WR(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_INTR_EN_SD_WR(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_INTR_EN_SD_WR(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_INTR_EN_SD_WR(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_INTR_EN_SD_RD(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_INTR_EN_SD_RD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_INTR_EN_SD_RD(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_INTR_EN_SD_RD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_INTR_EN_SD_ERR(r32) _BFGET_(r32, 2, 2)
#define SET32VIP_ctrl_INTR_EN_SD_ERR(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16VIP_ctrl_INTR_EN_SD_ERR(r16) _BFGET_(r16, 2, 2)
#define SET16VIP_ctrl_INTR_EN_SD_ERR(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32VIP_ctrl_INTR_EN_VBI(r32) _BFGET_(r32, 3, 3)
#define SET32VIP_ctrl_INTR_EN_VBI(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16VIP_ctrl_INTR_EN_VBI(r16) _BFGET_(r16, 3, 3)
#define SET16VIP_ctrl_INTR_EN_VBI(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32VIP_ctrl_INTR_EN_DVI(r32) _BFGET_(r32, 4, 4)
#define SET32VIP_ctrl_INTR_EN_DVI(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16VIP_ctrl_INTR_EN_DVI(r16) _BFGET_(r16, 4, 4)
#define SET16VIP_ctrl_INTR_EN_DVI(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32VIP_ctrl_INTR_EN_SD_SIG_ERR(r32) _BFGET_(r32, 5, 5)
#define SET32VIP_ctrl_INTR_EN_SD_SIG_ERR(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16VIP_ctrl_INTR_EN_SD_SIG_ERR(r16) _BFGET_(r16, 5, 5)
#define SET16VIP_ctrl_INTR_EN_SD_SIG_ERR(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32VIP_ctrl_INTR_EN_BCM_INVALID(r32) _BFGET_(r32, 6, 6)
#define SET32VIP_ctrl_INTR_EN_BCM_INVALID(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16VIP_ctrl_INTR_EN_BCM_INVALID(r16) _BFGET_(r16, 6, 6)
#define SET16VIP_ctrl_INTR_EN_BCM_INVALID(r16,v) _BFSET_(r16, 6, 6,v)
#define w32VIP_ctrl_INTR_EN {\
UNSG32 uINTR_EN_SD_WR : 1;\
UNSG32 uINTR_EN_SD_RD : 1;\
UNSG32 uINTR_EN_SD_ERR : 1;\
UNSG32 uINTR_EN_VBI : 1;\
UNSG32 uINTR_EN_DVI : 1;\
UNSG32 uINTR_EN_SD_SIG_ERR : 1;\
UNSG32 uINTR_EN_BCM_INVALID : 1;\
UNSG32 RSVDx50_b7 : 25;\
}
union { UNSG32 u32VIP_ctrl_INTR_EN;
struct w32VIP_ctrl_INTR_EN;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_SIG_CTRL_en(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_SIG_CTRL_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_SIG_CTRL_en(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_SIG_CTRL_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_SIG_CTRL {\
UNSG32 uSIG_CTRL_en : 1;\
UNSG32 RSVDx54_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_SIG_CTRL;
struct w32VIP_ctrl_SIG_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_SIG_pix_cnt_pix_cnt(r32) _BFGET_(r32,31, 0)
#define SET32VIP_ctrl_SIG_pix_cnt_pix_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32VIP_ctrl_SIG_pix_cnt {\
UNSG32 uSIG_pix_cnt_pix_cnt : 32;\
}
union { UNSG32 u32VIP_ctrl_SIG_pix_cnt;
struct w32VIP_ctrl_SIG_pix_cnt;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_SIG_STS_err(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_SIG_STS_err(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_SIG_STS_err(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_SIG_STS_err(r16,v) _BFSET_(r16, 0, 0,v)
#define w32VIP_ctrl_SIG_STS {\
UNSG32 uSIG_STS_err : 1;\
UNSG32 RSVDx5C_b1 : 31;\
}
union { UNSG32 u32VIP_ctrl_SIG_STS;
struct w32VIP_ctrl_SIG_STS;
};
///////////////////////////////////////////////////////////
#define GET32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw(r32) _BFGET_(r32, 0, 0)
#define SET32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw(r16) _BFGET_(r16, 0, 0)
#define SET16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_clr_hw(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw(r32) _BFGET_(r32, 1, 1)
#define SET32VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw(r16) _BFGET_(r16, 1, 1)
#define SET16VIP_ctrl_VIP_PIPE_CLR_dvi_wc_st_hw(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw(r32) _BFGET_(r32, 2, 2)
#define SET32VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw(r16) _BFGET_(r16, 2, 2)
#define SET16VIP_ctrl_VIP_PIPE_CLR_fl_dvi_wclr_hw(r16,v) _BFSET_(r16, 2, 2,v)
#define w32VIP_ctrl_VIP_PIPE_CLR {\
UNSG32 uVIP_PIPE_CLR_dvi_wc_clr_hw : 1;\
UNSG32 uVIP_PIPE_CLR_dvi_wc_st_hw : 1;\
UNSG32 uVIP_PIPE_CLR_fl_dvi_wclr_hw : 1;\
UNSG32 RSVDx60_b3 : 29;\
}
union { UNSG32 u32VIP_ctrl_VIP_PIPE_CLR;
struct w32VIP_ctrl_VIP_PIPE_CLR;
};
///////////////////////////////////////////////////////////
} SIE_VIP_ctrl;
typedef union T32VIP_ctrl_SCL_CLKEN_CTRL
{ UNSG32 u32;
struct w32VIP_ctrl_SCL_CLKEN_CTRL;
} T32VIP_ctrl_SCL_CLKEN_CTRL;
typedef union T32VIP_ctrl_DVI_LSIZE
{ UNSG32 u32;
struct w32VIP_ctrl_DVI_LSIZE;
} T32VIP_ctrl_DVI_LSIZE;
typedef union T32VIP_ctrl_OFRST_SEL
{ UNSG32 u32;
struct w32VIP_ctrl_OFRST_SEL;
} T32VIP_ctrl_OFRST_SEL;
typedef union T32VIP_ctrl_OFRST_SW
{ UNSG32 u32;
struct w32VIP_ctrl_OFRST_SW;
} T32VIP_ctrl_OFRST_SW;
typedef union T32VIP_ctrl_intr_sel
{ UNSG32 u32;
struct w32VIP_ctrl_intr_sel;
} T32VIP_ctrl_intr_sel;
typedef union T32VIP_ctrl_vbi_vde_cnt
{ UNSG32 u32;
struct w32VIP_ctrl_vbi_vde_cnt;
} T32VIP_ctrl_vbi_vde_cnt;
typedef union T32VIP_ctrl_VBI_CTRL
{ UNSG32 u32;
struct w32VIP_ctrl_VBI_CTRL;
} T32VIP_ctrl_VBI_CTRL;
typedef union T32VIP_ctrl_INTR_EN
{ UNSG32 u32;
struct w32VIP_ctrl_INTR_EN;
} T32VIP_ctrl_INTR_EN;
typedef union T32VIP_ctrl_SIG_CTRL
{ UNSG32 u32;
struct w32VIP_ctrl_SIG_CTRL;
} T32VIP_ctrl_SIG_CTRL;
typedef union T32VIP_ctrl_SIG_pix_cnt
{ UNSG32 u32;
struct w32VIP_ctrl_SIG_pix_cnt;
} T32VIP_ctrl_SIG_pix_cnt;
typedef union T32VIP_ctrl_SIG_STS
{ UNSG32 u32;
struct w32VIP_ctrl_SIG_STS;
} T32VIP_ctrl_SIG_STS;
typedef union T32VIP_ctrl_VIP_PIPE_CLR
{ UNSG32 u32;
struct w32VIP_ctrl_VIP_PIPE_CLR;
} T32VIP_ctrl_VIP_PIPE_CLR;
///////////////////////////////////////////////////////////
typedef union TVIP_ctrl_SCL_CLKEN_CTRL
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_SCL_CLKEN_CTRL;
};
} TVIP_ctrl_SCL_CLKEN_CTRL;
typedef union TVIP_ctrl_DVI_LSIZE
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_DVI_LSIZE;
};
} TVIP_ctrl_DVI_LSIZE;
typedef union TVIP_ctrl_OFRST_SEL
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_OFRST_SEL;
};
} TVIP_ctrl_OFRST_SEL;
typedef union TVIP_ctrl_OFRST_SW
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_OFRST_SW;
};
} TVIP_ctrl_OFRST_SW;
typedef union TVIP_ctrl_intr_sel
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_intr_sel;
};
} TVIP_ctrl_intr_sel;
typedef union TVIP_ctrl_vbi_vde_cnt
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_vbi_vde_cnt;
};
} TVIP_ctrl_vbi_vde_cnt;
typedef union TVIP_ctrl_VBI_CTRL
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_VBI_CTRL;
};
} TVIP_ctrl_VBI_CTRL;
typedef union TVIP_ctrl_INTR_EN
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_INTR_EN;
};
} TVIP_ctrl_INTR_EN;
typedef union TVIP_ctrl_SIG_CTRL
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_SIG_CTRL;
};
} TVIP_ctrl_SIG_CTRL;
typedef union TVIP_ctrl_SIG_pix_cnt
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_SIG_pix_cnt;
};
} TVIP_ctrl_SIG_pix_cnt;
typedef union TVIP_ctrl_SIG_STS
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_SIG_STS;
};
} TVIP_ctrl_SIG_STS;
typedef union TVIP_ctrl_VIP_PIPE_CLR
{ UNSG32 u32[1];
struct {
struct w32VIP_ctrl_VIP_PIPE_CLR;
};
} TVIP_ctrl_VIP_PIPE_CLR;
///////////////////////////////////////////////////////////
SIGN32 VIP_ctrl_drvrd(SIE_VIP_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 VIP_ctrl_drvwr(SIE_VIP_ctrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void VIP_ctrl_reset(SIE_VIP_ctrl *p);
SIGN32 VIP_ctrl_cmp (SIE_VIP_ctrl *p, SIE_VIP_ctrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define VIP_ctrl_check(p,pie,pfx,hLOG) VIP_ctrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define VIP_ctrl_print(p, pfx,hLOG) VIP_ctrl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: VIP_ctrl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE Vpp biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (R-)
/// # 0x00000 cfgReg
/// $VPP_REG cfgReg MEM
/// ###
/// * VPP Register Space, 32KB. (Hier:3)
/// * K2 uses 13 bits for address. In Berlin, K2 block registers are aligned on a 32-bit boundary. So, 15 address bits would be required to address the entire K2 block's address space.
/// ###
/// @ 0x10000 (P)
/// # 0x10000 cpcb0Clk
/// $CLK cpcb0Clk REG
/// ###
/// * vClk0 is driven as cpcb0Clkx and with vClk0 as input, a divider-cum-mux is implemented to generate cpcb0Clk. These set of controls control the cpcb0Clk.
/// ###
/// @ 0x10004 (P)
/// # 0x10004 cpcb1Clk
/// $CLK cpcb1Clk REG
/// ###
/// * vClk1 is driven as cpcb1Clkx and with vClk1 as input, a divider-cum-mux is implemented to generate cpcb1Clk. These set of controls control the cpcb1Clk.
/// ###
/// @ 0x10008 (P)
/// # 0x10008 cpcb2Clk
/// $CLK cpcb2Clk REG
/// ###
/// * vClk2 is driven as cpcb2Clkx and with vClk2 as input, a divider-cum-mux is implemented to generate cpcb2Clk. These set of controls control the cpcb2Clk.
/// ###
/// @ 0x1000C (P)
/// # 0x1000C FE_BE
/// $FE_BE FE_BE REG
/// ###
/// * All the BE channel registers of fe_top
/// ###
/// @ 0x1001C VP_CLKEN_CTRL (P)
/// %unsigned 1 toggle 0x0
/// ###
/// * 1: Toggle the clken to vp_top.
/// * 0: clken to vp_top is not toggled.
/// * Make this bit 1 for interlaced inputs. Make it zero for progressive inputs.
/// ###
/// %unsigned 1 diW 0x0
/// ###
/// * 1: Take care of rdy from diW while generating clken to vp_top
/// * 0 : don't consider rdy from diW
/// * Make this bit 1 whenever write client of DI is turned-on. Otherwise, make it zero. In general, this bit has to be made 1 when 3D DI is on for interlaced inputs or 3D VNR is on for progressive inputs.
/// ###
/// %unsigned 1 diR0 0x0
/// ###
/// * 1: Take care of rdy from diR0 while generating clken to vp_top
/// * 0 : don't consider rdy from diR0
/// * Make this bit 1 whenever read client0 of DI is turned-on. Otherwise, make it zero. In general, this bit has to be made 1 when 3D DI is on for interlaced inputs or 3D VNR is on for progressive inputs.
/// ###
/// %unsigned 1 diR1 0x0
/// ###
/// * 1: Take care of rdy from diR1 while generating clken to vp_top
/// * 0 : don't consider rdy from diR1
/// * Make this bit 1 whenever read client1 of DI is turned-on. Otherwise, make it zero. In general, this bit has to be made 1 when 3D DI is on for interlaced inputs.
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x10020 FE_MAIN_CTRL (P)
/// %unsigned 1 rff 0x0
/// ###
/// * Controls the “rff”(Repeat Field Flag) input of DI.
/// * TODO: How it is used by DI?
/// ###
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal at the input of VP_TOP.
/// ###
/// %unsigned 1 fld_mode 0x0
/// ###
/// * 0: s/w mode – s/w to proram value at every start (VBI)
/// * 1: h/w mode – h/w to toggle at every start(VBI)
/// ###
/// %unsigned 1 fld_init 0x0
/// ###
/// * Init value which will be talen for fld signal corresponding to first start programming
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x10024 FE_PIP_CTRL (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal at the input of PIP scaler.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x10028 FE_OSD_CTRL (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal at the input of OSD scaler.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x1002C FE_PG_CTRL (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal at the input of PG scaler.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x10030 CPCB0_FLD (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal to CPCB0 interlacer.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x10034 CPCB2_FLD (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal to CPCB2 interlacer.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x10038 FE_PAT_SEL (P)
/// %unsigned 1 pat_sel 0x0
/// ###
/// * Pattern Generator sits at the input of VP_TOP.
/// * 1: Feed Main channel with Pattern Generator output.
/// * 0: Main channel is fed with data from DRAM.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x1003C mainW (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// %% 30 # Stuffing bits...
/// @ 0x10040 mainR (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// %unsigned 1 packsel 0x0
/// %% 29 # Stuffing bits...
/// @ 0x10044 pipW (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// %% 30 # Stuffing bits...
/// @ 0x10048 pipR (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// %unsigned 1 packsel 0x0
/// %% 29 # Stuffing bits...
/// @ 0x1004C auxW (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// %% 30 # Stuffing bits...
/// @ 0x10050 auxR (P-)
/// %unsigned 1 start 0x0
/// ###
/// * Start bit for the respective clients.
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %unsigned 1 clear 0x0
/// ###
/// * 0 – Don't clear, normal state.
/// * 1 – Clear the asynchronous FIFO between the respective client and dHub.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x10054 rst (P)
/// %unsigned 1 lvds_phy 0x1
/// ###
/// * Reserved for future use
/// ###
/// %unsigned 1 be_ss 0x1
/// ###
/// * 0 – Reset the VPP BE pipe-line (CPCB, HDMI-Tx, Video encoder, etc.)
/// * 1 – reset de-asserted, normal state.
/// ###
/// %unsigned 1 vp_top 0x1
/// ###
/// * 0 – Reset the VP_TOP module (VNR+DI+DET)
/// * 1 – reset de-asserted, normal state.
/// ###
/// %unsigned 1 hdmi_tx 0x1
/// ###
/// * 0 – Reset the HDMI-TX module alone
/// * 1 – reset de-asserted, normal state.
/// ###
/// %unsigned 1 video_enc 0x1
/// ###
/// * 0 – Reset the Video Encoder module alone
/// * 1 – reset de-asserted, normal state.
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x10058 (P)
/// # 0x10058 VDAC_ctrl
/// $VDAC_ctrl VDAC_ctrl REG
/// @ 0x10064 (P)
/// # 0x10064 VDAC_sts
/// $VDAC_sts VDAC_sts REG
/// ###
/// * Control & status for all the 6 DACs
/// ###
/// @ 0x10068 (P)
/// # 0x10068 HDMI_ctrl
/// $HDMI_ctrl HDMI_ctrl REG
/// @ 0x10078 (P)
/// # 0x10078 HDMI_sts
/// $HDMI_sts HDMI_sts REG
/// ###
/// * Control & status for HDMI PHY
/// ###
/// @ 0x1007C regIfCtrl (P)
/// %unsigned 8 mwrWidth 0x1
/// ###
/// * Specifies the width of the MWR pulse (in terms of sysClks) to K2 blocks. CMU memories are loaded with MWR pulse directly. CMU operates on CPCB0 clock. Control this register so that the MWR pulse generated in vppSysClk domain could be sampled by CPCB0 clock.
/// ###
/// %unsigned 8 hold 0x1
/// ###
/// * Specifies the time (in terms of vppSysClks) between K2 read data mux output to sample point in VPP BIU.
/// * In case of timing closure issues, increase this delay, and accordingly set multi-cycle path constraint in SDC. TODO: Specify the value, to be written for software, after Berlin-B0 timing closure.
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x10080 MAIN_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// %% 23 # Stuffing bits...
/// @ 0x10084 PIP_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// %% 23 # Stuffing bits...
/// @ 0x10088 OSD_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// %% 23 # Stuffing bits...
/// @ 0x1008C PG_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// %% 23 # Stuffing bits...
/// @ 0x10090 AUX_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// ###
/// * Specifies the number of line buffer locations required to store one input (or scaled) line. How to calculate:
/// * If(hscaler before vscaler) hres = ohres;
/// * else hres = ihres;
/// * TS = Is 24 bit per pixel ? 5 : 8;
/// * lsize = ceil ( hres / (TS+1) )
/// ###
/// %% 23 # Stuffing bits...
/// @ 0x10094 vpIn_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the input of VP_TOP (3D DI+NR). it should be programmed with (main_ivres*main_ihres).
/// ###
/// @ 0x10098 vpOut_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the output of VP_TOP (3D DI+NR), or at the input of Main Scaler.
/// * When DI is not enabled, it should be programmed with (ivres*ihres).
/// * When DI is enabled, it should be programmed with (2*ivres*ihres).
/// ###
/// @ 0x1009C pip_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the input of PIP Scaler. It should be programmed with (pip_ivres*pip_ihres).
/// ###
/// @ 0x100A0 osd_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the input of OSD Scaler. It should be programmed with (osd_ivres*osd_ihres).
/// ###
/// @ 0x100A4 pg_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the input of PG Scaler. It should be programmed with (pg_ivres*pg_ihres).
/// ###
/// @ 0x100A8 diW_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected from DI to its write client. This is used to generate flush in diW client to write the partially formed 64-bit data (if any) to DDR.
/// * Should be programmed with (ivres+1)*ihres.
/// ###
/// @ 0x100AC diR_word (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of 64-bit words that have to be fetched from DDR. This is used to generate done so as to enable DI. Should be programmed as:
/// * ceil( (((ivres+1)*ihres) * (fb_mode?26:20)) / 64 )
/// ###
/// @ 0x100B0 mainW_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected from Main scaler to its write client in off-line scaler operation. This is used to generate flush in mainW client to write the partially formed 64-bit data (if any) to DDR.
/// * Should be programmed with (main_ovres*main_ohres).
/// ###
/// @ 0x100B4 mainR_word (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of 64-bit words that have to be fetched from DDR for mainR. In off-line scaler mode, CPCB gets data from mainR. Should be programmed as:
/// * ceil( main_ohres*main_ovres*16 / 64 )
/// ###
/// @ 0x100B8 pipW_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected from PIP scaler to its write client in off-line scaler operation. This is used to generate flush in pipW client to write the partially formed 64-bit data (if any) to DDR.
/// * Should be programmed with (pip_ovres*pip_ohres).
/// ###
/// @ 0x100BC pipR_word (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of 64-bit words that have to be fetched from DDR for pipR. In off-line scaler mode, CPCB gets data from pipR. Should be programmed as:
/// * ceil( pip_ohres*pip_ovres*16 / 64 )
/// ###
/// @ 0x100C0 auxW_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected from AUX scaler to its write client. This is used to generate flush in auxW client to write the partially formed 64-bit data (if any) to DDR.
/// * Should be programmed with (ovres*ohres).
/// ###
/// @ 0x100C4 auxR_word (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of 64-bit words that have to be fetched from DDR for auxR. For Aux, CPCB always get data from auxR. Should be programmed as:
/// * ceil( ohres*ovres*16 / 64 )
/// ###
/// @ 0x100C8 main_ols (P)
/// %unsigned 1 en 0x0
/// ###
/// * Controls off-line scaler mode for Main channel.
/// * 0 – Main Scaler works in in-line mode (i.e., read data from DRAM, scale it, and CPCB reads from scaler)
/// * 1 – Main scaler works in off-line mode (i.e., read data from DRAM, and write back the scaled data to DRAM. CPCB reads data from DRAM).
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x100CC pip_ols (P)
/// %unsigned 1 en 0x0
/// ###
/// * Controls off-line scaler mode for PIP channel.
/// * 0 – PIP Scaler works in in-line mode (i.e., read data from DRAM, scale it, and CPCB reads from scaler)
/// * 1 – PIP scaler works in off-line mode (i.e., read data from DRAM, and write back the scaled data to DRAM. CPCB reads data from DRAM).
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x100D0 enc_hsvs_sel (P)
/// %unsigned 1 sel 0x1
/// ###
/// * Selects which DAC channel's HS/VS to output
/// * 0 : selects HS/VS of DAC channel0 (DAC0,1,2)
/// * 1: selects HS/VS of DAC channel 1(DAC3,4,5)
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x100D4 CPCB_FIFO_UF (WOC-)
/// %unsigned 1 cpcb0_0 0x0
/// %unsigned 1 cpcb0_1 0x0
/// %unsigned 1 cpcb0_2 0x0
/// %unsigned 1 cpcb0_3 0x0
/// %unsigned 1 cpcb0_4 0x0
/// %unsigned 1 cpcb0_5 0x0
/// %unsigned 1 cpcb0_6 0x0
/// %unsigned 1 cpcb1_0 0x0
/// %unsigned 1 cpcb1_1 0x0
/// %unsigned 1 cpcb1_2 0x0
/// %unsigned 1 cpcb1_3 0x0
/// %unsigned 1 cpcb1_4 0x0
/// %unsigned 1 cpcb1_5 0x0
/// %unsigned 1 cpcb1_6 0x0
/// %unsigned 1 cpcb2_0 0x0
/// ###
/// * 1: indicates underflow happened since last clear.
/// * 0 : indicates that never underflow happened.
/// * Software shall write 1 to clear particular bit.
/// ###
/// %% 17 # Stuffing bits...
/// @ 0x100D8 (P)
/// # 0x100D8 VP_TG
/// $TG VP_TG REG
/// ###
/// * dummy TG for 3D DI (Main Channel).
/// ###
/// @ 0x10108 (W-)
/// # # Stuffing bytes...
/// %% 6080
/// @ 0x10400 (P)
/// # 0x10400 LDR
/// $LDR LDR REG
/// ###
/// * Channel Loder related registers.
/// ###
/// @ 0x12C00 HDMI2DVAO (P)
/// %unsigned 1 en 0x0
/// ###
/// * Selects between HDMI2DVAO and TTL30 outputs (Only for FPGA)
/// * 0 : DVO outputs TTL30 data
/// * 1: DVO outputs HDMI path data. The output of HDMI-TX core is fed to HDMI_RX and the output of HDMI-RX core is driven on DVO output.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C04 VP_DMX_CTRL (P)
/// %unsigned 1 sw_sel 0x0
/// ###
/// * Selects between hardware computed hres, ht, vres, vt, ivt or software programmed values.
/// * 0 : Hardware computed values are used.
/// * 1: Software programmed values are used.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C08 VP_DMX_HRES (P)
/// %unsigned 12 hres 0x0
/// ###
/// * Active no. of horizontal pixels at the input of VP. If actual resolution is 720, this register shall be programmed with 719.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x12C0C VP_DMX_HT (P)
/// %unsigned 12 ht 0x0
/// ###
/// * Total horizontal pixels at the input of VP. This shall be programmed with the htotal programmed in the VP TG -1.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x12C10 VP_DMX_VRES (P)
/// %unsigned 12 vres 0x0
/// ###
/// * Active vertical lines at the input of VP -1.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x12C14 VP_DMX_VT (P)
/// %unsigned 12 vt 0x0
/// ###
/// * 2*ivtotal-1. The ivtotal depends on the values programmed in VP TG.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x12C18 VP_DMX_IVT (P)
/// %unsigned 12 ivt 0x0
/// ###
/// * ivtotal-1. The ivtotal depends on the values programmed in VP TG.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x12C1C CPCB0_PL_EN (P)
/// %unsigned 1 Main 0x0
/// %unsigned 1 PIP 0x0
/// %unsigned 1 IG 0x0
/// %unsigned 1 PG 0x0
/// %unsigned 1 Cursor 0x0
/// %unsigned 1 MOSD 0x0
/// %unsigned 1 BG 0x0
/// ###
/// * 1: The particular channel is connected to CPCB0's respective plane input.
/// * Main -> pl-1, PIP -> pl-2, IG -> pl-3, PG -> pl-3a, Cursor->pl-3b, MOSD -> pl-3c and BG -> pl-3d.
/// * 0: The particular channel is not connected to CPCB0.
/// * Note: CPCB0_PL_EN & CPCB1_PL_EN are mutually exclusive, the same channel can't be connected to 2 CPCBs.
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x12C20 CPCB1_PL_EN (P)
/// %unsigned 1 Main 0x0
/// %unsigned 1 PIP 0x0
/// %unsigned 1 IG 0x0
/// %unsigned 1 PG 0x0
/// %unsigned 1 Cursor 0x0
/// %unsigned 1 MOSD 0x0
/// %unsigned 1 BG 0x0
/// ###
/// * 1: The particular channel is connected to CPCB1's respective plane input.
/// * Main -> pl-1, PIP -> pl-2, IG -> pl-3, PG -> pl-3a, Cursor->pl-3b, MOSD -> pl-3c and BG -> pl-3d.
/// * 0: The particular channel is not connected to CPCB1.
/// * Note: CPCB0_PL_EN & CPCB1_PL_EN are mutually exclusive, the same channel can't be connected to 2 CPCBs.
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x12C24 MAIN_WCLIENT (P)
/// %unsigned 1 en 0x0
/// ###
/// * Enables the write to Main Scaler's write client in in-line mode. Make this bit 1 for the last frame of in-line scaling (the frame before moving to off-line scaling). This is to facilitate smooth in-line to off-line transition.
/// * 0 – No write generated to write client in in-line mode.
/// * 1 – send the scaler output to write client (the data from scaler is pulled at the CPCB rate).
/// * This bit is don't care when “en” bit of main_ols register is 1.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C28 PIP_WCLIENT (P)
/// %unsigned 1 en 0x0
/// ###
/// * Enables the write to PIP Scaler's write client in in-line mode. Make this bit 1 for the last frame of in-line scaling (the frame before moving to off-line scaling). This is to facilitate smooth in-line to off-line transition.
/// * 0 – No write generated to write client in in-line mode.
/// * 1 – send the scaler output to write client (the data from scaler is pulled at the CPCB rate).
/// * This bit is don't care when “en” bit of pip_ols register is 1.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C2C DIW_CLIENT (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// ###
/// * Start bit for the Deinterlacer write client (diW).
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12C30 DIR0_CLIENT (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// ###
/// * Start bit for the R0 Deinterlacer read client (diR0).
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12C34 DIR1_CLIENT (P-)
/// %unsigned 1 start 0x0
/// %unsigned 1 clear 0x0
/// ###
/// * Start bit for the R1 Deinterlacer read client (diR1)
/// * 0 – No effect on hardware.
/// * 1 – start the client.
/// * The write 1 to this register is used to kick the hardware.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12C38 SD_TT_CLIENT (P)
/// %unsigned 1 enable 0x0
/// %unsigned 1 clear 0x0
/// ###
/// * Enable bit for the SD TTXT (teletext) read client
/// * 0 – Don't request data from dHub
/// * 1 – start requesting data from dHub.
/// * SW typically needs to enable it only at the start as part of initialization.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12C3C SD_TT_BYTE (P)
/// %unsigned 32 tot 0x0
/// ###
/// * Specifies the total number of (TT bytes per line or per frame) -1; used by HW to flush the partially consumed 64-bit data in TT read client.
/// * Whether this number is per line or per frame, depends on the TT packet data packing in DRAM.
/// * If the SW prefers to pack the TT bytes of adjacent packets with no holes, then program “tot” = TT bytes per frame
/// * If the SW prefers to start each TT packet on 64-byte boundary, then program “tot” = TT bytes per line.
/// ###
/// @ 0x12C40 DAC_RAMP_CTRL (P)
/// %unsigned 12 start 0x0
/// ###
/// * Start value for the Ramp generator.
/// * Ramp starts at “start” code and stops at “stop” code. It increases by 1 from “start”, reaches “stop” and then decrements by 1 to reach start – this repeats. DAC input stays at each code for step+1 no. of DAC clock cycles.
/// ###
/// %unsigned 12 stop 0xFFF
/// ###
/// * Stop value for the Ramp generator
/// ###
/// %unsigned 8 step 0x0
/// ###
/// * Step value for the Ramp generator. The code to the DAC is changed after (step+1) no. of DAC clock cycles.
/// ###
/// @ 0x12C44 DAC_TEST_CTRL (P)
/// %unsigned 2 sel 0x0
/// ###
/// * Controls the data driven to all 6 VDACs.
/// * 00: selects Video encoder output
/// * 01: selects ramp generator output (for ATE)
/// * 10: selects DRAM data (sine-wave)
/// * When, sel=10, DiR1 dHub channel is used for VDAC test purpose. Software should be aware of this.
/// * Each 16-bit is considered as one code (though only 12-bit of it is used). Software should prepare the data in DRAM in little-endian order and start the DiR1 dHub channel. It may use self-loop feature of dHub to repetitively fetch the same buffer.
/// * 11: reserved
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12C48 SCL_CLKEN_CTRL (P)
/// %unsigned 1 Main 0x0
/// %unsigned 1 PIP 0x0
/// %unsigned 1 IG 0x0
/// %unsigned 1 PG 0x0
/// %unsigned 1 AUX 0x1
/// %unsigned 1 MOSD 0x0
/// ###
/// * 0: Clock enable to scaler depends on the input FIFO status; scaler clken is deasserted when FE can't supply data to scaler.
/// * 1: Clock enable to scaler is always high.
/// * Since AUX scaler input always comes from CPCB0 – its clock enable should be 1 whenever it is being used.
/// ###
/// %% 26 # Stuffing bits...
/// @ 0x12C4C PAT_DNS_CTRL (P)
/// %unsigned 12 cblank 0x0
/// ###
/// * Blank value of chroma used for DNS in patgen path.
/// ###
/// %unsigned 1 enable 0x0
/// ###
/// * 0 – disable the down-sampler on patgen path
/// * 1 – enable the down-sampler on patgen path
/// ###
/// %% 19 # Stuffing bits...
/// @ 0x12C50 CPCB0_FLD_STS (R-)
/// %unsigned 1 fld 0x0
/// ###
/// * Status of the CPCB0 interlacer field signal.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C54 CPCB2_FLD_STS (R-)
/// %unsigned 1 fld 0x0
/// ###
/// * Status of the CPCB2 interlacer field signal.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C58 SD_TT_TEST (P)
/// %unsigned 8 data 0x0
/// ###
/// * 8-bit data to be sent to encoder as Teletext data.
/// ###
/// %unsigned 1 sel 0x0
/// ###
/// * 1: selects above “data” as TT input to encoder. Should only be used for Test purposes.
/// * 0: TT data comes from DRAM.
/// ###
/// %% 23 # Stuffing bits...
/// @ 0x12C5C DUMMY0 (P)
/// %unsigned 32 ctrl 0x0
/// ###
/// * Do nothing, dummy! May be used for ECOs.
/// ###
/// @ 0x12C60 DEBUG0 (R-)
/// %unsigned 8 diCnt 0x0
/// ###
/// * Deinterlacer checksum mismatch count; counter increments to 0xFF, and stays there. Cleared through Main plane clear enable.
/// * A non-zero value read indicates DI frame-buffer write/read mismatch.
/// ###
/// %unsigned 1 insert_frame 0x0
/// %unsigned 1 drop_frame 0x0
/// %unsigned 1 film_det_32 0x0
/// ###
/// * Flags from DI.
/// ###
/// %unsigned 1 vIFifoDone 0x0
/// ###
/// * 1: Main channel DMA is done at the input side of DEINT.
/// * 0: DMA is not done
/// ###
/// %unsigned 1 vOFifoDone 0x0
/// ###
/// * 1: Main channel DMA is done at the output side of DEINT.
/// * 0: DMA is not done.
/// ###
/// %unsigned 1 pipFifoDone 0x0
/// ###
/// * 1: PIP channel DMA is done.
/// * 0: DMA is not done.
/// ###
/// %unsigned 1 igFifoDone 0x0
/// ###
/// * 1: IG channel DMA is done.
/// * 0: DMA is not done.
/// ###
/// %unsigned 1 pgFifoDone 0x0
/// ###
/// * 1: PG channel DMA is done.
/// * 0: DMA is not done.
/// ###
/// %unsigned 1 mosdFifoDone 0x0
/// ###
/// * 1: MOSD channel DMA is done.
/// * 0: DMA is not done.
/// ###
/// %% 15 # Stuffing bits...
/// @ 0x12C64 MAIN_SCL_CROP (P)
/// %unsigned 3 ctrl 0x0
/// ###
/// * Crops the first pixel and/or last pixel before the H-scaler (after 422->444 conversion) of the Main channel.
/// * [0]: controls 1st pixel crop, 1: crop first pixel, 0: don't crop first pixel
/// * [1]: controls last pixel crop, 1: crop last pixel, 0: don't crop last pixel.
/// * [2]: controls last 2 pixel crop, 1: crop last two pixels, 0: don't crop last two pixels. Note: Setting bit[2] to 1 makes bit [1] don't care.
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x12C68 PIP_SCL_CROP (P)
/// %unsigned 3 ctrl 0x0
/// ###
/// * Crops the first pixel and/or last pixel before the H-scaler (after 422->444 conversion) of the PIP channel.
/// * [0]: controls 1st pixel crop, 1: crop first pixel, 0: don't crop first pixel
/// * [1]: controls last pixel crop, 1: crop last pixel, 0: don't crop last pixel.
/// * [2]: controls last two pixel crop, 1: crop last two pixels, 0: don't crop last two pixels. Note: Setting bit[2] to 1 makes bit[1] don't care.
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x12C6C PIP_LUMA_KEY (P)
/// %unsigned 1 en 0x0
/// %unsigned 8 min 0x0
/// %unsigned 8 max 0x0
/// ###
/// * Enable and min/max values for luma-key comparision.
/// ###
/// %% 15 # Stuffing bits...
/// @ 0x12C70 PIP_AL_IN (P)
/// %unsigned 8 hit_al 0x0
/// %unsigned 8 non_hit_al 0xFF
/// ###
/// * If input pixel luma to PIP scaler is in the range of min-max, alpha is hit_al; else alpha is non_hit_al
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x12C74 PIP_AL_OUT (P)
/// %unsigned 8 threshold 0x80
/// ###
/// * Threshold to compare the scaled alpha. If the scaled alpha is greater than or equal to “threshold” then scaled luma is unchanged, otherwise luma is replaced with “zero_luma”.
/// ###
/// %unsigned 8 zero_luma 0x0
/// ###
/// * Defines luma value to be replaced when scaled alpha is less than “threshold”.
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x12C78 mosd_pix (P)
/// %unsigned 32 tot 0x64
/// ###
/// * Specifies the total number of pixels expected at the input of MOSD Scaler. It should be programmed with (mosd_ivres*mosd_ihres).
/// ###
/// @ 0x12C7C MOSD_LSIZE (P)
/// %unsigned 9 lsize 0x1
/// ###
/// * Specifies the number of line buffer locations required to store one input (or scaled) line. How to calculate:
/// * If(hscaler before vscaler) hres = ohres;
/// * else hres = ihres;
/// * TS = Is 24 bit per pixel ? 5 : 8;
/// * lsize = ceil ( hres / (TS+1) )
/// ###
/// %% 23 # Stuffing bits...
/// @ 0x12C80 FE_MOSD_CTRL (P)
/// %unsigned 1 fld 0x0
/// ###
/// * Controls the field signal at the input of MOSD scaler.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12C84 OVERLAY_MUX (P)
/// %unsigned 1 MAIN 0x0
/// %unsigned 1 PIP 0x0
/// %unsigned 1 IG 0x0
/// %unsigned 1 PG 0x0
/// %unsigned 1 MOSD 0x0
/// %unsigned 1 CURSOR 0x0
/// %unsigned 1 BG 0x0
/// ###
/// * This mux is used to select between register programmed values and the output from scaler(or FE) to be fed into the CPCB overlay module. Setting a 1 to any of the bits will cause the register programmed values to be sent to the overlay module.
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x12C88 MAIN_OV_FXD_IMG (P)
/// %unsigned 24 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the Main channel.
/// ###
/// %% 8 # Stuffing bits...
/// @ 0x12C8C PIP_OV_FXD_IMG (P)
/// %unsigned 24 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the PIP channel.
/// ###
/// %% 8 # Stuffing bits...
/// @ 0x12C90 IG_OV_FXD_IMG (P)
/// %unsigned 32 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the IG channel.
/// ###
/// @ 0x12C94 PG_OV_FXD_IMG (P)
/// %unsigned 32 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the PG channel.
/// ###
/// @ 0x12C98 CURSOR_OV_FXD_IMG (P)
/// %unsigned 32 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the Cursor channel.
/// ###
/// @ 0x12C9C MOSD_OV_FXD_IMG (P)
/// %unsigned 32 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the MOSD channel.
/// ###
/// @ 0x12CA0 BG_OV_FXD_IMG (P)
/// %unsigned 16 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the BG channel.
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x12CA4 DET_OV_FXD_IMG (P)
/// %unsigned 8 REG 0x0
/// ###
/// * This register is used to provide a fixed color to the overlay module in CPCB. This is programmed in conjunction with the OVERLAY_MUX to select a fixed color for the detail channel.
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x12CA8 SENSIO_CTRL0 (P)
/// %unsigned 1 bypass 0x1
/// ###
/// * 1: bypass Sensio 3D decoder (hard-bypass, pixel data do not go through the Sensio 3D decoder)
/// * 0: Sensio 3D decoder is present in the path
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12CAC (P)
/// # 0x12CAC SENSIO_CTRL
/// $SENSIO SENSIO_CTRL REG
/// ###
/// * Sensio Control Registers
/// ###
/// @ 0x12CC8 (P)
/// # 0x12CC8 INV_SCAN_BG
/// $INV_SCAN INV_SCAN_BG REG
/// @ 0x12CCC (P)
/// # 0x12CCC INV_SCAN_MAIN
/// $INV_SCAN INV_SCAN_MAIN REG
/// @ 0x12CD0 (P)
/// # 0x12CD0 INV_SCAN_PIP
/// $INV_SCAN INV_SCAN_PIP REG
/// @ 0x12CD4 (P)
/// # 0x12CD4 INV_SCAN_PG
/// $INV_SCAN INV_SCAN_PG REG
/// @ 0x12CD8 (P)
/// # 0x12CD8 INV_SCAN_IG
/// $INV_SCAN INV_SCAN_IG REG
/// @ 0x12CDC (P)
/// # 0x12CDC INV_SCAN_CURSOR
/// $INV_SCAN INV_SCAN_CURSOR REG
/// @ 0x12CE0 (P)
/// # 0x12CE0 INV_SCAN_MOSD
/// $INV_SCAN INV_SCAN_MOSD REG
/// ###
/// * Aligns data input to serializer module in loader
/// ###
/// @ 0x12CE4 DROP_Y_INV_SCAN (P)
/// %unsigned 1 EN 0x0
/// ###
/// * Enable bit
/// ###
/// %unsigned 1 REPEAT_LASTY 0x0
/// ###
/// * Repeats LAST Y at end of Line
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x12CE8 VPP_INTR_EN (P)
/// %unsigned 1 vppCPCB0 0x1
/// ###
/// * Enable for CPCB0 VBI start interrupt
/// ###
/// %unsigned 1 vppCPCB1 0x1
/// ###
/// * Enable for CPCB1 VBI start interrupt
/// ###
/// %unsigned 1 vppCPCB2 0x1
/// ###
/// * Enable for CPCB2 VBI start interrupt
/// ###
/// %unsigned 1 vppOUT0 0x1
/// ###
/// * Enable for HDCP Interrupt
/// ###
/// %unsigned 1 vppOUT1 0x1
/// ###
/// * Enable for DDC Controller interrupt
/// ###
/// %unsigned 1 vppOUT2 0x1
/// ###
/// * Enable for DDC Controller interrupt
/// ###
/// %unsigned 1 vppOUT3 0x1
/// ###
/// * Enable for HPD interrupt (plug and unplug)
/// ###
/// %unsigned 1 vppOUT4 0x1
/// ###
/// * Enable for CPCB0 interlacer VDE start interrupt
/// ###
/// %unsigned 1 vppOUT5 0x1
/// ###
/// * Enable for CPCB1 VDE start interrupt
/// ###
/// %unsigned 1 vppOUT6 0x1
/// ###
/// * Enable for CPCB2 interlacer VDE start interrupt
/// ###
/// %unsigned 1 vppspdifrx 0x1
/// ###
/// * Enable for SPDIF-Rx interrupt
/// ###
/// %unsigned 1 vppspdifrx_ch 0x1
/// ###
/// * Enable for SPDIF-Rx interrupt
/// ###
/// %unsigned 1 BCM_INVALID 0x1
/// ###
/// * Enable BCM_INVALID interrupt when access to invalid address is made using BCM
/// ###
/// %% 19 # Stuffing bits...
/// @ 0x12CEC DEINT_FLD_STS (R-)
/// %unsigned 1 fld 0x0
/// ###
/// * Status of the De-Interlacer field signal.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x12CF0 (P)
/// # 0x12CF0 CLKGAT_CTRL
/// $CLKGAT_CTRL CLKGAT_CTRL REG
/// ###
/// * Clock gating enable registers for different blocks
/// ###
/// @ 0x12CF4 (W-)
/// # # Stuffing bytes...
/// %% 432224
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 131072B, bits: 2818b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_Vpp
#define h_Vpp (){}
#define RA_Vpp_cfgReg 0x0000
///////////////////////////////////////////////////////////
#define RA_Vpp_cpcb0Clk 0x10000
///////////////////////////////////////////////////////////
#define RA_Vpp_cpcb1Clk 0x10004
///////////////////////////////////////////////////////////
#define RA_Vpp_cpcb2Clk 0x10008
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_BE 0x1000C
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_CLKEN_CTRL 0x1001C
#define BA_Vpp_VP_CLKEN_CTRL_toggle 0x1001C
#define B16Vpp_VP_CLKEN_CTRL_toggle 0x1001C
#define LSb32Vpp_VP_CLKEN_CTRL_toggle 0
#define LSb16Vpp_VP_CLKEN_CTRL_toggle 0
#define bVpp_VP_CLKEN_CTRL_toggle 1
#define MSK32Vpp_VP_CLKEN_CTRL_toggle 0x00000001
#define BA_Vpp_VP_CLKEN_CTRL_diW 0x1001C
#define B16Vpp_VP_CLKEN_CTRL_diW 0x1001C
#define LSb32Vpp_VP_CLKEN_CTRL_diW 1
#define LSb16Vpp_VP_CLKEN_CTRL_diW 1
#define bVpp_VP_CLKEN_CTRL_diW 1
#define MSK32Vpp_VP_CLKEN_CTRL_diW 0x00000002
#define BA_Vpp_VP_CLKEN_CTRL_diR0 0x1001C
#define B16Vpp_VP_CLKEN_CTRL_diR0 0x1001C
#define LSb32Vpp_VP_CLKEN_CTRL_diR0 2
#define LSb16Vpp_VP_CLKEN_CTRL_diR0 2
#define bVpp_VP_CLKEN_CTRL_diR0 1
#define MSK32Vpp_VP_CLKEN_CTRL_diR0 0x00000004
#define BA_Vpp_VP_CLKEN_CTRL_diR1 0x1001C
#define B16Vpp_VP_CLKEN_CTRL_diR1 0x1001C
#define LSb32Vpp_VP_CLKEN_CTRL_diR1 3
#define LSb16Vpp_VP_CLKEN_CTRL_diR1 3
#define bVpp_VP_CLKEN_CTRL_diR1 1
#define MSK32Vpp_VP_CLKEN_CTRL_diR1 0x00000008
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_MAIN_CTRL 0x10020
#define BA_Vpp_FE_MAIN_CTRL_rff 0x10020
#define B16Vpp_FE_MAIN_CTRL_rff 0x10020
#define LSb32Vpp_FE_MAIN_CTRL_rff 0
#define LSb16Vpp_FE_MAIN_CTRL_rff 0
#define bVpp_FE_MAIN_CTRL_rff 1
#define MSK32Vpp_FE_MAIN_CTRL_rff 0x00000001
#define BA_Vpp_FE_MAIN_CTRL_fld 0x10020
#define B16Vpp_FE_MAIN_CTRL_fld 0x10020
#define LSb32Vpp_FE_MAIN_CTRL_fld 1
#define LSb16Vpp_FE_MAIN_CTRL_fld 1
#define bVpp_FE_MAIN_CTRL_fld 1
#define MSK32Vpp_FE_MAIN_CTRL_fld 0x00000002
#define BA_Vpp_FE_MAIN_CTRL_fld_mode 0x10020
#define B16Vpp_FE_MAIN_CTRL_fld_mode 0x10020
#define LSb32Vpp_FE_MAIN_CTRL_fld_mode 2
#define LSb16Vpp_FE_MAIN_CTRL_fld_mode 2
#define bVpp_FE_MAIN_CTRL_fld_mode 1
#define MSK32Vpp_FE_MAIN_CTRL_fld_mode 0x00000004
#define BA_Vpp_FE_MAIN_CTRL_fld_init 0x10020
#define B16Vpp_FE_MAIN_CTRL_fld_init 0x10020
#define LSb32Vpp_FE_MAIN_CTRL_fld_init 3
#define LSb16Vpp_FE_MAIN_CTRL_fld_init 3
#define bVpp_FE_MAIN_CTRL_fld_init 1
#define MSK32Vpp_FE_MAIN_CTRL_fld_init 0x00000008
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_PIP_CTRL 0x10024
#define BA_Vpp_FE_PIP_CTRL_fld 0x10024
#define B16Vpp_FE_PIP_CTRL_fld 0x10024
#define LSb32Vpp_FE_PIP_CTRL_fld 0
#define LSb16Vpp_FE_PIP_CTRL_fld 0
#define bVpp_FE_PIP_CTRL_fld 1
#define MSK32Vpp_FE_PIP_CTRL_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_OSD_CTRL 0x10028
#define BA_Vpp_FE_OSD_CTRL_fld 0x10028
#define B16Vpp_FE_OSD_CTRL_fld 0x10028
#define LSb32Vpp_FE_OSD_CTRL_fld 0
#define LSb16Vpp_FE_OSD_CTRL_fld 0
#define bVpp_FE_OSD_CTRL_fld 1
#define MSK32Vpp_FE_OSD_CTRL_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_PG_CTRL 0x1002C
#define BA_Vpp_FE_PG_CTRL_fld 0x1002C
#define B16Vpp_FE_PG_CTRL_fld 0x1002C
#define LSb32Vpp_FE_PG_CTRL_fld 0
#define LSb16Vpp_FE_PG_CTRL_fld 0
#define bVpp_FE_PG_CTRL_fld 1
#define MSK32Vpp_FE_PG_CTRL_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB0_FLD 0x10030
#define BA_Vpp_CPCB0_FLD_fld 0x10030
#define B16Vpp_CPCB0_FLD_fld 0x10030
#define LSb32Vpp_CPCB0_FLD_fld 0
#define LSb16Vpp_CPCB0_FLD_fld 0
#define bVpp_CPCB0_FLD_fld 1
#define MSK32Vpp_CPCB0_FLD_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB2_FLD 0x10034
#define BA_Vpp_CPCB2_FLD_fld 0x10034
#define B16Vpp_CPCB2_FLD_fld 0x10034
#define LSb32Vpp_CPCB2_FLD_fld 0
#define LSb16Vpp_CPCB2_FLD_fld 0
#define bVpp_CPCB2_FLD_fld 1
#define MSK32Vpp_CPCB2_FLD_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_PAT_SEL 0x10038
#define BA_Vpp_FE_PAT_SEL_pat_sel 0x10038
#define B16Vpp_FE_PAT_SEL_pat_sel 0x10038
#define LSb32Vpp_FE_PAT_SEL_pat_sel 0
#define LSb16Vpp_FE_PAT_SEL_pat_sel 0
#define bVpp_FE_PAT_SEL_pat_sel 1
#define MSK32Vpp_FE_PAT_SEL_pat_sel 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_mainW 0x1003C
#define BA_Vpp_mainW_start 0x1003C
#define B16Vpp_mainW_start 0x1003C
#define LSb32Vpp_mainW_start 0
#define LSb16Vpp_mainW_start 0
#define bVpp_mainW_start 1
#define MSK32Vpp_mainW_start 0x00000001
#define BA_Vpp_mainW_clear 0x1003C
#define B16Vpp_mainW_clear 0x1003C
#define LSb32Vpp_mainW_clear 1
#define LSb16Vpp_mainW_clear 1
#define bVpp_mainW_clear 1
#define MSK32Vpp_mainW_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_mainR 0x10040
#define BA_Vpp_mainR_start 0x10040
#define B16Vpp_mainR_start 0x10040
#define LSb32Vpp_mainR_start 0
#define LSb16Vpp_mainR_start 0
#define bVpp_mainR_start 1
#define MSK32Vpp_mainR_start 0x00000001
#define BA_Vpp_mainR_clear 0x10040
#define B16Vpp_mainR_clear 0x10040
#define LSb32Vpp_mainR_clear 1
#define LSb16Vpp_mainR_clear 1
#define bVpp_mainR_clear 1
#define MSK32Vpp_mainR_clear 0x00000002
#define BA_Vpp_mainR_packsel 0x10040
#define B16Vpp_mainR_packsel 0x10040
#define LSb32Vpp_mainR_packsel 2
#define LSb16Vpp_mainR_packsel 2
#define bVpp_mainR_packsel 1
#define MSK32Vpp_mainR_packsel 0x00000004
///////////////////////////////////////////////////////////
#define RA_Vpp_pipW 0x10044
#define BA_Vpp_pipW_start 0x10044
#define B16Vpp_pipW_start 0x10044
#define LSb32Vpp_pipW_start 0
#define LSb16Vpp_pipW_start 0
#define bVpp_pipW_start 1
#define MSK32Vpp_pipW_start 0x00000001
#define BA_Vpp_pipW_clear 0x10044
#define B16Vpp_pipW_clear 0x10044
#define LSb32Vpp_pipW_clear 1
#define LSb16Vpp_pipW_clear 1
#define bVpp_pipW_clear 1
#define MSK32Vpp_pipW_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_pipR 0x10048
#define BA_Vpp_pipR_start 0x10048
#define B16Vpp_pipR_start 0x10048
#define LSb32Vpp_pipR_start 0
#define LSb16Vpp_pipR_start 0
#define bVpp_pipR_start 1
#define MSK32Vpp_pipR_start 0x00000001
#define BA_Vpp_pipR_clear 0x10048
#define B16Vpp_pipR_clear 0x10048
#define LSb32Vpp_pipR_clear 1
#define LSb16Vpp_pipR_clear 1
#define bVpp_pipR_clear 1
#define MSK32Vpp_pipR_clear 0x00000002
#define BA_Vpp_pipR_packsel 0x10048
#define B16Vpp_pipR_packsel 0x10048
#define LSb32Vpp_pipR_packsel 2
#define LSb16Vpp_pipR_packsel 2
#define bVpp_pipR_packsel 1
#define MSK32Vpp_pipR_packsel 0x00000004
///////////////////////////////////////////////////////////
#define RA_Vpp_auxW 0x1004C
#define BA_Vpp_auxW_start 0x1004C
#define B16Vpp_auxW_start 0x1004C
#define LSb32Vpp_auxW_start 0
#define LSb16Vpp_auxW_start 0
#define bVpp_auxW_start 1
#define MSK32Vpp_auxW_start 0x00000001
#define BA_Vpp_auxW_clear 0x1004C
#define B16Vpp_auxW_clear 0x1004C
#define LSb32Vpp_auxW_clear 1
#define LSb16Vpp_auxW_clear 1
#define bVpp_auxW_clear 1
#define MSK32Vpp_auxW_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_auxR 0x10050
#define BA_Vpp_auxR_start 0x10050
#define B16Vpp_auxR_start 0x10050
#define LSb32Vpp_auxR_start 0
#define LSb16Vpp_auxR_start 0
#define bVpp_auxR_start 1
#define MSK32Vpp_auxR_start 0x00000001
#define BA_Vpp_auxR_clear 0x10050
#define B16Vpp_auxR_clear 0x10050
#define LSb32Vpp_auxR_clear 1
#define LSb16Vpp_auxR_clear 1
#define bVpp_auxR_clear 1
#define MSK32Vpp_auxR_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_rst 0x10054
#define BA_Vpp_rst_lvds_phy 0x10054
#define B16Vpp_rst_lvds_phy 0x10054
#define LSb32Vpp_rst_lvds_phy 0
#define LSb16Vpp_rst_lvds_phy 0
#define bVpp_rst_lvds_phy 1
#define MSK32Vpp_rst_lvds_phy 0x00000001
#define BA_Vpp_rst_be_ss 0x10054
#define B16Vpp_rst_be_ss 0x10054
#define LSb32Vpp_rst_be_ss 1
#define LSb16Vpp_rst_be_ss 1
#define bVpp_rst_be_ss 1
#define MSK32Vpp_rst_be_ss 0x00000002
#define BA_Vpp_rst_vp_top 0x10054
#define B16Vpp_rst_vp_top 0x10054
#define LSb32Vpp_rst_vp_top 2
#define LSb16Vpp_rst_vp_top 2
#define bVpp_rst_vp_top 1
#define MSK32Vpp_rst_vp_top 0x00000004
#define BA_Vpp_rst_hdmi_tx 0x10054
#define B16Vpp_rst_hdmi_tx 0x10054
#define LSb32Vpp_rst_hdmi_tx 3
#define LSb16Vpp_rst_hdmi_tx 3
#define bVpp_rst_hdmi_tx 1
#define MSK32Vpp_rst_hdmi_tx 0x00000008
#define BA_Vpp_rst_video_enc 0x10054
#define B16Vpp_rst_video_enc 0x10054
#define LSb32Vpp_rst_video_enc 4
#define LSb16Vpp_rst_video_enc 4
#define bVpp_rst_video_enc 1
#define MSK32Vpp_rst_video_enc 0x00000010
///////////////////////////////////////////////////////////
#define RA_Vpp_VDAC_ctrl 0x10058
///////////////////////////////////////////////////////////
#define RA_Vpp_VDAC_sts 0x10064
///////////////////////////////////////////////////////////
#define RA_Vpp_HDMI_ctrl 0x10068
///////////////////////////////////////////////////////////
#define RA_Vpp_HDMI_sts 0x10078
///////////////////////////////////////////////////////////
#define RA_Vpp_regIfCtrl 0x1007C
#define BA_Vpp_regIfCtrl_mwrWidth 0x1007C
#define B16Vpp_regIfCtrl_mwrWidth 0x1007C
#define LSb32Vpp_regIfCtrl_mwrWidth 0
#define LSb16Vpp_regIfCtrl_mwrWidth 0
#define bVpp_regIfCtrl_mwrWidth 8
#define MSK32Vpp_regIfCtrl_mwrWidth 0x000000FF
#define BA_Vpp_regIfCtrl_hold 0x1007D
#define B16Vpp_regIfCtrl_hold 0x1007C
#define LSb32Vpp_regIfCtrl_hold 8
#define LSb16Vpp_regIfCtrl_hold 8
#define bVpp_regIfCtrl_hold 8
#define MSK32Vpp_regIfCtrl_hold 0x0000FF00
///////////////////////////////////////////////////////////
#define RA_Vpp_MAIN_LSIZE 0x10080
#define BA_Vpp_MAIN_LSIZE_lsize 0x10080
#define B16Vpp_MAIN_LSIZE_lsize 0x10080
#define LSb32Vpp_MAIN_LSIZE_lsize 0
#define LSb16Vpp_MAIN_LSIZE_lsize 0
#define bVpp_MAIN_LSIZE_lsize 9
#define MSK32Vpp_MAIN_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_LSIZE 0x10084
#define BA_Vpp_PIP_LSIZE_lsize 0x10084
#define B16Vpp_PIP_LSIZE_lsize 0x10084
#define LSb32Vpp_PIP_LSIZE_lsize 0
#define LSb16Vpp_PIP_LSIZE_lsize 0
#define bVpp_PIP_LSIZE_lsize 9
#define MSK32Vpp_PIP_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_OSD_LSIZE 0x10088
#define BA_Vpp_OSD_LSIZE_lsize 0x10088
#define B16Vpp_OSD_LSIZE_lsize 0x10088
#define LSb32Vpp_OSD_LSIZE_lsize 0
#define LSb16Vpp_OSD_LSIZE_lsize 0
#define bVpp_OSD_LSIZE_lsize 9
#define MSK32Vpp_OSD_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_PG_LSIZE 0x1008C
#define BA_Vpp_PG_LSIZE_lsize 0x1008C
#define B16Vpp_PG_LSIZE_lsize 0x1008C
#define LSb32Vpp_PG_LSIZE_lsize 0
#define LSb16Vpp_PG_LSIZE_lsize 0
#define bVpp_PG_LSIZE_lsize 9
#define MSK32Vpp_PG_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_AUX_LSIZE 0x10090
#define BA_Vpp_AUX_LSIZE_lsize 0x10090
#define B16Vpp_AUX_LSIZE_lsize 0x10090
#define LSb32Vpp_AUX_LSIZE_lsize 0
#define LSb16Vpp_AUX_LSIZE_lsize 0
#define bVpp_AUX_LSIZE_lsize 9
#define MSK32Vpp_AUX_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_vpIn_pix 0x10094
#define BA_Vpp_vpIn_pix_tot 0x10094
#define B16Vpp_vpIn_pix_tot 0x10094
#define LSb32Vpp_vpIn_pix_tot 0
#define LSb16Vpp_vpIn_pix_tot 0
#define bVpp_vpIn_pix_tot 32
#define MSK32Vpp_vpIn_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_vpOut_pix 0x10098
#define BA_Vpp_vpOut_pix_tot 0x10098
#define B16Vpp_vpOut_pix_tot 0x10098
#define LSb32Vpp_vpOut_pix_tot 0
#define LSb16Vpp_vpOut_pix_tot 0
#define bVpp_vpOut_pix_tot 32
#define MSK32Vpp_vpOut_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_pip_pix 0x1009C
#define BA_Vpp_pip_pix_tot 0x1009C
#define B16Vpp_pip_pix_tot 0x1009C
#define LSb32Vpp_pip_pix_tot 0
#define LSb16Vpp_pip_pix_tot 0
#define bVpp_pip_pix_tot 32
#define MSK32Vpp_pip_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_osd_pix 0x100A0
#define BA_Vpp_osd_pix_tot 0x100A0
#define B16Vpp_osd_pix_tot 0x100A0
#define LSb32Vpp_osd_pix_tot 0
#define LSb16Vpp_osd_pix_tot 0
#define bVpp_osd_pix_tot 32
#define MSK32Vpp_osd_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_pg_pix 0x100A4
#define BA_Vpp_pg_pix_tot 0x100A4
#define B16Vpp_pg_pix_tot 0x100A4
#define LSb32Vpp_pg_pix_tot 0
#define LSb16Vpp_pg_pix_tot 0
#define bVpp_pg_pix_tot 32
#define MSK32Vpp_pg_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_diW_pix 0x100A8
#define BA_Vpp_diW_pix_tot 0x100A8
#define B16Vpp_diW_pix_tot 0x100A8
#define LSb32Vpp_diW_pix_tot 0
#define LSb16Vpp_diW_pix_tot 0
#define bVpp_diW_pix_tot 32
#define MSK32Vpp_diW_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_diR_word 0x100AC
#define BA_Vpp_diR_word_tot 0x100AC
#define B16Vpp_diR_word_tot 0x100AC
#define LSb32Vpp_diR_word_tot 0
#define LSb16Vpp_diR_word_tot 0
#define bVpp_diR_word_tot 32
#define MSK32Vpp_diR_word_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_mainW_pix 0x100B0
#define BA_Vpp_mainW_pix_tot 0x100B0
#define B16Vpp_mainW_pix_tot 0x100B0
#define LSb32Vpp_mainW_pix_tot 0
#define LSb16Vpp_mainW_pix_tot 0
#define bVpp_mainW_pix_tot 32
#define MSK32Vpp_mainW_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_mainR_word 0x100B4
#define BA_Vpp_mainR_word_tot 0x100B4
#define B16Vpp_mainR_word_tot 0x100B4
#define LSb32Vpp_mainR_word_tot 0
#define LSb16Vpp_mainR_word_tot 0
#define bVpp_mainR_word_tot 32
#define MSK32Vpp_mainR_word_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_pipW_pix 0x100B8
#define BA_Vpp_pipW_pix_tot 0x100B8
#define B16Vpp_pipW_pix_tot 0x100B8
#define LSb32Vpp_pipW_pix_tot 0
#define LSb16Vpp_pipW_pix_tot 0
#define bVpp_pipW_pix_tot 32
#define MSK32Vpp_pipW_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_pipR_word 0x100BC
#define BA_Vpp_pipR_word_tot 0x100BC
#define B16Vpp_pipR_word_tot 0x100BC
#define LSb32Vpp_pipR_word_tot 0
#define LSb16Vpp_pipR_word_tot 0
#define bVpp_pipR_word_tot 32
#define MSK32Vpp_pipR_word_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_auxW_pix 0x100C0
#define BA_Vpp_auxW_pix_tot 0x100C0
#define B16Vpp_auxW_pix_tot 0x100C0
#define LSb32Vpp_auxW_pix_tot 0
#define LSb16Vpp_auxW_pix_tot 0
#define bVpp_auxW_pix_tot 32
#define MSK32Vpp_auxW_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_auxR_word 0x100C4
#define BA_Vpp_auxR_word_tot 0x100C4
#define B16Vpp_auxR_word_tot 0x100C4
#define LSb32Vpp_auxR_word_tot 0
#define LSb16Vpp_auxR_word_tot 0
#define bVpp_auxR_word_tot 32
#define MSK32Vpp_auxR_word_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_main_ols 0x100C8
#define BA_Vpp_main_ols_en 0x100C8
#define B16Vpp_main_ols_en 0x100C8
#define LSb32Vpp_main_ols_en 0
#define LSb16Vpp_main_ols_en 0
#define bVpp_main_ols_en 1
#define MSK32Vpp_main_ols_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_pip_ols 0x100CC
#define BA_Vpp_pip_ols_en 0x100CC
#define B16Vpp_pip_ols_en 0x100CC
#define LSb32Vpp_pip_ols_en 0
#define LSb16Vpp_pip_ols_en 0
#define bVpp_pip_ols_en 1
#define MSK32Vpp_pip_ols_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_enc_hsvs_sel 0x100D0
#define BA_Vpp_enc_hsvs_sel_sel 0x100D0
#define B16Vpp_enc_hsvs_sel_sel 0x100D0
#define LSb32Vpp_enc_hsvs_sel_sel 0
#define LSb16Vpp_enc_hsvs_sel_sel 0
#define bVpp_enc_hsvs_sel_sel 1
#define MSK32Vpp_enc_hsvs_sel_sel 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB_FIFO_UF 0x100D4
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_0 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_0 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_0 0
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_0 0
#define bVpp_CPCB_FIFO_UF_cpcb0_0 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_0 0x00000001
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_1 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_1 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_1 1
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_1 1
#define bVpp_CPCB_FIFO_UF_cpcb0_1 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_1 0x00000002
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_2 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_2 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_2 2
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_2 2
#define bVpp_CPCB_FIFO_UF_cpcb0_2 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_2 0x00000004
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_3 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_3 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_3 3
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_3 3
#define bVpp_CPCB_FIFO_UF_cpcb0_3 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_3 0x00000008
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_4 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_4 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_4 4
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_4 4
#define bVpp_CPCB_FIFO_UF_cpcb0_4 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_4 0x00000010
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_5 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_5 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_5 5
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_5 5
#define bVpp_CPCB_FIFO_UF_cpcb0_5 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_5 0x00000020
#define BA_Vpp_CPCB_FIFO_UF_cpcb0_6 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb0_6 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb0_6 6
#define LSb16Vpp_CPCB_FIFO_UF_cpcb0_6 6
#define bVpp_CPCB_FIFO_UF_cpcb0_6 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb0_6 0x00000040
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_0 0x100D4
#define B16Vpp_CPCB_FIFO_UF_cpcb1_0 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_0 7
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_0 7
#define bVpp_CPCB_FIFO_UF_cpcb1_0 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_0 0x00000080
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_1 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_1 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_1 8
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_1 8
#define bVpp_CPCB_FIFO_UF_cpcb1_1 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_1 0x00000100
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_2 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_2 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_2 9
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_2 9
#define bVpp_CPCB_FIFO_UF_cpcb1_2 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_2 0x00000200
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_3 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_3 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_3 10
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_3 10
#define bVpp_CPCB_FIFO_UF_cpcb1_3 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_3 0x00000400
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_4 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_4 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_4 11
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_4 11
#define bVpp_CPCB_FIFO_UF_cpcb1_4 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_4 0x00000800
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_5 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_5 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_5 12
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_5 12
#define bVpp_CPCB_FIFO_UF_cpcb1_5 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_5 0x00001000
#define BA_Vpp_CPCB_FIFO_UF_cpcb1_6 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb1_6 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb1_6 13
#define LSb16Vpp_CPCB_FIFO_UF_cpcb1_6 13
#define bVpp_CPCB_FIFO_UF_cpcb1_6 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb1_6 0x00002000
#define BA_Vpp_CPCB_FIFO_UF_cpcb2_0 0x100D5
#define B16Vpp_CPCB_FIFO_UF_cpcb2_0 0x100D4
#define LSb32Vpp_CPCB_FIFO_UF_cpcb2_0 14
#define LSb16Vpp_CPCB_FIFO_UF_cpcb2_0 14
#define bVpp_CPCB_FIFO_UF_cpcb2_0 1
#define MSK32Vpp_CPCB_FIFO_UF_cpcb2_0 0x00004000
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_TG 0x100D8
///////////////////////////////////////////////////////////
#define RA_Vpp_LDR 0x10400
///////////////////////////////////////////////////////////
#define RA_Vpp_HDMI2DVAO 0x12C00
#define BA_Vpp_HDMI2DVAO_en 0x12C00
#define B16Vpp_HDMI2DVAO_en 0x12C00
#define LSb32Vpp_HDMI2DVAO_en 0
#define LSb16Vpp_HDMI2DVAO_en 0
#define bVpp_HDMI2DVAO_en 1
#define MSK32Vpp_HDMI2DVAO_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_CTRL 0x12C04
#define BA_Vpp_VP_DMX_CTRL_sw_sel 0x12C04
#define B16Vpp_VP_DMX_CTRL_sw_sel 0x12C04
#define LSb32Vpp_VP_DMX_CTRL_sw_sel 0
#define LSb16Vpp_VP_DMX_CTRL_sw_sel 0
#define bVpp_VP_DMX_CTRL_sw_sel 1
#define MSK32Vpp_VP_DMX_CTRL_sw_sel 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_HRES 0x12C08
#define BA_Vpp_VP_DMX_HRES_hres 0x12C08
#define B16Vpp_VP_DMX_HRES_hres 0x12C08
#define LSb32Vpp_VP_DMX_HRES_hres 0
#define LSb16Vpp_VP_DMX_HRES_hres 0
#define bVpp_VP_DMX_HRES_hres 12
#define MSK32Vpp_VP_DMX_HRES_hres 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_HT 0x12C0C
#define BA_Vpp_VP_DMX_HT_ht 0x12C0C
#define B16Vpp_VP_DMX_HT_ht 0x12C0C
#define LSb32Vpp_VP_DMX_HT_ht 0
#define LSb16Vpp_VP_DMX_HT_ht 0
#define bVpp_VP_DMX_HT_ht 12
#define MSK32Vpp_VP_DMX_HT_ht 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_VRES 0x12C10
#define BA_Vpp_VP_DMX_VRES_vres 0x12C10
#define B16Vpp_VP_DMX_VRES_vres 0x12C10
#define LSb32Vpp_VP_DMX_VRES_vres 0
#define LSb16Vpp_VP_DMX_VRES_vres 0
#define bVpp_VP_DMX_VRES_vres 12
#define MSK32Vpp_VP_DMX_VRES_vres 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_VT 0x12C14
#define BA_Vpp_VP_DMX_VT_vt 0x12C14
#define B16Vpp_VP_DMX_VT_vt 0x12C14
#define LSb32Vpp_VP_DMX_VT_vt 0
#define LSb16Vpp_VP_DMX_VT_vt 0
#define bVpp_VP_DMX_VT_vt 12
#define MSK32Vpp_VP_DMX_VT_vt 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_Vpp_VP_DMX_IVT 0x12C18
#define BA_Vpp_VP_DMX_IVT_ivt 0x12C18
#define B16Vpp_VP_DMX_IVT_ivt 0x12C18
#define LSb32Vpp_VP_DMX_IVT_ivt 0
#define LSb16Vpp_VP_DMX_IVT_ivt 0
#define bVpp_VP_DMX_IVT_ivt 12
#define MSK32Vpp_VP_DMX_IVT_ivt 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB0_PL_EN 0x12C1C
#define BA_Vpp_CPCB0_PL_EN_Main 0x12C1C
#define B16Vpp_CPCB0_PL_EN_Main 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_Main 0
#define LSb16Vpp_CPCB0_PL_EN_Main 0
#define bVpp_CPCB0_PL_EN_Main 1
#define MSK32Vpp_CPCB0_PL_EN_Main 0x00000001
#define BA_Vpp_CPCB0_PL_EN_PIP 0x12C1C
#define B16Vpp_CPCB0_PL_EN_PIP 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_PIP 1
#define LSb16Vpp_CPCB0_PL_EN_PIP 1
#define bVpp_CPCB0_PL_EN_PIP 1
#define MSK32Vpp_CPCB0_PL_EN_PIP 0x00000002
#define BA_Vpp_CPCB0_PL_EN_IG 0x12C1C
#define B16Vpp_CPCB0_PL_EN_IG 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_IG 2
#define LSb16Vpp_CPCB0_PL_EN_IG 2
#define bVpp_CPCB0_PL_EN_IG 1
#define MSK32Vpp_CPCB0_PL_EN_IG 0x00000004
#define BA_Vpp_CPCB0_PL_EN_PG 0x12C1C
#define B16Vpp_CPCB0_PL_EN_PG 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_PG 3
#define LSb16Vpp_CPCB0_PL_EN_PG 3
#define bVpp_CPCB0_PL_EN_PG 1
#define MSK32Vpp_CPCB0_PL_EN_PG 0x00000008
#define BA_Vpp_CPCB0_PL_EN_Cursor 0x12C1C
#define B16Vpp_CPCB0_PL_EN_Cursor 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_Cursor 4
#define LSb16Vpp_CPCB0_PL_EN_Cursor 4
#define bVpp_CPCB0_PL_EN_Cursor 1
#define MSK32Vpp_CPCB0_PL_EN_Cursor 0x00000010
#define BA_Vpp_CPCB0_PL_EN_MOSD 0x12C1C
#define B16Vpp_CPCB0_PL_EN_MOSD 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_MOSD 5
#define LSb16Vpp_CPCB0_PL_EN_MOSD 5
#define bVpp_CPCB0_PL_EN_MOSD 1
#define MSK32Vpp_CPCB0_PL_EN_MOSD 0x00000020
#define BA_Vpp_CPCB0_PL_EN_BG 0x12C1C
#define B16Vpp_CPCB0_PL_EN_BG 0x12C1C
#define LSb32Vpp_CPCB0_PL_EN_BG 6
#define LSb16Vpp_CPCB0_PL_EN_BG 6
#define bVpp_CPCB0_PL_EN_BG 1
#define MSK32Vpp_CPCB0_PL_EN_BG 0x00000040
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB1_PL_EN 0x12C20
#define BA_Vpp_CPCB1_PL_EN_Main 0x12C20
#define B16Vpp_CPCB1_PL_EN_Main 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_Main 0
#define LSb16Vpp_CPCB1_PL_EN_Main 0
#define bVpp_CPCB1_PL_EN_Main 1
#define MSK32Vpp_CPCB1_PL_EN_Main 0x00000001
#define BA_Vpp_CPCB1_PL_EN_PIP 0x12C20
#define B16Vpp_CPCB1_PL_EN_PIP 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_PIP 1
#define LSb16Vpp_CPCB1_PL_EN_PIP 1
#define bVpp_CPCB1_PL_EN_PIP 1
#define MSK32Vpp_CPCB1_PL_EN_PIP 0x00000002
#define BA_Vpp_CPCB1_PL_EN_IG 0x12C20
#define B16Vpp_CPCB1_PL_EN_IG 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_IG 2
#define LSb16Vpp_CPCB1_PL_EN_IG 2
#define bVpp_CPCB1_PL_EN_IG 1
#define MSK32Vpp_CPCB1_PL_EN_IG 0x00000004
#define BA_Vpp_CPCB1_PL_EN_PG 0x12C20
#define B16Vpp_CPCB1_PL_EN_PG 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_PG 3
#define LSb16Vpp_CPCB1_PL_EN_PG 3
#define bVpp_CPCB1_PL_EN_PG 1
#define MSK32Vpp_CPCB1_PL_EN_PG 0x00000008
#define BA_Vpp_CPCB1_PL_EN_Cursor 0x12C20
#define B16Vpp_CPCB1_PL_EN_Cursor 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_Cursor 4
#define LSb16Vpp_CPCB1_PL_EN_Cursor 4
#define bVpp_CPCB1_PL_EN_Cursor 1
#define MSK32Vpp_CPCB1_PL_EN_Cursor 0x00000010
#define BA_Vpp_CPCB1_PL_EN_MOSD 0x12C20
#define B16Vpp_CPCB1_PL_EN_MOSD 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_MOSD 5
#define LSb16Vpp_CPCB1_PL_EN_MOSD 5
#define bVpp_CPCB1_PL_EN_MOSD 1
#define MSK32Vpp_CPCB1_PL_EN_MOSD 0x00000020
#define BA_Vpp_CPCB1_PL_EN_BG 0x12C20
#define B16Vpp_CPCB1_PL_EN_BG 0x12C20
#define LSb32Vpp_CPCB1_PL_EN_BG 6
#define LSb16Vpp_CPCB1_PL_EN_BG 6
#define bVpp_CPCB1_PL_EN_BG 1
#define MSK32Vpp_CPCB1_PL_EN_BG 0x00000040
///////////////////////////////////////////////////////////
#define RA_Vpp_MAIN_WCLIENT 0x12C24
#define BA_Vpp_MAIN_WCLIENT_en 0x12C24
#define B16Vpp_MAIN_WCLIENT_en 0x12C24
#define LSb32Vpp_MAIN_WCLIENT_en 0
#define LSb16Vpp_MAIN_WCLIENT_en 0
#define bVpp_MAIN_WCLIENT_en 1
#define MSK32Vpp_MAIN_WCLIENT_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_WCLIENT 0x12C28
#define BA_Vpp_PIP_WCLIENT_en 0x12C28
#define B16Vpp_PIP_WCLIENT_en 0x12C28
#define LSb32Vpp_PIP_WCLIENT_en 0
#define LSb16Vpp_PIP_WCLIENT_en 0
#define bVpp_PIP_WCLIENT_en 1
#define MSK32Vpp_PIP_WCLIENT_en 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_DIW_CLIENT 0x12C2C
#define BA_Vpp_DIW_CLIENT_start 0x12C2C
#define B16Vpp_DIW_CLIENT_start 0x12C2C
#define LSb32Vpp_DIW_CLIENT_start 0
#define LSb16Vpp_DIW_CLIENT_start 0
#define bVpp_DIW_CLIENT_start 1
#define MSK32Vpp_DIW_CLIENT_start 0x00000001
#define BA_Vpp_DIW_CLIENT_clear 0x12C2C
#define B16Vpp_DIW_CLIENT_clear 0x12C2C
#define LSb32Vpp_DIW_CLIENT_clear 1
#define LSb16Vpp_DIW_CLIENT_clear 1
#define bVpp_DIW_CLIENT_clear 1
#define MSK32Vpp_DIW_CLIENT_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_DIR0_CLIENT 0x12C30
#define BA_Vpp_DIR0_CLIENT_start 0x12C30
#define B16Vpp_DIR0_CLIENT_start 0x12C30
#define LSb32Vpp_DIR0_CLIENT_start 0
#define LSb16Vpp_DIR0_CLIENT_start 0
#define bVpp_DIR0_CLIENT_start 1
#define MSK32Vpp_DIR0_CLIENT_start 0x00000001
#define BA_Vpp_DIR0_CLIENT_clear 0x12C30
#define B16Vpp_DIR0_CLIENT_clear 0x12C30
#define LSb32Vpp_DIR0_CLIENT_clear 1
#define LSb16Vpp_DIR0_CLIENT_clear 1
#define bVpp_DIR0_CLIENT_clear 1
#define MSK32Vpp_DIR0_CLIENT_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_DIR1_CLIENT 0x12C34
#define BA_Vpp_DIR1_CLIENT_start 0x12C34
#define B16Vpp_DIR1_CLIENT_start 0x12C34
#define LSb32Vpp_DIR1_CLIENT_start 0
#define LSb16Vpp_DIR1_CLIENT_start 0
#define bVpp_DIR1_CLIENT_start 1
#define MSK32Vpp_DIR1_CLIENT_start 0x00000001
#define BA_Vpp_DIR1_CLIENT_clear 0x12C34
#define B16Vpp_DIR1_CLIENT_clear 0x12C34
#define LSb32Vpp_DIR1_CLIENT_clear 1
#define LSb16Vpp_DIR1_CLIENT_clear 1
#define bVpp_DIR1_CLIENT_clear 1
#define MSK32Vpp_DIR1_CLIENT_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_SD_TT_CLIENT 0x12C38
#define BA_Vpp_SD_TT_CLIENT_enable 0x12C38
#define B16Vpp_SD_TT_CLIENT_enable 0x12C38
#define LSb32Vpp_SD_TT_CLIENT_enable 0
#define LSb16Vpp_SD_TT_CLIENT_enable 0
#define bVpp_SD_TT_CLIENT_enable 1
#define MSK32Vpp_SD_TT_CLIENT_enable 0x00000001
#define BA_Vpp_SD_TT_CLIENT_clear 0x12C38
#define B16Vpp_SD_TT_CLIENT_clear 0x12C38
#define LSb32Vpp_SD_TT_CLIENT_clear 1
#define LSb16Vpp_SD_TT_CLIENT_clear 1
#define bVpp_SD_TT_CLIENT_clear 1
#define MSK32Vpp_SD_TT_CLIENT_clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_SD_TT_BYTE 0x12C3C
#define BA_Vpp_SD_TT_BYTE_tot 0x12C3C
#define B16Vpp_SD_TT_BYTE_tot 0x12C3C
#define LSb32Vpp_SD_TT_BYTE_tot 0
#define LSb16Vpp_SD_TT_BYTE_tot 0
#define bVpp_SD_TT_BYTE_tot 32
#define MSK32Vpp_SD_TT_BYTE_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_DAC_RAMP_CTRL 0x12C40
#define BA_Vpp_DAC_RAMP_CTRL_start 0x12C40
#define B16Vpp_DAC_RAMP_CTRL_start 0x12C40
#define LSb32Vpp_DAC_RAMP_CTRL_start 0
#define LSb16Vpp_DAC_RAMP_CTRL_start 0
#define bVpp_DAC_RAMP_CTRL_start 12
#define MSK32Vpp_DAC_RAMP_CTRL_start 0x00000FFF
#define BA_Vpp_DAC_RAMP_CTRL_stop 0x12C41
#define B16Vpp_DAC_RAMP_CTRL_stop 0x12C40
#define LSb32Vpp_DAC_RAMP_CTRL_stop 12
#define LSb16Vpp_DAC_RAMP_CTRL_stop 12
#define bVpp_DAC_RAMP_CTRL_stop 12
#define MSK32Vpp_DAC_RAMP_CTRL_stop 0x00FFF000
#define BA_Vpp_DAC_RAMP_CTRL_step 0x12C43
#define B16Vpp_DAC_RAMP_CTRL_step 0x12C42
#define LSb32Vpp_DAC_RAMP_CTRL_step 24
#define LSb16Vpp_DAC_RAMP_CTRL_step 8
#define bVpp_DAC_RAMP_CTRL_step 8
#define MSK32Vpp_DAC_RAMP_CTRL_step 0xFF000000
///////////////////////////////////////////////////////////
#define RA_Vpp_DAC_TEST_CTRL 0x12C44
#define BA_Vpp_DAC_TEST_CTRL_sel 0x12C44
#define B16Vpp_DAC_TEST_CTRL_sel 0x12C44
#define LSb32Vpp_DAC_TEST_CTRL_sel 0
#define LSb16Vpp_DAC_TEST_CTRL_sel 0
#define bVpp_DAC_TEST_CTRL_sel 2
#define MSK32Vpp_DAC_TEST_CTRL_sel 0x00000003
///////////////////////////////////////////////////////////
#define RA_Vpp_SCL_CLKEN_CTRL 0x12C48
#define BA_Vpp_SCL_CLKEN_CTRL_Main 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_Main 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_Main 0
#define LSb16Vpp_SCL_CLKEN_CTRL_Main 0
#define bVpp_SCL_CLKEN_CTRL_Main 1
#define MSK32Vpp_SCL_CLKEN_CTRL_Main 0x00000001
#define BA_Vpp_SCL_CLKEN_CTRL_PIP 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_PIP 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_PIP 1
#define LSb16Vpp_SCL_CLKEN_CTRL_PIP 1
#define bVpp_SCL_CLKEN_CTRL_PIP 1
#define MSK32Vpp_SCL_CLKEN_CTRL_PIP 0x00000002
#define BA_Vpp_SCL_CLKEN_CTRL_IG 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_IG 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_IG 2
#define LSb16Vpp_SCL_CLKEN_CTRL_IG 2
#define bVpp_SCL_CLKEN_CTRL_IG 1
#define MSK32Vpp_SCL_CLKEN_CTRL_IG 0x00000004
#define BA_Vpp_SCL_CLKEN_CTRL_PG 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_PG 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_PG 3
#define LSb16Vpp_SCL_CLKEN_CTRL_PG 3
#define bVpp_SCL_CLKEN_CTRL_PG 1
#define MSK32Vpp_SCL_CLKEN_CTRL_PG 0x00000008
#define BA_Vpp_SCL_CLKEN_CTRL_AUX 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_AUX 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_AUX 4
#define LSb16Vpp_SCL_CLKEN_CTRL_AUX 4
#define bVpp_SCL_CLKEN_CTRL_AUX 1
#define MSK32Vpp_SCL_CLKEN_CTRL_AUX 0x00000010
#define BA_Vpp_SCL_CLKEN_CTRL_MOSD 0x12C48
#define B16Vpp_SCL_CLKEN_CTRL_MOSD 0x12C48
#define LSb32Vpp_SCL_CLKEN_CTRL_MOSD 5
#define LSb16Vpp_SCL_CLKEN_CTRL_MOSD 5
#define bVpp_SCL_CLKEN_CTRL_MOSD 1
#define MSK32Vpp_SCL_CLKEN_CTRL_MOSD 0x00000020
///////////////////////////////////////////////////////////
#define RA_Vpp_PAT_DNS_CTRL 0x12C4C
#define BA_Vpp_PAT_DNS_CTRL_cblank 0x12C4C
#define B16Vpp_PAT_DNS_CTRL_cblank 0x12C4C
#define LSb32Vpp_PAT_DNS_CTRL_cblank 0
#define LSb16Vpp_PAT_DNS_CTRL_cblank 0
#define bVpp_PAT_DNS_CTRL_cblank 12
#define MSK32Vpp_PAT_DNS_CTRL_cblank 0x00000FFF
#define BA_Vpp_PAT_DNS_CTRL_enable 0x12C4D
#define B16Vpp_PAT_DNS_CTRL_enable 0x12C4C
#define LSb32Vpp_PAT_DNS_CTRL_enable 12
#define LSb16Vpp_PAT_DNS_CTRL_enable 12
#define bVpp_PAT_DNS_CTRL_enable 1
#define MSK32Vpp_PAT_DNS_CTRL_enable 0x00001000
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB0_FLD_STS 0x12C50
#define BA_Vpp_CPCB0_FLD_STS_fld 0x12C50
#define B16Vpp_CPCB0_FLD_STS_fld 0x12C50
#define LSb32Vpp_CPCB0_FLD_STS_fld 0
#define LSb16Vpp_CPCB0_FLD_STS_fld 0
#define bVpp_CPCB0_FLD_STS_fld 1
#define MSK32Vpp_CPCB0_FLD_STS_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_CPCB2_FLD_STS 0x12C54
#define BA_Vpp_CPCB2_FLD_STS_fld 0x12C54
#define B16Vpp_CPCB2_FLD_STS_fld 0x12C54
#define LSb32Vpp_CPCB2_FLD_STS_fld 0
#define LSb16Vpp_CPCB2_FLD_STS_fld 0
#define bVpp_CPCB2_FLD_STS_fld 1
#define MSK32Vpp_CPCB2_FLD_STS_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_SD_TT_TEST 0x12C58
#define BA_Vpp_SD_TT_TEST_data 0x12C58
#define B16Vpp_SD_TT_TEST_data 0x12C58
#define LSb32Vpp_SD_TT_TEST_data 0
#define LSb16Vpp_SD_TT_TEST_data 0
#define bVpp_SD_TT_TEST_data 8
#define MSK32Vpp_SD_TT_TEST_data 0x000000FF
#define BA_Vpp_SD_TT_TEST_sel 0x12C59
#define B16Vpp_SD_TT_TEST_sel 0x12C58
#define LSb32Vpp_SD_TT_TEST_sel 8
#define LSb16Vpp_SD_TT_TEST_sel 8
#define bVpp_SD_TT_TEST_sel 1
#define MSK32Vpp_SD_TT_TEST_sel 0x00000100
///////////////////////////////////////////////////////////
#define RA_Vpp_DUMMY0 0x12C5C
#define BA_Vpp_DUMMY0_ctrl 0x12C5C
#define B16Vpp_DUMMY0_ctrl 0x12C5C
#define LSb32Vpp_DUMMY0_ctrl 0
#define LSb16Vpp_DUMMY0_ctrl 0
#define bVpp_DUMMY0_ctrl 32
#define MSK32Vpp_DUMMY0_ctrl 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_DEBUG0 0x12C60
#define BA_Vpp_DEBUG0_diCnt 0x12C60
#define B16Vpp_DEBUG0_diCnt 0x12C60
#define LSb32Vpp_DEBUG0_diCnt 0
#define LSb16Vpp_DEBUG0_diCnt 0
#define bVpp_DEBUG0_diCnt 8
#define MSK32Vpp_DEBUG0_diCnt 0x000000FF
#define BA_Vpp_DEBUG0_insert_frame 0x12C61
#define B16Vpp_DEBUG0_insert_frame 0x12C60
#define LSb32Vpp_DEBUG0_insert_frame 8
#define LSb16Vpp_DEBUG0_insert_frame 8
#define bVpp_DEBUG0_insert_frame 1
#define MSK32Vpp_DEBUG0_insert_frame 0x00000100
#define BA_Vpp_DEBUG0_drop_frame 0x12C61
#define B16Vpp_DEBUG0_drop_frame 0x12C60
#define LSb32Vpp_DEBUG0_drop_frame 9
#define LSb16Vpp_DEBUG0_drop_frame 9
#define bVpp_DEBUG0_drop_frame 1
#define MSK32Vpp_DEBUG0_drop_frame 0x00000200
#define BA_Vpp_DEBUG0_film_det_32 0x12C61
#define B16Vpp_DEBUG0_film_det_32 0x12C60
#define LSb32Vpp_DEBUG0_film_det_32 10
#define LSb16Vpp_DEBUG0_film_det_32 10
#define bVpp_DEBUG0_film_det_32 1
#define MSK32Vpp_DEBUG0_film_det_32 0x00000400
#define BA_Vpp_DEBUG0_vIFifoDone 0x12C61
#define B16Vpp_DEBUG0_vIFifoDone 0x12C60
#define LSb32Vpp_DEBUG0_vIFifoDone 11
#define LSb16Vpp_DEBUG0_vIFifoDone 11
#define bVpp_DEBUG0_vIFifoDone 1
#define MSK32Vpp_DEBUG0_vIFifoDone 0x00000800
#define BA_Vpp_DEBUG0_vOFifoDone 0x12C61
#define B16Vpp_DEBUG0_vOFifoDone 0x12C60
#define LSb32Vpp_DEBUG0_vOFifoDone 12
#define LSb16Vpp_DEBUG0_vOFifoDone 12
#define bVpp_DEBUG0_vOFifoDone 1
#define MSK32Vpp_DEBUG0_vOFifoDone 0x00001000
#define BA_Vpp_DEBUG0_pipFifoDone 0x12C61
#define B16Vpp_DEBUG0_pipFifoDone 0x12C60
#define LSb32Vpp_DEBUG0_pipFifoDone 13
#define LSb16Vpp_DEBUG0_pipFifoDone 13
#define bVpp_DEBUG0_pipFifoDone 1
#define MSK32Vpp_DEBUG0_pipFifoDone 0x00002000
#define BA_Vpp_DEBUG0_igFifoDone 0x12C61
#define B16Vpp_DEBUG0_igFifoDone 0x12C60
#define LSb32Vpp_DEBUG0_igFifoDone 14
#define LSb16Vpp_DEBUG0_igFifoDone 14
#define bVpp_DEBUG0_igFifoDone 1
#define MSK32Vpp_DEBUG0_igFifoDone 0x00004000
#define BA_Vpp_DEBUG0_pgFifoDone 0x12C61
#define B16Vpp_DEBUG0_pgFifoDone 0x12C60
#define LSb32Vpp_DEBUG0_pgFifoDone 15
#define LSb16Vpp_DEBUG0_pgFifoDone 15
#define bVpp_DEBUG0_pgFifoDone 1
#define MSK32Vpp_DEBUG0_pgFifoDone 0x00008000
#define BA_Vpp_DEBUG0_mosdFifoDone 0x12C62
#define B16Vpp_DEBUG0_mosdFifoDone 0x12C62
#define LSb32Vpp_DEBUG0_mosdFifoDone 16
#define LSb16Vpp_DEBUG0_mosdFifoDone 0
#define bVpp_DEBUG0_mosdFifoDone 1
#define MSK32Vpp_DEBUG0_mosdFifoDone 0x00010000
///////////////////////////////////////////////////////////
#define RA_Vpp_MAIN_SCL_CROP 0x12C64
#define BA_Vpp_MAIN_SCL_CROP_ctrl 0x12C64
#define B16Vpp_MAIN_SCL_CROP_ctrl 0x12C64
#define LSb32Vpp_MAIN_SCL_CROP_ctrl 0
#define LSb16Vpp_MAIN_SCL_CROP_ctrl 0
#define bVpp_MAIN_SCL_CROP_ctrl 3
#define MSK32Vpp_MAIN_SCL_CROP_ctrl 0x00000007
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_SCL_CROP 0x12C68
#define BA_Vpp_PIP_SCL_CROP_ctrl 0x12C68
#define B16Vpp_PIP_SCL_CROP_ctrl 0x12C68
#define LSb32Vpp_PIP_SCL_CROP_ctrl 0
#define LSb16Vpp_PIP_SCL_CROP_ctrl 0
#define bVpp_PIP_SCL_CROP_ctrl 3
#define MSK32Vpp_PIP_SCL_CROP_ctrl 0x00000007
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_LUMA_KEY 0x12C6C
#define BA_Vpp_PIP_LUMA_KEY_en 0x12C6C
#define B16Vpp_PIP_LUMA_KEY_en 0x12C6C
#define LSb32Vpp_PIP_LUMA_KEY_en 0
#define LSb16Vpp_PIP_LUMA_KEY_en 0
#define bVpp_PIP_LUMA_KEY_en 1
#define MSK32Vpp_PIP_LUMA_KEY_en 0x00000001
#define BA_Vpp_PIP_LUMA_KEY_min 0x12C6C
#define B16Vpp_PIP_LUMA_KEY_min 0x12C6C
#define LSb32Vpp_PIP_LUMA_KEY_min 1
#define LSb16Vpp_PIP_LUMA_KEY_min 1
#define bVpp_PIP_LUMA_KEY_min 8
#define MSK32Vpp_PIP_LUMA_KEY_min 0x000001FE
#define BA_Vpp_PIP_LUMA_KEY_max 0x12C6D
#define B16Vpp_PIP_LUMA_KEY_max 0x12C6C
#define LSb32Vpp_PIP_LUMA_KEY_max 9
#define LSb16Vpp_PIP_LUMA_KEY_max 9
#define bVpp_PIP_LUMA_KEY_max 8
#define MSK32Vpp_PIP_LUMA_KEY_max 0x0001FE00
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_AL_IN 0x12C70
#define BA_Vpp_PIP_AL_IN_hit_al 0x12C70
#define B16Vpp_PIP_AL_IN_hit_al 0x12C70
#define LSb32Vpp_PIP_AL_IN_hit_al 0
#define LSb16Vpp_PIP_AL_IN_hit_al 0
#define bVpp_PIP_AL_IN_hit_al 8
#define MSK32Vpp_PIP_AL_IN_hit_al 0x000000FF
#define BA_Vpp_PIP_AL_IN_non_hit_al 0x12C71
#define B16Vpp_PIP_AL_IN_non_hit_al 0x12C70
#define LSb32Vpp_PIP_AL_IN_non_hit_al 8
#define LSb16Vpp_PIP_AL_IN_non_hit_al 8
#define bVpp_PIP_AL_IN_non_hit_al 8
#define MSK32Vpp_PIP_AL_IN_non_hit_al 0x0000FF00
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_AL_OUT 0x12C74
#define BA_Vpp_PIP_AL_OUT_threshold 0x12C74
#define B16Vpp_PIP_AL_OUT_threshold 0x12C74
#define LSb32Vpp_PIP_AL_OUT_threshold 0
#define LSb16Vpp_PIP_AL_OUT_threshold 0
#define bVpp_PIP_AL_OUT_threshold 8
#define MSK32Vpp_PIP_AL_OUT_threshold 0x000000FF
#define BA_Vpp_PIP_AL_OUT_zero_luma 0x12C75
#define B16Vpp_PIP_AL_OUT_zero_luma 0x12C74
#define LSb32Vpp_PIP_AL_OUT_zero_luma 8
#define LSb16Vpp_PIP_AL_OUT_zero_luma 8
#define bVpp_PIP_AL_OUT_zero_luma 8
#define MSK32Vpp_PIP_AL_OUT_zero_luma 0x0000FF00
///////////////////////////////////////////////////////////
#define RA_Vpp_mosd_pix 0x12C78
#define BA_Vpp_mosd_pix_tot 0x12C78
#define B16Vpp_mosd_pix_tot 0x12C78
#define LSb32Vpp_mosd_pix_tot 0
#define LSb16Vpp_mosd_pix_tot 0
#define bVpp_mosd_pix_tot 32
#define MSK32Vpp_mosd_pix_tot 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_MOSD_LSIZE 0x12C7C
#define BA_Vpp_MOSD_LSIZE_lsize 0x12C7C
#define B16Vpp_MOSD_LSIZE_lsize 0x12C7C
#define LSb32Vpp_MOSD_LSIZE_lsize 0
#define LSb16Vpp_MOSD_LSIZE_lsize 0
#define bVpp_MOSD_LSIZE_lsize 9
#define MSK32Vpp_MOSD_LSIZE_lsize 0x000001FF
///////////////////////////////////////////////////////////
#define RA_Vpp_FE_MOSD_CTRL 0x12C80
#define BA_Vpp_FE_MOSD_CTRL_fld 0x12C80
#define B16Vpp_FE_MOSD_CTRL_fld 0x12C80
#define LSb32Vpp_FE_MOSD_CTRL_fld 0
#define LSb16Vpp_FE_MOSD_CTRL_fld 0
#define bVpp_FE_MOSD_CTRL_fld 1
#define MSK32Vpp_FE_MOSD_CTRL_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_OVERLAY_MUX 0x12C84
#define BA_Vpp_OVERLAY_MUX_MAIN 0x12C84
#define B16Vpp_OVERLAY_MUX_MAIN 0x12C84
#define LSb32Vpp_OVERLAY_MUX_MAIN 0
#define LSb16Vpp_OVERLAY_MUX_MAIN 0
#define bVpp_OVERLAY_MUX_MAIN 1
#define MSK32Vpp_OVERLAY_MUX_MAIN 0x00000001
#define BA_Vpp_OVERLAY_MUX_PIP 0x12C84
#define B16Vpp_OVERLAY_MUX_PIP 0x12C84
#define LSb32Vpp_OVERLAY_MUX_PIP 1
#define LSb16Vpp_OVERLAY_MUX_PIP 1
#define bVpp_OVERLAY_MUX_PIP 1
#define MSK32Vpp_OVERLAY_MUX_PIP 0x00000002
#define BA_Vpp_OVERLAY_MUX_IG 0x12C84
#define B16Vpp_OVERLAY_MUX_IG 0x12C84
#define LSb32Vpp_OVERLAY_MUX_IG 2
#define LSb16Vpp_OVERLAY_MUX_IG 2
#define bVpp_OVERLAY_MUX_IG 1
#define MSK32Vpp_OVERLAY_MUX_IG 0x00000004
#define BA_Vpp_OVERLAY_MUX_PG 0x12C84
#define B16Vpp_OVERLAY_MUX_PG 0x12C84
#define LSb32Vpp_OVERLAY_MUX_PG 3
#define LSb16Vpp_OVERLAY_MUX_PG 3
#define bVpp_OVERLAY_MUX_PG 1
#define MSK32Vpp_OVERLAY_MUX_PG 0x00000008
#define BA_Vpp_OVERLAY_MUX_MOSD 0x12C84
#define B16Vpp_OVERLAY_MUX_MOSD 0x12C84
#define LSb32Vpp_OVERLAY_MUX_MOSD 4
#define LSb16Vpp_OVERLAY_MUX_MOSD 4
#define bVpp_OVERLAY_MUX_MOSD 1
#define MSK32Vpp_OVERLAY_MUX_MOSD 0x00000010
#define BA_Vpp_OVERLAY_MUX_CURSOR 0x12C84
#define B16Vpp_OVERLAY_MUX_CURSOR 0x12C84
#define LSb32Vpp_OVERLAY_MUX_CURSOR 5
#define LSb16Vpp_OVERLAY_MUX_CURSOR 5
#define bVpp_OVERLAY_MUX_CURSOR 1
#define MSK32Vpp_OVERLAY_MUX_CURSOR 0x00000020
#define BA_Vpp_OVERLAY_MUX_BG 0x12C84
#define B16Vpp_OVERLAY_MUX_BG 0x12C84
#define LSb32Vpp_OVERLAY_MUX_BG 6
#define LSb16Vpp_OVERLAY_MUX_BG 6
#define bVpp_OVERLAY_MUX_BG 1
#define MSK32Vpp_OVERLAY_MUX_BG 0x00000040
///////////////////////////////////////////////////////////
#define RA_Vpp_MAIN_OV_FXD_IMG 0x12C88
#define BA_Vpp_MAIN_OV_FXD_IMG_REG 0x12C88
#define B16Vpp_MAIN_OV_FXD_IMG_REG 0x12C88
#define LSb32Vpp_MAIN_OV_FXD_IMG_REG 0
#define LSb16Vpp_MAIN_OV_FXD_IMG_REG 0
#define bVpp_MAIN_OV_FXD_IMG_REG 24
#define MSK32Vpp_MAIN_OV_FXD_IMG_REG 0x00FFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_PIP_OV_FXD_IMG 0x12C8C
#define BA_Vpp_PIP_OV_FXD_IMG_REG 0x12C8C
#define B16Vpp_PIP_OV_FXD_IMG_REG 0x12C8C
#define LSb32Vpp_PIP_OV_FXD_IMG_REG 0
#define LSb16Vpp_PIP_OV_FXD_IMG_REG 0
#define bVpp_PIP_OV_FXD_IMG_REG 24
#define MSK32Vpp_PIP_OV_FXD_IMG_REG 0x00FFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_IG_OV_FXD_IMG 0x12C90
#define BA_Vpp_IG_OV_FXD_IMG_REG 0x12C90
#define B16Vpp_IG_OV_FXD_IMG_REG 0x12C90
#define LSb32Vpp_IG_OV_FXD_IMG_REG 0
#define LSb16Vpp_IG_OV_FXD_IMG_REG 0
#define bVpp_IG_OV_FXD_IMG_REG 32
#define MSK32Vpp_IG_OV_FXD_IMG_REG 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_PG_OV_FXD_IMG 0x12C94
#define BA_Vpp_PG_OV_FXD_IMG_REG 0x12C94
#define B16Vpp_PG_OV_FXD_IMG_REG 0x12C94
#define LSb32Vpp_PG_OV_FXD_IMG_REG 0
#define LSb16Vpp_PG_OV_FXD_IMG_REG 0
#define bVpp_PG_OV_FXD_IMG_REG 32
#define MSK32Vpp_PG_OV_FXD_IMG_REG 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_CURSOR_OV_FXD_IMG 0x12C98
#define BA_Vpp_CURSOR_OV_FXD_IMG_REG 0x12C98
#define B16Vpp_CURSOR_OV_FXD_IMG_REG 0x12C98
#define LSb32Vpp_CURSOR_OV_FXD_IMG_REG 0
#define LSb16Vpp_CURSOR_OV_FXD_IMG_REG 0
#define bVpp_CURSOR_OV_FXD_IMG_REG 32
#define MSK32Vpp_CURSOR_OV_FXD_IMG_REG 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_MOSD_OV_FXD_IMG 0x12C9C
#define BA_Vpp_MOSD_OV_FXD_IMG_REG 0x12C9C
#define B16Vpp_MOSD_OV_FXD_IMG_REG 0x12C9C
#define LSb32Vpp_MOSD_OV_FXD_IMG_REG 0
#define LSb16Vpp_MOSD_OV_FXD_IMG_REG 0
#define bVpp_MOSD_OV_FXD_IMG_REG 32
#define MSK32Vpp_MOSD_OV_FXD_IMG_REG 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_BG_OV_FXD_IMG 0x12CA0
#define BA_Vpp_BG_OV_FXD_IMG_REG 0x12CA0
#define B16Vpp_BG_OV_FXD_IMG_REG 0x12CA0
#define LSb32Vpp_BG_OV_FXD_IMG_REG 0
#define LSb16Vpp_BG_OV_FXD_IMG_REG 0
#define bVpp_BG_OV_FXD_IMG_REG 16
#define MSK32Vpp_BG_OV_FXD_IMG_REG 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_Vpp_DET_OV_FXD_IMG 0x12CA4
#define BA_Vpp_DET_OV_FXD_IMG_REG 0x12CA4
#define B16Vpp_DET_OV_FXD_IMG_REG 0x12CA4
#define LSb32Vpp_DET_OV_FXD_IMG_REG 0
#define LSb16Vpp_DET_OV_FXD_IMG_REG 0
#define bVpp_DET_OV_FXD_IMG_REG 8
#define MSK32Vpp_DET_OV_FXD_IMG_REG 0x000000FF
///////////////////////////////////////////////////////////
#define RA_Vpp_SENSIO_CTRL0 0x12CA8
#define BA_Vpp_SENSIO_CTRL0_bypass 0x12CA8
#define B16Vpp_SENSIO_CTRL0_bypass 0x12CA8
#define LSb32Vpp_SENSIO_CTRL0_bypass 0
#define LSb16Vpp_SENSIO_CTRL0_bypass 0
#define bVpp_SENSIO_CTRL0_bypass 1
#define MSK32Vpp_SENSIO_CTRL0_bypass 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_SENSIO_CTRL 0x12CAC
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_BG 0x12CC8
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_MAIN 0x12CCC
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_PIP 0x12CD0
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_PG 0x12CD4
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_IG 0x12CD8
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_CURSOR 0x12CDC
///////////////////////////////////////////////////////////
#define RA_Vpp_INV_SCAN_MOSD 0x12CE0
///////////////////////////////////////////////////////////
#define RA_Vpp_DROP_Y_INV_SCAN 0x12CE4
#define BA_Vpp_DROP_Y_INV_SCAN_EN 0x12CE4
#define B16Vpp_DROP_Y_INV_SCAN_EN 0x12CE4
#define LSb32Vpp_DROP_Y_INV_SCAN_EN 0
#define LSb16Vpp_DROP_Y_INV_SCAN_EN 0
#define bVpp_DROP_Y_INV_SCAN_EN 1
#define MSK32Vpp_DROP_Y_INV_SCAN_EN 0x00000001
#define BA_Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY 0x12CE4
#define B16Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY 0x12CE4
#define LSb32Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY 1
#define LSb16Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY 1
#define bVpp_DROP_Y_INV_SCAN_REPEAT_LASTY 1
#define MSK32Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY 0x00000002
///////////////////////////////////////////////////////////
#define RA_Vpp_VPP_INTR_EN 0x12CE8
#define BA_Vpp_VPP_INTR_EN_vppCPCB0 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppCPCB0 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppCPCB0 0
#define LSb16Vpp_VPP_INTR_EN_vppCPCB0 0
#define bVpp_VPP_INTR_EN_vppCPCB0 1
#define MSK32Vpp_VPP_INTR_EN_vppCPCB0 0x00000001
#define BA_Vpp_VPP_INTR_EN_vppCPCB1 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppCPCB1 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppCPCB1 1
#define LSb16Vpp_VPP_INTR_EN_vppCPCB1 1
#define bVpp_VPP_INTR_EN_vppCPCB1 1
#define MSK32Vpp_VPP_INTR_EN_vppCPCB1 0x00000002
#define BA_Vpp_VPP_INTR_EN_vppCPCB2 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppCPCB2 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppCPCB2 2
#define LSb16Vpp_VPP_INTR_EN_vppCPCB2 2
#define bVpp_VPP_INTR_EN_vppCPCB2 1
#define MSK32Vpp_VPP_INTR_EN_vppCPCB2 0x00000004
#define BA_Vpp_VPP_INTR_EN_vppOUT0 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppOUT0 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT0 3
#define LSb16Vpp_VPP_INTR_EN_vppOUT0 3
#define bVpp_VPP_INTR_EN_vppOUT0 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT0 0x00000008
#define BA_Vpp_VPP_INTR_EN_vppOUT1 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppOUT1 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT1 4
#define LSb16Vpp_VPP_INTR_EN_vppOUT1 4
#define bVpp_VPP_INTR_EN_vppOUT1 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT1 0x00000010
#define BA_Vpp_VPP_INTR_EN_vppOUT2 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppOUT2 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT2 5
#define LSb16Vpp_VPP_INTR_EN_vppOUT2 5
#define bVpp_VPP_INTR_EN_vppOUT2 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT2 0x00000020
#define BA_Vpp_VPP_INTR_EN_vppOUT3 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppOUT3 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT3 6
#define LSb16Vpp_VPP_INTR_EN_vppOUT3 6
#define bVpp_VPP_INTR_EN_vppOUT3 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT3 0x00000040
#define BA_Vpp_VPP_INTR_EN_vppOUT4 0x12CE8
#define B16Vpp_VPP_INTR_EN_vppOUT4 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT4 7
#define LSb16Vpp_VPP_INTR_EN_vppOUT4 7
#define bVpp_VPP_INTR_EN_vppOUT4 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT4 0x00000080
#define BA_Vpp_VPP_INTR_EN_vppOUT5 0x12CE9
#define B16Vpp_VPP_INTR_EN_vppOUT5 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT5 8
#define LSb16Vpp_VPP_INTR_EN_vppOUT5 8
#define bVpp_VPP_INTR_EN_vppOUT5 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT5 0x00000100
#define BA_Vpp_VPP_INTR_EN_vppOUT6 0x12CE9
#define B16Vpp_VPP_INTR_EN_vppOUT6 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppOUT6 9
#define LSb16Vpp_VPP_INTR_EN_vppOUT6 9
#define bVpp_VPP_INTR_EN_vppOUT6 1
#define MSK32Vpp_VPP_INTR_EN_vppOUT6 0x00000200
#define BA_Vpp_VPP_INTR_EN_vppspdifrx 0x12CE9
#define B16Vpp_VPP_INTR_EN_vppspdifrx 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppspdifrx 10
#define LSb16Vpp_VPP_INTR_EN_vppspdifrx 10
#define bVpp_VPP_INTR_EN_vppspdifrx 1
#define MSK32Vpp_VPP_INTR_EN_vppspdifrx 0x00000400
#define BA_Vpp_VPP_INTR_EN_vppspdifrx_ch 0x12CE9
#define B16Vpp_VPP_INTR_EN_vppspdifrx_ch 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_vppspdifrx_ch 11
#define LSb16Vpp_VPP_INTR_EN_vppspdifrx_ch 11
#define bVpp_VPP_INTR_EN_vppspdifrx_ch 1
#define MSK32Vpp_VPP_INTR_EN_vppspdifrx_ch 0x00000800
#define BA_Vpp_VPP_INTR_EN_BCM_INVALID 0x12CE9
#define B16Vpp_VPP_INTR_EN_BCM_INVALID 0x12CE8
#define LSb32Vpp_VPP_INTR_EN_BCM_INVALID 12
#define LSb16Vpp_VPP_INTR_EN_BCM_INVALID 12
#define bVpp_VPP_INTR_EN_BCM_INVALID 1
#define MSK32Vpp_VPP_INTR_EN_BCM_INVALID 0x00001000
///////////////////////////////////////////////////////////
#define RA_Vpp_DEINT_FLD_STS 0x12CEC
#define BA_Vpp_DEINT_FLD_STS_fld 0x12CEC
#define B16Vpp_DEINT_FLD_STS_fld 0x12CEC
#define LSb32Vpp_DEINT_FLD_STS_fld 0
#define LSb16Vpp_DEINT_FLD_STS_fld 0
#define bVpp_DEINT_FLD_STS_fld 1
#define MSK32Vpp_DEINT_FLD_STS_fld 0x00000001
///////////////////////////////////////////////////////////
#define RA_Vpp_CLKGAT_CTRL 0x12CF0
///////////////////////////////////////////////////////////
typedef struct SIE_Vpp {
///////////////////////////////////////////////////////////
SIE_VPP_REG ie_cfgReg;
///////////////////////////////////////////////////////////
SIE_CLK ie_cpcb0Clk;
///////////////////////////////////////////////////////////
SIE_CLK ie_cpcb1Clk;
///////////////////////////////////////////////////////////
SIE_CLK ie_cpcb2Clk;
///////////////////////////////////////////////////////////
SIE_FE_BE ie_FE_BE;
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_CLKEN_CTRL_toggle(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_VP_CLKEN_CTRL_toggle(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_VP_CLKEN_CTRL_toggle(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_VP_CLKEN_CTRL_toggle(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_VP_CLKEN_CTRL_diW(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_VP_CLKEN_CTRL_diW(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_VP_CLKEN_CTRL_diW(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_VP_CLKEN_CTRL_diW(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_VP_CLKEN_CTRL_diR0(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_VP_CLKEN_CTRL_diR0(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_VP_CLKEN_CTRL_diR0(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_VP_CLKEN_CTRL_diR0(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_VP_CLKEN_CTRL_diR1(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_VP_CLKEN_CTRL_diR1(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_VP_CLKEN_CTRL_diR1(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_VP_CLKEN_CTRL_diR1(r16,v) _BFSET_(r16, 3, 3,v)
#define w32Vpp_VP_CLKEN_CTRL {\
UNSG32 uVP_CLKEN_CTRL_toggle : 1;\
UNSG32 uVP_CLKEN_CTRL_diW : 1;\
UNSG32 uVP_CLKEN_CTRL_diR0 : 1;\
UNSG32 uVP_CLKEN_CTRL_diR1 : 1;\
UNSG32 RSVDx1001C_b4 : 28;\
}
union { UNSG32 u32Vpp_VP_CLKEN_CTRL;
struct w32Vpp_VP_CLKEN_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_MAIN_CTRL_rff(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_MAIN_CTRL_rff(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_MAIN_CTRL_rff(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_MAIN_CTRL_rff(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_FE_MAIN_CTRL_fld(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_FE_MAIN_CTRL_fld(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_FE_MAIN_CTRL_fld(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_FE_MAIN_CTRL_fld(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_FE_MAIN_CTRL_fld_mode(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_FE_MAIN_CTRL_fld_mode(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_FE_MAIN_CTRL_fld_mode(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_FE_MAIN_CTRL_fld_mode(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_FE_MAIN_CTRL_fld_init(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_FE_MAIN_CTRL_fld_init(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_FE_MAIN_CTRL_fld_init(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_FE_MAIN_CTRL_fld_init(r16,v) _BFSET_(r16, 3, 3,v)
#define w32Vpp_FE_MAIN_CTRL {\
UNSG32 uFE_MAIN_CTRL_rff : 1;\
UNSG32 uFE_MAIN_CTRL_fld : 1;\
UNSG32 uFE_MAIN_CTRL_fld_mode : 1;\
UNSG32 uFE_MAIN_CTRL_fld_init : 1;\
UNSG32 RSVDx10020_b4 : 28;\
}
union { UNSG32 u32Vpp_FE_MAIN_CTRL;
struct w32Vpp_FE_MAIN_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_PIP_CTRL_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_PIP_CTRL_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_PIP_CTRL_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_PIP_CTRL_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_FE_PIP_CTRL {\
UNSG32 uFE_PIP_CTRL_fld : 1;\
UNSG32 RSVDx10024_b1 : 31;\
}
union { UNSG32 u32Vpp_FE_PIP_CTRL;
struct w32Vpp_FE_PIP_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_OSD_CTRL_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_OSD_CTRL_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_OSD_CTRL_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_OSD_CTRL_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_FE_OSD_CTRL {\
UNSG32 uFE_OSD_CTRL_fld : 1;\
UNSG32 RSVDx10028_b1 : 31;\
}
union { UNSG32 u32Vpp_FE_OSD_CTRL;
struct w32Vpp_FE_OSD_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_PG_CTRL_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_PG_CTRL_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_PG_CTRL_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_PG_CTRL_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_FE_PG_CTRL {\
UNSG32 uFE_PG_CTRL_fld : 1;\
UNSG32 RSVDx1002C_b1 : 31;\
}
union { UNSG32 u32Vpp_FE_PG_CTRL;
struct w32Vpp_FE_PG_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB0_FLD_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB0_FLD_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB0_FLD_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB0_FLD_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_CPCB0_FLD {\
UNSG32 uCPCB0_FLD_fld : 1;\
UNSG32 RSVDx10030_b1 : 31;\
}
union { UNSG32 u32Vpp_CPCB0_FLD;
struct w32Vpp_CPCB0_FLD;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB2_FLD_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB2_FLD_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB2_FLD_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB2_FLD_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_CPCB2_FLD {\
UNSG32 uCPCB2_FLD_fld : 1;\
UNSG32 RSVDx10034_b1 : 31;\
}
union { UNSG32 u32Vpp_CPCB2_FLD;
struct w32Vpp_CPCB2_FLD;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_PAT_SEL_pat_sel(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_PAT_SEL_pat_sel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_PAT_SEL_pat_sel(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_PAT_SEL_pat_sel(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_FE_PAT_SEL {\
UNSG32 uFE_PAT_SEL_pat_sel : 1;\
UNSG32 RSVDx10038_b1 : 31;\
}
union { UNSG32 u32Vpp_FE_PAT_SEL;
struct w32Vpp_FE_PAT_SEL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_mainW_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_mainW_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_mainW_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_mainW_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_mainW_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_mainW_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_mainW_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_mainW_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_mainW {\
UNSG32 umainW_start : 1;\
UNSG32 umainW_clear : 1;\
UNSG32 RSVDx1003C_b2 : 30;\
}
union { UNSG32 u32Vpp_mainW;
struct w32Vpp_mainW;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_mainR_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_mainR_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_mainR_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_mainR_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_mainR_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_mainR_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_mainR_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_mainR_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_mainR_packsel(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_mainR_packsel(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_mainR_packsel(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_mainR_packsel(r16,v) _BFSET_(r16, 2, 2,v)
#define w32Vpp_mainR {\
UNSG32 umainR_start : 1;\
UNSG32 umainR_clear : 1;\
UNSG32 umainR_packsel : 1;\
UNSG32 RSVDx10040_b3 : 29;\
}
union { UNSG32 u32Vpp_mainR;
struct w32Vpp_mainR;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pipW_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_pipW_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_pipW_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_pipW_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_pipW_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_pipW_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_pipW_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_pipW_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_pipW {\
UNSG32 upipW_start : 1;\
UNSG32 upipW_clear : 1;\
UNSG32 RSVDx10044_b2 : 30;\
}
union { UNSG32 u32Vpp_pipW;
struct w32Vpp_pipW;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pipR_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_pipR_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_pipR_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_pipR_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_pipR_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_pipR_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_pipR_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_pipR_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_pipR_packsel(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_pipR_packsel(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_pipR_packsel(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_pipR_packsel(r16,v) _BFSET_(r16, 2, 2,v)
#define w32Vpp_pipR {\
UNSG32 upipR_start : 1;\
UNSG32 upipR_clear : 1;\
UNSG32 upipR_packsel : 1;\
UNSG32 RSVDx10048_b3 : 29;\
}
union { UNSG32 u32Vpp_pipR;
struct w32Vpp_pipR;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_auxW_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_auxW_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_auxW_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_auxW_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_auxW_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_auxW_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_auxW_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_auxW_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_auxW {\
UNSG32 uauxW_start : 1;\
UNSG32 uauxW_clear : 1;\
UNSG32 RSVDx1004C_b2 : 30;\
}
union { UNSG32 u32Vpp_auxW;
struct w32Vpp_auxW;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_auxR_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_auxR_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_auxR_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_auxR_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_auxR_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_auxR_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_auxR_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_auxR_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_auxR {\
UNSG32 uauxR_start : 1;\
UNSG32 uauxR_clear : 1;\
UNSG32 RSVDx10050_b2 : 30;\
}
union { UNSG32 u32Vpp_auxR;
struct w32Vpp_auxR;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_rst_lvds_phy(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_rst_lvds_phy(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_rst_lvds_phy(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_rst_lvds_phy(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_rst_be_ss(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_rst_be_ss(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_rst_be_ss(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_rst_be_ss(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_rst_vp_top(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_rst_vp_top(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_rst_vp_top(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_rst_vp_top(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_rst_hdmi_tx(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_rst_hdmi_tx(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_rst_hdmi_tx(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_rst_hdmi_tx(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_rst_video_enc(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_rst_video_enc(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_rst_video_enc(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_rst_video_enc(r16,v) _BFSET_(r16, 4, 4,v)
#define w32Vpp_rst {\
UNSG32 urst_lvds_phy : 1;\
UNSG32 urst_be_ss : 1;\
UNSG32 urst_vp_top : 1;\
UNSG32 urst_hdmi_tx : 1;\
UNSG32 urst_video_enc : 1;\
UNSG32 RSVDx10054_b5 : 27;\
}
union { UNSG32 u32Vpp_rst;
struct w32Vpp_rst;
};
///////////////////////////////////////////////////////////
SIE_VDAC_ctrl ie_VDAC_ctrl;
///////////////////////////////////////////////////////////
SIE_VDAC_sts ie_VDAC_sts;
///////////////////////////////////////////////////////////
SIE_HDMI_ctrl ie_HDMI_ctrl;
///////////////////////////////////////////////////////////
SIE_HDMI_sts ie_HDMI_sts;
///////////////////////////////////////////////////////////
#define GET32Vpp_regIfCtrl_mwrWidth(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_regIfCtrl_mwrWidth(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_regIfCtrl_mwrWidth(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_regIfCtrl_mwrWidth(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32Vpp_regIfCtrl_hold(r32) _BFGET_(r32,15, 8)
#define SET32Vpp_regIfCtrl_hold(r32,v) _BFSET_(r32,15, 8,v)
#define GET16Vpp_regIfCtrl_hold(r16) _BFGET_(r16,15, 8)
#define SET16Vpp_regIfCtrl_hold(r16,v) _BFSET_(r16,15, 8,v)
#define w32Vpp_regIfCtrl {\
UNSG32 uregIfCtrl_mwrWidth : 8;\
UNSG32 uregIfCtrl_hold : 8;\
UNSG32 RSVDx1007C_b16 : 16;\
}
union { UNSG32 u32Vpp_regIfCtrl;
struct w32Vpp_regIfCtrl;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MAIN_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_MAIN_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_MAIN_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_MAIN_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_MAIN_LSIZE {\
UNSG32 uMAIN_LSIZE_lsize : 9;\
UNSG32 RSVDx10080_b9 : 23;\
}
union { UNSG32 u32Vpp_MAIN_LSIZE;
struct w32Vpp_MAIN_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_PIP_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_PIP_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_PIP_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_PIP_LSIZE {\
UNSG32 uPIP_LSIZE_lsize : 9;\
UNSG32 RSVDx10084_b9 : 23;\
}
union { UNSG32 u32Vpp_PIP_LSIZE;
struct w32Vpp_PIP_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_OSD_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_OSD_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_OSD_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_OSD_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_OSD_LSIZE {\
UNSG32 uOSD_LSIZE_lsize : 9;\
UNSG32 RSVDx10088_b9 : 23;\
}
union { UNSG32 u32Vpp_OSD_LSIZE;
struct w32Vpp_OSD_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PG_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_PG_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_PG_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_PG_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_PG_LSIZE {\
UNSG32 uPG_LSIZE_lsize : 9;\
UNSG32 RSVDx1008C_b9 : 23;\
}
union { UNSG32 u32Vpp_PG_LSIZE;
struct w32Vpp_PG_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_AUX_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_AUX_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_AUX_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_AUX_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_AUX_LSIZE {\
UNSG32 uAUX_LSIZE_lsize : 9;\
UNSG32 RSVDx10090_b9 : 23;\
}
union { UNSG32 u32Vpp_AUX_LSIZE;
struct w32Vpp_AUX_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_vpIn_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_vpIn_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_vpIn_pix {\
UNSG32 uvpIn_pix_tot : 32;\
}
union { UNSG32 u32Vpp_vpIn_pix;
struct w32Vpp_vpIn_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_vpOut_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_vpOut_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_vpOut_pix {\
UNSG32 uvpOut_pix_tot : 32;\
}
union { UNSG32 u32Vpp_vpOut_pix;
struct w32Vpp_vpOut_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pip_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_pip_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_pip_pix {\
UNSG32 upip_pix_tot : 32;\
}
union { UNSG32 u32Vpp_pip_pix;
struct w32Vpp_pip_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_osd_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_osd_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_osd_pix {\
UNSG32 uosd_pix_tot : 32;\
}
union { UNSG32 u32Vpp_osd_pix;
struct w32Vpp_osd_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pg_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_pg_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_pg_pix {\
UNSG32 upg_pix_tot : 32;\
}
union { UNSG32 u32Vpp_pg_pix;
struct w32Vpp_pg_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_diW_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_diW_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_diW_pix {\
UNSG32 udiW_pix_tot : 32;\
}
union { UNSG32 u32Vpp_diW_pix;
struct w32Vpp_diW_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_diR_word_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_diR_word_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_diR_word {\
UNSG32 udiR_word_tot : 32;\
}
union { UNSG32 u32Vpp_diR_word;
struct w32Vpp_diR_word;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_mainW_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_mainW_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_mainW_pix {\
UNSG32 umainW_pix_tot : 32;\
}
union { UNSG32 u32Vpp_mainW_pix;
struct w32Vpp_mainW_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_mainR_word_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_mainR_word_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_mainR_word {\
UNSG32 umainR_word_tot : 32;\
}
union { UNSG32 u32Vpp_mainR_word;
struct w32Vpp_mainR_word;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pipW_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_pipW_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_pipW_pix {\
UNSG32 upipW_pix_tot : 32;\
}
union { UNSG32 u32Vpp_pipW_pix;
struct w32Vpp_pipW_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pipR_word_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_pipR_word_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_pipR_word {\
UNSG32 upipR_word_tot : 32;\
}
union { UNSG32 u32Vpp_pipR_word;
struct w32Vpp_pipR_word;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_auxW_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_auxW_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_auxW_pix {\
UNSG32 uauxW_pix_tot : 32;\
}
union { UNSG32 u32Vpp_auxW_pix;
struct w32Vpp_auxW_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_auxR_word_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_auxR_word_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_auxR_word {\
UNSG32 uauxR_word_tot : 32;\
}
union { UNSG32 u32Vpp_auxR_word;
struct w32Vpp_auxR_word;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_main_ols_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_main_ols_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_main_ols_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_main_ols_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_main_ols {\
UNSG32 umain_ols_en : 1;\
UNSG32 RSVDx100C8_b1 : 31;\
}
union { UNSG32 u32Vpp_main_ols;
struct w32Vpp_main_ols;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_pip_ols_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_pip_ols_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_pip_ols_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_pip_ols_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_pip_ols {\
UNSG32 upip_ols_en : 1;\
UNSG32 RSVDx100CC_b1 : 31;\
}
union { UNSG32 u32Vpp_pip_ols;
struct w32Vpp_pip_ols;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_enc_hsvs_sel_sel(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_enc_hsvs_sel_sel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_enc_hsvs_sel_sel(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_enc_hsvs_sel_sel(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_enc_hsvs_sel {\
UNSG32 uenc_hsvs_sel_sel : 1;\
UNSG32 RSVDx100D0_b1 : 31;\
}
union { UNSG32 u32Vpp_enc_hsvs_sel;
struct w32Vpp_enc_hsvs_sel;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_0(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_0(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_0(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_0(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_1(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_1(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_2(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_2(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_2(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_2(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_3(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_3(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_3(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_3(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_4(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_4(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_4(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_4(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_5(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_5(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_5(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_5(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb0_6(r32) _BFGET_(r32, 6, 6)
#define SET32Vpp_CPCB_FIFO_UF_cpcb0_6(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb0_6(r16) _BFGET_(r16, 6, 6)
#define SET16Vpp_CPCB_FIFO_UF_cpcb0_6(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_0(r32) _BFGET_(r32, 7, 7)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_0(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_0(r16) _BFGET_(r16, 7, 7)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_0(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_1(r32) _BFGET_(r32, 8, 8)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_1(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_1(r16) _BFGET_(r16, 8, 8)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_1(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_2(r32) _BFGET_(r32, 9, 9)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_2(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_2(r16) _BFGET_(r16, 9, 9)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_2(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_3(r32) _BFGET_(r32,10,10)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_3(r32,v) _BFSET_(r32,10,10,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_3(r16) _BFGET_(r16,10,10)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_3(r16,v) _BFSET_(r16,10,10,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_4(r32) _BFGET_(r32,11,11)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_4(r32,v) _BFSET_(r32,11,11,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_4(r16) _BFGET_(r16,11,11)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_4(r16,v) _BFSET_(r16,11,11,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_5(r32) _BFGET_(r32,12,12)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_5(r32,v) _BFSET_(r32,12,12,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_5(r16) _BFGET_(r16,12,12)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_5(r16,v) _BFSET_(r16,12,12,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb1_6(r32) _BFGET_(r32,13,13)
#define SET32Vpp_CPCB_FIFO_UF_cpcb1_6(r32,v) _BFSET_(r32,13,13,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb1_6(r16) _BFGET_(r16,13,13)
#define SET16Vpp_CPCB_FIFO_UF_cpcb1_6(r16,v) _BFSET_(r16,13,13,v)
#define GET32Vpp_CPCB_FIFO_UF_cpcb2_0(r32) _BFGET_(r32,14,14)
#define SET32Vpp_CPCB_FIFO_UF_cpcb2_0(r32,v) _BFSET_(r32,14,14,v)
#define GET16Vpp_CPCB_FIFO_UF_cpcb2_0(r16) _BFGET_(r16,14,14)
#define SET16Vpp_CPCB_FIFO_UF_cpcb2_0(r16,v) _BFSET_(r16,14,14,v)
#define w32Vpp_CPCB_FIFO_UF {\
UNSG32 uCPCB_FIFO_UF_cpcb0_0 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_1 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_2 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_3 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_4 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_5 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb0_6 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_0 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_1 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_2 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_3 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_4 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_5 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb1_6 : 1;\
UNSG32 uCPCB_FIFO_UF_cpcb2_0 : 1;\
UNSG32 RSVDx100D4_b15 : 17;\
}
union { UNSG32 u32Vpp_CPCB_FIFO_UF;
struct w32Vpp_CPCB_FIFO_UF;
};
///////////////////////////////////////////////////////////
SIE_TG ie_VP_TG;
///////////////////////////////////////////////////////////
UNSG8 RSVDx10108 [760];
///////////////////////////////////////////////////////////
SIE_LDR ie_LDR;
///////////////////////////////////////////////////////////
#define GET32Vpp_HDMI2DVAO_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_HDMI2DVAO_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_HDMI2DVAO_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_HDMI2DVAO_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_HDMI2DVAO {\
UNSG32 uHDMI2DVAO_en : 1;\
UNSG32 RSVDx12C00_b1 : 31;\
}
union { UNSG32 u32Vpp_HDMI2DVAO;
struct w32Vpp_HDMI2DVAO;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_CTRL_sw_sel(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_VP_DMX_CTRL_sw_sel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_VP_DMX_CTRL_sw_sel(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_VP_DMX_CTRL_sw_sel(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_VP_DMX_CTRL {\
UNSG32 uVP_DMX_CTRL_sw_sel : 1;\
UNSG32 RSVDx12C04_b1 : 31;\
}
union { UNSG32 u32Vpp_VP_DMX_CTRL;
struct w32Vpp_VP_DMX_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_HRES_hres(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_VP_DMX_HRES_hres(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_VP_DMX_HRES_hres(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_VP_DMX_HRES_hres(r16,v) _BFSET_(r16,11, 0,v)
#define w32Vpp_VP_DMX_HRES {\
UNSG32 uVP_DMX_HRES_hres : 12;\
UNSG32 RSVDx12C08_b12 : 20;\
}
union { UNSG32 u32Vpp_VP_DMX_HRES;
struct w32Vpp_VP_DMX_HRES;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_HT_ht(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_VP_DMX_HT_ht(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_VP_DMX_HT_ht(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_VP_DMX_HT_ht(r16,v) _BFSET_(r16,11, 0,v)
#define w32Vpp_VP_DMX_HT {\
UNSG32 uVP_DMX_HT_ht : 12;\
UNSG32 RSVDx12C0C_b12 : 20;\
}
union { UNSG32 u32Vpp_VP_DMX_HT;
struct w32Vpp_VP_DMX_HT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_VRES_vres(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_VP_DMX_VRES_vres(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_VP_DMX_VRES_vres(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_VP_DMX_VRES_vres(r16,v) _BFSET_(r16,11, 0,v)
#define w32Vpp_VP_DMX_VRES {\
UNSG32 uVP_DMX_VRES_vres : 12;\
UNSG32 RSVDx12C10_b12 : 20;\
}
union { UNSG32 u32Vpp_VP_DMX_VRES;
struct w32Vpp_VP_DMX_VRES;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_VT_vt(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_VP_DMX_VT_vt(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_VP_DMX_VT_vt(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_VP_DMX_VT_vt(r16,v) _BFSET_(r16,11, 0,v)
#define w32Vpp_VP_DMX_VT {\
UNSG32 uVP_DMX_VT_vt : 12;\
UNSG32 RSVDx12C14_b12 : 20;\
}
union { UNSG32 u32Vpp_VP_DMX_VT;
struct w32Vpp_VP_DMX_VT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VP_DMX_IVT_ivt(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_VP_DMX_IVT_ivt(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_VP_DMX_IVT_ivt(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_VP_DMX_IVT_ivt(r16,v) _BFSET_(r16,11, 0,v)
#define w32Vpp_VP_DMX_IVT {\
UNSG32 uVP_DMX_IVT_ivt : 12;\
UNSG32 RSVDx12C18_b12 : 20;\
}
union { UNSG32 u32Vpp_VP_DMX_IVT;
struct w32Vpp_VP_DMX_IVT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB0_PL_EN_Main(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB0_PL_EN_Main(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB0_PL_EN_Main(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB0_PL_EN_Main(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_CPCB0_PL_EN_PIP(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_CPCB0_PL_EN_PIP(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_CPCB0_PL_EN_PIP(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_CPCB0_PL_EN_PIP(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_CPCB0_PL_EN_IG(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_CPCB0_PL_EN_IG(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_CPCB0_PL_EN_IG(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_CPCB0_PL_EN_IG(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_CPCB0_PL_EN_PG(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_CPCB0_PL_EN_PG(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_CPCB0_PL_EN_PG(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_CPCB0_PL_EN_PG(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_CPCB0_PL_EN_Cursor(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_CPCB0_PL_EN_Cursor(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_CPCB0_PL_EN_Cursor(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_CPCB0_PL_EN_Cursor(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_CPCB0_PL_EN_MOSD(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_CPCB0_PL_EN_MOSD(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_CPCB0_PL_EN_MOSD(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_CPCB0_PL_EN_MOSD(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Vpp_CPCB0_PL_EN_BG(r32) _BFGET_(r32, 6, 6)
#define SET32Vpp_CPCB0_PL_EN_BG(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Vpp_CPCB0_PL_EN_BG(r16) _BFGET_(r16, 6, 6)
#define SET16Vpp_CPCB0_PL_EN_BG(r16,v) _BFSET_(r16, 6, 6,v)
#define w32Vpp_CPCB0_PL_EN {\
UNSG32 uCPCB0_PL_EN_Main : 1;\
UNSG32 uCPCB0_PL_EN_PIP : 1;\
UNSG32 uCPCB0_PL_EN_IG : 1;\
UNSG32 uCPCB0_PL_EN_PG : 1;\
UNSG32 uCPCB0_PL_EN_Cursor : 1;\
UNSG32 uCPCB0_PL_EN_MOSD : 1;\
UNSG32 uCPCB0_PL_EN_BG : 1;\
UNSG32 RSVDx12C1C_b7 : 25;\
}
union { UNSG32 u32Vpp_CPCB0_PL_EN;
struct w32Vpp_CPCB0_PL_EN;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB1_PL_EN_Main(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB1_PL_EN_Main(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB1_PL_EN_Main(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB1_PL_EN_Main(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_CPCB1_PL_EN_PIP(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_CPCB1_PL_EN_PIP(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_CPCB1_PL_EN_PIP(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_CPCB1_PL_EN_PIP(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_CPCB1_PL_EN_IG(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_CPCB1_PL_EN_IG(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_CPCB1_PL_EN_IG(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_CPCB1_PL_EN_IG(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_CPCB1_PL_EN_PG(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_CPCB1_PL_EN_PG(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_CPCB1_PL_EN_PG(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_CPCB1_PL_EN_PG(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_CPCB1_PL_EN_Cursor(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_CPCB1_PL_EN_Cursor(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_CPCB1_PL_EN_Cursor(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_CPCB1_PL_EN_Cursor(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_CPCB1_PL_EN_MOSD(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_CPCB1_PL_EN_MOSD(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_CPCB1_PL_EN_MOSD(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_CPCB1_PL_EN_MOSD(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Vpp_CPCB1_PL_EN_BG(r32) _BFGET_(r32, 6, 6)
#define SET32Vpp_CPCB1_PL_EN_BG(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Vpp_CPCB1_PL_EN_BG(r16) _BFGET_(r16, 6, 6)
#define SET16Vpp_CPCB1_PL_EN_BG(r16,v) _BFSET_(r16, 6, 6,v)
#define w32Vpp_CPCB1_PL_EN {\
UNSG32 uCPCB1_PL_EN_Main : 1;\
UNSG32 uCPCB1_PL_EN_PIP : 1;\
UNSG32 uCPCB1_PL_EN_IG : 1;\
UNSG32 uCPCB1_PL_EN_PG : 1;\
UNSG32 uCPCB1_PL_EN_Cursor : 1;\
UNSG32 uCPCB1_PL_EN_MOSD : 1;\
UNSG32 uCPCB1_PL_EN_BG : 1;\
UNSG32 RSVDx12C20_b7 : 25;\
}
union { UNSG32 u32Vpp_CPCB1_PL_EN;
struct w32Vpp_CPCB1_PL_EN;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MAIN_WCLIENT_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_MAIN_WCLIENT_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_MAIN_WCLIENT_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_MAIN_WCLIENT_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_MAIN_WCLIENT {\
UNSG32 uMAIN_WCLIENT_en : 1;\
UNSG32 RSVDx12C24_b1 : 31;\
}
union { UNSG32 u32Vpp_MAIN_WCLIENT;
struct w32Vpp_MAIN_WCLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_WCLIENT_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_PIP_WCLIENT_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_PIP_WCLIENT_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_PIP_WCLIENT_en(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_PIP_WCLIENT {\
UNSG32 uPIP_WCLIENT_en : 1;\
UNSG32 RSVDx12C28_b1 : 31;\
}
union { UNSG32 u32Vpp_PIP_WCLIENT;
struct w32Vpp_PIP_WCLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DIW_CLIENT_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_DIW_CLIENT_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_DIW_CLIENT_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DIW_CLIENT_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_DIW_CLIENT_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_DIW_CLIENT_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_DIW_CLIENT_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_DIW_CLIENT_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_DIW_CLIENT {\
UNSG32 uDIW_CLIENT_start : 1;\
UNSG32 uDIW_CLIENT_clear : 1;\
UNSG32 RSVDx12C2C_b2 : 30;\
}
union { UNSG32 u32Vpp_DIW_CLIENT;
struct w32Vpp_DIW_CLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DIR0_CLIENT_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_DIR0_CLIENT_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_DIR0_CLIENT_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DIR0_CLIENT_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_DIR0_CLIENT_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_DIR0_CLIENT_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_DIR0_CLIENT_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_DIR0_CLIENT_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_DIR0_CLIENT {\
UNSG32 uDIR0_CLIENT_start : 1;\
UNSG32 uDIR0_CLIENT_clear : 1;\
UNSG32 RSVDx12C30_b2 : 30;\
}
union { UNSG32 u32Vpp_DIR0_CLIENT;
struct w32Vpp_DIR0_CLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DIR1_CLIENT_start(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_DIR1_CLIENT_start(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_DIR1_CLIENT_start(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DIR1_CLIENT_start(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_DIR1_CLIENT_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_DIR1_CLIENT_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_DIR1_CLIENT_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_DIR1_CLIENT_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_DIR1_CLIENT {\
UNSG32 uDIR1_CLIENT_start : 1;\
UNSG32 uDIR1_CLIENT_clear : 1;\
UNSG32 RSVDx12C34_b2 : 30;\
}
union { UNSG32 u32Vpp_DIR1_CLIENT;
struct w32Vpp_DIR1_CLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_SD_TT_CLIENT_enable(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_SD_TT_CLIENT_enable(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_SD_TT_CLIENT_enable(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_SD_TT_CLIENT_enable(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_SD_TT_CLIENT_clear(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_SD_TT_CLIENT_clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_SD_TT_CLIENT_clear(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_SD_TT_CLIENT_clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_SD_TT_CLIENT {\
UNSG32 uSD_TT_CLIENT_enable : 1;\
UNSG32 uSD_TT_CLIENT_clear : 1;\
UNSG32 RSVDx12C38_b2 : 30;\
}
union { UNSG32 u32Vpp_SD_TT_CLIENT;
struct w32Vpp_SD_TT_CLIENT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_SD_TT_BYTE_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_SD_TT_BYTE_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_SD_TT_BYTE {\
UNSG32 uSD_TT_BYTE_tot : 32;\
}
union { UNSG32 u32Vpp_SD_TT_BYTE;
struct w32Vpp_SD_TT_BYTE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DAC_RAMP_CTRL_start(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_DAC_RAMP_CTRL_start(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_DAC_RAMP_CTRL_start(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_DAC_RAMP_CTRL_start(r16,v) _BFSET_(r16,11, 0,v)
#define GET32Vpp_DAC_RAMP_CTRL_stop(r32) _BFGET_(r32,23,12)
#define SET32Vpp_DAC_RAMP_CTRL_stop(r32,v) _BFSET_(r32,23,12,v)
#define GET32Vpp_DAC_RAMP_CTRL_step(r32) _BFGET_(r32,31,24)
#define SET32Vpp_DAC_RAMP_CTRL_step(r32,v) _BFSET_(r32,31,24,v)
#define GET16Vpp_DAC_RAMP_CTRL_step(r16) _BFGET_(r16,15, 8)
#define SET16Vpp_DAC_RAMP_CTRL_step(r16,v) _BFSET_(r16,15, 8,v)
#define w32Vpp_DAC_RAMP_CTRL {\
UNSG32 uDAC_RAMP_CTRL_start : 12;\
UNSG32 uDAC_RAMP_CTRL_stop : 12;\
UNSG32 uDAC_RAMP_CTRL_step : 8;\
}
union { UNSG32 u32Vpp_DAC_RAMP_CTRL;
struct w32Vpp_DAC_RAMP_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DAC_TEST_CTRL_sel(r32) _BFGET_(r32, 1, 0)
#define SET32Vpp_DAC_TEST_CTRL_sel(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16Vpp_DAC_TEST_CTRL_sel(r16) _BFGET_(r16, 1, 0)
#define SET16Vpp_DAC_TEST_CTRL_sel(r16,v) _BFSET_(r16, 1, 0,v)
#define w32Vpp_DAC_TEST_CTRL {\
UNSG32 uDAC_TEST_CTRL_sel : 2;\
UNSG32 RSVDx12C44_b2 : 30;\
}
union { UNSG32 u32Vpp_DAC_TEST_CTRL;
struct w32Vpp_DAC_TEST_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_SCL_CLKEN_CTRL_Main(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_SCL_CLKEN_CTRL_Main(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_SCL_CLKEN_CTRL_Main(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_SCL_CLKEN_CTRL_Main(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_SCL_CLKEN_CTRL_PIP(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_SCL_CLKEN_CTRL_PIP(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_SCL_CLKEN_CTRL_PIP(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_SCL_CLKEN_CTRL_PIP(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_SCL_CLKEN_CTRL_IG(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_SCL_CLKEN_CTRL_IG(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_SCL_CLKEN_CTRL_IG(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_SCL_CLKEN_CTRL_IG(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_SCL_CLKEN_CTRL_PG(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_SCL_CLKEN_CTRL_PG(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_SCL_CLKEN_CTRL_PG(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_SCL_CLKEN_CTRL_PG(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_SCL_CLKEN_CTRL_AUX(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_SCL_CLKEN_CTRL_AUX(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_SCL_CLKEN_CTRL_AUX(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_SCL_CLKEN_CTRL_AUX(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_SCL_CLKEN_CTRL_MOSD(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_SCL_CLKEN_CTRL_MOSD(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_SCL_CLKEN_CTRL_MOSD(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_SCL_CLKEN_CTRL_MOSD(r16,v) _BFSET_(r16, 5, 5,v)
#define w32Vpp_SCL_CLKEN_CTRL {\
UNSG32 uSCL_CLKEN_CTRL_Main : 1;\
UNSG32 uSCL_CLKEN_CTRL_PIP : 1;\
UNSG32 uSCL_CLKEN_CTRL_IG : 1;\
UNSG32 uSCL_CLKEN_CTRL_PG : 1;\
UNSG32 uSCL_CLKEN_CTRL_AUX : 1;\
UNSG32 uSCL_CLKEN_CTRL_MOSD : 1;\
UNSG32 RSVDx12C48_b6 : 26;\
}
union { UNSG32 u32Vpp_SCL_CLKEN_CTRL;
struct w32Vpp_SCL_CLKEN_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PAT_DNS_CTRL_cblank(r32) _BFGET_(r32,11, 0)
#define SET32Vpp_PAT_DNS_CTRL_cblank(r32,v) _BFSET_(r32,11, 0,v)
#define GET16Vpp_PAT_DNS_CTRL_cblank(r16) _BFGET_(r16,11, 0)
#define SET16Vpp_PAT_DNS_CTRL_cblank(r16,v) _BFSET_(r16,11, 0,v)
#define GET32Vpp_PAT_DNS_CTRL_enable(r32) _BFGET_(r32,12,12)
#define SET32Vpp_PAT_DNS_CTRL_enable(r32,v) _BFSET_(r32,12,12,v)
#define GET16Vpp_PAT_DNS_CTRL_enable(r16) _BFGET_(r16,12,12)
#define SET16Vpp_PAT_DNS_CTRL_enable(r16,v) _BFSET_(r16,12,12,v)
#define w32Vpp_PAT_DNS_CTRL {\
UNSG32 uPAT_DNS_CTRL_cblank : 12;\
UNSG32 uPAT_DNS_CTRL_enable : 1;\
UNSG32 RSVDx12C4C_b13 : 19;\
}
union { UNSG32 u32Vpp_PAT_DNS_CTRL;
struct w32Vpp_PAT_DNS_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB0_FLD_STS_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB0_FLD_STS_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB0_FLD_STS_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB0_FLD_STS_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_CPCB0_FLD_STS {\
UNSG32 uCPCB0_FLD_STS_fld : 1;\
UNSG32 RSVDx12C50_b1 : 31;\
}
union { UNSG32 u32Vpp_CPCB0_FLD_STS;
struct w32Vpp_CPCB0_FLD_STS;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CPCB2_FLD_STS_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_CPCB2_FLD_STS_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_CPCB2_FLD_STS_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_CPCB2_FLD_STS_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_CPCB2_FLD_STS {\
UNSG32 uCPCB2_FLD_STS_fld : 1;\
UNSG32 RSVDx12C54_b1 : 31;\
}
union { UNSG32 u32Vpp_CPCB2_FLD_STS;
struct w32Vpp_CPCB2_FLD_STS;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_SD_TT_TEST_data(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_SD_TT_TEST_data(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_SD_TT_TEST_data(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_SD_TT_TEST_data(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32Vpp_SD_TT_TEST_sel(r32) _BFGET_(r32, 8, 8)
#define SET32Vpp_SD_TT_TEST_sel(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Vpp_SD_TT_TEST_sel(r16) _BFGET_(r16, 8, 8)
#define SET16Vpp_SD_TT_TEST_sel(r16,v) _BFSET_(r16, 8, 8,v)
#define w32Vpp_SD_TT_TEST {\
UNSG32 uSD_TT_TEST_data : 8;\
UNSG32 uSD_TT_TEST_sel : 1;\
UNSG32 RSVDx12C58_b9 : 23;\
}
union { UNSG32 u32Vpp_SD_TT_TEST;
struct w32Vpp_SD_TT_TEST;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DUMMY0_ctrl(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_DUMMY0_ctrl(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_DUMMY0 {\
UNSG32 uDUMMY0_ctrl : 32;\
}
union { UNSG32 u32Vpp_DUMMY0;
struct w32Vpp_DUMMY0;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DEBUG0_diCnt(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_DEBUG0_diCnt(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_DEBUG0_diCnt(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_DEBUG0_diCnt(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32Vpp_DEBUG0_insert_frame(r32) _BFGET_(r32, 8, 8)
#define SET32Vpp_DEBUG0_insert_frame(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Vpp_DEBUG0_insert_frame(r16) _BFGET_(r16, 8, 8)
#define SET16Vpp_DEBUG0_insert_frame(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Vpp_DEBUG0_drop_frame(r32) _BFGET_(r32, 9, 9)
#define SET32Vpp_DEBUG0_drop_frame(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Vpp_DEBUG0_drop_frame(r16) _BFGET_(r16, 9, 9)
#define SET16Vpp_DEBUG0_drop_frame(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Vpp_DEBUG0_film_det_32(r32) _BFGET_(r32,10,10)
#define SET32Vpp_DEBUG0_film_det_32(r32,v) _BFSET_(r32,10,10,v)
#define GET16Vpp_DEBUG0_film_det_32(r16) _BFGET_(r16,10,10)
#define SET16Vpp_DEBUG0_film_det_32(r16,v) _BFSET_(r16,10,10,v)
#define GET32Vpp_DEBUG0_vIFifoDone(r32) _BFGET_(r32,11,11)
#define SET32Vpp_DEBUG0_vIFifoDone(r32,v) _BFSET_(r32,11,11,v)
#define GET16Vpp_DEBUG0_vIFifoDone(r16) _BFGET_(r16,11,11)
#define SET16Vpp_DEBUG0_vIFifoDone(r16,v) _BFSET_(r16,11,11,v)
#define GET32Vpp_DEBUG0_vOFifoDone(r32) _BFGET_(r32,12,12)
#define SET32Vpp_DEBUG0_vOFifoDone(r32,v) _BFSET_(r32,12,12,v)
#define GET16Vpp_DEBUG0_vOFifoDone(r16) _BFGET_(r16,12,12)
#define SET16Vpp_DEBUG0_vOFifoDone(r16,v) _BFSET_(r16,12,12,v)
#define GET32Vpp_DEBUG0_pipFifoDone(r32) _BFGET_(r32,13,13)
#define SET32Vpp_DEBUG0_pipFifoDone(r32,v) _BFSET_(r32,13,13,v)
#define GET16Vpp_DEBUG0_pipFifoDone(r16) _BFGET_(r16,13,13)
#define SET16Vpp_DEBUG0_pipFifoDone(r16,v) _BFSET_(r16,13,13,v)
#define GET32Vpp_DEBUG0_igFifoDone(r32) _BFGET_(r32,14,14)
#define SET32Vpp_DEBUG0_igFifoDone(r32,v) _BFSET_(r32,14,14,v)
#define GET16Vpp_DEBUG0_igFifoDone(r16) _BFGET_(r16,14,14)
#define SET16Vpp_DEBUG0_igFifoDone(r16,v) _BFSET_(r16,14,14,v)
#define GET32Vpp_DEBUG0_pgFifoDone(r32) _BFGET_(r32,15,15)
#define SET32Vpp_DEBUG0_pgFifoDone(r32,v) _BFSET_(r32,15,15,v)
#define GET16Vpp_DEBUG0_pgFifoDone(r16) _BFGET_(r16,15,15)
#define SET16Vpp_DEBUG0_pgFifoDone(r16,v) _BFSET_(r16,15,15,v)
#define GET32Vpp_DEBUG0_mosdFifoDone(r32) _BFGET_(r32,16,16)
#define SET32Vpp_DEBUG0_mosdFifoDone(r32,v) _BFSET_(r32,16,16,v)
#define GET16Vpp_DEBUG0_mosdFifoDone(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DEBUG0_mosdFifoDone(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_DEBUG0 {\
UNSG32 uDEBUG0_diCnt : 8;\
UNSG32 uDEBUG0_insert_frame : 1;\
UNSG32 uDEBUG0_drop_frame : 1;\
UNSG32 uDEBUG0_film_det_32 : 1;\
UNSG32 uDEBUG0_vIFifoDone : 1;\
UNSG32 uDEBUG0_vOFifoDone : 1;\
UNSG32 uDEBUG0_pipFifoDone : 1;\
UNSG32 uDEBUG0_igFifoDone : 1;\
UNSG32 uDEBUG0_pgFifoDone : 1;\
UNSG32 uDEBUG0_mosdFifoDone : 1;\
UNSG32 RSVDx12C60_b17 : 15;\
}
union { UNSG32 u32Vpp_DEBUG0;
struct w32Vpp_DEBUG0;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MAIN_SCL_CROP_ctrl(r32) _BFGET_(r32, 2, 0)
#define SET32Vpp_MAIN_SCL_CROP_ctrl(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Vpp_MAIN_SCL_CROP_ctrl(r16) _BFGET_(r16, 2, 0)
#define SET16Vpp_MAIN_SCL_CROP_ctrl(r16,v) _BFSET_(r16, 2, 0,v)
#define w32Vpp_MAIN_SCL_CROP {\
UNSG32 uMAIN_SCL_CROP_ctrl : 3;\
UNSG32 RSVDx12C64_b3 : 29;\
}
union { UNSG32 u32Vpp_MAIN_SCL_CROP;
struct w32Vpp_MAIN_SCL_CROP;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_SCL_CROP_ctrl(r32) _BFGET_(r32, 2, 0)
#define SET32Vpp_PIP_SCL_CROP_ctrl(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16Vpp_PIP_SCL_CROP_ctrl(r16) _BFGET_(r16, 2, 0)
#define SET16Vpp_PIP_SCL_CROP_ctrl(r16,v) _BFSET_(r16, 2, 0,v)
#define w32Vpp_PIP_SCL_CROP {\
UNSG32 uPIP_SCL_CROP_ctrl : 3;\
UNSG32 RSVDx12C68_b3 : 29;\
}
union { UNSG32 u32Vpp_PIP_SCL_CROP;
struct w32Vpp_PIP_SCL_CROP;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_LUMA_KEY_en(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_PIP_LUMA_KEY_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_PIP_LUMA_KEY_en(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_PIP_LUMA_KEY_en(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_PIP_LUMA_KEY_min(r32) _BFGET_(r32, 8, 1)
#define SET32Vpp_PIP_LUMA_KEY_min(r32,v) _BFSET_(r32, 8, 1,v)
#define GET16Vpp_PIP_LUMA_KEY_min(r16) _BFGET_(r16, 8, 1)
#define SET16Vpp_PIP_LUMA_KEY_min(r16,v) _BFSET_(r16, 8, 1,v)
#define GET32Vpp_PIP_LUMA_KEY_max(r32) _BFGET_(r32,16, 9)
#define SET32Vpp_PIP_LUMA_KEY_max(r32,v) _BFSET_(r32,16, 9,v)
#define w32Vpp_PIP_LUMA_KEY {\
UNSG32 uPIP_LUMA_KEY_en : 1;\
UNSG32 uPIP_LUMA_KEY_min : 8;\
UNSG32 uPIP_LUMA_KEY_max : 8;\
UNSG32 RSVDx12C6C_b17 : 15;\
}
union { UNSG32 u32Vpp_PIP_LUMA_KEY;
struct w32Vpp_PIP_LUMA_KEY;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_AL_IN_hit_al(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_PIP_AL_IN_hit_al(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_PIP_AL_IN_hit_al(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_PIP_AL_IN_hit_al(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32Vpp_PIP_AL_IN_non_hit_al(r32) _BFGET_(r32,15, 8)
#define SET32Vpp_PIP_AL_IN_non_hit_al(r32,v) _BFSET_(r32,15, 8,v)
#define GET16Vpp_PIP_AL_IN_non_hit_al(r16) _BFGET_(r16,15, 8)
#define SET16Vpp_PIP_AL_IN_non_hit_al(r16,v) _BFSET_(r16,15, 8,v)
#define w32Vpp_PIP_AL_IN {\
UNSG32 uPIP_AL_IN_hit_al : 8;\
UNSG32 uPIP_AL_IN_non_hit_al : 8;\
UNSG32 RSVDx12C70_b16 : 16;\
}
union { UNSG32 u32Vpp_PIP_AL_IN;
struct w32Vpp_PIP_AL_IN;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_AL_OUT_threshold(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_PIP_AL_OUT_threshold(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_PIP_AL_OUT_threshold(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_PIP_AL_OUT_threshold(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32Vpp_PIP_AL_OUT_zero_luma(r32) _BFGET_(r32,15, 8)
#define SET32Vpp_PIP_AL_OUT_zero_luma(r32,v) _BFSET_(r32,15, 8,v)
#define GET16Vpp_PIP_AL_OUT_zero_luma(r16) _BFGET_(r16,15, 8)
#define SET16Vpp_PIP_AL_OUT_zero_luma(r16,v) _BFSET_(r16,15, 8,v)
#define w32Vpp_PIP_AL_OUT {\
UNSG32 uPIP_AL_OUT_threshold : 8;\
UNSG32 uPIP_AL_OUT_zero_luma : 8;\
UNSG32 RSVDx12C74_b16 : 16;\
}
union { UNSG32 u32Vpp_PIP_AL_OUT;
struct w32Vpp_PIP_AL_OUT;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_mosd_pix_tot(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_mosd_pix_tot(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_mosd_pix {\
UNSG32 umosd_pix_tot : 32;\
}
union { UNSG32 u32Vpp_mosd_pix;
struct w32Vpp_mosd_pix;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MOSD_LSIZE_lsize(r32) _BFGET_(r32, 8, 0)
#define SET32Vpp_MOSD_LSIZE_lsize(r32,v) _BFSET_(r32, 8, 0,v)
#define GET16Vpp_MOSD_LSIZE_lsize(r16) _BFGET_(r16, 8, 0)
#define SET16Vpp_MOSD_LSIZE_lsize(r16,v) _BFSET_(r16, 8, 0,v)
#define w32Vpp_MOSD_LSIZE {\
UNSG32 uMOSD_LSIZE_lsize : 9;\
UNSG32 RSVDx12C7C_b9 : 23;\
}
union { UNSG32 u32Vpp_MOSD_LSIZE;
struct w32Vpp_MOSD_LSIZE;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_FE_MOSD_CTRL_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_FE_MOSD_CTRL_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_FE_MOSD_CTRL_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_FE_MOSD_CTRL_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_FE_MOSD_CTRL {\
UNSG32 uFE_MOSD_CTRL_fld : 1;\
UNSG32 RSVDx12C80_b1 : 31;\
}
union { UNSG32 u32Vpp_FE_MOSD_CTRL;
struct w32Vpp_FE_MOSD_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_OVERLAY_MUX_MAIN(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_OVERLAY_MUX_MAIN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_OVERLAY_MUX_MAIN(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_OVERLAY_MUX_MAIN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_OVERLAY_MUX_PIP(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_OVERLAY_MUX_PIP(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_OVERLAY_MUX_PIP(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_OVERLAY_MUX_PIP(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_OVERLAY_MUX_IG(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_OVERLAY_MUX_IG(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_OVERLAY_MUX_IG(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_OVERLAY_MUX_IG(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_OVERLAY_MUX_PG(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_OVERLAY_MUX_PG(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_OVERLAY_MUX_PG(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_OVERLAY_MUX_PG(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_OVERLAY_MUX_MOSD(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_OVERLAY_MUX_MOSD(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_OVERLAY_MUX_MOSD(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_OVERLAY_MUX_MOSD(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_OVERLAY_MUX_CURSOR(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_OVERLAY_MUX_CURSOR(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_OVERLAY_MUX_CURSOR(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_OVERLAY_MUX_CURSOR(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Vpp_OVERLAY_MUX_BG(r32) _BFGET_(r32, 6, 6)
#define SET32Vpp_OVERLAY_MUX_BG(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Vpp_OVERLAY_MUX_BG(r16) _BFGET_(r16, 6, 6)
#define SET16Vpp_OVERLAY_MUX_BG(r16,v) _BFSET_(r16, 6, 6,v)
#define w32Vpp_OVERLAY_MUX {\
UNSG32 uOVERLAY_MUX_MAIN : 1;\
UNSG32 uOVERLAY_MUX_PIP : 1;\
UNSG32 uOVERLAY_MUX_IG : 1;\
UNSG32 uOVERLAY_MUX_PG : 1;\
UNSG32 uOVERLAY_MUX_MOSD : 1;\
UNSG32 uOVERLAY_MUX_CURSOR : 1;\
UNSG32 uOVERLAY_MUX_BG : 1;\
UNSG32 RSVDx12C84_b7 : 25;\
}
union { UNSG32 u32Vpp_OVERLAY_MUX;
struct w32Vpp_OVERLAY_MUX;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MAIN_OV_FXD_IMG_REG(r32) _BFGET_(r32,23, 0)
#define SET32Vpp_MAIN_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,23, 0,v)
#define w32Vpp_MAIN_OV_FXD_IMG {\
UNSG32 uMAIN_OV_FXD_IMG_REG : 24;\
UNSG32 RSVDx12C88_b24 : 8;\
}
union { UNSG32 u32Vpp_MAIN_OV_FXD_IMG;
struct w32Vpp_MAIN_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PIP_OV_FXD_IMG_REG(r32) _BFGET_(r32,23, 0)
#define SET32Vpp_PIP_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,23, 0,v)
#define w32Vpp_PIP_OV_FXD_IMG {\
UNSG32 uPIP_OV_FXD_IMG_REG : 24;\
UNSG32 RSVDx12C8C_b24 : 8;\
}
union { UNSG32 u32Vpp_PIP_OV_FXD_IMG;
struct w32Vpp_PIP_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_IG_OV_FXD_IMG_REG(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_IG_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_IG_OV_FXD_IMG {\
UNSG32 uIG_OV_FXD_IMG_REG : 32;\
}
union { UNSG32 u32Vpp_IG_OV_FXD_IMG;
struct w32Vpp_IG_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_PG_OV_FXD_IMG_REG(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_PG_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_PG_OV_FXD_IMG {\
UNSG32 uPG_OV_FXD_IMG_REG : 32;\
}
union { UNSG32 u32Vpp_PG_OV_FXD_IMG;
struct w32Vpp_PG_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_CURSOR_OV_FXD_IMG_REG(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_CURSOR_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_CURSOR_OV_FXD_IMG {\
UNSG32 uCURSOR_OV_FXD_IMG_REG : 32;\
}
union { UNSG32 u32Vpp_CURSOR_OV_FXD_IMG;
struct w32Vpp_CURSOR_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_MOSD_OV_FXD_IMG_REG(r32) _BFGET_(r32,31, 0)
#define SET32Vpp_MOSD_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,31, 0,v)
#define w32Vpp_MOSD_OV_FXD_IMG {\
UNSG32 uMOSD_OV_FXD_IMG_REG : 32;\
}
union { UNSG32 u32Vpp_MOSD_OV_FXD_IMG;
struct w32Vpp_MOSD_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_BG_OV_FXD_IMG_REG(r32) _BFGET_(r32,15, 0)
#define SET32Vpp_BG_OV_FXD_IMG_REG(r32,v) _BFSET_(r32,15, 0,v)
#define GET16Vpp_BG_OV_FXD_IMG_REG(r16) _BFGET_(r16,15, 0)
#define SET16Vpp_BG_OV_FXD_IMG_REG(r16,v) _BFSET_(r16,15, 0,v)
#define w32Vpp_BG_OV_FXD_IMG {\
UNSG32 uBG_OV_FXD_IMG_REG : 16;\
UNSG32 RSVDx12CA0_b16 : 16;\
}
union { UNSG32 u32Vpp_BG_OV_FXD_IMG;
struct w32Vpp_BG_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DET_OV_FXD_IMG_REG(r32) _BFGET_(r32, 7, 0)
#define SET32Vpp_DET_OV_FXD_IMG_REG(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16Vpp_DET_OV_FXD_IMG_REG(r16) _BFGET_(r16, 7, 0)
#define SET16Vpp_DET_OV_FXD_IMG_REG(r16,v) _BFSET_(r16, 7, 0,v)
#define w32Vpp_DET_OV_FXD_IMG {\
UNSG32 uDET_OV_FXD_IMG_REG : 8;\
UNSG32 RSVDx12CA4_b8 : 24;\
}
union { UNSG32 u32Vpp_DET_OV_FXD_IMG;
struct w32Vpp_DET_OV_FXD_IMG;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_SENSIO_CTRL0_bypass(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_SENSIO_CTRL0_bypass(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_SENSIO_CTRL0_bypass(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_SENSIO_CTRL0_bypass(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_SENSIO_CTRL0 {\
UNSG32 uSENSIO_CTRL0_bypass : 1;\
UNSG32 RSVDx12CA8_b1 : 31;\
}
union { UNSG32 u32Vpp_SENSIO_CTRL0;
struct w32Vpp_SENSIO_CTRL0;
};
///////////////////////////////////////////////////////////
SIE_SENSIO ie_SENSIO_CTRL;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_BG;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_MAIN;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_PIP;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_PG;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_IG;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_CURSOR;
///////////////////////////////////////////////////////////
SIE_INV_SCAN ie_INV_SCAN_MOSD;
///////////////////////////////////////////////////////////
#define GET32Vpp_DROP_Y_INV_SCAN_EN(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_DROP_Y_INV_SCAN_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_DROP_Y_INV_SCAN_EN(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DROP_Y_INV_SCAN_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_DROP_Y_INV_SCAN_REPEAT_LASTY(r16,v) _BFSET_(r16, 1, 1,v)
#define w32Vpp_DROP_Y_INV_SCAN {\
UNSG32 uDROP_Y_INV_SCAN_EN : 1;\
UNSG32 uDROP_Y_INV_SCAN_REPEAT_LASTY : 1;\
UNSG32 RSVDx12CE4_b2 : 30;\
}
union { UNSG32 u32Vpp_DROP_Y_INV_SCAN;
struct w32Vpp_DROP_Y_INV_SCAN;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_VPP_INTR_EN_vppCPCB0(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_VPP_INTR_EN_vppCPCB0(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_VPP_INTR_EN_vppCPCB0(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_VPP_INTR_EN_vppCPCB0(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32Vpp_VPP_INTR_EN_vppCPCB1(r32) _BFGET_(r32, 1, 1)
#define SET32Vpp_VPP_INTR_EN_vppCPCB1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16Vpp_VPP_INTR_EN_vppCPCB1(r16) _BFGET_(r16, 1, 1)
#define SET16Vpp_VPP_INTR_EN_vppCPCB1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32Vpp_VPP_INTR_EN_vppCPCB2(r32) _BFGET_(r32, 2, 2)
#define SET32Vpp_VPP_INTR_EN_vppCPCB2(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16Vpp_VPP_INTR_EN_vppCPCB2(r16) _BFGET_(r16, 2, 2)
#define SET16Vpp_VPP_INTR_EN_vppCPCB2(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT0(r32) _BFGET_(r32, 3, 3)
#define SET32Vpp_VPP_INTR_EN_vppOUT0(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT0(r16) _BFGET_(r16, 3, 3)
#define SET16Vpp_VPP_INTR_EN_vppOUT0(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT1(r32) _BFGET_(r32, 4, 4)
#define SET32Vpp_VPP_INTR_EN_vppOUT1(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT1(r16) _BFGET_(r16, 4, 4)
#define SET16Vpp_VPP_INTR_EN_vppOUT1(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT2(r32) _BFGET_(r32, 5, 5)
#define SET32Vpp_VPP_INTR_EN_vppOUT2(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT2(r16) _BFGET_(r16, 5, 5)
#define SET16Vpp_VPP_INTR_EN_vppOUT2(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT3(r32) _BFGET_(r32, 6, 6)
#define SET32Vpp_VPP_INTR_EN_vppOUT3(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT3(r16) _BFGET_(r16, 6, 6)
#define SET16Vpp_VPP_INTR_EN_vppOUT3(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT4(r32) _BFGET_(r32, 7, 7)
#define SET32Vpp_VPP_INTR_EN_vppOUT4(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT4(r16) _BFGET_(r16, 7, 7)
#define SET16Vpp_VPP_INTR_EN_vppOUT4(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT5(r32) _BFGET_(r32, 8, 8)
#define SET32Vpp_VPP_INTR_EN_vppOUT5(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT5(r16) _BFGET_(r16, 8, 8)
#define SET16Vpp_VPP_INTR_EN_vppOUT5(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32Vpp_VPP_INTR_EN_vppOUT6(r32) _BFGET_(r32, 9, 9)
#define SET32Vpp_VPP_INTR_EN_vppOUT6(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16Vpp_VPP_INTR_EN_vppOUT6(r16) _BFGET_(r16, 9, 9)
#define SET16Vpp_VPP_INTR_EN_vppOUT6(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32Vpp_VPP_INTR_EN_vppspdifrx(r32) _BFGET_(r32,10,10)
#define SET32Vpp_VPP_INTR_EN_vppspdifrx(r32,v) _BFSET_(r32,10,10,v)
#define GET16Vpp_VPP_INTR_EN_vppspdifrx(r16) _BFGET_(r16,10,10)
#define SET16Vpp_VPP_INTR_EN_vppspdifrx(r16,v) _BFSET_(r16,10,10,v)
#define GET32Vpp_VPP_INTR_EN_vppspdifrx_ch(r32) _BFGET_(r32,11,11)
#define SET32Vpp_VPP_INTR_EN_vppspdifrx_ch(r32,v) _BFSET_(r32,11,11,v)
#define GET16Vpp_VPP_INTR_EN_vppspdifrx_ch(r16) _BFGET_(r16,11,11)
#define SET16Vpp_VPP_INTR_EN_vppspdifrx_ch(r16,v) _BFSET_(r16,11,11,v)
#define GET32Vpp_VPP_INTR_EN_BCM_INVALID(r32) _BFGET_(r32,12,12)
#define SET32Vpp_VPP_INTR_EN_BCM_INVALID(r32,v) _BFSET_(r32,12,12,v)
#define GET16Vpp_VPP_INTR_EN_BCM_INVALID(r16) _BFGET_(r16,12,12)
#define SET16Vpp_VPP_INTR_EN_BCM_INVALID(r16,v) _BFSET_(r16,12,12,v)
#define w32Vpp_VPP_INTR_EN {\
UNSG32 uVPP_INTR_EN_vppCPCB0 : 1;\
UNSG32 uVPP_INTR_EN_vppCPCB1 : 1;\
UNSG32 uVPP_INTR_EN_vppCPCB2 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT0 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT1 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT2 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT3 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT4 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT5 : 1;\
UNSG32 uVPP_INTR_EN_vppOUT6 : 1;\
UNSG32 uVPP_INTR_EN_vppspdifrx : 1;\
UNSG32 uVPP_INTR_EN_vppspdifrx_ch : 1;\
UNSG32 uVPP_INTR_EN_BCM_INVALID : 1;\
UNSG32 RSVDx12CE8_b13 : 19;\
}
union { UNSG32 u32Vpp_VPP_INTR_EN;
struct w32Vpp_VPP_INTR_EN;
};
///////////////////////////////////////////////////////////
#define GET32Vpp_DEINT_FLD_STS_fld(r32) _BFGET_(r32, 0, 0)
#define SET32Vpp_DEINT_FLD_STS_fld(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16Vpp_DEINT_FLD_STS_fld(r16) _BFGET_(r16, 0, 0)
#define SET16Vpp_DEINT_FLD_STS_fld(r16,v) _BFSET_(r16, 0, 0,v)
#define w32Vpp_DEINT_FLD_STS {\
UNSG32 uDEINT_FLD_STS_fld : 1;\
UNSG32 RSVDx12CEC_b1 : 31;\
}
union { UNSG32 u32Vpp_DEINT_FLD_STS;
struct w32Vpp_DEINT_FLD_STS;
};
///////////////////////////////////////////////////////////
SIE_CLKGAT_CTRL ie_CLKGAT_CTRL;
///////////////////////////////////////////////////////////
UNSG8 RSVDx12CF4 [54028];
///////////////////////////////////////////////////////////
} SIE_Vpp;
typedef union T32Vpp_VP_CLKEN_CTRL
{ UNSG32 u32;
struct w32Vpp_VP_CLKEN_CTRL;
} T32Vpp_VP_CLKEN_CTRL;
typedef union T32Vpp_FE_MAIN_CTRL
{ UNSG32 u32;
struct w32Vpp_FE_MAIN_CTRL;
} T32Vpp_FE_MAIN_CTRL;
typedef union T32Vpp_FE_PIP_CTRL
{ UNSG32 u32;
struct w32Vpp_FE_PIP_CTRL;
} T32Vpp_FE_PIP_CTRL;
typedef union T32Vpp_FE_OSD_CTRL
{ UNSG32 u32;
struct w32Vpp_FE_OSD_CTRL;
} T32Vpp_FE_OSD_CTRL;
typedef union T32Vpp_FE_PG_CTRL
{ UNSG32 u32;
struct w32Vpp_FE_PG_CTRL;
} T32Vpp_FE_PG_CTRL;
typedef union T32Vpp_CPCB0_FLD
{ UNSG32 u32;
struct w32Vpp_CPCB0_FLD;
} T32Vpp_CPCB0_FLD;
typedef union T32Vpp_CPCB2_FLD
{ UNSG32 u32;
struct w32Vpp_CPCB2_FLD;
} T32Vpp_CPCB2_FLD;
typedef union T32Vpp_FE_PAT_SEL
{ UNSG32 u32;
struct w32Vpp_FE_PAT_SEL;
} T32Vpp_FE_PAT_SEL;
typedef union T32Vpp_mainW
{ UNSG32 u32;
struct w32Vpp_mainW;
} T32Vpp_mainW;
typedef union T32Vpp_mainR
{ UNSG32 u32;
struct w32Vpp_mainR;
} T32Vpp_mainR;
typedef union T32Vpp_pipW
{ UNSG32 u32;
struct w32Vpp_pipW;
} T32Vpp_pipW;
typedef union T32Vpp_pipR
{ UNSG32 u32;
struct w32Vpp_pipR;
} T32Vpp_pipR;
typedef union T32Vpp_auxW
{ UNSG32 u32;
struct w32Vpp_auxW;
} T32Vpp_auxW;
typedef union T32Vpp_auxR
{ UNSG32 u32;
struct w32Vpp_auxR;
} T32Vpp_auxR;
typedef union T32Vpp_rst
{ UNSG32 u32;
struct w32Vpp_rst;
} T32Vpp_rst;
typedef union T32Vpp_regIfCtrl
{ UNSG32 u32;
struct w32Vpp_regIfCtrl;
} T32Vpp_regIfCtrl;
typedef union T32Vpp_MAIN_LSIZE
{ UNSG32 u32;
struct w32Vpp_MAIN_LSIZE;
} T32Vpp_MAIN_LSIZE;
typedef union T32Vpp_PIP_LSIZE
{ UNSG32 u32;
struct w32Vpp_PIP_LSIZE;
} T32Vpp_PIP_LSIZE;
typedef union T32Vpp_OSD_LSIZE
{ UNSG32 u32;
struct w32Vpp_OSD_LSIZE;
} T32Vpp_OSD_LSIZE;
typedef union T32Vpp_PG_LSIZE
{ UNSG32 u32;
struct w32Vpp_PG_LSIZE;
} T32Vpp_PG_LSIZE;
typedef union T32Vpp_AUX_LSIZE
{ UNSG32 u32;
struct w32Vpp_AUX_LSIZE;
} T32Vpp_AUX_LSIZE;
typedef union T32Vpp_vpIn_pix
{ UNSG32 u32;
struct w32Vpp_vpIn_pix;
} T32Vpp_vpIn_pix;
typedef union T32Vpp_vpOut_pix
{ UNSG32 u32;
struct w32Vpp_vpOut_pix;
} T32Vpp_vpOut_pix;
typedef union T32Vpp_pip_pix
{ UNSG32 u32;
struct w32Vpp_pip_pix;
} T32Vpp_pip_pix;
typedef union T32Vpp_osd_pix
{ UNSG32 u32;
struct w32Vpp_osd_pix;
} T32Vpp_osd_pix;
typedef union T32Vpp_pg_pix
{ UNSG32 u32;
struct w32Vpp_pg_pix;
} T32Vpp_pg_pix;
typedef union T32Vpp_diW_pix
{ UNSG32 u32;
struct w32Vpp_diW_pix;
} T32Vpp_diW_pix;
typedef union T32Vpp_diR_word
{ UNSG32 u32;
struct w32Vpp_diR_word;
} T32Vpp_diR_word;
typedef union T32Vpp_mainW_pix
{ UNSG32 u32;
struct w32Vpp_mainW_pix;
} T32Vpp_mainW_pix;
typedef union T32Vpp_mainR_word
{ UNSG32 u32;
struct w32Vpp_mainR_word;
} T32Vpp_mainR_word;
typedef union T32Vpp_pipW_pix
{ UNSG32 u32;
struct w32Vpp_pipW_pix;
} T32Vpp_pipW_pix;
typedef union T32Vpp_pipR_word
{ UNSG32 u32;
struct w32Vpp_pipR_word;
} T32Vpp_pipR_word;
typedef union T32Vpp_auxW_pix
{ UNSG32 u32;
struct w32Vpp_auxW_pix;
} T32Vpp_auxW_pix;
typedef union T32Vpp_auxR_word
{ UNSG32 u32;
struct w32Vpp_auxR_word;
} T32Vpp_auxR_word;
typedef union T32Vpp_main_ols
{ UNSG32 u32;
struct w32Vpp_main_ols;
} T32Vpp_main_ols;
typedef union T32Vpp_pip_ols
{ UNSG32 u32;
struct w32Vpp_pip_ols;
} T32Vpp_pip_ols;
typedef union T32Vpp_enc_hsvs_sel
{ UNSG32 u32;
struct w32Vpp_enc_hsvs_sel;
} T32Vpp_enc_hsvs_sel;
typedef union T32Vpp_CPCB_FIFO_UF
{ UNSG32 u32;
struct w32Vpp_CPCB_FIFO_UF;
} T32Vpp_CPCB_FIFO_UF;
typedef union T32Vpp_HDMI2DVAO
{ UNSG32 u32;
struct w32Vpp_HDMI2DVAO;
} T32Vpp_HDMI2DVAO;
typedef union T32Vpp_VP_DMX_CTRL
{ UNSG32 u32;
struct w32Vpp_VP_DMX_CTRL;
} T32Vpp_VP_DMX_CTRL;
typedef union T32Vpp_VP_DMX_HRES
{ UNSG32 u32;
struct w32Vpp_VP_DMX_HRES;
} T32Vpp_VP_DMX_HRES;
typedef union T32Vpp_VP_DMX_HT
{ UNSG32 u32;
struct w32Vpp_VP_DMX_HT;
} T32Vpp_VP_DMX_HT;
typedef union T32Vpp_VP_DMX_VRES
{ UNSG32 u32;
struct w32Vpp_VP_DMX_VRES;
} T32Vpp_VP_DMX_VRES;
typedef union T32Vpp_VP_DMX_VT
{ UNSG32 u32;
struct w32Vpp_VP_DMX_VT;
} T32Vpp_VP_DMX_VT;
typedef union T32Vpp_VP_DMX_IVT
{ UNSG32 u32;
struct w32Vpp_VP_DMX_IVT;
} T32Vpp_VP_DMX_IVT;
typedef union T32Vpp_CPCB0_PL_EN
{ UNSG32 u32;
struct w32Vpp_CPCB0_PL_EN;
} T32Vpp_CPCB0_PL_EN;
typedef union T32Vpp_CPCB1_PL_EN
{ UNSG32 u32;
struct w32Vpp_CPCB1_PL_EN;
} T32Vpp_CPCB1_PL_EN;
typedef union T32Vpp_MAIN_WCLIENT
{ UNSG32 u32;
struct w32Vpp_MAIN_WCLIENT;
} T32Vpp_MAIN_WCLIENT;
typedef union T32Vpp_PIP_WCLIENT
{ UNSG32 u32;
struct w32Vpp_PIP_WCLIENT;
} T32Vpp_PIP_WCLIENT;
typedef union T32Vpp_DIW_CLIENT
{ UNSG32 u32;
struct w32Vpp_DIW_CLIENT;
} T32Vpp_DIW_CLIENT;
typedef union T32Vpp_DIR0_CLIENT
{ UNSG32 u32;
struct w32Vpp_DIR0_CLIENT;
} T32Vpp_DIR0_CLIENT;
typedef union T32Vpp_DIR1_CLIENT
{ UNSG32 u32;
struct w32Vpp_DIR1_CLIENT;
} T32Vpp_DIR1_CLIENT;
typedef union T32Vpp_SD_TT_CLIENT
{ UNSG32 u32;
struct w32Vpp_SD_TT_CLIENT;
} T32Vpp_SD_TT_CLIENT;
typedef union T32Vpp_SD_TT_BYTE
{ UNSG32 u32;
struct w32Vpp_SD_TT_BYTE;
} T32Vpp_SD_TT_BYTE;
typedef union T32Vpp_DAC_RAMP_CTRL
{ UNSG32 u32;
struct w32Vpp_DAC_RAMP_CTRL;
} T32Vpp_DAC_RAMP_CTRL;
typedef union T32Vpp_DAC_TEST_CTRL
{ UNSG32 u32;
struct w32Vpp_DAC_TEST_CTRL;
} T32Vpp_DAC_TEST_CTRL;
typedef union T32Vpp_SCL_CLKEN_CTRL
{ UNSG32 u32;
struct w32Vpp_SCL_CLKEN_CTRL;
} T32Vpp_SCL_CLKEN_CTRL;
typedef union T32Vpp_PAT_DNS_CTRL
{ UNSG32 u32;
struct w32Vpp_PAT_DNS_CTRL;
} T32Vpp_PAT_DNS_CTRL;
typedef union T32Vpp_CPCB0_FLD_STS
{ UNSG32 u32;
struct w32Vpp_CPCB0_FLD_STS;
} T32Vpp_CPCB0_FLD_STS;
typedef union T32Vpp_CPCB2_FLD_STS
{ UNSG32 u32;
struct w32Vpp_CPCB2_FLD_STS;
} T32Vpp_CPCB2_FLD_STS;
typedef union T32Vpp_SD_TT_TEST
{ UNSG32 u32;
struct w32Vpp_SD_TT_TEST;
} T32Vpp_SD_TT_TEST;
typedef union T32Vpp_DUMMY0
{ UNSG32 u32;
struct w32Vpp_DUMMY0;
} T32Vpp_DUMMY0;
typedef union T32Vpp_DEBUG0
{ UNSG32 u32;
struct w32Vpp_DEBUG0;
} T32Vpp_DEBUG0;
typedef union T32Vpp_MAIN_SCL_CROP
{ UNSG32 u32;
struct w32Vpp_MAIN_SCL_CROP;
} T32Vpp_MAIN_SCL_CROP;
typedef union T32Vpp_PIP_SCL_CROP
{ UNSG32 u32;
struct w32Vpp_PIP_SCL_CROP;
} T32Vpp_PIP_SCL_CROP;
typedef union T32Vpp_PIP_LUMA_KEY
{ UNSG32 u32;
struct w32Vpp_PIP_LUMA_KEY;
} T32Vpp_PIP_LUMA_KEY;
typedef union T32Vpp_PIP_AL_IN
{ UNSG32 u32;
struct w32Vpp_PIP_AL_IN;
} T32Vpp_PIP_AL_IN;
typedef union T32Vpp_PIP_AL_OUT
{ UNSG32 u32;
struct w32Vpp_PIP_AL_OUT;
} T32Vpp_PIP_AL_OUT;
typedef union T32Vpp_mosd_pix
{ UNSG32 u32;
struct w32Vpp_mosd_pix;
} T32Vpp_mosd_pix;
typedef union T32Vpp_MOSD_LSIZE
{ UNSG32 u32;
struct w32Vpp_MOSD_LSIZE;
} T32Vpp_MOSD_LSIZE;
typedef union T32Vpp_FE_MOSD_CTRL
{ UNSG32 u32;
struct w32Vpp_FE_MOSD_CTRL;
} T32Vpp_FE_MOSD_CTRL;
typedef union T32Vpp_OVERLAY_MUX
{ UNSG32 u32;
struct w32Vpp_OVERLAY_MUX;
} T32Vpp_OVERLAY_MUX;
typedef union T32Vpp_MAIN_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_MAIN_OV_FXD_IMG;
} T32Vpp_MAIN_OV_FXD_IMG;
typedef union T32Vpp_PIP_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_PIP_OV_FXD_IMG;
} T32Vpp_PIP_OV_FXD_IMG;
typedef union T32Vpp_IG_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_IG_OV_FXD_IMG;
} T32Vpp_IG_OV_FXD_IMG;
typedef union T32Vpp_PG_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_PG_OV_FXD_IMG;
} T32Vpp_PG_OV_FXD_IMG;
typedef union T32Vpp_CURSOR_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_CURSOR_OV_FXD_IMG;
} T32Vpp_CURSOR_OV_FXD_IMG;
typedef union T32Vpp_MOSD_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_MOSD_OV_FXD_IMG;
} T32Vpp_MOSD_OV_FXD_IMG;
typedef union T32Vpp_BG_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_BG_OV_FXD_IMG;
} T32Vpp_BG_OV_FXD_IMG;
typedef union T32Vpp_DET_OV_FXD_IMG
{ UNSG32 u32;
struct w32Vpp_DET_OV_FXD_IMG;
} T32Vpp_DET_OV_FXD_IMG;
typedef union T32Vpp_SENSIO_CTRL0
{ UNSG32 u32;
struct w32Vpp_SENSIO_CTRL0;
} T32Vpp_SENSIO_CTRL0;
typedef union T32Vpp_DROP_Y_INV_SCAN
{ UNSG32 u32;
struct w32Vpp_DROP_Y_INV_SCAN;
} T32Vpp_DROP_Y_INV_SCAN;
typedef union T32Vpp_VPP_INTR_EN
{ UNSG32 u32;
struct w32Vpp_VPP_INTR_EN;
} T32Vpp_VPP_INTR_EN;
typedef union T32Vpp_DEINT_FLD_STS
{ UNSG32 u32;
struct w32Vpp_DEINT_FLD_STS;
} T32Vpp_DEINT_FLD_STS;
///////////////////////////////////////////////////////////
typedef union TVpp_VP_CLKEN_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_CLKEN_CTRL;
};
} TVpp_VP_CLKEN_CTRL;
typedef union TVpp_FE_MAIN_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_MAIN_CTRL;
};
} TVpp_FE_MAIN_CTRL;
typedef union TVpp_FE_PIP_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_PIP_CTRL;
};
} TVpp_FE_PIP_CTRL;
typedef union TVpp_FE_OSD_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_OSD_CTRL;
};
} TVpp_FE_OSD_CTRL;
typedef union TVpp_FE_PG_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_PG_CTRL;
};
} TVpp_FE_PG_CTRL;
typedef union TVpp_CPCB0_FLD
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB0_FLD;
};
} TVpp_CPCB0_FLD;
typedef union TVpp_CPCB2_FLD
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB2_FLD;
};
} TVpp_CPCB2_FLD;
typedef union TVpp_FE_PAT_SEL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_PAT_SEL;
};
} TVpp_FE_PAT_SEL;
typedef union TVpp_mainW
{ UNSG32 u32[1];
struct {
struct w32Vpp_mainW;
};
} TVpp_mainW;
typedef union TVpp_mainR
{ UNSG32 u32[1];
struct {
struct w32Vpp_mainR;
};
} TVpp_mainR;
typedef union TVpp_pipW
{ UNSG32 u32[1];
struct {
struct w32Vpp_pipW;
};
} TVpp_pipW;
typedef union TVpp_pipR
{ UNSG32 u32[1];
struct {
struct w32Vpp_pipR;
};
} TVpp_pipR;
typedef union TVpp_auxW
{ UNSG32 u32[1];
struct {
struct w32Vpp_auxW;
};
} TVpp_auxW;
typedef union TVpp_auxR
{ UNSG32 u32[1];
struct {
struct w32Vpp_auxR;
};
} TVpp_auxR;
typedef union TVpp_rst
{ UNSG32 u32[1];
struct {
struct w32Vpp_rst;
};
} TVpp_rst;
typedef union TVpp_regIfCtrl
{ UNSG32 u32[1];
struct {
struct w32Vpp_regIfCtrl;
};
} TVpp_regIfCtrl;
typedef union TVpp_MAIN_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_MAIN_LSIZE;
};
} TVpp_MAIN_LSIZE;
typedef union TVpp_PIP_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_LSIZE;
};
} TVpp_PIP_LSIZE;
typedef union TVpp_OSD_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_OSD_LSIZE;
};
} TVpp_OSD_LSIZE;
typedef union TVpp_PG_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_PG_LSIZE;
};
} TVpp_PG_LSIZE;
typedef union TVpp_AUX_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_AUX_LSIZE;
};
} TVpp_AUX_LSIZE;
typedef union TVpp_vpIn_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_vpIn_pix;
};
} TVpp_vpIn_pix;
typedef union TVpp_vpOut_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_vpOut_pix;
};
} TVpp_vpOut_pix;
typedef union TVpp_pip_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_pip_pix;
};
} TVpp_pip_pix;
typedef union TVpp_osd_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_osd_pix;
};
} TVpp_osd_pix;
typedef union TVpp_pg_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_pg_pix;
};
} TVpp_pg_pix;
typedef union TVpp_diW_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_diW_pix;
};
} TVpp_diW_pix;
typedef union TVpp_diR_word
{ UNSG32 u32[1];
struct {
struct w32Vpp_diR_word;
};
} TVpp_diR_word;
typedef union TVpp_mainW_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_mainW_pix;
};
} TVpp_mainW_pix;
typedef union TVpp_mainR_word
{ UNSG32 u32[1];
struct {
struct w32Vpp_mainR_word;
};
} TVpp_mainR_word;
typedef union TVpp_pipW_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_pipW_pix;
};
} TVpp_pipW_pix;
typedef union TVpp_pipR_word
{ UNSG32 u32[1];
struct {
struct w32Vpp_pipR_word;
};
} TVpp_pipR_word;
typedef union TVpp_auxW_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_auxW_pix;
};
} TVpp_auxW_pix;
typedef union TVpp_auxR_word
{ UNSG32 u32[1];
struct {
struct w32Vpp_auxR_word;
};
} TVpp_auxR_word;
typedef union TVpp_main_ols
{ UNSG32 u32[1];
struct {
struct w32Vpp_main_ols;
};
} TVpp_main_ols;
typedef union TVpp_pip_ols
{ UNSG32 u32[1];
struct {
struct w32Vpp_pip_ols;
};
} TVpp_pip_ols;
typedef union TVpp_enc_hsvs_sel
{ UNSG32 u32[1];
struct {
struct w32Vpp_enc_hsvs_sel;
};
} TVpp_enc_hsvs_sel;
typedef union TVpp_CPCB_FIFO_UF
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB_FIFO_UF;
};
} TVpp_CPCB_FIFO_UF;
typedef union TVpp_HDMI2DVAO
{ UNSG32 u32[1];
struct {
struct w32Vpp_HDMI2DVAO;
};
} TVpp_HDMI2DVAO;
typedef union TVpp_VP_DMX_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_CTRL;
};
} TVpp_VP_DMX_CTRL;
typedef union TVpp_VP_DMX_HRES
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_HRES;
};
} TVpp_VP_DMX_HRES;
typedef union TVpp_VP_DMX_HT
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_HT;
};
} TVpp_VP_DMX_HT;
typedef union TVpp_VP_DMX_VRES
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_VRES;
};
} TVpp_VP_DMX_VRES;
typedef union TVpp_VP_DMX_VT
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_VT;
};
} TVpp_VP_DMX_VT;
typedef union TVpp_VP_DMX_IVT
{ UNSG32 u32[1];
struct {
struct w32Vpp_VP_DMX_IVT;
};
} TVpp_VP_DMX_IVT;
typedef union TVpp_CPCB0_PL_EN
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB0_PL_EN;
};
} TVpp_CPCB0_PL_EN;
typedef union TVpp_CPCB1_PL_EN
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB1_PL_EN;
};
} TVpp_CPCB1_PL_EN;
typedef union TVpp_MAIN_WCLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_MAIN_WCLIENT;
};
} TVpp_MAIN_WCLIENT;
typedef union TVpp_PIP_WCLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_WCLIENT;
};
} TVpp_PIP_WCLIENT;
typedef union TVpp_DIW_CLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_DIW_CLIENT;
};
} TVpp_DIW_CLIENT;
typedef union TVpp_DIR0_CLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_DIR0_CLIENT;
};
} TVpp_DIR0_CLIENT;
typedef union TVpp_DIR1_CLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_DIR1_CLIENT;
};
} TVpp_DIR1_CLIENT;
typedef union TVpp_SD_TT_CLIENT
{ UNSG32 u32[1];
struct {
struct w32Vpp_SD_TT_CLIENT;
};
} TVpp_SD_TT_CLIENT;
typedef union TVpp_SD_TT_BYTE
{ UNSG32 u32[1];
struct {
struct w32Vpp_SD_TT_BYTE;
};
} TVpp_SD_TT_BYTE;
typedef union TVpp_DAC_RAMP_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_DAC_RAMP_CTRL;
};
} TVpp_DAC_RAMP_CTRL;
typedef union TVpp_DAC_TEST_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_DAC_TEST_CTRL;
};
} TVpp_DAC_TEST_CTRL;
typedef union TVpp_SCL_CLKEN_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_SCL_CLKEN_CTRL;
};
} TVpp_SCL_CLKEN_CTRL;
typedef union TVpp_PAT_DNS_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_PAT_DNS_CTRL;
};
} TVpp_PAT_DNS_CTRL;
typedef union TVpp_CPCB0_FLD_STS
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB0_FLD_STS;
};
} TVpp_CPCB0_FLD_STS;
typedef union TVpp_CPCB2_FLD_STS
{ UNSG32 u32[1];
struct {
struct w32Vpp_CPCB2_FLD_STS;
};
} TVpp_CPCB2_FLD_STS;
typedef union TVpp_SD_TT_TEST
{ UNSG32 u32[1];
struct {
struct w32Vpp_SD_TT_TEST;
};
} TVpp_SD_TT_TEST;
typedef union TVpp_DUMMY0
{ UNSG32 u32[1];
struct {
struct w32Vpp_DUMMY0;
};
} TVpp_DUMMY0;
typedef union TVpp_DEBUG0
{ UNSG32 u32[1];
struct {
struct w32Vpp_DEBUG0;
};
} TVpp_DEBUG0;
typedef union TVpp_MAIN_SCL_CROP
{ UNSG32 u32[1];
struct {
struct w32Vpp_MAIN_SCL_CROP;
};
} TVpp_MAIN_SCL_CROP;
typedef union TVpp_PIP_SCL_CROP
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_SCL_CROP;
};
} TVpp_PIP_SCL_CROP;
typedef union TVpp_PIP_LUMA_KEY
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_LUMA_KEY;
};
} TVpp_PIP_LUMA_KEY;
typedef union TVpp_PIP_AL_IN
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_AL_IN;
};
} TVpp_PIP_AL_IN;
typedef union TVpp_PIP_AL_OUT
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_AL_OUT;
};
} TVpp_PIP_AL_OUT;
typedef union TVpp_mosd_pix
{ UNSG32 u32[1];
struct {
struct w32Vpp_mosd_pix;
};
} TVpp_mosd_pix;
typedef union TVpp_MOSD_LSIZE
{ UNSG32 u32[1];
struct {
struct w32Vpp_MOSD_LSIZE;
};
} TVpp_MOSD_LSIZE;
typedef union TVpp_FE_MOSD_CTRL
{ UNSG32 u32[1];
struct {
struct w32Vpp_FE_MOSD_CTRL;
};
} TVpp_FE_MOSD_CTRL;
typedef union TVpp_OVERLAY_MUX
{ UNSG32 u32[1];
struct {
struct w32Vpp_OVERLAY_MUX;
};
} TVpp_OVERLAY_MUX;
typedef union TVpp_MAIN_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_MAIN_OV_FXD_IMG;
};
} TVpp_MAIN_OV_FXD_IMG;
typedef union TVpp_PIP_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_PIP_OV_FXD_IMG;
};
} TVpp_PIP_OV_FXD_IMG;
typedef union TVpp_IG_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_IG_OV_FXD_IMG;
};
} TVpp_IG_OV_FXD_IMG;
typedef union TVpp_PG_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_PG_OV_FXD_IMG;
};
} TVpp_PG_OV_FXD_IMG;
typedef union TVpp_CURSOR_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_CURSOR_OV_FXD_IMG;
};
} TVpp_CURSOR_OV_FXD_IMG;
typedef union TVpp_MOSD_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_MOSD_OV_FXD_IMG;
};
} TVpp_MOSD_OV_FXD_IMG;
typedef union TVpp_BG_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_BG_OV_FXD_IMG;
};
} TVpp_BG_OV_FXD_IMG;
typedef union TVpp_DET_OV_FXD_IMG
{ UNSG32 u32[1];
struct {
struct w32Vpp_DET_OV_FXD_IMG;
};
} TVpp_DET_OV_FXD_IMG;
typedef union TVpp_SENSIO_CTRL0
{ UNSG32 u32[1];
struct {
struct w32Vpp_SENSIO_CTRL0;
};
} TVpp_SENSIO_CTRL0;
typedef union TVpp_DROP_Y_INV_SCAN
{ UNSG32 u32[1];
struct {
struct w32Vpp_DROP_Y_INV_SCAN;
};
} TVpp_DROP_Y_INV_SCAN;
typedef union TVpp_VPP_INTR_EN
{ UNSG32 u32[1];
struct {
struct w32Vpp_VPP_INTR_EN;
};
} TVpp_VPP_INTR_EN;
typedef union TVpp_DEINT_FLD_STS
{ UNSG32 u32[1];
struct {
struct w32Vpp_DEINT_FLD_STS;
};
} TVpp_DEINT_FLD_STS;
///////////////////////////////////////////////////////////
SIGN32 Vpp_drvrd(SIE_Vpp *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 Vpp_drvwr(SIE_Vpp *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void Vpp_reset(SIE_Vpp *p);
SIGN32 Vpp_cmp (SIE_Vpp *p, SIE_Vpp *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define Vpp_check(p,pie,pfx,hLOG) Vpp_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define Vpp_print(p, pfx,hLOG) Vpp_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: Vpp
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: vpp.h
////////////////////////////////////////////////////////////